hm_svm.h@ 70000

Last change on this file since 70000 was 70000, checked in by vboxsync, 7 years ago
VMM: Nested Hw.virt: Make SVM intercept functions smarter. Avoids swapping of modified VMCB state in a lot of tricky to detect situations and makes it a lot cleaner that the VMCB is only finally restored before the #VMEXIT is done.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 43.2 KB

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1	/** @file
2	* HM - SVM (AMD-V) Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_svm_h
27	#define ___VBox_vmm_svm_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33
34	#ifdef RT_OS_SOLARIS
35	# undef ES
36	# undef CS
37	# undef DS
38	# undef SS
39	# undef FS
40	# undef GS
41	#endif
42
43	/** @defgroup grp_hm_svm SVM (AMD-V) Types and Definitions
44	* @ingroup grp_hm
45	* @{
46	*/
47
48	/** @name SVM generic / convenient defines.
49	* @{
50	*/
51	/** Number of pages required for the VMCB. */
52	#define SVM_VMCB_PAGES 1
53	/** Number of pages required for the MSR permission bitmap. */
54	#define SVM_MSRPM_PAGES 2
55	/** Number of pages required for the IO permission bitmap. */
56	#define SVM_IOPM_PAGES 3
57	/** @} */
58
59	/*
60	* Ugly!
61	* When compiling the recompiler, its own svm.h defines clash with
62	* the following defines. Avoid just the duplicates here as we still
63	* require other definitions and structures in this header.
64	*/
65	#ifndef IN_REM_R3
66	/** @name SVM_EXIT_XXX - SVM Basic Exit Reasons.
67	* @{
68	*/
69	/** Invalid guest state in VMCB. */
70	# define SVM_EXIT_INVALID (uint64_t)(-1)
71	/** Read from CR0-CR15. */
72	# define SVM_EXIT_READ_CR0 0x0
73	# define SVM_EXIT_READ_CR1 0x1
74	# define SVM_EXIT_READ_CR2 0x2
75	# define SVM_EXIT_READ_CR3 0x3
76	# define SVM_EXIT_READ_CR4 0x4
77	# define SVM_EXIT_READ_CR5 0x5
78	# define SVM_EXIT_READ_CR6 0x6
79	# define SVM_EXIT_READ_CR7 0x7
80	# define SVM_EXIT_READ_CR8 0x8
81	# define SVM_EXIT_READ_CR9 0x9
82	# define SVM_EXIT_READ_CR10 0xA
83	# define SVM_EXIT_READ_CR11 0xB
84	# define SVM_EXIT_READ_CR12 0xC
85	# define SVM_EXIT_READ_CR13 0xD
86	# define SVM_EXIT_READ_CR14 0xE
87	# define SVM_EXIT_READ_CR15 0xF
88	/** Writes to CR0-CR15. */
89	# define SVM_EXIT_WRITE_CR0 0x10
90	# define SVM_EXIT_WRITE_CR1 0x11
91	# define SVM_EXIT_WRITE_CR2 0x12
92	# define SVM_EXIT_WRITE_CR3 0x13
93	# define SVM_EXIT_WRITE_CR4 0x14
94	# define SVM_EXIT_WRITE_CR5 0x15
95	# define SVM_EXIT_WRITE_CR6 0x16
96	# define SVM_EXIT_WRITE_CR7 0x17
97	# define SVM_EXIT_WRITE_CR8 0x18
98	# define SVM_EXIT_WRITE_CR9 0x19
99	# define SVM_EXIT_WRITE_CR10 0x1A
100	# define SVM_EXIT_WRITE_CR11 0x1B
101	# define SVM_EXIT_WRITE_CR12 0x1C
102	# define SVM_EXIT_WRITE_CR13 0x1D
103	# define SVM_EXIT_WRITE_CR14 0x1E
104	# define SVM_EXIT_WRITE_CR15 0x1F
105	/** Read from DR0-DR15. */
106	# define SVM_EXIT_READ_DR0 0x20
107	# define SVM_EXIT_READ_DR1 0x21
108	# define SVM_EXIT_READ_DR2 0x22
109	# define SVM_EXIT_READ_DR3 0x23
110	# define SVM_EXIT_READ_DR4 0x24
111	# define SVM_EXIT_READ_DR5 0x25
112	# define SVM_EXIT_READ_DR6 0x26
113	# define SVM_EXIT_READ_DR7 0x27
114	# define SVM_EXIT_READ_DR8 0x28
115	# define SVM_EXIT_READ_DR9 0x29
116	# define SVM_EXIT_READ_DR10 0x2A
117	# define SVM_EXIT_READ_DR11 0x2B
118	# define SVM_EXIT_READ_DR12 0x2C
119	# define SVM_EXIT_READ_DR13 0x2D
120	# define SVM_EXIT_READ_DR14 0x2E
121	# define SVM_EXIT_READ_DR15 0x2F
122	/** Writes to DR0-DR15. */
123	# define SVM_EXIT_WRITE_DR0 0x30
124	# define SVM_EXIT_WRITE_DR1 0x31
125	# define SVM_EXIT_WRITE_DR2 0x32
126	# define SVM_EXIT_WRITE_DR3 0x33
127	# define SVM_EXIT_WRITE_DR4 0x34
128	# define SVM_EXIT_WRITE_DR5 0x35
129	# define SVM_EXIT_WRITE_DR6 0x36
130	# define SVM_EXIT_WRITE_DR7 0x37
131	# define SVM_EXIT_WRITE_DR8 0x38
132	# define SVM_EXIT_WRITE_DR9 0x39
133	# define SVM_EXIT_WRITE_DR10 0x3A
134	# define SVM_EXIT_WRITE_DR11 0x3B
135	# define SVM_EXIT_WRITE_DR12 0x3C
136	# define SVM_EXIT_WRITE_DR13 0x3D
137	# define SVM_EXIT_WRITE_DR14 0x3E
138	# define SVM_EXIT_WRITE_DR15 0x3F
139	/* Exception 0-31. */
140	# define SVM_EXIT_EXCEPTION_0 0x40
141	# define SVM_EXIT_EXCEPTION_1 0x41
142	# define SVM_EXIT_EXCEPTION_2 0x42
143	# define SVM_EXIT_EXCEPTION_3 0x43
144	# define SVM_EXIT_EXCEPTION_4 0x44
145	# define SVM_EXIT_EXCEPTION_5 0x45
146	# define SVM_EXIT_EXCEPTION_6 0x46
147	# define SVM_EXIT_EXCEPTION_7 0x47
148	# define SVM_EXIT_EXCEPTION_8 0x48
149	# define SVM_EXIT_EXCEPTION_9 0x49
150	# define SVM_EXIT_EXCEPTION_10 0x4A
151	# define SVM_EXIT_EXCEPTION_11 0x4B
152	# define SVM_EXIT_EXCEPTION_12 0x4C
153	# define SVM_EXIT_EXCEPTION_13 0x4D
154	# define SVM_EXIT_EXCEPTION_14 0x4E
155	# define SVM_EXIT_EXCEPTION_15 0x4F
156	# define SVM_EXIT_EXCEPTION_16 0x50
157	# define SVM_EXIT_EXCEPTION_17 0x51
158	# define SVM_EXIT_EXCEPTION_18 0x52
159	# define SVM_EXIT_EXCEPTION_19 0x53
160	# define SVM_EXIT_EXCEPTION_20 0x54
161	# define SVM_EXIT_EXCEPTION_21 0x55
162	# define SVM_EXIT_EXCEPTION_22 0x56
163	# define SVM_EXIT_EXCEPTION_23 0x57
164	# define SVM_EXIT_EXCEPTION_24 0x58
165	# define SVM_EXIT_EXCEPTION_25 0x59
166	# define SVM_EXIT_EXCEPTION_26 0x5A
167	# define SVM_EXIT_EXCEPTION_27 0x5B
168	# define SVM_EXIT_EXCEPTION_28 0x5C
169	# define SVM_EXIT_EXCEPTION_29 0x5D
170	# define SVM_EXIT_EXCEPTION_30 0x5E
171	# define SVM_EXIT_EXCEPTION_31 0x5F
172	/** Physical maskable interrupt. */
173	# define SVM_EXIT_INTR 0x60
174	/** Non-maskable interrupt. */
175	# define SVM_EXIT_NMI 0x61
176	/** System Management interrupt. */
177	# define SVM_EXIT_SMI 0x62
178	/** Physical INIT signal. */
179	# define SVM_EXIT_INIT 0x63
180	/** Virtual interrupt. */
181	# define SVM_EXIT_VINTR 0x64
182	/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
183	# define SVM_EXIT_CR0_SEL_WRITE 0x65
184	/** IDTR read. */
185	# define SVM_EXIT_IDTR_READ 0x66
186	/** GDTR read. */
187	# define SVM_EXIT_GDTR_READ 0x67
188	/** LDTR read. */
189	# define SVM_EXIT_LDTR_READ 0x68
190	/** TR read. */
191	# define SVM_EXIT_TR_READ 0x69
192	/** IDTR write. */
193	# define SVM_EXIT_IDTR_WRITE 0x6A
194	/** GDTR write. */
195	# define SVM_EXIT_GDTR_WRITE 0x6B
196	/** LDTR write. */
197	# define SVM_EXIT_LDTR_WRITE 0x6C
198	/** TR write. */
199	# define SVM_EXIT_TR_WRITE 0x6D
200	/** RDTSC instruction. */
201	# define SVM_EXIT_RDTSC 0x6E
202	/** RDPMC instruction. */
203	# define SVM_EXIT_RDPMC 0x6F
204	/** PUSHF instruction. */
205	# define SVM_EXIT_PUSHF 0x70
206	/** POPF instruction. */
207	# define SVM_EXIT_POPF 0x71
208	/** CPUID instruction. */
209	# define SVM_EXIT_CPUID 0x72
210	/** RSM instruction. */
211	# define SVM_EXIT_RSM 0x73
212	/** IRET instruction. */
213	# define SVM_EXIT_IRET 0x74
214	/** software interrupt (INTn instructions). */
215	# define SVM_EXIT_SWINT 0x75
216	/** INVD instruction. */
217	# define SVM_EXIT_INVD 0x76
218	/** PAUSE instruction. */
219	# define SVM_EXIT_PAUSE 0x77
220	/** HLT instruction. */
221	# define SVM_EXIT_HLT 0x78
222	/** INVLPG instructions. */
223	# define SVM_EXIT_INVLPG 0x79
224	/** INVLPGA instruction. */
225	# define SVM_EXIT_INVLPGA 0x7A
226	/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
227	# define SVM_EXIT_IOIO 0x7B
228	/** RDMSR or WRMSR access to protected MSR. */
229	# define SVM_EXIT_MSR 0x7C
230	/** task switch. */
231	# define SVM_EXIT_TASK_SWITCH 0x7D
232	/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
233	# define SVM_EXIT_FERR_FREEZE 0x7E
234	/** Shutdown. */
235	# define SVM_EXIT_SHUTDOWN 0x7F
236	/** VMRUN instruction. */
237	# define SVM_EXIT_VMRUN 0x80
238	/** VMMCALL instruction. */
239	# define SVM_EXIT_VMMCALL 0x81
240	/** VMLOAD instruction. */
241	# define SVM_EXIT_VMLOAD 0x82
242	/** VMSAVE instruction. */
243	# define SVM_EXIT_VMSAVE 0x83
244	/** STGI instruction. */
245	# define SVM_EXIT_STGI 0x84
246	/** CLGI instruction. */
247	# define SVM_EXIT_CLGI 0x85
248	/** SKINIT instruction. */
249	# define SVM_EXIT_SKINIT 0x86
250	/** RDTSCP instruction. */
251	# define SVM_EXIT_RDTSCP 0x87
252	/** ICEBP instruction. */
253	# define SVM_EXIT_ICEBP 0x88
254	/** WBINVD instruction. */
255	# define SVM_EXIT_WBINVD 0x89
256	/** MONITOR instruction. */
257	# define SVM_EXIT_MONITOR 0x8A
258	/** MWAIT instruction. */
259	# define SVM_EXIT_MWAIT 0x8B
260	/** MWAIT instruction, when armed. */
261	# define SVM_EXIT_MWAIT_ARMED 0x8C
262	/** XSETBV instruction. */
263	# define SVM_EXIT_XSETBV 0x8D
264	/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
265	# define SVM_EXIT_NPF 0x400
266	/** AVIC: Virtual IPI delivery not completed. */
267	# define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
268	/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
269	* hardware. */
270	# define SVM_EXIT_AVIC_NOACCEL 0x402
271	/** The maximum possible exit value. */
272	# define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
273	/** @} */
274	#endif /* !IN_REM_R3*/
275
276
277	/** @name SVMVMCB.u64ExitInfo2 for task switches
278	* @{
279	*/
280	/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
281	#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
282	/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
283	#define SVM_EXIT2_TASK_SWITCH_JMP RT_BIT_64(38)
284	/** Set to 1 if the task switch has an error code; else cleared to 0. */
285	#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
286	/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
287	#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
288	/** @} */
289
290	/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
291	* @{
292	*/
293	/** The access was a read MSR. */
294	#define SVM_EXIT1_MSR_READ 0x0
295	/** The access was a write MSR. */
296	#define SVM_EXIT1_MSR_WRITE 0x1
297	/** @} */
298
299	/** @name SVMVMCB.u64ExitInfo1 for Mov CRx accesses.
300	* @{
301	*/
302	/** The mask of whether the access was via a Mov CRx instruction. */
303	#define SVM_EXIT1_MOV_CRX_MASK RT_BIT_64(63)
304	/** The mask for the GPR number of the Mov CRx instruction. */
305	#define SVM_EXIT1_MOV_CRX_GPR_NUMBER 0xf
306	/** @} */
307
308	/** @name SVMVMCB.u64ExitInfo1 for Mov DRx accesses.
309	* @{
310	*/
311	/** The mask for the GPR number of the Mov DRx instruction. */
312	#define SVM_EXIT1_MOV_DRX_GPR_NUMBER 0xf
313	/** @} */
314
315	/** @name SVMVMCB.ctrl.u64InterceptCtrl
316	* @{
317	*/
318	/** Intercept INTR (physical maskable interrupt). */
319	#define SVM_CTRL_INTERCEPT_INTR RT_BIT_64(0)
320	/** Intercept NMI. */
321	#define SVM_CTRL_INTERCEPT_NMI RT_BIT_64(1)
322	/** Intercept SMI. */
323	#define SVM_CTRL_INTERCEPT_SMI RT_BIT_64(2)
324	/** Intercept INIT. */
325	#define SVM_CTRL_INTERCEPT_INIT RT_BIT_64(3)
326	/** Intercept VINTR (virtual maskable interrupt). */
327	#define SVM_CTRL_INTERCEPT_VINTR RT_BIT_64(4)
328	/** Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
329	#define SVM_CTRL_INTERCEPT_CR0_SEL_WRITES RT_BIT_64(5)
330	/** Intercept reads of IDTR. */
331	#define SVM_CTRL_INTERCEPT_IDTR_READS RT_BIT_64(6)
332	/** Intercept reads of GDTR. */
333	#define SVM_CTRL_INTERCEPT_GDTR_READS RT_BIT_64(7)
334	/** Intercept reads of LDTR. */
335	#define SVM_CTRL_INTERCEPT_LDTR_READS RT_BIT_64(8)
336	/** Intercept reads of TR. */
337	#define SVM_CTRL_INTERCEPT_TR_READS RT_BIT_64(9)
338	/** Intercept writes of IDTR. */
339	#define SVM_CTRL_INTERCEPT_IDTR_WRITES RT_BIT_64(10)
340	/** Intercept writes of GDTR. */
341	#define SVM_CTRL_INTERCEPT_GDTR_WRITES RT_BIT_64(11)
342	/** Intercept writes of LDTR. */
343	#define SVM_CTRL_INTERCEPT_LDTR_WRITES RT_BIT_64(12)
344	/** Intercept writes of TR. */
345	#define SVM_CTRL_INTERCEPT_TR_WRITES RT_BIT_64(13)
346	/** Intercept RDTSC instruction. */
347	#define SVM_CTRL_INTERCEPT_RDTSC RT_BIT_64(14)
348	/** Intercept RDPMC instruction. */
349	#define SVM_CTRL_INTERCEPT_RDPMC RT_BIT_64(15)
350	/** Intercept PUSHF instruction. */
351	#define SVM_CTRL_INTERCEPT_PUSHF RT_BIT_64(16)
352	/** Intercept POPF instruction. */
353	#define SVM_CTRL_INTERCEPT_POPF RT_BIT_64(17)
354	/** Intercept CPUID instruction. */
355	#define SVM_CTRL_INTERCEPT_CPUID RT_BIT_64(18)
356	/** Intercept RSM instruction. */
357	#define SVM_CTRL_INTERCEPT_RSM RT_BIT_64(19)
358	/** Intercept IRET instruction. */
359	#define SVM_CTRL_INTERCEPT_IRET RT_BIT_64(20)
360	/** Intercept INTn instruction. */
361	#define SVM_CTRL_INTERCEPT_INTN RT_BIT_64(21)
362	/** Intercept INVD instruction. */
363	#define SVM_CTRL_INTERCEPT_INVD RT_BIT_64(22)
364	/** Intercept PAUSE instruction. */
365	#define SVM_CTRL_INTERCEPT_PAUSE RT_BIT_64(23)
366	/** Intercept HLT instruction. */
367	#define SVM_CTRL_INTERCEPT_HLT RT_BIT_64(24)
368	/** Intercept INVLPG instruction. */
369	#define SVM_CTRL_INTERCEPT_INVLPG RT_BIT_64(25)
370	/** Intercept INVLPGA instruction. */
371	#define SVM_CTRL_INTERCEPT_INVLPGA RT_BIT_64(26)
372	/** IOIO_PROT Intercept IN/OUT accesses to selected ports. */
373	#define SVM_CTRL_INTERCEPT_IOIO_PROT RT_BIT_64(27)
374	/** MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
375	#define SVM_CTRL_INTERCEPT_MSR_PROT RT_BIT_64(28)
376	/** Intercept task switches. */
377	#define SVM_CTRL_INTERCEPT_TASK_SWITCH RT_BIT_64(29)
378	/** FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
379	#define SVM_CTRL_INTERCEPT_FERR_FREEZE RT_BIT_64(30)
380	/** Intercept shutdown events. */
381	#define SVM_CTRL_INTERCEPT_SHUTDOWN RT_BIT_64(31)
382	/** Intercept VMRUN instruction. */
383	#define SVM_CTRL_INTERCEPT_VMRUN RT_BIT_64(32 + 0)
384	/** Intercept VMMCALL instruction. */
385	#define SVM_CTRL_INTERCEPT_VMMCALL RT_BIT_64(32 + 1)
386	/** Intercept VMLOAD instruction. */
387	#define SVM_CTRL_INTERCEPT_VMLOAD RT_BIT_64(32 + 2)
388	/** Intercept VMSAVE instruction. */
389	#define SVM_CTRL_INTERCEPT_VMSAVE RT_BIT_64(32 + 3)
390	/** Intercept STGI instruction. */
391	#define SVM_CTRL_INTERCEPT_STGI RT_BIT_64(32 + 4)
392	/** Intercept CLGI instruction. */
393	#define SVM_CTRL_INTERCEPT_CLGI RT_BIT_64(32 + 5)
394	/** Intercept SKINIT instruction. */
395	#define SVM_CTRL_INTERCEPT_SKINIT RT_BIT_64(32 + 6)
396	/** Intercept RDTSCP instruction. */
397	#define SVM_CTRL_INTERCEPT_RDTSCP RT_BIT_64(32 + 7)
398	/** Intercept ICEBP instruction. */
399	#define SVM_CTRL_INTERCEPT_ICEBP RT_BIT_64(32 + 8)
400	/** Intercept WBINVD instruction. */
401	#define SVM_CTRL_INTERCEPT_WBINVD RT_BIT_64(32 + 9)
402	/** Intercept MONITOR instruction. */
403	#define SVM_CTRL_INTERCEPT_MONITOR RT_BIT_64(32 + 10)
404	/** Intercept MWAIT instruction unconditionally. */
405	#define SVM_CTRL_INTERCEPT_MWAIT RT_BIT_64(32 + 11)
406	/** Intercept MWAIT instruction when armed. */
407	#define SVM_CTRL_INTERCEPT_MWAIT_ARMED RT_BIT_64(32 + 12)
408	/** Intercept XSETBV instruction. */
409	#define SVM_CTRL_INTERCEPT_XSETBV RT_BIT_64(32 + 13)
410	/* Bit 14 - Reserved, SBZ. */
411	/** Intercept EFER writes after guest instruction finishes. */
412	#define SVM_CTRL_INTERCEPT_EFER_WRITES_TRAP RT_BIT_64(32 + 15)
413	/** Intercept CR0 writes after guest instruction finishes. */
414	#define SVM_CTRL_INTERCEPT_CR0_WRITES_TRAP RT_BIT_64(32 + 16)
415	/** Intercept CR0 writes after guest instruction finishes. */
416	#define SVM_CTRL_INTERCEPT_CR1_WRITES_TRAP RT_BIT_64(32 + 17)
417	/** Intercept CR0 writes after guest instruction finishes. */
418	#define SVM_CTRL_INTERCEPT_CR2_WRITES_TRAP RT_BIT_64(32 + 18)
419	/** Intercept CR0 writes after guest instruction finishes. */
420	#define SVM_CTRL_INTERCEPT_CR3_WRITES_TRAP RT_BIT_64(32 + 19)
421	/** Intercept CR0 writes after guest instruction finishes. */
422	#define SVM_CTRL_INTERCEPT_CR4_WRITES_TRAP RT_BIT_64(32 + 20)
423	/** Intercept CR0 writes after guest instruction finishes. */
424	#define SVM_CTRL_INTERCEPT_CR5_WRITES_TRAP RT_BIT_64(32 + 21)
425	/** Intercept CR0 writes after guest instruction finishes. */
426	#define SVM_CTRL_INTERCEPT_CR6_WRITES_TRAP RT_BIT_64(32 + 22)
427	/** Intercept CR0 writes after guest instruction finishes. */
428	#define SVM_CTRL_INTERCEPT_CR7_WRITES_TRAP RT_BIT_64(32 + 23)
429	/** Intercept CR0 writes after guest instruction finishes. */
430	#define SVM_CTRL_INTERCEPT_CR8_WRITES_TRAP RT_BIT_64(32 + 24)
431	/** Intercept CR0 writes after guest instruction finishes. */
432	#define SVM_CTRL_INTERCEPT_CR9_WRITES_TRAP RT_BIT_64(32 + 25)
433	/** Intercept CR0 writes after guest instruction finishes. */
434	#define SVM_CTRL_INTERCEPT_CR10_WRITES_TRAP RT_BIT_64(32 + 26)
435	/** Intercept CR0 writes after guest instruction finishes. */
436	#define SVM_CTRL_INTERCEPT_CR11_WRITES_TRAP RT_BIT_64(32 + 27)
437	/** Intercept CR0 writes after guest instruction finishes. */
438	#define SVM_CTRL_INTERCEPT_CR12_WRITES_TRAP RT_BIT_64(32 + 28)
439	/** Intercept CR0 writes after guest instruction finishes. */
440	#define SVM_CTRL_INTERCEPT_CR13_WRITES_TRAP RT_BIT_64(32 + 29)
441	/** Intercept CR0 writes after guest instruction finishes. */
442	#define SVM_CTRL_INTERCEPT_CR14_WRITES_TRAP RT_BIT_64(32 + 30)
443	/** Intercept CR0 writes after guest instruction finishes. */
444	#define SVM_CTRL_INTERCEPT_CR15_WRITES_TRAP RT_BIT_64(32 + 31)
445	/** @} */
446
447	/** @name SVMVMCB.ctrl.u64NestedPaging
448	* @{
449	*/
450	#define SVM_NESTED_PAGING_ENABLE RT_BIT_64(0)
451	/** @} */
452
453	/** @name SVMVMCB.ctrl.u64IntShadow
454	* @{
455	*/
456	#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT_64(0)
457	/** @} */
458
459	/** @name SVMVMCB.u64LbrVirt
460	* @{
461	*/
462	#define SVM_LBR_VIRT_ENABLE RT_BIT_64(0)
463	/** @} */
464
465	/** @name SVMINTCTRL.u3Type
466	* @{
467	*/
468	/** External or virtual interrupt. */
469	#define SVM_EVENT_EXTERNAL_IRQ 0
470	/** Non-maskable interrupt. */
471	#define SVM_EVENT_NMI 2
472	/** Exception; fault or trap. */
473	#define SVM_EVENT_EXCEPTION 3
474	/** Software interrupt. */
475	#define SVM_EVENT_SOFTWARE_INT 4
476	/** @} */
477
478
479	/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
480	* @{
481	*/
482	/** Flush nothing. */
483	#define SVM_TLB_FLUSH_NOTHING 0
484	/** Flush entire TLB (host+guest entries) */
485	#define SVM_TLB_FLUSH_ENTIRE 1
486	/** Flush this guest's TLB entries (by ASID) */
487	#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
488	/** Flush this guest's non-global TLB entries (by ASID) */
489	#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
490	/** @} */
491
492
493	/**
494	* SVM Selector type; includes hidden parts.
495	*/
496	typedef struct
497	{
498	uint16_t u16Sel;
499	uint16_t u16Attr;
500	uint32_t u32Limit;
501	uint64_t u64Base; /*< Only lower 32 bits are implemented for CS, DS, ES & SS. /
502	} SVMSEL;
503	AssertCompileSize(SVMSEL, 16);
504
505	/**
506	* SVM GDTR/IDTR type.
507	*/
508	typedef struct
509	{
510	uint16_t u16Reserved1;
511	uint16_t u16Reserved2;
512	uint32_t u32Limit; /*< Only lower 16 bits are implemented. /
513	uint64_t u64Base;
514	} SVMGDTR;
515	AssertCompileSize(SVMGDTR, 16);
516	typedef SVMGDTR SVMIDTR;
517
518	/**
519	* SVM Event injection structure (EVENTINJ and EXITINTINFO).
520	*/
521	typedef union
522	{
523	struct
524	{
525	uint32_t u8Vector : 8;
526	uint32_t u3Type : 3;
527	uint32_t u1ErrorCodeValid : 1;
528	uint32_t u19Reserved : 19;
529	uint32_t u1Valid : 1;
530	uint32_t u32ErrorCode : 32;
531	} n;
532	uint64_t u;
533	} SVMEVENT;
534	/** Pointer to the SVMEVENT union. */
535	typedef SVMEVENT *PSVMEVENT;
536	/** Pointer to a const SVMEVENT union. */
537	typedef const SVMEVENT *PCSVMEVENT;
538
539	/** Gets the event type given an SVMEVENT parameter. */
540	#define SVM_EVENT_GET_TYPE(a_SvmEvent) (((a_SvmEvent) >> 8) & 7)
541
542	/**
543	* SVM Interrupt control structure (Virtual Interrupt Control).
544	*/
545	typedef union
546	{
547	struct
548	{
549	uint32_t u8VTPR : 8; /* V_TPR */
550	uint32_t u1VIrqPending : 1; /* V_IRQ */
551	uint32_t u7Reserved : 7;
552	uint32_t u4VIntrPrio : 4; /* V_INTR_PRIO */
553	uint32_t u1IgnoreTPR : 1; /* V_IGN_TPR */
554	uint32_t u3Reserved : 3;
555	uint32_t u1VIntrMasking : 1; /* V_INTR_MASKING */
556	uint32_t u6Reserved : 6;
557	uint32_t u1AvicEnable : 1;
558	uint32_t u8VIntrVector : 8; /* V_INTR_VECTOR */
559	uint32_t u24Reserved : 24;
560	} n;
561	uint64_t u;
562	} SVMINTCTRL;
563
564	/**
565	* SVM TLB control structure.
566	*/
567	typedef union
568	{
569	struct
570	{
571	uint32_t u32ASID : 32;
572	uint32_t u8TLBFlush : 8;
573	uint32_t u24Reserved : 24;
574	} n;
575	uint64_t u;
576	} SVMTLBCTRL;
577
578	/**
579	* SVM IOIO exit info. structure (EXITINFO1 for IOIO intercepts).
580	*/
581	typedef union
582	{
583	struct
584	{
585	uint32_t u1Type : 1; /*< Bit 0: 0 = out, 1 = in /
586	uint32_t u1Reserved : 1; /*< Bit 1: Reserved /
587	uint32_t u1STR : 1; /*< Bit 2: String I/O (1) or not (0). /
588	uint32_t u1REP : 1; /*< Bit 3: Repeat prefixed string I/O. /
589	uint32_t u1OP8 : 1; /*< Bit 4: 8-bit operand. /
590	uint32_t u1OP16 : 1; /*< Bit 5: 16-bit operand. /
591	uint32_t u1OP32 : 1; /*< Bit 6: 32-bit operand. /
592	uint32_t u1ADDR16 : 1; /*< Bit 7: 16-bit address size. /
593	uint32_t u1ADDR32 : 1; /*< Bit 8: 32-bit address size. /
594	uint32_t u1ADDR64 : 1; /*< Bit 9: 64-bit address size. /
595	uint32_t u3SEG : 3; /*< BITS 12:10: Effective segment number. Added w/ decode assist in APM v3.17. /
596	uint32_t u3Reserved : 3;
597	uint32_t u16Port : 16; /*< Bits 31:16: Port number. /
598	} n;
599	uint32_t u;
600	} SVMIOIOEXITINFO;
601	/** Pointer to an SVM IOIO exit info. structure. */
602	typedef SVMIOIOEXITINFO *PSVMIOIOEXITINFO;
603	/** Pointer to a const SVM IOIO exit info. structure. */
604	typedef const SVMIOIOEXITINFO *PCSVMIOIOEXITINFO;
605
606	/** 8-bit IO transfer. */
607	#define SVM_IOIO_8_BIT_OP RT_BIT_32(4)
608	/** 16-bit IO transfer. */
609	#define SVM_IOIO_16_BIT_OP RT_BIT_32(5)
610	/** 32-bit IO transfer. */
611	#define SVM_IOIO_32_BIT_OP RT_BIT_32(6)
612	/** Number of bits to shift right to get the operand sizes. */
613	#define SVM_IOIO_OP_SIZE_SHIFT 4
614	/** Mask of all possible IO transfer sizes. */
615	#define SVM_IOIO_OP_SIZE_MASK (SVM_IOIO_8_BIT_OP \| SVM_IOIO_16_BIT_OP \| SVM_IOIO_32_BIT_OP)
616	/** 16-bit address for the IO buffer. */
617	#define SVM_IOIO_16_BIT_ADDR RT_BIT_32(7)
618	/** 32-bit address for the IO buffer. */
619	#define SVM_IOIO_32_BIT_ADDR RT_BIT_32(8)
620	/** 64-bit address for the IO buffer. */
621	#define SVM_IOIO_64_BIT_ADDR RT_BIT_32(9)
622	/** Number of bits to shift right to get the address sizes. */
623	#define SVM_IOIO_ADDR_SIZE_SHIFT 7
624	/** Mask of all the IO address sizes. */
625	#define SVM_IOIO_ADDR_SIZE_MASK (SVM_IOIO_16_BIT_ADDR \| SVM_IOIO_32_BIT_ADDR \| SVM_IOIO_64_BIT_ADDR)
626	/** Number of bits to shift right to get the IO port number. */
627	#define SVM_IOIO_PORT_SHIFT 16
628	/** IO write. */
629	#define SVM_IOIO_WRITE 0
630	/** IO read. */
631	#define SVM_IOIO_READ 1
632	/**
633	* SVM IOIO transfer type.
634	*/
635	typedef enum
636	{
637	SVMIOIOTYPE_OUT = SVM_IOIO_WRITE,
638	SVMIOIOTYPE_IN = SVM_IOIO_READ
639	} SVMIOIOTYPE;
640
641	/**
642	* SVM nested paging structure.
643	*/
644	typedef union
645	{
646	struct
647	{
648	uint32_t u1NestedPaging : 1; /*< enabled/disabled /
649	} n;
650	uint64_t u;
651	} SVMNPCTRL;
652
653	/**
654	* SVM AVIC.
655	*/
656	typedef union
657	{
658	struct
659	{
660	uint64_t u12Reserved1 : 12;
661	uint64_t u40Addr : 40;
662	uint64_t u12Reserved2 : 12;
663	} n;
664	uint64_t u;
665	} SVMAVIC;
666	AssertCompileSize(SVMAVIC, 8);
667
668	/**
669	* SVM AVIC PHYSICAL_TABLE pointer.
670	*/
671	typedef union
672	{
673	struct
674	{
675	uint64_t u8LastGuestCoreId : 8;
676	uint64_t u4Reserved : 4;
677	uint64_t u40Addr : 40;
678	uint64_t u12Reserved : 12;
679	} n;
680	uint64_t u;
681	} SVMAVICPHYS;
682	AssertCompileSize(SVMAVICPHYS, 8);
683
684
685	/**
686	* SVM VMCB control area.
687	*/
688	#pragma pack(1)
689	typedef struct
690	{
691	/** Offset 0x00 - Intercept reads of CR0-CR15. */
692	uint16_t u16InterceptRdCRx;
693	/** Offset 0x02 - Intercept writes to CR0-CR15. */
694	uint16_t u16InterceptWrCRx;
695	/** Offset 0x04 - Intercept reads of DR0-DR15. */
696	uint16_t u16InterceptRdDRx;
697	/** Offset 0x06 - Intercept writes to DR0-DR15. */
698	uint16_t u16InterceptWrDRx;
699	/** Offset 0x08 - Intercept exception vectors 0-31. */
700	uint32_t u32InterceptXcpt;
701	/** Offset 0x0c - Intercept control. */
702	uint64_t u64InterceptCtrl;
703	/** Offset 0x14-0x3f - Reserved. */
704	uint8_t u8Reserved[0x3c - 0x14];
705	/** Offset 0x3c - PAUSE filter threshold. */
706	uint16_t u16PauseFilterThreshold;
707	/** Offset 0x3e - PAUSE intercept filter count. */
708	uint16_t u16PauseFilterCount;
709	/** Offset 0x40 - Physical address of IOPM. */
710	uint64_t u64IOPMPhysAddr;
711	/** Offset 0x48 - Physical address of MSRPM. */
712	uint64_t u64MSRPMPhysAddr;
713	/** Offset 0x50 - TSC Offset. */
714	uint64_t u64TSCOffset;
715	/** Offset 0x58 - TLB control field. */
716	SVMTLBCTRL TLBCtrl;
717	/** Offset 0x60 - Interrupt control field. */
718	SVMINTCTRL IntCtrl;
719	/** Offset 0x68 - Interrupt shadow. */
720	uint64_t u64IntShadow;
721	/** Offset 0x70 - Exit code. */
722	uint64_t u64ExitCode;
723	/** Offset 0x78 - Exit info 1. */
724	uint64_t u64ExitInfo1;
725	/** Offset 0x80 - Exit info 2. */
726	uint64_t u64ExitInfo2;
727	/** Offset 0x88 - Exit Interrupt info. */
728	SVMEVENT ExitIntInfo;
729	/** Offset 0x90 - Nested Paging. */
730	SVMNPCTRL NestedPaging;
731	/** Offset 0x98 - AVIC APIC BAR. */
732	SVMAVIC AvicBar;
733	/** Offset 0xa0-0xa7 - Reserved. */
734	uint8_t u8Reserved2[0xA8 - 0xA0];
735	/** Offset 0xa8 - Event injection. */
736	SVMEVENT EventInject;
737	/** Offset 0xb0 - Host CR3 for nested paging. */
738	uint64_t u64NestedPagingCR3;
739	/** Offset 0xb8 - LBR Virtualization. */
740	uint64_t u64LBRVirt;
741	/** Offset 0xc0 - VMCB Clean Bits. */
742	uint64_t u64VmcbCleanBits;
743	/** Offset 0xc8 - Next sequential instruction pointer. */
744	uint64_t u64NextRIP;
745	/** Offset 0xd0 - Number of bytes fetched. */
746	uint8_t cbInstrFetched;
747	/** Offset 0xd1 - Fetched bytes. */
748	uint8_t abInstr[15];
749	/** Offset 0xe0 - AVIC APIC_BACKING_PAGE pointer. */
750	SVMAVIC AvicBackingPagePtr;
751	/** Offset 0xe8-0xef - Reserved. */
752	uint8_t u8Reserved3[0xF0 - 0xE8];
753	/** Offset 0xf0 - AVIC LOGICAL_TABLE pointer. */
754	SVMAVIC AvicLogicalTablePtr;
755	/** Offset 0xf8 - AVIC PHYSICAL_TABLE pointer. */
756	SVMAVICPHYS AvicPhysicalTablePtr;
757	} SVMVMCBCTRL;
758	#pragma pack()
759	/** Pointer to the SVMVMCBSTATESAVE structure. */
760	typedef SVMVMCBCTRL *PSVMVMCBCTRL;
761	/** Pointer to a const SVMVMCBSTATESAVE structure. */
762	typedef const SVMVMCBCTRL *PCSVMVMCBCTRL;
763	AssertCompileSize(SVMVMCBCTRL, 0x100);
764	AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdCRx, 0x00);
765	AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrCRx, 0x02);
766	AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdDRx, 0x04);
767	AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrDRx, 0x06);
768	AssertCompileMemberOffset(SVMVMCBCTRL, u32InterceptXcpt, 0x08);
769	AssertCompileMemberOffset(SVMVMCBCTRL, u64InterceptCtrl, 0x0c);
770	AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved, 0x14);
771	AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterThreshold, 0x3c);
772	AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterCount, 0x3e);
773	AssertCompileMemberOffset(SVMVMCBCTRL, u64IOPMPhysAddr, 0x40);
774	AssertCompileMemberOffset(SVMVMCBCTRL, u64MSRPMPhysAddr, 0x48);
775	AssertCompileMemberOffset(SVMVMCBCTRL, u64TSCOffset, 0x50);
776	AssertCompileMemberOffset(SVMVMCBCTRL, TLBCtrl, 0x58);
777	AssertCompileMemberOffset(SVMVMCBCTRL, IntCtrl, 0x60);
778	AssertCompileMemberOffset(SVMVMCBCTRL, u64IntShadow, 0x68);
779	AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitCode, 0x70);
780	AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo1, 0x78);
781	AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo2, 0x80);
782	AssertCompileMemberOffset(SVMVMCBCTRL, ExitIntInfo, 0x88);
783	AssertCompileMemberOffset(SVMVMCBCTRL, NestedPaging, 0x90);
784	AssertCompileMemberOffset(SVMVMCBCTRL, AvicBar, 0x98);
785	AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved2, 0xa0);
786	AssertCompileMemberOffset(SVMVMCBCTRL, EventInject, 0xa8);
787	AssertCompileMemberOffset(SVMVMCBCTRL, u64NestedPagingCR3, 0xb0);
788	AssertCompileMemberOffset(SVMVMCBCTRL, u64LBRVirt, 0xb8);
789	AssertCompileMemberOffset(SVMVMCBCTRL, u64VmcbCleanBits, 0xc0);
790	AssertCompileMemberOffset(SVMVMCBCTRL, u64NextRIP, 0xc8);
791	AssertCompileMemberOffset(SVMVMCBCTRL, cbInstrFetched, 0xd0);
792	AssertCompileMemberOffset(SVMVMCBCTRL, abInstr, 0xd1);
793	AssertCompileMemberOffset(SVMVMCBCTRL, AvicBackingPagePtr, 0xe0);
794	AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved3, 0xe8);
795	AssertCompileMemberOffset(SVMVMCBCTRL, AvicLogicalTablePtr, 0xf0);
796	AssertCompileMemberOffset(SVMVMCBCTRL, AvicPhysicalTablePtr, 0xf8);
797
798	/**
799	* SVM VMCB state save area.
800	*/
801	#pragma pack(1)
802	typedef struct
803	{
804	/** Offset 0x400 - Guest ES register + hidden parts. */
805	SVMSEL ES;
806	/** Offset 0x410 - Guest CS register + hidden parts. */
807	SVMSEL CS;
808	/** Offset 0x420 - Guest SS register + hidden parts. */
809	SVMSEL SS;
810	/** Offset 0x430 - Guest DS register + hidden parts. */
811	SVMSEL DS;
812	/** Offset 0x440 - Guest FS register + hidden parts. */
813	SVMSEL FS;
814	/** Offset 0x450 - Guest GS register + hidden parts. */
815	SVMSEL GS;
816	/** Offset 0x460 - Guest GDTR register. */
817	SVMGDTR GDTR;
818	/** Offset 0x470 - Guest LDTR register + hidden parts. */
819	SVMSEL LDTR;
820	/** Offset 0x480 - Guest IDTR register. */
821	SVMIDTR IDTR;
822	/** Offset 0x490 - Guest TR register + hidden parts. */
823	SVMSEL TR;
824	/** Offset 0x4A0-0x4CA - Reserved. */
825	uint8_t u8Reserved4[0x4CB - 0x4A0];
826	/** Offset 0x4CB - CPL. */
827	uint8_t u8CPL;
828	/** Offset 0x4CC-0x4CF - Reserved. */
829	uint8_t u8Reserved5[0x4D0 - 0x4CC];
830	/** Offset 0x4D0 - EFER. */
831	uint64_t u64EFER;
832	/** Offset 0x4D8-0x547 - Reserved. */
833	uint8_t u8Reserved6[0x548 - 0x4D8];
834	/** Offset 0x548 - CR4. */
835	uint64_t u64CR4;
836	/** Offset 0x550 - CR3. */
837	uint64_t u64CR3;
838	/** Offset 0x558 - CR0. */
839	uint64_t u64CR0;
840	/** Offset 0x560 - DR7. */
841	uint64_t u64DR7;
842	/** Offset 0x568 - DR6. */
843	uint64_t u64DR6;
844	/** Offset 0x570 - RFLAGS. */
845	uint64_t u64RFlags;
846	/** Offset 0x578 - RIP. */
847	uint64_t u64RIP;
848	/** Offset 0x580-0x5D7 - Reserved. */
849	uint8_t u8Reserved7[0x5D8 - 0x580];
850	/** Offset 0x5D8 - RSP. */
851	uint64_t u64RSP;
852	/** Offset 0x5E0-0x5F7 - Reserved. */
853	uint8_t u8Reserved8[0x5F8 - 0x5E0];
854	/** Offset 0x5F8 - RAX. */
855	uint64_t u64RAX;
856	/** Offset 0x600 - STAR. */
857	uint64_t u64STAR;
858	/** Offset 0x608 - LSTAR. */
859	uint64_t u64LSTAR;
860	/** Offset 0x610 - CSTAR. */
861	uint64_t u64CSTAR;
862	/** Offset 0x618 - SFMASK. */
863	uint64_t u64SFMASK;
864	/** Offset 0x620 - KernelGSBase. */
865	uint64_t u64KernelGSBase;
866	/** Offset 0x628 - SYSENTER_CS. */
867	uint64_t u64SysEnterCS;
868	/** Offset 0x630 - SYSENTER_ESP. */
869	uint64_t u64SysEnterESP;
870	/** Offset 0x638 - SYSENTER_EIP. */
871	uint64_t u64SysEnterEIP;
872	/** Offset 0x640 - CR2. */
873	uint64_t u64CR2;
874	/** Offset 0x648-0x667 - Reserved. */
875	uint8_t u8Reserved9[0x668 - 0x648];
876	/** Offset 0x668 - G_PAT. */
877	uint64_t u64GPAT;
878	/** Offset 0x670 - DBGCTL. */
879	uint64_t u64DBGCTL;
880	/** Offset 0x678 - BR_FROM. */
881	uint64_t u64BR_FROM;
882	/** Offset 0x680 - BR_TO. */
883	uint64_t u64BR_TO;
884	/** Offset 0x688 - LASTEXCPFROM. */
885	uint64_t u64LASTEXCPFROM;
886	/** Offset 0x690 - LASTEXCPTO. */
887	uint64_t u64LASTEXCPTO;
888	} SVMVMCBSTATESAVE;
889	#pragma pack()
890	/** Pointer to the SVMVMCBSTATESAVE structure. */
891	typedef SVMVMCBSTATESAVE *PSVMVMCBSTATESAVE;
892	/** Pointer to a const SVMVMCBSTATESAVE structure. */
893	typedef const SVMVMCBSTATESAVE *PCSVMVMCBSTATESAVE;
894	AssertCompileSize(SVMVMCBSTATESAVE, 0x298);
895	AssertCompileMemberOffset(SVMVMCBSTATESAVE, ES, 0x400 - 0x400);
896	AssertCompileMemberOffset(SVMVMCBSTATESAVE, CS, 0x410 - 0x400);
897	AssertCompileMemberOffset(SVMVMCBSTATESAVE, SS, 0x420 - 0x400);
898	AssertCompileMemberOffset(SVMVMCBSTATESAVE, DS, 0x430 - 0x400);
899	AssertCompileMemberOffset(SVMVMCBSTATESAVE, FS, 0x440 - 0x400);
900	AssertCompileMemberOffset(SVMVMCBSTATESAVE, GS, 0x450 - 0x400);
901	AssertCompileMemberOffset(SVMVMCBSTATESAVE, GDTR, 0x460 - 0x400);
902	AssertCompileMemberOffset(SVMVMCBSTATESAVE, LDTR, 0x470 - 0x400);
903	AssertCompileMemberOffset(SVMVMCBSTATESAVE, IDTR, 0x480 - 0x400);
904	AssertCompileMemberOffset(SVMVMCBSTATESAVE, TR, 0x490 - 0x400);
905	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved4, 0x4a0 - 0x400);
906	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8CPL, 0x4cb - 0x400);
907	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved5, 0x4cc - 0x400);
908	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64EFER, 0x4d0 - 0x400);
909	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved6, 0x4d8 - 0x400);
910	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR4, 0x548 - 0x400);
911	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR3, 0x550 - 0x400);
912	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR0, 0x558 - 0x400);
913	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR7, 0x560 - 0x400);
914	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR6, 0x568 - 0x400);
915	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RFlags, 0x570 - 0x400);
916	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RIP, 0x578 - 0x400);
917	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved7, 0x580 - 0x400);
918	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RSP, 0x5d8 - 0x400);
919	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved8, 0x5e0 - 0x400);
920	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RAX, 0x5f8 - 0x400);
921	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64STAR, 0x600 - 0x400);
922	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LSTAR, 0x608 - 0x400);
923	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CSTAR, 0x610 - 0x400);
924	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SFMASK, 0x618 - 0x400);
925	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64KernelGSBase, 0x620 - 0x400);
926	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterCS, 0x628 - 0x400);
927	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterESP, 0x630 - 0x400);
928	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterEIP, 0x638 - 0x400);
929	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR2, 0x640 - 0x400);
930	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved9, 0x648 - 0x400);
931	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64GPAT, 0x668 - 0x400);
932	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DBGCTL, 0x670 - 0x400);
933	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_FROM, 0x678 - 0x400);
934	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_TO, 0x680 - 0x400);
935	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPFROM, 0x688 - 0x400);
936	AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPTO, 0x690 - 0x400);
937
938	/**
939	* SVM VM Control Block. (VMCB)
940	*/
941	#pragma pack(1)
942	typedef struct SVMVMCB
943	{
944	/** Offset 0x00 - Control area. */
945	SVMVMCBCTRL ctrl;
946	/** Offset 0x100-0x3FF - Reserved. */
947	uint8_t u8Reserved3[0x400 - 0x100];
948	/** Offset 0x400 - State save area. */
949	SVMVMCBSTATESAVE guest;
950	/** Offset 0x698-0xFFF- Reserved. */
951	uint8_t u8Reserved10[0x1000 - 0x698];
952	} SVMVMCB;
953	#pragma pack()
954	/** Pointer to the SVMVMCB structure. */
955	typedef SVMVMCB *PSVMVMCB;
956	/** Pointer to a const SVMVMCB structure. */
957	typedef const SVMVMCB *PCSVMVMCB;
958	AssertCompileMemberOffset(SVMVMCB, ctrl, 0x00);
959	AssertCompileMemberOffset(SVMVMCB, u8Reserved3, 0x100);
960	AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
961	AssertCompileMemberOffset(SVMVMCB, u8Reserved10, 0x698);
962	AssertCompileSize(SVMVMCB, 0x1000);
963
964	/** SVM nested-guest VMCB cache.
965	*
966	* A state structure for holding information across AMD-V VMRUN/\#VMEXIT
967	* operation during execution of the nested-guest, restored on \#VMEXIT.
968	*/
969	#pragma pack(1)
970	typedef struct SVMNESTEDVMCBCACHE
971	{
972	/** @name Nested-guest VMCB controls.
973	* @{ */
974	/** Cache of CRX read intercepts. */
975	uint16_t u16InterceptRdCRx;
976	/** Cache of CRX write intercepts. */
977	uint16_t u16InterceptWrCRx;
978	/** Cache of DRX read intercepts. */
979	uint16_t u16InterceptRdDRx;
980	/** Cache of DRX write intercepts. */
981	uint16_t u16InterceptWrDRx;
982	/** Cache of exception intercepts. */
983	uint32_t u32InterceptXcpt;
984	/** Alignment. */
985	uint32_t u32Padding0;
986
987	/** Cache of control intercepts. */
988	uint64_t u64InterceptCtrl;
989	/** Cache of IOPM nested-guest physical address. */
990	uint64_t u64IOPMPhysAddr;
991	/** Cache of MSRPM nested-guest physical address. */
992	uint64_t u64MSRPMPhysAddr;
993	/** Cache of the VMCB clean bits. */
994	uint64_t u64VmcbCleanBits;
995	/** Cache of the TLB control. */
996	SVMTLBCTRL TLBCtrl;
997	/** Cache of the nested-paging control. */
998	SVMNPCTRL NestedPagingCtrl;
999	/** @} */
1000
1001	/** @name Nested-guest VMCB guest state.
1002	* @{ */
1003	/** Cache of CR0. */
1004	uint64_t u64CR0;
1005	/** Cache of CR3. */
1006	uint64_t u64CR3;
1007	/** Cache of CR4. */
1008	uint64_t u64CR4;
1009	/** Cache of EFER. */
1010	uint64_t u64EFER;
1011	/** @} */
1012
1013	/** @name Other miscellaneous state.
1014	* @{ */
1015	/** Cache of V_INTR_MASKING bit. */
1016	bool fVIntrMasking;
1017	/** Alignment. */
1018	bool afPadding0[7];
1019	/** @} */
1020	} SVMNESTEDVMCBCACHE;
1021	#pragma pack()
1022	/** Pointer to the SVMNESTEDVMCBCACHE structure. */
1023	typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
1024	/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
1025	typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
1026	AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
1027
1028	#ifdef IN_RING0
1029	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1030	#endif /* IN_RING0 */
1031
1032	/**
1033	* Segment attribute conversion between CPU and AMD-V VMCB format.
1034	*
1035	* The CPU format of the segment attribute is described in X86DESCATTRBITS
1036	* which is 16-bits (i.e. includes 4 bits of the segment limit).
1037	*
1038	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
1039	* only the attribute bits and nothing else). Upper 4-bits are unused.
1040	*/
1041	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
1042	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
1043
1044	/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1045	* Copies the specified segment register to a VMCB from a virtual CPU context.
1046	*
1047	* @param a_pCtx The virtual-CPU context.
1048	* @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1049	* @param a_REG The segment register in the VMCB state-save
1050	* struct (ES/CS/SS/DS).
1051	* @param a_reg The segment register in the virtual CPU struct
1052	* (es/cs/ss/ds).
1053	*/
1054	#define HMSVM_SEG_REG_COPY_TO_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1055	do \
1056	{ \
1057	Assert((a_pCtx)->a_reg.fFlags & CPUMSELREG_FLAGS_VALID); \
1058	Assert((a_pCtx)->a_reg.ValidSel == (a_pCtx)->a_reg.Sel); \
1059	(a_pVmcbStateSave)->a_REG.u16Sel = (a_pCtx)->a_reg.Sel; \
1060	(a_pVmcbStateSave)->a_REG.u32Limit = (a_pCtx)->a_reg.u32Limit; \
1061	(a_pVmcbStateSave)->a_REG.u64Base = (a_pCtx)->a_reg.u64Base; \
1062	(a_pVmcbStateSave)->a_REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR((a_pCtx)->a_reg.Attr.u); \
1063	} while (0)
1064
1065	/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1066	* Copies the specified segment register from the VMCB to a virtual CPU
1067	* context.
1068	*
1069	* @param a_pCtx The virtual-CPU context.
1070	* @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1071	* @param a_REG The segment register in the VMCB state-save
1072	* struct (ES/CS/SS/DS).
1073	* @param a_reg The segment register in the virtual CPU struct
1074	* (es/ds/ss/ds).
1075	*/
1076	#define HMSVM_SEG_REG_COPY_FROM_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1077	do \
1078	{ \
1079	(a_pCtx)->a_reg.Sel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1080	(a_pCtx)->a_reg.ValidSel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1081	(a_pCtx)->a_reg.fFlags = CPUMSELREG_FLAGS_VALID; \
1082	(a_pCtx)->a_reg.u32Limit = (a_pVmcbStateSave)->a_REG.u32Limit; \
1083	(a_pCtx)->a_reg.u64Base = (a_pVmcbStateSave)->a_REG.u64Base; \
1084	(a_pCtx)->a_reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR((a_pVmcbStateSave)->a_REG.u16Attr); \
1085	} while (0)
1086
1087	VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept);
1088	VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr);
1089	VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr);
1090	VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr);
1091	VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr);
1092	VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector);
1093	VMM_INT_DECL(bool) HMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx);
1094
1095	/** @} */
1096
1097	#endif
1098

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source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 70000

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