VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 70415

Last change on this file since 70415 was 70415, checked in by vboxsync, 7 years ago

VMM/HM: Nested Hw.virt: Implement virtual GIF to not intercept CLGI/STGI on CPUs that support the feature.
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1/** @file
2 * HM - SVM (AMD-V) Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2017 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_svm_h
27#define ___VBox_vmm_svm_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/assert.h>
32#include <iprt/asm.h>
33
34#ifdef RT_OS_SOLARIS
35# undef ES
36# undef CS
37# undef DS
38# undef SS
39# undef FS
40# undef GS
41#endif
42
43/** @defgroup grp_hm_svm SVM (AMD-V) Types and Definitions
44 * @ingroup grp_hm
45 * @{
46 */
47
48/** @name SVM generic / convenient defines.
49 * @{
50 */
51/** Number of pages required for the VMCB. */
52#define SVM_VMCB_PAGES 1
53/** Number of pages required for the MSR permission bitmap. */
54#define SVM_MSRPM_PAGES 2
55/** Number of pages required for the IO permission bitmap. */
56#define SVM_IOPM_PAGES 3
57/** @} */
58
59/*
60 * Ugly!
61 * When compiling the recompiler, its own svm.h defines clash with
62 * the following defines. Avoid just the duplicates here as we still
63 * require other definitions and structures in this header.
64 */
65#ifndef IN_REM_R3
66/** @name SVM_EXIT_XXX - SVM Basic Exit Reasons.
67 * @{
68 */
69/** Invalid guest state in VMCB. */
70# define SVM_EXIT_INVALID (uint64_t)(-1)
71/** Read from CR0-CR15. */
72# define SVM_EXIT_READ_CR0 0x0
73# define SVM_EXIT_READ_CR1 0x1
74# define SVM_EXIT_READ_CR2 0x2
75# define SVM_EXIT_READ_CR3 0x3
76# define SVM_EXIT_READ_CR4 0x4
77# define SVM_EXIT_READ_CR5 0x5
78# define SVM_EXIT_READ_CR6 0x6
79# define SVM_EXIT_READ_CR7 0x7
80# define SVM_EXIT_READ_CR8 0x8
81# define SVM_EXIT_READ_CR9 0x9
82# define SVM_EXIT_READ_CR10 0xA
83# define SVM_EXIT_READ_CR11 0xB
84# define SVM_EXIT_READ_CR12 0xC
85# define SVM_EXIT_READ_CR13 0xD
86# define SVM_EXIT_READ_CR14 0xE
87# define SVM_EXIT_READ_CR15 0xF
88/** Writes to CR0-CR15. */
89# define SVM_EXIT_WRITE_CR0 0x10
90# define SVM_EXIT_WRITE_CR1 0x11
91# define SVM_EXIT_WRITE_CR2 0x12
92# define SVM_EXIT_WRITE_CR3 0x13
93# define SVM_EXIT_WRITE_CR4 0x14
94# define SVM_EXIT_WRITE_CR5 0x15
95# define SVM_EXIT_WRITE_CR6 0x16
96# define SVM_EXIT_WRITE_CR7 0x17
97# define SVM_EXIT_WRITE_CR8 0x18
98# define SVM_EXIT_WRITE_CR9 0x19
99# define SVM_EXIT_WRITE_CR10 0x1A
100# define SVM_EXIT_WRITE_CR11 0x1B
101# define SVM_EXIT_WRITE_CR12 0x1C
102# define SVM_EXIT_WRITE_CR13 0x1D
103# define SVM_EXIT_WRITE_CR14 0x1E
104# define SVM_EXIT_WRITE_CR15 0x1F
105/** Read from DR0-DR15. */
106# define SVM_EXIT_READ_DR0 0x20
107# define SVM_EXIT_READ_DR1 0x21
108# define SVM_EXIT_READ_DR2 0x22
109# define SVM_EXIT_READ_DR3 0x23
110# define SVM_EXIT_READ_DR4 0x24
111# define SVM_EXIT_READ_DR5 0x25
112# define SVM_EXIT_READ_DR6 0x26
113# define SVM_EXIT_READ_DR7 0x27
114# define SVM_EXIT_READ_DR8 0x28
115# define SVM_EXIT_READ_DR9 0x29
116# define SVM_EXIT_READ_DR10 0x2A
117# define SVM_EXIT_READ_DR11 0x2B
118# define SVM_EXIT_READ_DR12 0x2C
119# define SVM_EXIT_READ_DR13 0x2D
120# define SVM_EXIT_READ_DR14 0x2E
121# define SVM_EXIT_READ_DR15 0x2F
122/** Writes to DR0-DR15. */
123# define SVM_EXIT_WRITE_DR0 0x30
124# define SVM_EXIT_WRITE_DR1 0x31
125# define SVM_EXIT_WRITE_DR2 0x32
126# define SVM_EXIT_WRITE_DR3 0x33
127# define SVM_EXIT_WRITE_DR4 0x34
128# define SVM_EXIT_WRITE_DR5 0x35
129# define SVM_EXIT_WRITE_DR6 0x36
130# define SVM_EXIT_WRITE_DR7 0x37
131# define SVM_EXIT_WRITE_DR8 0x38
132# define SVM_EXIT_WRITE_DR9 0x39
133# define SVM_EXIT_WRITE_DR10 0x3A
134# define SVM_EXIT_WRITE_DR11 0x3B
135# define SVM_EXIT_WRITE_DR12 0x3C
136# define SVM_EXIT_WRITE_DR13 0x3D
137# define SVM_EXIT_WRITE_DR14 0x3E
138# define SVM_EXIT_WRITE_DR15 0x3F
139/* Exception 0-31. */
140# define SVM_EXIT_EXCEPTION_0 0x40
141# define SVM_EXIT_EXCEPTION_1 0x41
142# define SVM_EXIT_EXCEPTION_2 0x42
143# define SVM_EXIT_EXCEPTION_3 0x43
144# define SVM_EXIT_EXCEPTION_4 0x44
145# define SVM_EXIT_EXCEPTION_5 0x45
146# define SVM_EXIT_EXCEPTION_6 0x46
147# define SVM_EXIT_EXCEPTION_7 0x47
148# define SVM_EXIT_EXCEPTION_8 0x48
149# define SVM_EXIT_EXCEPTION_9 0x49
150# define SVM_EXIT_EXCEPTION_10 0x4A
151# define SVM_EXIT_EXCEPTION_11 0x4B
152# define SVM_EXIT_EXCEPTION_12 0x4C
153# define SVM_EXIT_EXCEPTION_13 0x4D
154# define SVM_EXIT_EXCEPTION_14 0x4E
155# define SVM_EXIT_EXCEPTION_15 0x4F
156# define SVM_EXIT_EXCEPTION_16 0x50
157# define SVM_EXIT_EXCEPTION_17 0x51
158# define SVM_EXIT_EXCEPTION_18 0x52
159# define SVM_EXIT_EXCEPTION_19 0x53
160# define SVM_EXIT_EXCEPTION_20 0x54
161# define SVM_EXIT_EXCEPTION_21 0x55
162# define SVM_EXIT_EXCEPTION_22 0x56
163# define SVM_EXIT_EXCEPTION_23 0x57
164# define SVM_EXIT_EXCEPTION_24 0x58
165# define SVM_EXIT_EXCEPTION_25 0x59
166# define SVM_EXIT_EXCEPTION_26 0x5A
167# define SVM_EXIT_EXCEPTION_27 0x5B
168# define SVM_EXIT_EXCEPTION_28 0x5C
169# define SVM_EXIT_EXCEPTION_29 0x5D
170# define SVM_EXIT_EXCEPTION_30 0x5E
171# define SVM_EXIT_EXCEPTION_31 0x5F
172/** Physical maskable interrupt. */
173# define SVM_EXIT_INTR 0x60
174/** Non-maskable interrupt. */
175# define SVM_EXIT_NMI 0x61
176/** System Management interrupt. */
177# define SVM_EXIT_SMI 0x62
178/** Physical INIT signal. */
179# define SVM_EXIT_INIT 0x63
180/** Virtual interrupt. */
181# define SVM_EXIT_VINTR 0x64
182/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
183# define SVM_EXIT_CR0_SEL_WRITE 0x65
184/** IDTR read. */
185# define SVM_EXIT_IDTR_READ 0x66
186/** GDTR read. */
187# define SVM_EXIT_GDTR_READ 0x67
188/** LDTR read. */
189# define SVM_EXIT_LDTR_READ 0x68
190/** TR read. */
191# define SVM_EXIT_TR_READ 0x69
192/** IDTR write. */
193# define SVM_EXIT_IDTR_WRITE 0x6A
194/** GDTR write. */
195# define SVM_EXIT_GDTR_WRITE 0x6B
196/** LDTR write. */
197# define SVM_EXIT_LDTR_WRITE 0x6C
198/** TR write. */
199# define SVM_EXIT_TR_WRITE 0x6D
200/** RDTSC instruction. */
201# define SVM_EXIT_RDTSC 0x6E
202/** RDPMC instruction. */
203# define SVM_EXIT_RDPMC 0x6F
204/** PUSHF instruction. */
205# define SVM_EXIT_PUSHF 0x70
206/** POPF instruction. */
207# define SVM_EXIT_POPF 0x71
208/** CPUID instruction. */
209# define SVM_EXIT_CPUID 0x72
210/** RSM instruction. */
211# define SVM_EXIT_RSM 0x73
212/** IRET instruction. */
213# define SVM_EXIT_IRET 0x74
214/** software interrupt (INTn instructions). */
215# define SVM_EXIT_SWINT 0x75
216/** INVD instruction. */
217# define SVM_EXIT_INVD 0x76
218/** PAUSE instruction. */
219# define SVM_EXIT_PAUSE 0x77
220/** HLT instruction. */
221# define SVM_EXIT_HLT 0x78
222/** INVLPG instructions. */
223# define SVM_EXIT_INVLPG 0x79
224/** INVLPGA instruction. */
225# define SVM_EXIT_INVLPGA 0x7A
226/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
227# define SVM_EXIT_IOIO 0x7B
228/** RDMSR or WRMSR access to protected MSR. */
229# define SVM_EXIT_MSR 0x7C
230/** task switch. */
231# define SVM_EXIT_TASK_SWITCH 0x7D
232/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
233# define SVM_EXIT_FERR_FREEZE 0x7E
234/** Shutdown. */
235# define SVM_EXIT_SHUTDOWN 0x7F
236/** VMRUN instruction. */
237# define SVM_EXIT_VMRUN 0x80
238/** VMMCALL instruction. */
239# define SVM_EXIT_VMMCALL 0x81
240/** VMLOAD instruction. */
241# define SVM_EXIT_VMLOAD 0x82
242/** VMSAVE instruction. */
243# define SVM_EXIT_VMSAVE 0x83
244/** STGI instruction. */
245# define SVM_EXIT_STGI 0x84
246/** CLGI instruction. */
247# define SVM_EXIT_CLGI 0x85
248/** SKINIT instruction. */
249# define SVM_EXIT_SKINIT 0x86
250/** RDTSCP instruction. */
251# define SVM_EXIT_RDTSCP 0x87
252/** ICEBP instruction. */
253# define SVM_EXIT_ICEBP 0x88
254/** WBINVD instruction. */
255# define SVM_EXIT_WBINVD 0x89
256/** MONITOR instruction. */
257# define SVM_EXIT_MONITOR 0x8A
258/** MWAIT instruction. */
259# define SVM_EXIT_MWAIT 0x8B
260/** MWAIT instruction, when armed. */
261# define SVM_EXIT_MWAIT_ARMED 0x8C
262/** XSETBV instruction. */
263# define SVM_EXIT_XSETBV 0x8D
264/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
265# define SVM_EXIT_NPF 0x400
266/** AVIC: Virtual IPI delivery not completed. */
267# define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
268/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
269 * hardware. */
270# define SVM_EXIT_AVIC_NOACCEL 0x402
271/** The maximum possible exit value. */
272# define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
273/** @} */
274#endif /* !IN_REM_R3*/
275
276
277/** @name SVMVMCB.u64ExitInfo2 for task switches
278 * @{
279 */
280/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
281#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
282/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
283#define SVM_EXIT2_TASK_SWITCH_JMP RT_BIT_64(38)
284/** Set to 1 if the task switch has an error code; else cleared to 0. */
285#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
286/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
287#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
288/** @} */
289
290/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
291 * @{
292 */
293/** The access was a read MSR. */
294#define SVM_EXIT1_MSR_READ 0x0
295/** The access was a write MSR. */
296#define SVM_EXIT1_MSR_WRITE 0x1
297/** @} */
298
299/** @name SVMVMCB.u64ExitInfo1 for Mov CRx accesses.
300 * @{
301 */
302/** The mask of whether the access was via a Mov CRx instruction. */
303#define SVM_EXIT1_MOV_CRX_MASK RT_BIT_64(63)
304/** The mask for the GPR number of the Mov CRx instruction. */
305#define SVM_EXIT1_MOV_CRX_GPR_NUMBER 0xf
306/** @} */
307
308/** @name SVMVMCB.u64ExitInfo1 for Mov DRx accesses.
309 * @{
310 */
311/** The mask for the GPR number of the Mov DRx instruction. */
312#define SVM_EXIT1_MOV_DRX_GPR_NUMBER 0xf
313/** @} */
314
315/** @name SVMVMCB.ctrl.u64InterceptCtrl
316 * @{
317 */
318/** Intercept INTR (physical maskable interrupt). */
319#define SVM_CTRL_INTERCEPT_INTR RT_BIT_64(0)
320/** Intercept NMI. */
321#define SVM_CTRL_INTERCEPT_NMI RT_BIT_64(1)
322/** Intercept SMI. */
323#define SVM_CTRL_INTERCEPT_SMI RT_BIT_64(2)
324/** Intercept INIT. */
325#define SVM_CTRL_INTERCEPT_INIT RT_BIT_64(3)
326/** Intercept VINTR (virtual maskable interrupt). */
327#define SVM_CTRL_INTERCEPT_VINTR RT_BIT_64(4)
328/** Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
329#define SVM_CTRL_INTERCEPT_CR0_SEL_WRITES RT_BIT_64(5)
330/** Intercept reads of IDTR. */
331#define SVM_CTRL_INTERCEPT_IDTR_READS RT_BIT_64(6)
332/** Intercept reads of GDTR. */
333#define SVM_CTRL_INTERCEPT_GDTR_READS RT_BIT_64(7)
334/** Intercept reads of LDTR. */
335#define SVM_CTRL_INTERCEPT_LDTR_READS RT_BIT_64(8)
336/** Intercept reads of TR. */
337#define SVM_CTRL_INTERCEPT_TR_READS RT_BIT_64(9)
338/** Intercept writes of IDTR. */
339#define SVM_CTRL_INTERCEPT_IDTR_WRITES RT_BIT_64(10)
340/** Intercept writes of GDTR. */
341#define SVM_CTRL_INTERCEPT_GDTR_WRITES RT_BIT_64(11)
342/** Intercept writes of LDTR. */
343#define SVM_CTRL_INTERCEPT_LDTR_WRITES RT_BIT_64(12)
344/** Intercept writes of TR. */
345#define SVM_CTRL_INTERCEPT_TR_WRITES RT_BIT_64(13)
346/** Intercept RDTSC instruction. */
347#define SVM_CTRL_INTERCEPT_RDTSC RT_BIT_64(14)
348/** Intercept RDPMC instruction. */
349#define SVM_CTRL_INTERCEPT_RDPMC RT_BIT_64(15)
350/** Intercept PUSHF instruction. */
351#define SVM_CTRL_INTERCEPT_PUSHF RT_BIT_64(16)
352/** Intercept POPF instruction. */
353#define SVM_CTRL_INTERCEPT_POPF RT_BIT_64(17)
354/** Intercept CPUID instruction. */
355#define SVM_CTRL_INTERCEPT_CPUID RT_BIT_64(18)
356/** Intercept RSM instruction. */
357#define SVM_CTRL_INTERCEPT_RSM RT_BIT_64(19)
358/** Intercept IRET instruction. */
359#define SVM_CTRL_INTERCEPT_IRET RT_BIT_64(20)
360/** Intercept INTn instruction. */
361#define SVM_CTRL_INTERCEPT_INTN RT_BIT_64(21)
362/** Intercept INVD instruction. */
363#define SVM_CTRL_INTERCEPT_INVD RT_BIT_64(22)
364/** Intercept PAUSE instruction. */
365#define SVM_CTRL_INTERCEPT_PAUSE RT_BIT_64(23)
366/** Intercept HLT instruction. */
367#define SVM_CTRL_INTERCEPT_HLT RT_BIT_64(24)
368/** Intercept INVLPG instruction. */
369#define SVM_CTRL_INTERCEPT_INVLPG RT_BIT_64(25)
370/** Intercept INVLPGA instruction. */
371#define SVM_CTRL_INTERCEPT_INVLPGA RT_BIT_64(26)
372/** IOIO_PROT Intercept IN/OUT accesses to selected ports. */
373#define SVM_CTRL_INTERCEPT_IOIO_PROT RT_BIT_64(27)
374/** MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
375#define SVM_CTRL_INTERCEPT_MSR_PROT RT_BIT_64(28)
376/** Intercept task switches. */
377#define SVM_CTRL_INTERCEPT_TASK_SWITCH RT_BIT_64(29)
378/** FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
379#define SVM_CTRL_INTERCEPT_FERR_FREEZE RT_BIT_64(30)
380/** Intercept shutdown events. */
381#define SVM_CTRL_INTERCEPT_SHUTDOWN RT_BIT_64(31)
382/** Intercept VMRUN instruction. */
383#define SVM_CTRL_INTERCEPT_VMRUN RT_BIT_64(32 + 0)
384/** Intercept VMMCALL instruction. */
385#define SVM_CTRL_INTERCEPT_VMMCALL RT_BIT_64(32 + 1)
386/** Intercept VMLOAD instruction. */
387#define SVM_CTRL_INTERCEPT_VMLOAD RT_BIT_64(32 + 2)
388/** Intercept VMSAVE instruction. */
389#define SVM_CTRL_INTERCEPT_VMSAVE RT_BIT_64(32 + 3)
390/** Intercept STGI instruction. */
391#define SVM_CTRL_INTERCEPT_STGI RT_BIT_64(32 + 4)
392/** Intercept CLGI instruction. */
393#define SVM_CTRL_INTERCEPT_CLGI RT_BIT_64(32 + 5)
394/** Intercept SKINIT instruction. */
395#define SVM_CTRL_INTERCEPT_SKINIT RT_BIT_64(32 + 6)
396/** Intercept RDTSCP instruction. */
397#define SVM_CTRL_INTERCEPT_RDTSCP RT_BIT_64(32 + 7)
398/** Intercept ICEBP instruction. */
399#define SVM_CTRL_INTERCEPT_ICEBP RT_BIT_64(32 + 8)
400/** Intercept WBINVD instruction. */
401#define SVM_CTRL_INTERCEPT_WBINVD RT_BIT_64(32 + 9)
402/** Intercept MONITOR instruction. */
403#define SVM_CTRL_INTERCEPT_MONITOR RT_BIT_64(32 + 10)
404/** Intercept MWAIT instruction unconditionally. */
405#define SVM_CTRL_INTERCEPT_MWAIT RT_BIT_64(32 + 11)
406/** Intercept MWAIT instruction when armed. */
407#define SVM_CTRL_INTERCEPT_MWAIT_ARMED RT_BIT_64(32 + 12)
408/** Intercept XSETBV instruction. */
409#define SVM_CTRL_INTERCEPT_XSETBV RT_BIT_64(32 + 13)
410/* Bit 14 - Reserved, SBZ. */
411/** Intercept EFER writes after guest instruction finishes. */
412#define SVM_CTRL_INTERCEPT_EFER_WRITES_TRAP RT_BIT_64(32 + 15)
413/** Intercept CR0 writes after guest instruction finishes. */
414#define SVM_CTRL_INTERCEPT_CR0_WRITES_TRAP RT_BIT_64(32 + 16)
415/** Intercept CR0 writes after guest instruction finishes. */
416#define SVM_CTRL_INTERCEPT_CR1_WRITES_TRAP RT_BIT_64(32 + 17)
417/** Intercept CR0 writes after guest instruction finishes. */
418#define SVM_CTRL_INTERCEPT_CR2_WRITES_TRAP RT_BIT_64(32 + 18)
419/** Intercept CR0 writes after guest instruction finishes. */
420#define SVM_CTRL_INTERCEPT_CR3_WRITES_TRAP RT_BIT_64(32 + 19)
421/** Intercept CR0 writes after guest instruction finishes. */
422#define SVM_CTRL_INTERCEPT_CR4_WRITES_TRAP RT_BIT_64(32 + 20)
423/** Intercept CR0 writes after guest instruction finishes. */
424#define SVM_CTRL_INTERCEPT_CR5_WRITES_TRAP RT_BIT_64(32 + 21)
425/** Intercept CR0 writes after guest instruction finishes. */
426#define SVM_CTRL_INTERCEPT_CR6_WRITES_TRAP RT_BIT_64(32 + 22)
427/** Intercept CR0 writes after guest instruction finishes. */
428#define SVM_CTRL_INTERCEPT_CR7_WRITES_TRAP RT_BIT_64(32 + 23)
429/** Intercept CR0 writes after guest instruction finishes. */
430#define SVM_CTRL_INTERCEPT_CR8_WRITES_TRAP RT_BIT_64(32 + 24)
431/** Intercept CR0 writes after guest instruction finishes. */
432#define SVM_CTRL_INTERCEPT_CR9_WRITES_TRAP RT_BIT_64(32 + 25)
433/** Intercept CR0 writes after guest instruction finishes. */
434#define SVM_CTRL_INTERCEPT_CR10_WRITES_TRAP RT_BIT_64(32 + 26)
435/** Intercept CR0 writes after guest instruction finishes. */
436#define SVM_CTRL_INTERCEPT_CR11_WRITES_TRAP RT_BIT_64(32 + 27)
437/** Intercept CR0 writes after guest instruction finishes. */
438#define SVM_CTRL_INTERCEPT_CR12_WRITES_TRAP RT_BIT_64(32 + 28)
439/** Intercept CR0 writes after guest instruction finishes. */
440#define SVM_CTRL_INTERCEPT_CR13_WRITES_TRAP RT_BIT_64(32 + 29)
441/** Intercept CR0 writes after guest instruction finishes. */
442#define SVM_CTRL_INTERCEPT_CR14_WRITES_TRAP RT_BIT_64(32 + 30)
443/** Intercept CR0 writes after guest instruction finishes. */
444#define SVM_CTRL_INTERCEPT_CR15_WRITES_TRAP RT_BIT_64(32 + 31)
445/** @} */
446
447/** @name SVMINTCTRL.u3Type
448 * @{
449 */
450/** External or virtual interrupt. */
451#define SVM_EVENT_EXTERNAL_IRQ 0
452/** Non-maskable interrupt. */
453#define SVM_EVENT_NMI 2
454/** Exception; fault or trap. */
455#define SVM_EVENT_EXCEPTION 3
456/** Software interrupt. */
457#define SVM_EVENT_SOFTWARE_INT 4
458/** @} */
459
460/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
461 * @{
462 */
463/** Flush nothing. */
464#define SVM_TLB_FLUSH_NOTHING 0
465/** Flush entire TLB (host+guest entries) */
466#define SVM_TLB_FLUSH_ENTIRE 1
467/** Flush this guest's TLB entries (by ASID) */
468#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
469/** Flush this guest's non-global TLB entries (by ASID) */
470#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
471/** @} */
472
473/**
474 * SVM selector/segment register type.
475 */
476typedef struct
477{
478 uint16_t u16Sel;
479 uint16_t u16Attr;
480 uint32_t u32Limit;
481 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
482} SVMSELREG;
483AssertCompileSize(SVMSELREG, 16);
484/** Pointer to the SVMSELREG struct. */
485typedef SVMSELREG *PSVMSELREG;
486/** Pointer to a const SVMSELREG struct. */
487typedef const SVMSELREG *PCSVMSELREG;
488
489/**
490 * SVM GDTR/IDTR type.
491 */
492typedef struct
493{
494 uint16_t u16Reserved1;
495 uint16_t u16Reserved2;
496 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
497 uint64_t u64Base;
498} SVMXDTR;
499AssertCompileSize(SVMXDTR, 16);
500typedef SVMXDTR SVMIDTR;
501typedef SVMXDTR SVMGDTR;
502/** Pointer to the SVMXDTR struct. */
503typedef SVMXDTR *PSVMXDTR;
504/** Pointer to a const SVMXDTR struct. */
505typedef const SVMXDTR *PCSVMXDTR;
506
507/**
508 * SVM Event injection structure (EVENTINJ and EXITINTINFO).
509 */
510typedef union
511{
512 struct
513 {
514 uint32_t u8Vector : 8;
515 uint32_t u3Type : 3;
516 uint32_t u1ErrorCodeValid : 1;
517 uint32_t u19Reserved : 19;
518 uint32_t u1Valid : 1;
519 uint32_t u32ErrorCode : 32;
520 } n;
521 uint64_t u;
522} SVMEVENT;
523/** Pointer to the SVMEVENT union. */
524typedef SVMEVENT *PSVMEVENT;
525/** Pointer to a const SVMEVENT union. */
526typedef const SVMEVENT *PCSVMEVENT;
527
528/** Gets the event type given an SVMEVENT parameter. */
529#define SVM_EVENT_GET_TYPE(a_SvmEvent) (((a_SvmEvent) >> 8) & 7)
530
531/**
532 * SVM Interrupt control structure (Virtual Interrupt Control).
533 */
534typedef union
535{
536 struct
537 {
538 uint32_t u8VTPR : 8; /* V_TPR */
539 uint32_t u1VIrqPending : 1; /* V_IRQ */
540 uint32_t u1VGif : 1; /* VGIF */
541 uint32_t u6Reserved0 : 6;
542 uint32_t u4VIntrPrio : 4; /* V_INTR_PRIO */
543 uint32_t u1IgnoreTPR : 1; /* V_IGN_TPR */
544 uint32_t u3Reserved : 3;
545 uint32_t u1VIntrMasking : 1; /* V_INTR_MASKING */
546 uint32_t u1VGifEnable : 1; /* VGIF enable */
547 uint32_t u5Reserved1 : 5;
548 uint32_t u1AvicEnable : 1; /* AVIC enable */
549 uint32_t u8VIntrVector : 8; /* V_INTR_VECTOR */
550 uint32_t u24Reserved : 24;
551 } n;
552 uint64_t u;
553} SVMINTCTRL;
554
555/**
556 * SVM TLB control structure.
557 */
558typedef union
559{
560 struct
561 {
562 uint32_t u32ASID : 32;
563 uint32_t u8TLBFlush : 8;
564 uint32_t u24Reserved : 24;
565 } n;
566 uint64_t u;
567} SVMTLBCTRL;
568
569/**
570 * SVM IOIO exit info. structure (EXITINFO1 for IOIO intercepts).
571 */
572typedef union
573{
574 struct
575 {
576 uint32_t u1Type : 1; /**< Bit 0: 0 = out, 1 = in */
577 uint32_t u1Reserved : 1; /**< Bit 1: Reserved */
578 uint32_t u1STR : 1; /**< Bit 2: String I/O (1) or not (0). */
579 uint32_t u1REP : 1; /**< Bit 3: Repeat prefixed string I/O. */
580 uint32_t u1OP8 : 1; /**< Bit 4: 8-bit operand. */
581 uint32_t u1OP16 : 1; /**< Bit 5: 16-bit operand. */
582 uint32_t u1OP32 : 1; /**< Bit 6: 32-bit operand. */
583 uint32_t u1ADDR16 : 1; /**< Bit 7: 16-bit address size. */
584 uint32_t u1ADDR32 : 1; /**< Bit 8: 32-bit address size. */
585 uint32_t u1ADDR64 : 1; /**< Bit 9: 64-bit address size. */
586 uint32_t u3SEG : 3; /**< BITS 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
587 uint32_t u3Reserved : 3;
588 uint32_t u16Port : 16; /**< Bits 31:16: Port number. */
589 } n;
590 uint32_t u;
591} SVMIOIOEXITINFO;
592/** Pointer to an SVM IOIO exit info. structure. */
593typedef SVMIOIOEXITINFO *PSVMIOIOEXITINFO;
594/** Pointer to a const SVM IOIO exit info. structure. */
595typedef const SVMIOIOEXITINFO *PCSVMIOIOEXITINFO;
596
597/** 8-bit IO transfer. */
598#define SVM_IOIO_8_BIT_OP RT_BIT_32(4)
599/** 16-bit IO transfer. */
600#define SVM_IOIO_16_BIT_OP RT_BIT_32(5)
601/** 32-bit IO transfer. */
602#define SVM_IOIO_32_BIT_OP RT_BIT_32(6)
603/** Number of bits to shift right to get the operand sizes. */
604#define SVM_IOIO_OP_SIZE_SHIFT 4
605/** Mask of all possible IO transfer sizes. */
606#define SVM_IOIO_OP_SIZE_MASK (SVM_IOIO_8_BIT_OP | SVM_IOIO_16_BIT_OP | SVM_IOIO_32_BIT_OP)
607/** 16-bit address for the IO buffer. */
608#define SVM_IOIO_16_BIT_ADDR RT_BIT_32(7)
609/** 32-bit address for the IO buffer. */
610#define SVM_IOIO_32_BIT_ADDR RT_BIT_32(8)
611/** 64-bit address for the IO buffer. */
612#define SVM_IOIO_64_BIT_ADDR RT_BIT_32(9)
613/** Number of bits to shift right to get the address sizes. */
614#define SVM_IOIO_ADDR_SIZE_SHIFT 7
615/** Mask of all the IO address sizes. */
616#define SVM_IOIO_ADDR_SIZE_MASK (SVM_IOIO_16_BIT_ADDR | SVM_IOIO_32_BIT_ADDR | SVM_IOIO_64_BIT_ADDR)
617/** Number of bits to shift right to get the IO port number. */
618#define SVM_IOIO_PORT_SHIFT 16
619/** IO write. */
620#define SVM_IOIO_WRITE 0
621/** IO read. */
622#define SVM_IOIO_READ 1
623/**
624 * SVM IOIO transfer type.
625 */
626typedef enum
627{
628 SVMIOIOTYPE_OUT = SVM_IOIO_WRITE,
629 SVMIOIOTYPE_IN = SVM_IOIO_READ
630} SVMIOIOTYPE;
631
632/**
633 * SVM AVIC.
634 */
635typedef union
636{
637 struct
638 {
639 uint64_t u12Reserved1 : 12;
640 uint64_t u40Addr : 40;
641 uint64_t u12Reserved2 : 12;
642 } n;
643 uint64_t u;
644} SVMAVIC;
645AssertCompileSize(SVMAVIC, 8);
646
647/**
648 * SVM AVIC PHYSICAL_TABLE pointer.
649 */
650typedef union
651{
652 struct
653 {
654 uint64_t u8LastGuestCoreId : 8;
655 uint64_t u4Reserved : 4;
656 uint64_t u40Addr : 40;
657 uint64_t u12Reserved : 12;
658 } n;
659 uint64_t u;
660} SVMAVICPHYS;
661AssertCompileSize(SVMAVICPHYS, 8);
662
663/**
664 * SVM Nested Paging struct.
665 */
666typedef union
667{
668 struct
669 {
670 uint32_t u1NestedPaging : 1;
671 uint32_t u1Sev : 1;
672 uint32_t u1SevEs : 1;
673 uint32_t u29Reserved0 : 29;
674 } n;
675 uint64_t u;
676} SVMNP;
677AssertCompileSize(SVMNP, 8);
678
679/**
680 * SVM Interrupt shadow struct.
681 */
682typedef union
683{
684 struct
685 {
686 uint32_t u1IntShadow : 1;
687 uint32_t u1GuestIntMask : 1;
688 uint32_t u30Reserved0 : 30;
689 } n;
690 uint64_t u;
691} SVMINTSHADOW;
692AssertCompileSize(SVMINTSHADOW, 8);
693
694/**
695 * SVM LBR virtualization struct.
696 */
697typedef union
698{
699 struct
700 {
701 uint32_t u1LbrVirt : 1;
702 uint32_t u1VirtVmsaveVmload : 1;
703 uint32_t u30Reserved1 : 30;
704 } n;
705 uint64_t u;
706} SVMLBRVIRT;
707AssertCompileSize(SVMLBRVIRT, 8);
708
709/**
710 * SVM VMCB control area.
711 */
712#pragma pack(1)
713typedef struct
714{
715 /** Offset 0x00 - Intercept reads of CR0-CR15. */
716 uint16_t u16InterceptRdCRx;
717 /** Offset 0x02 - Intercept writes to CR0-CR15. */
718 uint16_t u16InterceptWrCRx;
719 /** Offset 0x04 - Intercept reads of DR0-DR15. */
720 uint16_t u16InterceptRdDRx;
721 /** Offset 0x06 - Intercept writes to DR0-DR15. */
722 uint16_t u16InterceptWrDRx;
723 /** Offset 0x08 - Intercept exception vectors 0-31. */
724 uint32_t u32InterceptXcpt;
725 /** Offset 0x0c - Intercept control. */
726 uint64_t u64InterceptCtrl;
727 /** Offset 0x14-0x3f - Reserved. */
728 uint8_t u8Reserved[0x3c - 0x14];
729 /** Offset 0x3c - PAUSE filter threshold. */
730 uint16_t u16PauseFilterThreshold;
731 /** Offset 0x3e - PAUSE intercept filter count. */
732 uint16_t u16PauseFilterCount;
733 /** Offset 0x40 - Physical address of IOPM. */
734 uint64_t u64IOPMPhysAddr;
735 /** Offset 0x48 - Physical address of MSRPM. */
736 uint64_t u64MSRPMPhysAddr;
737 /** Offset 0x50 - TSC Offset. */
738 uint64_t u64TSCOffset;
739 /** Offset 0x58 - TLB control field. */
740 SVMTLBCTRL TLBCtrl;
741 /** Offset 0x60 - Interrupt control field. */
742 SVMINTCTRL IntCtrl;
743 /** Offset 0x68 - Interrupt shadow. */
744 SVMINTSHADOW IntShadow;
745 /** Offset 0x70 - Exit code. */
746 uint64_t u64ExitCode;
747 /** Offset 0x78 - Exit info 1. */
748 uint64_t u64ExitInfo1;
749 /** Offset 0x80 - Exit info 2. */
750 uint64_t u64ExitInfo2;
751 /** Offset 0x88 - Exit Interrupt info. */
752 SVMEVENT ExitIntInfo;
753 /** Offset 0x90 - Nested Paging. */
754 SVMNP NestedPaging;
755 /** Offset 0x98 - AVIC APIC BAR. */
756 SVMAVIC AvicBar;
757 /** Offset 0xa0-0xa7 - Reserved. */
758 uint8_t u8Reserved2[0xA8 - 0xA0];
759 /** Offset 0xa8 - Event injection. */
760 SVMEVENT EventInject;
761 /** Offset 0xb0 - Host CR3 for nested paging. */
762 uint64_t u64NestedPagingCR3;
763 /** Offset 0xb8 - LBR Virtualization. */
764 SVMLBRVIRT LbrVirt;
765 /** Offset 0xc0 - VMCB Clean Bits. */
766 uint32_t u32VmcbCleanBits;
767 uint32_t u32Reserved0;
768 /** Offset 0xc8 - Next sequential instruction pointer. */
769 uint64_t u64NextRIP;
770 /** Offset 0xd0 - Number of bytes fetched. */
771 uint8_t cbInstrFetched;
772 /** Offset 0xd1 - Fetched bytes. */
773 uint8_t abInstr[15];
774 /** Offset 0xe0 - AVIC APIC_BACKING_PAGE pointer. */
775 SVMAVIC AvicBackingPagePtr;
776 /** Offset 0xe8-0xef - Reserved. */
777 uint8_t u8Reserved3[0xF0 - 0xE8];
778 /** Offset 0xf0 - AVIC LOGICAL_TABLE pointer. */
779 SVMAVIC AvicLogicalTablePtr;
780 /** Offset 0xf8 - AVIC PHYSICAL_TABLE pointer. */
781 SVMAVICPHYS AvicPhysicalTablePtr;
782} SVMVMCBCTRL;
783#pragma pack()
784/** Pointer to the SVMVMCBSTATESAVE structure. */
785typedef SVMVMCBCTRL *PSVMVMCBCTRL;
786/** Pointer to a const SVMVMCBSTATESAVE structure. */
787typedef const SVMVMCBCTRL *PCSVMVMCBCTRL;
788AssertCompileSize(SVMVMCBCTRL, 0x100);
789AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdCRx, 0x00);
790AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrCRx, 0x02);
791AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdDRx, 0x04);
792AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrDRx, 0x06);
793AssertCompileMemberOffset(SVMVMCBCTRL, u32InterceptXcpt, 0x08);
794AssertCompileMemberOffset(SVMVMCBCTRL, u64InterceptCtrl, 0x0c);
795AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved, 0x14);
796AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterThreshold, 0x3c);
797AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterCount, 0x3e);
798AssertCompileMemberOffset(SVMVMCBCTRL, u64IOPMPhysAddr, 0x40);
799AssertCompileMemberOffset(SVMVMCBCTRL, u64MSRPMPhysAddr, 0x48);
800AssertCompileMemberOffset(SVMVMCBCTRL, u64TSCOffset, 0x50);
801AssertCompileMemberOffset(SVMVMCBCTRL, TLBCtrl, 0x58);
802AssertCompileMemberOffset(SVMVMCBCTRL, IntCtrl, 0x60);
803AssertCompileMemberOffset(SVMVMCBCTRL, IntShadow, 0x68);
804AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitCode, 0x70);
805AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo1, 0x78);
806AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo2, 0x80);
807AssertCompileMemberOffset(SVMVMCBCTRL, ExitIntInfo, 0x88);
808AssertCompileMemberOffset(SVMVMCBCTRL, NestedPaging, 0x90);
809AssertCompileMemberOffset(SVMVMCBCTRL, AvicBar, 0x98);
810AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved2, 0xa0);
811AssertCompileMemberOffset(SVMVMCBCTRL, EventInject, 0xa8);
812AssertCompileMemberOffset(SVMVMCBCTRL, u64NestedPagingCR3, 0xb0);
813AssertCompileMemberOffset(SVMVMCBCTRL, LbrVirt, 0xb8);
814AssertCompileMemberOffset(SVMVMCBCTRL, u32VmcbCleanBits, 0xc0);
815AssertCompileMemberOffset(SVMVMCBCTRL, u64NextRIP, 0xc8);
816AssertCompileMemberOffset(SVMVMCBCTRL, cbInstrFetched, 0xd0);
817AssertCompileMemberOffset(SVMVMCBCTRL, abInstr, 0xd1);
818AssertCompileMemberOffset(SVMVMCBCTRL, AvicBackingPagePtr, 0xe0);
819AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved3, 0xe8);
820AssertCompileMemberOffset(SVMVMCBCTRL, AvicLogicalTablePtr, 0xf0);
821AssertCompileMemberOffset(SVMVMCBCTRL, AvicPhysicalTablePtr, 0xf8);
822
823/**
824 * SVM VMCB state save area.
825 */
826#pragma pack(1)
827typedef struct
828{
829 /** Offset 0x400 - Guest ES register + hidden parts. */
830 SVMSELREG ES;
831 /** Offset 0x410 - Guest CS register + hidden parts. */
832 SVMSELREG CS;
833 /** Offset 0x420 - Guest SS register + hidden parts. */
834 SVMSELREG SS;
835 /** Offset 0x430 - Guest DS register + hidden parts. */
836 SVMSELREG DS;
837 /** Offset 0x440 - Guest FS register + hidden parts. */
838 SVMSELREG FS;
839 /** Offset 0x450 - Guest GS register + hidden parts. */
840 SVMSELREG GS;
841 /** Offset 0x460 - Guest GDTR register. */
842 SVMGDTR GDTR;
843 /** Offset 0x470 - Guest LDTR register + hidden parts. */
844 SVMSELREG LDTR;
845 /** Offset 0x480 - Guest IDTR register. */
846 SVMIDTR IDTR;
847 /** Offset 0x490 - Guest TR register + hidden parts. */
848 SVMSELREG TR;
849 /** Offset 0x4A0-0x4CA - Reserved. */
850 uint8_t u8Reserved4[0x4CB - 0x4A0];
851 /** Offset 0x4CB - CPL. */
852 uint8_t u8CPL;
853 /** Offset 0x4CC-0x4CF - Reserved. */
854 uint8_t u8Reserved5[0x4D0 - 0x4CC];
855 /** Offset 0x4D0 - EFER. */
856 uint64_t u64EFER;
857 /** Offset 0x4D8-0x547 - Reserved. */
858 uint8_t u8Reserved6[0x548 - 0x4D8];
859 /** Offset 0x548 - CR4. */
860 uint64_t u64CR4;
861 /** Offset 0x550 - CR3. */
862 uint64_t u64CR3;
863 /** Offset 0x558 - CR0. */
864 uint64_t u64CR0;
865 /** Offset 0x560 - DR7. */
866 uint64_t u64DR7;
867 /** Offset 0x568 - DR6. */
868 uint64_t u64DR6;
869 /** Offset 0x570 - RFLAGS. */
870 uint64_t u64RFlags;
871 /** Offset 0x578 - RIP. */
872 uint64_t u64RIP;
873 /** Offset 0x580-0x5D7 - Reserved. */
874 uint8_t u8Reserved7[0x5D8 - 0x580];
875 /** Offset 0x5D8 - RSP. */
876 uint64_t u64RSP;
877 /** Offset 0x5E0-0x5F7 - Reserved. */
878 uint8_t u8Reserved8[0x5F8 - 0x5E0];
879 /** Offset 0x5F8 - RAX. */
880 uint64_t u64RAX;
881 /** Offset 0x600 - STAR. */
882 uint64_t u64STAR;
883 /** Offset 0x608 - LSTAR. */
884 uint64_t u64LSTAR;
885 /** Offset 0x610 - CSTAR. */
886 uint64_t u64CSTAR;
887 /** Offset 0x618 - SFMASK. */
888 uint64_t u64SFMASK;
889 /** Offset 0x620 - KernelGSBase. */
890 uint64_t u64KernelGSBase;
891 /** Offset 0x628 - SYSENTER_CS. */
892 uint64_t u64SysEnterCS;
893 /** Offset 0x630 - SYSENTER_ESP. */
894 uint64_t u64SysEnterESP;
895 /** Offset 0x638 - SYSENTER_EIP. */
896 uint64_t u64SysEnterEIP;
897 /** Offset 0x640 - CR2. */
898 uint64_t u64CR2;
899 /** Offset 0x648-0x667 - Reserved. */
900 uint8_t u8Reserved9[0x668 - 0x648];
901 /** Offset 0x668 - G_PAT. */
902 uint64_t u64GPAT;
903 /** Offset 0x670 - DBGCTL. */
904 uint64_t u64DBGCTL;
905 /** Offset 0x678 - BR_FROM. */
906 uint64_t u64BR_FROM;
907 /** Offset 0x680 - BR_TO. */
908 uint64_t u64BR_TO;
909 /** Offset 0x688 - LASTEXCPFROM. */
910 uint64_t u64LASTEXCPFROM;
911 /** Offset 0x690 - LASTEXCPTO. */
912 uint64_t u64LASTEXCPTO;
913} SVMVMCBSTATESAVE;
914#pragma pack()
915/** Pointer to the SVMVMCBSTATESAVE structure. */
916typedef SVMVMCBSTATESAVE *PSVMVMCBSTATESAVE;
917/** Pointer to a const SVMVMCBSTATESAVE structure. */
918typedef const SVMVMCBSTATESAVE *PCSVMVMCBSTATESAVE;
919AssertCompileSize(SVMVMCBSTATESAVE, 0x298);
920AssertCompileMemberOffset(SVMVMCBSTATESAVE, ES, 0x400 - 0x400);
921AssertCompileMemberOffset(SVMVMCBSTATESAVE, CS, 0x410 - 0x400);
922AssertCompileMemberOffset(SVMVMCBSTATESAVE, SS, 0x420 - 0x400);
923AssertCompileMemberOffset(SVMVMCBSTATESAVE, DS, 0x430 - 0x400);
924AssertCompileMemberOffset(SVMVMCBSTATESAVE, FS, 0x440 - 0x400);
925AssertCompileMemberOffset(SVMVMCBSTATESAVE, GS, 0x450 - 0x400);
926AssertCompileMemberOffset(SVMVMCBSTATESAVE, GDTR, 0x460 - 0x400);
927AssertCompileMemberOffset(SVMVMCBSTATESAVE, LDTR, 0x470 - 0x400);
928AssertCompileMemberOffset(SVMVMCBSTATESAVE, IDTR, 0x480 - 0x400);
929AssertCompileMemberOffset(SVMVMCBSTATESAVE, TR, 0x490 - 0x400);
930AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved4, 0x4a0 - 0x400);
931AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8CPL, 0x4cb - 0x400);
932AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved5, 0x4cc - 0x400);
933AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64EFER, 0x4d0 - 0x400);
934AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved6, 0x4d8 - 0x400);
935AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR4, 0x548 - 0x400);
936AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR3, 0x550 - 0x400);
937AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR0, 0x558 - 0x400);
938AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR7, 0x560 - 0x400);
939AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR6, 0x568 - 0x400);
940AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RFlags, 0x570 - 0x400);
941AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RIP, 0x578 - 0x400);
942AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved7, 0x580 - 0x400);
943AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RSP, 0x5d8 - 0x400);
944AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved8, 0x5e0 - 0x400);
945AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RAX, 0x5f8 - 0x400);
946AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64STAR, 0x600 - 0x400);
947AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LSTAR, 0x608 - 0x400);
948AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CSTAR, 0x610 - 0x400);
949AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SFMASK, 0x618 - 0x400);
950AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64KernelGSBase, 0x620 - 0x400);
951AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterCS, 0x628 - 0x400);
952AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterESP, 0x630 - 0x400);
953AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterEIP, 0x638 - 0x400);
954AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR2, 0x640 - 0x400);
955AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved9, 0x648 - 0x400);
956AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64GPAT, 0x668 - 0x400);
957AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DBGCTL, 0x670 - 0x400);
958AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_FROM, 0x678 - 0x400);
959AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_TO, 0x680 - 0x400);
960AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPFROM, 0x688 - 0x400);
961AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPTO, 0x690 - 0x400);
962
963/**
964 * SVM VM Control Block. (VMCB)
965 */
966#pragma pack(1)
967typedef struct SVMVMCB
968{
969 /** Offset 0x00 - Control area. */
970 SVMVMCBCTRL ctrl;
971 /** Offset 0x100-0x3FF - Reserved. */
972 uint8_t u8Reserved3[0x400 - 0x100];
973 /** Offset 0x400 - State save area. */
974 SVMVMCBSTATESAVE guest;
975 /** Offset 0x698-0xFFF- Reserved. */
976 uint8_t u8Reserved10[0x1000 - 0x698];
977} SVMVMCB;
978#pragma pack()
979/** Pointer to the SVMVMCB structure. */
980typedef SVMVMCB *PSVMVMCB;
981/** Pointer to a const SVMVMCB structure. */
982typedef const SVMVMCB *PCSVMVMCB;
983AssertCompileMemberOffset(SVMVMCB, ctrl, 0x00);
984AssertCompileMemberOffset(SVMVMCB, u8Reserved3, 0x100);
985AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
986AssertCompileMemberOffset(SVMVMCB, u8Reserved10, 0x698);
987AssertCompileSize(SVMVMCB, 0x1000);
988
989/** SVM nested-guest VMCB cache.
990 *
991 * A state structure for holding information across AMD-V VMRUN/\#VMEXIT
992 * operation during execution of the nested-guest, restored on \#VMEXIT.
993 */
994#pragma pack(1)
995typedef struct SVMNESTEDVMCBCACHE
996{
997 /** @name Nested-guest VMCB controls.
998 * @{ */
999 /** Cache of CRX read intercepts. */
1000 uint16_t u16InterceptRdCRx;
1001 /** Cache of CRX write intercepts. */
1002 uint16_t u16InterceptWrCRx;
1003 /** Cache of DRX read intercepts. */
1004 uint16_t u16InterceptRdDRx;
1005 /** Cache of DRX write intercepts. */
1006 uint16_t u16InterceptWrDRx;
1007 /** Cache of exception intercepts. */
1008 uint32_t u32InterceptXcpt;
1009 /** Alignment. */
1010 uint32_t u32Padding0;
1011
1012 /** Cache of control intercepts. */
1013 uint64_t u64InterceptCtrl;
1014 /** Cache of IOPM nested-guest physical address. */
1015 uint64_t u64IOPMPhysAddr;
1016 /** Cache of MSRPM nested-guest physical address. */
1017 uint64_t u64MSRPMPhysAddr;
1018 /** Cache of the TSC offset. */
1019 uint64_t u64TSCOffset;
1020 /** Cache of the VMCB clean bits. */
1021 uint32_t u32VmcbCleanBits;
1022 uint32_t u32Reserved0;
1023 /** Cache of the TLB control. */
1024 SVMTLBCTRL TLBCtrl;
1025 /** Cache of the nested-paging control. */
1026 uint32_t u1NestedPaging : 1;
1027 /** Cache of the LBR virtualization control. */
1028 uint32_t u1LbrVirt : 1;
1029 uint32_t u31Reserved0 : 30;
1030 uint32_t u32Reserved1;
1031 /** @} */
1032
1033 /** @name Nested-guest VMCB guest state.
1034 * @{ */
1035 /** Cache of CR0. */
1036 uint64_t u64CR0;
1037 /** Cache of CR3. */
1038 uint64_t u64CR3;
1039 /** Cache of CR4. */
1040 uint64_t u64CR4;
1041 /** Cache of EFER. */
1042 uint64_t u64EFER;
1043 /** Cache of DBGCTL. */
1044 uint64_t u64DBGCTL;
1045 /** @} */
1046
1047 /** @name Other miscellaneous state.
1048 * @{ */
1049 /** Cache of V_INTR_MASKING bit. */
1050 bool fVIntrMasking;
1051 /** Alignment. */
1052 bool afPadding0[7];
1053 /** @} */
1054} SVMNESTEDVMCBCACHE;
1055#pragma pack()
1056/** Pointer to the SVMNESTEDVMCBCACHE structure. */
1057typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
1058/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
1059typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
1060AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
1061
1062#ifdef IN_RING0
1063VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1064#endif /* IN_RING0 */
1065
1066/**
1067 * Segment attribute conversion between CPU and AMD-V VMCB format.
1068 *
1069 * The CPU format of the segment attribute is described in X86DESCATTRBITS
1070 * which is 16-bits (i.e. includes 4 bits of the segment limit).
1071 *
1072 * The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
1073 * only the attribute bits and nothing else). Upper 4-bits are unused.
1074 */
1075#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0xf000) >> 4) )
1076#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0x0f00) << 4) )
1077
1078/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1079 * Copies the specified segment register to a VMCB from a virtual CPU context.
1080 *
1081 * @param a_pCtx The virtual-CPU context.
1082 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1083 * @param a_REG The segment register in the VMCB state-save
1084 * struct (ES/CS/SS/DS).
1085 * @param a_reg The segment register in the virtual CPU struct
1086 * (es/cs/ss/ds).
1087 */
1088#define HMSVM_SEG_REG_COPY_TO_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1089 do \
1090 { \
1091 Assert((a_pCtx)->a_reg.fFlags & CPUMSELREG_FLAGS_VALID); \
1092 Assert((a_pCtx)->a_reg.ValidSel == (a_pCtx)->a_reg.Sel); \
1093 (a_pVmcbStateSave)->a_REG.u16Sel = (a_pCtx)->a_reg.Sel; \
1094 (a_pVmcbStateSave)->a_REG.u32Limit = (a_pCtx)->a_reg.u32Limit; \
1095 (a_pVmcbStateSave)->a_REG.u64Base = (a_pCtx)->a_reg.u64Base; \
1096 (a_pVmcbStateSave)->a_REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR((a_pCtx)->a_reg.Attr.u); \
1097 } while (0)
1098
1099/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1100 * Copies the specified segment register from the VMCB to a virtual CPU
1101 * context.
1102 *
1103 * @param a_pCtx The virtual-CPU context.
1104 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1105 * @param a_REG The segment register in the VMCB state-save
1106 * struct (ES/CS/SS/DS).
1107 * @param a_reg The segment register in the virtual CPU struct
1108 * (es/ds/ss/ds).
1109 */
1110#define HMSVM_SEG_REG_COPY_FROM_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1111 do \
1112 { \
1113 (a_pCtx)->a_reg.Sel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1114 (a_pCtx)->a_reg.ValidSel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1115 (a_pCtx)->a_reg.fFlags = CPUMSELREG_FLAGS_VALID; \
1116 (a_pCtx)->a_reg.u32Limit = (a_pVmcbStateSave)->a_REG.u32Limit; \
1117 (a_pCtx)->a_reg.u64Base = (a_pVmcbStateSave)->a_REG.u64Base; \
1118 (a_pCtx)->a_reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR((a_pVmcbStateSave)->a_REG.u16Attr); \
1119 } while (0)
1120
1121VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept);
1122VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr);
1123VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr);
1124VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr);
1125VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr);
1126VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector);
1127VMM_INT_DECL(bool) HMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx);
1128
1129/** @} */
1130
1131#endif
1132
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