VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 76399

Last change on this file since 76399 was 76397, checked in by vboxsync, 6 years ago

VBox/vmm/hm_svm.h,hm_vmx.h: Try avoid including VBox/err.h in widely used headers, so split out the inline stuff from hm_vmx.h into hmvmxinline.h. bugref:9344
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1/** @file
2 * HM - SVM (AMD-V) Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2017 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_svm_h
27#define ___VBox_vmm_svm_h
28
29#include <VBox/types.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32
33#ifdef RT_OS_SOLARIS
34# undef ES
35# undef CS
36# undef DS
37# undef SS
38# undef FS
39# undef GS
40#endif
41
42/** @defgroup grp_hm_svm SVM (AMD-V) Types and Definitions
43 * @ingroup grp_hm
44 * @{
45 */
46
47/** @name SVM generic / convenient defines.
48 * @{
49 */
50/** Number of pages required for the VMCB. */
51#define SVM_VMCB_PAGES 1
52/** Number of pages required for the MSR permission bitmap. */
53#define SVM_MSRPM_PAGES 2
54/** Number of pages required for the IO permission bitmap. */
55#define SVM_IOPM_PAGES 3
56/** @} */
57
58/*
59 * Ugly!
60 * When compiling the recompiler, its own svm.h defines clash with
61 * the following defines. Avoid just the duplicates here as we still
62 * require other definitions and structures in this header.
63 */
64#ifndef IN_REM_R3
65/** @name SVM_EXIT_XXX - SVM Basic Exit Reasons.
66 * @{
67 */
68/** Invalid guest state in VMCB. */
69# define SVM_EXIT_INVALID (uint64_t)(-1)
70/** Read from CR0-CR15. */
71# define SVM_EXIT_READ_CR0 0x0
72# define SVM_EXIT_READ_CR1 0x1
73# define SVM_EXIT_READ_CR2 0x2
74# define SVM_EXIT_READ_CR3 0x3
75# define SVM_EXIT_READ_CR4 0x4
76# define SVM_EXIT_READ_CR5 0x5
77# define SVM_EXIT_READ_CR6 0x6
78# define SVM_EXIT_READ_CR7 0x7
79# define SVM_EXIT_READ_CR8 0x8
80# define SVM_EXIT_READ_CR9 0x9
81# define SVM_EXIT_READ_CR10 0xa
82# define SVM_EXIT_READ_CR11 0xb
83# define SVM_EXIT_READ_CR12 0xc
84# define SVM_EXIT_READ_CR13 0xd
85# define SVM_EXIT_READ_CR14 0xe
86# define SVM_EXIT_READ_CR15 0xf
87/** Writes to CR0-CR15. */
88# define SVM_EXIT_WRITE_CR0 0x10
89# define SVM_EXIT_WRITE_CR1 0x11
90# define SVM_EXIT_WRITE_CR2 0x12
91# define SVM_EXIT_WRITE_CR3 0x13
92# define SVM_EXIT_WRITE_CR4 0x14
93# define SVM_EXIT_WRITE_CR5 0x15
94# define SVM_EXIT_WRITE_CR6 0x16
95# define SVM_EXIT_WRITE_CR7 0x17
96# define SVM_EXIT_WRITE_CR8 0x18
97# define SVM_EXIT_WRITE_CR9 0x19
98# define SVM_EXIT_WRITE_CR10 0x1a
99# define SVM_EXIT_WRITE_CR11 0x1b
100# define SVM_EXIT_WRITE_CR12 0x1c
101# define SVM_EXIT_WRITE_CR13 0x1d
102# define SVM_EXIT_WRITE_CR14 0x1e
103# define SVM_EXIT_WRITE_CR15 0x1f
104/** Read from DR0-DR15. */
105# define SVM_EXIT_READ_DR0 0x20
106# define SVM_EXIT_READ_DR1 0x21
107# define SVM_EXIT_READ_DR2 0x22
108# define SVM_EXIT_READ_DR3 0x23
109# define SVM_EXIT_READ_DR4 0x24
110# define SVM_EXIT_READ_DR5 0x25
111# define SVM_EXIT_READ_DR6 0x26
112# define SVM_EXIT_READ_DR7 0x27
113# define SVM_EXIT_READ_DR8 0x28
114# define SVM_EXIT_READ_DR9 0x29
115# define SVM_EXIT_READ_DR10 0x2a
116# define SVM_EXIT_READ_DR11 0x2b
117# define SVM_EXIT_READ_DR12 0x2c
118# define SVM_EXIT_READ_DR13 0x2d
119# define SVM_EXIT_READ_DR14 0x2e
120# define SVM_EXIT_READ_DR15 0x2f
121/** Writes to DR0-DR15. */
122# define SVM_EXIT_WRITE_DR0 0x30
123# define SVM_EXIT_WRITE_DR1 0x31
124# define SVM_EXIT_WRITE_DR2 0x32
125# define SVM_EXIT_WRITE_DR3 0x33
126# define SVM_EXIT_WRITE_DR4 0x34
127# define SVM_EXIT_WRITE_DR5 0x35
128# define SVM_EXIT_WRITE_DR6 0x36
129# define SVM_EXIT_WRITE_DR7 0x37
130# define SVM_EXIT_WRITE_DR8 0x38
131# define SVM_EXIT_WRITE_DR9 0x39
132# define SVM_EXIT_WRITE_DR10 0x3a
133# define SVM_EXIT_WRITE_DR11 0x3b
134# define SVM_EXIT_WRITE_DR12 0x3c
135# define SVM_EXIT_WRITE_DR13 0x3d
136# define SVM_EXIT_WRITE_DR14 0x3e
137# define SVM_EXIT_WRITE_DR15 0x3f
138/* Exception 0-31. */
139# define SVM_EXIT_XCPT_0 0x40
140# define SVM_EXIT_XCPT_1 0x41
141# define SVM_EXIT_XCPT_2 0x42
142# define SVM_EXIT_XCPT_3 0x43
143# define SVM_EXIT_XCPT_4 0x44
144# define SVM_EXIT_XCPT_5 0x45
145# define SVM_EXIT_XCPT_6 0x46
146# define SVM_EXIT_XCPT_7 0x47
147# define SVM_EXIT_XCPT_8 0x48
148# define SVM_EXIT_XCPT_9 0x49
149# define SVM_EXIT_XCPT_10 0x4a
150# define SVM_EXIT_XCPT_11 0x4b
151# define SVM_EXIT_XCPT_12 0x4c
152# define SVM_EXIT_XCPT_13 0x4d
153# define SVM_EXIT_XCPT_14 0x4e
154# define SVM_EXIT_XCPT_15 0x4f
155# define SVM_EXIT_XCPT_16 0x50
156# define SVM_EXIT_XCPT_17 0x51
157# define SVM_EXIT_XCPT_18 0x52
158# define SVM_EXIT_XCPT_19 0x53
159# define SVM_EXIT_XCPT_20 0x54
160# define SVM_EXIT_XCPT_21 0x55
161# define SVM_EXIT_XCPT_22 0x56
162# define SVM_EXIT_XCPT_23 0x57
163# define SVM_EXIT_XCPT_24 0x58
164# define SVM_EXIT_XCPT_25 0x59
165# define SVM_EXIT_XCPT_26 0x5a
166# define SVM_EXIT_XCPT_27 0x5b
167# define SVM_EXIT_XCPT_28 0x5c
168# define SVM_EXIT_XCPT_29 0x5d
169# define SVM_EXIT_XCPT_30 0x5e
170# define SVM_EXIT_XCPT_31 0x5f
171/* Exception (more readable) */
172# define SVM_EXIT_XCPT_DE SVM_EXIT_XCPT_0
173# define SVM_EXIT_XCPT_DB SVM_EXIT_XCPT_1
174# define SVM_EXIT_XCPT_NMI SVM_EXIT_XCPT_2
175# define SVM_EXIT_XCPT_BP SVM_EXIT_XCPT_3
176# define SVM_EXIT_XCPT_OF SVM_EXIT_XCPT_4
177# define SVM_EXIT_XCPT_BR SVM_EXIT_XCPT_5
178# define SVM_EXIT_XCPT_UD SVM_EXIT_XCPT_6
179# define SVM_EXIT_XCPT_NM SVM_EXIT_XCPT_7
180# define SVM_EXIT_XCPT_DF SVM_EXIT_XCPT_8
181# define SVM_EXIT_XCPT_CO_SEG_OVERRUN SVM_EXIT_XCPT_9
182# define SVM_EXIT_XCPT_TS SVM_EXIT_XCPT_10
183# define SVM_EXIT_XCPT_NP SVM_EXIT_XCPT_11
184# define SVM_EXIT_XCPT_SS SVM_EXIT_XCPT_12
185# define SVM_EXIT_XCPT_GP SVM_EXIT_XCPT_13
186# define SVM_EXIT_XCPT_PF SVM_EXIT_XCPT_14
187# define SVM_EXIT_XCPT_MF SVM_EXIT_XCPT_16
188# define SVM_EXIT_XCPT_AC SVM_EXIT_XCPT_17
189# define SVM_EXIT_XCPT_MC SVM_EXIT_XCPT_18
190# define SVM_EXIT_XCPT_XF SVM_EXIT_XCPT_19
191# define SVM_EXIT_XCPT_VE SVM_EXIT_XCPT_20
192# define SVM_EXIT_XCPT_SX SVM_EXIT_XCPT_30
193/** Physical maskable interrupt. */
194# define SVM_EXIT_INTR 0x60
195/** Non-maskable interrupt. */
196# define SVM_EXIT_NMI 0x61
197/** System Management interrupt. */
198# define SVM_EXIT_SMI 0x62
199/** Physical INIT signal. */
200# define SVM_EXIT_INIT 0x63
201/** Virtual interrupt. */
202# define SVM_EXIT_VINTR 0x64
203/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
204# define SVM_EXIT_CR0_SEL_WRITE 0x65
205/** IDTR read. */
206# define SVM_EXIT_IDTR_READ 0x66
207/** GDTR read. */
208# define SVM_EXIT_GDTR_READ 0x67
209/** LDTR read. */
210# define SVM_EXIT_LDTR_READ 0x68
211/** TR read. */
212# define SVM_EXIT_TR_READ 0x69
213/** IDTR write. */
214# define SVM_EXIT_IDTR_WRITE 0x6a
215/** GDTR write. */
216# define SVM_EXIT_GDTR_WRITE 0x6b
217/** LDTR write. */
218# define SVM_EXIT_LDTR_WRITE 0x6c
219/** TR write. */
220# define SVM_EXIT_TR_WRITE 0x6d
221/** RDTSC instruction. */
222# define SVM_EXIT_RDTSC 0x6e
223/** RDPMC instruction. */
224# define SVM_EXIT_RDPMC 0x6f
225/** PUSHF instruction. */
226# define SVM_EXIT_PUSHF 0x70
227/** POPF instruction. */
228# define SVM_EXIT_POPF 0x71
229/** CPUID instruction. */
230# define SVM_EXIT_CPUID 0x72
231/** RSM instruction. */
232# define SVM_EXIT_RSM 0x73
233/** IRET instruction. */
234# define SVM_EXIT_IRET 0x74
235/** software interrupt (INTn instructions). */
236# define SVM_EXIT_SWINT 0x75
237/** INVD instruction. */
238# define SVM_EXIT_INVD 0x76
239/** PAUSE instruction. */
240# define SVM_EXIT_PAUSE 0x77
241/** HLT instruction. */
242# define SVM_EXIT_HLT 0x78
243/** INVLPG instructions. */
244# define SVM_EXIT_INVLPG 0x79
245/** INVLPGA instruction. */
246# define SVM_EXIT_INVLPGA 0x7a
247/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
248# define SVM_EXIT_IOIO 0x7b
249/** RDMSR or WRMSR access to protected MSR. */
250# define SVM_EXIT_MSR 0x7c
251/** task switch. */
252# define SVM_EXIT_TASK_SWITCH 0x7d
253/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
254# define SVM_EXIT_FERR_FREEZE 0x7e
255/** Shutdown. */
256# define SVM_EXIT_SHUTDOWN 0x7f
257/** VMRUN instruction. */
258# define SVM_EXIT_VMRUN 0x80
259/** VMMCALL instruction. */
260# define SVM_EXIT_VMMCALL 0x81
261/** VMLOAD instruction. */
262# define SVM_EXIT_VMLOAD 0x82
263/** VMSAVE instruction. */
264# define SVM_EXIT_VMSAVE 0x83
265/** STGI instruction. */
266# define SVM_EXIT_STGI 0x84
267/** CLGI instruction. */
268# define SVM_EXIT_CLGI 0x85
269/** SKINIT instruction. */
270# define SVM_EXIT_SKINIT 0x86
271/** RDTSCP instruction. */
272# define SVM_EXIT_RDTSCP 0x87
273/** ICEBP instruction. */
274# define SVM_EXIT_ICEBP 0x88
275/** WBINVD instruction. */
276# define SVM_EXIT_WBINVD 0x89
277/** MONITOR instruction. */
278# define SVM_EXIT_MONITOR 0x8a
279/** MWAIT instruction. */
280# define SVM_EXIT_MWAIT 0x8b
281/** MWAIT instruction, when armed. */
282# define SVM_EXIT_MWAIT_ARMED 0x8c
283/** XSETBV instruction. */
284# define SVM_EXIT_XSETBV 0x8d
285/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
286# define SVM_EXIT_NPF 0x400
287/** AVIC: Virtual IPI delivery not completed. */
288# define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
289/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
290 * hardware. */
291# define SVM_EXIT_AVIC_NOACCEL 0x402
292/** The maximum possible exit value. */
293# define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
294/** @} */
295#endif /* !IN_REM_R3*/
296
297
298/** @name SVMVMCB.u64ExitInfo2 for task switches
299 * @{
300 */
301/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
302#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
303/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
304#define SVM_EXIT2_TASK_SWITCH_JUMP RT_BIT_64(38)
305/** Set to 1 if the task switch has an error code; else cleared to 0. */
306#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
307/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
308#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
309/** @} */
310
311/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
312 * @{
313 */
314/** The access was a read MSR. */
315#define SVM_EXIT1_MSR_READ 0x0
316/** The access was a write MSR. */
317#define SVM_EXIT1_MSR_WRITE 0x1
318/** @} */
319
320/** @name SVMVMCB.u64ExitInfo1 for Mov CRx accesses.
321 * @{
322 */
323/** The mask of whether the access was via a Mov CRx instruction. */
324#define SVM_EXIT1_MOV_CRX_MASK RT_BIT_64(63)
325/** The mask for the GPR number of the Mov CRx instruction. */
326#define SVM_EXIT1_MOV_CRX_GPR_NUMBER 0xf
327/** @} */
328
329/** @name SVMVMCB.u64ExitInfo1 for Mov DRx accesses.
330 * @{
331 */
332/** The mask for the GPR number of the Mov DRx instruction. */
333#define SVM_EXIT1_MOV_DRX_GPR_NUMBER 0xf
334/** @} */
335
336/** @name SVMVMCB.ctrl.u64InterceptCtrl
337 * @{
338 */
339/** Intercept INTR (physical maskable interrupt). */
340#define SVM_CTRL_INTERCEPT_INTR RT_BIT_64(0)
341/** Intercept NMI. */
342#define SVM_CTRL_INTERCEPT_NMI RT_BIT_64(1)
343/** Intercept SMI. */
344#define SVM_CTRL_INTERCEPT_SMI RT_BIT_64(2)
345/** Intercept INIT. */
346#define SVM_CTRL_INTERCEPT_INIT RT_BIT_64(3)
347/** Intercept VINTR (virtual maskable interrupt). */
348#define SVM_CTRL_INTERCEPT_VINTR RT_BIT_64(4)
349/** Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
350#define SVM_CTRL_INTERCEPT_CR0_SEL_WRITE RT_BIT_64(5)
351/** Intercept reads of IDTR. */
352#define SVM_CTRL_INTERCEPT_IDTR_READS RT_BIT_64(6)
353/** Intercept reads of GDTR. */
354#define SVM_CTRL_INTERCEPT_GDTR_READS RT_BIT_64(7)
355/** Intercept reads of LDTR. */
356#define SVM_CTRL_INTERCEPT_LDTR_READS RT_BIT_64(8)
357/** Intercept reads of TR. */
358#define SVM_CTRL_INTERCEPT_TR_READS RT_BIT_64(9)
359/** Intercept writes of IDTR. */
360#define SVM_CTRL_INTERCEPT_IDTR_WRITES RT_BIT_64(10)
361/** Intercept writes of GDTR. */
362#define SVM_CTRL_INTERCEPT_GDTR_WRITES RT_BIT_64(11)
363/** Intercept writes of LDTR. */
364#define SVM_CTRL_INTERCEPT_LDTR_WRITES RT_BIT_64(12)
365/** Intercept writes of TR. */
366#define SVM_CTRL_INTERCEPT_TR_WRITES RT_BIT_64(13)
367/** Intercept RDTSC instruction. */
368#define SVM_CTRL_INTERCEPT_RDTSC RT_BIT_64(14)
369/** Intercept RDPMC instruction. */
370#define SVM_CTRL_INTERCEPT_RDPMC RT_BIT_64(15)
371/** Intercept PUSHF instruction. */
372#define SVM_CTRL_INTERCEPT_PUSHF RT_BIT_64(16)
373/** Intercept POPF instruction. */
374#define SVM_CTRL_INTERCEPT_POPF RT_BIT_64(17)
375/** Intercept CPUID instruction. */
376#define SVM_CTRL_INTERCEPT_CPUID RT_BIT_64(18)
377/** Intercept RSM instruction. */
378#define SVM_CTRL_INTERCEPT_RSM RT_BIT_64(19)
379/** Intercept IRET instruction. */
380#define SVM_CTRL_INTERCEPT_IRET RT_BIT_64(20)
381/** Intercept INTn instruction. */
382#define SVM_CTRL_INTERCEPT_INTN RT_BIT_64(21)
383/** Intercept INVD instruction. */
384#define SVM_CTRL_INTERCEPT_INVD RT_BIT_64(22)
385/** Intercept PAUSE instruction. */
386#define SVM_CTRL_INTERCEPT_PAUSE RT_BIT_64(23)
387/** Intercept HLT instruction. */
388#define SVM_CTRL_INTERCEPT_HLT RT_BIT_64(24)
389/** Intercept INVLPG instruction. */
390#define SVM_CTRL_INTERCEPT_INVLPG RT_BIT_64(25)
391/** Intercept INVLPGA instruction. */
392#define SVM_CTRL_INTERCEPT_INVLPGA RT_BIT_64(26)
393/** IOIO_PROT Intercept IN/OUT accesses to selected ports. */
394#define SVM_CTRL_INTERCEPT_IOIO_PROT RT_BIT_64(27)
395/** MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
396#define SVM_CTRL_INTERCEPT_MSR_PROT RT_BIT_64(28)
397/** Intercept task switches. */
398#define SVM_CTRL_INTERCEPT_TASK_SWITCH RT_BIT_64(29)
399/** FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
400#define SVM_CTRL_INTERCEPT_FERR_FREEZE RT_BIT_64(30)
401/** Intercept shutdown events. */
402#define SVM_CTRL_INTERCEPT_SHUTDOWN RT_BIT_64(31)
403/** Intercept VMRUN instruction. */
404#define SVM_CTRL_INTERCEPT_VMRUN RT_BIT_64(32 + 0)
405/** Intercept VMMCALL instruction. */
406#define SVM_CTRL_INTERCEPT_VMMCALL RT_BIT_64(32 + 1)
407/** Intercept VMLOAD instruction. */
408#define SVM_CTRL_INTERCEPT_VMLOAD RT_BIT_64(32 + 2)
409/** Intercept VMSAVE instruction. */
410#define SVM_CTRL_INTERCEPT_VMSAVE RT_BIT_64(32 + 3)
411/** Intercept STGI instruction. */
412#define SVM_CTRL_INTERCEPT_STGI RT_BIT_64(32 + 4)
413/** Intercept CLGI instruction. */
414#define SVM_CTRL_INTERCEPT_CLGI RT_BIT_64(32 + 5)
415/** Intercept SKINIT instruction. */
416#define SVM_CTRL_INTERCEPT_SKINIT RT_BIT_64(32 + 6)
417/** Intercept RDTSCP instruction. */
418#define SVM_CTRL_INTERCEPT_RDTSCP RT_BIT_64(32 + 7)
419/** Intercept ICEBP instruction. */
420#define SVM_CTRL_INTERCEPT_ICEBP RT_BIT_64(32 + 8)
421/** Intercept WBINVD instruction. */
422#define SVM_CTRL_INTERCEPT_WBINVD RT_BIT_64(32 + 9)
423/** Intercept MONITOR instruction. */
424#define SVM_CTRL_INTERCEPT_MONITOR RT_BIT_64(32 + 10)
425/** Intercept MWAIT instruction unconditionally. */
426#define SVM_CTRL_INTERCEPT_MWAIT RT_BIT_64(32 + 11)
427/** Intercept MWAIT instruction when armed. */
428#define SVM_CTRL_INTERCEPT_MWAIT_ARMED RT_BIT_64(32 + 12)
429/** Intercept XSETBV instruction. */
430#define SVM_CTRL_INTERCEPT_XSETBV RT_BIT_64(32 + 13)
431/* Bit 14 - Reserved, SBZ. */
432/** Intercept EFER writes after guest instruction finishes. */
433#define SVM_CTRL_INTERCEPT_EFER_WRITES_TRAP RT_BIT_64(32 + 15)
434/** Intercept CR0 writes after guest instruction finishes. */
435#define SVM_CTRL_INTERCEPT_CR0_WRITES_TRAP RT_BIT_64(32 + 16)
436/** Intercept CR0 writes after guest instruction finishes. */
437#define SVM_CTRL_INTERCEPT_CR1_WRITES_TRAP RT_BIT_64(32 + 17)
438/** Intercept CR0 writes after guest instruction finishes. */
439#define SVM_CTRL_INTERCEPT_CR2_WRITES_TRAP RT_BIT_64(32 + 18)
440/** Intercept CR0 writes after guest instruction finishes. */
441#define SVM_CTRL_INTERCEPT_CR3_WRITES_TRAP RT_BIT_64(32 + 19)
442/** Intercept CR0 writes after guest instruction finishes. */
443#define SVM_CTRL_INTERCEPT_CR4_WRITES_TRAP RT_BIT_64(32 + 20)
444/** Intercept CR0 writes after guest instruction finishes. */
445#define SVM_CTRL_INTERCEPT_CR5_WRITES_TRAP RT_BIT_64(32 + 21)
446/** Intercept CR0 writes after guest instruction finishes. */
447#define SVM_CTRL_INTERCEPT_CR6_WRITES_TRAP RT_BIT_64(32 + 22)
448/** Intercept CR0 writes after guest instruction finishes. */
449#define SVM_CTRL_INTERCEPT_CR7_WRITES_TRAP RT_BIT_64(32 + 23)
450/** Intercept CR0 writes after guest instruction finishes. */
451#define SVM_CTRL_INTERCEPT_CR8_WRITES_TRAP RT_BIT_64(32 + 24)
452/** Intercept CR0 writes after guest instruction finishes. */
453#define SVM_CTRL_INTERCEPT_CR9_WRITES_TRAP RT_BIT_64(32 + 25)
454/** Intercept CR0 writes after guest instruction finishes. */
455#define SVM_CTRL_INTERCEPT_CR10_WRITES_TRAP RT_BIT_64(32 + 26)
456/** Intercept CR0 writes after guest instruction finishes. */
457#define SVM_CTRL_INTERCEPT_CR11_WRITES_TRAP RT_BIT_64(32 + 27)
458/** Intercept CR0 writes after guest instruction finishes. */
459#define SVM_CTRL_INTERCEPT_CR12_WRITES_TRAP RT_BIT_64(32 + 28)
460/** Intercept CR0 writes after guest instruction finishes. */
461#define SVM_CTRL_INTERCEPT_CR13_WRITES_TRAP RT_BIT_64(32 + 29)
462/** Intercept CR0 writes after guest instruction finishes. */
463#define SVM_CTRL_INTERCEPT_CR14_WRITES_TRAP RT_BIT_64(32 + 30)
464/** Intercept CR0 writes after guest instruction finishes. */
465#define SVM_CTRL_INTERCEPT_CR15_WRITES_TRAP RT_BIT_64(32 + 31)
466/** @} */
467
468/** @name SVMINTCTRL.u3Type
469 * @{
470 */
471/** External or virtual interrupt. */
472#define SVM_EVENT_EXTERNAL_IRQ 0
473/** Non-maskable interrupt. */
474#define SVM_EVENT_NMI 2
475/** Exception; fault or trap. */
476#define SVM_EVENT_EXCEPTION 3
477/** Software interrupt. */
478#define SVM_EVENT_SOFTWARE_INT 4
479/** @} */
480
481/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
482 * @{
483 */
484/** Flush nothing. */
485#define SVM_TLB_FLUSH_NOTHING 0
486/** Flush entire TLB (host+guest entries) */
487#define SVM_TLB_FLUSH_ENTIRE 1
488/** Flush this guest's TLB entries (by ASID) */
489#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
490/** Flush this guest's non-global TLB entries (by ASID) */
491#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
492/** @} */
493
494/**
495 * SVM selector/segment register type.
496 */
497typedef struct
498{
499 uint16_t u16Sel;
500 uint16_t u16Attr;
501 uint32_t u32Limit;
502 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
503} SVMSELREG;
504AssertCompileSize(SVMSELREG, 16);
505/** Pointer to the SVMSELREG struct. */
506typedef SVMSELREG *PSVMSELREG;
507/** Pointer to a const SVMSELREG struct. */
508typedef const SVMSELREG *PCSVMSELREG;
509
510/**
511 * SVM GDTR/IDTR type.
512 */
513typedef struct
514{
515 uint16_t u16Reserved0;
516 uint16_t u16Reserved1;
517 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
518 uint64_t u64Base;
519} SVMXDTR;
520AssertCompileSize(SVMXDTR, 16);
521typedef SVMXDTR SVMIDTR;
522typedef SVMXDTR SVMGDTR;
523/** Pointer to the SVMXDTR struct. */
524typedef SVMXDTR *PSVMXDTR;
525/** Pointer to a const SVMXDTR struct. */
526typedef const SVMXDTR *PCSVMXDTR;
527
528/**
529 * SVM Event injection structure (EVENTINJ and EXITINTINFO).
530 */
531typedef union
532{
533 struct
534 {
535 uint32_t u8Vector : 8;
536 uint32_t u3Type : 3;
537 uint32_t u1ErrorCodeValid : 1;
538 uint32_t u19Reserved : 19;
539 uint32_t u1Valid : 1;
540 uint32_t u32ErrorCode : 32;
541 } n;
542 uint64_t u;
543} SVMEVENT;
544/** Pointer to the SVMEVENT union. */
545typedef SVMEVENT *PSVMEVENT;
546/** Pointer to a const SVMEVENT union. */
547typedef const SVMEVENT *PCSVMEVENT;
548
549/** Gets the event type given an SVMEVENT parameter. */
550#define SVM_EVENT_GET_TYPE(a_SvmEvent) (((a_SvmEvent) >> 8) & 7)
551
552/**
553 * SVM Interrupt control structure (Virtual Interrupt Control).
554 */
555typedef union
556{
557 struct
558 {
559 uint32_t u8VTPR : 8; /* V_TPR */
560 uint32_t u1VIrqPending : 1; /* V_IRQ */
561 uint32_t u1VGif : 1; /* VGIF */
562 uint32_t u6Reserved : 6;
563 uint32_t u4VIntrPrio : 4; /* V_INTR_PRIO */
564 uint32_t u1IgnoreTPR : 1; /* V_IGN_TPR */
565 uint32_t u3Reserved : 3;
566 uint32_t u1VIntrMasking : 1; /* V_INTR_MASKING */
567 uint32_t u1VGifEnable : 1; /* VGIF enable */
568 uint32_t u5Reserved : 5;
569 uint32_t u1AvicEnable : 1; /* AVIC enable */
570 uint32_t u8VIntrVector : 8; /* V_INTR_VECTOR */
571 uint32_t u24Reserved : 24;
572 } n;
573 uint64_t u;
574} SVMINTCTRL;
575/** Pointer to an SVMINTCTRL structure. */
576typedef SVMINTCTRL *PSVMINTCTRL;
577/** Pointer to a const SVMINTCTRL structure. */
578typedef const SVMINTCTRL *PCSVMINTCTRL;
579
580/**
581 * SVM TLB control structure.
582 */
583typedef union
584{
585 struct
586 {
587 uint32_t u32ASID : 32;
588 uint32_t u8TLBFlush : 8;
589 uint32_t u24Reserved : 24;
590 } n;
591 uint64_t u;
592} SVMTLBCTRL;
593
594/**
595 * SVM IOIO exit info. structure (EXITINFO1 for IOIO intercepts).
596 */
597typedef union
598{
599 struct
600 {
601 uint32_t u1Type : 1; /**< Bit 0: 0 = out, 1 = in */
602 uint32_t u1Reserved : 1; /**< Bit 1: Reserved */
603 uint32_t u1Str : 1; /**< Bit 2: String I/O (1) or not (0). */
604 uint32_t u1Rep : 1; /**< Bit 3: Repeat prefixed string I/O. */
605 uint32_t u1Op8 : 1; /**< Bit 4: 8-bit operand. */
606 uint32_t u1Op16 : 1; /**< Bit 5: 16-bit operand. */
607 uint32_t u1Op32 : 1; /**< Bit 6: 32-bit operand. */
608 uint32_t u1Addr16 : 1; /**< Bit 7: 16-bit address size. */
609 uint32_t u1Addr32 : 1; /**< Bit 8: 32-bit address size. */
610 uint32_t u1Addr64 : 1; /**< Bit 9: 64-bit address size. */
611 uint32_t u3Seg : 3; /**< Bits 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
612 uint32_t u3Reserved : 3;
613 uint32_t u16Port : 16; /**< Bits 31:16: Port number. */
614 } n;
615 uint32_t u;
616} SVMIOIOEXITINFO;
617/** Pointer to an SVM IOIO exit info. structure. */
618typedef SVMIOIOEXITINFO *PSVMIOIOEXITINFO;
619/** Pointer to a const SVM IOIO exit info. structure. */
620typedef const SVMIOIOEXITINFO *PCSVMIOIOEXITINFO;
621
622/** 8-bit IO transfer. */
623#define SVM_IOIO_8_BIT_OP RT_BIT_32(4)
624/** 16-bit IO transfer. */
625#define SVM_IOIO_16_BIT_OP RT_BIT_32(5)
626/** 32-bit IO transfer. */
627#define SVM_IOIO_32_BIT_OP RT_BIT_32(6)
628/** Number of bits to shift right to get the operand sizes. */
629#define SVM_IOIO_OP_SIZE_SHIFT 4
630/** Mask of all possible IO transfer sizes. */
631#define SVM_IOIO_OP_SIZE_MASK (SVM_IOIO_8_BIT_OP | SVM_IOIO_16_BIT_OP | SVM_IOIO_32_BIT_OP)
632/** 16-bit address for the IO buffer. */
633#define SVM_IOIO_16_BIT_ADDR RT_BIT_32(7)
634/** 32-bit address for the IO buffer. */
635#define SVM_IOIO_32_BIT_ADDR RT_BIT_32(8)
636/** 64-bit address for the IO buffer. */
637#define SVM_IOIO_64_BIT_ADDR RT_BIT_32(9)
638/** Number of bits to shift right to get the address sizes. */
639#define SVM_IOIO_ADDR_SIZE_SHIFT 7
640/** Mask of all the IO address sizes. */
641#define SVM_IOIO_ADDR_SIZE_MASK (SVM_IOIO_16_BIT_ADDR | SVM_IOIO_32_BIT_ADDR | SVM_IOIO_64_BIT_ADDR)
642/** Number of bits to shift right to get the IO port number. */
643#define SVM_IOIO_PORT_SHIFT 16
644/** IO write. */
645#define SVM_IOIO_WRITE 0
646/** IO read. */
647#define SVM_IOIO_READ 1
648/**
649 * SVM IOIO transfer type.
650 */
651typedef enum
652{
653 SVMIOIOTYPE_OUT = SVM_IOIO_WRITE,
654 SVMIOIOTYPE_IN = SVM_IOIO_READ
655} SVMIOIOTYPE;
656
657/**
658 * SVM AVIC.
659 */
660typedef union
661{
662 struct
663 {
664 uint64_t u12Reserved0 : 12;
665 uint64_t u40Addr : 40;
666 uint64_t u12Reserved1 : 12;
667 } n;
668 uint64_t u;
669} SVMAVIC;
670AssertCompileSize(SVMAVIC, 8);
671
672/**
673 * SVM AVIC PHYSICAL_TABLE pointer.
674 */
675typedef union
676{
677 struct
678 {
679 uint64_t u8LastGuestCoreId : 8;
680 uint64_t u4Reserved : 4;
681 uint64_t u40Addr : 40;
682 uint64_t u12Reserved : 12;
683 } n;
684 uint64_t u;
685} SVMAVICPHYS;
686AssertCompileSize(SVMAVICPHYS, 8);
687
688/**
689 * SVM Nested Paging struct.
690 */
691typedef union
692{
693 struct
694 {
695 uint32_t u1NestedPaging : 1;
696 uint32_t u1Sev : 1;
697 uint32_t u1SevEs : 1;
698 uint32_t u29Reserved : 29;
699 } n;
700 uint64_t u;
701} SVMNP;
702AssertCompileSize(SVMNP, 8);
703
704/**
705 * SVM Interrupt shadow struct.
706 */
707typedef union
708{
709 struct
710 {
711 uint32_t u1IntShadow : 1;
712 uint32_t u1GuestIntMask : 1;
713 uint32_t u30Reserved : 30;
714 } n;
715 uint64_t u;
716} SVMINTSHADOW;
717AssertCompileSize(SVMINTSHADOW, 8);
718
719/**
720 * SVM LBR virtualization struct.
721 */
722typedef union
723{
724 struct
725 {
726 uint32_t u1LbrVirt : 1;
727 uint32_t u1VirtVmsaveVmload : 1;
728 uint32_t u30Reserved : 30;
729 } n;
730 uint64_t u;
731} SVMLBRVIRT;
732AssertCompileSize(SVMLBRVIRT, 8);
733
734/** Maximum number of bytes in the Guest-instruction bytes field. */
735#define SVM_CTRL_GUEST_INSTR_BYTES_MAX 15
736
737/**
738 * SVM VMCB control area.
739 */
740#pragma pack(1)
741typedef struct
742{
743 /** Offset 0x00 - Intercept reads of CR0-CR15. */
744 uint16_t u16InterceptRdCRx;
745 /** Offset 0x02 - Intercept writes to CR0-CR15. */
746 uint16_t u16InterceptWrCRx;
747 /** Offset 0x04 - Intercept reads of DR0-DR15. */
748 uint16_t u16InterceptRdDRx;
749 /** Offset 0x06 - Intercept writes to DR0-DR15. */
750 uint16_t u16InterceptWrDRx;
751 /** Offset 0x08 - Intercept exception vectors 0-31. */
752 uint32_t u32InterceptXcpt;
753 /** Offset 0x0c - Intercept control. */
754 uint64_t u64InterceptCtrl;
755 /** Offset 0x14-0x3f - Reserved. */
756 uint8_t u8Reserved0[0x3c - 0x14];
757 /** Offset 0x3c - PAUSE filter threshold. */
758 uint16_t u16PauseFilterThreshold;
759 /** Offset 0x3e - PAUSE intercept filter count. */
760 uint16_t u16PauseFilterCount;
761 /** Offset 0x40 - Physical address of IOPM. */
762 uint64_t u64IOPMPhysAddr;
763 /** Offset 0x48 - Physical address of MSRPM. */
764 uint64_t u64MSRPMPhysAddr;
765 /** Offset 0x50 - TSC Offset. */
766 uint64_t u64TSCOffset;
767 /** Offset 0x58 - TLB control field. */
768 SVMTLBCTRL TLBCtrl;
769 /** Offset 0x60 - Interrupt control field. */
770 SVMINTCTRL IntCtrl;
771 /** Offset 0x68 - Interrupt shadow. */
772 SVMINTSHADOW IntShadow;
773 /** Offset 0x70 - Exit code. */
774 uint64_t u64ExitCode;
775 /** Offset 0x78 - Exit info 1. */
776 uint64_t u64ExitInfo1;
777 /** Offset 0x80 - Exit info 2. */
778 uint64_t u64ExitInfo2;
779 /** Offset 0x88 - Exit Interrupt info. */
780 SVMEVENT ExitIntInfo;
781 /** Offset 0x90 - Nested Paging control. */
782 SVMNP NestedPagingCtrl;
783 /** Offset 0x98 - AVIC APIC BAR. */
784 SVMAVIC AvicBar;
785 /** Offset 0xa0-0xa7 - Reserved. */
786 uint8_t u8Reserved1[0xa8 - 0xa0];
787 /** Offset 0xa8 - Event injection. */
788 SVMEVENT EventInject;
789 /** Offset 0xb0 - Host CR3 for nested paging. */
790 uint64_t u64NestedPagingCR3;
791 /** Offset 0xb8 - LBR Virtualization. */
792 SVMLBRVIRT LbrVirt;
793 /** Offset 0xc0 - VMCB Clean Bits. */
794 uint32_t u32VmcbCleanBits;
795 uint32_t u32Reserved0;
796 /** Offset 0xc8 - Next sequential instruction pointer. */
797 uint64_t u64NextRIP;
798 /** Offset 0xd0 - Number of bytes fetched. */
799 uint8_t cbInstrFetched;
800 /** Offset 0xd1 - Guest instruction bytes. */
801 uint8_t abInstr[SVM_CTRL_GUEST_INSTR_BYTES_MAX];
802 /** Offset 0xe0 - AVIC APIC_BACKING_PAGE pointer. */
803 SVMAVIC AvicBackingPagePtr;
804 /** Offset 0xe8-0xef - Reserved. */
805 uint8_t u8Reserved2[0xf0 - 0xe8];
806 /** Offset 0xf0 - AVIC LOGICAL_TABLE pointer. */
807 SVMAVIC AvicLogicalTablePtr;
808 /** Offset 0xf8 - AVIC PHYSICAL_TABLE pointer. */
809 SVMAVICPHYS AvicPhysicalTablePtr;
810} SVMVMCBCTRL;
811#pragma pack()
812/** Pointer to the SVMVMCBSTATESAVE structure. */
813typedef SVMVMCBCTRL *PSVMVMCBCTRL;
814/** Pointer to a const SVMVMCBSTATESAVE structure. */
815typedef const SVMVMCBCTRL *PCSVMVMCBCTRL;
816AssertCompileSize(SVMVMCBCTRL, 0x100);
817AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdCRx, 0x00);
818AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrCRx, 0x02);
819AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdDRx, 0x04);
820AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrDRx, 0x06);
821AssertCompileMemberOffset(SVMVMCBCTRL, u32InterceptXcpt, 0x08);
822AssertCompileMemberOffset(SVMVMCBCTRL, u64InterceptCtrl, 0x0c);
823AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved0, 0x14);
824AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterThreshold, 0x3c);
825AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterCount, 0x3e);
826AssertCompileMemberOffset(SVMVMCBCTRL, u64IOPMPhysAddr, 0x40);
827AssertCompileMemberOffset(SVMVMCBCTRL, u64MSRPMPhysAddr, 0x48);
828AssertCompileMemberOffset(SVMVMCBCTRL, u64TSCOffset, 0x50);
829AssertCompileMemberOffset(SVMVMCBCTRL, TLBCtrl, 0x58);
830AssertCompileMemberOffset(SVMVMCBCTRL, IntCtrl, 0x60);
831AssertCompileMemberOffset(SVMVMCBCTRL, IntShadow, 0x68);
832AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitCode, 0x70);
833AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo1, 0x78);
834AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo2, 0x80);
835AssertCompileMemberOffset(SVMVMCBCTRL, ExitIntInfo, 0x88);
836AssertCompileMemberOffset(SVMVMCBCTRL, NestedPagingCtrl, 0x90);
837AssertCompileMemberOffset(SVMVMCBCTRL, AvicBar, 0x98);
838AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved1, 0xa0);
839AssertCompileMemberOffset(SVMVMCBCTRL, EventInject, 0xa8);
840AssertCompileMemberOffset(SVMVMCBCTRL, u64NestedPagingCR3, 0xb0);
841AssertCompileMemberOffset(SVMVMCBCTRL, LbrVirt, 0xb8);
842AssertCompileMemberOffset(SVMVMCBCTRL, u32VmcbCleanBits, 0xc0);
843AssertCompileMemberOffset(SVMVMCBCTRL, u64NextRIP, 0xc8);
844AssertCompileMemberOffset(SVMVMCBCTRL, cbInstrFetched, 0xd0);
845AssertCompileMemberOffset(SVMVMCBCTRL, abInstr, 0xd1);
846AssertCompileMemberOffset(SVMVMCBCTRL, AvicBackingPagePtr, 0xe0);
847AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved2, 0xe8);
848AssertCompileMemberOffset(SVMVMCBCTRL, AvicLogicalTablePtr, 0xf0);
849AssertCompileMemberOffset(SVMVMCBCTRL, AvicPhysicalTablePtr, 0xf8);
850AssertCompileMemberSize(SVMVMCBCTRL, abInstr, 0x0f);
851
852/**
853 * SVM VMCB state save area.
854 */
855#pragma pack(1)
856typedef struct
857{
858 /** Offset 0x400 - Guest ES register + hidden parts. */
859 SVMSELREG ES;
860 /** Offset 0x410 - Guest CS register + hidden parts. */
861 SVMSELREG CS;
862 /** Offset 0x420 - Guest SS register + hidden parts. */
863 SVMSELREG SS;
864 /** Offset 0x430 - Guest DS register + hidden parts. */
865 SVMSELREG DS;
866 /** Offset 0x440 - Guest FS register + hidden parts. */
867 SVMSELREG FS;
868 /** Offset 0x450 - Guest GS register + hidden parts. */
869 SVMSELREG GS;
870 /** Offset 0x460 - Guest GDTR register. */
871 SVMGDTR GDTR;
872 /** Offset 0x470 - Guest LDTR register + hidden parts. */
873 SVMSELREG LDTR;
874 /** Offset 0x480 - Guest IDTR register. */
875 SVMIDTR IDTR;
876 /** Offset 0x490 - Guest TR register + hidden parts. */
877 SVMSELREG TR;
878 /** Offset 0x4A0-0x4CA - Reserved. */
879 uint8_t u8Reserved0[0x4cb - 0x4a0];
880 /** Offset 0x4CB - CPL. */
881 uint8_t u8CPL;
882 /** Offset 0x4CC-0x4CF - Reserved. */
883 uint8_t u8Reserved1[0x4d0 - 0x4cc];
884 /** Offset 0x4D0 - EFER. */
885 uint64_t u64EFER;
886 /** Offset 0x4D8-0x547 - Reserved. */
887 uint8_t u8Reserved2[0x548 - 0x4d8];
888 /** Offset 0x548 - CR4. */
889 uint64_t u64CR4;
890 /** Offset 0x550 - CR3. */
891 uint64_t u64CR3;
892 /** Offset 0x558 - CR0. */
893 uint64_t u64CR0;
894 /** Offset 0x560 - DR7. */
895 uint64_t u64DR7;
896 /** Offset 0x568 - DR6. */
897 uint64_t u64DR6;
898 /** Offset 0x570 - RFLAGS. */
899 uint64_t u64RFlags;
900 /** Offset 0x578 - RIP. */
901 uint64_t u64RIP;
902 /** Offset 0x580-0x5D7 - Reserved. */
903 uint8_t u8Reserved3[0x5d8 - 0x580];
904 /** Offset 0x5D8 - RSP. */
905 uint64_t u64RSP;
906 /** Offset 0x5E0-0x5F7 - Reserved. */
907 uint8_t u8Reserved4[0x5f8 - 0x5e0];
908 /** Offset 0x5F8 - RAX. */
909 uint64_t u64RAX;
910 /** Offset 0x600 - STAR. */
911 uint64_t u64STAR;
912 /** Offset 0x608 - LSTAR. */
913 uint64_t u64LSTAR;
914 /** Offset 0x610 - CSTAR. */
915 uint64_t u64CSTAR;
916 /** Offset 0x618 - SFMASK. */
917 uint64_t u64SFMASK;
918 /** Offset 0x620 - KernelGSBase. */
919 uint64_t u64KernelGSBase;
920 /** Offset 0x628 - SYSENTER_CS. */
921 uint64_t u64SysEnterCS;
922 /** Offset 0x630 - SYSENTER_ESP. */
923 uint64_t u64SysEnterESP;
924 /** Offset 0x638 - SYSENTER_EIP. */
925 uint64_t u64SysEnterEIP;
926 /** Offset 0x640 - CR2. */
927 uint64_t u64CR2;
928 /** Offset 0x648-0x667 - Reserved. */
929 uint8_t u8Reserved5[0x668 - 0x648];
930 /** Offset 0x668 - PAT (Page Attribute Table) MSR. */
931 uint64_t u64PAT;
932 /** Offset 0x670 - DBGCTL. */
933 uint64_t u64DBGCTL;
934 /** Offset 0x678 - BR_FROM. */
935 uint64_t u64BR_FROM;
936 /** Offset 0x680 - BR_TO. */
937 uint64_t u64BR_TO;
938 /** Offset 0x688 - LASTEXCPFROM. */
939 uint64_t u64LASTEXCPFROM;
940 /** Offset 0x690 - LASTEXCPTO. */
941 uint64_t u64LASTEXCPTO;
942} SVMVMCBSTATESAVE;
943#pragma pack()
944/** Pointer to the SVMVMCBSTATESAVE structure. */
945typedef SVMVMCBSTATESAVE *PSVMVMCBSTATESAVE;
946/** Pointer to a const SVMVMCBSTATESAVE structure. */
947typedef const SVMVMCBSTATESAVE *PCSVMVMCBSTATESAVE;
948AssertCompileSize(SVMVMCBSTATESAVE, 0x298);
949AssertCompileMemberOffset(SVMVMCBSTATESAVE, ES, 0x400 - 0x400);
950AssertCompileMemberOffset(SVMVMCBSTATESAVE, CS, 0x410 - 0x400);
951AssertCompileMemberOffset(SVMVMCBSTATESAVE, SS, 0x420 - 0x400);
952AssertCompileMemberOffset(SVMVMCBSTATESAVE, DS, 0x430 - 0x400);
953AssertCompileMemberOffset(SVMVMCBSTATESAVE, FS, 0x440 - 0x400);
954AssertCompileMemberOffset(SVMVMCBSTATESAVE, GS, 0x450 - 0x400);
955AssertCompileMemberOffset(SVMVMCBSTATESAVE, GDTR, 0x460 - 0x400);
956AssertCompileMemberOffset(SVMVMCBSTATESAVE, LDTR, 0x470 - 0x400);
957AssertCompileMemberOffset(SVMVMCBSTATESAVE, IDTR, 0x480 - 0x400);
958AssertCompileMemberOffset(SVMVMCBSTATESAVE, TR, 0x490 - 0x400);
959AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved0, 0x4a0 - 0x400);
960AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8CPL, 0x4cb - 0x400);
961AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved1, 0x4cc - 0x400);
962AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64EFER, 0x4d0 - 0x400);
963AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved2, 0x4d8 - 0x400);
964AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR4, 0x548 - 0x400);
965AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR3, 0x550 - 0x400);
966AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR0, 0x558 - 0x400);
967AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR7, 0x560 - 0x400);
968AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR6, 0x568 - 0x400);
969AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RFlags, 0x570 - 0x400);
970AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RIP, 0x578 - 0x400);
971AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved3, 0x580 - 0x400);
972AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RSP, 0x5d8 - 0x400);
973AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved4, 0x5e0 - 0x400);
974AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RAX, 0x5f8 - 0x400);
975AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64STAR, 0x600 - 0x400);
976AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LSTAR, 0x608 - 0x400);
977AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CSTAR, 0x610 - 0x400);
978AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SFMASK, 0x618 - 0x400);
979AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64KernelGSBase, 0x620 - 0x400);
980AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterCS, 0x628 - 0x400);
981AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterESP, 0x630 - 0x400);
982AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterEIP, 0x638 - 0x400);
983AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR2, 0x640 - 0x400);
984AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved5, 0x648 - 0x400);
985AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64PAT, 0x668 - 0x400);
986AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DBGCTL, 0x670 - 0x400);
987AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_FROM, 0x678 - 0x400);
988AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_TO, 0x680 - 0x400);
989AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPFROM, 0x688 - 0x400);
990AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPTO, 0x690 - 0x400);
991
992/**
993 * SVM VM Control Block. (VMCB)
994 */
995#pragma pack(1)
996typedef struct SVMVMCB
997{
998 /** Offset 0x00 - Control area. */
999 SVMVMCBCTRL ctrl;
1000 /** Offset 0x100-0x3FF - Reserved. */
1001 uint8_t u8Reserved0[0x400 - 0x100];
1002 /** Offset 0x400 - State save area. */
1003 SVMVMCBSTATESAVE guest;
1004 /** Offset 0x698-0xFFF- Reserved. */
1005 uint8_t u8Reserved1[0x1000 - 0x698];
1006} SVMVMCB;
1007#pragma pack()
1008/** Pointer to the SVMVMCB structure. */
1009typedef SVMVMCB *PSVMVMCB;
1010/** Pointer to a const SVMVMCB structure. */
1011typedef const SVMVMCB *PCSVMVMCB;
1012AssertCompileMemberOffset(SVMVMCB, ctrl, 0x00);
1013AssertCompileMemberOffset(SVMVMCB, u8Reserved0, 0x100);
1014AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
1015AssertCompileMemberOffset(SVMVMCB, u8Reserved1, 0x698);
1016AssertCompileSize(SVMVMCB, 0x1000);
1017
1018/**
1019 * SVM MSRs.
1020 */
1021typedef struct SVMMSRS
1022{
1023 /** HWCR MSR. */
1024 uint64_t u64MsrHwcr;
1025 /** Reserved for future. */
1026 uint64_t u64Padding[23];
1027} SVMMSRS;
1028AssertCompileSizeAlignment(SVMMSRS, 8);
1029AssertCompileSize(SVMMSRS, 192);
1030/** Pointer to a SVMMSRS struct. */
1031typedef SVMMSRS *PSVMMSRS;
1032/** Pointer to a const SVMMSRS struct. */
1033typedef const SVMMSRS *PCSVMMSRS;
1034
1035/**
1036 * SVM nested-guest VMCB cache.
1037 *
1038 * Contains VMCB fields from the nested-guest VMCB before they're modified by
1039 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
1040 *
1041 * A VMCB field needs to be cached when it needs to be modified for execution using
1042 * hardware-assisted SVM and any of the following are true:
1043 * - If the original field needs to be inspected during execution of the
1044 * nested-guest or \#VMEXIT processing.
1045 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
1046 *
1047 * A VMCB field needs to be restored only when the field is written back to
1048 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
1049 * guest.
1050 *
1051 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
1052 * this structure.
1053 */
1054#pragma pack(1)
1055typedef struct SVMNESTEDVMCBCACHE
1056{
1057 /** Cache of CRX read intercepts. */
1058 uint16_t u16InterceptRdCRx;
1059 /** Cache of CRX write intercepts. */
1060 uint16_t u16InterceptWrCRx;
1061 /** Cache of DRX read intercepts. */
1062 uint16_t u16InterceptRdDRx;
1063 /** Cache of DRX write intercepts. */
1064 uint16_t u16InterceptWrDRx;
1065
1066 /** Cache of the pause-filter threshold. */
1067 uint16_t u16PauseFilterThreshold;
1068 /** Cache of the pause-filter count. */
1069 uint16_t u16PauseFilterCount;
1070
1071 /** Cache of exception intercepts. */
1072 uint32_t u32InterceptXcpt;
1073 /** Cache of control intercepts. */
1074 uint64_t u64InterceptCtrl;
1075
1076 /** Cache of the TSC offset. */
1077 uint64_t u64TSCOffset;
1078
1079 /** Cache of V_INTR_MASKING bit. */
1080 bool fVIntrMasking;
1081 /** Cache of the nested-paging bit. */
1082 bool fNestedPaging;
1083 /** Cache of the LBR virtualization bit. */
1084 bool fLbrVirt;
1085 /** Whether the VMCB is cached by HM. */
1086 bool fCacheValid;
1087 /** Alignment. */
1088 bool afPadding0[4];
1089} SVMNESTEDVMCBCACHE;
1090#pragma pack()
1091/** Pointer to the SVMNESTEDVMCBCACHE structure. */
1092typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
1093/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
1094typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
1095AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
1096
1097/**
1098 * Segment attribute conversion between CPU and AMD-V VMCB format.
1099 *
1100 * The CPU format of the segment attribute is described in X86DESCATTRBITS
1101 * which is 16-bits (i.e. includes 4 bits of the segment limit).
1102 *
1103 * The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
1104 * only the attribute bits and nothing else). Upper 4-bits are unused.
1105 */
1106#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0xf000) >> 4) )
1107#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0x0f00) << 4) )
1108
1109/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1110 * Copies the specified segment register to a VMCB from a virtual CPU context.
1111 *
1112 * @param a_pCtx The virtual-CPU context.
1113 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1114 * @param a_REG The segment register in the VMCB state-save
1115 * struct (ES/CS/SS/DS).
1116 * @param a_reg The segment register in the virtual CPU struct
1117 * (es/cs/ss/ds).
1118 */
1119#define HMSVM_SEG_REG_COPY_TO_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1120 do \
1121 { \
1122 Assert((a_pCtx)->a_reg.fFlags & CPUMSELREG_FLAGS_VALID); \
1123 Assert((a_pCtx)->a_reg.ValidSel == (a_pCtx)->a_reg.Sel); \
1124 (a_pVmcbStateSave)->a_REG.u16Sel = (a_pCtx)->a_reg.Sel; \
1125 (a_pVmcbStateSave)->a_REG.u32Limit = (a_pCtx)->a_reg.u32Limit; \
1126 (a_pVmcbStateSave)->a_REG.u64Base = (a_pCtx)->a_reg.u64Base; \
1127 (a_pVmcbStateSave)->a_REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR((a_pCtx)->a_reg.Attr.u); \
1128 } while (0)
1129
1130/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1131 * Copies the specified segment register from the VMCB to a virtual CPU
1132 * context.
1133 *
1134 * @param a_pCtx The virtual-CPU context.
1135 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1136 * @param a_REG The segment register in the VMCB state-save
1137 * struct (ES/CS/SS/DS).
1138 * @param a_reg The segment register in the virtual CPU struct
1139 * (es/ds/ss/ds).
1140 */
1141#define HMSVM_SEG_REG_COPY_FROM_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1142 do \
1143 { \
1144 (a_pCtx)->a_reg.Sel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1145 (a_pCtx)->a_reg.ValidSel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1146 (a_pCtx)->a_reg.fFlags = CPUMSELREG_FLAGS_VALID; \
1147 (a_pCtx)->a_reg.u32Limit = (a_pVmcbStateSave)->a_REG.u32Limit; \
1148 (a_pCtx)->a_reg.u64Base = (a_pVmcbStateSave)->a_REG.u64Base; \
1149 (a_pCtx)->a_reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR((a_pVmcbStateSave)->a_REG.u16Attr); \
1150 } while (0)
1151
1152
1153/** @defgroup grp_hm_svm_c SVM C Helpers
1154 *
1155 * These are functions that strictly only implement SVM functionality that is in
1156 * accordance to the SVM spec. and thus fit to use by IEM/REM/HM.
1157 *
1158 * These are not HM all-context API functions, those are to be placed in hm.h.
1159 * @{
1160 */
1161VMM_INT_DECL(int) HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit);
1162VMM_INT_DECL(bool) HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
1163 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
1164 PSVMIOIOEXITINFO pIoExitInfo);
1165/** @} */
1166
1167
1168/** @defgroup grp_hm_svm_hwexec SVM Hardware-assisted execution Helpers
1169 *
1170 * These functions are only here because the inline functions in cpum.h calls them.
1171 * Don't add any more functions here unless there is no other option.
1172 * @{
1173 */
1174VMM_INT_DECL(bool) HMHasGuestSvmVmcbCached(PVMCPU pVCpu);
1175VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, uint64_t fIntercept);
1176VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, uint8_t uCr);
1177VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, uint8_t uCr);
1178VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, uint8_t uDr);
1179VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, uint8_t uDr);
1180VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, uint8_t uVector);
1181VMM_INT_DECL(bool) HMIsGuestSvmVirtIntrMasking(PVMCPU pVCpu);
1182VMM_INT_DECL(bool) HMIsGuestSvmNestedPagingEnabled(PVMCPU pVCpu);
1183VMM_INT_DECL(uint16_t) HMGetGuestSvmPauseFilterCount(PVMCPU pVCpu);
1184/** @} */
1185
1186
1187/** @} */
1188
1189#endif
1190
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