VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 78454

Last change on this file since 78454 was 78371, checked in by vboxsync, 6 years ago

VMM: Move VT-x/AMD-V helpers that are based on CPU specs to CPUM in preparation of upcoming changes. It is better placed in CPUM if say NEM in future needs to implement nested VT-x/AMD-V.
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File size: 46.8 KB
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1/** @file
2 * HM - SVM (AMD-V) Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2019 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_hm_svm_h
27#define VBOX_INCLUDED_vmm_hm_svm_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/types.h>
33#include <iprt/assert.h>
34#include <iprt/asm.h>
35
36#ifdef RT_OS_SOLARIS
37# undef ES
38# undef CS
39# undef DS
40# undef SS
41# undef FS
42# undef GS
43#endif
44
45/** @defgroup grp_hm_svm SVM (AMD-V) Types and Definitions
46 * @ingroup grp_hm
47 * @{
48 */
49
50/** @name SVM generic / convenient defines.
51 * @{
52 */
53/** Number of pages required for the VMCB. */
54#define SVM_VMCB_PAGES 1
55/** Number of pages required for the MSR permission bitmap. */
56#define SVM_MSRPM_PAGES 2
57/** Number of pages required for the IO permission bitmap. */
58#define SVM_IOPM_PAGES 3
59/** @} */
60
61/*
62 * Ugly!
63 * When compiling the recompiler, its own svm.h defines clash with
64 * the following defines. Avoid just the duplicates here as we still
65 * require other definitions and structures in this header.
66 */
67#ifndef IN_REM_R3
68/** @name SVM_EXIT_XXX - SVM Basic Exit Reasons.
69 * @{
70 */
71/** Invalid guest state in VMCB. */
72# define SVM_EXIT_INVALID (uint64_t)(-1)
73/** Read from CR0-CR15. */
74# define SVM_EXIT_READ_CR0 0x0
75# define SVM_EXIT_READ_CR1 0x1
76# define SVM_EXIT_READ_CR2 0x2
77# define SVM_EXIT_READ_CR3 0x3
78# define SVM_EXIT_READ_CR4 0x4
79# define SVM_EXIT_READ_CR5 0x5
80# define SVM_EXIT_READ_CR6 0x6
81# define SVM_EXIT_READ_CR7 0x7
82# define SVM_EXIT_READ_CR8 0x8
83# define SVM_EXIT_READ_CR9 0x9
84# define SVM_EXIT_READ_CR10 0xa
85# define SVM_EXIT_READ_CR11 0xb
86# define SVM_EXIT_READ_CR12 0xc
87# define SVM_EXIT_READ_CR13 0xd
88# define SVM_EXIT_READ_CR14 0xe
89# define SVM_EXIT_READ_CR15 0xf
90/** Writes to CR0-CR15. */
91# define SVM_EXIT_WRITE_CR0 0x10
92# define SVM_EXIT_WRITE_CR1 0x11
93# define SVM_EXIT_WRITE_CR2 0x12
94# define SVM_EXIT_WRITE_CR3 0x13
95# define SVM_EXIT_WRITE_CR4 0x14
96# define SVM_EXIT_WRITE_CR5 0x15
97# define SVM_EXIT_WRITE_CR6 0x16
98# define SVM_EXIT_WRITE_CR7 0x17
99# define SVM_EXIT_WRITE_CR8 0x18
100# define SVM_EXIT_WRITE_CR9 0x19
101# define SVM_EXIT_WRITE_CR10 0x1a
102# define SVM_EXIT_WRITE_CR11 0x1b
103# define SVM_EXIT_WRITE_CR12 0x1c
104# define SVM_EXIT_WRITE_CR13 0x1d
105# define SVM_EXIT_WRITE_CR14 0x1e
106# define SVM_EXIT_WRITE_CR15 0x1f
107/** Read from DR0-DR15. */
108# define SVM_EXIT_READ_DR0 0x20
109# define SVM_EXIT_READ_DR1 0x21
110# define SVM_EXIT_READ_DR2 0x22
111# define SVM_EXIT_READ_DR3 0x23
112# define SVM_EXIT_READ_DR4 0x24
113# define SVM_EXIT_READ_DR5 0x25
114# define SVM_EXIT_READ_DR6 0x26
115# define SVM_EXIT_READ_DR7 0x27
116# define SVM_EXIT_READ_DR8 0x28
117# define SVM_EXIT_READ_DR9 0x29
118# define SVM_EXIT_READ_DR10 0x2a
119# define SVM_EXIT_READ_DR11 0x2b
120# define SVM_EXIT_READ_DR12 0x2c
121# define SVM_EXIT_READ_DR13 0x2d
122# define SVM_EXIT_READ_DR14 0x2e
123# define SVM_EXIT_READ_DR15 0x2f
124/** Writes to DR0-DR15. */
125# define SVM_EXIT_WRITE_DR0 0x30
126# define SVM_EXIT_WRITE_DR1 0x31
127# define SVM_EXIT_WRITE_DR2 0x32
128# define SVM_EXIT_WRITE_DR3 0x33
129# define SVM_EXIT_WRITE_DR4 0x34
130# define SVM_EXIT_WRITE_DR5 0x35
131# define SVM_EXIT_WRITE_DR6 0x36
132# define SVM_EXIT_WRITE_DR7 0x37
133# define SVM_EXIT_WRITE_DR8 0x38
134# define SVM_EXIT_WRITE_DR9 0x39
135# define SVM_EXIT_WRITE_DR10 0x3a
136# define SVM_EXIT_WRITE_DR11 0x3b
137# define SVM_EXIT_WRITE_DR12 0x3c
138# define SVM_EXIT_WRITE_DR13 0x3d
139# define SVM_EXIT_WRITE_DR14 0x3e
140# define SVM_EXIT_WRITE_DR15 0x3f
141/* Exception 0-31. */
142# define SVM_EXIT_XCPT_0 0x40
143# define SVM_EXIT_XCPT_1 0x41
144# define SVM_EXIT_XCPT_2 0x42
145# define SVM_EXIT_XCPT_3 0x43
146# define SVM_EXIT_XCPT_4 0x44
147# define SVM_EXIT_XCPT_5 0x45
148# define SVM_EXIT_XCPT_6 0x46
149# define SVM_EXIT_XCPT_7 0x47
150# define SVM_EXIT_XCPT_8 0x48
151# define SVM_EXIT_XCPT_9 0x49
152# define SVM_EXIT_XCPT_10 0x4a
153# define SVM_EXIT_XCPT_11 0x4b
154# define SVM_EXIT_XCPT_12 0x4c
155# define SVM_EXIT_XCPT_13 0x4d
156# define SVM_EXIT_XCPT_14 0x4e
157# define SVM_EXIT_XCPT_15 0x4f
158# define SVM_EXIT_XCPT_16 0x50
159# define SVM_EXIT_XCPT_17 0x51
160# define SVM_EXIT_XCPT_18 0x52
161# define SVM_EXIT_XCPT_19 0x53
162# define SVM_EXIT_XCPT_20 0x54
163# define SVM_EXIT_XCPT_21 0x55
164# define SVM_EXIT_XCPT_22 0x56
165# define SVM_EXIT_XCPT_23 0x57
166# define SVM_EXIT_XCPT_24 0x58
167# define SVM_EXIT_XCPT_25 0x59
168# define SVM_EXIT_XCPT_26 0x5a
169# define SVM_EXIT_XCPT_27 0x5b
170# define SVM_EXIT_XCPT_28 0x5c
171# define SVM_EXIT_XCPT_29 0x5d
172# define SVM_EXIT_XCPT_30 0x5e
173# define SVM_EXIT_XCPT_31 0x5f
174/* Exception (more readable) */
175# define SVM_EXIT_XCPT_DE SVM_EXIT_XCPT_0
176# define SVM_EXIT_XCPT_DB SVM_EXIT_XCPT_1
177# define SVM_EXIT_XCPT_NMI SVM_EXIT_XCPT_2
178# define SVM_EXIT_XCPT_BP SVM_EXIT_XCPT_3
179# define SVM_EXIT_XCPT_OF SVM_EXIT_XCPT_4
180# define SVM_EXIT_XCPT_BR SVM_EXIT_XCPT_5
181# define SVM_EXIT_XCPT_UD SVM_EXIT_XCPT_6
182# define SVM_EXIT_XCPT_NM SVM_EXIT_XCPT_7
183# define SVM_EXIT_XCPT_DF SVM_EXIT_XCPT_8
184# define SVM_EXIT_XCPT_CO_SEG_OVERRUN SVM_EXIT_XCPT_9
185# define SVM_EXIT_XCPT_TS SVM_EXIT_XCPT_10
186# define SVM_EXIT_XCPT_NP SVM_EXIT_XCPT_11
187# define SVM_EXIT_XCPT_SS SVM_EXIT_XCPT_12
188# define SVM_EXIT_XCPT_GP SVM_EXIT_XCPT_13
189# define SVM_EXIT_XCPT_PF SVM_EXIT_XCPT_14
190# define SVM_EXIT_XCPT_MF SVM_EXIT_XCPT_16
191# define SVM_EXIT_XCPT_AC SVM_EXIT_XCPT_17
192# define SVM_EXIT_XCPT_MC SVM_EXIT_XCPT_18
193# define SVM_EXIT_XCPT_XF SVM_EXIT_XCPT_19
194# define SVM_EXIT_XCPT_VE SVM_EXIT_XCPT_20
195# define SVM_EXIT_XCPT_SX SVM_EXIT_XCPT_30
196/** Physical maskable interrupt. */
197# define SVM_EXIT_INTR 0x60
198/** Non-maskable interrupt. */
199# define SVM_EXIT_NMI 0x61
200/** System Management interrupt. */
201# define SVM_EXIT_SMI 0x62
202/** Physical INIT signal. */
203# define SVM_EXIT_INIT 0x63
204/** Virtual interrupt. */
205# define SVM_EXIT_VINTR 0x64
206/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
207# define SVM_EXIT_CR0_SEL_WRITE 0x65
208/** IDTR read. */
209# define SVM_EXIT_IDTR_READ 0x66
210/** GDTR read. */
211# define SVM_EXIT_GDTR_READ 0x67
212/** LDTR read. */
213# define SVM_EXIT_LDTR_READ 0x68
214/** TR read. */
215# define SVM_EXIT_TR_READ 0x69
216/** IDTR write. */
217# define SVM_EXIT_IDTR_WRITE 0x6a
218/** GDTR write. */
219# define SVM_EXIT_GDTR_WRITE 0x6b
220/** LDTR write. */
221# define SVM_EXIT_LDTR_WRITE 0x6c
222/** TR write. */
223# define SVM_EXIT_TR_WRITE 0x6d
224/** RDTSC instruction. */
225# define SVM_EXIT_RDTSC 0x6e
226/** RDPMC instruction. */
227# define SVM_EXIT_RDPMC 0x6f
228/** PUSHF instruction. */
229# define SVM_EXIT_PUSHF 0x70
230/** POPF instruction. */
231# define SVM_EXIT_POPF 0x71
232/** CPUID instruction. */
233# define SVM_EXIT_CPUID 0x72
234/** RSM instruction. */
235# define SVM_EXIT_RSM 0x73
236/** IRET instruction. */
237# define SVM_EXIT_IRET 0x74
238/** software interrupt (INTn instructions). */
239# define SVM_EXIT_SWINT 0x75
240/** INVD instruction. */
241# define SVM_EXIT_INVD 0x76
242/** PAUSE instruction. */
243# define SVM_EXIT_PAUSE 0x77
244/** HLT instruction. */
245# define SVM_EXIT_HLT 0x78
246/** INVLPG instructions. */
247# define SVM_EXIT_INVLPG 0x79
248/** INVLPGA instruction. */
249# define SVM_EXIT_INVLPGA 0x7a
250/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
251# define SVM_EXIT_IOIO 0x7b
252/** RDMSR or WRMSR access to protected MSR. */
253# define SVM_EXIT_MSR 0x7c
254/** task switch. */
255# define SVM_EXIT_TASK_SWITCH 0x7d
256/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
257# define SVM_EXIT_FERR_FREEZE 0x7e
258/** Shutdown. */
259# define SVM_EXIT_SHUTDOWN 0x7f
260/** VMRUN instruction. */
261# define SVM_EXIT_VMRUN 0x80
262/** VMMCALL instruction. */
263# define SVM_EXIT_VMMCALL 0x81
264/** VMLOAD instruction. */
265# define SVM_EXIT_VMLOAD 0x82
266/** VMSAVE instruction. */
267# define SVM_EXIT_VMSAVE 0x83
268/** STGI instruction. */
269# define SVM_EXIT_STGI 0x84
270/** CLGI instruction. */
271# define SVM_EXIT_CLGI 0x85
272/** SKINIT instruction. */
273# define SVM_EXIT_SKINIT 0x86
274/** RDTSCP instruction. */
275# define SVM_EXIT_RDTSCP 0x87
276/** ICEBP instruction. */
277# define SVM_EXIT_ICEBP 0x88
278/** WBINVD instruction. */
279# define SVM_EXIT_WBINVD 0x89
280/** MONITOR instruction. */
281# define SVM_EXIT_MONITOR 0x8a
282/** MWAIT instruction. */
283# define SVM_EXIT_MWAIT 0x8b
284/** MWAIT instruction, when armed. */
285# define SVM_EXIT_MWAIT_ARMED 0x8c
286/** XSETBV instruction. */
287# define SVM_EXIT_XSETBV 0x8d
288/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
289# define SVM_EXIT_NPF 0x400
290/** AVIC: Virtual IPI delivery not completed. */
291# define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
292/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
293 * hardware. */
294# define SVM_EXIT_AVIC_NOACCEL 0x402
295/** The maximum possible exit value. */
296# define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
297/** @} */
298#endif /* !IN_REM_R3*/
299
300
301/** @name SVMVMCB.u64ExitInfo2 for task switches
302 * @{
303 */
304/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
305#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
306/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
307#define SVM_EXIT2_TASK_SWITCH_JUMP RT_BIT_64(38)
308/** Set to 1 if the task switch has an error code; else cleared to 0. */
309#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
310/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
311#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
312/** @} */
313
314/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
315 * @{
316 */
317/** The access was a read MSR. */
318#define SVM_EXIT1_MSR_READ 0x0
319/** The access was a write MSR. */
320#define SVM_EXIT1_MSR_WRITE 0x1
321/** @} */
322
323/** @name SVMVMCB.u64ExitInfo1 for Mov CRx accesses.
324 * @{
325 */
326/** The mask of whether the access was via a Mov CRx instruction. */
327#define SVM_EXIT1_MOV_CRX_MASK RT_BIT_64(63)
328/** The mask for the GPR number of the Mov CRx instruction. */
329#define SVM_EXIT1_MOV_CRX_GPR_NUMBER 0xf
330/** @} */
331
332/** @name SVMVMCB.u64ExitInfo1 for Mov DRx accesses.
333 * @{
334 */
335/** The mask for the GPR number of the Mov DRx instruction. */
336#define SVM_EXIT1_MOV_DRX_GPR_NUMBER 0xf
337/** @} */
338
339/** @name SVMVMCB.ctrl.u64InterceptCtrl
340 * @{
341 */
342/** Intercept INTR (physical maskable interrupt). */
343#define SVM_CTRL_INTERCEPT_INTR RT_BIT_64(0)
344/** Intercept NMI. */
345#define SVM_CTRL_INTERCEPT_NMI RT_BIT_64(1)
346/** Intercept SMI. */
347#define SVM_CTRL_INTERCEPT_SMI RT_BIT_64(2)
348/** Intercept INIT. */
349#define SVM_CTRL_INTERCEPT_INIT RT_BIT_64(3)
350/** Intercept VINTR (virtual maskable interrupt). */
351#define SVM_CTRL_INTERCEPT_VINTR RT_BIT_64(4)
352/** Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
353#define SVM_CTRL_INTERCEPT_CR0_SEL_WRITE RT_BIT_64(5)
354/** Intercept reads of IDTR. */
355#define SVM_CTRL_INTERCEPT_IDTR_READS RT_BIT_64(6)
356/** Intercept reads of GDTR. */
357#define SVM_CTRL_INTERCEPT_GDTR_READS RT_BIT_64(7)
358/** Intercept reads of LDTR. */
359#define SVM_CTRL_INTERCEPT_LDTR_READS RT_BIT_64(8)
360/** Intercept reads of TR. */
361#define SVM_CTRL_INTERCEPT_TR_READS RT_BIT_64(9)
362/** Intercept writes of IDTR. */
363#define SVM_CTRL_INTERCEPT_IDTR_WRITES RT_BIT_64(10)
364/** Intercept writes of GDTR. */
365#define SVM_CTRL_INTERCEPT_GDTR_WRITES RT_BIT_64(11)
366/** Intercept writes of LDTR. */
367#define SVM_CTRL_INTERCEPT_LDTR_WRITES RT_BIT_64(12)
368/** Intercept writes of TR. */
369#define SVM_CTRL_INTERCEPT_TR_WRITES RT_BIT_64(13)
370/** Intercept RDTSC instruction. */
371#define SVM_CTRL_INTERCEPT_RDTSC RT_BIT_64(14)
372/** Intercept RDPMC instruction. */
373#define SVM_CTRL_INTERCEPT_RDPMC RT_BIT_64(15)
374/** Intercept PUSHF instruction. */
375#define SVM_CTRL_INTERCEPT_PUSHF RT_BIT_64(16)
376/** Intercept POPF instruction. */
377#define SVM_CTRL_INTERCEPT_POPF RT_BIT_64(17)
378/** Intercept CPUID instruction. */
379#define SVM_CTRL_INTERCEPT_CPUID RT_BIT_64(18)
380/** Intercept RSM instruction. */
381#define SVM_CTRL_INTERCEPT_RSM RT_BIT_64(19)
382/** Intercept IRET instruction. */
383#define SVM_CTRL_INTERCEPT_IRET RT_BIT_64(20)
384/** Intercept INTn instruction. */
385#define SVM_CTRL_INTERCEPT_INTN RT_BIT_64(21)
386/** Intercept INVD instruction. */
387#define SVM_CTRL_INTERCEPT_INVD RT_BIT_64(22)
388/** Intercept PAUSE instruction. */
389#define SVM_CTRL_INTERCEPT_PAUSE RT_BIT_64(23)
390/** Intercept HLT instruction. */
391#define SVM_CTRL_INTERCEPT_HLT RT_BIT_64(24)
392/** Intercept INVLPG instruction. */
393#define SVM_CTRL_INTERCEPT_INVLPG RT_BIT_64(25)
394/** Intercept INVLPGA instruction. */
395#define SVM_CTRL_INTERCEPT_INVLPGA RT_BIT_64(26)
396/** IOIO_PROT Intercept IN/OUT accesses to selected ports. */
397#define SVM_CTRL_INTERCEPT_IOIO_PROT RT_BIT_64(27)
398/** MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
399#define SVM_CTRL_INTERCEPT_MSR_PROT RT_BIT_64(28)
400/** Intercept task switches. */
401#define SVM_CTRL_INTERCEPT_TASK_SWITCH RT_BIT_64(29)
402/** FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
403#define SVM_CTRL_INTERCEPT_FERR_FREEZE RT_BIT_64(30)
404/** Intercept shutdown events. */
405#define SVM_CTRL_INTERCEPT_SHUTDOWN RT_BIT_64(31)
406/** Intercept VMRUN instruction. */
407#define SVM_CTRL_INTERCEPT_VMRUN RT_BIT_64(32 + 0)
408/** Intercept VMMCALL instruction. */
409#define SVM_CTRL_INTERCEPT_VMMCALL RT_BIT_64(32 + 1)
410/** Intercept VMLOAD instruction. */
411#define SVM_CTRL_INTERCEPT_VMLOAD RT_BIT_64(32 + 2)
412/** Intercept VMSAVE instruction. */
413#define SVM_CTRL_INTERCEPT_VMSAVE RT_BIT_64(32 + 3)
414/** Intercept STGI instruction. */
415#define SVM_CTRL_INTERCEPT_STGI RT_BIT_64(32 + 4)
416/** Intercept CLGI instruction. */
417#define SVM_CTRL_INTERCEPT_CLGI RT_BIT_64(32 + 5)
418/** Intercept SKINIT instruction. */
419#define SVM_CTRL_INTERCEPT_SKINIT RT_BIT_64(32 + 6)
420/** Intercept RDTSCP instruction. */
421#define SVM_CTRL_INTERCEPT_RDTSCP RT_BIT_64(32 + 7)
422/** Intercept ICEBP instruction. */
423#define SVM_CTRL_INTERCEPT_ICEBP RT_BIT_64(32 + 8)
424/** Intercept WBINVD instruction. */
425#define SVM_CTRL_INTERCEPT_WBINVD RT_BIT_64(32 + 9)
426/** Intercept MONITOR instruction. */
427#define SVM_CTRL_INTERCEPT_MONITOR RT_BIT_64(32 + 10)
428/** Intercept MWAIT instruction unconditionally. */
429#define SVM_CTRL_INTERCEPT_MWAIT RT_BIT_64(32 + 11)
430/** Intercept MWAIT instruction when armed. */
431#define SVM_CTRL_INTERCEPT_MWAIT_ARMED RT_BIT_64(32 + 12)
432/** Intercept XSETBV instruction. */
433#define SVM_CTRL_INTERCEPT_XSETBV RT_BIT_64(32 + 13)
434/* Bit 14 - Reserved, SBZ. */
435/** Intercept EFER writes after guest instruction finishes. */
436#define SVM_CTRL_INTERCEPT_EFER_WRITES_TRAP RT_BIT_64(32 + 15)
437/** Intercept CR0 writes after guest instruction finishes. */
438#define SVM_CTRL_INTERCEPT_CR0_WRITES_TRAP RT_BIT_64(32 + 16)
439/** Intercept CR0 writes after guest instruction finishes. */
440#define SVM_CTRL_INTERCEPT_CR1_WRITES_TRAP RT_BIT_64(32 + 17)
441/** Intercept CR0 writes after guest instruction finishes. */
442#define SVM_CTRL_INTERCEPT_CR2_WRITES_TRAP RT_BIT_64(32 + 18)
443/** Intercept CR0 writes after guest instruction finishes. */
444#define SVM_CTRL_INTERCEPT_CR3_WRITES_TRAP RT_BIT_64(32 + 19)
445/** Intercept CR0 writes after guest instruction finishes. */
446#define SVM_CTRL_INTERCEPT_CR4_WRITES_TRAP RT_BIT_64(32 + 20)
447/** Intercept CR0 writes after guest instruction finishes. */
448#define SVM_CTRL_INTERCEPT_CR5_WRITES_TRAP RT_BIT_64(32 + 21)
449/** Intercept CR0 writes after guest instruction finishes. */
450#define SVM_CTRL_INTERCEPT_CR6_WRITES_TRAP RT_BIT_64(32 + 22)
451/** Intercept CR0 writes after guest instruction finishes. */
452#define SVM_CTRL_INTERCEPT_CR7_WRITES_TRAP RT_BIT_64(32 + 23)
453/** Intercept CR0 writes after guest instruction finishes. */
454#define SVM_CTRL_INTERCEPT_CR8_WRITES_TRAP RT_BIT_64(32 + 24)
455/** Intercept CR0 writes after guest instruction finishes. */
456#define SVM_CTRL_INTERCEPT_CR9_WRITES_TRAP RT_BIT_64(32 + 25)
457/** Intercept CR0 writes after guest instruction finishes. */
458#define SVM_CTRL_INTERCEPT_CR10_WRITES_TRAP RT_BIT_64(32 + 26)
459/** Intercept CR0 writes after guest instruction finishes. */
460#define SVM_CTRL_INTERCEPT_CR11_WRITES_TRAP RT_BIT_64(32 + 27)
461/** Intercept CR0 writes after guest instruction finishes. */
462#define SVM_CTRL_INTERCEPT_CR12_WRITES_TRAP RT_BIT_64(32 + 28)
463/** Intercept CR0 writes after guest instruction finishes. */
464#define SVM_CTRL_INTERCEPT_CR13_WRITES_TRAP RT_BIT_64(32 + 29)
465/** Intercept CR0 writes after guest instruction finishes. */
466#define SVM_CTRL_INTERCEPT_CR14_WRITES_TRAP RT_BIT_64(32 + 30)
467/** Intercept CR0 writes after guest instruction finishes. */
468#define SVM_CTRL_INTERCEPT_CR15_WRITES_TRAP RT_BIT_64(32 + 31)
469/** @} */
470
471/** @name SVMINTCTRL.u3Type
472 * @{
473 */
474/** External or virtual interrupt. */
475#define SVM_EVENT_EXTERNAL_IRQ 0
476/** Non-maskable interrupt. */
477#define SVM_EVENT_NMI 2
478/** Exception; fault or trap. */
479#define SVM_EVENT_EXCEPTION 3
480/** Software interrupt. */
481#define SVM_EVENT_SOFTWARE_INT 4
482/** @} */
483
484/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
485 * @{
486 */
487/** Flush nothing. */
488#define SVM_TLB_FLUSH_NOTHING 0
489/** Flush entire TLB (host+guest entries) */
490#define SVM_TLB_FLUSH_ENTIRE 1
491/** Flush this guest's TLB entries (by ASID) */
492#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
493/** Flush this guest's non-global TLB entries (by ASID) */
494#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
495/** @} */
496
497/**
498 * SVM selector/segment register type.
499 */
500typedef struct
501{
502 uint16_t u16Sel;
503 uint16_t u16Attr;
504 uint32_t u32Limit;
505 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
506} SVMSELREG;
507AssertCompileSize(SVMSELREG, 16);
508/** Pointer to the SVMSELREG struct. */
509typedef SVMSELREG *PSVMSELREG;
510/** Pointer to a const SVMSELREG struct. */
511typedef const SVMSELREG *PCSVMSELREG;
512
513/**
514 * SVM GDTR/IDTR type.
515 */
516typedef struct
517{
518 uint16_t u16Reserved0;
519 uint16_t u16Reserved1;
520 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
521 uint64_t u64Base;
522} SVMXDTR;
523AssertCompileSize(SVMXDTR, 16);
524typedef SVMXDTR SVMIDTR;
525typedef SVMXDTR SVMGDTR;
526/** Pointer to the SVMXDTR struct. */
527typedef SVMXDTR *PSVMXDTR;
528/** Pointer to a const SVMXDTR struct. */
529typedef const SVMXDTR *PCSVMXDTR;
530
531/**
532 * SVM Event injection structure (EVENTINJ and EXITINTINFO).
533 */
534typedef union
535{
536 struct
537 {
538 uint32_t u8Vector : 8;
539 uint32_t u3Type : 3;
540 uint32_t u1ErrorCodeValid : 1;
541 uint32_t u19Reserved : 19;
542 uint32_t u1Valid : 1;
543 uint32_t u32ErrorCode : 32;
544 } n;
545 uint64_t u;
546} SVMEVENT;
547/** Pointer to the SVMEVENT union. */
548typedef SVMEVENT *PSVMEVENT;
549/** Pointer to a const SVMEVENT union. */
550typedef const SVMEVENT *PCSVMEVENT;
551
552/** Gets the event type given an SVMEVENT parameter. */
553#define SVM_EVENT_GET_TYPE(a_SvmEvent) (((a_SvmEvent) >> 8) & 7)
554
555/**
556 * SVM Interrupt control structure (Virtual Interrupt Control).
557 */
558typedef union
559{
560 struct
561 {
562 uint32_t u8VTPR : 8; /* V_TPR */
563 uint32_t u1VIrqPending : 1; /* V_IRQ */
564 uint32_t u1VGif : 1; /* VGIF */
565 uint32_t u6Reserved : 6;
566 uint32_t u4VIntrPrio : 4; /* V_INTR_PRIO */
567 uint32_t u1IgnoreTPR : 1; /* V_IGN_TPR */
568 uint32_t u3Reserved : 3;
569 uint32_t u1VIntrMasking : 1; /* V_INTR_MASKING */
570 uint32_t u1VGifEnable : 1; /* VGIF enable */
571 uint32_t u5Reserved : 5;
572 uint32_t u1AvicEnable : 1; /* AVIC enable */
573 uint32_t u8VIntrVector : 8; /* V_INTR_VECTOR */
574 uint32_t u24Reserved : 24;
575 } n;
576 uint64_t u;
577} SVMINTCTRL;
578/** Pointer to an SVMINTCTRL structure. */
579typedef SVMINTCTRL *PSVMINTCTRL;
580/** Pointer to a const SVMINTCTRL structure. */
581typedef const SVMINTCTRL *PCSVMINTCTRL;
582
583/**
584 * SVM TLB control structure.
585 */
586typedef union
587{
588 struct
589 {
590 uint32_t u32ASID : 32;
591 uint32_t u8TLBFlush : 8;
592 uint32_t u24Reserved : 24;
593 } n;
594 uint64_t u;
595} SVMTLBCTRL;
596
597/**
598 * SVM IOIO exit info. structure (EXITINFO1 for IOIO intercepts).
599 */
600typedef union
601{
602 struct
603 {
604 uint32_t u1Type : 1; /**< Bit 0: 0 = out, 1 = in */
605 uint32_t u1Reserved : 1; /**< Bit 1: Reserved */
606 uint32_t u1Str : 1; /**< Bit 2: String I/O (1) or not (0). */
607 uint32_t u1Rep : 1; /**< Bit 3: Repeat prefixed string I/O. */
608 uint32_t u1Op8 : 1; /**< Bit 4: 8-bit operand. */
609 uint32_t u1Op16 : 1; /**< Bit 5: 16-bit operand. */
610 uint32_t u1Op32 : 1; /**< Bit 6: 32-bit operand. */
611 uint32_t u1Addr16 : 1; /**< Bit 7: 16-bit address size. */
612 uint32_t u1Addr32 : 1; /**< Bit 8: 32-bit address size. */
613 uint32_t u1Addr64 : 1; /**< Bit 9: 64-bit address size. */
614 uint32_t u3Seg : 3; /**< Bits 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
615 uint32_t u3Reserved : 3;
616 uint32_t u16Port : 16; /**< Bits 31:16: Port number. */
617 } n;
618 uint32_t u;
619} SVMIOIOEXITINFO;
620/** Pointer to an SVM IOIO exit info. structure. */
621typedef SVMIOIOEXITINFO *PSVMIOIOEXITINFO;
622/** Pointer to a const SVM IOIO exit info. structure. */
623typedef const SVMIOIOEXITINFO *PCSVMIOIOEXITINFO;
624
625/** 8-bit IO transfer. */
626#define SVM_IOIO_8_BIT_OP RT_BIT_32(4)
627/** 16-bit IO transfer. */
628#define SVM_IOIO_16_BIT_OP RT_BIT_32(5)
629/** 32-bit IO transfer. */
630#define SVM_IOIO_32_BIT_OP RT_BIT_32(6)
631/** Number of bits to shift right to get the operand sizes. */
632#define SVM_IOIO_OP_SIZE_SHIFT 4
633/** Mask of all possible IO transfer sizes. */
634#define SVM_IOIO_OP_SIZE_MASK (SVM_IOIO_8_BIT_OP | SVM_IOIO_16_BIT_OP | SVM_IOIO_32_BIT_OP)
635/** 16-bit address for the IO buffer. */
636#define SVM_IOIO_16_BIT_ADDR RT_BIT_32(7)
637/** 32-bit address for the IO buffer. */
638#define SVM_IOIO_32_BIT_ADDR RT_BIT_32(8)
639/** 64-bit address for the IO buffer. */
640#define SVM_IOIO_64_BIT_ADDR RT_BIT_32(9)
641/** Number of bits to shift right to get the address sizes. */
642#define SVM_IOIO_ADDR_SIZE_SHIFT 7
643/** Mask of all the IO address sizes. */
644#define SVM_IOIO_ADDR_SIZE_MASK (SVM_IOIO_16_BIT_ADDR | SVM_IOIO_32_BIT_ADDR | SVM_IOIO_64_BIT_ADDR)
645/** Number of bits to shift right to get the IO port number. */
646#define SVM_IOIO_PORT_SHIFT 16
647/** IO write. */
648#define SVM_IOIO_WRITE 0
649/** IO read. */
650#define SVM_IOIO_READ 1
651/**
652 * SVM IOIO transfer type.
653 */
654typedef enum
655{
656 SVMIOIOTYPE_OUT = SVM_IOIO_WRITE,
657 SVMIOIOTYPE_IN = SVM_IOIO_READ
658} SVMIOIOTYPE;
659
660/**
661 * SVM AVIC.
662 */
663typedef union
664{
665 struct
666 {
667 RT_GCC_EXTENSION uint64_t u12Reserved0 : 12;
668 RT_GCC_EXTENSION uint64_t u40Addr : 40;
669 RT_GCC_EXTENSION uint64_t u12Reserved1 : 12;
670 } n;
671 uint64_t u;
672} SVMAVIC;
673AssertCompileSize(SVMAVIC, 8);
674
675/**
676 * SVM AVIC PHYSICAL_TABLE pointer.
677 */
678typedef union
679{
680 struct
681 {
682 RT_GCC_EXTENSION uint64_t u8LastGuestCoreId : 8;
683 RT_GCC_EXTENSION uint64_t u4Reserved : 4;
684 RT_GCC_EXTENSION uint64_t u40Addr : 40;
685 RT_GCC_EXTENSION uint64_t u12Reserved : 12;
686 } n;
687 uint64_t u;
688} SVMAVICPHYS;
689AssertCompileSize(SVMAVICPHYS, 8);
690
691/**
692 * SVM Nested Paging struct.
693 */
694typedef union
695{
696 struct
697 {
698 uint32_t u1NestedPaging : 1;
699 uint32_t u1Sev : 1;
700 uint32_t u1SevEs : 1;
701 uint32_t u29Reserved : 29;
702 } n;
703 uint64_t u;
704} SVMNP;
705AssertCompileSize(SVMNP, 8);
706
707/**
708 * SVM Interrupt shadow struct.
709 */
710typedef union
711{
712 struct
713 {
714 uint32_t u1IntShadow : 1;
715 uint32_t u1GuestIntMask : 1;
716 uint32_t u30Reserved : 30;
717 } n;
718 uint64_t u;
719} SVMINTSHADOW;
720AssertCompileSize(SVMINTSHADOW, 8);
721
722/**
723 * SVM LBR virtualization struct.
724 */
725typedef union
726{
727 struct
728 {
729 uint32_t u1LbrVirt : 1;
730 uint32_t u1VirtVmsaveVmload : 1;
731 uint32_t u30Reserved : 30;
732 } n;
733 uint64_t u;
734} SVMLBRVIRT;
735AssertCompileSize(SVMLBRVIRT, 8);
736
737/** Maximum number of bytes in the Guest-instruction bytes field. */
738#define SVM_CTRL_GUEST_INSTR_BYTES_MAX 15
739
740/**
741 * SVM VMCB control area.
742 */
743#pragma pack(1)
744typedef struct
745{
746 /** Offset 0x00 - Intercept reads of CR0-CR15. */
747 uint16_t u16InterceptRdCRx;
748 /** Offset 0x02 - Intercept writes to CR0-CR15. */
749 uint16_t u16InterceptWrCRx;
750 /** Offset 0x04 - Intercept reads of DR0-DR15. */
751 uint16_t u16InterceptRdDRx;
752 /** Offset 0x06 - Intercept writes to DR0-DR15. */
753 uint16_t u16InterceptWrDRx;
754 /** Offset 0x08 - Intercept exception vectors 0-31. */
755 uint32_t u32InterceptXcpt;
756 /** Offset 0x0c - Intercept control. */
757 uint64_t u64InterceptCtrl;
758 /** Offset 0x14-0x3f - Reserved. */
759 uint8_t u8Reserved0[0x3c - 0x14];
760 /** Offset 0x3c - PAUSE filter threshold. */
761 uint16_t u16PauseFilterThreshold;
762 /** Offset 0x3e - PAUSE intercept filter count. */
763 uint16_t u16PauseFilterCount;
764 /** Offset 0x40 - Physical address of IOPM. */
765 uint64_t u64IOPMPhysAddr;
766 /** Offset 0x48 - Physical address of MSRPM. */
767 uint64_t u64MSRPMPhysAddr;
768 /** Offset 0x50 - TSC Offset. */
769 uint64_t u64TSCOffset;
770 /** Offset 0x58 - TLB control field. */
771 SVMTLBCTRL TLBCtrl;
772 /** Offset 0x60 - Interrupt control field. */
773 SVMINTCTRL IntCtrl;
774 /** Offset 0x68 - Interrupt shadow. */
775 SVMINTSHADOW IntShadow;
776 /** Offset 0x70 - Exit code. */
777 uint64_t u64ExitCode;
778 /** Offset 0x78 - Exit info 1. */
779 uint64_t u64ExitInfo1;
780 /** Offset 0x80 - Exit info 2. */
781 uint64_t u64ExitInfo2;
782 /** Offset 0x88 - Exit Interrupt info. */
783 SVMEVENT ExitIntInfo;
784 /** Offset 0x90 - Nested Paging control. */
785 SVMNP NestedPagingCtrl;
786 /** Offset 0x98 - AVIC APIC BAR. */
787 SVMAVIC AvicBar;
788 /** Offset 0xa0-0xa7 - Reserved. */
789 uint8_t u8Reserved1[0xa8 - 0xa0];
790 /** Offset 0xa8 - Event injection. */
791 SVMEVENT EventInject;
792 /** Offset 0xb0 - Host CR3 for nested paging. */
793 uint64_t u64NestedPagingCR3;
794 /** Offset 0xb8 - LBR Virtualization. */
795 SVMLBRVIRT LbrVirt;
796 /** Offset 0xc0 - VMCB Clean Bits. */
797 uint32_t u32VmcbCleanBits;
798 uint32_t u32Reserved0;
799 /** Offset 0xc8 - Next sequential instruction pointer. */
800 uint64_t u64NextRIP;
801 /** Offset 0xd0 - Number of bytes fetched. */
802 uint8_t cbInstrFetched;
803 /** Offset 0xd1 - Guest instruction bytes. */
804 uint8_t abInstr[SVM_CTRL_GUEST_INSTR_BYTES_MAX];
805 /** Offset 0xe0 - AVIC APIC_BACKING_PAGE pointer. */
806 SVMAVIC AvicBackingPagePtr;
807 /** Offset 0xe8-0xef - Reserved. */
808 uint8_t u8Reserved2[0xf0 - 0xe8];
809 /** Offset 0xf0 - AVIC LOGICAL_TABLE pointer. */
810 SVMAVIC AvicLogicalTablePtr;
811 /** Offset 0xf8 - AVIC PHYSICAL_TABLE pointer. */
812 SVMAVICPHYS AvicPhysicalTablePtr;
813} SVMVMCBCTRL;
814#pragma pack()
815/** Pointer to the SVMVMCBSTATESAVE structure. */
816typedef SVMVMCBCTRL *PSVMVMCBCTRL;
817/** Pointer to a const SVMVMCBSTATESAVE structure. */
818typedef const SVMVMCBCTRL *PCSVMVMCBCTRL;
819AssertCompileSize(SVMVMCBCTRL, 0x100);
820AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdCRx, 0x00);
821AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrCRx, 0x02);
822AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdDRx, 0x04);
823AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrDRx, 0x06);
824AssertCompileMemberOffset(SVMVMCBCTRL, u32InterceptXcpt, 0x08);
825AssertCompileMemberOffset(SVMVMCBCTRL, u64InterceptCtrl, 0x0c);
826AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved0, 0x14);
827AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterThreshold, 0x3c);
828AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterCount, 0x3e);
829AssertCompileMemberOffset(SVMVMCBCTRL, u64IOPMPhysAddr, 0x40);
830AssertCompileMemberOffset(SVMVMCBCTRL, u64MSRPMPhysAddr, 0x48);
831AssertCompileMemberOffset(SVMVMCBCTRL, u64TSCOffset, 0x50);
832AssertCompileMemberOffset(SVMVMCBCTRL, TLBCtrl, 0x58);
833AssertCompileMemberOffset(SVMVMCBCTRL, IntCtrl, 0x60);
834AssertCompileMemberOffset(SVMVMCBCTRL, IntShadow, 0x68);
835AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitCode, 0x70);
836AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo1, 0x78);
837AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo2, 0x80);
838AssertCompileMemberOffset(SVMVMCBCTRL, ExitIntInfo, 0x88);
839AssertCompileMemberOffset(SVMVMCBCTRL, NestedPagingCtrl, 0x90);
840AssertCompileMemberOffset(SVMVMCBCTRL, AvicBar, 0x98);
841AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved1, 0xa0);
842AssertCompileMemberOffset(SVMVMCBCTRL, EventInject, 0xa8);
843AssertCompileMemberOffset(SVMVMCBCTRL, u64NestedPagingCR3, 0xb0);
844AssertCompileMemberOffset(SVMVMCBCTRL, LbrVirt, 0xb8);
845AssertCompileMemberOffset(SVMVMCBCTRL, u32VmcbCleanBits, 0xc0);
846AssertCompileMemberOffset(SVMVMCBCTRL, u64NextRIP, 0xc8);
847AssertCompileMemberOffset(SVMVMCBCTRL, cbInstrFetched, 0xd0);
848AssertCompileMemberOffset(SVMVMCBCTRL, abInstr, 0xd1);
849AssertCompileMemberOffset(SVMVMCBCTRL, AvicBackingPagePtr, 0xe0);
850AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved2, 0xe8);
851AssertCompileMemberOffset(SVMVMCBCTRL, AvicLogicalTablePtr, 0xf0);
852AssertCompileMemberOffset(SVMVMCBCTRL, AvicPhysicalTablePtr, 0xf8);
853AssertCompileMemberSize(SVMVMCBCTRL, abInstr, 0x0f);
854
855/**
856 * SVM VMCB state save area.
857 */
858#pragma pack(1)
859typedef struct
860{
861 /** Offset 0x400 - Guest ES register + hidden parts. */
862 SVMSELREG ES;
863 /** Offset 0x410 - Guest CS register + hidden parts. */
864 SVMSELREG CS;
865 /** Offset 0x420 - Guest SS register + hidden parts. */
866 SVMSELREG SS;
867 /** Offset 0x430 - Guest DS register + hidden parts. */
868 SVMSELREG DS;
869 /** Offset 0x440 - Guest FS register + hidden parts. */
870 SVMSELREG FS;
871 /** Offset 0x450 - Guest GS register + hidden parts. */
872 SVMSELREG GS;
873 /** Offset 0x460 - Guest GDTR register. */
874 SVMGDTR GDTR;
875 /** Offset 0x470 - Guest LDTR register + hidden parts. */
876 SVMSELREG LDTR;
877 /** Offset 0x480 - Guest IDTR register. */
878 SVMIDTR IDTR;
879 /** Offset 0x490 - Guest TR register + hidden parts. */
880 SVMSELREG TR;
881 /** Offset 0x4A0-0x4CA - Reserved. */
882 uint8_t u8Reserved0[0x4cb - 0x4a0];
883 /** Offset 0x4CB - CPL. */
884 uint8_t u8CPL;
885 /** Offset 0x4CC-0x4CF - Reserved. */
886 uint8_t u8Reserved1[0x4d0 - 0x4cc];
887 /** Offset 0x4D0 - EFER. */
888 uint64_t u64EFER;
889 /** Offset 0x4D8-0x547 - Reserved. */
890 uint8_t u8Reserved2[0x548 - 0x4d8];
891 /** Offset 0x548 - CR4. */
892 uint64_t u64CR4;
893 /** Offset 0x550 - CR3. */
894 uint64_t u64CR3;
895 /** Offset 0x558 - CR0. */
896 uint64_t u64CR0;
897 /** Offset 0x560 - DR7. */
898 uint64_t u64DR7;
899 /** Offset 0x568 - DR6. */
900 uint64_t u64DR6;
901 /** Offset 0x570 - RFLAGS. */
902 uint64_t u64RFlags;
903 /** Offset 0x578 - RIP. */
904 uint64_t u64RIP;
905 /** Offset 0x580-0x5D7 - Reserved. */
906 uint8_t u8Reserved3[0x5d8 - 0x580];
907 /** Offset 0x5D8 - RSP. */
908 uint64_t u64RSP;
909 /** Offset 0x5E0-0x5F7 - Reserved. */
910 uint8_t u8Reserved4[0x5f8 - 0x5e0];
911 /** Offset 0x5F8 - RAX. */
912 uint64_t u64RAX;
913 /** Offset 0x600 - STAR. */
914 uint64_t u64STAR;
915 /** Offset 0x608 - LSTAR. */
916 uint64_t u64LSTAR;
917 /** Offset 0x610 - CSTAR. */
918 uint64_t u64CSTAR;
919 /** Offset 0x618 - SFMASK. */
920 uint64_t u64SFMASK;
921 /** Offset 0x620 - KernelGSBase. */
922 uint64_t u64KernelGSBase;
923 /** Offset 0x628 - SYSENTER_CS. */
924 uint64_t u64SysEnterCS;
925 /** Offset 0x630 - SYSENTER_ESP. */
926 uint64_t u64SysEnterESP;
927 /** Offset 0x638 - SYSENTER_EIP. */
928 uint64_t u64SysEnterEIP;
929 /** Offset 0x640 - CR2. */
930 uint64_t u64CR2;
931 /** Offset 0x648-0x667 - Reserved. */
932 uint8_t u8Reserved5[0x668 - 0x648];
933 /** Offset 0x668 - PAT (Page Attribute Table) MSR. */
934 uint64_t u64PAT;
935 /** Offset 0x670 - DBGCTL. */
936 uint64_t u64DBGCTL;
937 /** Offset 0x678 - BR_FROM. */
938 uint64_t u64BR_FROM;
939 /** Offset 0x680 - BR_TO. */
940 uint64_t u64BR_TO;
941 /** Offset 0x688 - LASTEXCPFROM. */
942 uint64_t u64LASTEXCPFROM;
943 /** Offset 0x690 - LASTEXCPTO. */
944 uint64_t u64LASTEXCPTO;
945} SVMVMCBSTATESAVE;
946#pragma pack()
947/** Pointer to the SVMVMCBSTATESAVE structure. */
948typedef SVMVMCBSTATESAVE *PSVMVMCBSTATESAVE;
949/** Pointer to a const SVMVMCBSTATESAVE structure. */
950typedef const SVMVMCBSTATESAVE *PCSVMVMCBSTATESAVE;
951AssertCompileSize(SVMVMCBSTATESAVE, 0x298);
952AssertCompileMemberOffset(SVMVMCBSTATESAVE, ES, 0x400 - 0x400);
953AssertCompileMemberOffset(SVMVMCBSTATESAVE, CS, 0x410 - 0x400);
954AssertCompileMemberOffset(SVMVMCBSTATESAVE, SS, 0x420 - 0x400);
955AssertCompileMemberOffset(SVMVMCBSTATESAVE, DS, 0x430 - 0x400);
956AssertCompileMemberOffset(SVMVMCBSTATESAVE, FS, 0x440 - 0x400);
957AssertCompileMemberOffset(SVMVMCBSTATESAVE, GS, 0x450 - 0x400);
958AssertCompileMemberOffset(SVMVMCBSTATESAVE, GDTR, 0x460 - 0x400);
959AssertCompileMemberOffset(SVMVMCBSTATESAVE, LDTR, 0x470 - 0x400);
960AssertCompileMemberOffset(SVMVMCBSTATESAVE, IDTR, 0x480 - 0x400);
961AssertCompileMemberOffset(SVMVMCBSTATESAVE, TR, 0x490 - 0x400);
962AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved0, 0x4a0 - 0x400);
963AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8CPL, 0x4cb - 0x400);
964AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved1, 0x4cc - 0x400);
965AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64EFER, 0x4d0 - 0x400);
966AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved2, 0x4d8 - 0x400);
967AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR4, 0x548 - 0x400);
968AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR3, 0x550 - 0x400);
969AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR0, 0x558 - 0x400);
970AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR7, 0x560 - 0x400);
971AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR6, 0x568 - 0x400);
972AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RFlags, 0x570 - 0x400);
973AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RIP, 0x578 - 0x400);
974AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved3, 0x580 - 0x400);
975AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RSP, 0x5d8 - 0x400);
976AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved4, 0x5e0 - 0x400);
977AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RAX, 0x5f8 - 0x400);
978AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64STAR, 0x600 - 0x400);
979AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LSTAR, 0x608 - 0x400);
980AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CSTAR, 0x610 - 0x400);
981AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SFMASK, 0x618 - 0x400);
982AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64KernelGSBase, 0x620 - 0x400);
983AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterCS, 0x628 - 0x400);
984AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterESP, 0x630 - 0x400);
985AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterEIP, 0x638 - 0x400);
986AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR2, 0x640 - 0x400);
987AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved5, 0x648 - 0x400);
988AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64PAT, 0x668 - 0x400);
989AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DBGCTL, 0x670 - 0x400);
990AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_FROM, 0x678 - 0x400);
991AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_TO, 0x680 - 0x400);
992AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPFROM, 0x688 - 0x400);
993AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPTO, 0x690 - 0x400);
994
995/**
996 * SVM VM Control Block. (VMCB)
997 */
998#pragma pack(1)
999typedef struct SVMVMCB
1000{
1001 /** Offset 0x00 - Control area. */
1002 SVMVMCBCTRL ctrl;
1003 /** Offset 0x100-0x3FF - Reserved. */
1004 uint8_t u8Reserved0[0x400 - 0x100];
1005 /** Offset 0x400 - State save area. */
1006 SVMVMCBSTATESAVE guest;
1007 /** Offset 0x698-0xFFF- Reserved. */
1008 uint8_t u8Reserved1[0x1000 - 0x698];
1009} SVMVMCB;
1010#pragma pack()
1011/** Pointer to the SVMVMCB structure. */
1012typedef SVMVMCB *PSVMVMCB;
1013/** Pointer to a const SVMVMCB structure. */
1014typedef const SVMVMCB *PCSVMVMCB;
1015AssertCompileMemberOffset(SVMVMCB, ctrl, 0x00);
1016AssertCompileMemberOffset(SVMVMCB, u8Reserved0, 0x100);
1017AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
1018AssertCompileMemberOffset(SVMVMCB, u8Reserved1, 0x698);
1019AssertCompileSize(SVMVMCB, 0x1000);
1020
1021/**
1022 * SVM MSRs.
1023 */
1024typedef struct SVMMSRS
1025{
1026 /** HWCR MSR. */
1027 uint64_t u64MsrHwcr;
1028 /** Reserved for future. */
1029 uint64_t u64Padding[27];
1030} SVMMSRS;
1031AssertCompileSizeAlignment(SVMMSRS, 8);
1032AssertCompileSize(SVMMSRS, 224);
1033/** Pointer to a SVMMSRS struct. */
1034typedef SVMMSRS *PSVMMSRS;
1035/** Pointer to a const SVMMSRS struct. */
1036typedef const SVMMSRS *PCSVMMSRS;
1037
1038/**
1039 * SVM nested-guest VMCB cache.
1040 *
1041 * Contains VMCB fields from the nested-guest VMCB before they're modified by
1042 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
1043 *
1044 * A VMCB field needs to be cached when it needs to be modified for execution using
1045 * hardware-assisted SVM and any of the following are true:
1046 * - If the original field needs to be inspected during execution of the
1047 * nested-guest or \#VMEXIT processing.
1048 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
1049 *
1050 * A VMCB field needs to be restored only when the field is written back to
1051 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
1052 * guest.
1053 *
1054 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
1055 * this structure.
1056 */
1057#pragma pack(1)
1058typedef struct SVMNESTEDVMCBCACHE
1059{
1060 /** Cache of CRX read intercepts. */
1061 uint16_t u16InterceptRdCRx;
1062 /** Cache of CRX write intercepts. */
1063 uint16_t u16InterceptWrCRx;
1064 /** Cache of DRX read intercepts. */
1065 uint16_t u16InterceptRdDRx;
1066 /** Cache of DRX write intercepts. */
1067 uint16_t u16InterceptWrDRx;
1068
1069 /** Cache of the pause-filter threshold. */
1070 uint16_t u16PauseFilterThreshold;
1071 /** Cache of the pause-filter count. */
1072 uint16_t u16PauseFilterCount;
1073
1074 /** Cache of exception intercepts. */
1075 uint32_t u32InterceptXcpt;
1076 /** Cache of control intercepts. */
1077 uint64_t u64InterceptCtrl;
1078
1079 /** Cache of the TSC offset. */
1080 uint64_t u64TSCOffset;
1081
1082 /** Cache of V_INTR_MASKING bit. */
1083 bool fVIntrMasking;
1084 /** Cache of the nested-paging bit. */
1085 bool fNestedPaging;
1086 /** Cache of the LBR virtualization bit. */
1087 bool fLbrVirt;
1088 /** Whether the VMCB is cached by HM. */
1089 bool fCacheValid;
1090 /** Alignment. */
1091 bool afPadding0[4];
1092} SVMNESTEDVMCBCACHE;
1093#pragma pack()
1094/** Pointer to the SVMNESTEDVMCBCACHE structure. */
1095typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
1096/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
1097typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
1098AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
1099
1100/**
1101 * Segment attribute conversion between CPU and AMD-V VMCB format.
1102 *
1103 * The CPU format of the segment attribute is described in X86DESCATTRBITS
1104 * which is 16-bits (i.e. includes 4 bits of the segment limit).
1105 *
1106 * The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
1107 * only the attribute bits and nothing else). Upper 4-bits are unused.
1108 */
1109#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0xf000) >> 4) )
1110#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0x0f00) << 4) )
1111
1112/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1113 * Copies the specified segment register to a VMCB from a virtual CPU context.
1114 *
1115 * @param a_pCtx The virtual-CPU context.
1116 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1117 * @param a_REG The segment register in the VMCB state-save
1118 * struct (ES/CS/SS/DS).
1119 * @param a_reg The segment register in the virtual CPU struct
1120 * (es/cs/ss/ds).
1121 */
1122#define HMSVM_SEG_REG_COPY_TO_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1123 do \
1124 { \
1125 Assert((a_pCtx)->a_reg.fFlags & CPUMSELREG_FLAGS_VALID); \
1126 Assert((a_pCtx)->a_reg.ValidSel == (a_pCtx)->a_reg.Sel); \
1127 (a_pVmcbStateSave)->a_REG.u16Sel = (a_pCtx)->a_reg.Sel; \
1128 (a_pVmcbStateSave)->a_REG.u32Limit = (a_pCtx)->a_reg.u32Limit; \
1129 (a_pVmcbStateSave)->a_REG.u64Base = (a_pCtx)->a_reg.u64Base; \
1130 (a_pVmcbStateSave)->a_REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR((a_pCtx)->a_reg.Attr.u); \
1131 } while (0)
1132
1133/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1134 * Copies the specified segment register from the VMCB to a virtual CPU
1135 * context.
1136 *
1137 * @param a_pCtx The virtual-CPU context.
1138 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1139 * @param a_REG The segment register in the VMCB state-save
1140 * struct (ES/CS/SS/DS).
1141 * @param a_reg The segment register in the virtual CPU struct
1142 * (es/ds/ss/ds).
1143 */
1144#define HMSVM_SEG_REG_COPY_FROM_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1145 do \
1146 { \
1147 (a_pCtx)->a_reg.Sel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1148 (a_pCtx)->a_reg.ValidSel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1149 (a_pCtx)->a_reg.fFlags = CPUMSELREG_FLAGS_VALID; \
1150 (a_pCtx)->a_reg.u32Limit = (a_pVmcbStateSave)->a_REG.u32Limit; \
1151 (a_pCtx)->a_reg.u64Base = (a_pVmcbStateSave)->a_REG.u64Base; \
1152 (a_pCtx)->a_reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR((a_pVmcbStateSave)->a_REG.u16Attr); \
1153 } while (0)
1154
1155
1156/** @defgroup grp_hm_svm_hwexec SVM Hardware-assisted execution Helpers
1157 *
1158 * These functions are only here because the inline functions in cpum.h calls them.
1159 * Don't add any more functions here unless there is no other option.
1160 * @{
1161 */
1162VMM_INT_DECL(bool) HMHasGuestSvmVmcbCached(PVMCPU pVCpu);
1163VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, uint64_t fIntercept);
1164VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, uint8_t uCr);
1165VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, uint8_t uCr);
1166VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, uint8_t uDr);
1167VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, uint8_t uDr);
1168VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, uint8_t uVector);
1169VMM_INT_DECL(bool) HMIsGuestSvmVirtIntrMasking(PVMCPU pVCpu);
1170VMM_INT_DECL(bool) HMIsGuestSvmNestedPagingEnabled(PVMCPU pVCpu);
1171VMM_INT_DECL(uint16_t) HMGetGuestSvmPauseFilterCount(PVMCPU pVCpu);
1172/** @} */
1173
1174
1175/** @} */
1176
1177#endif /* !VBOX_INCLUDED_vmm_hm_svm_h */
1178
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