VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 47764

Last change on this file since 47764 was 47760, checked in by vboxsync, 12 years ago

VMM/HM: Preemption hooks. Some common structural changes and cleanup, and initial imlementation
of VT-x/AMD-V specific hook functionality.. Work in progress.
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File size: 96.3 KB
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1/** @file
2 * HM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2013 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vmx_h
27#define ___VBox_vmm_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/x86.h>
32#include <iprt/assert.h>
33
34/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35 when targeting AMD64. */
36#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37# include <intrin.h>
38/* We always want them as intrinsics, no functions. */
39# pragma intrinsic(__vmx_on)
40# pragma intrinsic(__vmx_off)
41# pragma intrinsic(__vmx_vmclear)
42# pragma intrinsic(__vmx_vmptrld)
43# pragma intrinsic(__vmx_vmread)
44# pragma intrinsic(__vmx_vmwrite)
45# define VMX_USE_MSC_INTRINSICS 1
46#else
47# define VMX_USE_MSC_INTRINSICS 0
48#endif
49
50
51/** @defgroup grp_vmx vmx Types and Definitions
52 * @ingroup grp_hm
53 * @{
54 */
55
56/** @name Host-state restoration flags.
57 * @{
58 */
59/* If you change these values don't forget to update the assembly defines as well! */
60#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
61#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
62#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
63#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
64#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
65#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
66#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
67/** @} */
68
69/**
70 * Host-state restoration structure.
71 * This holds host-state fields that require manual restoration.
72 * Assembly version found in hm_vmx.mac (should be automatically verified).
73 */
74typedef struct VMXRESTOREHOST
75{
76 RTSEL uHostSelDS; /* 0x00 */
77 RTSEL uHostSelES; /* 0x02 */
78 RTSEL uHostSelFS; /* 0x04 */
79 RTSEL uHostSelGS; /* 0x06 */
80 RTSEL uHostSelTR; /* 0x08 */
81 uint8_t abPadding0[4];
82 X86XDTR64 HostGdtr; /**< 0x0e - should be aligned by it's 64-bit member. */
83 uint8_t abPadding1[6];
84 X86XDTR64 HostIdtr; /**< 0x1e - should be aligned by it's 64-bit member. */
85 uint64_t uHostFSBase; /* 0x28 */
86 uint64_t uHostGSBase; /* 0x30 */
87} VMXRESTOREHOST;
88/** Pointer to VMXRESTOREHOST. */
89typedef VMXRESTOREHOST *PVMXRESTOREHOST;
90AssertCompileSize(X86XDTR64, 10);
91AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
92AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
93AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
94AssertCompileSize(VMXRESTOREHOST, 56);
95
96/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
97 * @{
98 */
99/** An error occurred while checking invalid-guest-state. */
100#define VMX_IGS_ERROR 0
101/** The invalid guest-state checks did not find any reason why. */
102#define VMX_IGS_REASON_NOT_FOUND 1
103/** CR0 fixed1 bits invalid. */
104#define VMX_IGS_CR0_FIXED1 2
105/** CR0 fixed0 bits invalid. */
106#define VMX_IGS_CR0_FIXED0 3
107/** CR0.PE and CR0.PE invalid VT-x/host combination. */
108#define VMX_IGS_CR0_PG_PE_COMBO 4
109/** CR4 fixed1 bits invalid. */
110#define VMX_IGS_CR4_FIXED1 5
111/** CR4 fixed0 bits invalid. */
112#define VMX_IGS_CR4_FIXED0 6
113/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
114 * VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
115#define VMX_IGS_DEBUGCTL_MSR_RESERVED 7
116/** CR0.PG not set for long-mode when not using unrestricted guest. */
117#define VMX_IGS_CR0_PG_LONGMODE 8
118/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
119#define VMX_IGS_CR4_PAE_LONGMODE 9
120/** CR4.PCIDE set for 32-bit guest. */
121#define VMX_IGS_CR4_PCIDE 10
122/** VMCS' DR7 reserved bits not set to 0. */
123#define VMX_IGS_DR7_RESERVED 11
124/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
125#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12
126/** VMCS' EFER MSR reserved bits not set to 0. */
127#define VMX_IGS_EFER_MSR_RESERVED 13
128/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
129#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14
130/** VMCS' EFER MSR.LMA does not match CR0.PG of the guest when not using
131 * unrestricted guest. */
132#define VMX_IGS_EFER_LMA_PG_MISMATCH 15
133/** CS.Attr.P bit invalid. */
134#define VMX_IGS_CS_ATTR_P_INVALID 16
135/** CS.Attr reserved bits not set to 0. */
136#define VMX_IGS_CS_ATTR_RESERVED 17
137/** CS.Attr.G bit invalid. */
138#define VMX_IGS_CS_ATTR_G_INVALID 18
139/** CS is unusable. */
140#define VMX_IGS_CS_ATTR_UNUSABLE 19
141/** CS and SS DPL unequal. */
142#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20
143/** CS and SS DPL mismatch. */
144#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21
145/** CS Attr.Type invalid. */
146#define VMX_IGS_CS_ATTR_TYPE_INVALID 22
147/** CS and SS RPL unequal. */
148#define VMX_IGS_SS_CS_RPL_UNEQUAL 23
149/** SS.Attr.DPL and SS RPL unequal. */
150#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24
151/** SS.Attr.DPL invalid for segment type. */
152#define VMX_IGS_SS_ATTR_DPL_INVALID 25
153/** SS.Attr.Type invalid. */
154#define VMX_IGS_SS_ATTR_TYPE_INVALID 26
155/** SS.Attr.P bit invalid. */
156#define VMX_IGS_SS_ATTR_P_INVALID 27
157/** SS.Attr reserved bits not set to 0. */
158#define VMX_IGS_SS_ATTR_RESERVED 28
159/** SS.Attr.G bit invalid. */
160#define VMX_IGS_SS_ATTR_G_INVALID 29
161/** DS.Attr.A bit invalid. */
162#define VMX_IGS_DS_ATTR_A_INVALID 30
163/** DS.Attr.P bit invalid. */
164#define VMX_IGS_DS_ATTR_P_INVALID 31
165/** DS.Attr.DPL and DS RPL unequal. */
166#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32
167/** DS.Attr reserved bits not set to 0. */
168#define VMX_IGS_DS_ATTR_RESERVED 33
169/** DS.Attr.G bit invalid. */
170#define VMX_IGS_DS_ATTR_G_INVALID 34
171/** DS.Attr.Type invalid. */
172#define VMX_IGS_DS_ATTR_TYPE_INVALID 35
173/** ES.Attr.A bit invalid. */
174#define VMX_IGS_ES_ATTR_A_INVALID 36
175/** ES.Attr.P bit invalid. */
176#define VMX_IGS_ES_ATTR_P_INVALID 37
177/** ES.Attr.DPL and DS RPL unequal. */
178#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38
179/** ES.Attr reserved bits not set to 0. */
180#define VMX_IGS_ES_ATTR_RESERVED 39
181/** ES.Attr.G bit invalid. */
182#define VMX_IGS_ES_ATTR_G_INVALID 40
183/** ES.Attr.Type invalid. */
184#define VMX_IGS_ES_ATTR_TYPE_INVALID 41
185/** FS.Attr.A bit invalid. */
186#define VMX_IGS_FS_ATTR_A_INVALID 42
187/** FS.Attr.P bit invalid. */
188#define VMX_IGS_FS_ATTR_P_INVALID 43
189/** FS.Attr.DPL and DS RPL unequal. */
190#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44
191/** FS.Attr reserved bits not set to 0. */
192#define VMX_IGS_FS_ATTR_RESERVED 45
193/** FS.Attr.G bit invalid. */
194#define VMX_IGS_FS_ATTR_G_INVALID 46
195/** FS.Attr.Type invalid. */
196#define VMX_IGS_FS_ATTR_TYPE_INVALID 47
197/** GS.Attr.A bit invalid. */
198#define VMX_IGS_GS_ATTR_A_INVALID 48
199/** GS.Attr.P bit invalid. */
200#define VMX_IGS_GS_ATTR_P_INVALID 49
201/** GS.Attr.DPL and DS RPL unequal. */
202#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 50
203/** GS.Attr reserved bits not set to 0. */
204#define VMX_IGS_GS_ATTR_RESERVED 51
205/** GS.Attr.G bit invalid. */
206#define VMX_IGS_GS_ATTR_G_INVALID 52
207/** GS.Attr.Type invalid. */
208#define VMX_IGS_GS_ATTR_TYPE_INVALID 53
209/** V86 mode CS.Base invalid. */
210#define VMX_IGS_V86_CS_BASE_INVALID 54
211/** V86 mode CS.Limit invalid. */
212#define VMX_IGS_V86_CS_LIMIT_INVALID 55
213/** V86 mode CS.Attr invalid. */
214#define VMX_IGS_V86_CS_ATTR_INVALID 56
215/** V86 mode SS.Base invalid. */
216#define VMX_IGS_V86_SS_BASE_INVALID 57
217/** V86 mode SS.Limit invalid. */
218#define VMX_IGS_V86_SS_LIMIT_INVALID 59
219/** V86 mode SS.Attr invalid. */
220#define VMX_IGS_V86_SS_ATTR_INVALID 59
221/** V86 mode DS.Base invalid. */
222#define VMX_IGS_V86_DS_BASE_INVALID 60
223/** V86 mode DS.Limit invalid. */
224#define VMX_IGS_V86_DS_LIMIT_INVALID 61
225/** V86 mode DS.Attr invalid. */
226#define VMX_IGS_V86_DS_ATTR_INVALID 62
227/** V86 mode ES.Base invalid. */
228#define VMX_IGS_V86_ES_BASE_INVALID 63
229/** V86 mode ES.Limit invalid. */
230#define VMX_IGS_V86_ES_LIMIT_INVALID 64
231/** V86 mode ES.Attr invalid. */
232#define VMX_IGS_V86_ES_ATTR_INVALID 65
233/** V86 mode FS.Base invalid. */
234#define VMX_IGS_V86_FS_BASE_INVALID 66
235/** V86 mode FS.Limit invalid. */
236#define VMX_IGS_V86_FS_LIMIT_INVALID 67
237/** V86 mode FS.Attr invalid. */
238#define VMX_IGS_V86_FS_ATTR_INVALID 68
239/** V86 mode GS.Base invalid. */
240#define VMX_IGS_V86_GS_BASE_INVALID 69
241/** V86 mode GS.Limit invalid. */
242#define VMX_IGS_V86_GS_LIMIT_INVALID 70
243/** V86 mode GS.Attr invalid. */
244#define VMX_IGS_V86_GS_ATTR_INVALID 71
245/** Longmode CS.Base invalid. */
246#define VMX_IGS_LONGMODE_CS_BASE_INVALID 72
247/** Longmode SS.Base invalid. */
248#define VMX_IGS_LONGMODE_SS_BASE_INVALID 73
249/** Longmode DS.Base invalid. */
250#define VMX_IGS_LONGMODE_DS_BASE_INVALID 74
251/** Longmode ES.Base invalid. */
252#define VMX_IGS_LONGMODE_ES_BASE_INVALID 75
253/** SYSENTER ESP is not canonical. */
254#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76
255/** SYSENTER EIP is not canonical. */
256#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77
257/** PAT MSR invalid. */
258#define VMX_IGS_PAT_MSR_INVALID 78
259/** PAT MSR reserved bits not set to 0. */
260#define VMX_IGS_PAT_MSR_RESERVED 79
261/** GDTR.Base is not canonical. */
262#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80
263/** IDTR.Base is not canonical. */
264#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81
265/** GDTR.Limit invalid. */
266#define VMX_IGS_GDTR_LIMIT_INVALID 82
267/** IDTR.Limit invalid. */
268#define VMX_IGS_IDTR_LIMIT_INVALID 83
269/** Longmode RIP is invalid. */
270#define VMX_IGS_LONGMODE_RIP_INVALID 84
271/** RFLAGS reserved bits not set to 0. */
272#define VMX_IGS_RFLAGS_RESERVED 85
273/** RFLAGS RA1 reserved bits not set to 1. */
274#define VMX_IGS_RFLAGS_RESERVED1 86
275/** RFLAGS.VM (V86 mode) invalid. */
276#define VMX_IGS_RFLAGS_VM_INVALID 87
277/** RFLAGS.IF invalid. */
278#define VMX_IGS_RFLAGS_IF_INVALID 88
279/** Activity state invalid. */
280#define VMX_IGS_ACTIVITY_STATE_INVALID 89
281/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
282#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90
283/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
284#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91
285/** Activity state SIPI WAIT invalid. */
286#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92
287/** Interruptibility state reserved bits not set to 0. */
288#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93
289/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
290#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94
291/** Interruptibility state block-by-STI invalid for EFLAGS. */
292#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95
293/** Interruptibility state invalid while trying to deliver external
294 * interrupt. */
295#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96
296/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
297 * NMI. */
298#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97
299/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
300#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98
301/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
302#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99
303/** Interruptibilty state block-by-STI (maybe) invalid when trying to deliver
304 * an NMI. */
305#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100
306/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
307 * active. */
308#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101
309/** Pending debug exceptions reserved bits not set to 0. */
310#define VMX_IGS_PENDING_DEBUG_RESERVED 102
311/** Longmode pending debug exceptions reserved bits not set to 0. */
312#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103
313/** Pending debug exceptions.BS bit is not set when it should be. */
314#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104
315/** Pending debug exceptions.BS bit is not clear when it should be. */
316#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105
317/** VMCS link pointer reserved bits not set to 0. */
318#define VMX_IGS_VMCS_LINK_PTR_RESERVED 106
319/** TR cannot index into LDT, TI bit MBZ. */
320#define VMX_IGS_TR_TI_INVALID 107
321/** LDTR cannot index into LDT. TI bit MBZ. */
322#define VMX_IGS_LDTR_TI_INVALID 108
323/** TR.Base is not canonical. */
324#define VMX_IGS_TR_BASE_NOT_CANONICAL 109
325/** FS.Base is not canonical. */
326#define VMX_IGS_FS_BASE_NOT_CANONICAL 110
327/** GS.Base is not canonical. */
328#define VMX_IGS_GS_BASE_NOT_CANONICAL 111
329/** LDTR.Base is not canonical. */
330#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 112
331/** TR is unusable. */
332#define VMX_IGS_TR_ATTR_UNUSABLE 113
333/** TR.Attr.S bit invalid. */
334#define VMX_IGS_TR_ATTR_S_INVALID 114
335/** TR is not present. */
336#define VMX_IGS_TR_ATTR_P_INVALID 115
337/** TR.Attr reserved bits not set to 0. */
338#define VMX_IGS_TR_ATTR_RESERVED 116
339/** TR.Attr.G bit invalid. */
340#define VMX_IGS_TR_ATTR_G_INVALID 117
341/** Longmode TR.Attr.Type invalid. */
342#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 118
343/** TR.Attr.Type invalid. */
344#define VMX_IGS_TR_ATTR_TYPE_INVALID 119
345/** CS.Attr.S invalid. */
346#define VMX_IGS_CS_ATTR_S_INVALID 120
347/** CS.Attr.DPL invalid. */
348#define VMX_IGS_CS_ATTR_DPL_INVALID 121
349/** @} */
350
351/** @name VMX VMCS-Read cache indices.
352 * @{
353 */
354#ifndef VBOX_WITH_OLD_VTX_CODE
355# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
356# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
357# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
358# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
359# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
360# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
361# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
362# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
363# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
364# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
365# define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
366# define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
367# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
368# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
369# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
370# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
371# define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
372# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
373#else /* VBOX_WITH_OLD_VTX_CODE */
374# define VMX_VMCS_GUEST_RIP_CACHE_IDX 0
375# define VMX_VMCS_GUEST_RSP_CACHE_IDX 1
376# define VMX_VMCS_GUEST_RFLAGS_CACHE_IDX 2
377# define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE_CACHE_IDX 3
378# define VMX_VMCS_CTRL_CR0_READ_SHADOW_CACHE_IDX 4
379# define VMX_VMCS_GUEST_CR0_CACHE_IDX 5
380# define VMX_VMCS_CTRL_CR4_READ_SHADOW_CACHE_IDX 6
381# define VMX_VMCS_GUEST_CR4_CACHE_IDX 7
382# define VMX_VMCS_GUEST_DR7_CACHE_IDX 8
383# define VMX_VMCS32_GUEST_SYSENTER_CS_CACHE_IDX 9
384# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 10
385# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 11
386# define VMX_VMCS32_GUEST_GDTR_LIMIT_CACHE_IDX 12
387# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 13
388# define VMX_VMCS32_GUEST_IDTR_LIMIT_CACHE_IDX 14
389# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 15
390# define VMX_VMCS16_GUEST_FIELD_CS_CACHE_IDX 16
391# define VMX_VMCS32_GUEST_CS_LIMIT_CACHE_IDX 17
392# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 18
393# define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS_CACHE_IDX 19
394# define VMX_VMCS16_GUEST_FIELD_DS_CACHE_IDX 20
395# define VMX_VMCS32_GUEST_DS_LIMIT_CACHE_IDX 21
396# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 22
397# define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS_CACHE_IDX 23
398# define VMX_VMCS16_GUEST_FIELD_ES_CACHE_IDX 24
399# define VMX_VMCS32_GUEST_ES_LIMIT_CACHE_IDX 25
400# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 26
401# define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS_CACHE_IDX 27
402# define VMX_VMCS16_GUEST_FIELD_FS_CACHE_IDX 28
403# define VMX_VMCS32_GUEST_FS_LIMIT_CACHE_IDX 29
404# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 30
405# define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS_CACHE_IDX 31
406# define VMX_VMCS16_GUEST_FIELD_GS_CACHE_IDX 32
407# define VMX_VMCS32_GUEST_GS_LIMIT_CACHE_IDX 33
408# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 34
409# define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS_CACHE_IDX 35
410# define VMX_VMCS16_GUEST_FIELD_SS_CACHE_IDX 36
411# define VMX_VMCS32_GUEST_SS_LIMIT_CACHE_IDX 37
412# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 38
413# define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS_CACHE_IDX 39
414# define VMX_VMCS16_GUEST_FIELD_TR_CACHE_IDX 40
415# define VMX_VMCS32_GUEST_TR_LIMIT_CACHE_IDX 41
416# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 42
417# define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS_CACHE_IDX 43
418# define VMX_VMCS16_GUEST_FIELD_LDTR_CACHE_IDX 44
419# define VMX_VMCS32_GUEST_LDTR_LIMIT_CACHE_IDX 45
420# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 46
421# define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS_CACHE_IDX 47
422# define VMX_VMCS32_RO_EXIT_REASON_CACHE_IDX 48
423# define VMX_VMCS32_RO_VM_INSTR_ERROR_CACHE_IDX 49
424# define VMX_VMCS32_RO_EXIT_INSTR_LENGTH_CACHE_IDX 50
425# define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE_CACHE_IDX 51
426# define VMX_VMCS32_RO_EXIT_INSTR_INFO_CACHE_IDX 52
427# define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO_CACHE_IDX 53
428# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 54
429# define VMX_VMCS32_RO_IDT_INFO_CACHE_IDX 55
430# define VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX 56
431# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX + 1)
432# define VMX_VMCS_GUEST_CR3_CACHE_IDX 57
433# define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX 58
434# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX + 1)
435#endif /* VBOX_WITH_OLD_VTX_CODE */
436/** @} */
437
438/** @name VMX EPT paging structures
439 * @{
440 */
441
442/**
443 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
444 */
445#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
446
447/**
448 * EPT Page Directory Pointer Entry. Bit view.
449 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
450 * this did cause trouble with one compiler/version).
451 */
452#pragma pack(1)
453typedef struct EPTPML4EBITS
454{
455 /** Present bit. */
456 uint64_t u1Present : 1;
457 /** Writable bit. */
458 uint64_t u1Write : 1;
459 /** Executable bit. */
460 uint64_t u1Execute : 1;
461 /** Reserved (must be 0). */
462 uint64_t u5Reserved : 5;
463 /** Available for software. */
464 uint64_t u4Available : 4;
465 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
466 uint64_t u40PhysAddr : 40;
467 /** Availabe for software. */
468 uint64_t u12Available : 12;
469} EPTPML4EBITS;
470#pragma pack()
471AssertCompileSize(EPTPML4EBITS, 8);
472
473/** Bits 12-51 - - EPT - Physical Page number of the next level. */
474#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
475/** The page shift to get the PML4 index. */
476#define EPT_PML4_SHIFT X86_PML4_SHIFT
477/** The PML4 index mask (apply to a shifted page address). */
478#define EPT_PML4_MASK X86_PML4_MASK
479
480/**
481 * EPT PML4E.
482 */
483#pragma pack(1)
484typedef union EPTPML4E
485{
486 /** Normal view. */
487 EPTPML4EBITS n;
488 /** Unsigned integer view. */
489 X86PGPAEUINT u;
490 /** 64 bit unsigned integer view. */
491 uint64_t au64[1];
492 /** 32 bit unsigned integer view. */
493 uint32_t au32[2];
494} EPTPML4E;
495#pragma pack()
496/** Pointer to a PML4 table entry. */
497typedef EPTPML4E *PEPTPML4E;
498/** Pointer to a const PML4 table entry. */
499typedef const EPTPML4E *PCEPTPML4E;
500AssertCompileSize(EPTPML4E, 8);
501
502/**
503 * EPT PML4 Table.
504 */
505#pragma pack(1)
506typedef struct EPTPML4
507{
508 EPTPML4E a[EPT_PG_ENTRIES];
509} EPTPML4;
510#pragma pack()
511/** Pointer to an EPT PML4 Table. */
512typedef EPTPML4 *PEPTPML4;
513/** Pointer to a const EPT PML4 Table. */
514typedef const EPTPML4 *PCEPTPML4;
515
516/**
517 * EPT Page Directory Pointer Entry. Bit view.
518 */
519#pragma pack(1)
520typedef struct EPTPDPTEBITS
521{
522 /** Present bit. */
523 uint64_t u1Present : 1;
524 /** Writable bit. */
525 uint64_t u1Write : 1;
526 /** Executable bit. */
527 uint64_t u1Execute : 1;
528 /** Reserved (must be 0). */
529 uint64_t u5Reserved : 5;
530 /** Available for software. */
531 uint64_t u4Available : 4;
532 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
533 uint64_t u40PhysAddr : 40;
534 /** Availabe for software. */
535 uint64_t u12Available : 12;
536} EPTPDPTEBITS;
537#pragma pack()
538AssertCompileSize(EPTPDPTEBITS, 8);
539
540/** Bits 12-51 - - EPT - Physical Page number of the next level. */
541#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
542/** The page shift to get the PDPT index. */
543#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
544/** The PDPT index mask (apply to a shifted page address). */
545#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
546
547/**
548 * EPT Page Directory Pointer.
549 */
550#pragma pack(1)
551typedef union EPTPDPTE
552{
553 /** Normal view. */
554 EPTPDPTEBITS n;
555 /** Unsigned integer view. */
556 X86PGPAEUINT u;
557 /** 64 bit unsigned integer view. */
558 uint64_t au64[1];
559 /** 32 bit unsigned integer view. */
560 uint32_t au32[2];
561} EPTPDPTE;
562#pragma pack()
563/** Pointer to an EPT Page Directory Pointer Entry. */
564typedef EPTPDPTE *PEPTPDPTE;
565/** Pointer to a const EPT Page Directory Pointer Entry. */
566typedef const EPTPDPTE *PCEPTPDPTE;
567AssertCompileSize(EPTPDPTE, 8);
568
569/**
570 * EPT Page Directory Pointer Table.
571 */
572#pragma pack(1)
573typedef struct EPTPDPT
574{
575 EPTPDPTE a[EPT_PG_ENTRIES];
576} EPTPDPT;
577#pragma pack()
578/** Pointer to an EPT Page Directory Pointer Table. */
579typedef EPTPDPT *PEPTPDPT;
580/** Pointer to a const EPT Page Directory Pointer Table. */
581typedef const EPTPDPT *PCEPTPDPT;
582
583
584/**
585 * EPT Page Directory Table Entry. Bit view.
586 */
587#pragma pack(1)
588typedef struct EPTPDEBITS
589{
590 /** Present bit. */
591 uint64_t u1Present : 1;
592 /** Writable bit. */
593 uint64_t u1Write : 1;
594 /** Executable bit. */
595 uint64_t u1Execute : 1;
596 /** Reserved (must be 0). */
597 uint64_t u4Reserved : 4;
598 /** Big page (must be 0 here). */
599 uint64_t u1Size : 1;
600 /** Available for software. */
601 uint64_t u4Available : 4;
602 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
603 uint64_t u40PhysAddr : 40;
604 /** Availabe for software. */
605 uint64_t u12Available : 12;
606} EPTPDEBITS;
607#pragma pack()
608AssertCompileSize(EPTPDEBITS, 8);
609
610/** Bits 12-51 - - EPT - Physical Page number of the next level. */
611#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
612/** The page shift to get the PD index. */
613#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
614/** The PD index mask (apply to a shifted page address). */
615#define EPT_PD_MASK X86_PD_PAE_MASK
616
617/**
618 * EPT 2MB Page Directory Table Entry. Bit view.
619 */
620#pragma pack(1)
621typedef struct EPTPDE2MBITS
622{
623 /** Present bit. */
624 uint64_t u1Present : 1;
625 /** Writable bit. */
626 uint64_t u1Write : 1;
627 /** Executable bit. */
628 uint64_t u1Execute : 1;
629 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
630 uint64_t u3EMT : 3;
631 /** Ignore PAT memory type */
632 uint64_t u1IgnorePAT : 1;
633 /** Big page (must be 1 here). */
634 uint64_t u1Size : 1;
635 /** Available for software. */
636 uint64_t u4Available : 4;
637 /** Reserved (must be 0). */
638 uint64_t u9Reserved : 9;
639 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
640 uint64_t u31PhysAddr : 31;
641 /** Availabe for software. */
642 uint64_t u12Available : 12;
643} EPTPDE2MBITS;
644#pragma pack()
645AssertCompileSize(EPTPDE2MBITS, 8);
646
647/** Bits 21-51 - - EPT - Physical Page number of the next level. */
648#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
649
650/**
651 * EPT Page Directory Table Entry.
652 */
653#pragma pack(1)
654typedef union EPTPDE
655{
656 /** Normal view. */
657 EPTPDEBITS n;
658 /** 2MB view (big). */
659 EPTPDE2MBITS b;
660 /** Unsigned integer view. */
661 X86PGPAEUINT u;
662 /** 64 bit unsigned integer view. */
663 uint64_t au64[1];
664 /** 32 bit unsigned integer view. */
665 uint32_t au32[2];
666} EPTPDE;
667#pragma pack()
668/** Pointer to an EPT Page Directory Table Entry. */
669typedef EPTPDE *PEPTPDE;
670/** Pointer to a const EPT Page Directory Table Entry. */
671typedef const EPTPDE *PCEPTPDE;
672AssertCompileSize(EPTPDE, 8);
673
674/**
675 * EPT Page Directory Table.
676 */
677#pragma pack(1)
678typedef struct EPTPD
679{
680 EPTPDE a[EPT_PG_ENTRIES];
681} EPTPD;
682#pragma pack()
683/** Pointer to an EPT Page Directory Table. */
684typedef EPTPD *PEPTPD;
685/** Pointer to a const EPT Page Directory Table. */
686typedef const EPTPD *PCEPTPD;
687
688
689/**
690 * EPT Page Table Entry. Bit view.
691 */
692#pragma pack(1)
693typedef struct EPTPTEBITS
694{
695 /** 0 - Present bit.
696 * @remark This is a convenience "misnomer". The bit actually indicates
697 * read access and the CPU will consider an entry with any of the
698 * first three bits set as present. Since all our valid entries
699 * will have this bit set, it can be used as a present indicator
700 * and allow some code sharing. */
701 uint64_t u1Present : 1;
702 /** 1 - Writable bit. */
703 uint64_t u1Write : 1;
704 /** 2 - Executable bit. */
705 uint64_t u1Execute : 1;
706 /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
707 uint64_t u3EMT : 3;
708 /** 6 - Ignore PAT memory type */
709 uint64_t u1IgnorePAT : 1;
710 /** 11:7 - Available for software. */
711 uint64_t u5Available : 5;
712 /** 51:12 - Physical address of page. Restricted by maximum physical
713 * address width of the cpu. */
714 uint64_t u40PhysAddr : 40;
715 /** 63:52 - Available for software. */
716 uint64_t u12Available : 12;
717} EPTPTEBITS;
718#pragma pack()
719AssertCompileSize(EPTPTEBITS, 8);
720
721/** Bits 12-51 - - EPT - Physical Page number of the next level. */
722#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
723/** The page shift to get the EPT PTE index. */
724#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
725/** The EPT PT index mask (apply to a shifted page address). */
726#define EPT_PT_MASK X86_PT_PAE_MASK
727
728/**
729 * EPT Page Table Entry.
730 */
731#pragma pack(1)
732typedef union EPTPTE
733{
734 /** Normal view. */
735 EPTPTEBITS n;
736 /** Unsigned integer view. */
737 X86PGPAEUINT u;
738 /** 64 bit unsigned integer view. */
739 uint64_t au64[1];
740 /** 32 bit unsigned integer view. */
741 uint32_t au32[2];
742} EPTPTE;
743#pragma pack()
744/** Pointer to an EPT Page Directory Table Entry. */
745typedef EPTPTE *PEPTPTE;
746/** Pointer to a const EPT Page Directory Table Entry. */
747typedef const EPTPTE *PCEPTPTE;
748AssertCompileSize(EPTPTE, 8);
749
750/**
751 * EPT Page Table.
752 */
753#pragma pack(1)
754typedef struct EPTPT
755{
756 EPTPTE a[EPT_PG_ENTRIES];
757} EPTPT;
758#pragma pack()
759/** Pointer to an extended page table. */
760typedef EPTPT *PEPTPT;
761/** Pointer to a const extended table. */
762typedef const EPTPT *PCEPTPT;
763
764/**
765 * VPID flush types.
766 */
767typedef enum
768{
769 /** Invalidate a specific page. */
770 VMX_FLUSH_VPID_INDIV_ADDR = 0,
771 /** Invalidate one context (specific VPID). */
772 VMX_FLUSH_VPID_SINGLE_CONTEXT = 1,
773 /** Invalidate all contexts (all VPIDs). */
774 VMX_FLUSH_VPID_ALL_CONTEXTS = 2,
775 /** Invalidate a single VPID context retaining global mappings. */
776 VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
777 /** Unsupported by VirtualBox. */
778 VMX_FLUSH_VPID_NOT_SUPPORTED = 0xbad,
779 /** Unsupported by CPU. */
780 VMX_FLUSH_VPID_NONE = 0xb00,
781 /** 32bit hackishness. */
782 VMX_FLUSH_VPID_32BIT_HACK = 0x7fffffff
783} VMX_FLUSH_VPID;
784
785/**
786 * EPT flush types.
787 */
788typedef enum
789{
790 /** Invalidate one context (specific EPT). */
791 VMX_FLUSH_EPT_SINGLE_CONTEXT = 1,
792 /* Invalidate all contexts (all EPTs) */
793 VMX_FLUSH_EPT_ALL_CONTEXTS = 2,
794 /** Unsupported by VirtualBox. */
795 VMX_FLUSH_EPT_NOT_SUPPORTED = 0xbad,
796 /** Unsupported by CPU. */
797 VMX_FLUSH_EPT_NONE = 0xb00,
798 /** 32bit hackishness. */
799 VMX_FLUSH_EPT_32BIT_HACK = 0x7fffffff
800} VMX_FLUSH_EPT;
801/** @} */
802
803/** @name MSR autoload/store elements
804 * @{
805 */
806#pragma pack(1)
807typedef struct
808{
809 uint32_t u32IndexMSR;
810 uint32_t u32Reserved;
811 uint64_t u64Value;
812} VMXMSR;
813#pragma pack()
814/** Pointer to an MSR load/store element. */
815typedef VMXMSR *PVMXMSR;
816/** Pointer to a const MSR load/store element. */
817typedef const VMXMSR *PCVMXMSR;
818
819/** @} */
820
821
822/** @name VMX-capability qword
823 * @{
824 */
825#pragma pack(1)
826typedef union
827{
828 struct
829 {
830 /** Bits set here -must- be set in the correpsonding VM-execution controls. */
831 uint32_t disallowed0;
832 /** Bits cleared here -must- be cleared in the corresponding VM-execution
833 * controls. */
834 uint32_t allowed1;
835 } n;
836 uint64_t u;
837} VMX_CAPABILITY;
838#pragma pack()
839/** @} */
840
841/** @name VMX EFLAGS reserved bits.
842 * @{
843 */
844/** And-mask for setting reserved bits to zero */
845#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
846/** Or-mask for setting reserved bits to 1 */
847#define VMX_EFLAGS_RESERVED_1 0x00000002
848/** @} */
849
850/** @name VMX Basic Exit Reasons.
851 * @{
852 */
853/** -1 Invalid exit code */
854#define VMX_EXIT_INVALID -1
855/** 0 Exception or non-maskable interrupt (NMI). */
856#define VMX_EXIT_XCPT_OR_NMI 0
857/** 1 External interrupt. */
858#define VMX_EXIT_EXT_INT 1
859/** 2 Triple fault. */
860#define VMX_EXIT_TRIPLE_FAULT 2
861/** 3 INIT signal. */
862#define VMX_EXIT_INIT_SIGNAL 3
863/** 4 Start-up IPI (SIPI). */
864#define VMX_EXIT_SIPI 4
865/** 5 I/O system-management interrupt (SMI). */
866#define VMX_EXIT_IO_SMI 5
867/** 6 Other SMI. */
868#define VMX_EXIT_SMI 6
869/** 7 Interrupt window exiting. */
870#define VMX_EXIT_INT_WINDOW 7
871/** 8 NMI window exiting. */
872#define VMX_EXIT_NMI_WINDOW 8
873/** 9 Task switch. */
874#define VMX_EXIT_TASK_SWITCH 9
875/** 10 Guest software attempted to execute CPUID. */
876#define VMX_EXIT_CPUID 10
877/** 10 Guest software attempted to execute GETSEC. */
878#define VMX_EXIT_GETSEC 11
879/** 12 Guest software attempted to execute HLT. */
880#define VMX_EXIT_HLT 12
881/** 13 Guest software attempted to execute INVD. */
882#define VMX_EXIT_INVD 13
883/** 14 Guest software attempted to execute INVLPG. */
884#define VMX_EXIT_INVLPG 14
885/** 15 Guest software attempted to execute RDPMC. */
886#define VMX_EXIT_RDPMC 15
887/** 16 Guest software attempted to execute RDTSC. */
888#define VMX_EXIT_RDTSC 16
889/** 17 Guest software attempted to execute RSM in SMM. */
890#define VMX_EXIT_RSM 17
891/** 18 Guest software executed VMCALL. */
892#define VMX_EXIT_VMCALL 18
893/** 19 Guest software executed VMCLEAR. */
894#define VMX_EXIT_VMCLEAR 19
895/** 20 Guest software executed VMLAUNCH. */
896#define VMX_EXIT_VMLAUNCH 20
897/** 21 Guest software executed VMPTRLD. */
898#define VMX_EXIT_VMPTRLD 21
899/** 22 Guest software executed VMPTRST. */
900#define VMX_EXIT_VMPTRST 22
901/** 23 Guest software executed VMREAD. */
902#define VMX_EXIT_VMREAD 23
903/** 24 Guest software executed VMRESUME. */
904#define VMX_EXIT_VMRESUME 24
905/** 25 Guest software executed VMWRITE. */
906#define VMX_EXIT_VMWRITE 25
907/** 26 Guest software executed VMXOFF. */
908#define VMX_EXIT_VMXOFF 26
909/** 27 Guest software executed VMXON. */
910#define VMX_EXIT_VMXON 27
911/** 28 Control-register accesses. */
912#define VMX_EXIT_MOV_CRX 28
913/** 29 Debug-register accesses. */
914#define VMX_EXIT_MOV_DRX 29
915/** 30 I/O instruction. */
916#define VMX_EXIT_IO_INSTR 30
917/** 31 RDMSR. Guest software attempted to execute RDMSR. */
918#define VMX_EXIT_RDMSR 31
919/** 32 WRMSR. Guest software attempted to execute WRMSR. */
920#define VMX_EXIT_WRMSR 32
921/** 33 VM-entry failure due to invalid guest state. */
922#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
923/** 34 VM-entry failure due to MSR loading. */
924#define VMX_EXIT_ERR_MSR_LOAD 34
925/** 36 Guest software executed MWAIT. */
926#define VMX_EXIT_MWAIT 36
927/** 37 VM exit due to monitor trap flag. */
928#define VMX_EXIT_MTF 37
929/** 39 Guest software attempted to execute MONITOR. */
930#define VMX_EXIT_MONITOR 39
931/** 40 Guest software attempted to execute PAUSE. */
932#define VMX_EXIT_PAUSE 40
933/** 41 VM-entry failure due to machine-check. */
934#define VMX_EXIT_ERR_MACHINE_CHECK 41
935/** 43 TPR below threshold. Guest software executed MOV to CR8. */
936#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
937/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
938#define VMX_EXIT_APIC_ACCESS 44
939/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
940#define VMX_EXIT_XDTR_ACCESS 46
941/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
942#define VMX_EXIT_TR_ACCESS 47
943/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
944#define VMX_EXIT_EPT_VIOLATION 48
945/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
946#define VMX_EXIT_EPT_MISCONFIG 49
947/** 50 INVEPT. Guest software attempted to execute INVEPT. */
948#define VMX_EXIT_INVEPT 50
949/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
950#define VMX_EXIT_RDTSCP 51
951/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
952#define VMX_EXIT_PREEMPT_TIMER 52
953/** 53 INVVPID. Guest software attempted to execute INVVPID. */
954#define VMX_EXIT_INVVPID 53
955/** 54 WBINVD. Guest software attempted to execute WBINVD. */
956#define VMX_EXIT_WBINVD 54
957/** 55 XSETBV. Guest software attempted to execute XSETBV. */
958#define VMX_EXIT_XSETBV 55
959/** 57 RDRAND. Guest software attempted to execute RDRAND. */
960#define VMX_EXIT_RDRAND 57
961/** 58 INVPCID. Guest software attempted to execute INVPCID. */
962#define VMX_EXIT_INVPCID 58
963/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
964#define VMX_EXIT_VMFUNC 59
965/** The maximum exit value (inclusive). */
966#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
967/** @} */
968
969
970/** @name VM Instruction Errors
971 * @{
972 */
973/** VMCALL executed in VMX root operation. */
974#define VMX_ERROR_VMCALL 1
975/** VMCLEAR with invalid physical address. */
976#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
977/** VMCLEAR with VMXON pointer. */
978#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
979/** VMLAUNCH with non-clear VMCS. */
980#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
981/** VMRESUME with non-launched VMCS. */
982#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
983/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
984#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
985/** VM-entry with invalid control field(s). */
986#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
987/** VM-entry with invalid host-state field(s). */
988#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
989/** VMPTRLD with invalid physical address. */
990#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
991/** VMPTRLD with VMXON pointer. */
992#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
993/** VMPTRLD with incorrect VMCS revision identifier. */
994#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
995/** VMREAD/VMWRITE from/to unsupported VMCS component. */
996#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
997#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
998/** VMWRITE to read-only VMCS component. */
999#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1000/** VMXON executed in VMX root operation. */
1001#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1002/** VM entry with invalid executive-VMCS pointer. */
1003#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1004/** VM entry with non-launched executive VMCS. */
1005#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1006/** VM entry with executive-VMCS pointer not VMXON pointer. */
1007#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1008/** VMCALL with non-clear VMCS. */
1009#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1010/** VMCALL with invalid VM-exit control fields. */
1011#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1012/** VMCALL with incorrect MSEG revision identifier. */
1013#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1014/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1015#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1016/** VMCALL with invalid SMM-monitor features. */
1017#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1018/** VM entry with invalid VM-execution control fields in executive VMCS. */
1019#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1020/** VM entry with events blocked by MOV SS. */
1021#define VMX_ERROR_VMENTRY_MOV_SS 26
1022/** Invalid operand to INVEPT/INVVPID. */
1023#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1024
1025/** @} */
1026
1027
1028/** @name VMX MSRs - Basic VMX information.
1029 * @{
1030 */
1031/** VMCS revision identifier used by the processor. */
1032#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
1033/** Size of the VMCS. */
1034#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0xFFF)
1035/** Width of physical address used for the VMCS.
1036 * 0 -> limited to the available amount of physical ram
1037 * 1 -> within the first 4 GB
1038 */
1039#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1040/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1041#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1042/** Memory type that must be used for the VMCS. */
1043#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1044/** Whether the processor provides additional information for exits due to INS/OUTS. */
1045#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1046/** @} */
1047
1048
1049/** @name VMX MSRs - Misc VMX info.
1050 * @{
1051 */
1052/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1053#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1054/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1055#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1056/** Activity states supported by the implementation. */
1057#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1058/** Number of CR3 target values supported by the processor. (0-256) */
1059#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1060/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
1061#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1062/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1063#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1064/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1065#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1066/** Whether VMWRITE can be used to write VM-exit information fields. */
1067#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1068/** MSEG revision identifier used by the processor. */
1069#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1070/** @} */
1071
1072
1073/** @name VMX MSRs - VMCS enumeration field info
1074 * @{
1075 */
1076/** Highest field index. */
1077#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1078/** @} */
1079
1080
1081/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1082 * @{
1083 */
1084#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1085#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
1086#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
1087#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
1088#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
1089#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
1090#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
1091#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
1092#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1093#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
1094#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
1095#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
1096#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1097#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
1098#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
1099#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
1100#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
1101#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1102#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1103#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1104#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1105#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1106#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1107#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1108#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1109
1110/** @} */
1111
1112/** @name Extended Page Table Pointer (EPTP)
1113 * @{
1114 */
1115/** Uncachable EPT paging structure memory type. */
1116#define VMX_EPT_MEMTYPE_UC 0
1117/** Write-back EPT paging structure memory type. */
1118#define VMX_EPT_MEMTYPE_WB 6
1119/** Shift value to get the EPT page walk length (bits 5-3) */
1120#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1121/** Mask value to get the EPT page walk length (bits 5-3) */
1122#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1123/** Default EPT page-walk length (1 less than the actual EPT page-walk
1124 * length) */
1125#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1126/** @} */
1127
1128
1129/** @name VMCS field encoding - 16 bits guest fields
1130 * @{
1131 */
1132#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
1133#define VMX_VMCS16_GUEST_FIELD_ES 0x800
1134#define VMX_VMCS16_GUEST_FIELD_CS 0x802
1135#define VMX_VMCS16_GUEST_FIELD_SS 0x804
1136#define VMX_VMCS16_GUEST_FIELD_DS 0x806
1137#define VMX_VMCS16_GUEST_FIELD_FS 0x808
1138#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
1139#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
1140#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
1141/** @} */
1142
1143/** @name VMCS field encoding - 16 bits host fields
1144 * @{
1145 */
1146#define VMX_VMCS16_HOST_FIELD_ES 0xC00
1147#define VMX_VMCS16_HOST_FIELD_CS 0xC02
1148#define VMX_VMCS16_HOST_FIELD_SS 0xC04
1149#define VMX_VMCS16_HOST_FIELD_DS 0xC06
1150#define VMX_VMCS16_HOST_FIELD_FS 0xC08
1151#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
1152#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
1153/** @} */
1154
1155/** @name VMCS field encoding - 64 bits host fields
1156 * @{
1157 */
1158#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
1159#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
1160#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
1161#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
1162#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
1163#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
1164/** @} */
1165
1166
1167/** @name VMCS field encoding - 64 Bits control fields
1168 * @{
1169 */
1170#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1171#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1172#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1173#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1174
1175/* Optional */
1176#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1177#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1178
1179#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1180#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1181#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1182#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1183
1184#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1185#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1186
1187#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1188#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1189
1190#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1191#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1192
1193/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1194#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1195#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1196
1197/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1198#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1199#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1200
1201/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1202#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1203#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1204
1205/** Extended page table pointer. */
1206#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1207#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1208
1209/** Extended page table pointer lists. */
1210#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1211#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1212
1213/** VM-exit guest phyiscal address. */
1214#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1215#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1216/** @} */
1217
1218
1219/** @name VMCS field encoding - 64 Bits guest fields
1220 * @{
1221 */
1222#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1223#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1224#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
1225#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
1226#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1227#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1228#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1229#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1230#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
1231#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
1232#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1233#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1234#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1235#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1236#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1237#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1238#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1239#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1240/** @} */
1241
1242
1243/** @name VMCS field encoding - 32 Bits control fields
1244 * @{
1245 */
1246#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1247#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1248#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1249#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1250#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1251#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1252#define VMX_VMCS32_CTRL_EXIT 0x400C
1253#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1254#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1255#define VMX_VMCS32_CTRL_ENTRY 0x4012
1256#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1257#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1258#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1259#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1260#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1261#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1262/** @} */
1263
1264
1265/** @name VMX_VMCS_CTRL_PIN_EXEC
1266 * @{
1267 */
1268/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1269#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1270/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1271#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1272/** Virtual NMIs. */
1273#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1274/** Activate VMX preemption timer. */
1275#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1276/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1277/** @} */
1278
1279/** @name VMX_VMCS_CTRL_PROC_EXEC
1280 * @{
1281 */
1282/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
1283#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1284/** Use timestamp counter offset. */
1285#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1286/** VM Exit when executing the HLT instruction. */
1287#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1288/** VM Exit when executing the INVLPG instruction. */
1289#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1290/** VM Exit when executing the MWAIT instruction. */
1291#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1292/** VM Exit when executing the RDPMC instruction. */
1293#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1294/** VM Exit when executing the RDTSC/RDTSCP instruction. */
1295#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1296/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1297#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1298/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1299#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1300/** VM Exit on CR8 loads. */
1301#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1302/** VM Exit on CR8 stores. */
1303#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1304/** Use TPR shadow. */
1305#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1306/** VM Exit when virtual nmi blocking is disabled. */
1307#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1308/** VM Exit when executing a MOV DRx instruction. */
1309#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1310/** VM Exit when executing IO instructions. */
1311#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1312/** Use IO bitmaps. */
1313#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1314/** Monitor trap flag. */
1315#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1316/** Use MSR bitmaps. */
1317#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1318/** VM Exit when executing the MONITOR instruction. */
1319#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1320/** VM Exit when executing the PAUSE instruction. */
1321#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1322/** Determines whether the secondary processor based VM-execution controls are used. */
1323#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1324/** @} */
1325
1326/** @name VMX_VMCS_CTRL_PROC_EXEC2
1327 * @{
1328 */
1329/** Virtualize APIC access. */
1330#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1331/** EPT supported/enabled. */
1332#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1333/** Descriptor table instructions cause VM-exits. */
1334#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1335/** RDTSCP supported/enabled. */
1336#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1337/** Virtualize x2APIC mode. */
1338#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1339/** VPID supported/enabled. */
1340#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1341/** VM Exit when executing the WBINVD instruction. */
1342#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1343/** Unrestricted guest execution. */
1344#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1345/** A specified nr of pause loops cause a VM-exit. */
1346#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1347/** VM Exit when executing RDRAND instructions. */
1348#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1349/** Enables INVPCID instructions. */
1350#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1351/** Enables VMFUNC instructions. */
1352#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1353/** @} */
1354
1355
1356/** @name VMX_VMCS_CTRL_ENTRY
1357 * @{
1358 */
1359/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1360#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1361/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1362#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1363/** In SMM mode after VM-entry. */
1364#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1365/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1366#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1367/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
1368#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1369/** Whether the guest IA32_PAT MSR is loaded on VM entry. */
1370#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1371/** Whether the guest IA32_EFER MSR is loaded on VM entry. */
1372#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1373/** @} */
1374
1375
1376/** @name VMX_VMCS_CTRL_EXIT
1377 * @{
1378 */
1379/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1380#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1381/** Return to long mode after a VM-exit. */
1382#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1383/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
1384#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1385/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1386#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1387/** Whether the guest IA32_PAT MSR is saved on VM exit. */
1388#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1389/** Whether the host IA32_PAT MSR is loaded on VM exit. */
1390#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1391/** Whether the guest IA32_EFER MSR is saved on VM exit. */
1392#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1393/** Whether the host IA32_EFER MSR is loaded on VM exit. */
1394#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1395/** Whether the value of the VMX preemption timer is saved on every VM exit. */
1396#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1397/** @} */
1398
1399
1400/** @name VMX_VMCS_CTRL_VMFUNC
1401 * @{
1402 */
1403/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1404#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1405/** @} */
1406
1407
1408/** @name VMCS field encoding - 32 Bits read-only fields
1409 * @{
1410 */
1411#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1412#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1413#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1414#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1415#define VMX_VMCS32_RO_IDT_INFO 0x4408
1416#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1417#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1418#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1419/** @} */
1420
1421/** @name VMX_VMCS32_RO_EXIT_REASON
1422 * @{
1423 */
1424#define VMX_EXIT_REASON_BASIC(a) (a & 0xffff)
1425/** @} */
1426
1427/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1428 * @{
1429 */
1430#define VMX_ENTRY_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
1431#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1432#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1433/** @} */
1434
1435
1436/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1437 * @{
1438 */
1439#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
1440#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1441#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1442#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1443#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1444#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
1445#ifdef VBOX_WITH_OLD_VTX_CODE
1446# define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
1447#endif
1448#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1449#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) (a & RT_BIT(31))
1450/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1451#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
1452/** @} */
1453
1454/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1455 * @{
1456 */
1457#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1458#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1459#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1460#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4 /**< int xx */
1461#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DB_XCPT 5 /**< Why are we getting this one?? */
1462#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1463/** @} */
1464
1465/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1466 * @{
1467 */
1468#define VMX_IDT_VECTORING_INFO_VECTOR(a) (a & 0xff)
1469#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1470#define VMX_IDT_VECTORING_INFO_TYPE(a) ((a >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1471#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1472#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1473#define VMX_IDT_VECTORING_INFO_VALID(a) (a & RT_BIT(31))
1474#define VMX_ENTRY_INTR_INFO_FROM_EXIT_IDT_INFO(a) (a & ~RT_BIT(12))
1475/** @} */
1476
1477/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1478 * @{
1479 */
1480#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1481#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1482#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1483#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1484#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1485#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1486/** @} */
1487
1488
1489/** @name VMCS field encoding - 32 Bits guest state fields
1490 * @{
1491 */
1492#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1493#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1494#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1495#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1496#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1497#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1498#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1499#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1500#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1501#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1502#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1503#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1504#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1505#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1506#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1507#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1508#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1509#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1510#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1511#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1512#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
1513#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1514/** @} */
1515
1516
1517/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1518 * @{
1519 */
1520/** The logical processor is active. */
1521#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1522/** The logical processor is inactive, because executed a HLT instruction. */
1523#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1524/** The logical processor is inactive, because of a triple fault or other serious error. */
1525#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1526/** The logical processor is inactive, because it's waiting for a startup-IPI */
1527#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1528/** @} */
1529
1530
1531/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1532 * @{
1533 */
1534#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1535#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1536#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1537#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1538/** @} */
1539
1540
1541/** @name VMCS field encoding - 32 Bits host state fields
1542 * @{
1543 */
1544#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1545/** @} */
1546
1547/** @name Natural width control fields
1548 * @{
1549 */
1550#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1551#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1552#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1553#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1554#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1555#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1556#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1557#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1558/** @} */
1559
1560
1561/** @name Natural width read-only data fields
1562 * @{
1563 */
1564#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1565#define VMX_VMCS_RO_IO_RCX 0x6402
1566#define VMX_VMCS_RO_IO_RSX 0x6404
1567#define VMX_VMCS_RO_IO_RDI 0x6406
1568#define VMX_VMCS_RO_IO_RIP 0x6408
1569#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1570/** @} */
1571
1572
1573/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1574 * @{
1575 */
1576/** 0-2: Debug register number */
1577#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1578/** 3: Reserved; cleared to 0. */
1579#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1580/** 4: Direction of move (0 = write, 1 = read) */
1581#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1582/** 5-7: Reserved; cleared to 0. */
1583#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1584/** 8-11: General purpose register number. */
1585#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1586/** Rest: reserved. */
1587/** @} */
1588
1589/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1590 * @{
1591 */
1592#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1593#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1594/** @} */
1595
1596
1597
1598/** @name CRx accesses
1599 * @{
1600 */
1601/** 0-3: Control register number (0 for CLTS & LMSW) */
1602#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1603/** 4-5: Access type. */
1604#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1605/** 6: LMSW operand type */
1606#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1607/** 7: Reserved; cleared to 0. */
1608#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1609/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1610#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1611/** 12-15: Reserved; cleared to 0. */
1612#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1613/** 16-31: LMSW source data (else 0). */
1614#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1615/** Rest: reserved. */
1616/** @} */
1617
1618/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1619 * @{
1620 */
1621#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1622#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1623#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1624#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1625/** @} */
1626
1627/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1628 * @{
1629 */
1630#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1631#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1632/** Task switch caused by a call instruction. */
1633#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1634/** Task switch caused by an iret instruction. */
1635#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1636/** Task switch caused by a jmp instruction. */
1637#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1638/** Task switch caused by an interrupt gate. */
1639#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1640/** @} */
1641
1642
1643/** @name VMX_EXIT_EPT_VIOLATION
1644 * @{
1645 */
1646/** Set if the violation was caused by a data read. */
1647#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1648/** Set if the violation was caused by a data write. */
1649#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1650/** Set if the violation was caused by an insruction fetch. */
1651#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1652/** AND of the present bit of all EPT structures. */
1653#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1654/** AND of the write bit of all EPT structures. */
1655#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1656/** AND of the execute bit of all EPT structures. */
1657#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1658/** Set if the guest linear address field contains the faulting address. */
1659#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1660/** If bit 7 is one: (reserved otherwise)
1661 * 1 - violation due to physical address access.
1662 * 0 - violation caused by page walk or access/dirty bit updates
1663 */
1664#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1665/** @} */
1666
1667
1668/** @name VMX_EXIT_PORT_IO
1669 * @{
1670 */
1671/** 0-2: IO operation width. */
1672#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1673/** 3: IO operation direction. */
1674#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1675/** 4: String IO operation (INS / OUTS). */
1676#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1677/** 5: Repeated IO operation. */
1678#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1679/** 6: Operand encoding. */
1680#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1681/** 16-31: IO Port (0-0xffff). */
1682#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1683/* Rest reserved. */
1684/** @} */
1685
1686/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1687 * @{
1688 */
1689#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1690#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1691/** @} */
1692
1693
1694/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1695 * @{
1696 */
1697#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1698#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1699/** @} */
1700
1701/** @name VMX_EXIT_APIC_ACCESS
1702 * @{
1703 */
1704/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1705#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1706/** 12-15: Access type. */
1707#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000)
1708/* Rest reserved. */
1709/** @} */
1710
1711
1712/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1713 * @{
1714 */
1715/** Linear read access. */
1716#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1717/** Linear write access. */
1718#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1719/** Linear instruction fetch access. */
1720#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1721/** Linear read/write access during event delivery. */
1722#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1723/** Physical read/write access during event delivery. */
1724#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1725/** Physical access for an instruction fetch or during instruction execution. */
1726#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1727/** @} */
1728
1729/** @} */
1730
1731/** @name VMCS field encoding - Natural width guest state fields
1732 * @{
1733 */
1734#define VMX_VMCS_GUEST_CR0 0x6800
1735#define VMX_VMCS_GUEST_CR3 0x6802
1736#define VMX_VMCS_GUEST_CR4 0x6804
1737#define VMX_VMCS_GUEST_ES_BASE 0x6806
1738#define VMX_VMCS_GUEST_CS_BASE 0x6808
1739#define VMX_VMCS_GUEST_SS_BASE 0x680A
1740#define VMX_VMCS_GUEST_DS_BASE 0x680C
1741#define VMX_VMCS_GUEST_FS_BASE 0x680E
1742#define VMX_VMCS_GUEST_GS_BASE 0x6810
1743#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1744#define VMX_VMCS_GUEST_TR_BASE 0x6814
1745#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1746#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1747#define VMX_VMCS_GUEST_DR7 0x681A
1748#define VMX_VMCS_GUEST_RSP 0x681C
1749#define VMX_VMCS_GUEST_RIP 0x681E
1750#define VMX_VMCS_GUEST_RFLAGS 0x6820
1751#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1752#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1753#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1754/** @} */
1755
1756
1757/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1758 * @{
1759 */
1760/** Hardware breakpoint 0 was met. */
1761#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1762/** Hardware breakpoint 1 was met. */
1763#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1764/** Hardware breakpoint 2 was met. */
1765#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1766/** Hardware breakpoint 3 was met. */
1767#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1768/** At least one data or IO breakpoint was hit. */
1769#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1770/** A debug exception would have been triggered by single-step execution mode. */
1771#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1772/** Bits 4-11, 13 and 15-63 are reserved. */
1773
1774/** @} */
1775
1776/** @name VMCS field encoding - Natural width host state fields
1777 * @{
1778 */
1779#define VMX_VMCS_HOST_CR0 0x6C00
1780#define VMX_VMCS_HOST_CR3 0x6C02
1781#define VMX_VMCS_HOST_CR4 0x6C04
1782#define VMX_VMCS_HOST_FS_BASE 0x6C06
1783#define VMX_VMCS_HOST_GS_BASE 0x6C08
1784#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1785#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1786#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1787#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1788#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1789#define VMX_VMCS_HOST_RSP 0x6C14
1790#define VMX_VMCS_HOST_RIP 0x6C16
1791/** @} */
1792
1793/** @} */
1794
1795
1796/** @defgroup grp_vmx_asm vmx assembly helpers
1797 * @ingroup grp_vmx
1798 * @{
1799 */
1800
1801/**
1802 * Restores some host-state fields that need not be done on every VM-exit.
1803 *
1804 * @returns VBox status code.
1805 * @param fRestoreHostFlags Flags of which host registers needs to be
1806 * restored.
1807 * @param pRestoreHost Pointer to the host-restore structure.
1808 */
1809DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1810
1811
1812/**
1813 * Dispatches an NMI to the host.
1814 */
1815DECLASM(int) VMXDispatchHostNmi(void);
1816
1817
1818/**
1819 * Executes VMXON
1820 *
1821 * @returns VBox status code
1822 * @param pVMXOn Physical address of VMXON structure
1823 */
1824#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1825DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1826#else
1827DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1828{
1829# if RT_INLINE_ASM_GNU_STYLE
1830 int rc = VINF_SUCCESS;
1831 __asm__ __volatile__ (
1832 "push %3 \n\t"
1833 "push %2 \n\t"
1834 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1835 "ja 2f \n\t"
1836 "je 1f \n\t"
1837 "movl $"RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1838 "jmp 2f \n\t"
1839 "1: \n\t"
1840 "movl $"RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1841 "2: \n\t"
1842 "add $8, %%esp \n\t"
1843 :"=rm"(rc)
1844 :"0"(VINF_SUCCESS),
1845 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1846 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1847 :"memory"
1848 );
1849 return rc;
1850
1851# elif VMX_USE_MSC_INTRINSICS
1852 unsigned char rcMsc = __vmx_on(&pVMXOn);
1853 if (RT_LIKELY(rcMsc == 0))
1854 return VINF_SUCCESS;
1855 return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
1856
1857# else
1858 int rc = VINF_SUCCESS;
1859 __asm
1860 {
1861 push dword ptr [pVMXOn+4]
1862 push dword ptr [pVMXOn]
1863 _emit 0xF3
1864 _emit 0x0F
1865 _emit 0xC7
1866 _emit 0x34
1867 _emit 0x24 /* VMXON [esp] */
1868 jnc vmxon_good
1869 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1870 jmp the_end
1871
1872vmxon_good:
1873 jnz the_end
1874 mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1875the_end:
1876 add esp, 8
1877 }
1878# endif
1879}
1880#endif
1881
1882
1883/**
1884 * Executes VMXOFF
1885 */
1886#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1887DECLASM(void) VMXDisable(void);
1888#else
1889DECLINLINE(void) VMXDisable(void)
1890{
1891# if RT_INLINE_ASM_GNU_STYLE
1892 __asm__ __volatile__ (
1893 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1894 );
1895
1896# elif VMX_USE_MSC_INTRINSICS
1897 __vmx_off();
1898
1899# else
1900 __asm
1901 {
1902 _emit 0x0F
1903 _emit 0x01
1904 _emit 0xC4 /* VMXOFF */
1905 }
1906# endif
1907}
1908#endif
1909
1910
1911/**
1912 * Executes VMCLEAR
1913 *
1914 * @returns VBox status code
1915 * @param pVMCS Physical address of VM control structure
1916 */
1917#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1918DECLASM(int) VMXClearVmcs(RTHCPHYS pVMCS);
1919#else
1920DECLINLINE(int) VMXClearVmcs(RTHCPHYS pVMCS)
1921{
1922# if RT_INLINE_ASM_GNU_STYLE
1923 int rc = VINF_SUCCESS;
1924 __asm__ __volatile__ (
1925 "push %3 \n\t"
1926 "push %2 \n\t"
1927 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1928 "jnc 1f \n\t"
1929 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1930 "1: \n\t"
1931 "add $8, %%esp \n\t"
1932 :"=rm"(rc)
1933 :"0"(VINF_SUCCESS),
1934 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1935 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1936 :"memory"
1937 );
1938 return rc;
1939
1940# elif VMX_USE_MSC_INTRINSICS
1941 unsigned char rcMsc = __vmx_vmclear(&pVMCS);
1942 if (RT_LIKELY(rcMsc == 0))
1943 return VINF_SUCCESS;
1944 return VERR_VMX_INVALID_VMCS_PTR;
1945
1946# else
1947 int rc = VINF_SUCCESS;
1948 __asm
1949 {
1950 push dword ptr [pVMCS+4]
1951 push dword ptr [pVMCS]
1952 _emit 0x66
1953 _emit 0x0F
1954 _emit 0xC7
1955 _emit 0x34
1956 _emit 0x24 /* VMCLEAR [esp] */
1957 jnc success
1958 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1959success:
1960 add esp, 8
1961 }
1962 return rc;
1963# endif
1964}
1965#endif
1966
1967
1968/**
1969 * Executes VMPTRLD
1970 *
1971 * @returns VBox status code
1972 * @param pVMCS Physical address of VMCS structure
1973 */
1974#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1975DECLASM(int) VMXActivateVmcs(RTHCPHYS pVMCS);
1976#else
1977DECLINLINE(int) VMXActivateVmcs(RTHCPHYS pVMCS)
1978{
1979# if RT_INLINE_ASM_GNU_STYLE
1980 int rc = VINF_SUCCESS;
1981 __asm__ __volatile__ (
1982 "push %3 \n\t"
1983 "push %2 \n\t"
1984 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1985 "jnc 1f \n\t"
1986 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1987 "1: \n\t"
1988 "add $8, %%esp \n\t"
1989 :"=rm"(rc)
1990 :"0"(VINF_SUCCESS),
1991 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1992 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1993 );
1994 return rc;
1995
1996# elif VMX_USE_MSC_INTRINSICS
1997 unsigned char rcMsc = __vmx_vmptrld(&pVMCS);
1998 if (RT_LIKELY(rcMsc == 0))
1999 return VINF_SUCCESS;
2000 return VERR_VMX_INVALID_VMCS_PTR;
2001
2002# else
2003 int rc = VINF_SUCCESS;
2004 __asm
2005 {
2006 push dword ptr [pVMCS+4]
2007 push dword ptr [pVMCS]
2008 _emit 0x0F
2009 _emit 0xC7
2010 _emit 0x34
2011 _emit 0x24 /* VMPTRLD [esp] */
2012 jnc success
2013 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2014
2015success:
2016 add esp, 8
2017 }
2018 return rc;
2019# endif
2020}
2021#endif
2022
2023/**
2024 * Executes VMPTRST
2025 *
2026 * @returns VBox status code
2027 * @param pVMCS Address that will receive the current pointer
2028 */
2029DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pVMCS);
2030
2031/**
2032 * Executes VMWRITE
2033 *
2034 * @returns VBox status code
2035 * @retval VINF_SUCCESS
2036 * @retval VERR_VMX_INVALID_VMCS_PTR
2037 * @retval VERR_VMX_INVALID_VMCS_FIELD
2038 *
2039 * @param idxField VMCS index
2040 * @param u32Val 32 bits value
2041 *
2042 * @remarks The values of the two status codes can be ORed together, the result
2043 * will be VERR_VMX_INVALID_VMCS_PTR.
2044 */
2045#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2046DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2047#else
2048DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2049{
2050# if RT_INLINE_ASM_GNU_STYLE
2051 int rc = VINF_SUCCESS;
2052 __asm__ __volatile__ (
2053 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2054 "ja 2f \n\t"
2055 "je 1f \n\t"
2056 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2057 "jmp 2f \n\t"
2058 "1: \n\t"
2059 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2060 "2: \n\t"
2061 :"=rm"(rc)
2062 :"0"(VINF_SUCCESS),
2063 "a"(idxField),
2064 "d"(u32Val)
2065 );
2066 return rc;
2067
2068# elif VMX_USE_MSC_INTRINSICS
2069 unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2070 if (RT_LIKELY(rcMsc == 0))
2071 return VINF_SUCCESS;
2072 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2073
2074#else
2075 int rc = VINF_SUCCESS;
2076 __asm
2077 {
2078 push dword ptr [u32Val]
2079 mov eax, [idxField]
2080 _emit 0x0F
2081 _emit 0x79
2082 _emit 0x04
2083 _emit 0x24 /* VMWRITE eax, [esp] */
2084 jnc valid_vmcs
2085 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2086 jmp the_end
2087
2088valid_vmcs:
2089 jnz the_end
2090 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2091the_end:
2092 add esp, 4
2093 }
2094 return rc;
2095# endif
2096}
2097#endif
2098
2099/**
2100 * Executes VMWRITE
2101 *
2102 * @returns VBox status code
2103 * @retval VINF_SUCCESS
2104 * @retval VERR_VMX_INVALID_VMCS_PTR
2105 * @retval VERR_VMX_INVALID_VMCS_FIELD
2106 *
2107 * @param idxField VMCS index
2108 * @param u64Val 16, 32 or 64 bits value
2109 *
2110 * @remarks The values of the two status codes can be ORed together, the result
2111 * will be VERR_VMX_INVALID_VMCS_PTR.
2112 */
2113#if !defined(RT_ARCH_X86) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2114# if !VMX_USE_MSC_INTRINSICS || ARCH_BITS != 64
2115DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2116# else /* VMX_USE_MSC_INTRINSICS */
2117DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2118{
2119 unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2120 if (RT_LIKELY(rcMsc == 0))
2121 return VINF_SUCCESS;
2122 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2123}
2124# endif /* VMX_USE_MSC_INTRINSICS */
2125#else
2126# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2127VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2128#endif
2129
2130#ifdef VBOX_WITH_OLD_VTX_CODE
2131# if ARCH_BITS == 64
2132# define VMXWriteVmcs VMXWriteVmcs64
2133# else
2134# define VMXWriteVmcs VMXWriteVmcs32
2135# endif
2136#else /* !VBOX_WITH_OLD_VTX_CODE */
2137# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2138# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
2139 VMXWriteVmcs64(idxField, uVal) \
2140 : VMXWriteVmcs32(idxField, uVal)
2141# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
2142 VMXWriteVmcs64(idxField, u64Val) \
2143 : VMXWriteVmcs32(idxField, u64Val)
2144# elif ARCH_BITS == 32
2145# define VMXWriteVmcsHstN VMXWriteVmcs32
2146# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2147# else /* ARCH_BITS == 64 */
2148# define VMXWriteVmcsHstN VMXWriteVmcs64
2149# define VMXWriteVmcsGstN VMXWriteVmcs64
2150# endif
2151#endif /* !VBOX_WITH_OLD_VTX_CODE */
2152
2153
2154/**
2155 * Invalidate a page using invept
2156 * @returns VBox status code
2157 * @param enmFlush Type of flush
2158 * @param pDescriptor Descriptor
2159 */
2160DECLASM(int) VMXR0InvEPT(VMX_FLUSH_EPT enmFlush, uint64_t *pDescriptor);
2161
2162/**
2163 * Invalidate a page using invvpid
2164 * @returns VBox status code
2165 * @param enmFlush Type of flush
2166 * @param pDescriptor Descriptor
2167 */
2168DECLASM(int) VMXR0InvVPID(VMX_FLUSH_VPID enmFlush, uint64_t *pDescriptor);
2169
2170/**
2171 * Executes VMREAD
2172 *
2173 * @returns VBox status code
2174 * @retval VINF_SUCCESS
2175 * @retval VERR_VMX_INVALID_VMCS_PTR
2176 * @retval VERR_VMX_INVALID_VMCS_FIELD
2177 *
2178 * @param idxField VMCS index
2179 * @param pData Ptr to store VM field value
2180 *
2181 * @remarks The values of the two status codes can be ORed together, the result
2182 * will be VERR_VMX_INVALID_VMCS_PTR.
2183 */
2184#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2185DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2186#else
2187DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2188{
2189# if RT_INLINE_ASM_GNU_STYLE
2190 int rc = VINF_SUCCESS;
2191 __asm__ __volatile__ (
2192 "movl $"RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2193 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2194 "ja 2f \n\t"
2195 "je 1f \n\t"
2196 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2197 "jmp 2f \n\t"
2198 "1: \n\t"
2199 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2200 "2: \n\t"
2201 :"=&r"(rc),
2202 "=d"(*pData)
2203 :"a"(idxField),
2204 "d"(0)
2205 );
2206 return rc;
2207
2208# elif VMX_USE_MSC_INTRINSICS
2209 unsigned char rcMsc;
2210# if ARCH_BITS == 32
2211 rcMsc = __vmx_vmread(idxField, pData);
2212# else
2213 uint64_t u64Tmp;
2214 rcMsc = __vmx_vmread(idxField, &u64Tmp);
2215 *pData = (uint32_t)u64Tmp;
2216# endif
2217 if (RT_LIKELY(rcMsc == 0))
2218 return VINF_SUCCESS;
2219 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2220
2221#else
2222 int rc = VINF_SUCCESS;
2223 __asm
2224 {
2225 sub esp, 4
2226 mov dword ptr [esp], 0
2227 mov eax, [idxField]
2228 _emit 0x0F
2229 _emit 0x78
2230 _emit 0x04
2231 _emit 0x24 /* VMREAD eax, [esp] */
2232 mov edx, pData
2233 pop dword ptr [edx]
2234 jnc valid_vmcs
2235 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2236 jmp the_end
2237
2238valid_vmcs:
2239 jnz the_end
2240 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2241the_end:
2242 }
2243 return rc;
2244# endif
2245}
2246#endif
2247
2248/**
2249 * Executes VMREAD
2250 *
2251 * @returns VBox status code
2252 * @retval VINF_SUCCESS
2253 * @retval VERR_VMX_INVALID_VMCS_PTR
2254 * @retval VERR_VMX_INVALID_VMCS_FIELD
2255 *
2256 * @param idxField VMCS index
2257 * @param pData Ptr to store VM field value
2258 *
2259 * @remarks The values of the two status codes can be ORed together, the result
2260 * will be VERR_VMX_INVALID_VMCS_PTR.
2261 */
2262#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2263DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2264#else
2265DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2266{
2267# if VMX_USE_MSC_INTRINSICS
2268 unsigned char rcMsc;
2269# if ARCH_BITS == 32
2270 size_t uLow;
2271 size_t uHigh;
2272 rcMsc = __vmx_vmread(idxField, &uLow);
2273 rcMsc |= __vmx_vmread(idxField + 1, &uHigh);
2274 *pData = RT_MAKE_U64(uLow, uHigh);
2275# else
2276 rcMsc = __vmx_vmread(idxField, pData);
2277# endif
2278 if (RT_LIKELY(rcMsc == 0))
2279 return VINF_SUCCESS;
2280 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2281
2282# elif ARCH_BITS == 32
2283 int rc;
2284 uint32_t val_hi, val;
2285 rc = VMXReadVmcs32(idxField, &val);
2286 rc |= VMXReadVmcs32(idxField + 1, &val_hi);
2287 AssertRC(rc);
2288 *pData = RT_MAKE_U64(val, val_hi);
2289 return rc;
2290
2291# else
2292# error "Shouldn't be here..."
2293# endif
2294}
2295#endif
2296
2297#ifdef VBOX_WITH_OLD_VTX_CODE
2298# if ARCH_BITS == 64
2299# define VMXReadVmcsField VMXReadVmcs64
2300# else
2301# define VMXReadVmcsField VMXReadVmcs32
2302# endif
2303#endif
2304
2305/**
2306 * Gets the last instruction error value from the current VMCS
2307 *
2308 * @returns error value
2309 */
2310DECLINLINE(uint32_t) VMXGetLastError(void)
2311{
2312#if ARCH_BITS == 64
2313 uint64_t uLastError = 0;
2314 int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2315 AssertRC(rc);
2316 return (uint32_t)uLastError;
2317
2318#else /* 32-bit host: */
2319 uint32_t uLastError = 0;
2320 int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2321 AssertRC(rc);
2322 return uLastError;
2323#endif
2324}
2325
2326#ifdef IN_RING0
2327VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2328VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2329#endif /* IN_RING0 */
2330
2331/** @} */
2332
2333#endif
2334
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