hm_vmx.h@ 53425

Last change on this file since 53425 was 52573, checked in by vboxsync, 10 years ago
VMM/HMVMXR0: Fix a wrong invalid-guest-state check with regards to EFER.LMA and LME.
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File size: 96.1 KB

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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2014 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# include <intrin.h>
38	/* We always want them as intrinsics, no functions. */
39	# pragma intrinsic(__vmx_on)
40	# pragma intrinsic(__vmx_off)
41	# pragma intrinsic(__vmx_vmclear)
42	# pragma intrinsic(__vmx_vmptrld)
43	# pragma intrinsic(__vmx_vmread)
44	# pragma intrinsic(__vmx_vmwrite)
45	# define VMX_USE_MSC_INTRINSICS 1
46	#else
47	# define VMX_USE_MSC_INTRINSICS 0
48	#endif
49
50
51	/** @defgroup grp_vmx vmx Types and Definitions
52	* @ingroup grp_hm
53	* @{
54	*/
55
56	/** @def HMVMXCPU_GST_SET_UPDATED
57	* Sets a guest-state-updated flag.
58	*
59	* @param pVCpu Pointer to the VMCPU.
60	* @param fFlag The flag to set.
61	*/
62	#define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
63
64	/** @def HMVMXCPU_GST_IS_SET
65	* Checks if all the flags in the specified guest-state-updated set is pending.
66	*
67	* @param pVCpu Pointer to the VMCPU.
68	* @param fFlag The flag to check.
69	*/
70	#define HMVMXCPU_GST_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
71
72	/** @def HMVMXCPU_GST_IS_UPDATED
73	* Checks if one or more of the flags in the specified guest-state-updated set
74	* is updated.
75	*
76	* @param pVCpu Pointer to the VMCPU.
77	* @param fFlags The flags to check for.
78	*/
79	#define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
80
81	/** @def HMVMXCPU_GST_RESET_TO
82	* Resets the guest-state-updated flags to the specified value.
83	*
84	* @param pVCpu Pointer to the VMCPU.
85	* @param fFlags The new value.
86	*/
87	#define HMVMXCPU_GST_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlags)))
88
89	/** @def HMVMXCPU_GST_VALUE
90	* Returns the current guest-state-updated flags value.
91	*
92	* @param pVCpu Pointer to the VMCPU.
93	*/
94	#define HMVMXCPU_GST_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState))
95
96	/** @name Host-state restoration flags.
97	* @{
98	*/
99	/* If you change these values don't forget to update the assembly defines as well! */
100	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
101	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
102	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
103	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
104	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
105	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
106	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
107	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
108	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
109	/** @} */
110
111	/**
112	* Host-state restoration structure.
113	* This holds host-state fields that require manual restoration.
114	* Assembly version found in hm_vmx.mac (should be automatically verified).
115	*/
116	typedef struct VMXRESTOREHOST
117	{
118	RTSEL uHostSelDS; /* 0x00 */
119	RTSEL uHostSelES; /* 0x02 */
120	RTSEL uHostSelFS; /* 0x04 */
121	RTSEL uHostSelGS; /* 0x06 */
122	RTSEL uHostSelTR; /* 0x08 */
123	uint8_t abPadding0[4];
124	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
125	uint8_t abPadding1[6];
126	X86XDTR64 HostIdtr; /*< 0x1e - should be aligned by it's 64-bit member. /
127	uint64_t uHostFSBase; /* 0x28 */
128	uint64_t uHostGSBase; /* 0x30 */
129	} VMXRESTOREHOST;
130	/** Pointer to VMXRESTOREHOST. */
131	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
132	AssertCompileSize(X86XDTR64, 10);
133	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
134	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
135	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
136	AssertCompileSize(VMXRESTOREHOST, 56);
137	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
138
139	/** @name Host-state MSR lazy-restoration flags.
140	* @{
141	*/
142	/** The host MSRs have been saved. */
143	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
144	/** The guest MSRs are loaded and in effect. */
145	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
146	/** @} */
147
148	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
149	* UFC = Unsupported Feature Combination.
150	* @{
151	*/
152	/** Unsupported pin-based VM-execution controls combo. */
153	#define VMX_UFC_CTRL_PIN_EXEC 0
154	/** Unsupported processor-based VM-execution controls combo. */
155	#define VMX_UFC_CTRL_PROC_EXEC 1
156	/** Unsupported pin-based VM-execution controls combo. */
157	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 2
158	/** Unsupported VM-entry controls combo. */
159	#define VMX_UFC_CTRL_ENTRY 3
160	/** Unsupported VM-exit controls combo. */
161	#define VMX_UFC_CTRL_EXIT 4
162	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
163	* for storing host MSRs. */
164	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 5
165	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
166	* for storing guest MSRs. */
167	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 6
168	/** Invalid VMCS size. */
169	#define VMX_UFC_INVALID_VMCS_SIZE 7
170	/** Unsupported secondary processor-based VM-execution controls combo. */
171	#define VMX_UFC_CTRL_PROC_EXEC2 8
172	/** Invalid unrestricted-guest execution controls combo. */
173	#define VMX_UFC_INVALID_UX_COMBO 9
174	/** @} */
175
176	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
177	* IGS = Invalid Guest State.
178	* @{
179	*/
180	/** An error occurred while checking invalid-guest-state. */
181	#define VMX_IGS_ERROR 0
182	/** The invalid guest-state checks did not find any reason why. */
183	#define VMX_IGS_REASON_NOT_FOUND 1
184	/** CR0 fixed1 bits invalid. */
185	#define VMX_IGS_CR0_FIXED1 2
186	/** CR0 fixed0 bits invalid. */
187	#define VMX_IGS_CR0_FIXED0 3
188	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
189	#define VMX_IGS_CR0_PG_PE_COMBO 4
190	/** CR4 fixed1 bits invalid. */
191	#define VMX_IGS_CR4_FIXED1 5
192	/** CR4 fixed0 bits invalid. */
193	#define VMX_IGS_CR4_FIXED0 6
194	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
195	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
196	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 7
197	/** CR0.PG not set for long-mode when not using unrestricted guest. */
198	#define VMX_IGS_CR0_PG_LONGMODE 8
199	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
200	#define VMX_IGS_CR4_PAE_LONGMODE 9
201	/** CR4.PCIDE set for 32-bit guest. */
202	#define VMX_IGS_CR4_PCIDE 10
203	/** VMCS' DR7 reserved bits not set to 0. */
204	#define VMX_IGS_DR7_RESERVED 11
205	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
206	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12
207	/** VMCS' EFER MSR reserved bits not set to 0. */
208	#define VMX_IGS_EFER_MSR_RESERVED 13
209	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
210	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14
211	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
212	* without unrestricted guest. */
213	#define VMX_IGS_EFER_LMA_LME_MISMATCH 15
214	/** CS.Attr.P bit invalid. */
215	#define VMX_IGS_CS_ATTR_P_INVALID 16
216	/** CS.Attr reserved bits not set to 0. */
217	#define VMX_IGS_CS_ATTR_RESERVED 17
218	/** CS.Attr.G bit invalid. */
219	#define VMX_IGS_CS_ATTR_G_INVALID 18
220	/** CS is unusable. */
221	#define VMX_IGS_CS_ATTR_UNUSABLE 19
222	/** CS and SS DPL unequal. */
223	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20
224	/** CS and SS DPL mismatch. */
225	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21
226	/** CS Attr.Type invalid. */
227	#define VMX_IGS_CS_ATTR_TYPE_INVALID 22
228	/** CS and SS RPL unequal. */
229	#define VMX_IGS_SS_CS_RPL_UNEQUAL 23
230	/** SS.Attr.DPL and SS RPL unequal. */
231	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24
232	/** SS.Attr.DPL invalid for segment type. */
233	#define VMX_IGS_SS_ATTR_DPL_INVALID 25
234	/** SS.Attr.Type invalid. */
235	#define VMX_IGS_SS_ATTR_TYPE_INVALID 26
236	/** SS.Attr.P bit invalid. */
237	#define VMX_IGS_SS_ATTR_P_INVALID 27
238	/** SS.Attr reserved bits not set to 0. */
239	#define VMX_IGS_SS_ATTR_RESERVED 28
240	/** SS.Attr.G bit invalid. */
241	#define VMX_IGS_SS_ATTR_G_INVALID 29
242	/** DS.Attr.A bit invalid. */
243	#define VMX_IGS_DS_ATTR_A_INVALID 30
244	/** DS.Attr.P bit invalid. */
245	#define VMX_IGS_DS_ATTR_P_INVALID 31
246	/** DS.Attr.DPL and DS RPL unequal. */
247	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32
248	/** DS.Attr reserved bits not set to 0. */
249	#define VMX_IGS_DS_ATTR_RESERVED 33
250	/** DS.Attr.G bit invalid. */
251	#define VMX_IGS_DS_ATTR_G_INVALID 34
252	/** DS.Attr.Type invalid. */
253	#define VMX_IGS_DS_ATTR_TYPE_INVALID 35
254	/** ES.Attr.A bit invalid. */
255	#define VMX_IGS_ES_ATTR_A_INVALID 36
256	/** ES.Attr.P bit invalid. */
257	#define VMX_IGS_ES_ATTR_P_INVALID 37
258	/** ES.Attr.DPL and DS RPL unequal. */
259	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38
260	/** ES.Attr reserved bits not set to 0. */
261	#define VMX_IGS_ES_ATTR_RESERVED 39
262	/** ES.Attr.G bit invalid. */
263	#define VMX_IGS_ES_ATTR_G_INVALID 40
264	/** ES.Attr.Type invalid. */
265	#define VMX_IGS_ES_ATTR_TYPE_INVALID 41
266	/** FS.Attr.A bit invalid. */
267	#define VMX_IGS_FS_ATTR_A_INVALID 42
268	/** FS.Attr.P bit invalid. */
269	#define VMX_IGS_FS_ATTR_P_INVALID 43
270	/** FS.Attr.DPL and DS RPL unequal. */
271	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44
272	/** FS.Attr reserved bits not set to 0. */
273	#define VMX_IGS_FS_ATTR_RESERVED 45
274	/** FS.Attr.G bit invalid. */
275	#define VMX_IGS_FS_ATTR_G_INVALID 46
276	/** FS.Attr.Type invalid. */
277	#define VMX_IGS_FS_ATTR_TYPE_INVALID 47
278	/** GS.Attr.A bit invalid. */
279	#define VMX_IGS_GS_ATTR_A_INVALID 48
280	/** GS.Attr.P bit invalid. */
281	#define VMX_IGS_GS_ATTR_P_INVALID 49
282	/** GS.Attr.DPL and DS RPL unequal. */
283	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 50
284	/** GS.Attr reserved bits not set to 0. */
285	#define VMX_IGS_GS_ATTR_RESERVED 51
286	/** GS.Attr.G bit invalid. */
287	#define VMX_IGS_GS_ATTR_G_INVALID 52
288	/** GS.Attr.Type invalid. */
289	#define VMX_IGS_GS_ATTR_TYPE_INVALID 53
290	/** V86 mode CS.Base invalid. */
291	#define VMX_IGS_V86_CS_BASE_INVALID 54
292	/** V86 mode CS.Limit invalid. */
293	#define VMX_IGS_V86_CS_LIMIT_INVALID 55
294	/** V86 mode CS.Attr invalid. */
295	#define VMX_IGS_V86_CS_ATTR_INVALID 56
296	/** V86 mode SS.Base invalid. */
297	#define VMX_IGS_V86_SS_BASE_INVALID 57
298	/** V86 mode SS.Limit invalid. */
299	#define VMX_IGS_V86_SS_LIMIT_INVALID 58
300	/** V86 mode SS.Attr invalid. */
301	#define VMX_IGS_V86_SS_ATTR_INVALID 59
302	/** V86 mode DS.Base invalid. */
303	#define VMX_IGS_V86_DS_BASE_INVALID 60
304	/** V86 mode DS.Limit invalid. */
305	#define VMX_IGS_V86_DS_LIMIT_INVALID 61
306	/** V86 mode DS.Attr invalid. */
307	#define VMX_IGS_V86_DS_ATTR_INVALID 62
308	/** V86 mode ES.Base invalid. */
309	#define VMX_IGS_V86_ES_BASE_INVALID 63
310	/** V86 mode ES.Limit invalid. */
311	#define VMX_IGS_V86_ES_LIMIT_INVALID 64
312	/** V86 mode ES.Attr invalid. */
313	#define VMX_IGS_V86_ES_ATTR_INVALID 65
314	/** V86 mode FS.Base invalid. */
315	#define VMX_IGS_V86_FS_BASE_INVALID 66
316	/** V86 mode FS.Limit invalid. */
317	#define VMX_IGS_V86_FS_LIMIT_INVALID 67
318	/** V86 mode FS.Attr invalid. */
319	#define VMX_IGS_V86_FS_ATTR_INVALID 68
320	/** V86 mode GS.Base invalid. */
321	#define VMX_IGS_V86_GS_BASE_INVALID 69
322	/** V86 mode GS.Limit invalid. */
323	#define VMX_IGS_V86_GS_LIMIT_INVALID 70
324	/** V86 mode GS.Attr invalid. */
325	#define VMX_IGS_V86_GS_ATTR_INVALID 71
326	/** Longmode CS.Base invalid. */
327	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 72
328	/** Longmode SS.Base invalid. */
329	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 73
330	/** Longmode DS.Base invalid. */
331	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 74
332	/** Longmode ES.Base invalid. */
333	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 75
334	/** SYSENTER ESP is not canonical. */
335	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76
336	/** SYSENTER EIP is not canonical. */
337	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77
338	/** PAT MSR invalid. */
339	#define VMX_IGS_PAT_MSR_INVALID 78
340	/** PAT MSR reserved bits not set to 0. */
341	#define VMX_IGS_PAT_MSR_RESERVED 79
342	/** GDTR.Base is not canonical. */
343	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80
344	/** IDTR.Base is not canonical. */
345	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81
346	/** GDTR.Limit invalid. */
347	#define VMX_IGS_GDTR_LIMIT_INVALID 82
348	/** IDTR.Limit invalid. */
349	#define VMX_IGS_IDTR_LIMIT_INVALID 83
350	/** Longmode RIP is invalid. */
351	#define VMX_IGS_LONGMODE_RIP_INVALID 84
352	/** RFLAGS reserved bits not set to 0. */
353	#define VMX_IGS_RFLAGS_RESERVED 85
354	/** RFLAGS RA1 reserved bits not set to 1. */
355	#define VMX_IGS_RFLAGS_RESERVED1 86
356	/** RFLAGS.VM (V86 mode) invalid. */
357	#define VMX_IGS_RFLAGS_VM_INVALID 87
358	/** RFLAGS.IF invalid. */
359	#define VMX_IGS_RFLAGS_IF_INVALID 88
360	/** Activity state invalid. */
361	#define VMX_IGS_ACTIVITY_STATE_INVALID 89
362	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
363	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90
364	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
365	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91
366	/** Activity state SIPI WAIT invalid. */
367	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92
368	/** Interruptibility state reserved bits not set to 0. */
369	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93
370	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
371	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94
372	/** Interruptibility state block-by-STI invalid for EFLAGS. */
373	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95
374	/** Interruptibility state invalid while trying to deliver external
375	* interrupt. */
376	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96
377	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
378	* NMI. */
379	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97
380	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
381	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98
382	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
383	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99
384	/** Interruptibilty state block-by-STI (maybe) invalid when trying to deliver
385	* an NMI. */
386	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100
387	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
388	* active. */
389	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101
390	/** Pending debug exceptions reserved bits not set to 0. */
391	#define VMX_IGS_PENDING_DEBUG_RESERVED 102
392	/** Longmode pending debug exceptions reserved bits not set to 0. */
393	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103
394	/** Pending debug exceptions.BS bit is not set when it should be. */
395	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104
396	/** Pending debug exceptions.BS bit is not clear when it should be. */
397	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105
398	/** VMCS link pointer reserved bits not set to 0. */
399	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 106
400	/** TR cannot index into LDT, TI bit MBZ. */
401	#define VMX_IGS_TR_TI_INVALID 107
402	/** LDTR cannot index into LDT. TI bit MBZ. */
403	#define VMX_IGS_LDTR_TI_INVALID 108
404	/** TR.Base is not canonical. */
405	#define VMX_IGS_TR_BASE_NOT_CANONICAL 109
406	/** FS.Base is not canonical. */
407	#define VMX_IGS_FS_BASE_NOT_CANONICAL 110
408	/** GS.Base is not canonical. */
409	#define VMX_IGS_GS_BASE_NOT_CANONICAL 111
410	/** LDTR.Base is not canonical. */
411	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 112
412	/** TR is unusable. */
413	#define VMX_IGS_TR_ATTR_UNUSABLE 113
414	/** TR.Attr.S bit invalid. */
415	#define VMX_IGS_TR_ATTR_S_INVALID 114
416	/** TR is not present. */
417	#define VMX_IGS_TR_ATTR_P_INVALID 115
418	/** TR.Attr reserved bits not set to 0. */
419	#define VMX_IGS_TR_ATTR_RESERVED 116
420	/** TR.Attr.G bit invalid. */
421	#define VMX_IGS_TR_ATTR_G_INVALID 117
422	/** Longmode TR.Attr.Type invalid. */
423	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 118
424	/** TR.Attr.Type invalid. */
425	#define VMX_IGS_TR_ATTR_TYPE_INVALID 119
426	/** CS.Attr.S invalid. */
427	#define VMX_IGS_CS_ATTR_S_INVALID 120
428	/** CS.Attr.DPL invalid. */
429	#define VMX_IGS_CS_ATTR_DPL_INVALID 121
430	/** PAE PDPTE reserved bits not set to 0. */
431	#define VMX_IGS_PAE_PDPTE_RESERVED 123
432	/** @} */
433
434	/** @name VMX VMCS-Read cache indices.
435	* @{
436	*/
437	# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
438	# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
439	# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
440	# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
441	# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
442	# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
443	# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
444	# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
445	# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
446	# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
447	# define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
448	# define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
449	# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
450	# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
451	# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
452	# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
453	# define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
454	# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
455	/** @} */
456
457	/** @name VMX EPT paging structures
458	* @{
459	*/
460
461	/**
462	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
463	*/
464	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
465
466	/**
467	* EPT Page Directory Pointer Entry. Bit view.
468	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
469	* this did cause trouble with one compiler/version).
470	*/
471	#pragma pack(1)
472	typedef struct EPTPML4EBITS
473	{
474	/** Present bit. */
475	uint64_t u1Present : 1;
476	/** Writable bit. */
477	uint64_t u1Write : 1;
478	/** Executable bit. */
479	uint64_t u1Execute : 1;
480	/** Reserved (must be 0). */
481	uint64_t u5Reserved : 5;
482	/** Available for software. */
483	uint64_t u4Available : 4;
484	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
485	uint64_t u40PhysAddr : 40;
486	/** Availabe for software. */
487	uint64_t u12Available : 12;
488	} EPTPML4EBITS;
489	#pragma pack()
490	AssertCompileSize(EPTPML4EBITS, 8);
491
492	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
493	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
494	/** The page shift to get the PML4 index. */
495	#define EPT_PML4_SHIFT X86_PML4_SHIFT
496	/** The PML4 index mask (apply to a shifted page address). */
497	#define EPT_PML4_MASK X86_PML4_MASK
498
499	/**
500	* EPT PML4E.
501	*/
502	#pragma pack(1)
503	typedef union EPTPML4E
504	{
505	/** Normal view. */
506	EPTPML4EBITS n;
507	/** Unsigned integer view. */
508	X86PGPAEUINT u;
509	/** 64 bit unsigned integer view. */
510	uint64_t au64[1];
511	/** 32 bit unsigned integer view. */
512	uint32_t au32[2];
513	} EPTPML4E;
514	#pragma pack()
515	/** Pointer to a PML4 table entry. */
516	typedef EPTPML4E *PEPTPML4E;
517	/** Pointer to a const PML4 table entry. */
518	typedef const EPTPML4E *PCEPTPML4E;
519	AssertCompileSize(EPTPML4E, 8);
520
521	/**
522	* EPT PML4 Table.
523	*/
524	#pragma pack(1)
525	typedef struct EPTPML4
526	{
527	EPTPML4E a[EPT_PG_ENTRIES];
528	} EPTPML4;
529	#pragma pack()
530	/** Pointer to an EPT PML4 Table. */
531	typedef EPTPML4 *PEPTPML4;
532	/** Pointer to a const EPT PML4 Table. */
533	typedef const EPTPML4 *PCEPTPML4;
534
535	/**
536	* EPT Page Directory Pointer Entry. Bit view.
537	*/
538	#pragma pack(1)
539	typedef struct EPTPDPTEBITS
540	{
541	/** Present bit. */
542	uint64_t u1Present : 1;
543	/** Writable bit. */
544	uint64_t u1Write : 1;
545	/** Executable bit. */
546	uint64_t u1Execute : 1;
547	/** Reserved (must be 0). */
548	uint64_t u5Reserved : 5;
549	/** Available for software. */
550	uint64_t u4Available : 4;
551	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
552	uint64_t u40PhysAddr : 40;
553	/** Availabe for software. */
554	uint64_t u12Available : 12;
555	} EPTPDPTEBITS;
556	#pragma pack()
557	AssertCompileSize(EPTPDPTEBITS, 8);
558
559	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
560	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
561	/** The page shift to get the PDPT index. */
562	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
563	/** The PDPT index mask (apply to a shifted page address). */
564	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
565
566	/**
567	* EPT Page Directory Pointer.
568	*/
569	#pragma pack(1)
570	typedef union EPTPDPTE
571	{
572	/** Normal view. */
573	EPTPDPTEBITS n;
574	/** Unsigned integer view. */
575	X86PGPAEUINT u;
576	/** 64 bit unsigned integer view. */
577	uint64_t au64[1];
578	/** 32 bit unsigned integer view. */
579	uint32_t au32[2];
580	} EPTPDPTE;
581	#pragma pack()
582	/** Pointer to an EPT Page Directory Pointer Entry. */
583	typedef EPTPDPTE *PEPTPDPTE;
584	/** Pointer to a const EPT Page Directory Pointer Entry. */
585	typedef const EPTPDPTE *PCEPTPDPTE;
586	AssertCompileSize(EPTPDPTE, 8);
587
588	/**
589	* EPT Page Directory Pointer Table.
590	*/
591	#pragma pack(1)
592	typedef struct EPTPDPT
593	{
594	EPTPDPTE a[EPT_PG_ENTRIES];
595	} EPTPDPT;
596	#pragma pack()
597	/** Pointer to an EPT Page Directory Pointer Table. */
598	typedef EPTPDPT *PEPTPDPT;
599	/** Pointer to a const EPT Page Directory Pointer Table. */
600	typedef const EPTPDPT *PCEPTPDPT;
601
602
603	/**
604	* EPT Page Directory Table Entry. Bit view.
605	*/
606	#pragma pack(1)
607	typedef struct EPTPDEBITS
608	{
609	/** Present bit. */
610	uint64_t u1Present : 1;
611	/** Writable bit. */
612	uint64_t u1Write : 1;
613	/** Executable bit. */
614	uint64_t u1Execute : 1;
615	/** Reserved (must be 0). */
616	uint64_t u4Reserved : 4;
617	/** Big page (must be 0 here). */
618	uint64_t u1Size : 1;
619	/** Available for software. */
620	uint64_t u4Available : 4;
621	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
622	uint64_t u40PhysAddr : 40;
623	/** Availabe for software. */
624	uint64_t u12Available : 12;
625	} EPTPDEBITS;
626	#pragma pack()
627	AssertCompileSize(EPTPDEBITS, 8);
628
629	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
630	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
631	/** The page shift to get the PD index. */
632	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
633	/** The PD index mask (apply to a shifted page address). */
634	#define EPT_PD_MASK X86_PD_PAE_MASK
635
636	/**
637	* EPT 2MB Page Directory Table Entry. Bit view.
638	*/
639	#pragma pack(1)
640	typedef struct EPTPDE2MBITS
641	{
642	/** Present bit. */
643	uint64_t u1Present : 1;
644	/** Writable bit. */
645	uint64_t u1Write : 1;
646	/** Executable bit. */
647	uint64_t u1Execute : 1;
648	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
649	uint64_t u3EMT : 3;
650	/** Ignore PAT memory type */
651	uint64_t u1IgnorePAT : 1;
652	/** Big page (must be 1 here). */
653	uint64_t u1Size : 1;
654	/** Available for software. */
655	uint64_t u4Available : 4;
656	/** Reserved (must be 0). */
657	uint64_t u9Reserved : 9;
658	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
659	uint64_t u31PhysAddr : 31;
660	/** Availabe for software. */
661	uint64_t u12Available : 12;
662	} EPTPDE2MBITS;
663	#pragma pack()
664	AssertCompileSize(EPTPDE2MBITS, 8);
665
666	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
667	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
668
669	/**
670	* EPT Page Directory Table Entry.
671	*/
672	#pragma pack(1)
673	typedef union EPTPDE
674	{
675	/** Normal view. */
676	EPTPDEBITS n;
677	/** 2MB view (big). */
678	EPTPDE2MBITS b;
679	/** Unsigned integer view. */
680	X86PGPAEUINT u;
681	/** 64 bit unsigned integer view. */
682	uint64_t au64[1];
683	/** 32 bit unsigned integer view. */
684	uint32_t au32[2];
685	} EPTPDE;
686	#pragma pack()
687	/** Pointer to an EPT Page Directory Table Entry. */
688	typedef EPTPDE *PEPTPDE;
689	/** Pointer to a const EPT Page Directory Table Entry. */
690	typedef const EPTPDE *PCEPTPDE;
691	AssertCompileSize(EPTPDE, 8);
692
693	/**
694	* EPT Page Directory Table.
695	*/
696	#pragma pack(1)
697	typedef struct EPTPD
698	{
699	EPTPDE a[EPT_PG_ENTRIES];
700	} EPTPD;
701	#pragma pack()
702	/** Pointer to an EPT Page Directory Table. */
703	typedef EPTPD *PEPTPD;
704	/** Pointer to a const EPT Page Directory Table. */
705	typedef const EPTPD *PCEPTPD;
706
707
708	/**
709	* EPT Page Table Entry. Bit view.
710	*/
711	#pragma pack(1)
712	typedef struct EPTPTEBITS
713	{
714	/** 0 - Present bit.
715	* @remark This is a convenience "misnomer". The bit actually indicates
716	* read access and the CPU will consider an entry with any of the
717	* first three bits set as present. Since all our valid entries
718	* will have this bit set, it can be used as a present indicator
719	* and allow some code sharing. */
720	uint64_t u1Present : 1;
721	/** 1 - Writable bit. */
722	uint64_t u1Write : 1;
723	/** 2 - Executable bit. */
724	uint64_t u1Execute : 1;
725	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
726	uint64_t u3EMT : 3;
727	/** 6 - Ignore PAT memory type */
728	uint64_t u1IgnorePAT : 1;
729	/** 11:7 - Available for software. */
730	uint64_t u5Available : 5;
731	/** 51:12 - Physical address of page. Restricted by maximum physical
732	* address width of the cpu. */
733	uint64_t u40PhysAddr : 40;
734	/** 63:52 - Available for software. */
735	uint64_t u12Available : 12;
736	} EPTPTEBITS;
737	#pragma pack()
738	AssertCompileSize(EPTPTEBITS, 8);
739
740	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
741	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
742	/** The page shift to get the EPT PTE index. */
743	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
744	/** The EPT PT index mask (apply to a shifted page address). */
745	#define EPT_PT_MASK X86_PT_PAE_MASK
746
747	/**
748	* EPT Page Table Entry.
749	*/
750	#pragma pack(1)
751	typedef union EPTPTE
752	{
753	/** Normal view. */
754	EPTPTEBITS n;
755	/** Unsigned integer view. */
756	X86PGPAEUINT u;
757	/** 64 bit unsigned integer view. */
758	uint64_t au64[1];
759	/** 32 bit unsigned integer view. */
760	uint32_t au32[2];
761	} EPTPTE;
762	#pragma pack()
763	/** Pointer to an EPT Page Directory Table Entry. */
764	typedef EPTPTE *PEPTPTE;
765	/** Pointer to a const EPT Page Directory Table Entry. */
766	typedef const EPTPTE *PCEPTPTE;
767	AssertCompileSize(EPTPTE, 8);
768
769	/**
770	* EPT Page Table.
771	*/
772	#pragma pack(1)
773	typedef struct EPTPT
774	{
775	EPTPTE a[EPT_PG_ENTRIES];
776	} EPTPT;
777	#pragma pack()
778	/** Pointer to an extended page table. */
779	typedef EPTPT *PEPTPT;
780	/** Pointer to a const extended table. */
781	typedef const EPTPT *PCEPTPT;
782
783	/** @name VMX VPID flush types.
784	* Warning!! Valid enum members are in accordance to the VT-x spec.
785	* @{
786	*/
787	typedef enum
788	{
789	/** Invalidate a specific page. */
790	VMXFLUSHVPID_INDIV_ADDR = 0,
791	/** Invalidate one context (specific VPID). */
792	VMXFLUSHVPID_SINGLE_CONTEXT = 1,
793	/** Invalidate all contexts (all VPIDs). */
794	VMXFLUSHVPID_ALL_CONTEXTS = 2,
795	/** Invalidate a single VPID context retaining global mappings. */
796	VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
797	/** Unsupported by VirtualBox. */
798	VMXFLUSHVPID_NOT_SUPPORTED = 0xbad0,
799	/** Unsupported by CPU. */
800	VMXFLUSHVPID_NONE = 0xbad1
801	} VMXFLUSHVPID;
802	AssertCompileSize(VMXFLUSHVPID, 4);
803	/** @} */
804
805	/** @name VMX EPT flush types.
806	* Warning!! Valid enums values below are in accordance to the VT-x spec.
807	* @{
808	*/
809	typedef enum
810	{
811	/** Invalidate one context (specific EPT). */
812	VMXFLUSHEPT_SINGLE_CONTEXT = 1,
813	/* Invalidate all contexts (all EPTs) */
814	VMXFLUSHEPT_ALL_CONTEXTS = 2,
815	/** Unsupported by VirtualBox. */
816	VMXFLUSHEPT_NOT_SUPPORTED = 0xbad0,
817	/** Unsupported by CPU. */
818	VMXFLUSHEPT_NONE = 0xbad1
819	} VMXFLUSHEPT;
820	AssertCompileSize(VMXFLUSHEPT, 4);
821	/** @} */
822
823	/** @name VMX MSR autoload/store element.
824	* In accordance to VT-x spec.
825	* @{
826	*/
827	#pragma pack(1)
828	typedef struct
829	{
830	/** The MSR Id. */
831	uint32_t u32Msr;
832	/** Reserved (MBZ). */
833	uint32_t u32Reserved;
834	/** The MSR value. */
835	uint64_t u64Value;
836	} VMXAUTOMSR;
837	#pragma pack()
838	/** Pointer to an MSR load/store element. */
839	typedef VMXAUTOMSR *PVMXAUTOMSR;
840	/** Pointer to a const MSR load/store element. */
841	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
842	/** @} */
843
844	/** @name VMX-capability qword
845	* @{
846	*/
847	#pragma pack(1)
848	typedef union
849	{
850	struct
851	{
852	/** Bits set here -must- be set in the correpsonding VM-execution controls. */
853	uint32_t disallowed0;
854	/** Bits cleared here -must- be cleared in the corresponding VM-execution
855	* controls. */
856	uint32_t allowed1;
857	} n;
858	uint64_t u;
859	} VMXCAPABILITY;
860	#pragma pack()
861	/** @} */
862
863	/** @name VMX MSRs.
864	* @{
865	*/
866	typedef struct VMXMSRS
867	{
868	uint64_t u64FeatureCtrl;
869	uint64_t u64BasicInfo;
870	VMXCAPABILITY VmxPinCtls;
871	VMXCAPABILITY VmxProcCtls;
872	VMXCAPABILITY VmxProcCtls2;
873	VMXCAPABILITY VmxExit;
874	VMXCAPABILITY VmxEntry;
875	uint64_t u64Misc;
876	uint64_t u64Cr0Fixed0;
877	uint64_t u64Cr0Fixed1;
878	uint64_t u64Cr4Fixed0;
879	uint64_t u64Cr4Fixed1;
880	uint64_t u64VmcsEnum;
881	uint64_t u64Vmfunc;
882	uint64_t u64EptVpidCaps;
883	} VMXMSRS;
884	/** Pointer to a VMXMSRS struct. */
885	typedef VMXMSRS *PVMXMSRS;
886	AssertCompileSizeAlignment(VMXMSRS, 8);
887	/** @} */
888
889	/** @name VMX EFLAGS reserved bits.
890	* @{
891	*/
892	/** And-mask for setting reserved bits to zero */
893	#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
894	/** Or-mask for setting reserved bits to 1 */
895	#define VMX_EFLAGS_RESERVED_1 0x00000002
896	/** @} */
897
898	/** @name VMX Basic Exit Reasons.
899	* @{
900	*/
901	/** -1 Invalid exit code */
902	#define VMX_EXIT_INVALID -1
903	/** 0 Exception or non-maskable interrupt (NMI). */
904	#define VMX_EXIT_XCPT_OR_NMI 0
905	/** 1 External interrupt. */
906	#define VMX_EXIT_EXT_INT 1
907	/** 2 Triple fault. */
908	#define VMX_EXIT_TRIPLE_FAULT 2
909	/** 3 INIT signal. */
910	#define VMX_EXIT_INIT_SIGNAL 3
911	/** 4 Start-up IPI (SIPI). */
912	#define VMX_EXIT_SIPI 4
913	/** 5 I/O system-management interrupt (SMI). */
914	#define VMX_EXIT_IO_SMI 5
915	/** 6 Other SMI. */
916	#define VMX_EXIT_SMI 6
917	/** 7 Interrupt window exiting. */
918	#define VMX_EXIT_INT_WINDOW 7
919	/** 8 NMI window exiting. */
920	#define VMX_EXIT_NMI_WINDOW 8
921	/** 9 Task switch. */
922	#define VMX_EXIT_TASK_SWITCH 9
923	/** 10 Guest software attempted to execute CPUID. */
924	#define VMX_EXIT_CPUID 10
925	/** 10 Guest software attempted to execute GETSEC. */
926	#define VMX_EXIT_GETSEC 11
927	/** 12 Guest software attempted to execute HLT. */
928	#define VMX_EXIT_HLT 12
929	/** 13 Guest software attempted to execute INVD. */
930	#define VMX_EXIT_INVD 13
931	/** 14 Guest software attempted to execute INVLPG. */
932	#define VMX_EXIT_INVLPG 14
933	/** 15 Guest software attempted to execute RDPMC. */
934	#define VMX_EXIT_RDPMC 15
935	/** 16 Guest software attempted to execute RDTSC. */
936	#define VMX_EXIT_RDTSC 16
937	/** 17 Guest software attempted to execute RSM in SMM. */
938	#define VMX_EXIT_RSM 17
939	/** 18 Guest software executed VMCALL. */
940	#define VMX_EXIT_VMCALL 18
941	/** 19 Guest software executed VMCLEAR. */
942	#define VMX_EXIT_VMCLEAR 19
943	/** 20 Guest software executed VMLAUNCH. */
944	#define VMX_EXIT_VMLAUNCH 20
945	/** 21 Guest software executed VMPTRLD. */
946	#define VMX_EXIT_VMPTRLD 21
947	/** 22 Guest software executed VMPTRST. */
948	#define VMX_EXIT_VMPTRST 22
949	/** 23 Guest software executed VMREAD. */
950	#define VMX_EXIT_VMREAD 23
951	/** 24 Guest software executed VMRESUME. */
952	#define VMX_EXIT_VMRESUME 24
953	/** 25 Guest software executed VMWRITE. */
954	#define VMX_EXIT_VMWRITE 25
955	/** 26 Guest software executed VMXOFF. */
956	#define VMX_EXIT_VMXOFF 26
957	/** 27 Guest software executed VMXON. */
958	#define VMX_EXIT_VMXON 27
959	/** 28 Control-register accesses. */
960	#define VMX_EXIT_MOV_CRX 28
961	/** 29 Debug-register accesses. */
962	#define VMX_EXIT_MOV_DRX 29
963	/** 30 I/O instruction. */
964	#define VMX_EXIT_IO_INSTR 30
965	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
966	#define VMX_EXIT_RDMSR 31
967	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
968	#define VMX_EXIT_WRMSR 32
969	/** 33 VM-entry failure due to invalid guest state. */
970	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
971	/** 34 VM-entry failure due to MSR loading. */
972	#define VMX_EXIT_ERR_MSR_LOAD 34
973	/** 36 Guest software executed MWAIT. */
974	#define VMX_EXIT_MWAIT 36
975	/** 37 VM-exit due to monitor trap flag. */
976	#define VMX_EXIT_MTF 37
977	/** 39 Guest software attempted to execute MONITOR. */
978	#define VMX_EXIT_MONITOR 39
979	/** 40 Guest software attempted to execute PAUSE. */
980	#define VMX_EXIT_PAUSE 40
981	/** 41 VM-entry failure due to machine-check. */
982	#define VMX_EXIT_ERR_MACHINE_CHECK 41
983	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
984	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
985	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
986	#define VMX_EXIT_APIC_ACCESS 44
987	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
988	#define VMX_EXIT_XDTR_ACCESS 46
989	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
990	#define VMX_EXIT_TR_ACCESS 47
991	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
992	#define VMX_EXIT_EPT_VIOLATION 48
993	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
994	#define VMX_EXIT_EPT_MISCONFIG 49
995	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
996	#define VMX_EXIT_INVEPT 50
997	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
998	#define VMX_EXIT_RDTSCP 51
999	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1000	#define VMX_EXIT_PREEMPT_TIMER 52
1001	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1002	#define VMX_EXIT_INVVPID 53
1003	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1004	#define VMX_EXIT_WBINVD 54
1005	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1006	#define VMX_EXIT_XSETBV 55
1007	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1008	#define VMX_EXIT_RDRAND 57
1009	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1010	#define VMX_EXIT_INVPCID 58
1011	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1012	#define VMX_EXIT_VMFUNC 59
1013	/** The maximum exit value (inclusive). */
1014	#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
1015	/** @} */
1016
1017
1018	/** @name VM Instruction Errors
1019	* @{
1020	*/
1021	/** VMCALL executed in VMX root operation. */
1022	#define VMX_ERROR_VMCALL 1
1023	/** VMCLEAR with invalid physical address. */
1024	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1025	/** VMCLEAR with VMXON pointer. */
1026	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1027	/** VMLAUNCH with non-clear VMCS. */
1028	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1029	/** VMRESUME with non-launched VMCS. */
1030	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1031	/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1032	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1033	/** VM-entry with invalid control field(s). */
1034	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1035	/** VM-entry with invalid host-state field(s). */
1036	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1037	/** VMPTRLD with invalid physical address. */
1038	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1039	/** VMPTRLD with VMXON pointer. */
1040	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1041	/** VMPTRLD with incorrect VMCS revision identifier. */
1042	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1043	/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1044	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1045	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1046	/** VMWRITE to read-only VMCS component. */
1047	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1048	/** VMXON executed in VMX root operation. */
1049	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1050	/** VM-entry with invalid executive-VMCS pointer. */
1051	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1052	/** VM-entry with non-launched executive VMCS. */
1053	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1054	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1055	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1056	/** VMCALL with non-clear VMCS. */
1057	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1058	/** VMCALL with invalid VM-exit control fields. */
1059	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1060	/** VMCALL with incorrect MSEG revision identifier. */
1061	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1062	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1063	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1064	/** VMCALL with invalid SMM-monitor features. */
1065	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1066	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1067	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1068	/** VM-entry with events blocked by MOV SS. */
1069	#define VMX_ERROR_VMENTRY_MOV_SS 26
1070	/** Invalid operand to INVEPT/INVVPID. */
1071	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1072
1073	/** @} */
1074
1075
1076	/** @name VMX MSRs - Basic VMX information.
1077	* @{
1078	*/
1079	/** VMCS revision identifier used by the processor. */
1080	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) ((a) & 0x7FFFFFFF)
1081	/** Size of the VMCS. */
1082	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0x1FFF)
1083	/** Width of physical address used for the VMCS.
1084	* 0 -> limited to the available amount of physical ram
1085	* 1 -> within the first 4 GB
1086	*/
1087	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1088	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1089	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1090	/** Memory type that must be used for the VMCS. */
1091	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1092	/** Whether the processor provides additional information for exits due to INS/OUTS. */
1093	#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1094	/** @} */
1095
1096
1097	/** @name VMX MSRs - Misc VMX info.
1098	* @{
1099	*/
1100	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1101	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1102	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1103	#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1104	/** Activity states supported by the implementation. */
1105	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1106	/** Number of CR3 target values supported by the processor. (0-256) */
1107	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1108	/** Maximum nr of MSRs in the VMCS. (N+1)512. /
1109	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1110	/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1111	#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1112	/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1113	#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1114	/** Whether VMWRITE can be used to write VM-exit information fields. */
1115	#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1116	/** MSEG revision identifier used by the processor. */
1117	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1118	/** @} */
1119
1120
1121	/** @name VMX MSRs - VMCS enumeration field info
1122	* @{
1123	*/
1124	/** Highest field index. */
1125	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1126	/** @} */
1127
1128
1129	/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1130	* @{
1131	*/
1132	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1133	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
1134	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
1135	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
1136	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
1137	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
1138	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
1139	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
1140	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1141	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
1142	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
1143	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
1144	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1145	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
1146	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
1147	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
1148	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
1149	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1150	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1151	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1152	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1153	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1154	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1155	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1156	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1157
1158	/** @} */
1159
1160	/** @name Extended Page Table Pointer (EPTP)
1161	* @{
1162	*/
1163	/** Uncachable EPT paging structure memory type. */
1164	#define VMX_EPT_MEMTYPE_UC 0
1165	/** Write-back EPT paging structure memory type. */
1166	#define VMX_EPT_MEMTYPE_WB 6
1167	/** Shift value to get the EPT page walk length (bits 5-3) */
1168	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1169	/** Mask value to get the EPT page walk length (bits 5-3) */
1170	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1171	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1172	* length) */
1173	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1174	/** @} */
1175
1176
1177	/** @name VMCS field encoding - 16 bits guest fields
1178	* @{
1179	*/
1180	#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
1181	#define VMX_VMCS16_GUEST_FIELD_ES 0x800
1182	#define VMX_VMCS16_GUEST_FIELD_CS 0x802
1183	#define VMX_VMCS16_GUEST_FIELD_SS 0x804
1184	#define VMX_VMCS16_GUEST_FIELD_DS 0x806
1185	#define VMX_VMCS16_GUEST_FIELD_FS 0x808
1186	#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
1187	#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
1188	#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
1189	/** @} */
1190
1191	/** @name VMCS field encoding - 16 bits host fields
1192	* @{
1193	*/
1194	#define VMX_VMCS16_HOST_FIELD_ES 0xC00
1195	#define VMX_VMCS16_HOST_FIELD_CS 0xC02
1196	#define VMX_VMCS16_HOST_FIELD_SS 0xC04
1197	#define VMX_VMCS16_HOST_FIELD_DS 0xC06
1198	#define VMX_VMCS16_HOST_FIELD_FS 0xC08
1199	#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
1200	#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
1201	/** @} */
1202
1203	/** @name VMCS field encoding - 64 bits host fields
1204	* @{
1205	*/
1206	#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
1207	#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
1208	#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
1209	#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
1210	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
1211	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
1212	/** @} */
1213
1214
1215	/** @name VMCS field encoding - 64 Bits control fields
1216	* @{
1217	*/
1218	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1219	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1220	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1221	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1222
1223	/* Optional */
1224	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1225	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1226
1227	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1228	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1229	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1230	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1231
1232	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1233	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1234
1235	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1236	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1237
1238	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1239	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1240
1241	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1242	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1243	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1244
1245	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1246	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1247	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1248
1249	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1250	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1251	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1252
1253	/** Extended page table pointer. */
1254	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1255	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1256
1257	/** Extended page table pointer lists. */
1258	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1259	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1260
1261	/** VM-exit guest phyiscal address. */
1262	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1263	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1264	/** @} */
1265
1266
1267	/** @name VMCS field encoding - 64 Bits guest fields
1268	* @{
1269	*/
1270	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1271	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1272	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
1273	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
1274	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1275	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1276	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1277	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1278	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
1279	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
1280	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1281	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1282	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1283	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1284	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1285	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1286	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1287	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1288	/** @} */
1289
1290
1291	/** @name VMCS field encoding - 32 Bits control fields
1292	* @{
1293	*/
1294	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1295	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1296	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1297	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1298	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1299	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1300	#define VMX_VMCS32_CTRL_EXIT 0x400C
1301	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1302	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1303	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1304	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1305	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1306	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1307	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1308	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1309	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1310	/** @} */
1311
1312
1313	/** @name VMX_VMCS_CTRL_PIN_EXEC
1314	* @{
1315	*/
1316	/** External interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1317	#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1318	/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1319	#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1320	/** Virtual NMIs. */
1321	#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1322	/** Activate VMX preemption timer. */
1323	#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1324	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1325	/** @} */
1326
1327	/** @name VMX_VMCS_CTRL_PROC_EXEC
1328	* @{
1329	*/
1330	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1331	#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1332	/** Use timestamp counter offset. */
1333	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1334	/** VM-exit when executing the HLT instruction. */
1335	#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1336	/** VM-exit when executing the INVLPG instruction. */
1337	#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1338	/** VM-exit when executing the MWAIT instruction. */
1339	#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1340	/** VM-exit when executing the RDPMC instruction. */
1341	#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1342	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1343	#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1344	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1345	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1346	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1347	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1348	/** VM-exit on CR8 loads. */
1349	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1350	/** VM-exit on CR8 stores. */
1351	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1352	/** Use TPR shadow. */
1353	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1354	/** VM-exit when virtual NMI blocking is disabled. */
1355	#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1356	/** VM-exit when executing a MOV DRx instruction. */
1357	#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1358	/** VM-exit when executing IO instructions. */
1359	#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1360	/** Use IO bitmaps. */
1361	#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1362	/** Monitor trap flag. */
1363	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1364	/** Use MSR bitmaps. */
1365	#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1366	/** VM-exit when executing the MONITOR instruction. */
1367	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1368	/** VM-exit when executing the PAUSE instruction. */
1369	#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1370	/** Determines whether the secondary processor based VM-execution controls are used. */
1371	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1372	/** @} */
1373
1374	/** @name VMX_VMCS_CTRL_PROC_EXEC2
1375	* @{
1376	*/
1377	/** Virtualize APIC access. */
1378	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1379	/** EPT supported/enabled. */
1380	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1381	/** Descriptor table instructions cause VM-exits. */
1382	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1383	/** RDTSCP supported/enabled. */
1384	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1385	/** Virtualize x2APIC mode. */
1386	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1387	/** VPID supported/enabled. */
1388	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1389	/** VM-exit when executing the WBINVD instruction. */
1390	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1391	/** Unrestricted guest execution. */
1392	#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1393	/** A specified nr of pause loops cause a VM-exit. */
1394	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1395	/** VM-exit when executing RDRAND instructions. */
1396	#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1397	/** Enables INVPCID instructions. */
1398	#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1399	/** Enables VMFUNC instructions. */
1400	#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1401	/** @} */
1402
1403
1404	/** @name VMX_VMCS_CTRL_ENTRY
1405	* @{
1406	*/
1407	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1408	#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1409	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1410	#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1411	/** In SMM mode after VM-entry. */
1412	#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1413	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1414	#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1415	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
1416	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1417	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
1418	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1419	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
1420	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1421	/** @} */
1422
1423
1424	/** @name VMX_VMCS_CTRL_EXIT
1425	* @{
1426	*/
1427	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1428	#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1429	/** Return to long mode after a VM-exit. */
1430	#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1431	/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
1432	#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1433	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1434	#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1435	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
1436	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1437	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
1438	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1439	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
1440	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1441	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
1442	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1443	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
1444	#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1445	/** @} */
1446
1447
1448	/** @name VMX_VMCS_CTRL_VMFUNC
1449	* @{
1450	*/
1451	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1452	#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1453	/** @} */
1454
1455
1456	/** @name VMCS field encoding - 32 Bits read-only fields
1457	* @{
1458	*/
1459	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1460	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1461	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1462	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1463	#define VMX_VMCS32_RO_IDT_INFO 0x4408
1464	#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1465	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1466	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1467	/** @} */
1468
1469	/** @name VMX_VMCS32_RO_EXIT_REASON
1470	* @{
1471	*/
1472	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
1473	/** @} */
1474
1475	/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1476	* @{
1477	*/
1478	#define VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1479	#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1480	#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1481	/** @} */
1482
1483
1484	/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1485	* @{
1486	*/
1487	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) ((a) & 0xff)
1488	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1489	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1490	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1491	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1492	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(a) ((a) & RT_BIT(12))
1493	#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1494	#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1495	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1496	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
1497	/** @} */
1498
1499	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1500	* @{
1501	*/
1502	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1503	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1504	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1505	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4
1506	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT 5
1507	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1508	/** @} */
1509
1510	/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1511	* @{
1512	*/
1513	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
1514	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1515	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1516	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1517	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1518	#define VMX_IDT_VECTORING_INFO_VALID(a) ((a) & RT_BIT(31))
1519	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
1520	/** @} */
1521
1522	/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1523	* @{
1524	*/
1525	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1526	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1527	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1528	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1529	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1530	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1531	/** @} */
1532
1533
1534	/** @name VMCS field encoding - 32 Bits guest state fields
1535	* @{
1536	*/
1537	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1538	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1539	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1540	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1541	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1542	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1543	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1544	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1545	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1546	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1547	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1548	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1549	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1550	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1551	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1552	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1553	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1554	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1555	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1556	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1557	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
1558	#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1559	/** @} */
1560
1561
1562	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1563	* @{
1564	*/
1565	/** The logical processor is active. */
1566	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1567	/** The logical processor is inactive, because executed a HLT instruction. */
1568	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1569	/** The logical processor is inactive, because of a triple fault or other serious error. */
1570	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1571	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1572	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1573	/** @} */
1574
1575
1576	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1577	* @{
1578	*/
1579	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1580	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1581	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1582	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1583	/** @} */
1584
1585
1586	/** @name VMCS field encoding - 32 Bits host state fields
1587	* @{
1588	*/
1589	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1590	/** @} */
1591
1592	/** @name Natural width control fields
1593	* @{
1594	*/
1595	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1596	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1597	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1598	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1599	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1600	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1601	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1602	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1603	/** @} */
1604
1605
1606	/** @name Natural width read-only data fields
1607	* @{
1608	*/
1609	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1610	#define VMX_VMCS_RO_IO_RCX 0x6402
1611	#define VMX_VMCS_RO_IO_RSX 0x6404
1612	#define VMX_VMCS_RO_IO_RDI 0x6406
1613	#define VMX_VMCS_RO_IO_RIP 0x6408
1614	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1615	/** @} */
1616
1617
1618	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1619	* @{
1620	*/
1621	/** 0-2: Debug register number */
1622	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) ((a) & 7)
1623	/** 3: Reserved; cleared to 0. */
1624	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) (((a) >> 3) & 1)
1625	/** 4: Direction of move (0 = write, 1 = read) */
1626	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) (((a) >> 4) & 1)
1627	/** 5-7: Reserved; cleared to 0. */
1628	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) (((a) >> 5) & 7)
1629	/** 8-11: General purpose register number. */
1630	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) (((a) >> 8) & 0xF)
1631	/** Rest: reserved. */
1632	/** @} */
1633
1634	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1635	* @{
1636	*/
1637	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1638	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1639	/** @} */
1640
1641
1642
1643	/** @name CRx accesses
1644	* @{
1645	*/
1646	/** 0-3: Control register number (0 for CLTS & LMSW) */
1647	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) ((a) & 0xF)
1648	/** 4-5: Access type. */
1649	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) (((a) >> 4) & 3)
1650	/** 6: LMSW operand type */
1651	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) (((a) >> 6) & 1)
1652	/** 7: Reserved; cleared to 0. */
1653	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) (((a) >> 7) & 1)
1654	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1655	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) (((a) >> 8) & 0xF)
1656	/** 12-15: Reserved; cleared to 0. */
1657	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) (((a) >> 12) & 0xF)
1658	/** 16-31: LMSW source data (else 0). */
1659	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) (((a) >> 16) & 0xFFFF)
1660	/** Rest: reserved. */
1661	/** @} */
1662
1663	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1664	* @{
1665	*/
1666	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1667	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1668	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1669	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1670	/** @} */
1671
1672	/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1673	* @{
1674	*/
1675	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
1676	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
1677	/** Task switch caused by a call instruction. */
1678	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1679	/** Task switch caused by an iret instruction. */
1680	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1681	/** Task switch caused by a jmp instruction. */
1682	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1683	/** Task switch caused by an interrupt gate. */
1684	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1685	/** @} */
1686
1687
1688	/** @name VMX_EXIT_EPT_VIOLATION
1689	* @{
1690	*/
1691	/** Set if the violation was caused by a data read. */
1692	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1693	/** Set if the violation was caused by a data write. */
1694	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1695	/** Set if the violation was caused by an insruction fetch. */
1696	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1697	/** AND of the present bit of all EPT structures. */
1698	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1699	/** AND of the write bit of all EPT structures. */
1700	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1701	/** AND of the execute bit of all EPT structures. */
1702	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1703	/** Set if the guest linear address field contains the faulting address. */
1704	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1705	/** If bit 7 is one: (reserved otherwise)
1706	* 1 - violation due to physical address access.
1707	* 0 - violation caused by page walk or access/dirty bit updates
1708	*/
1709	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1710	/** @} */
1711
1712
1713	/** @name VMX_EXIT_PORT_IO
1714	* @{
1715	*/
1716	/** 0-2: IO operation width. */
1717	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1718	/** 3: IO operation direction. */
1719	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1720	/** 4: String IO operation (INS / OUTS). */
1721	#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1722	/** 5: Repeated IO operation. */
1723	#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1724	/** 6: Operand encoding. */
1725	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1726	/** 16-31: IO Port (0-0xffff). */
1727	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1728	/* Rest reserved. */
1729	/** @} */
1730
1731	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1732	* @{
1733	*/
1734	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1735	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1736	/** @} */
1737
1738
1739	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1740	* @{
1741	*/
1742	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1743	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1744	/** @} */
1745
1746	/** @name VMX_EXIT_APIC_ACCESS
1747	* @{
1748	*/
1749	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of access within the APIC page. */
1750	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1751	/** 12-15: Access type. */
1752	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000)
1753	/* Rest reserved. */
1754	/** @} */
1755
1756
1757	/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1758	* @{
1759	*/
1760	/** Linear read access. */
1761	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1762	/** Linear write access. */
1763	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1764	/** Linear instruction fetch access. */
1765	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1766	/** Linear read/write access during event delivery. */
1767	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1768	/** Physical read/write access during event delivery. */
1769	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1770	/** Physical access for an instruction fetch or during instruction execution. */
1771	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1772	/** @} */
1773
1774	/** @} */
1775
1776	/** @name VMCS field encoding - Natural width guest state fields
1777	* @{
1778	*/
1779	#define VMX_VMCS_GUEST_CR0 0x6800
1780	#define VMX_VMCS_GUEST_CR3 0x6802
1781	#define VMX_VMCS_GUEST_CR4 0x6804
1782	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1783	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1784	#define VMX_VMCS_GUEST_SS_BASE 0x680A
1785	#define VMX_VMCS_GUEST_DS_BASE 0x680C
1786	#define VMX_VMCS_GUEST_FS_BASE 0x680E
1787	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1788	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1789	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1790	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1791	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1792	#define VMX_VMCS_GUEST_DR7 0x681A
1793	#define VMX_VMCS_GUEST_RSP 0x681C
1794	#define VMX_VMCS_GUEST_RIP 0x681E
1795	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1796	#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1797	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1798	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1799	/** @} */
1800
1801
1802	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1803	* @{
1804	*/
1805	/** Hardware breakpoint 0 was met. */
1806	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1807	/** Hardware breakpoint 1 was met. */
1808	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1809	/** Hardware breakpoint 2 was met. */
1810	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1811	/** Hardware breakpoint 3 was met. */
1812	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1813	/** At least one data or IO breakpoint was hit. */
1814	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1815	/** A debug exception would have been triggered by single-step execution mode. */
1816	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1817	/** Bits 4-11, 13 and 15-63 are reserved. */
1818
1819	/** @} */
1820
1821	/** @name VMCS field encoding - Natural width host state fields
1822	* @{
1823	*/
1824	#define VMX_VMCS_HOST_CR0 0x6C00
1825	#define VMX_VMCS_HOST_CR3 0x6C02
1826	#define VMX_VMCS_HOST_CR4 0x6C04
1827	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1828	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1829	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1830	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1831	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1832	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1833	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1834	#define VMX_VMCS_HOST_RSP 0x6C14
1835	#define VMX_VMCS_HOST_RIP 0x6C16
1836	/** @} */
1837
1838	/** @} */
1839
1840
1841	/** @defgroup grp_vmx_asm vmx assembly helpers
1842	* @ingroup grp_vmx
1843	* @{
1844	*/
1845
1846	/**
1847	* Restores some host-state fields that need not be done on every VM-exit.
1848	*
1849	* @returns VBox status code.
1850	* @param fRestoreHostFlags Flags of which host registers needs to be
1851	* restored.
1852	* @param pRestoreHost Pointer to the host-restore structure.
1853	*/
1854	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1855
1856
1857	/**
1858	* Dispatches an NMI to the host.
1859	*/
1860	DECLASM(int) VMXDispatchHostNmi(void);
1861
1862
1863	/**
1864	* Executes VMXON
1865	*
1866	* @returns VBox status code
1867	* @param pVMXOn Physical address of VMXON structure
1868	*/
1869	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1870	DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1871	#else
1872	DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1873	{
1874	# if RT_INLINE_ASM_GNU_STYLE
1875	int rc = VINF_SUCCESS;
1876	__asm__ __volatile__ (
1877	"push %3 \n\t"
1878	"push %2 \n\t"
1879	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1880	"ja 2f \n\t"
1881	"je 1f \n\t"
1882	"movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1883	"jmp 2f \n\t"
1884	"1: \n\t"
1885	"movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1886	"2: \n\t"
1887	"add $8, %%esp \n\t"
1888	:"=rm"(rc)
1889	:"0"(VINF_SUCCESS),
1890	"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1891	"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1892	:"memory"
1893	);
1894	return rc;
1895
1896	# elif VMX_USE_MSC_INTRINSICS
1897	unsigned char rcMsc = __vmx_on(&pVMXOn);
1898	if (RT_LIKELY(rcMsc == 0))
1899	return VINF_SUCCESS;
1900	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
1901
1902	# else
1903	int rc = VINF_SUCCESS;
1904	__asm
1905	{
1906	push dword ptr [pVMXOn+4]
1907	push dword ptr [pVMXOn]
1908	_emit 0xF3
1909	_emit 0x0F
1910	_emit 0xC7
1911	_emit 0x34
1912	_emit 0x24 /* VMXON [esp] */
1913	jnc vmxon_good
1914	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1915	jmp the_end
1916
1917	vmxon_good:
1918	jnz the_end
1919	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1920	the_end:
1921	add esp, 8
1922	}
1923	return rc;
1924	# endif
1925	}
1926	#endif
1927
1928
1929	/**
1930	* Executes VMXOFF
1931	*/
1932	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1933	DECLASM(void) VMXDisable(void);
1934	#else
1935	DECLINLINE(void) VMXDisable(void)
1936	{
1937	# if RT_INLINE_ASM_GNU_STYLE
1938	__asm__ __volatile__ (
1939	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1940	);
1941
1942	# elif VMX_USE_MSC_INTRINSICS
1943	__vmx_off();
1944
1945	# else
1946	__asm
1947	{
1948	_emit 0x0F
1949	_emit 0x01
1950	_emit 0xC4 /* VMXOFF */
1951	}
1952	# endif
1953	}
1954	#endif
1955
1956
1957	/**
1958	* Executes VMCLEAR
1959	*
1960	* @returns VBox status code
1961	* @param pVMCS Physical address of VM control structure
1962	*/
1963	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1964	DECLASM(int) VMXClearVmcs(RTHCPHYS pVMCS);
1965	#else
1966	DECLINLINE(int) VMXClearVmcs(RTHCPHYS pVMCS)
1967	{
1968	# if RT_INLINE_ASM_GNU_STYLE
1969	int rc = VINF_SUCCESS;
1970	__asm__ __volatile__ (
1971	"push %3 \n\t"
1972	"push %2 \n\t"
1973	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1974	"jnc 1f \n\t"
1975	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1976	"1: \n\t"
1977	"add $8, %%esp \n\t"
1978	:"=rm"(rc)
1979	:"0"(VINF_SUCCESS),
1980	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1981	"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1982	:"memory"
1983	);
1984	return rc;
1985
1986	# elif VMX_USE_MSC_INTRINSICS
1987	unsigned char rcMsc = __vmx_vmclear(&pVMCS);
1988	if (RT_LIKELY(rcMsc == 0))
1989	return VINF_SUCCESS;
1990	return VERR_VMX_INVALID_VMCS_PTR;
1991
1992	# else
1993	int rc = VINF_SUCCESS;
1994	__asm
1995	{
1996	push dword ptr [pVMCS+4]
1997	push dword ptr [pVMCS]
1998	_emit 0x66
1999	_emit 0x0F
2000	_emit 0xC7
2001	_emit 0x34
2002	_emit 0x24 /* VMCLEAR [esp] */
2003	jnc success
2004	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2005	success:
2006	add esp, 8
2007	}
2008	return rc;
2009	# endif
2010	}
2011	#endif
2012
2013
2014	/**
2015	* Executes VMPTRLD
2016	*
2017	* @returns VBox status code
2018	* @param pVMCS Physical address of VMCS structure
2019	*/
2020	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2021	DECLASM(int) VMXActivateVmcs(RTHCPHYS pVMCS);
2022	#else
2023	DECLINLINE(int) VMXActivateVmcs(RTHCPHYS pVMCS)
2024	{
2025	# if RT_INLINE_ASM_GNU_STYLE
2026	int rc = VINF_SUCCESS;
2027	__asm__ __volatile__ (
2028	"push %3 \n\t"
2029	"push %2 \n\t"
2030	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2031	"jnc 1f \n\t"
2032	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2033	"1: \n\t"
2034	"add $8, %%esp \n\t"
2035	:"=rm"(rc)
2036	:"0"(VINF_SUCCESS),
2037	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
2038	"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
2039	);
2040	return rc;
2041
2042	# elif VMX_USE_MSC_INTRINSICS
2043	unsigned char rcMsc = __vmx_vmptrld(&pVMCS);
2044	if (RT_LIKELY(rcMsc == 0))
2045	return VINF_SUCCESS;
2046	return VERR_VMX_INVALID_VMCS_PTR;
2047
2048	# else
2049	int rc = VINF_SUCCESS;
2050	__asm
2051	{
2052	push dword ptr [pVMCS+4]
2053	push dword ptr [pVMCS]
2054	_emit 0x0F
2055	_emit 0xC7
2056	_emit 0x34
2057	_emit 0x24 /* VMPTRLD [esp] */
2058	jnc success
2059	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2060
2061	success:
2062	add esp, 8
2063	}
2064	return rc;
2065	# endif
2066	}
2067	#endif
2068
2069	/**
2070	* Executes VMPTRST
2071	*
2072	* @returns VBox status code
2073	* @param pVMCS Address that will receive the current pointer
2074	*/
2075	DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pVMCS);
2076
2077	/**
2078	* Executes VMWRITE
2079	*
2080	* @returns VBox status code
2081	* @retval VINF_SUCCESS
2082	* @retval VERR_VMX_INVALID_VMCS_PTR
2083	* @retval VERR_VMX_INVALID_VMCS_FIELD
2084	*
2085	* @param idxField VMCS index
2086	* @param u32Val 32 bits value
2087	*
2088	* @remarks The values of the two status codes can be ORed together, the result
2089	* will be VERR_VMX_INVALID_VMCS_PTR.
2090	*/
2091	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2092	DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2093	#else
2094	DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2095	{
2096	# if RT_INLINE_ASM_GNU_STYLE
2097	int rc = VINF_SUCCESS;
2098	__asm__ __volatile__ (
2099	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2100	"ja 2f \n\t"
2101	"je 1f \n\t"
2102	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2103	"jmp 2f \n\t"
2104	"1: \n\t"
2105	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2106	"2: \n\t"
2107	:"=rm"(rc)
2108	:"0"(VINF_SUCCESS),
2109	"a"(idxField),
2110	"d"(u32Val)
2111	);
2112	return rc;
2113
2114	# elif VMX_USE_MSC_INTRINSICS
2115	unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2116	if (RT_LIKELY(rcMsc == 0))
2117	return VINF_SUCCESS;
2118	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2119
2120	#else
2121	int rc = VINF_SUCCESS;
2122	__asm
2123	{
2124	push dword ptr [u32Val]
2125	mov eax, [idxField]
2126	_emit 0x0F
2127	_emit 0x79
2128	_emit 0x04
2129	_emit 0x24 /* VMWRITE eax, [esp] */
2130	jnc valid_vmcs
2131	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2132	jmp the_end
2133
2134	valid_vmcs:
2135	jnz the_end
2136	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2137	the_end:
2138	add esp, 4
2139	}
2140	return rc;
2141	# endif
2142	}
2143	#endif
2144
2145	/**
2146	* Executes VMWRITE
2147	*
2148	* @returns VBox status code
2149	* @retval VINF_SUCCESS
2150	* @retval VERR_VMX_INVALID_VMCS_PTR
2151	* @retval VERR_VMX_INVALID_VMCS_FIELD
2152	*
2153	* @param idxField VMCS index
2154	* @param u64Val 16, 32 or 64 bits value
2155	*
2156	* @remarks The values of the two status codes can be ORed together, the result
2157	* will be VERR_VMX_INVALID_VMCS_PTR.
2158	*/
2159	#if !defined(RT_ARCH_X86) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2160	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
2161	DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2162	# else /* VMX_USE_MSC_INTRINSICS */
2163	DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2164	{
2165	unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2166	if (RT_LIKELY(rcMsc == 0))
2167	return VINF_SUCCESS;
2168	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2169	}
2170	# endif /* VMX_USE_MSC_INTRINSICS */
2171	#else
2172	# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2173	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2174	#endif
2175
2176	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2177	# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
2178	VMXWriteVmcs64(idxField, uVal) \
2179	: VMXWriteVmcs32(idxField, uVal)
2180	# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
2181	VMXWriteVmcs64(idxField, u64Val) \
2182	: VMXWriteVmcs32(idxField, u64Val)
2183	#elif ARCH_BITS == 32
2184	# define VMXWriteVmcsHstN VMXWriteVmcs32
2185	# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2186	# else /* ARCH_BITS == 64 */
2187	# define VMXWriteVmcsHstN VMXWriteVmcs64
2188	# define VMXWriteVmcsGstN VMXWriteVmcs64
2189	# endif
2190
2191
2192	/**
2193	* Invalidate a page using invept
2194	* @returns VBox status code
2195	* @param enmFlush Type of flush
2196	* @param pDescriptor Descriptor
2197	*/
2198	DECLASM(int) VMXR0InvEPT(VMXFLUSHEPT enmFlush, uint64_t *pDescriptor);
2199
2200	/**
2201	* Invalidate a page using invvpid
2202	* @returns VBox status code
2203	* @param enmFlush Type of flush
2204	* @param pDescriptor Descriptor
2205	*/
2206	DECLASM(int) VMXR0InvVPID(VMXFLUSHVPID enmFlush, uint64_t *pDescriptor);
2207
2208	/**
2209	* Executes VMREAD
2210	*
2211	* @returns VBox status code
2212	* @retval VINF_SUCCESS
2213	* @retval VERR_VMX_INVALID_VMCS_PTR
2214	* @retval VERR_VMX_INVALID_VMCS_FIELD
2215	*
2216	* @param idxField VMCS index
2217	* @param pData Ptr to store VM field value
2218	*
2219	* @remarks The values of the two status codes can be ORed together, the result
2220	* will be VERR_VMX_INVALID_VMCS_PTR.
2221	*/
2222	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2223	DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2224	#else
2225	DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2226	{
2227	# if RT_INLINE_ASM_GNU_STYLE
2228	int rc = VINF_SUCCESS;
2229	__asm__ __volatile__ (
2230	"movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2231	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2232	"ja 2f \n\t"
2233	"je 1f \n\t"
2234	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2235	"jmp 2f \n\t"
2236	"1: \n\t"
2237	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2238	"2: \n\t"
2239	:"=&r"(rc),
2240	"=d"(*pData)
2241	:"a"(idxField),
2242	"d"(0)
2243	);
2244	return rc;
2245
2246	# elif VMX_USE_MSC_INTRINSICS
2247	unsigned char rcMsc;
2248	# if ARCH_BITS == 32
2249	rcMsc = __vmx_vmread(idxField, pData);
2250	# else
2251	uint64_t u64Tmp;
2252	rcMsc = __vmx_vmread(idxField, &u64Tmp);
2253	*pData = (uint32_t)u64Tmp;
2254	# endif
2255	if (RT_LIKELY(rcMsc == 0))
2256	return VINF_SUCCESS;
2257	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2258
2259	#else
2260	int rc = VINF_SUCCESS;
2261	__asm
2262	{
2263	sub esp, 4
2264	mov dword ptr [esp], 0
2265	mov eax, [idxField]
2266	_emit 0x0F
2267	_emit 0x78
2268	_emit 0x04
2269	_emit 0x24 /* VMREAD eax, [esp] */
2270	mov edx, pData
2271	pop dword ptr [edx]
2272	jnc valid_vmcs
2273	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2274	jmp the_end
2275
2276	valid_vmcs:
2277	jnz the_end
2278	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2279	the_end:
2280	}
2281	return rc;
2282	# endif
2283	}
2284	#endif
2285
2286	/**
2287	* Executes VMREAD
2288	*
2289	* @returns VBox status code
2290	* @retval VINF_SUCCESS
2291	* @retval VERR_VMX_INVALID_VMCS_PTR
2292	* @retval VERR_VMX_INVALID_VMCS_FIELD
2293	*
2294	* @param idxField VMCS index
2295	* @param pData Ptr to store VM field value
2296	*
2297	* @remarks The values of the two status codes can be ORed together, the result
2298	* will be VERR_VMX_INVALID_VMCS_PTR.
2299	*/
2300	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2301	DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2302	#else
2303	DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2304	{
2305	# if VMX_USE_MSC_INTRINSICS
2306	unsigned char rcMsc;
2307	# if ARCH_BITS == 32
2308	size_t uLow;
2309	size_t uHigh;
2310	rcMsc = __vmx_vmread(idxField, &uLow);
2311	rcMsc \|= __vmx_vmread(idxField + 1, &uHigh);
2312	*pData = RT_MAKE_U64(uLow, uHigh);
2313	# else
2314	rcMsc = __vmx_vmread(idxField, pData);
2315	# endif
2316	if (RT_LIKELY(rcMsc == 0))
2317	return VINF_SUCCESS;
2318	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2319
2320	# elif ARCH_BITS == 32
2321	int rc;
2322	uint32_t val_hi, val;
2323	rc = VMXReadVmcs32(idxField, &val);
2324	rc \|= VMXReadVmcs32(idxField + 1, &val_hi);
2325	AssertRC(rc);
2326	*pData = RT_MAKE_U64(val, val_hi);
2327	return rc;
2328
2329	# else
2330	# error "Shouldn't be here..."
2331	# endif
2332	}
2333	#endif
2334
2335	/**
2336	* Gets the last instruction error value from the current VMCS
2337	*
2338	* @returns error value
2339	*/
2340	DECLINLINE(uint32_t) VMXGetLastError(void)
2341	{
2342	#if ARCH_BITS == 64
2343	uint64_t uLastError = 0;
2344	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2345	AssertRC(rc);
2346	return (uint32_t)uLastError;
2347
2348	#else /* 32-bit host: */
2349	uint32_t uLastError = 0;
2350	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2351	AssertRC(rc);
2352	return uLastError;
2353	#endif
2354	}
2355
2356	#ifdef IN_RING0
2357	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2358	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2359	#endif /* IN_RING0 */
2360
2361	/** @} */
2362
2363	#endif
2364

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 53425

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