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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 55254

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1/** @file
2 * HM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2014 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vmx_h
27#define ___VBox_vmm_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/x86.h>
32#include <iprt/assert.h>
33
34/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35 when targeting AMD64. */
36#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37# include <intrin.h>
38/* We always want them as intrinsics, no functions. */
39# pragma intrinsic(__vmx_on)
40# pragma intrinsic(__vmx_off)
41# pragma intrinsic(__vmx_vmclear)
42# pragma intrinsic(__vmx_vmptrld)
43# pragma intrinsic(__vmx_vmread)
44# pragma intrinsic(__vmx_vmwrite)
45# define VMX_USE_MSC_INTRINSICS 1
46#else
47# define VMX_USE_MSC_INTRINSICS 0
48#endif
49
50
51/** @defgroup grp_vmx vmx Types and Definitions
52 * @ingroup grp_hm
53 * @{
54 */
55
56/** @def HMVMXCPU_GST_SET_UPDATED
57 * Sets a guest-state-updated flag.
58 *
59 * @param pVCpu Pointer to the VMCPU.
60 * @param fFlag The flag to set.
61 */
62#define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
63
64/** @def HMVMXCPU_GST_IS_SET
65 * Checks if all the flags in the specified guest-state-updated set is pending.
66 *
67 * @param pVCpu Pointer to the VMCPU.
68 * @param fFlag The flag to check.
69 */
70#define HMVMXCPU_GST_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
71
72/** @def HMVMXCPU_GST_IS_UPDATED
73 * Checks if one or more of the flags in the specified guest-state-updated set
74 * is updated.
75 *
76 * @param pVCpu Pointer to the VMCPU.
77 * @param fFlags The flags to check for.
78 */
79#define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
80
81/** @def HMVMXCPU_GST_RESET_TO
82 * Resets the guest-state-updated flags to the specified value.
83 *
84 * @param pVCpu Pointer to the VMCPU.
85 * @param fFlags The new value.
86 */
87#define HMVMXCPU_GST_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlags)))
88
89/** @def HMVMXCPU_GST_VALUE
90 * Returns the current guest-state-updated flags value.
91 *
92 * @param pVCpu Pointer to the VMCPU.
93 */
94#define HMVMXCPU_GST_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState))
95
96/** @name Host-state restoration flags.
97 * @note If you change these values don't forget to update the assembly
98 * defines as well!
99 * @{
100 */
101#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
102#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
103#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
104#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
105#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
106#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
107#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
108#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
109#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
110/** @} */
111
112/**
113 * Host-state restoration structure.
114 * This holds host-state fields that require manual restoration.
115 * Assembly version found in hm_vmx.mac (should be automatically verified).
116 */
117typedef struct VMXRESTOREHOST
118{
119 RTSEL uHostSelDS; /* 0x00 */
120 RTSEL uHostSelES; /* 0x02 */
121 RTSEL uHostSelFS; /* 0x04 */
122 RTSEL uHostSelGS; /* 0x06 */
123 RTSEL uHostSelTR; /* 0x08 */
124 uint8_t abPadding0[4];
125 X86XDTR64 HostGdtr; /**< 0x0e - should be aligned by it's 64-bit member. */
126 uint8_t abPadding1[6];
127 X86XDTR64 HostIdtr; /**< 0x1e - should be aligned by it's 64-bit member. */
128 uint64_t uHostFSBase; /* 0x28 */
129 uint64_t uHostGSBase; /* 0x30 */
130} VMXRESTOREHOST;
131/** Pointer to VMXRESTOREHOST. */
132typedef VMXRESTOREHOST *PVMXRESTOREHOST;
133AssertCompileSize(X86XDTR64, 10);
134AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
135AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
136AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
137AssertCompileSize(VMXRESTOREHOST, 56);
138AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
139
140/** @name Host-state MSR lazy-restoration flags.
141 * @{
142 */
143/** The host MSRs have been saved. */
144#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
145/** The guest MSRs are loaded and in effect. */
146#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
147/** @} */
148
149/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
150 * UFC = Unsupported Feature Combination.
151 * @{
152 */
153/** Unsupported pin-based VM-execution controls combo. */
154#define VMX_UFC_CTRL_PIN_EXEC 0
155/** Unsupported processor-based VM-execution controls combo. */
156#define VMX_UFC_CTRL_PROC_EXEC 1
157/** Unsupported pin-based VM-execution controls combo. */
158#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 2
159/** Unsupported VM-entry controls combo. */
160#define VMX_UFC_CTRL_ENTRY 3
161/** Unsupported VM-exit controls combo. */
162#define VMX_UFC_CTRL_EXIT 4
163/** MSR storage capacity of the VMCS autoload/store area is not sufficient
164 * for storing host MSRs. */
165#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 5
166/** MSR storage capacity of the VMCS autoload/store area is not sufficient
167 * for storing guest MSRs. */
168#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 6
169/** Invalid VMCS size. */
170#define VMX_UFC_INVALID_VMCS_SIZE 7
171/** Unsupported secondary processor-based VM-execution controls combo. */
172#define VMX_UFC_CTRL_PROC_EXEC2 8
173/** Invalid unrestricted-guest execution controls combo. */
174#define VMX_UFC_INVALID_UX_COMBO 9
175/** @} */
176
177/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
178 * IGS = Invalid Guest State.
179 * @{
180 */
181/** An error occurred while checking invalid-guest-state. */
182#define VMX_IGS_ERROR 0
183/** The invalid guest-state checks did not find any reason why. */
184#define VMX_IGS_REASON_NOT_FOUND 1
185/** CR0 fixed1 bits invalid. */
186#define VMX_IGS_CR0_FIXED1 2
187/** CR0 fixed0 bits invalid. */
188#define VMX_IGS_CR0_FIXED0 3
189/** CR0.PE and CR0.PE invalid VT-x/host combination. */
190#define VMX_IGS_CR0_PG_PE_COMBO 4
191/** CR4 fixed1 bits invalid. */
192#define VMX_IGS_CR4_FIXED1 5
193/** CR4 fixed0 bits invalid. */
194#define VMX_IGS_CR4_FIXED0 6
195/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
196 * VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
197#define VMX_IGS_DEBUGCTL_MSR_RESERVED 7
198/** CR0.PG not set for long-mode when not using unrestricted guest. */
199#define VMX_IGS_CR0_PG_LONGMODE 8
200/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
201#define VMX_IGS_CR4_PAE_LONGMODE 9
202/** CR4.PCIDE set for 32-bit guest. */
203#define VMX_IGS_CR4_PCIDE 10
204/** VMCS' DR7 reserved bits not set to 0. */
205#define VMX_IGS_DR7_RESERVED 11
206/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
207#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12
208/** VMCS' EFER MSR reserved bits not set to 0. */
209#define VMX_IGS_EFER_MSR_RESERVED 13
210/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
211#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14
212/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
213 * without unrestricted guest. */
214#define VMX_IGS_EFER_LMA_LME_MISMATCH 15
215/** CS.Attr.P bit invalid. */
216#define VMX_IGS_CS_ATTR_P_INVALID 16
217/** CS.Attr reserved bits not set to 0. */
218#define VMX_IGS_CS_ATTR_RESERVED 17
219/** CS.Attr.G bit invalid. */
220#define VMX_IGS_CS_ATTR_G_INVALID 18
221/** CS is unusable. */
222#define VMX_IGS_CS_ATTR_UNUSABLE 19
223/** CS and SS DPL unequal. */
224#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20
225/** CS and SS DPL mismatch. */
226#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21
227/** CS Attr.Type invalid. */
228#define VMX_IGS_CS_ATTR_TYPE_INVALID 22
229/** CS and SS RPL unequal. */
230#define VMX_IGS_SS_CS_RPL_UNEQUAL 23
231/** SS.Attr.DPL and SS RPL unequal. */
232#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24
233/** SS.Attr.DPL invalid for segment type. */
234#define VMX_IGS_SS_ATTR_DPL_INVALID 25
235/** SS.Attr.Type invalid. */
236#define VMX_IGS_SS_ATTR_TYPE_INVALID 26
237/** SS.Attr.P bit invalid. */
238#define VMX_IGS_SS_ATTR_P_INVALID 27
239/** SS.Attr reserved bits not set to 0. */
240#define VMX_IGS_SS_ATTR_RESERVED 28
241/** SS.Attr.G bit invalid. */
242#define VMX_IGS_SS_ATTR_G_INVALID 29
243/** DS.Attr.A bit invalid. */
244#define VMX_IGS_DS_ATTR_A_INVALID 30
245/** DS.Attr.P bit invalid. */
246#define VMX_IGS_DS_ATTR_P_INVALID 31
247/** DS.Attr.DPL and DS RPL unequal. */
248#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32
249/** DS.Attr reserved bits not set to 0. */
250#define VMX_IGS_DS_ATTR_RESERVED 33
251/** DS.Attr.G bit invalid. */
252#define VMX_IGS_DS_ATTR_G_INVALID 34
253/** DS.Attr.Type invalid. */
254#define VMX_IGS_DS_ATTR_TYPE_INVALID 35
255/** ES.Attr.A bit invalid. */
256#define VMX_IGS_ES_ATTR_A_INVALID 36
257/** ES.Attr.P bit invalid. */
258#define VMX_IGS_ES_ATTR_P_INVALID 37
259/** ES.Attr.DPL and DS RPL unequal. */
260#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38
261/** ES.Attr reserved bits not set to 0. */
262#define VMX_IGS_ES_ATTR_RESERVED 39
263/** ES.Attr.G bit invalid. */
264#define VMX_IGS_ES_ATTR_G_INVALID 40
265/** ES.Attr.Type invalid. */
266#define VMX_IGS_ES_ATTR_TYPE_INVALID 41
267/** FS.Attr.A bit invalid. */
268#define VMX_IGS_FS_ATTR_A_INVALID 42
269/** FS.Attr.P bit invalid. */
270#define VMX_IGS_FS_ATTR_P_INVALID 43
271/** FS.Attr.DPL and DS RPL unequal. */
272#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44
273/** FS.Attr reserved bits not set to 0. */
274#define VMX_IGS_FS_ATTR_RESERVED 45
275/** FS.Attr.G bit invalid. */
276#define VMX_IGS_FS_ATTR_G_INVALID 46
277/** FS.Attr.Type invalid. */
278#define VMX_IGS_FS_ATTR_TYPE_INVALID 47
279/** GS.Attr.A bit invalid. */
280#define VMX_IGS_GS_ATTR_A_INVALID 48
281/** GS.Attr.P bit invalid. */
282#define VMX_IGS_GS_ATTR_P_INVALID 49
283/** GS.Attr.DPL and DS RPL unequal. */
284#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 50
285/** GS.Attr reserved bits not set to 0. */
286#define VMX_IGS_GS_ATTR_RESERVED 51
287/** GS.Attr.G bit invalid. */
288#define VMX_IGS_GS_ATTR_G_INVALID 52
289/** GS.Attr.Type invalid. */
290#define VMX_IGS_GS_ATTR_TYPE_INVALID 53
291/** V86 mode CS.Base invalid. */
292#define VMX_IGS_V86_CS_BASE_INVALID 54
293/** V86 mode CS.Limit invalid. */
294#define VMX_IGS_V86_CS_LIMIT_INVALID 55
295/** V86 mode CS.Attr invalid. */
296#define VMX_IGS_V86_CS_ATTR_INVALID 56
297/** V86 mode SS.Base invalid. */
298#define VMX_IGS_V86_SS_BASE_INVALID 57
299/** V86 mode SS.Limit invalid. */
300#define VMX_IGS_V86_SS_LIMIT_INVALID 58
301/** V86 mode SS.Attr invalid. */
302#define VMX_IGS_V86_SS_ATTR_INVALID 59
303/** V86 mode DS.Base invalid. */
304#define VMX_IGS_V86_DS_BASE_INVALID 60
305/** V86 mode DS.Limit invalid. */
306#define VMX_IGS_V86_DS_LIMIT_INVALID 61
307/** V86 mode DS.Attr invalid. */
308#define VMX_IGS_V86_DS_ATTR_INVALID 62
309/** V86 mode ES.Base invalid. */
310#define VMX_IGS_V86_ES_BASE_INVALID 63
311/** V86 mode ES.Limit invalid. */
312#define VMX_IGS_V86_ES_LIMIT_INVALID 64
313/** V86 mode ES.Attr invalid. */
314#define VMX_IGS_V86_ES_ATTR_INVALID 65
315/** V86 mode FS.Base invalid. */
316#define VMX_IGS_V86_FS_BASE_INVALID 66
317/** V86 mode FS.Limit invalid. */
318#define VMX_IGS_V86_FS_LIMIT_INVALID 67
319/** V86 mode FS.Attr invalid. */
320#define VMX_IGS_V86_FS_ATTR_INVALID 68
321/** V86 mode GS.Base invalid. */
322#define VMX_IGS_V86_GS_BASE_INVALID 69
323/** V86 mode GS.Limit invalid. */
324#define VMX_IGS_V86_GS_LIMIT_INVALID 70
325/** V86 mode GS.Attr invalid. */
326#define VMX_IGS_V86_GS_ATTR_INVALID 71
327/** Longmode CS.Base invalid. */
328#define VMX_IGS_LONGMODE_CS_BASE_INVALID 72
329/** Longmode SS.Base invalid. */
330#define VMX_IGS_LONGMODE_SS_BASE_INVALID 73
331/** Longmode DS.Base invalid. */
332#define VMX_IGS_LONGMODE_DS_BASE_INVALID 74
333/** Longmode ES.Base invalid. */
334#define VMX_IGS_LONGMODE_ES_BASE_INVALID 75
335/** SYSENTER ESP is not canonical. */
336#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76
337/** SYSENTER EIP is not canonical. */
338#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77
339/** PAT MSR invalid. */
340#define VMX_IGS_PAT_MSR_INVALID 78
341/** PAT MSR reserved bits not set to 0. */
342#define VMX_IGS_PAT_MSR_RESERVED 79
343/** GDTR.Base is not canonical. */
344#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80
345/** IDTR.Base is not canonical. */
346#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81
347/** GDTR.Limit invalid. */
348#define VMX_IGS_GDTR_LIMIT_INVALID 82
349/** IDTR.Limit invalid. */
350#define VMX_IGS_IDTR_LIMIT_INVALID 83
351/** Longmode RIP is invalid. */
352#define VMX_IGS_LONGMODE_RIP_INVALID 84
353/** RFLAGS reserved bits not set to 0. */
354#define VMX_IGS_RFLAGS_RESERVED 85
355/** RFLAGS RA1 reserved bits not set to 1. */
356#define VMX_IGS_RFLAGS_RESERVED1 86
357/** RFLAGS.VM (V86 mode) invalid. */
358#define VMX_IGS_RFLAGS_VM_INVALID 87
359/** RFLAGS.IF invalid. */
360#define VMX_IGS_RFLAGS_IF_INVALID 88
361/** Activity state invalid. */
362#define VMX_IGS_ACTIVITY_STATE_INVALID 89
363/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
364#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90
365/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
366#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91
367/** Activity state SIPI WAIT invalid. */
368#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92
369/** Interruptibility state reserved bits not set to 0. */
370#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93
371/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
372#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94
373/** Interruptibility state block-by-STI invalid for EFLAGS. */
374#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95
375/** Interruptibility state invalid while trying to deliver external
376 * interrupt. */
377#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96
378/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
379 * NMI. */
380#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97
381/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
382#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98
383/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
384#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99
385/** Interruptibilty state block-by-STI (maybe) invalid when trying to deliver
386 * an NMI. */
387#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100
388/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
389 * active. */
390#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101
391/** Pending debug exceptions reserved bits not set to 0. */
392#define VMX_IGS_PENDING_DEBUG_RESERVED 102
393/** Longmode pending debug exceptions reserved bits not set to 0. */
394#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103
395/** Pending debug exceptions.BS bit is not set when it should be. */
396#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104
397/** Pending debug exceptions.BS bit is not clear when it should be. */
398#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105
399/** VMCS link pointer reserved bits not set to 0. */
400#define VMX_IGS_VMCS_LINK_PTR_RESERVED 106
401/** TR cannot index into LDT, TI bit MBZ. */
402#define VMX_IGS_TR_TI_INVALID 107
403/** LDTR cannot index into LDT. TI bit MBZ. */
404#define VMX_IGS_LDTR_TI_INVALID 108
405/** TR.Base is not canonical. */
406#define VMX_IGS_TR_BASE_NOT_CANONICAL 109
407/** FS.Base is not canonical. */
408#define VMX_IGS_FS_BASE_NOT_CANONICAL 110
409/** GS.Base is not canonical. */
410#define VMX_IGS_GS_BASE_NOT_CANONICAL 111
411/** LDTR.Base is not canonical. */
412#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 112
413/** TR is unusable. */
414#define VMX_IGS_TR_ATTR_UNUSABLE 113
415/** TR.Attr.S bit invalid. */
416#define VMX_IGS_TR_ATTR_S_INVALID 114
417/** TR is not present. */
418#define VMX_IGS_TR_ATTR_P_INVALID 115
419/** TR.Attr reserved bits not set to 0. */
420#define VMX_IGS_TR_ATTR_RESERVED 116
421/** TR.Attr.G bit invalid. */
422#define VMX_IGS_TR_ATTR_G_INVALID 117
423/** Longmode TR.Attr.Type invalid. */
424#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 118
425/** TR.Attr.Type invalid. */
426#define VMX_IGS_TR_ATTR_TYPE_INVALID 119
427/** CS.Attr.S invalid. */
428#define VMX_IGS_CS_ATTR_S_INVALID 120
429/** CS.Attr.DPL invalid. */
430#define VMX_IGS_CS_ATTR_DPL_INVALID 121
431/** PAE PDPTE reserved bits not set to 0. */
432#define VMX_IGS_PAE_PDPTE_RESERVED 123
433/** @} */
434
435/** @name VMX VMCS-Read cache indices.
436 * @{
437 */
438#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
439#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
440#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
441#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
442#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
443#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
444#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
445#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
446#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
447#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
448#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
449#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
450#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
451#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
452#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
453#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
454#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
455#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
456/** @} */
457
458/** @name VMX EPT paging structures
459 * @{
460 */
461
462/**
463 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
464 */
465#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
466
467/**
468 * EPT Page Directory Pointer Entry. Bit view.
469 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
470 * this did cause trouble with one compiler/version).
471 */
472typedef struct EPTPML4EBITS
473{
474 /** Present bit. */
475 uint64_t u1Present : 1;
476 /** Writable bit. */
477 uint64_t u1Write : 1;
478 /** Executable bit. */
479 uint64_t u1Execute : 1;
480 /** Reserved (must be 0). */
481 uint64_t u5Reserved : 5;
482 /** Available for software. */
483 uint64_t u4Available : 4;
484 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
485 uint64_t u40PhysAddr : 40;
486 /** Availabe for software. */
487 uint64_t u12Available : 12;
488} EPTPML4EBITS;
489AssertCompileSize(EPTPML4EBITS, 8);
490
491/** Bits 12-51 - - EPT - Physical Page number of the next level. */
492#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
493/** The page shift to get the PML4 index. */
494#define EPT_PML4_SHIFT X86_PML4_SHIFT
495/** The PML4 index mask (apply to a shifted page address). */
496#define EPT_PML4_MASK X86_PML4_MASK
497
498/**
499 * EPT PML4E.
500 */
501typedef union EPTPML4E
502{
503 /** Normal view. */
504 EPTPML4EBITS n;
505 /** Unsigned integer view. */
506 X86PGPAEUINT u;
507 /** 64 bit unsigned integer view. */
508 uint64_t au64[1];
509 /** 32 bit unsigned integer view. */
510 uint32_t au32[2];
511} EPTPML4E;
512AssertCompileSize(EPTPML4E, 8);
513/** Pointer to a PML4 table entry. */
514typedef EPTPML4E *PEPTPML4E;
515/** Pointer to a const PML4 table entry. */
516typedef const EPTPML4E *PCEPTPML4E;
517
518/**
519 * EPT PML4 Table.
520 */
521typedef struct EPTPML4
522{
523 EPTPML4E a[EPT_PG_ENTRIES];
524} EPTPML4;
525AssertCompileSize(EPTPML4, 0x1000);
526/** Pointer to an EPT PML4 Table. */
527typedef EPTPML4 *PEPTPML4;
528/** Pointer to a const EPT PML4 Table. */
529typedef const EPTPML4 *PCEPTPML4;
530
531/**
532 * EPT Page Directory Pointer Entry. Bit view.
533 */
534typedef struct EPTPDPTEBITS
535{
536 /** Present bit. */
537 uint64_t u1Present : 1;
538 /** Writable bit. */
539 uint64_t u1Write : 1;
540 /** Executable bit. */
541 uint64_t u1Execute : 1;
542 /** Reserved (must be 0). */
543 uint64_t u5Reserved : 5;
544 /** Available for software. */
545 uint64_t u4Available : 4;
546 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
547 uint64_t u40PhysAddr : 40;
548 /** Availabe for software. */
549 uint64_t u12Available : 12;
550} EPTPDPTEBITS;
551AssertCompileSize(EPTPDPTEBITS, 8);
552
553/** Bits 12-51 - - EPT - Physical Page number of the next level. */
554#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
555/** The page shift to get the PDPT index. */
556#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
557/** The PDPT index mask (apply to a shifted page address). */
558#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
559
560/**
561 * EPT Page Directory Pointer.
562 */
563typedef union EPTPDPTE
564{
565 /** Normal view. */
566 EPTPDPTEBITS n;
567 /** Unsigned integer view. */
568 X86PGPAEUINT u;
569 /** 64 bit unsigned integer view. */
570 uint64_t au64[1];
571 /** 32 bit unsigned integer view. */
572 uint32_t au32[2];
573} EPTPDPTE;
574AssertCompileSize(EPTPDPTE, 8);
575/** Pointer to an EPT Page Directory Pointer Entry. */
576typedef EPTPDPTE *PEPTPDPTE;
577/** Pointer to a const EPT Page Directory Pointer Entry. */
578typedef const EPTPDPTE *PCEPTPDPTE;
579
580/**
581 * EPT Page Directory Pointer Table.
582 */
583typedef struct EPTPDPT
584{
585 EPTPDPTE a[EPT_PG_ENTRIES];
586} EPTPDPT;
587AssertCompileSize(EPTPDPT, 0x1000);
588/** Pointer to an EPT Page Directory Pointer Table. */
589typedef EPTPDPT *PEPTPDPT;
590/** Pointer to a const EPT Page Directory Pointer Table. */
591typedef const EPTPDPT *PCEPTPDPT;
592
593
594/**
595 * EPT Page Directory Table Entry. Bit view.
596 */
597typedef struct EPTPDEBITS
598{
599 /** Present bit. */
600 uint64_t u1Present : 1;
601 /** Writable bit. */
602 uint64_t u1Write : 1;
603 /** Executable bit. */
604 uint64_t u1Execute : 1;
605 /** Reserved (must be 0). */
606 uint64_t u4Reserved : 4;
607 /** Big page (must be 0 here). */
608 uint64_t u1Size : 1;
609 /** Available for software. */
610 uint64_t u4Available : 4;
611 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
612 uint64_t u40PhysAddr : 40;
613 /** Availabe for software. */
614 uint64_t u12Available : 12;
615} EPTPDEBITS;
616AssertCompileSize(EPTPDEBITS, 8);
617
618/** Bits 12-51 - - EPT - Physical Page number of the next level. */
619#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
620/** The page shift to get the PD index. */
621#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
622/** The PD index mask (apply to a shifted page address). */
623#define EPT_PD_MASK X86_PD_PAE_MASK
624
625/**
626 * EPT 2MB Page Directory Table Entry. Bit view.
627 */
628typedef struct EPTPDE2MBITS
629{
630 /** Present bit. */
631 uint64_t u1Present : 1;
632 /** Writable bit. */
633 uint64_t u1Write : 1;
634 /** Executable bit. */
635 uint64_t u1Execute : 1;
636 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
637 uint64_t u3EMT : 3;
638 /** Ignore PAT memory type */
639 uint64_t u1IgnorePAT : 1;
640 /** Big page (must be 1 here). */
641 uint64_t u1Size : 1;
642 /** Available for software. */
643 uint64_t u4Available : 4;
644 /** Reserved (must be 0). */
645 uint64_t u9Reserved : 9;
646 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
647 uint64_t u31PhysAddr : 31;
648 /** Availabe for software. */
649 uint64_t u12Available : 12;
650} EPTPDE2MBITS;
651AssertCompileSize(EPTPDE2MBITS, 8);
652
653/** Bits 21-51 - - EPT - Physical Page number of the next level. */
654#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
655
656/**
657 * EPT Page Directory Table Entry.
658 */
659typedef union EPTPDE
660{
661 /** Normal view. */
662 EPTPDEBITS n;
663 /** 2MB view (big). */
664 EPTPDE2MBITS b;
665 /** Unsigned integer view. */
666 X86PGPAEUINT u;
667 /** 64 bit unsigned integer view. */
668 uint64_t au64[1];
669 /** 32 bit unsigned integer view. */
670 uint32_t au32[2];
671} EPTPDE;
672AssertCompileSize(EPTPDE, 8);
673/** Pointer to an EPT Page Directory Table Entry. */
674typedef EPTPDE *PEPTPDE;
675/** Pointer to a const EPT Page Directory Table Entry. */
676typedef const EPTPDE *PCEPTPDE;
677
678/**
679 * EPT Page Directory Table.
680 */
681typedef struct EPTPD
682{
683 EPTPDE a[EPT_PG_ENTRIES];
684} EPTPD;
685AssertCompileSize(EPTPD, 0x1000);
686/** Pointer to an EPT Page Directory Table. */
687typedef EPTPD *PEPTPD;
688/** Pointer to a const EPT Page Directory Table. */
689typedef const EPTPD *PCEPTPD;
690
691
692/**
693 * EPT Page Table Entry. Bit view.
694 */
695typedef struct EPTPTEBITS
696{
697 /** 0 - Present bit.
698 * @remark This is a convenience "misnomer". The bit actually indicates
699 * read access and the CPU will consider an entry with any of the
700 * first three bits set as present. Since all our valid entries
701 * will have this bit set, it can be used as a present indicator
702 * and allow some code sharing. */
703 uint64_t u1Present : 1;
704 /** 1 - Writable bit. */
705 uint64_t u1Write : 1;
706 /** 2 - Executable bit. */
707 uint64_t u1Execute : 1;
708 /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
709 uint64_t u3EMT : 3;
710 /** 6 - Ignore PAT memory type */
711 uint64_t u1IgnorePAT : 1;
712 /** 11:7 - Available for software. */
713 uint64_t u5Available : 5;
714 /** 51:12 - Physical address of page. Restricted by maximum physical
715 * address width of the cpu. */
716 uint64_t u40PhysAddr : 40;
717 /** 63:52 - Available for software. */
718 uint64_t u12Available : 12;
719} EPTPTEBITS;
720AssertCompileSize(EPTPTEBITS, 8);
721
722/** Bits 12-51 - - EPT - Physical Page number of the next level. */
723#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
724/** The page shift to get the EPT PTE index. */
725#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
726/** The EPT PT index mask (apply to a shifted page address). */
727#define EPT_PT_MASK X86_PT_PAE_MASK
728
729/**
730 * EPT Page Table Entry.
731 */
732typedef union EPTPTE
733{
734 /** Normal view. */
735 EPTPTEBITS n;
736 /** Unsigned integer view. */
737 X86PGPAEUINT u;
738 /** 64 bit unsigned integer view. */
739 uint64_t au64[1];
740 /** 32 bit unsigned integer view. */
741 uint32_t au32[2];
742} EPTPTE;
743AssertCompileSize(EPTPTE, 8);
744/** Pointer to an EPT Page Directory Table Entry. */
745typedef EPTPTE *PEPTPTE;
746/** Pointer to a const EPT Page Directory Table Entry. */
747typedef const EPTPTE *PCEPTPTE;
748
749/**
750 * EPT Page Table.
751 */
752typedef struct EPTPT
753{
754 EPTPTE a[EPT_PG_ENTRIES];
755} EPTPT;
756AssertCompileSize(EPTPT, 0x1000);
757/** Pointer to an extended page table. */
758typedef EPTPT *PEPTPT;
759/** Pointer to a const extended table. */
760typedef const EPTPT *PCEPTPT;
761
762/** @} */
763
764/** VMX VPID flush types.
765 * Warning!! Valid enum members are in accordance to the VT-x spec.
766 */
767typedef enum
768{
769 /** Invalidate a specific page. */
770 VMXFLUSHVPID_INDIV_ADDR = 0,
771 /** Invalidate one context (specific VPID). */
772 VMXFLUSHVPID_SINGLE_CONTEXT = 1,
773 /** Invalidate all contexts (all VPIDs). */
774 VMXFLUSHVPID_ALL_CONTEXTS = 2,
775 /** Invalidate a single VPID context retaining global mappings. */
776 VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
777 /** Unsupported by VirtualBox. */
778 VMXFLUSHVPID_NOT_SUPPORTED = 0xbad0,
779 /** Unsupported by CPU. */
780 VMXFLUSHVPID_NONE = 0xbad1
781} VMXFLUSHVPID;
782AssertCompileSize(VMXFLUSHVPID, 4);
783
784/** VMX EPT flush types.
785 * @note Warning!! Valid enums values below are in accordance to the VT-x spec.
786 */
787typedef enum
788{
789 /** Invalidate one context (specific EPT). */
790 VMXFLUSHEPT_SINGLE_CONTEXT = 1,
791 /* Invalidate all contexts (all EPTs) */
792 VMXFLUSHEPT_ALL_CONTEXTS = 2,
793 /** Unsupported by VirtualBox. */
794 VMXFLUSHEPT_NOT_SUPPORTED = 0xbad0,
795 /** Unsupported by CPU. */
796 VMXFLUSHEPT_NONE = 0xbad1
797} VMXFLUSHEPT;
798AssertCompileSize(VMXFLUSHEPT, 4);
799
800/** VMX MSR autoload/store element.
801 * In accordance to VT-x spec.
802 */
803typedef struct
804{
805 /** The MSR Id. */
806 uint32_t u32Msr;
807 /** Reserved (MBZ). */
808 uint32_t u32Reserved;
809 /** The MSR value. */
810 uint64_t u64Value;
811} VMXAUTOMSR;
812AssertCompileSize(VMXAUTOMSR, 16);
813/** Pointer to an MSR load/store element. */
814typedef VMXAUTOMSR *PVMXAUTOMSR;
815/** Pointer to a const MSR load/store element. */
816typedef const VMXAUTOMSR *PCVMXAUTOMSR;
817
818/**
819 * VMX-capability qword
820 */
821typedef union
822{
823 struct
824 {
825 /** Bits set here -must- be set in the correpsonding VM-execution controls. */
826 uint32_t disallowed0;
827 /** Bits cleared here -must- be cleared in the corresponding VM-execution
828 * controls. */
829 uint32_t allowed1;
830 } n;
831 uint64_t u;
832} VMXCAPABILITY;
833AssertCompileSize(VMXCAPABILITY, 8);
834
835/**
836 * VMX MSRs.
837 */
838typedef struct VMXMSRS
839{
840 uint64_t u64FeatureCtrl;
841 uint64_t u64BasicInfo;
842 VMXCAPABILITY VmxPinCtls;
843 VMXCAPABILITY VmxProcCtls;
844 VMXCAPABILITY VmxProcCtls2;
845 VMXCAPABILITY VmxExit;
846 VMXCAPABILITY VmxEntry;
847 uint64_t u64Misc;
848 uint64_t u64Cr0Fixed0;
849 uint64_t u64Cr0Fixed1;
850 uint64_t u64Cr4Fixed0;
851 uint64_t u64Cr4Fixed1;
852 uint64_t u64VmcsEnum;
853 uint64_t u64Vmfunc;
854 uint64_t u64EptVpidCaps;
855} VMXMSRS;
856AssertCompileSizeAlignment(VMXMSRS, 8);
857/** Pointer to a VMXMSRS struct. */
858typedef VMXMSRS *PVMXMSRS;
859
860/** @name VMX EFLAGS reserved bits.
861 * @{
862 */
863/** And-mask for setting reserved bits to zero */
864#define VMX_EFLAGS_RESERVED_0 (X86_EFL_1 | X86_EFL_LIVE_MASK)
865/** Or-mask for setting reserved bits to 1 */
866#define VMX_EFLAGS_RESERVED_1 X86_EFL_1
867/** @} */
868
869/** @name VMX Basic Exit Reasons.
870 * @{
871 */
872/** -1 Invalid exit code */
873#define VMX_EXIT_INVALID -1
874/** 0 Exception or non-maskable interrupt (NMI). */
875#define VMX_EXIT_XCPT_OR_NMI 0
876/** 1 External interrupt. */
877#define VMX_EXIT_EXT_INT 1
878/** 2 Triple fault. */
879#define VMX_EXIT_TRIPLE_FAULT 2
880/** 3 INIT signal. */
881#define VMX_EXIT_INIT_SIGNAL 3
882/** 4 Start-up IPI (SIPI). */
883#define VMX_EXIT_SIPI 4
884/** 5 I/O system-management interrupt (SMI). */
885#define VMX_EXIT_IO_SMI 5
886/** 6 Other SMI. */
887#define VMX_EXIT_SMI 6
888/** 7 Interrupt window exiting. */
889#define VMX_EXIT_INT_WINDOW 7
890/** 8 NMI window exiting. */
891#define VMX_EXIT_NMI_WINDOW 8
892/** 9 Task switch. */
893#define VMX_EXIT_TASK_SWITCH 9
894/** 10 Guest software attempted to execute CPUID. */
895#define VMX_EXIT_CPUID 10
896/** 11 Guest software attempted to execute GETSEC. */
897#define VMX_EXIT_GETSEC 11
898/** 12 Guest software attempted to execute HLT. */
899#define VMX_EXIT_HLT 12
900/** 13 Guest software attempted to execute INVD. */
901#define VMX_EXIT_INVD 13
902/** 14 Guest software attempted to execute INVLPG. */
903#define VMX_EXIT_INVLPG 14
904/** 15 Guest software attempted to execute RDPMC. */
905#define VMX_EXIT_RDPMC 15
906/** 16 Guest software attempted to execute RDTSC. */
907#define VMX_EXIT_RDTSC 16
908/** 17 Guest software attempted to execute RSM in SMM. */
909#define VMX_EXIT_RSM 17
910/** 18 Guest software executed VMCALL. */
911#define VMX_EXIT_VMCALL 18
912/** 19 Guest software executed VMCLEAR. */
913#define VMX_EXIT_VMCLEAR 19
914/** 20 Guest software executed VMLAUNCH. */
915#define VMX_EXIT_VMLAUNCH 20
916/** 21 Guest software executed VMPTRLD. */
917#define VMX_EXIT_VMPTRLD 21
918/** 22 Guest software executed VMPTRST. */
919#define VMX_EXIT_VMPTRST 22
920/** 23 Guest software executed VMREAD. */
921#define VMX_EXIT_VMREAD 23
922/** 24 Guest software executed VMRESUME. */
923#define VMX_EXIT_VMRESUME 24
924/** 25 Guest software executed VMWRITE. */
925#define VMX_EXIT_VMWRITE 25
926/** 26 Guest software executed VMXOFF. */
927#define VMX_EXIT_VMXOFF 26
928/** 27 Guest software executed VMXON. */
929#define VMX_EXIT_VMXON 27
930/** 28 Control-register accesses. */
931#define VMX_EXIT_MOV_CRX 28
932/** 29 Debug-register accesses. */
933#define VMX_EXIT_MOV_DRX 29
934/** 30 I/O instruction. */
935#define VMX_EXIT_IO_INSTR 30
936/** 31 RDMSR. Guest software attempted to execute RDMSR. */
937#define VMX_EXIT_RDMSR 31
938/** 32 WRMSR. Guest software attempted to execute WRMSR. */
939#define VMX_EXIT_WRMSR 32
940/** 33 VM-entry failure due to invalid guest state. */
941#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
942/** 34 VM-entry failure due to MSR loading. */
943#define VMX_EXIT_ERR_MSR_LOAD 34
944/** 36 Guest software executed MWAIT. */
945#define VMX_EXIT_MWAIT 36
946/** 37 VM-exit due to monitor trap flag. */
947#define VMX_EXIT_MTF 37
948/** 39 Guest software attempted to execute MONITOR. */
949#define VMX_EXIT_MONITOR 39
950/** 40 Guest software attempted to execute PAUSE. */
951#define VMX_EXIT_PAUSE 40
952/** 41 VM-entry failure due to machine-check. */
953#define VMX_EXIT_ERR_MACHINE_CHECK 41
954/** 43 TPR below threshold. Guest software executed MOV to CR8. */
955#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
956/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
957#define VMX_EXIT_APIC_ACCESS 44
958/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
959#define VMX_EXIT_XDTR_ACCESS 46
960/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
961#define VMX_EXIT_TR_ACCESS 47
962/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
963#define VMX_EXIT_EPT_VIOLATION 48
964/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
965#define VMX_EXIT_EPT_MISCONFIG 49
966/** 50 INVEPT. Guest software attempted to execute INVEPT. */
967#define VMX_EXIT_INVEPT 50
968/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
969#define VMX_EXIT_RDTSCP 51
970/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
971#define VMX_EXIT_PREEMPT_TIMER 52
972/** 53 INVVPID. Guest software attempted to execute INVVPID. */
973#define VMX_EXIT_INVVPID 53
974/** 54 WBINVD. Guest software attempted to execute WBINVD. */
975#define VMX_EXIT_WBINVD 54
976/** 55 XSETBV. Guest software attempted to execute XSETBV. */
977#define VMX_EXIT_XSETBV 55
978/** 57 RDRAND. Guest software attempted to execute RDRAND. */
979#define VMX_EXIT_RDRAND 57
980/** 58 INVPCID. Guest software attempted to execute INVPCID. */
981#define VMX_EXIT_INVPCID 58
982/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
983#define VMX_EXIT_VMFUNC 59
984#if 1
985/** The maximum exit value (inclusive). */
986#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
987#else
988/** 60 ??? */
989#define VMX_EXIT_RESERVED_60 60
990/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
991 * enabled. */
992#define VMX_EXIT_RDSEED 61
993/** 62 ??? */
994#define VMX_EXIT_RESERVED_62 62
995/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
996 * enabled (XSAVES/XRSTORS was enabled too, of course). */
997#define VMX_EXIT_XSAVES 63
998/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
999 * was enabled (XSAVES/XRSTORS was enabled too, of course). */
1000#define VMX_EXIT_XRSTORS 64
1001/** The maximum exit value (inclusive). */
1002#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
1003#endif
1004/** @} */
1005
1006
1007/** @name VM Instruction Errors
1008 * @{
1009 */
1010/** VMCALL executed in VMX root operation. */
1011#define VMX_ERROR_VMCALL 1
1012/** VMCLEAR with invalid physical address. */
1013#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1014/** VMCLEAR with VMXON pointer. */
1015#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1016/** VMLAUNCH with non-clear VMCS. */
1017#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1018/** VMRESUME with non-launched VMCS. */
1019#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1020/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1021#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1022/** VM-entry with invalid control field(s). */
1023#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1024/** VM-entry with invalid host-state field(s). */
1025#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1026/** VMPTRLD with invalid physical address. */
1027#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1028/** VMPTRLD with VMXON pointer. */
1029#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1030/** VMPTRLD with incorrect VMCS revision identifier. */
1031#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1032/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1033#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1034#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1035/** VMWRITE to read-only VMCS component. */
1036#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1037/** VMXON executed in VMX root operation. */
1038#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1039/** VM-entry with invalid executive-VMCS pointer. */
1040#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1041/** VM-entry with non-launched executive VMCS. */
1042#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1043/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1044#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1045/** VMCALL with non-clear VMCS. */
1046#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1047/** VMCALL with invalid VM-exit control fields. */
1048#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1049/** VMCALL with incorrect MSEG revision identifier. */
1050#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1051/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1052#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1053/** VMCALL with invalid SMM-monitor features. */
1054#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1055/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1056#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1057/** VM-entry with events blocked by MOV SS. */
1058#define VMX_ERROR_VMENTRY_MOV_SS 26
1059/** Invalid operand to INVEPT/INVVPID. */
1060#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1061/** @} */
1062
1063
1064/** @name VMX MSRs - Basic VMX information.
1065 * @{
1066 */
1067/** VMCS revision identifier used by the processor. */
1068#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) ((a) & 0x7FFFFFFF)
1069/** Size of the VMCS. */
1070#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0x1FFF)
1071/** Width of physical address used for the VMCS.
1072 * 0 -> limited to the available amount of physical ram
1073 * 1 -> within the first 4 GB
1074 */
1075#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1076/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1077#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1078/** Memory type that must be used for the VMCS. */
1079#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1080/** Whether the processor provides additional information for exits due to INS/OUTS. */
1081#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1082/** @} */
1083
1084
1085/** @name VMX MSRs - Misc VMX info.
1086 * @{
1087 */
1088/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1089#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1090/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1091#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1092/** Activity states supported by the implementation. */
1093#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1094/** Number of CR3 target values supported by the processor. (0-256) */
1095#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1096/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
1097#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1098/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1099#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1100/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1101#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1102/** Whether VMWRITE can be used to write VM-exit information fields. */
1103#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1104/** MSEG revision identifier used by the processor. */
1105#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1106/** @} */
1107
1108
1109/** @name VMX MSRs - VMCS enumeration field info
1110 * @{
1111 */
1112/** Highest field index. */
1113#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1114/** @} */
1115
1116
1117/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1118 * @{
1119 */
1120#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1121#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
1122#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
1123#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
1124#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
1125#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
1126#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
1127#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
1128#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1129#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
1130#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
1131#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
1132#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1133#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
1134#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
1135#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
1136#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
1137#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1138#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1139#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1140#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1141#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1142#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1143#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1144#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1145/** @} */
1146
1147/** @name Extended Page Table Pointer (EPTP)
1148 * @{
1149 */
1150/** Uncachable EPT paging structure memory type. */
1151#define VMX_EPT_MEMTYPE_UC 0
1152/** Write-back EPT paging structure memory type. */
1153#define VMX_EPT_MEMTYPE_WB 6
1154/** Shift value to get the EPT page walk length (bits 5-3) */
1155#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1156/** Mask value to get the EPT page walk length (bits 5-3) */
1157#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1158/** Default EPT page-walk length (1 less than the actual EPT page-walk
1159 * length) */
1160#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1161/** @} */
1162
1163
1164/** @name VMCS field encoding - 16 bits guest fields
1165 * @{
1166 */
1167#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
1168#define VMX_VMCS16_GUEST_FIELD_ES 0x800
1169#define VMX_VMCS16_GUEST_FIELD_CS 0x802
1170#define VMX_VMCS16_GUEST_FIELD_SS 0x804
1171#define VMX_VMCS16_GUEST_FIELD_DS 0x806
1172#define VMX_VMCS16_GUEST_FIELD_FS 0x808
1173#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
1174#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
1175#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
1176/** @} */
1177
1178/** @name VMCS field encoding - 16 bits host fields
1179 * @{
1180 */
1181#define VMX_VMCS16_HOST_FIELD_ES 0xC00
1182#define VMX_VMCS16_HOST_FIELD_CS 0xC02
1183#define VMX_VMCS16_HOST_FIELD_SS 0xC04
1184#define VMX_VMCS16_HOST_FIELD_DS 0xC06
1185#define VMX_VMCS16_HOST_FIELD_FS 0xC08
1186#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
1187#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
1188/** @} */
1189
1190/** @name VMCS field encoding - 64 bits host fields
1191 * @{
1192 */
1193#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
1194#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
1195#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
1196#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
1197#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
1198#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
1199/** @} */
1200
1201
1202/** @name VMCS field encoding - 64 Bits control fields
1203 * @{
1204 */
1205#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1206#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1207#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1208#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1209
1210/* Optional */
1211#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1212#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1213
1214#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1215#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1216#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1217#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1218
1219#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1220#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1221
1222#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1223#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1224
1225#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1226#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1227
1228/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1229#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1230#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1231
1232/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1233#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1234#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1235
1236/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1237#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1238#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1239
1240/** Extended page table pointer. */
1241#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1242#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1243
1244/** Extended page table pointer lists. */
1245#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1246#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1247
1248/** VM-exit guest phyiscal address. */
1249#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1250#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1251/** @} */
1252
1253
1254/** @name VMCS field encoding - 64 Bits guest fields
1255 * @{
1256 */
1257#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1258#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1259#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
1260#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
1261#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1262#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1263#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1264#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1265#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
1266#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
1267#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1268#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1269#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1270#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1271#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1272#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1273#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1274#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1275/** @} */
1276
1277
1278/** @name VMCS field encoding - 32 Bits control fields
1279 * @{
1280 */
1281#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1282#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1283#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1284#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1285#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1286#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1287#define VMX_VMCS32_CTRL_EXIT 0x400C
1288#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1289#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1290#define VMX_VMCS32_CTRL_ENTRY 0x4012
1291#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1292#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1293#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1294#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1295#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1296#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1297/** @} */
1298
1299
1300/** @name VMX_VMCS_CTRL_PIN_EXEC
1301 * @{
1302 */
1303/** External interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1304#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1305/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1306#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1307/** Virtual NMIs. */
1308#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1309/** Activate VMX preemption timer. */
1310#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1311/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1312/** @} */
1313
1314/** @name VMX_VMCS_CTRL_PROC_EXEC
1315 * @{
1316 */
1317/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1318#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1319/** Use timestamp counter offset. */
1320#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1321/** VM-exit when executing the HLT instruction. */
1322#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1323/** VM-exit when executing the INVLPG instruction. */
1324#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1325/** VM-exit when executing the MWAIT instruction. */
1326#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1327/** VM-exit when executing the RDPMC instruction. */
1328#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1329/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1330#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1331/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1332#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1333/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1334#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1335/** VM-exit on CR8 loads. */
1336#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1337/** VM-exit on CR8 stores. */
1338#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1339/** Use TPR shadow. */
1340#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1341/** VM-exit when virtual NMI blocking is disabled. */
1342#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1343/** VM-exit when executing a MOV DRx instruction. */
1344#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1345/** VM-exit when executing IO instructions. */
1346#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1347/** Use IO bitmaps. */
1348#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1349/** Monitor trap flag. */
1350#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1351/** Use MSR bitmaps. */
1352#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1353/** VM-exit when executing the MONITOR instruction. */
1354#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1355/** VM-exit when executing the PAUSE instruction. */
1356#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1357/** Determines whether the secondary processor based VM-execution controls are used. */
1358#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1359/** @} */
1360
1361/** @name VMX_VMCS_CTRL_PROC_EXEC2
1362 * @{
1363 */
1364/** Virtualize APIC access. */
1365#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1366/** EPT supported/enabled. */
1367#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1368/** Descriptor table instructions cause VM-exits. */
1369#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1370/** RDTSCP supported/enabled. */
1371#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1372/** Virtualize x2APIC mode. */
1373#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1374/** VPID supported/enabled. */
1375#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1376/** VM-exit when executing the WBINVD instruction. */
1377#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1378/** Unrestricted guest execution. */
1379#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1380/** A specified nr of pause loops cause a VM-exit. */
1381#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1382/** VM-exit when executing RDRAND instructions. */
1383#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1384/** Enables INVPCID instructions. */
1385#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1386/** Enables VMFUNC instructions. */
1387#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1388/** Enables VMCS shadowing. */
1389#define VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING RT_BIT_64(14)
1390/** VM-exit when executing RDSEED. */
1391#define VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT RT_BIT_64(16)
1392/** Controls whether EPT-violations may cause \#VE instead of exits. */
1393#define VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE RT_BIT_64(18)
1394/** Enables XSAVES/SRSTORS. */
1395#define VMX_VMCS_CTRL_PROC_EXEC2_XSAVES RT_BIT_64(20)
1396
1397/** @} */
1398
1399
1400/** @name VMX_VMCS_CTRL_ENTRY
1401 * @{
1402 */
1403/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1404#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1405/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1406#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1407/** In SMM mode after VM-entry. */
1408#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1409/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1410#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1411/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
1412#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1413/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
1414#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1415/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
1416#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1417/** @} */
1418
1419
1420/** @name VMX_VMCS_CTRL_EXIT
1421 * @{
1422 */
1423/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1424#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1425/** Return to long mode after a VM-exit. */
1426#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1427/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
1428#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1429/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1430#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1431/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
1432#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1433/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
1434#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1435/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
1436#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1437/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
1438#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1439/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
1440#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1441/** @} */
1442
1443
1444/** @name VMX_VMCS_CTRL_VMFUNC
1445 * @{
1446 */
1447/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1448#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1449/** @} */
1450
1451
1452/** @name VMCS field encoding - 32 Bits read-only fields
1453 * @{
1454 */
1455#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1456#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1457#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1458#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1459#define VMX_VMCS32_RO_IDT_INFO 0x4408
1460#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1461#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1462#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1463/** @} */
1464
1465/** @name VMX_VMCS32_RO_EXIT_REASON
1466 * @{
1467 */
1468#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
1469/** @} */
1470
1471/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1472 * @{
1473 */
1474#define VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1475#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1476#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1477/** @} */
1478
1479
1480/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1481 * @{
1482 */
1483#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) ((a) & 0xff)
1484#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1485#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1486#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1487#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1488#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(a) ((a) & RT_BIT(12))
1489#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1490#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1491/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1492#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
1493/** @} */
1494
1495/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1496 * @{
1497 */
1498#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1499#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1500#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1501#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4
1502#define VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT 5
1503#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1504/** @} */
1505
1506/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1507 * @{
1508 */
1509#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
1510#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1511#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1512#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1513#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1514#define VMX_IDT_VECTORING_INFO_VALID(a) ((a) & RT_BIT(31))
1515#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
1516/** @} */
1517
1518/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1519 * @{
1520 */
1521#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1522#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1523#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1524#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1525#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1526#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1527/** @} */
1528
1529
1530/** @name VMCS field encoding - 32 Bits guest state fields
1531 * @{
1532 */
1533#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1534#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1535#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1536#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1537#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1538#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1539#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1540#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1541#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1542#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1543#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1544#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1545#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1546#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1547#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1548#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1549#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1550#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1551#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1552#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1553#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
1554#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1555/** @} */
1556
1557
1558/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1559 * @{
1560 */
1561/** The logical processor is active. */
1562#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1563/** The logical processor is inactive, because executed a HLT instruction. */
1564#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1565/** The logical processor is inactive, because of a triple fault or other serious error. */
1566#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1567/** The logical processor is inactive, because it's waiting for a startup-IPI */
1568#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1569/** @} */
1570
1571
1572/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1573 * @{
1574 */
1575#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1576#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1577#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1578#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1579/** @} */
1580
1581
1582/** @name VMCS field encoding - 32 Bits host state fields
1583 * @{
1584 */
1585#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1586/** @} */
1587
1588/** @name Natural width control fields
1589 * @{
1590 */
1591#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1592#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1593#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1594#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1595#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1596#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1597#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1598#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1599/** @} */
1600
1601
1602/** @name Natural width read-only data fields
1603 * @{
1604 */
1605#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1606#define VMX_VMCS_RO_IO_RCX 0x6402
1607#define VMX_VMCS_RO_IO_RSX 0x6404
1608#define VMX_VMCS_RO_IO_RDI 0x6406
1609#define VMX_VMCS_RO_IO_RIP 0x6408
1610#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1611/** @} */
1612
1613
1614/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1615 * @{
1616 */
1617/** 0-2: Debug register number */
1618#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) ((a) & 7)
1619/** 3: Reserved; cleared to 0. */
1620#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) (((a) >> 3) & 1)
1621/** 4: Direction of move (0 = write, 1 = read) */
1622#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) (((a) >> 4) & 1)
1623/** 5-7: Reserved; cleared to 0. */
1624#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) (((a) >> 5) & 7)
1625/** 8-11: General purpose register number. */
1626#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) (((a) >> 8) & 0xF)
1627/** Rest: reserved. */
1628/** @} */
1629
1630/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1631 * @{
1632 */
1633#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1634#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1635/** @} */
1636
1637
1638
1639/** @name CRx accesses
1640 * @{
1641 */
1642/** 0-3: Control register number (0 for CLTS & LMSW) */
1643#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) ((a) & 0xF)
1644/** 4-5: Access type. */
1645#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) (((a) >> 4) & 3)
1646/** 6: LMSW operand type */
1647#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) (((a) >> 6) & 1)
1648/** 7: Reserved; cleared to 0. */
1649#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) (((a) >> 7) & 1)
1650/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1651#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) (((a) >> 8) & 0xF)
1652/** 12-15: Reserved; cleared to 0. */
1653#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) (((a) >> 12) & 0xF)
1654/** 16-31: LMSW source data (else 0). */
1655#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) (((a) >> 16) & 0xFFFF)
1656/* Rest: reserved. */
1657/** @} */
1658
1659/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1660 * @{
1661 */
1662#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1663#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1664#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1665#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1666/** @} */
1667
1668/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1669 * @{
1670 */
1671#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
1672#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
1673/** Task switch caused by a call instruction. */
1674#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1675/** Task switch caused by an iret instruction. */
1676#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1677/** Task switch caused by a jmp instruction. */
1678#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1679/** Task switch caused by an interrupt gate. */
1680#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1681/** @} */
1682
1683
1684/** @name VMX_EXIT_EPT_VIOLATION
1685 * @{
1686 */
1687/** Set if the violation was caused by a data read. */
1688#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1689/** Set if the violation was caused by a data write. */
1690#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1691/** Set if the violation was caused by an insruction fetch. */
1692#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1693/** AND of the present bit of all EPT structures. */
1694#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1695/** AND of the write bit of all EPT structures. */
1696#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1697/** AND of the execute bit of all EPT structures. */
1698#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1699/** Set if the guest linear address field contains the faulting address. */
1700#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1701/** If bit 7 is one: (reserved otherwise)
1702 * 1 - violation due to physical address access.
1703 * 0 - violation caused by page walk or access/dirty bit updates
1704 */
1705#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1706/** @} */
1707
1708
1709/** @name VMX_EXIT_PORT_IO
1710 * @{
1711 */
1712/** 0-2: IO operation width. */
1713#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1714/** 3: IO operation direction. */
1715#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1716/** 4: String IO operation (INS / OUTS). */
1717#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1718/** 5: Repeated IO operation. */
1719#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1720/** 6: Operand encoding. */
1721#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1722/** 16-31: IO Port (0-0xffff). */
1723#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1724/* Rest reserved. */
1725/** @} */
1726
1727/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1728 * @{
1729 */
1730#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1731#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1732/** @} */
1733
1734
1735/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1736 * @{
1737 */
1738#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1739#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1740/** @} */
1741
1742/** @name VMX_EXIT_APIC_ACCESS
1743 * @{
1744 */
1745/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of access within the APIC page. */
1746#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1747/** 12-15: Access type. */
1748#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
1749/* Rest reserved. */
1750/** @} */
1751
1752
1753/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE return values
1754 * @{
1755 */
1756/** Linear read access. */
1757#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1758/** Linear write access. */
1759#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1760/** Linear instruction fetch access. */
1761#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1762/** Linear read/write access during event delivery. */
1763#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1764/** Physical read/write access during event delivery. */
1765#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1766/** Physical access for an instruction fetch or during instruction execution. */
1767#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1768/** @} */
1769
1770
1771/** @name VMCS field encoding - Natural width guest state fields
1772 * @{
1773 */
1774#define VMX_VMCS_GUEST_CR0 0x6800
1775#define VMX_VMCS_GUEST_CR3 0x6802
1776#define VMX_VMCS_GUEST_CR4 0x6804
1777#define VMX_VMCS_GUEST_ES_BASE 0x6806
1778#define VMX_VMCS_GUEST_CS_BASE 0x6808
1779#define VMX_VMCS_GUEST_SS_BASE 0x680A
1780#define VMX_VMCS_GUEST_DS_BASE 0x680C
1781#define VMX_VMCS_GUEST_FS_BASE 0x680E
1782#define VMX_VMCS_GUEST_GS_BASE 0x6810
1783#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1784#define VMX_VMCS_GUEST_TR_BASE 0x6814
1785#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1786#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1787#define VMX_VMCS_GUEST_DR7 0x681A
1788#define VMX_VMCS_GUEST_RSP 0x681C
1789#define VMX_VMCS_GUEST_RIP 0x681E
1790#define VMX_VMCS_GUEST_RFLAGS 0x6820
1791#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1792#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1793#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1794/** @} */
1795
1796
1797/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1798 * Bits 4-11, 13 and 15-63 are reserved.
1799 * @{
1800 */
1801/** Hardware breakpoint 0 was met. */
1802#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1803/** Hardware breakpoint 1 was met. */
1804#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1805/** Hardware breakpoint 2 was met. */
1806#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1807/** Hardware breakpoint 3 was met. */
1808#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1809/** At least one data or IO breakpoint was hit. */
1810#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1811/** A debug exception would have been triggered by single-step execution mode. */
1812#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1813/** @} */
1814
1815/** @name VMCS field encoding - Natural width host state fields
1816 * @{
1817 */
1818#define VMX_VMCS_HOST_CR0 0x6C00
1819#define VMX_VMCS_HOST_CR3 0x6C02
1820#define VMX_VMCS_HOST_CR4 0x6C04
1821#define VMX_VMCS_HOST_FS_BASE 0x6C06
1822#define VMX_VMCS_HOST_GS_BASE 0x6C08
1823#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1824#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1825#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1826#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1827#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1828#define VMX_VMCS_HOST_RSP 0x6C14
1829#define VMX_VMCS_HOST_RIP 0x6C16
1830/** @} */
1831
1832
1833/** @defgroup grp_vmx_asm vmx assembly helpers
1834 * @{
1835 */
1836
1837/**
1838 * Restores some host-state fields that need not be done on every VM-exit.
1839 *
1840 * @returns VBox status code.
1841 * @param fRestoreHostFlags Flags of which host registers needs to be
1842 * restored.
1843 * @param pRestoreHost Pointer to the host-restore structure.
1844 */
1845DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1846
1847
1848/**
1849 * Dispatches an NMI to the host.
1850 */
1851DECLASM(int) VMXDispatchHostNmi(void);
1852
1853
1854/**
1855 * Executes VMXON
1856 *
1857 * @returns VBox status code
1858 * @param pVMXOn Physical address of VMXON structure
1859 */
1860#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1861DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1862#else
1863DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1864{
1865# if RT_INLINE_ASM_GNU_STYLE
1866 int rc = VINF_SUCCESS;
1867 __asm__ __volatile__ (
1868 "push %3 \n\t"
1869 "push %2 \n\t"
1870 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1871 "ja 2f \n\t"
1872 "je 1f \n\t"
1873 "movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1874 "jmp 2f \n\t"
1875 "1: \n\t"
1876 "movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1877 "2: \n\t"
1878 "add $8, %%esp \n\t"
1879 :"=rm"(rc)
1880 :"0"(VINF_SUCCESS),
1881 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1882 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1883 :"memory"
1884 );
1885 return rc;
1886
1887# elif VMX_USE_MSC_INTRINSICS
1888 unsigned char rcMsc = __vmx_on(&pVMXOn);
1889 if (RT_LIKELY(rcMsc == 0))
1890 return VINF_SUCCESS;
1891 return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
1892
1893# else
1894 int rc = VINF_SUCCESS;
1895 __asm
1896 {
1897 push dword ptr [pVMXOn+4]
1898 push dword ptr [pVMXOn]
1899 _emit 0xF3
1900 _emit 0x0F
1901 _emit 0xC7
1902 _emit 0x34
1903 _emit 0x24 /* VMXON [esp] */
1904 jnc vmxon_good
1905 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1906 jmp the_end
1907
1908vmxon_good:
1909 jnz the_end
1910 mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1911the_end:
1912 add esp, 8
1913 }
1914 return rc;
1915# endif
1916}
1917#endif
1918
1919
1920/**
1921 * Executes VMXOFF
1922 */
1923#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1924DECLASM(void) VMXDisable(void);
1925#else
1926DECLINLINE(void) VMXDisable(void)
1927{
1928# if RT_INLINE_ASM_GNU_STYLE
1929 __asm__ __volatile__ (
1930 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1931 );
1932
1933# elif VMX_USE_MSC_INTRINSICS
1934 __vmx_off();
1935
1936# else
1937 __asm
1938 {
1939 _emit 0x0F
1940 _emit 0x01
1941 _emit 0xC4 /* VMXOFF */
1942 }
1943# endif
1944}
1945#endif
1946
1947
1948/**
1949 * Executes VMCLEAR
1950 *
1951 * @returns VBox status code
1952 * @param pVMCS Physical address of VM control structure
1953 */
1954#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1955DECLASM(int) VMXClearVmcs(RTHCPHYS pVMCS);
1956#else
1957DECLINLINE(int) VMXClearVmcs(RTHCPHYS pVMCS)
1958{
1959# if RT_INLINE_ASM_GNU_STYLE
1960 int rc = VINF_SUCCESS;
1961 __asm__ __volatile__ (
1962 "push %3 \n\t"
1963 "push %2 \n\t"
1964 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1965 "jnc 1f \n\t"
1966 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1967 "1: \n\t"
1968 "add $8, %%esp \n\t"
1969 :"=rm"(rc)
1970 :"0"(VINF_SUCCESS),
1971 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1972 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1973 :"memory"
1974 );
1975 return rc;
1976
1977# elif VMX_USE_MSC_INTRINSICS
1978 unsigned char rcMsc = __vmx_vmclear(&pVMCS);
1979 if (RT_LIKELY(rcMsc == 0))
1980 return VINF_SUCCESS;
1981 return VERR_VMX_INVALID_VMCS_PTR;
1982
1983# else
1984 int rc = VINF_SUCCESS;
1985 __asm
1986 {
1987 push dword ptr [pVMCS+4]
1988 push dword ptr [pVMCS]
1989 _emit 0x66
1990 _emit 0x0F
1991 _emit 0xC7
1992 _emit 0x34
1993 _emit 0x24 /* VMCLEAR [esp] */
1994 jnc success
1995 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1996success:
1997 add esp, 8
1998 }
1999 return rc;
2000# endif
2001}
2002#endif
2003
2004
2005/**
2006 * Executes VMPTRLD
2007 *
2008 * @returns VBox status code
2009 * @param pVMCS Physical address of VMCS structure
2010 */
2011#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2012DECLASM(int) VMXActivateVmcs(RTHCPHYS pVMCS);
2013#else
2014DECLINLINE(int) VMXActivateVmcs(RTHCPHYS pVMCS)
2015{
2016# if RT_INLINE_ASM_GNU_STYLE
2017 int rc = VINF_SUCCESS;
2018 __asm__ __volatile__ (
2019 "push %3 \n\t"
2020 "push %2 \n\t"
2021 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2022 "jnc 1f \n\t"
2023 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2024 "1: \n\t"
2025 "add $8, %%esp \n\t"
2026 :"=rm"(rc)
2027 :"0"(VINF_SUCCESS),
2028 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
2029 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
2030 );
2031 return rc;
2032
2033# elif VMX_USE_MSC_INTRINSICS
2034 unsigned char rcMsc = __vmx_vmptrld(&pVMCS);
2035 if (RT_LIKELY(rcMsc == 0))
2036 return VINF_SUCCESS;
2037 return VERR_VMX_INVALID_VMCS_PTR;
2038
2039# else
2040 int rc = VINF_SUCCESS;
2041 __asm
2042 {
2043 push dword ptr [pVMCS+4]
2044 push dword ptr [pVMCS]
2045 _emit 0x0F
2046 _emit 0xC7
2047 _emit 0x34
2048 _emit 0x24 /* VMPTRLD [esp] */
2049 jnc success
2050 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2051
2052success:
2053 add esp, 8
2054 }
2055 return rc;
2056# endif
2057}
2058#endif
2059
2060/**
2061 * Executes VMPTRST
2062 *
2063 * @returns VBox status code
2064 * @param pVMCS Address that will receive the current pointer
2065 */
2066DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pVMCS);
2067
2068/**
2069 * Executes VMWRITE
2070 *
2071 * @returns VBox status code
2072 * @retval VINF_SUCCESS
2073 * @retval VERR_VMX_INVALID_VMCS_PTR
2074 * @retval VERR_VMX_INVALID_VMCS_FIELD
2075 *
2076 * @param idxField VMCS index
2077 * @param u32Val 32 bits value
2078 *
2079 * @remarks The values of the two status codes can be ORed together, the result
2080 * will be VERR_VMX_INVALID_VMCS_PTR.
2081 */
2082#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2083DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2084#else
2085DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2086{
2087# if RT_INLINE_ASM_GNU_STYLE
2088 int rc = VINF_SUCCESS;
2089 __asm__ __volatile__ (
2090 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2091 "ja 2f \n\t"
2092 "je 1f \n\t"
2093 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2094 "jmp 2f \n\t"
2095 "1: \n\t"
2096 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2097 "2: \n\t"
2098 :"=rm"(rc)
2099 :"0"(VINF_SUCCESS),
2100 "a"(idxField),
2101 "d"(u32Val)
2102 );
2103 return rc;
2104
2105# elif VMX_USE_MSC_INTRINSICS
2106 unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2107 if (RT_LIKELY(rcMsc == 0))
2108 return VINF_SUCCESS;
2109 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2110
2111#else
2112 int rc = VINF_SUCCESS;
2113 __asm
2114 {
2115 push dword ptr [u32Val]
2116 mov eax, [idxField]
2117 _emit 0x0F
2118 _emit 0x79
2119 _emit 0x04
2120 _emit 0x24 /* VMWRITE eax, [esp] */
2121 jnc valid_vmcs
2122 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2123 jmp the_end
2124
2125valid_vmcs:
2126 jnz the_end
2127 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2128the_end:
2129 add esp, 4
2130 }
2131 return rc;
2132# endif
2133}
2134#endif
2135
2136/**
2137 * Executes VMWRITE
2138 *
2139 * @returns VBox status code
2140 * @retval VINF_SUCCESS
2141 * @retval VERR_VMX_INVALID_VMCS_PTR
2142 * @retval VERR_VMX_INVALID_VMCS_FIELD
2143 *
2144 * @param idxField VMCS index
2145 * @param u64Val 16, 32 or 64 bits value
2146 *
2147 * @remarks The values of the two status codes can be ORed together, the result
2148 * will be VERR_VMX_INVALID_VMCS_PTR.
2149 */
2150#if !defined(RT_ARCH_X86) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2151# if !VMX_USE_MSC_INTRINSICS || ARCH_BITS != 64
2152DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2153# else /* VMX_USE_MSC_INTRINSICS */
2154DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2155{
2156 unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2157 if (RT_LIKELY(rcMsc == 0))
2158 return VINF_SUCCESS;
2159 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2160}
2161# endif /* VMX_USE_MSC_INTRINSICS */
2162#else
2163# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2164VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2165#endif
2166
2167#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2168# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
2169 VMXWriteVmcs64(idxField, uVal) \
2170 : VMXWriteVmcs32(idxField, uVal)
2171# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
2172 VMXWriteVmcs64(idxField, u64Val) \
2173 : VMXWriteVmcs32(idxField, u64Val)
2174#elif ARCH_BITS == 32
2175# define VMXWriteVmcsHstN VMXWriteVmcs32
2176# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2177#else /* ARCH_BITS == 64 */
2178# define VMXWriteVmcsHstN VMXWriteVmcs64
2179# define VMXWriteVmcsGstN VMXWriteVmcs64
2180#endif
2181
2182
2183/**
2184 * Invalidate a page using invept
2185 * @returns VBox status code
2186 * @param enmFlush Type of flush
2187 * @param pDescriptor Descriptor
2188 */
2189DECLASM(int) VMXR0InvEPT(VMXFLUSHEPT enmFlush, uint64_t *pDescriptor);
2190
2191/**
2192 * Invalidate a page using invvpid
2193 * @returns VBox status code
2194 * @param enmFlush Type of flush
2195 * @param pDescriptor Descriptor
2196 */
2197DECLASM(int) VMXR0InvVPID(VMXFLUSHVPID enmFlush, uint64_t *pDescriptor);
2198
2199/**
2200 * Executes VMREAD
2201 *
2202 * @returns VBox status code
2203 * @retval VINF_SUCCESS
2204 * @retval VERR_VMX_INVALID_VMCS_PTR
2205 * @retval VERR_VMX_INVALID_VMCS_FIELD
2206 *
2207 * @param idxField VMCS index
2208 * @param pData Ptr to store VM field value
2209 *
2210 * @remarks The values of the two status codes can be ORed together, the result
2211 * will be VERR_VMX_INVALID_VMCS_PTR.
2212 */
2213#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2214DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2215#else
2216DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2217{
2218# if RT_INLINE_ASM_GNU_STYLE
2219 int rc = VINF_SUCCESS;
2220 __asm__ __volatile__ (
2221 "movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2222 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2223 "ja 2f \n\t"
2224 "je 1f \n\t"
2225 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2226 "jmp 2f \n\t"
2227 "1: \n\t"
2228 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2229 "2: \n\t"
2230 :"=&r"(rc),
2231 "=d"(*pData)
2232 :"a"(idxField),
2233 "d"(0)
2234 );
2235 return rc;
2236
2237# elif VMX_USE_MSC_INTRINSICS
2238 unsigned char rcMsc;
2239# if ARCH_BITS == 32
2240 rcMsc = __vmx_vmread(idxField, pData);
2241# else
2242 uint64_t u64Tmp;
2243 rcMsc = __vmx_vmread(idxField, &u64Tmp);
2244 *pData = (uint32_t)u64Tmp;
2245# endif
2246 if (RT_LIKELY(rcMsc == 0))
2247 return VINF_SUCCESS;
2248 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2249
2250#else
2251 int rc = VINF_SUCCESS;
2252 __asm
2253 {
2254 sub esp, 4
2255 mov dword ptr [esp], 0
2256 mov eax, [idxField]
2257 _emit 0x0F
2258 _emit 0x78
2259 _emit 0x04
2260 _emit 0x24 /* VMREAD eax, [esp] */
2261 mov edx, pData
2262 pop dword ptr [edx]
2263 jnc valid_vmcs
2264 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2265 jmp the_end
2266
2267valid_vmcs:
2268 jnz the_end
2269 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2270the_end:
2271 }
2272 return rc;
2273# endif
2274}
2275#endif
2276
2277/**
2278 * Executes VMREAD
2279 *
2280 * @returns VBox status code
2281 * @retval VINF_SUCCESS
2282 * @retval VERR_VMX_INVALID_VMCS_PTR
2283 * @retval VERR_VMX_INVALID_VMCS_FIELD
2284 *
2285 * @param idxField VMCS index
2286 * @param pData Ptr to store VM field value
2287 *
2288 * @remarks The values of the two status codes can be ORed together, the result
2289 * will be VERR_VMX_INVALID_VMCS_PTR.
2290 */
2291#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2292DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2293#else
2294DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2295{
2296# if VMX_USE_MSC_INTRINSICS
2297 unsigned char rcMsc;
2298# if ARCH_BITS == 32
2299 size_t uLow;
2300 size_t uHigh;
2301 rcMsc = __vmx_vmread(idxField, &uLow);
2302 rcMsc |= __vmx_vmread(idxField + 1, &uHigh);
2303 *pData = RT_MAKE_U64(uLow, uHigh);
2304# else
2305 rcMsc = __vmx_vmread(idxField, pData);
2306# endif
2307 if (RT_LIKELY(rcMsc == 0))
2308 return VINF_SUCCESS;
2309 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2310
2311# elif ARCH_BITS == 32
2312 int rc;
2313 uint32_t val_hi, val;
2314 rc = VMXReadVmcs32(idxField, &val);
2315 rc |= VMXReadVmcs32(idxField + 1, &val_hi);
2316 AssertRC(rc);
2317 *pData = RT_MAKE_U64(val, val_hi);
2318 return rc;
2319
2320# else
2321# error "Shouldn't be here..."
2322# endif
2323}
2324#endif
2325
2326/**
2327 * Gets the last instruction error value from the current VMCS
2328 *
2329 * @returns error value
2330 */
2331DECLINLINE(uint32_t) VMXGetLastError(void)
2332{
2333#if ARCH_BITS == 64
2334 uint64_t uLastError = 0;
2335 int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2336 AssertRC(rc);
2337 return (uint32_t)uLastError;
2338
2339#else /* 32-bit host: */
2340 uint32_t uLastError = 0;
2341 int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2342 AssertRC(rc);
2343 return uLastError;
2344#endif
2345}
2346
2347#ifdef IN_RING0
2348VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2349VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2350#endif /* IN_RING0 */
2351
2352/** @} */
2353
2354/** @} */
2355
2356#endif
2357
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