hm_vmx.h@ 73379

Last change on this file since 73379 was 73311, checked in by vboxsync, 7 years ago
VMM/HMVMXR0: Nested VMX: bugref:9180 Cleanups, add new VMCS bits.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# pragma warning(push)
38	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
39	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
40	# include <intrin.h>
41	# pragma warning(pop)
42	/* We always want them as intrinsics, no functions. */
43	# pragma intrinsic(__vmx_on)
44	# pragma intrinsic(__vmx_off)
45	# pragma intrinsic(__vmx_vmclear)
46	# pragma intrinsic(__vmx_vmptrld)
47	# pragma intrinsic(__vmx_vmread)
48	# pragma intrinsic(__vmx_vmwrite)
49	# define VMX_USE_MSC_INTRINSICS 1
50	#else
51	# define VMX_USE_MSC_INTRINSICS 0
52	#endif
53
54
55	/** @defgroup grp_hm_vmx VMX Types and Definitions
56	* @ingroup grp_hm
57	* @{
58	*/
59
60	/** @name Host-state restoration flags.
61	* @note If you change these values don't forget to update the assembly
62	* defines as well!
63	* @{
64	*/
65	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
66	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
67	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
68	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
69	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
70	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
71	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
72	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
73	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
74	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
75	/** @} */
76
77	/**
78	* Host-state restoration structure.
79	* This holds host-state fields that require manual restoration.
80	* Assembly version found in hm_vmx.mac (should be automatically verified).
81	*/
82	typedef struct VMXRESTOREHOST
83	{
84	RTSEL uHostSelDS; /* 0x00 */
85	RTSEL uHostSelES; /* 0x02 */
86	RTSEL uHostSelFS; /* 0x04 */
87	RTSEL uHostSelGS; /* 0x06 */
88	RTSEL uHostSelTR; /* 0x08 */
89	uint8_t abPadding0[4];
90	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
91	uint8_t abPadding1[6];
92	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
93	uint8_t abPadding2[6];
94	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
95	uint64_t uHostFSBase; /* 0x38 */
96	uint64_t uHostGSBase; /* 0x40 */
97	} VMXRESTOREHOST;
98	/** Pointer to VMXRESTOREHOST. */
99	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
100	AssertCompileSize(X86XDTR64, 10);
101	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
102	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
103	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
104	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
105	AssertCompileSize(VMXRESTOREHOST, 72);
106	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
107
108	/** @name Host-state MSR lazy-restoration flags.
109	* @{
110	*/
111	/** The host MSRs have been saved. */
112	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
113	/** The guest MSRs are loaded and in effect. */
114	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
115	/** @} */
116
117	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
118	* UFC = Unsupported Feature Combination.
119	* @{
120	*/
121	/** Unsupported pin-based VM-execution controls combo. */
122	#define VMX_UFC_CTRL_PIN_EXEC 1
123	/** Unsupported processor-based VM-execution controls combo. */
124	#define VMX_UFC_CTRL_PROC_EXEC 2
125	/** Unsupported move debug register VM-exit combo. */
126	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
127	/** Unsupported VM-entry controls combo. */
128	#define VMX_UFC_CTRL_ENTRY 4
129	/** Unsupported VM-exit controls combo. */
130	#define VMX_UFC_CTRL_EXIT 5
131	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
132	* for storing host MSRs. */
133	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
134	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
135	* for storing guest MSRs. */
136	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
137	/** Invalid VMCS size. */
138	#define VMX_UFC_INVALID_VMCS_SIZE 8
139	/** Unsupported secondary processor-based VM-execution controls combo. */
140	#define VMX_UFC_CTRL_PROC_EXEC2 9
141	/** Invalid unrestricted-guest execution controls combo. */
142	#define VMX_UFC_INVALID_UX_COMBO 10
143	/** EPT flush type not supported. */
144	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
145	/** EPT paging structure memory type is not write-back. */
146	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
147	/** EPT requires INVEPT instr. support but it's not available. */
148	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
149	/** EPT requires page-walk length of 4. */
150	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
151	/** @} */
152
153	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
154	* VCI = VMCS-field Cache Invalid.
155	* @{
156	*/
157	/** Cache of VM-entry controls invalid. */
158	#define VMX_VCI_CTRL_ENTRY 300
159	/** Cache of VM-exit controls invalid. */
160	#define VMX_VCI_CTRL_EXIT 301
161	/** Cache of pin-based VM-execution controls invalid. */
162	#define VMX_VCI_CTRL_PIN_EXEC 302
163	/** Cache of processor-based VM-execution controls invalid. */
164	#define VMX_VCI_CTRL_PROC_EXEC 303
165	/** Cache of secondary processor-based VM-execution controls invalid. */
166	#define VMX_VCI_CTRL_PROC_EXEC2 304
167	/** Cache of exception bitmap invalid. */
168	#define VMX_VCI_CTRL_XCPT_BITMAP 305
169	/** Cache of TSC offset invalid. */
170	#define VMX_VCI_CTRL_TSC_OFFSET 306
171	/** @} */
172
173	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
174	* IGS = Invalid Guest State.
175	* @{
176	*/
177	/** An error occurred while checking invalid-guest-state. */
178	#define VMX_IGS_ERROR 500
179	/** The invalid guest-state checks did not find any reason why. */
180	#define VMX_IGS_REASON_NOT_FOUND 501
181	/** CR0 fixed1 bits invalid. */
182	#define VMX_IGS_CR0_FIXED1 502
183	/** CR0 fixed0 bits invalid. */
184	#define VMX_IGS_CR0_FIXED0 503
185	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
186	#define VMX_IGS_CR0_PG_PE_COMBO 504
187	/** CR4 fixed1 bits invalid. */
188	#define VMX_IGS_CR4_FIXED1 505
189	/** CR4 fixed0 bits invalid. */
190	#define VMX_IGS_CR4_FIXED0 506
191	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
192	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
193	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
194	/** CR0.PG not set for long-mode when not using unrestricted guest. */
195	#define VMX_IGS_CR0_PG_LONGMODE 508
196	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
197	#define VMX_IGS_CR4_PAE_LONGMODE 509
198	/** CR4.PCIDE set for 32-bit guest. */
199	#define VMX_IGS_CR4_PCIDE 510
200	/** VMCS' DR7 reserved bits not set to 0. */
201	#define VMX_IGS_DR7_RESERVED 511
202	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
203	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
204	/** VMCS' EFER MSR reserved bits not set to 0. */
205	#define VMX_IGS_EFER_MSR_RESERVED 513
206	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
207	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
208	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
209	* without unrestricted guest. */
210	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
211	/** CS.Attr.P bit invalid. */
212	#define VMX_IGS_CS_ATTR_P_INVALID 516
213	/** CS.Attr reserved bits not set to 0. */
214	#define VMX_IGS_CS_ATTR_RESERVED 517
215	/** CS.Attr.G bit invalid. */
216	#define VMX_IGS_CS_ATTR_G_INVALID 518
217	/** CS is unusable. */
218	#define VMX_IGS_CS_ATTR_UNUSABLE 519
219	/** CS and SS DPL unequal. */
220	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
221	/** CS and SS DPL mismatch. */
222	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
223	/** CS Attr.Type invalid. */
224	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
225	/** CS and SS RPL unequal. */
226	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
227	/** SS.Attr.DPL and SS RPL unequal. */
228	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
229	/** SS.Attr.DPL invalid for segment type. */
230	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
231	/** SS.Attr.Type invalid. */
232	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
233	/** SS.Attr.P bit invalid. */
234	#define VMX_IGS_SS_ATTR_P_INVALID 527
235	/** SS.Attr reserved bits not set to 0. */
236	#define VMX_IGS_SS_ATTR_RESERVED 528
237	/** SS.Attr.G bit invalid. */
238	#define VMX_IGS_SS_ATTR_G_INVALID 529
239	/** DS.Attr.A bit invalid. */
240	#define VMX_IGS_DS_ATTR_A_INVALID 530
241	/** DS.Attr.P bit invalid. */
242	#define VMX_IGS_DS_ATTR_P_INVALID 531
243	/** DS.Attr.DPL and DS RPL unequal. */
244	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
245	/** DS.Attr reserved bits not set to 0. */
246	#define VMX_IGS_DS_ATTR_RESERVED 533
247	/** DS.Attr.G bit invalid. */
248	#define VMX_IGS_DS_ATTR_G_INVALID 534
249	/** DS.Attr.Type invalid. */
250	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
251	/** ES.Attr.A bit invalid. */
252	#define VMX_IGS_ES_ATTR_A_INVALID 536
253	/** ES.Attr.P bit invalid. */
254	#define VMX_IGS_ES_ATTR_P_INVALID 537
255	/** ES.Attr.DPL and DS RPL unequal. */
256	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
257	/** ES.Attr reserved bits not set to 0. */
258	#define VMX_IGS_ES_ATTR_RESERVED 539
259	/** ES.Attr.G bit invalid. */
260	#define VMX_IGS_ES_ATTR_G_INVALID 540
261	/** ES.Attr.Type invalid. */
262	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
263	/** FS.Attr.A bit invalid. */
264	#define VMX_IGS_FS_ATTR_A_INVALID 542
265	/** FS.Attr.P bit invalid. */
266	#define VMX_IGS_FS_ATTR_P_INVALID 543
267	/** FS.Attr.DPL and DS RPL unequal. */
268	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
269	/** FS.Attr reserved bits not set to 0. */
270	#define VMX_IGS_FS_ATTR_RESERVED 545
271	/** FS.Attr.G bit invalid. */
272	#define VMX_IGS_FS_ATTR_G_INVALID 546
273	/** FS.Attr.Type invalid. */
274	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
275	/** GS.Attr.A bit invalid. */
276	#define VMX_IGS_GS_ATTR_A_INVALID 548
277	/** GS.Attr.P bit invalid. */
278	#define VMX_IGS_GS_ATTR_P_INVALID 549
279	/** GS.Attr.DPL and DS RPL unequal. */
280	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
281	/** GS.Attr reserved bits not set to 0. */
282	#define VMX_IGS_GS_ATTR_RESERVED 551
283	/** GS.Attr.G bit invalid. */
284	#define VMX_IGS_GS_ATTR_G_INVALID 552
285	/** GS.Attr.Type invalid. */
286	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
287	/** V86 mode CS.Base invalid. */
288	#define VMX_IGS_V86_CS_BASE_INVALID 554
289	/** V86 mode CS.Limit invalid. */
290	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
291	/** V86 mode CS.Attr invalid. */
292	#define VMX_IGS_V86_CS_ATTR_INVALID 556
293	/** V86 mode SS.Base invalid. */
294	#define VMX_IGS_V86_SS_BASE_INVALID 557
295	/** V86 mode SS.Limit invalid. */
296	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
297	/** V86 mode SS.Attr invalid. */
298	#define VMX_IGS_V86_SS_ATTR_INVALID 559
299	/** V86 mode DS.Base invalid. */
300	#define VMX_IGS_V86_DS_BASE_INVALID 560
301	/** V86 mode DS.Limit invalid. */
302	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
303	/** V86 mode DS.Attr invalid. */
304	#define VMX_IGS_V86_DS_ATTR_INVALID 562
305	/** V86 mode ES.Base invalid. */
306	#define VMX_IGS_V86_ES_BASE_INVALID 563
307	/** V86 mode ES.Limit invalid. */
308	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
309	/** V86 mode ES.Attr invalid. */
310	#define VMX_IGS_V86_ES_ATTR_INVALID 565
311	/** V86 mode FS.Base invalid. */
312	#define VMX_IGS_V86_FS_BASE_INVALID 566
313	/** V86 mode FS.Limit invalid. */
314	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
315	/** V86 mode FS.Attr invalid. */
316	#define VMX_IGS_V86_FS_ATTR_INVALID 568
317	/** V86 mode GS.Base invalid. */
318	#define VMX_IGS_V86_GS_BASE_INVALID 569
319	/** V86 mode GS.Limit invalid. */
320	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
321	/** V86 mode GS.Attr invalid. */
322	#define VMX_IGS_V86_GS_ATTR_INVALID 571
323	/** Longmode CS.Base invalid. */
324	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
325	/** Longmode SS.Base invalid. */
326	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
327	/** Longmode DS.Base invalid. */
328	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
329	/** Longmode ES.Base invalid. */
330	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
331	/** SYSENTER ESP is not canonical. */
332	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
333	/** SYSENTER EIP is not canonical. */
334	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
335	/** PAT MSR invalid. */
336	#define VMX_IGS_PAT_MSR_INVALID 578
337	/** PAT MSR reserved bits not set to 0. */
338	#define VMX_IGS_PAT_MSR_RESERVED 579
339	/** GDTR.Base is not canonical. */
340	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
341	/** IDTR.Base is not canonical. */
342	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
343	/** GDTR.Limit invalid. */
344	#define VMX_IGS_GDTR_LIMIT_INVALID 582
345	/** IDTR.Limit invalid. */
346	#define VMX_IGS_IDTR_LIMIT_INVALID 583
347	/** Longmode RIP is invalid. */
348	#define VMX_IGS_LONGMODE_RIP_INVALID 584
349	/** RFLAGS reserved bits not set to 0. */
350	#define VMX_IGS_RFLAGS_RESERVED 585
351	/** RFLAGS RA1 reserved bits not set to 1. */
352	#define VMX_IGS_RFLAGS_RESERVED1 586
353	/** RFLAGS.VM (V86 mode) invalid. */
354	#define VMX_IGS_RFLAGS_VM_INVALID 587
355	/** RFLAGS.IF invalid. */
356	#define VMX_IGS_RFLAGS_IF_INVALID 588
357	/** Activity state invalid. */
358	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
359	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
360	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
361	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
362	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
363	/** Activity state SIPI WAIT invalid. */
364	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
365	/** Interruptibility state reserved bits not set to 0. */
366	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
367	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
368	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
369	/** Interruptibility state block-by-STI invalid for EFLAGS. */
370	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
371	/** Interruptibility state invalid while trying to deliver external
372	* interrupt. */
373	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
374	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
375	* NMI. */
376	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
377	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
378	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
379	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
380	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
381	/** Interruptibility state block-by-STI (maybe) invalid when trying to
382	* deliver an NMI. */
383	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
384	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
385	* active. */
386	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
387	/** Pending debug exceptions reserved bits not set to 0. */
388	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
389	/** Longmode pending debug exceptions reserved bits not set to 0. */
390	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
391	/** Pending debug exceptions.BS bit is not set when it should be. */
392	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
393	/** Pending debug exceptions.BS bit is not clear when it should be. */
394	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
395	/** VMCS link pointer reserved bits not set to 0. */
396	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
397	/** TR cannot index into LDT, TI bit MBZ. */
398	#define VMX_IGS_TR_TI_INVALID 607
399	/** LDTR cannot index into LDT. TI bit MBZ. */
400	#define VMX_IGS_LDTR_TI_INVALID 608
401	/** TR.Base is not canonical. */
402	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
403	/** FS.Base is not canonical. */
404	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
405	/** GS.Base is not canonical. */
406	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
407	/** LDTR.Base is not canonical. */
408	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
409	/** TR is unusable. */
410	#define VMX_IGS_TR_ATTR_UNUSABLE 613
411	/** TR.Attr.S bit invalid. */
412	#define VMX_IGS_TR_ATTR_S_INVALID 614
413	/** TR is not present. */
414	#define VMX_IGS_TR_ATTR_P_INVALID 615
415	/** TR.Attr reserved bits not set to 0. */
416	#define VMX_IGS_TR_ATTR_RESERVED 616
417	/** TR.Attr.G bit invalid. */
418	#define VMX_IGS_TR_ATTR_G_INVALID 617
419	/** Longmode TR.Attr.Type invalid. */
420	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
421	/** TR.Attr.Type invalid. */
422	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
423	/** CS.Attr.S invalid. */
424	#define VMX_IGS_CS_ATTR_S_INVALID 620
425	/** CS.Attr.DPL invalid. */
426	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
427	/** PAE PDPTE reserved bits not set to 0. */
428	#define VMX_IGS_PAE_PDPTE_RESERVED 623
429	/** @} */
430
431	/** @name VMX VMCS-Read cache indices.
432	* @{
433	*/
434	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
435	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
436	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
437	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
438	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
439	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
440	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
441	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
442	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
443	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
444	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
445	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
446	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
447	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
448	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
449	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
450	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
451	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
452	/** @} */
453
454	/** @name VMX EPT paging structures
455	* @{
456	*/
457
458	/**
459	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
460	*/
461	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
462
463	/**
464	* EPT Page Directory Pointer Entry. Bit view.
465	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
466	* this did cause trouble with one compiler/version).
467	*/
468	typedef struct EPTPML4EBITS
469	{
470	/** Present bit. */
471	uint64_t u1Present : 1;
472	/** Writable bit. */
473	uint64_t u1Write : 1;
474	/** Executable bit. */
475	uint64_t u1Execute : 1;
476	/** Reserved (must be 0). */
477	uint64_t u5Reserved : 5;
478	/** Available for software. */
479	uint64_t u4Available : 4;
480	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
481	uint64_t u40PhysAddr : 40;
482	/** Available for software. */
483	uint64_t u12Available : 12;
484	} EPTPML4EBITS;
485	AssertCompileSize(EPTPML4EBITS, 8);
486
487	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
488	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
489	/** The page shift to get the PML4 index. */
490	#define EPT_PML4_SHIFT X86_PML4_SHIFT
491	/** The PML4 index mask (apply to a shifted page address). */
492	#define EPT_PML4_MASK X86_PML4_MASK
493
494	/**
495	* EPT PML4E.
496	*/
497	typedef union EPTPML4E
498	{
499	/** Normal view. */
500	EPTPML4EBITS n;
501	/** Unsigned integer view. */
502	X86PGPAEUINT u;
503	/** 64 bit unsigned integer view. */
504	uint64_t au64[1];
505	/** 32 bit unsigned integer view. */
506	uint32_t au32[2];
507	} EPTPML4E;
508	AssertCompileSize(EPTPML4E, 8);
509	/** Pointer to a PML4 table entry. */
510	typedef EPTPML4E *PEPTPML4E;
511	/** Pointer to a const PML4 table entry. */
512	typedef const EPTPML4E *PCEPTPML4E;
513
514	/**
515	* EPT PML4 Table.
516	*/
517	typedef struct EPTPML4
518	{
519	EPTPML4E a[EPT_PG_ENTRIES];
520	} EPTPML4;
521	AssertCompileSize(EPTPML4, 0x1000);
522	/** Pointer to an EPT PML4 Table. */
523	typedef EPTPML4 *PEPTPML4;
524	/** Pointer to a const EPT PML4 Table. */
525	typedef const EPTPML4 *PCEPTPML4;
526
527	/**
528	* EPT Page Directory Pointer Entry. Bit view.
529	*/
530	typedef struct EPTPDPTEBITS
531	{
532	/** Present bit. */
533	uint64_t u1Present : 1;
534	/** Writable bit. */
535	uint64_t u1Write : 1;
536	/** Executable bit. */
537	uint64_t u1Execute : 1;
538	/** Reserved (must be 0). */
539	uint64_t u5Reserved : 5;
540	/** Available for software. */
541	uint64_t u4Available : 4;
542	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
543	uint64_t u40PhysAddr : 40;
544	/** Available for software. */
545	uint64_t u12Available : 12;
546	} EPTPDPTEBITS;
547	AssertCompileSize(EPTPDPTEBITS, 8);
548
549	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
550	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
551	/** The page shift to get the PDPT index. */
552	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
553	/** The PDPT index mask (apply to a shifted page address). */
554	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
555
556	/**
557	* EPT Page Directory Pointer.
558	*/
559	typedef union EPTPDPTE
560	{
561	/** Normal view. */
562	EPTPDPTEBITS n;
563	/** Unsigned integer view. */
564	X86PGPAEUINT u;
565	/** 64 bit unsigned integer view. */
566	uint64_t au64[1];
567	/** 32 bit unsigned integer view. */
568	uint32_t au32[2];
569	} EPTPDPTE;
570	AssertCompileSize(EPTPDPTE, 8);
571	/** Pointer to an EPT Page Directory Pointer Entry. */
572	typedef EPTPDPTE *PEPTPDPTE;
573	/** Pointer to a const EPT Page Directory Pointer Entry. */
574	typedef const EPTPDPTE *PCEPTPDPTE;
575
576	/**
577	* EPT Page Directory Pointer Table.
578	*/
579	typedef struct EPTPDPT
580	{
581	EPTPDPTE a[EPT_PG_ENTRIES];
582	} EPTPDPT;
583	AssertCompileSize(EPTPDPT, 0x1000);
584	/** Pointer to an EPT Page Directory Pointer Table. */
585	typedef EPTPDPT *PEPTPDPT;
586	/** Pointer to a const EPT Page Directory Pointer Table. */
587	typedef const EPTPDPT *PCEPTPDPT;
588
589	/**
590	* EPT Page Directory Table Entry. Bit view.
591	*/
592	typedef struct EPTPDEBITS
593	{
594	/** Present bit. */
595	uint64_t u1Present : 1;
596	/** Writable bit. */
597	uint64_t u1Write : 1;
598	/** Executable bit. */
599	uint64_t u1Execute : 1;
600	/** Reserved (must be 0). */
601	uint64_t u4Reserved : 4;
602	/** Big page (must be 0 here). */
603	uint64_t u1Size : 1;
604	/** Available for software. */
605	uint64_t u4Available : 4;
606	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
607	uint64_t u40PhysAddr : 40;
608	/** Available for software. */
609	uint64_t u12Available : 12;
610	} EPTPDEBITS;
611	AssertCompileSize(EPTPDEBITS, 8);
612
613	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
614	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
615	/** The page shift to get the PD index. */
616	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
617	/** The PD index mask (apply to a shifted page address). */
618	#define EPT_PD_MASK X86_PD_PAE_MASK
619
620	/**
621	* EPT 2MB Page Directory Table Entry. Bit view.
622	*/
623	typedef struct EPTPDE2MBITS
624	{
625	/** Present bit. */
626	uint64_t u1Present : 1;
627	/** Writable bit. */
628	uint64_t u1Write : 1;
629	/** Executable bit. */
630	uint64_t u1Execute : 1;
631	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
632	uint64_t u3EMT : 3;
633	/** Ignore PAT memory type */
634	uint64_t u1IgnorePAT : 1;
635	/** Big page (must be 1 here). */
636	uint64_t u1Size : 1;
637	/** Available for software. */
638	uint64_t u4Available : 4;
639	/** Reserved (must be 0). */
640	uint64_t u9Reserved : 9;
641	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
642	uint64_t u31PhysAddr : 31;
643	/** Available for software. */
644	uint64_t u12Available : 12;
645	} EPTPDE2MBITS;
646	AssertCompileSize(EPTPDE2MBITS, 8);
647
648	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
649	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
650
651	/**
652	* EPT Page Directory Table Entry.
653	*/
654	typedef union EPTPDE
655	{
656	/** Normal view. */
657	EPTPDEBITS n;
658	/** 2MB view (big). */
659	EPTPDE2MBITS b;
660	/** Unsigned integer view. */
661	X86PGPAEUINT u;
662	/** 64 bit unsigned integer view. */
663	uint64_t au64[1];
664	/** 32 bit unsigned integer view. */
665	uint32_t au32[2];
666	} EPTPDE;
667	AssertCompileSize(EPTPDE, 8);
668	/** Pointer to an EPT Page Directory Table Entry. */
669	typedef EPTPDE *PEPTPDE;
670	/** Pointer to a const EPT Page Directory Table Entry. */
671	typedef const EPTPDE *PCEPTPDE;
672
673	/**
674	* EPT Page Directory Table.
675	*/
676	typedef struct EPTPD
677	{
678	EPTPDE a[EPT_PG_ENTRIES];
679	} EPTPD;
680	AssertCompileSize(EPTPD, 0x1000);
681	/** Pointer to an EPT Page Directory Table. */
682	typedef EPTPD *PEPTPD;
683	/** Pointer to a const EPT Page Directory Table. */
684	typedef const EPTPD *PCEPTPD;
685
686	/**
687	* EPT Page Table Entry. Bit view.
688	*/
689	typedef struct EPTPTEBITS
690	{
691	/** 0 - Present bit.
692	* @remarks This is a convenience "misnomer". The bit actually indicates read access
693	* and the CPU will consider an entry with any of the first three bits set
694	* as present. Since all our valid entries will have this bit set, it can
695	* be used as a present indicator and allow some code sharing. */
696	uint64_t u1Present : 1;
697	/** 1 - Writable bit. */
698	uint64_t u1Write : 1;
699	/** 2 - Executable bit. */
700	uint64_t u1Execute : 1;
701	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
702	uint64_t u3EMT : 3;
703	/** 6 - Ignore PAT memory type */
704	uint64_t u1IgnorePAT : 1;
705	/** 11:7 - Available for software. */
706	uint64_t u5Available : 5;
707	/** 51:12 - Physical address of page. Restricted by maximum physical
708	* address width of the cpu. */
709	uint64_t u40PhysAddr : 40;
710	/** 63:52 - Available for software. */
711	uint64_t u12Available : 12;
712	} EPTPTEBITS;
713	AssertCompileSize(EPTPTEBITS, 8);
714
715	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
716	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
717	/** The page shift to get the EPT PTE index. */
718	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
719	/** The EPT PT index mask (apply to a shifted page address). */
720	#define EPT_PT_MASK X86_PT_PAE_MASK
721
722	/**
723	* EPT Page Table Entry.
724	*/
725	typedef union EPTPTE
726	{
727	/** Normal view. */
728	EPTPTEBITS n;
729	/** Unsigned integer view. */
730	X86PGPAEUINT u;
731	/** 64 bit unsigned integer view. */
732	uint64_t au64[1];
733	/** 32 bit unsigned integer view. */
734	uint32_t au32[2];
735	} EPTPTE;
736	AssertCompileSize(EPTPTE, 8);
737	/** Pointer to an EPT Page Directory Table Entry. */
738	typedef EPTPTE *PEPTPTE;
739	/** Pointer to a const EPT Page Directory Table Entry. */
740	typedef const EPTPTE *PCEPTPTE;
741
742	/**
743	* EPT Page Table.
744	*/
745	typedef struct EPTPT
746	{
747	EPTPTE a[EPT_PG_ENTRIES];
748	} EPTPT;
749	AssertCompileSize(EPTPT, 0x1000);
750	/** Pointer to an extended page table. */
751	typedef EPTPT *PEPTPT;
752	/** Pointer to a const extended table. */
753	typedef const EPTPT *PCEPTPT;
754
755	/** @} */
756
757	/**
758	* VMX VPID flush types.
759	* @note Valid enum members are in accordance to the VT-x spec.
760	*/
761	typedef enum
762	{
763	/** Invalidate a specific page. */
764	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
765	/** Invalidate one context (specific VPID). */
766	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
767	/** Invalidate all contexts (all VPIDs). */
768	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
769	/** Invalidate a single VPID context retaining global mappings. */
770	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
771	/** Unsupported by VirtualBox. */
772	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
773	/** Unsupported by CPU. */
774	VMXTLBFLUSHVPID_NONE = 0xbad1
775	} VMXTLBFLUSHVPID;
776	AssertCompileSize(VMXTLBFLUSHVPID, 4);
777
778	/**
779	* VMX EPT flush types.
780	* @note Valid enums values are in accordance to the VT-x spec.
781	*/
782	typedef enum
783	{
784	/** Invalidate one context (specific EPT). */
785	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
786	/* Invalidate all contexts (all EPTs) */
787	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
788	/** Unsupported by VirtualBox. */
789	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
790	/** Unsupported by CPU. */
791	VMXTLBFLUSHEPT_NONE = 0xbad1
792	} VMXTLBFLUSHEPT;
793	AssertCompileSize(VMXTLBFLUSHEPT, 4);
794
795	/**
796	* VMX Posted Interrupt Descriptor.
797	* In accordance to the VT-x spec.
798	*/
799	typedef struct VMXPOSTEDINTRDESC
800	{
801	uint32_t aVectorBitmap[8];
802	uint32_t fOutstandingNotification : 1;
803	uint32_t uReserved0 : 31;
804	uint8_t au8Reserved0[28];
805	} VMXPOSTEDINTRDESC;
806	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
807	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
808	/** Pointer to a posted interrupt descriptor. */
809	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
810	/** Pointer to a const posted interrupt descriptor. */
811	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
812
813	/**
814	* VMX MSR autoload/store element.
815	* In accordance to the VT-x spec.
816	*/
817	typedef struct VMXAUTOMSR
818	{
819	/** The MSR Id. */
820	uint32_t u32Msr;
821	/** Reserved (MBZ). */
822	uint32_t u32Reserved;
823	/** The MSR value. */
824	uint64_t u64Value;
825	} VMXAUTOMSR;
826	AssertCompileSize(VMXAUTOMSR, 16);
827	/** Pointer to an MSR load/store element. */
828	typedef VMXAUTOMSR *PVMXAUTOMSR;
829	/** Pointer to a const MSR load/store element. */
830	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
831
832	/**
833	* VMX controls MSR.
834	*/
835	typedef union
836	{
837	struct
838	{
839	/** Bits set here -must- be set in the corresponding VM-execution controls. */
840	uint32_t disallowed0;
841	/** Bits cleared here -must- be cleared in the corresponding VM-execution
842	* controls. */
843	uint32_t allowed1;
844	} n;
845	uint64_t u;
846	} VMXCTLSMSR;
847	AssertCompileSize(VMXCTLSMSR, 8);
848	/** Pointer to a VMXCTLSMSR union. */
849	typedef VMXCTLSMSR *PVMXCTLSMSR;
850	/** Pointer to a const VMXCTLSMSR union. */
851	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
852
853	/**
854	* VMX tagged-TLB flush types.
855	*/
856	typedef enum
857	{
858	VMXTLBFLUSHTYPE_EPT,
859	VMXTLBFLUSHTYPE_VPID,
860	VMXTLBFLUSHTYPE_EPT_VPID,
861	VMXTLBFLUSHTYPE_NONE
862	} VMXTLBFLUSHTYPE;
863	/** Pointer to a VMXTLBFLUSHTYPE enum. */
864	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
865	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
866	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
867
868	/**
869	* VMX MSRs.
870	*/
871	typedef struct VMXMSRS
872	{
873	uint64_t u64FeatCtrl;
874	uint64_t u64Basic;
875	VMXCTLSMSR PinCtls;
876	VMXCTLSMSR ProcCtls;
877	VMXCTLSMSR ProcCtls2;
878	VMXCTLSMSR ExitCtls;
879	VMXCTLSMSR EntryCtls;
880	VMXCTLSMSR TruePinCtls;
881	VMXCTLSMSR TrueProcCtls;
882	VMXCTLSMSR TrueEntryCtls;
883	VMXCTLSMSR TrueExitCtls;
884	uint64_t u64Misc;
885	uint64_t u64Cr0Fixed0;
886	uint64_t u64Cr0Fixed1;
887	uint64_t u64Cr4Fixed0;
888	uint64_t u64Cr4Fixed1;
889	uint64_t u64VmcsEnum;
890	uint64_t u64Vmfunc;
891	uint64_t u64EptVpidCaps;
892	} VMXMSRS;
893	AssertCompileSizeAlignment(VMXMSRS, 8);
894	/** Pointer to a VMXMSRS struct. */
895	typedef VMXMSRS *PVMXMSRS;
896
897	/** @name VMX Basic Exit Reasons.
898	* @{
899	*/
900	/** -1 Invalid exit code */
901	#define VMX_EXIT_INVALID (-1)
902	/** 0 Exception or non-maskable interrupt (NMI). */
903	#define VMX_EXIT_XCPT_OR_NMI 0
904	/** 1 External interrupt. */
905	#define VMX_EXIT_EXT_INT 1
906	/** 2 Triple fault. */
907	#define VMX_EXIT_TRIPLE_FAULT 2
908	/** 3 INIT signal. */
909	#define VMX_EXIT_INIT_SIGNAL 3
910	/** 4 Start-up IPI (SIPI). */
911	#define VMX_EXIT_SIPI 4
912	/** 5 I/O system-management interrupt (SMI). */
913	#define VMX_EXIT_IO_SMI 5
914	/** 6 Other SMI. */
915	#define VMX_EXIT_SMI 6
916	/** 7 Interrupt window exiting. */
917	#define VMX_EXIT_INT_WINDOW 7
918	/** 8 NMI window exiting. */
919	#define VMX_EXIT_NMI_WINDOW 8
920	/** 9 Task switch. */
921	#define VMX_EXIT_TASK_SWITCH 9
922	/** 10 Guest software attempted to execute CPUID. */
923	#define VMX_EXIT_CPUID 10
924	/** 11 Guest software attempted to execute GETSEC. */
925	#define VMX_EXIT_GETSEC 11
926	/** 12 Guest software attempted to execute HLT. */
927	#define VMX_EXIT_HLT 12
928	/** 13 Guest software attempted to execute INVD. */
929	#define VMX_EXIT_INVD 13
930	/** 14 Guest software attempted to execute INVLPG. */
931	#define VMX_EXIT_INVLPG 14
932	/** 15 Guest software attempted to execute RDPMC. */
933	#define VMX_EXIT_RDPMC 15
934	/** 16 Guest software attempted to execute RDTSC. */
935	#define VMX_EXIT_RDTSC 16
936	/** 17 Guest software attempted to execute RSM in SMM. */
937	#define VMX_EXIT_RSM 17
938	/** 18 Guest software executed VMCALL. */
939	#define VMX_EXIT_VMCALL 18
940	/** 19 Guest software executed VMCLEAR. */
941	#define VMX_EXIT_VMCLEAR 19
942	/** 20 Guest software executed VMLAUNCH. */
943	#define VMX_EXIT_VMLAUNCH 20
944	/** 21 Guest software executed VMPTRLD. */
945	#define VMX_EXIT_VMPTRLD 21
946	/** 22 Guest software executed VMPTRST. */
947	#define VMX_EXIT_VMPTRST 22
948	/** 23 Guest software executed VMREAD. */
949	#define VMX_EXIT_VMREAD 23
950	/** 24 Guest software executed VMRESUME. */
951	#define VMX_EXIT_VMRESUME 24
952	/** 25 Guest software executed VMWRITE. */
953	#define VMX_EXIT_VMWRITE 25
954	/** 26 Guest software executed VMXOFF. */
955	#define VMX_EXIT_VMXOFF 26
956	/** 27 Guest software executed VMXON. */
957	#define VMX_EXIT_VMXON 27
958	/** 28 Control-register accesses. */
959	#define VMX_EXIT_MOV_CRX 28
960	/** 29 Debug-register accesses. */
961	#define VMX_EXIT_MOV_DRX 29
962	/** 30 I/O instruction. */
963	#define VMX_EXIT_IO_INSTR 30
964	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
965	#define VMX_EXIT_RDMSR 31
966	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
967	#define VMX_EXIT_WRMSR 32
968	/** 33 VM-entry failure due to invalid guest state. */
969	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
970	/** 34 VM-entry failure due to MSR loading. */
971	#define VMX_EXIT_ERR_MSR_LOAD 34
972	/** 36 Guest software executed MWAIT. */
973	#define VMX_EXIT_MWAIT 36
974	/** 37 VM-exit due to monitor trap flag. */
975	#define VMX_EXIT_MTF 37
976	/** 39 Guest software attempted to execute MONITOR. */
977	#define VMX_EXIT_MONITOR 39
978	/** 40 Guest software attempted to execute PAUSE. */
979	#define VMX_EXIT_PAUSE 40
980	/** 41 VM-entry failure due to machine-check. */
981	#define VMX_EXIT_ERR_MACHINE_CHECK 41
982	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
983	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
984	/** 44 APIC access. Guest software attempted to access memory at a physical
985	* address on the APIC-access page. */
986	#define VMX_EXIT_APIC_ACCESS 44
987	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
988	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
989	#define VMX_EXIT_VIRTUALIZED_EOI 45
990	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
991	* SGDT, or SIDT. */
992	#define VMX_EXIT_XDTR_ACCESS 46
993	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
994	* SLDT, or STR. */
995	#define VMX_EXIT_TR_ACCESS 47
996	/** 48 EPT violation. An attempt to access memory with a guest-physical address
997	* was disallowed by the configuration of the EPT paging structures. */
998	#define VMX_EXIT_EPT_VIOLATION 48
999	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1000	* address encountered a misconfigured EPT paging-structure entry. */
1001	#define VMX_EXIT_EPT_MISCONFIG 49
1002	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1003	#define VMX_EXIT_INVEPT 50
1004	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1005	#define VMX_EXIT_RDTSCP 51
1006	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1007	#define VMX_EXIT_PREEMPT_TIMER 52
1008	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1009	#define VMX_EXIT_INVVPID 53
1010	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1011	#define VMX_EXIT_WBINVD 54
1012	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1013	#define VMX_EXIT_XSETBV 55
1014	/** 56 APIC write. Guest completed write to virtual-APIC. */
1015	#define VMX_EXIT_APIC_WRITE 56
1016	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1017	#define VMX_EXIT_RDRAND 57
1018	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1019	#define VMX_EXIT_INVPCID 58
1020	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1021	#define VMX_EXIT_VMFUNC 59
1022	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1023	#define VMX_EXIT_ENCLS 60
1024	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1025	* enabled. */
1026	#define VMX_EXIT_RDSEED 61
1027	/** 62 - Page-modification log full. */
1028	#define VMX_EXIT_PML_FULL 62
1029	/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
1030	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1031	#define VMX_EXIT_XSAVES 63
1032	/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
1033	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1034	#define VMX_EXIT_XRSTORS 64
1035	/** The maximum exit value (inclusive). */
1036	#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
1037	/** @} */
1038
1039
1040	/** @name VM Instruction Errors.
1041	* @{
1042	*/
1043	/** VMCALL executed in VMX root operation. */
1044	#define VMX_ERROR_VMCALL 1
1045	/** VMCLEAR with invalid physical address. */
1046	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1047	/** VMCLEAR with VMXON pointer. */
1048	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1049	/** VMLAUNCH with non-clear VMCS. */
1050	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1051	/** VMRESUME with non-launched VMCS. */
1052	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1053	/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1054	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1055	/** VM-entry with invalid control field(s). */
1056	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1057	/** VM-entry with invalid host-state field(s). */
1058	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1059	/** VMPTRLD with invalid physical address. */
1060	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1061	/** VMPTRLD with VMXON pointer. */
1062	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1063	/** VMPTRLD with incorrect VMCS revision identifier. */
1064	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1065	/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1066	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1067	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1068	/** VMWRITE to read-only VMCS component. */
1069	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1070	/** VMXON executed in VMX root operation. */
1071	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1072	/** VM-entry with invalid executive-VMCS pointer. */
1073	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1074	/** VM-entry with non-launched executive VMCS. */
1075	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1076	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1077	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1078	/** VMCALL with non-clear VMCS. */
1079	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1080	/** VMCALL with invalid VM-exit control fields. */
1081	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1082	/** VMCALL with incorrect MSEG revision identifier. */
1083	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1084	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1085	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1086	/** VMCALL with invalid SMM-monitor features. */
1087	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1088	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1089	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1090	/** VM-entry with events blocked by MOV SS. */
1091	#define VMX_ERROR_VMENTRY_MOV_SS 26
1092	/** Invalid operand to INVEPT/INVVPID. */
1093	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1094	/** @} */
1095
1096
1097	/** @name VMX MSR - Basic VMX information.
1098	* @{
1099	*/
1100	/** VMCS revision identifier used by the processor. */
1101	#define MSR_IA32_VMX_BASIC_VMCS_ID(a) ((a) & 0x7fffffff)
1102	/** Shift to get the VMCS size. */
1103	#define MSR_IA32_VMX_BASIC_VMCS_SIZE_SHIFT 32
1104	/** VMCS size in bytes. */
1105	#define MSR_IA32_VMX_BASIC_VMCS_SIZE(a) (((a) >> 32) & 0x1fff)
1106	/** Shift to get the width of physical addresses and associated memory regions. */
1107	#define MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH_SHIFT 48
1108	/** Width of physical addresses used for the VMCS and associated memory regions. */
1109	#define MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1110	/** Shift to get the dual-monitor treatment of SMI and SMM. */
1111	#define MSR_IA32_VMX_BASIC_DUAL_MON_SHIFT 49
1112	/** Dual-monitor treatment of SMI and SMM supported. */
1113	#define MSR_IA32_VMX_BASIC_DUAL_MON(a) (((a) >> 49) & 1)
1114	/** Shift to get the memory type that must be used for the VMCS and associated
1115	* memory regions. */
1116	#define MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE_SHIFT 50
1117	/** Memory type that must be used for the VMCS and associated memory regions. */
1118	#define MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xf)
1119	/** Shift to get the additional VM-exit information for INS/OUTS. */
1120	#define MSR_IA32_VMX_BASIC_VMCS_INS_OUTS_SHIFT 54
1121	/** Additional VM-exit information for INS/OUTS. */
1122	#define MSR_IA32_VMX_BASIC_VMCS_INS_OUTS(a) (((a) >> 54) & 1)
1123	/** Shift to get the VMCS true controls. */
1124	#define MSR_IA32_VMX_BASIC_TRUE_CONTROLS_SHIFT 55
1125	/** Whether default 1 bits in control MSRs (pin/proc/exit/entry) may be
1126	* cleared to 0 and that 'true' control MSRs are supported. */
1127	#define MSR_IA32_VMX_BASIC_TRUE_CONTROLS(a) (((a) >> 55) & 1)
1128	/** @} */
1129
1130
1131	/** @name VMX MSR - Misc VMX info.
1132	* @{
1133	*/
1134	/** Relationship between the preemption timer and tsc; count down every time bit
1135	* x of the tsc changes. */
1136	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1137	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1138	#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1139	/** Activity states supported by the implementation. */
1140	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1141	/** Number of CR3 target values supported by the processor. (0-256) */
1142	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1ff)
1143	/** Maximum number of MSRs in the VMCS. (N+1)512. /
1144	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1145	/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1146	#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1147	/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1148	#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1149	/** Whether VMWRITE can be used to write VM-exit information fields. */
1150	#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1151	/** MSEG revision identifier used by the processor. */
1152	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1153	/** @} */
1154
1155
1156	/** @name VMX MSR - VMCS enumeration field info
1157	* @{
1158	*/
1159	/** Highest field index. */
1160	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1ff)
1161	/** @} */
1162
1163
1164	/** @name VMX MSR - EPT/VPID capabilities.
1165	* @{
1166	*/
1167	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1168	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1169	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1170	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1171	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1172	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1173	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1174	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1175	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1176	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1177	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1178	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1179	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1180	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1181	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1182	/** @} */
1183
1184
1185	/** @name Extended Page Table Pointer (EPTP)
1186	* @{
1187	*/
1188	/** Uncachable EPT paging structure memory type. */
1189	#define VMX_EPT_MEMTYPE_UC 0
1190	/** Write-back EPT paging structure memory type. */
1191	#define VMX_EPT_MEMTYPE_WB 6
1192	/** Shift value to get the EPT page walk length (bits 5-3) */
1193	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1194	/** Mask value to get the EPT page walk length (bits 5-3) */
1195	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1196	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1197	* length) */
1198	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1199	/** @} */
1200
1201
1202	/** @name VMCS field encoding: 16-bit guest fields.
1203	* @{
1204	*/
1205	#define VMX_VMCS16_VPID 0x000
1206	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x002
1207	#define VMX_VMCS16_EPTP_INDEX 0x004
1208	#define VMX_VMCS16_GUEST_ES_SEL 0x800
1209	#define VMX_VMCS16_GUEST_CS_SEL 0x802
1210	#define VMX_VMCS16_GUEST_SS_SEL 0x804
1211	#define VMX_VMCS16_GUEST_DS_SEL 0x806
1212	#define VMX_VMCS16_GUEST_FS_SEL 0x808
1213	#define VMX_VMCS16_GUEST_GS_SEL 0x80a
1214	#define VMX_VMCS16_GUEST_LDTR_SEL 0x80c
1215	#define VMX_VMCS16_GUEST_TR_SEL 0x80e
1216	#define VMX_VMCS16_GUEST_INTR_STATUS 0x810
1217	#define VMX_VMCS16_GUEST_PML_INDEX 0x812
1218	/** @} */
1219
1220
1221	/** @name VMCS field encoding: 16-bits host fields.
1222	* @{
1223	*/
1224	#define VMX_VMCS16_HOST_ES_SEL 0xc00
1225	#define VMX_VMCS16_HOST_CS_SEL 0xc02
1226	#define VMX_VMCS16_HOST_SS_SEL 0xc04
1227	#define VMX_VMCS16_HOST_DS_SEL 0xc06
1228	#define VMX_VMCS16_HOST_FS_SEL 0xc08
1229	#define VMX_VMCS16_HOST_GS_SEL 0xc0a
1230	#define VMX_VMCS16_HOST_TR_SEL 0xc0c
1231	/** @} */
1232
1233
1234	/** @name VMCS field encoding: 64-bit control fields.
1235	* @{
1236	*/
1237	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1238	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1239	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1240	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1241	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1242	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1243	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1244	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1245	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1246	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1247	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1248	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1249	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1250	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1251	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1252	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1253	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1254	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1255	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1256	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1257	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1258	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1259	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1260	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1261	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1262	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1263	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1264	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1265	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1266	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1267	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1268	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1269	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1270	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1271	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1272	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1273	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1274	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1275	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1276	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1277	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1278	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1279	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1280	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1281	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1282	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1283	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1284	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1285	/** @} */
1286
1287
1288	/** @name VMCS field encoding: 64-bit read-only data fields.
1289	* @{
1290	*/
1291	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1292	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1293	/** @} */
1294
1295
1296	/** @name VMCS field encoding: 64-bit guest fields.
1297	* @{
1298	*/
1299	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1300	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1301	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
1302	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
1303	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1304	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1305	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1306	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1307	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
1308	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
1309	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1310	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1311	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1312	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1313	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1314	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1315	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1316	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1317	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1318	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1319	/** @} */
1320
1321
1322	/** @name VMCS field encoding: 64-bit host fields.
1323	* @{
1324	*/
1325	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1326	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1327	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1328	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1329	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04 /*< MSR IA32_PERF_GLOBAL_CTRL /
1330	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05 /*< MSR IA32_PERF_GLOBAL_CTRL /
1331	/** @} */
1332
1333
1334	/** @name VMCS field encoding: 32-bit control fields.
1335	* @{
1336	*/
1337	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1338	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1339	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1340	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1341	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1342	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1343	#define VMX_VMCS32_CTRL_EXIT 0x400c
1344	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1345	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1346	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1347	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1348	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1349	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1350	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1351	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1352	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1353	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1354	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1355	/** @} */
1356
1357
1358	/** @name VMCS field encoding: 32-bits read-only fields.
1359	* @{
1360	*/
1361	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1362	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1363	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1364	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1365	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1366	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1367	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1368	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1369	/** @} */
1370
1371
1372	/** @name VMCS field encoding: 32-bit guest-state fields.
1373	* @{
1374	*/
1375	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1376	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1377	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1378	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1379	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1380	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1381	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1382	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1383	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1384	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1385	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1386	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1387	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1388	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1389	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1390	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1391	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1392	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1393	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1394	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1395	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1396	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a /*< MSR IA32_SYSENTER_CS /
1397	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1398	/** @} */
1399
1400
1401	/** @name VMCS field encoding: 32-bit host-state fields.
1402	* @{
1403	*/
1404	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1405	/** @} */
1406
1407
1408	/** @name Natural width control fields.
1409	* @{
1410	*/
1411	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1412	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1413	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1414	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1415	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1416	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1417	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1418	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600e
1419	/** @} */
1420
1421	/** @name Natural width read-only data fields.
1422	* @{
1423	*/
1424	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1425	#define VMX_VMCS_RO_IO_RCX 0x6402
1426	#define VMX_VMCS_RO_IO_RSX 0x6404
1427	#define VMX_VMCS_RO_IO_RDI 0x6406
1428	#define VMX_VMCS_RO_IO_RIP 0x6408
1429	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640a
1430	/** @} */
1431
1432
1433	/** @name VMCS field encoding: Natural width guest-state fields.
1434	* @{
1435	*/
1436	#define VMX_VMCS_GUEST_CR0 0x6800
1437	#define VMX_VMCS_GUEST_CR3 0x6802
1438	#define VMX_VMCS_GUEST_CR4 0x6804
1439	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1440	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1441	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1442	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1443	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1444	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1445	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1446	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1447	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1448	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1449	#define VMX_VMCS_GUEST_DR7 0x681a
1450	#define VMX_VMCS_GUEST_RSP 0x681c
1451	#define VMX_VMCS_GUEST_RIP 0x681e
1452	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1453	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
1454	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1455	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1456	/** @} */
1457
1458
1459	/** @name VMCS field encoding: Natural width host-state fields.
1460	* @{
1461	*/
1462	#define VMX_VMCS_HOST_CR0 0x6c00
1463	#define VMX_VMCS_HOST_CR3 0x6c02
1464	#define VMX_VMCS_HOST_CR4 0x6c04
1465	#define VMX_VMCS_HOST_FS_BASE 0x6c06
1466	#define VMX_VMCS_HOST_GS_BASE 0x6c08
1467	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
1468	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
1469	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
1470	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
1471	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
1472	#define VMX_VMCS_HOST_RSP 0x6c14
1473	#define VMX_VMCS_HOST_RIP 0x6c16
1474	/** @} */
1475
1476
1477	/** @name Pin-based VM-execution controls.
1478	* @{
1479	*/
1480	/** External interrupts cause VM-exits if set; otherwise dispatched through the
1481	* guest's IDT. */
1482	#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1483	/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through
1484	* the guest's IDT. */
1485	#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1486	/** Virtual NMIs. */
1487	#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1488	/** Activate VMX preemption timer. */
1489	#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1490	/** Process interrupts with the posted-interrupt notification vector. */
1491	#define VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR RT_BIT(7)
1492	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1493	/** @} */
1494
1495
1496	/** @name Processor-based VM-execution controls.
1497	* @{
1498	*/
1499	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1500	#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1501	/** Use timestamp counter offset. */
1502	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1503	/** VM-exit when executing the HLT instruction. */
1504	#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1505	/** VM-exit when executing the INVLPG instruction. */
1506	#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1507	/** VM-exit when executing the MWAIT instruction. */
1508	#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1509	/** VM-exit when executing the RDPMC instruction. */
1510	#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1511	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1512	#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1513	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
1514	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1515	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1516	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
1517	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1518	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1519	/** VM-exit on CR8 loads. */
1520	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1521	/** VM-exit on CR8 stores. */
1522	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1523	/** Use TPR shadow. */
1524	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1525	/** VM-exit when virtual NMI blocking is disabled. */
1526	#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1527	/** VM-exit when executing a MOV DRx instruction. */
1528	#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1529	/** VM-exit when executing IO instructions. */
1530	#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1531	/** Use IO bitmaps. */
1532	#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1533	/** Monitor trap flag. */
1534	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1535	/** Use MSR bitmaps. */
1536	#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1537	/** VM-exit when executing the MONITOR instruction. */
1538	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1539	/** VM-exit when executing the PAUSE instruction. */
1540	#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1541	/** Whether the secondary processor based VM-execution controls are used. */
1542	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1543	/** @} */
1544
1545
1546	/** @name Secondary Processor-based VM-execution controls.
1547	* @{
1548	*/
1549	/** Virtualize APIC access. */
1550	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1551	/** EPT supported/enabled. */
1552	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1553	/** Descriptor table instructions cause VM-exits. */
1554	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1555	/** RDTSCP supported/enabled. */
1556	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1557	/** Virtualize x2APIC mode. */
1558	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1559	/** VPID supported/enabled. */
1560	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1561	/** VM-exit when executing the WBINVD instruction. */
1562	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1563	/** Unrestricted guest execution. */
1564	#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1565	/** APIC register virtualization. */
1566	#define VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT RT_BIT(8)
1567	/** Virtual-interrupt delivery. */
1568	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY RT_BIT(9)
1569	/** A specified number of pause loops cause a VM-exit. */
1570	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1571	/** VM-exit when executing RDRAND instructions. */
1572	#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1573	/** Enables INVPCID instructions. */
1574	#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1575	/** Enables VMFUNC instructions. */
1576	#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1577	/** Enables VMCS shadowing. */
1578	#define VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING RT_BIT(14)
1579	/** Enables ENCLS VM-exits. */
1580	#define VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT RT_BIT(15)
1581	/** VM-exit when executing RDSEED. */
1582	#define VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT RT_BIT(16)
1583	/** Enables page-modification logging. */
1584	#define VMX_VMCS_CTRL_PROC_EXEC2_PML RT_BIT(17)
1585	/** Controls whether EPT-violations may cause \#VE instead of exits. */
1586	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE RT_BIT(18)
1587	/** Conceal VMX non-root operation from Intel processor trace (PT). */
1588	#define VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT RT_BIT(19)
1589	/** Enables XSAVES/XRSTORS instructions. */
1590	#define VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS RT_BIT(20)
1591	/** Use TSC scaling. */
1592	#define VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING RT_BIT(25)
1593	/** @} */
1594
1595
1596	/** @name VM-entry controls.
1597	* @{
1598	*/
1599	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
1600	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1601	#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1602	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1603	#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1604	/** In SMM mode after VM-entry. */
1605	#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1606	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1607	#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1608	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
1609	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1610	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
1611	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1612	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
1613	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1614	/** @} */
1615
1616
1617	/** @name VM-exit controls.
1618	* @{
1619	*/
1620	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
1621	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1622	#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1623	/** Return to long mode after a VM-exit. */
1624	#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1625	/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
1626	#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1627	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1628	#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1629	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
1630	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1631	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
1632	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1633	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
1634	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1635	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
1636	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1637	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
1638	#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1639	/** @} */
1640
1641
1642	/** @name VM function controls.
1643	* @{
1644	*/
1645	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1646	#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1647	/** @} */
1648
1649
1650	/** @name VM-exit reason.
1651	* @{
1652	*/
1653	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
1654	/** @} */
1655
1656
1657	/** @name VM-entry interruption information.
1658	* @{
1659	*/
1660	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
1661	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
1662	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
1663	/** @} */
1664
1665
1666	/** @name VM-exit interruption information.
1667	* @{
1668	*/
1669	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
1670	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
1671	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
1672	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
1673	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
1674	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
1675	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
1676	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
1677	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
1678	/** Construct an irq event injection value from the exit interruption info value
1679	* (same except that bit 12 is reserved). */
1680	#define VMX_VMCS_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
1681	/** @} */
1682
1683
1684	/** @name VM-exit interruption information types.
1685	* @{
1686	*/
1687	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
1688	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
1689	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
1690	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
1691	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
1692	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
1693	/** @} */
1694
1695
1696	/** @name IDT-vectoring information.
1697	* @{
1698	*/
1699	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
1700	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1701	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
1702	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1703	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
1704	#define VMX_IDT_VECTORING_INFO_VALID(a) ((a) & RT_BIT(31))
1705	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
1706	/** @} */
1707
1708
1709	/** @name IDT-vectoring information vector types.
1710	* @{
1711	*/
1712	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1713	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1714	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1715	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1716	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1717	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1718	/** @} */
1719
1720
1721	/** @name Guest-activity states.
1722	* @{
1723	*/
1724	/** The logical processor is active. */
1725	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1726	/** The logical processor is inactive, because executed a HLT instruction. */
1727	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1728	/** The logical processor is inactive, because of a triple fault or other serious error. */
1729	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1730	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1731	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1732	/** @} */
1733
1734
1735	/** @name Guest-interruptibility states.
1736	* @{
1737	*/
1738	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
1739	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
1740	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
1741	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
1742	/** @} */
1743
1744
1745	/** @name Exit qualification for Mov DRx.
1746	* @{
1747	*/
1748	/** 0-2: Debug register number */
1749	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
1750	/** 3: Reserved; cleared to 0. */
1751	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
1752	/** 4: Direction of move (0 = write, 1 = read) */
1753	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
1754	/** 5-7: Reserved; cleared to 0. */
1755	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
1756	/** 8-11: General purpose register number. */
1757	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
1758	/** Rest: reserved. */
1759	/** @} */
1760
1761
1762	/** @name Exit qualification for debug exceptions types.
1763	* @{
1764	*/
1765	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
1766	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
1767	/** @} */
1768
1769
1770	/** @name Exit qualification for control-register accesses.
1771	* @{
1772	*/
1773	/** 0-3: Control register number (0 for CLTS & LMSW) */
1774	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
1775	/** 4-5: Access type. */
1776	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
1777	/** 6: LMSW operand type */
1778	#define VMX_EXIT_QUAL_CRX_LMSW_OP(a) (((a) >> 6) & 1)
1779	/** 7: Reserved; cleared to 0. */
1780	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
1781	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1782	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
1783	/** 12-15: Reserved; cleared to 0. */
1784	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
1785	/** 16-31: LMSW source data (else 0). */
1786	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
1787	/* Rest: reserved. */
1788	/** @} */
1789
1790
1791	/** @name Exit qualification for control-register access types.
1792	* @{
1793	*/
1794	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
1795	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
1796	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
1797	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
1798	/** @} */
1799
1800
1801	/** @name Exit qualification for task switch.
1802	* @{
1803	*/
1804	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
1805	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
1806	/** Task switch caused by a call instruction. */
1807	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
1808	/** Task switch caused by an iret instruction. */
1809	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
1810	/** Task switch caused by a jmp instruction. */
1811	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
1812	/** Task switch caused by an interrupt gate. */
1813	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
1814	/** @} */
1815
1816
1817	/** @name Exit qualification for EPT violations.
1818	* @{
1819	*/
1820	/** Set if the violation was caused by a data read. */
1821	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
1822	/** Set if the violation was caused by a data write. */
1823	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
1824	/** Set if the violation was caused by an instruction fetch. */
1825	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
1826	/** AND of the present bit of all EPT structures. */
1827	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
1828	/** AND of the write bit of all EPT structures. */
1829	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
1830	/** AND of the execute bit of all EPT structures. */
1831	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
1832	/** Set if the guest linear address field contains the faulting address. */
1833	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
1834	/** If bit 7 is one: (reserved otherwise)
1835	* 1 - violation due to physical address access.
1836	* 0 - violation caused by page walk or access/dirty bit updates
1837	*/
1838	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
1839	/** @} */
1840
1841
1842	/** @name Exit qualification for I/O instructions.
1843	* @{
1844	*/
1845	/** 0-2: IO operation width. */
1846	#define VMX_EXIT_QUAL_IO_WIDTH(a) ((a) & 7)
1847	/** 3: IO operation direction. */
1848	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
1849	/** 4: String IO operation (INS / OUTS). */
1850	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
1851	/** 5: Repeated IO operation. */
1852	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
1853	/** 6: Operand encoding. */
1854	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
1855	/** 16-31: IO Port (0-0xffff). */
1856	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
1857	/* Rest reserved. */
1858	/** @} */
1859
1860
1861	/** @name Exit qualification for I/O instruction types.
1862	* @{
1863	*/
1864	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
1865	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
1866	/** @} */
1867
1868
1869	/** @name Exit qualification for I/O instruction encoding.
1870	* @{
1871	*/
1872	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
1873	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
1874	/** @} */
1875
1876
1877	/** @name Exit qualification for APIC-access VM-exits from linear and
1878	* guest-physical accesses.
1879	* @{
1880	*/
1881	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
1882	* access within the APIC page. */
1883	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1884	/** 12-15: Access type. */
1885	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
1886	/* Rest reserved. */
1887	/** @} */
1888
1889
1890	/** @name Exit qualification for linear address APIC-access types.
1891	* @{
1892	*/
1893	/** Linear read access. */
1894	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1895	/** Linear write access. */
1896	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1897	/** Linear instruction fetch access. */
1898	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1899	/** Linear read/write access during event delivery. */
1900	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1901	/** Physical read/write access during event delivery. */
1902	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1903	/** Physical access for an instruction fetch or during instruction execution. */
1904	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1905	/** @} */
1906
1907
1908	/** @name VMX_XDTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information
1909	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
1910	* @{
1911	*/
1912	/** Address calculation scaling field (powers of two). */
1913	#define VMX_XDTR_INSINFO_SCALE_SHIFT 0
1914	#define VMX_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
1915	/** Bits 2 thru 6 are undefined. */
1916	#define VMX_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
1917	#define VMX_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
1918	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
1919	* @remarks anyone's guess why this is a 3 bit field... */
1920	#define VMX_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
1921	#define VMX_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
1922	/** Bit 10 is defined as zero. */
1923	#define VMX_XDTR_INSINFO_ZERO_10_SHIFT 10
1924	#define VMX_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
1925	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
1926	* for exits from 64-bit code as the operand size there is fixed. */
1927	#define VMX_XDTR_INSINFO_OP_SIZE_SHIFT 11
1928	#define VMX_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
1929	/** Bits 12 thru 14 are undefined. */
1930	#define VMX_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
1931	#define VMX_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
1932	/** Applicable segment register (X86_SREG_XXX values). */
1933	#define VMX_XDTR_INSINFO_SREG_SHIFT 15
1934	#define VMX_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
1935	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
1936	#define VMX_XDTR_INSINFO_INDEX_REG_SHIFT 18
1937	#define VMX_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
1938	/** Is VMX_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
1939	#define VMX_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
1940	#define VMX_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
1941	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
1942	#define VMX_XDTR_INSINFO_BASE_REG_SHIFT 23
1943	#define VMX_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
1944	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
1945	#define VMX_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
1946	#define VMX_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
1947	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values) */
1948	#define VMX_XDTR_INSINFO_INSTR_ID_SHIFT 28
1949	#define VMX_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
1950	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
1951	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
1952	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
1953	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
1954	/** Bits 30 & 31 are undefined. */
1955	#define VMX_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
1956	#define VMX_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
1957	RT_BF_ASSERT_COMPILE_CHECKS(VMX_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
1958	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
1959	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
1960	/** @} */
1961
1962
1963	/** @name VMX_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information
1964	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
1965	* This is similar to VMX_XDTR_INSINFO_XXX.
1966	* @{
1967	*/
1968	/** Address calculation scaling field (powers of two). */
1969	#define VMX_YYTR_INSINFO_SCALE_SHIFT 0
1970	#define VMX_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
1971	/** Bit 2 is undefined. */
1972	#define VMX_YYTR_INSINFO_UNDEF_2_SHIFT 2
1973	#define VMX_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
1974	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
1975	#define VMX_YYTR_INSINFO_REG1_SHIFT 3
1976	#define VMX_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
1977	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
1978	* @remarks anyone's guess why this is a 3 bit field... */
1979	#define VMX_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
1980	#define VMX_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
1981	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
1982	#define VMX_YYTR_INSINFO_HAS_REG1_SHIFT 10
1983	#define VMX_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
1984	/** Bits 11 thru 14 are undefined. */
1985	#define VMX_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
1986	#define VMX_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
1987	/** Applicable segment register (X86_SREG_XXX values). */
1988	#define VMX_YYTR_INSINFO_SREG_SHIFT 15
1989	#define VMX_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
1990	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
1991	#define VMX_YYTR_INSINFO_INDEX_REG_SHIFT 18
1992	#define VMX_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
1993	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
1994	#define VMX_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
1995	#define VMX_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
1996	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
1997	#define VMX_YYTR_INSINFO_BASE_REG_SHIFT 23
1998	#define VMX_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
1999	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2000	#define VMX_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
2001	#define VMX_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2002	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
2003	#define VMX_YYTR_INSINFO_INSTR_ID_SHIFT 28
2004	#define VMX_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2005	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
2006	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
2007	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
2008	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
2009	/** Bits 30 & 31 are undefined. */
2010	#define VMX_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
2011	#define VMX_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
2012	RT_BF_ASSERT_COMPILE_CHECKS(VMX_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
2013	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
2014	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
2015	/** @} */
2016
2017
2018	/** @name Format of Pending-Debug-Exceptions.
2019	* Bits 4-11, 13, 15 and 17-63 are reserved.
2020	* @{
2021	*/
2022	/** Hardware breakpoint 0 was met. */
2023	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT(0)
2024	/** Hardware breakpoint 1 was met. */
2025	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT(1)
2026	/** Hardware breakpoint 2 was met. */
2027	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT(2)
2028	/** Hardware breakpoint 3 was met. */
2029	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT(3)
2030	/** At least one data or IO breakpoint was hit. */
2031	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT(12)
2032	/** A debug exception would have been triggered by single-step execution mode. */
2033	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT(14)
2034	/** A debug exception occurred inside an RTM region. */
2035	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT(16)
2036	/** @} */
2037
2038
2039	/** VMCS revision identifier used for emulating VMX (bit 31 MBZ). Bump this
2040	* arbitarily chosen identifier if incompatible changes to the layout of our VMCS
2041	* structure is done. */
2042	#define VMX_VMCS_REVISION_ID UINT32_C(0x1d000001)
2043	AssertCompile(!(VMX_VMCS_REVISION_ID & RT_BIT(31)));
2044	/** VMCS (and related regions) memory type - Uncacheable. */
2045	#define VMX_VMCS_MEM_TYPE_UC 0
2046	/** VMCS (and related regions) memory type - Write back. */
2047	#define VMX_VMCS_MEM_TYPE_WB 6
2048
2049
2050	/** @defgroup grp_hm_vmx_asm VMX Assembly Helpers
2051	* @{
2052	*/
2053
2054	/**
2055	* Restores some host-state fields that need not be done on every VM-exit.
2056	*
2057	* @returns VBox status code.
2058	* @param fRestoreHostFlags Flags of which host registers needs to be
2059	* restored.
2060	* @param pRestoreHost Pointer to the host-restore structure.
2061	*/
2062	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
2063
2064
2065	/**
2066	* Dispatches an NMI to the host.
2067	*/
2068	DECLASM(int) VMXDispatchHostNmi(void);
2069
2070
2071	/**
2072	* Executes VMXON.
2073	*
2074	* @returns VBox status code.
2075	* @param HCPhysVmxOn Physical address of VMXON structure.
2076	*/
2077	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2078	DECLASM(int) VMXEnable(RTHCPHYS HCPhysVmxOn);
2079	#else
2080	DECLINLINE(int) VMXEnable(RTHCPHYS HCPhysVmxOn)
2081	{
2082	# if RT_INLINE_ASM_GNU_STYLE
2083	int rc = VINF_SUCCESS;
2084	__asm__ __volatile__ (
2085	"push %3 \n\t"
2086	"push %2 \n\t"
2087	".byte 0xf3, 0x0f, 0xc7, 0x34, 0x24 # VMXON [esp] \n\t"
2088	"ja 2f \n\t"
2089	"je 1f \n\t"
2090	"movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
2091	"jmp 2f \n\t"
2092	"1: \n\t"
2093	"movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
2094	"2: \n\t"
2095	"add $8, %%esp \n\t"
2096	:"=rm"(rc)
2097	:"0"(VINF_SUCCESS),
2098	"ir"((uint32_t)HCPhysVmxOn), /* don't allow direct memory reference here, */
2099	"ir"((uint32_t)(HCPhysVmxOn >> 32)) /* this would not work with -fomit-frame-pointer */
2100	:"memory"
2101	);
2102	return rc;
2103
2104	# elif VMX_USE_MSC_INTRINSICS
2105	unsigned char rcMsc = __vmx_on(&HCPhysVmxOn);
2106	if (RT_LIKELY(rcMsc == 0))
2107	return VINF_SUCCESS;
2108	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
2109
2110	# else
2111	int rc = VINF_SUCCESS;
2112	__asm
2113	{
2114	push dword ptr [HCPhysVmxOn + 4]
2115	push dword ptr [HCPhysVmxOn]
2116	_emit 0xf3
2117	_emit 0x0f
2118	_emit 0xc7
2119	_emit 0x34
2120	_emit 0x24 /* VMXON [esp] */
2121	jnc vmxon_good
2122	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
2123	jmp the_end
2124
2125	vmxon_good:
2126	jnz the_end
2127	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
2128	the_end:
2129	add esp, 8
2130	}
2131	return rc;
2132	# endif
2133	}
2134	#endif
2135
2136
2137	/**
2138	* Executes VMXOFF.
2139	*/
2140	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2141	DECLASM(void) VMXDisable(void);
2142	#else
2143	DECLINLINE(void) VMXDisable(void)
2144	{
2145	# if RT_INLINE_ASM_GNU_STYLE
2146	__asm__ __volatile__ (
2147	".byte 0x0f, 0x01, 0xc4 # VMXOFF \n\t"
2148	);
2149
2150	# elif VMX_USE_MSC_INTRINSICS
2151	__vmx_off();
2152
2153	# else
2154	__asm
2155	{
2156	_emit 0x0f
2157	_emit 0x01
2158	_emit 0xc4 /* VMXOFF */
2159	}
2160	# endif
2161	}
2162	#endif
2163
2164
2165	/**
2166	* Executes VMCLEAR.
2167	*
2168	* @returns VBox status code.
2169	* @param HCPhysVmcs Physical address of VM control structure.
2170	*/
2171	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2172	DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
2173	#else
2174	DECLINLINE(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs)
2175	{
2176	# if RT_INLINE_ASM_GNU_STYLE
2177	int rc = VINF_SUCCESS;
2178	__asm__ __volatile__ (
2179	"push %3 \n\t"
2180	"push %2 \n\t"
2181	".byte 0x66, 0x0f, 0xc7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
2182	"jnc 1f \n\t"
2183	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2184	"1: \n\t"
2185	"add $8, %%esp \n\t"
2186	:"=rm"(rc)
2187	:"0"(VINF_SUCCESS),
2188	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2189	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this would not work with -fomit-frame-pointer */
2190	:"memory"
2191	);
2192	return rc;
2193
2194	# elif VMX_USE_MSC_INTRINSICS
2195	unsigned char rcMsc = __vmx_vmclear(&HCPhysVmcs);
2196	if (RT_LIKELY(rcMsc == 0))
2197	return VINF_SUCCESS;
2198	return VERR_VMX_INVALID_VMCS_PTR;
2199
2200	# else
2201	int rc = VINF_SUCCESS;
2202	__asm
2203	{
2204	push dword ptr [HCPhysVmcs + 4]
2205	push dword ptr [HCPhysVmcs]
2206	_emit 0x66
2207	_emit 0x0f
2208	_emit 0xc7
2209	_emit 0x34
2210	_emit 0x24 /* VMCLEAR [esp] */
2211	jnc success
2212	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2213	success:
2214	add esp, 8
2215	}
2216	return rc;
2217	# endif
2218	}
2219	#endif
2220
2221
2222	/**
2223	* Executes VMPTRLD.
2224	*
2225	* @returns VBox status code.
2226	* @param HCPhysVmcs Physical address of VMCS structure.
2227	*/
2228	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2229	DECLASM(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs);
2230	#else
2231	DECLINLINE(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs)
2232	{
2233	# if RT_INLINE_ASM_GNU_STYLE
2234	int rc = VINF_SUCCESS;
2235	__asm__ __volatile__ (
2236	"push %3 \n\t"
2237	"push %2 \n\t"
2238	".byte 0x0f, 0xc7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2239	"jnc 1f \n\t"
2240	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2241	"1: \n\t"
2242	"add $8, %%esp \n\t"
2243	:"=rm"(rc)
2244	:"0"(VINF_SUCCESS),
2245	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2246	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this will not work with -fomit-frame-pointer */
2247	);
2248	return rc;
2249
2250	# elif VMX_USE_MSC_INTRINSICS
2251	unsigned char rcMsc = __vmx_vmptrld(&HCPhysVmcs);
2252	if (RT_LIKELY(rcMsc == 0))
2253	return VINF_SUCCESS;
2254	return VERR_VMX_INVALID_VMCS_PTR;
2255
2256	# else
2257	int rc = VINF_SUCCESS;
2258	__asm
2259	{
2260	push dword ptr [HCPhysVmcs + 4]
2261	push dword ptr [HCPhysVmcs]
2262	_emit 0x0f
2263	_emit 0xc7
2264	_emit 0x34
2265	_emit 0x24 /* VMPTRLD [esp] */
2266	jnc success
2267	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2268
2269	success:
2270	add esp, 8
2271	}
2272	return rc;
2273	# endif
2274	}
2275	#endif
2276
2277
2278	/**
2279	* Executes VMPTRST.
2280	*
2281	* @returns VBox status code.
2282	* @param pHCPhysVmcs Where to store the physical address of the current
2283	* VMCS.
2284	*/
2285	DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
2286
2287
2288	/**
2289	* Executes VMWRITE.
2290	*
2291	* @returns VBox status code.
2292	* @retval VINF_SUCCESS.
2293	* @retval VERR_VMX_INVALID_VMCS_PTR.
2294	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2295	*
2296	* @param idxField VMCS index.
2297	* @param u32Val 32-bit value.
2298	*
2299	* @remarks The values of the two status codes can be OR'ed together, the result
2300	* will be VERR_VMX_INVALID_VMCS_PTR.
2301	*/
2302	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2303	DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2304	#else
2305	DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2306	{
2307	# if RT_INLINE_ASM_GNU_STYLE
2308	int rc = VINF_SUCCESS;
2309	__asm__ __volatile__ (
2310	".byte 0x0f, 0x79, 0xc2 # VMWRITE eax, edx \n\t"
2311	"ja 2f \n\t"
2312	"je 1f \n\t"
2313	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2314	"jmp 2f \n\t"
2315	"1: \n\t"
2316	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2317	"2: \n\t"
2318	:"=rm"(rc)
2319	:"0"(VINF_SUCCESS),
2320	"a"(idxField),
2321	"d"(u32Val)
2322	);
2323	return rc;
2324
2325	# elif VMX_USE_MSC_INTRINSICS
2326	unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2327	if (RT_LIKELY(rcMsc == 0))
2328	return VINF_SUCCESS;
2329	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2330
2331	#else
2332	int rc = VINF_SUCCESS;
2333	__asm
2334	{
2335	push dword ptr [u32Val]
2336	mov eax, [idxField]
2337	_emit 0x0f
2338	_emit 0x79
2339	_emit 0x04
2340	_emit 0x24 /* VMWRITE eax, [esp] */
2341	jnc valid_vmcs
2342	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2343	jmp the_end
2344
2345	valid_vmcs:
2346	jnz the_end
2347	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2348	the_end:
2349	add esp, 4
2350	}
2351	return rc;
2352	# endif
2353	}
2354	#endif
2355
2356	/**
2357	* Executes VMWRITE.
2358	*
2359	* @returns VBox status code.
2360	* @retval VINF_SUCCESS.
2361	* @retval VERR_VMX_INVALID_VMCS_PTR.
2362	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2363	*
2364	* @param idxField VMCS index.
2365	* @param u64Val 16, 32 or 64-bit value.
2366	*
2367	* @remarks The values of the two status codes can be OR'ed together, the result
2368	* will be VERR_VMX_INVALID_VMCS_PTR.
2369	*/
2370	#if !defined(RT_ARCH_X86)
2371	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
2372	DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2373	# else /* VMX_USE_MSC_INTRINSICS */
2374	DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2375	{
2376	unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2377	if (RT_LIKELY(rcMsc == 0))
2378	return VINF_SUCCESS;
2379	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2380	}
2381	# endif /* VMX_USE_MSC_INTRINSICS */
2382	#else
2383	# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2384	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2385	#endif
2386
2387	#if ARCH_BITS == 32
2388	# define VMXWriteVmcsHstN VMXWriteVmcs32
2389	# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2390	#else /* ARCH_BITS == 64 */
2391	# define VMXWriteVmcsHstN VMXWriteVmcs64
2392	# define VMXWriteVmcsGstN VMXWriteVmcs64
2393	#endif
2394
2395
2396	/**
2397	* Invalidate a page using INVEPT.
2398	*
2399	* @returns VBox status code.
2400	* @param enmFlush Type of flush.
2401	* @param pDescriptor Pointer to the descriptor.
2402	*/
2403	DECLASM(int) VMXR0InvEPT(VMXTLBFLUSHEPT enmFlush, uint64_t *pDescriptor);
2404
2405
2406	/**
2407	* Invalidate a page using INVVPID.
2408	*
2409	* @returns VBox status code.
2410	* @param enmFlush Type of flush.
2411	* @param pDescriptor Pointer to the descriptor.
2412	*/
2413	DECLASM(int) VMXR0InvVPID(VMXTLBFLUSHVPID enmFlush, uint64_t *pDescriptor);
2414
2415
2416	/**
2417	* Executes VMREAD.
2418	*
2419	* @returns VBox status code.
2420	* @retval VINF_SUCCESS.
2421	* @retval VERR_VMX_INVALID_VMCS_PTR.
2422	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2423	*
2424	* @param idxField VMCS index.
2425	* @param pData Where to store VM field value.
2426	*
2427	* @remarks The values of the two status codes can be OR'ed together, the result
2428	* will be VERR_VMX_INVALID_VMCS_PTR.
2429	*/
2430	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2431	DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2432	#else
2433	DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2434	{
2435	# if RT_INLINE_ASM_GNU_STYLE
2436	int rc = VINF_SUCCESS;
2437	__asm__ __volatile__ (
2438	"movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2439	".byte 0x0f, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2440	"ja 2f \n\t"
2441	"je 1f \n\t"
2442	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2443	"jmp 2f \n\t"
2444	"1: \n\t"
2445	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2446	"2: \n\t"
2447	:"=&r"(rc),
2448	"=d"(*pData)
2449	:"a"(idxField),
2450	"d"(0)
2451	);
2452	return rc;
2453
2454	# elif VMX_USE_MSC_INTRINSICS
2455	unsigned char rcMsc;
2456	# if ARCH_BITS == 32
2457	rcMsc = __vmx_vmread(idxField, pData);
2458	# else
2459	uint64_t u64Tmp;
2460	rcMsc = __vmx_vmread(idxField, &u64Tmp);
2461	*pData = (uint32_t)u64Tmp;
2462	# endif
2463	if (RT_LIKELY(rcMsc == 0))
2464	return VINF_SUCCESS;
2465	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2466
2467	#else
2468	int rc = VINF_SUCCESS;
2469	__asm
2470	{
2471	sub esp, 4
2472	mov dword ptr [esp], 0
2473	mov eax, [idxField]
2474	_emit 0x0f
2475	_emit 0x78
2476	_emit 0x04
2477	_emit 0x24 /* VMREAD eax, [esp] */
2478	mov edx, pData
2479	pop dword ptr [edx]
2480	jnc valid_vmcs
2481	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2482	jmp the_end
2483
2484	valid_vmcs:
2485	jnz the_end
2486	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2487	the_end:
2488	}
2489	return rc;
2490	# endif
2491	}
2492	#endif
2493
2494	/**
2495	* Executes VMREAD.
2496	*
2497	* @returns VBox status code.
2498	* @retval VINF_SUCCESS.
2499	* @retval VERR_VMX_INVALID_VMCS_PTR.
2500	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2501	*
2502	* @param idxField VMCS index.
2503	* @param pData Where to store VM field value.
2504	*
2505	* @remarks The values of the two status codes can be OR'ed together, the result
2506	* will be VERR_VMX_INVALID_VMCS_PTR.
2507	*/
2508	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS)
2509	DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2510	#else
2511	DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2512	{
2513	# if VMX_USE_MSC_INTRINSICS
2514	unsigned char rcMsc;
2515	# if ARCH_BITS == 32
2516	size_t uLow;
2517	size_t uHigh;
2518	rcMsc = __vmx_vmread(idxField, &uLow);
2519	rcMsc \|= __vmx_vmread(idxField + 1, &uHigh);
2520	*pData = RT_MAKE_U64(uLow, uHigh);
2521	# else
2522	rcMsc = __vmx_vmread(idxField, pData);
2523	# endif
2524	if (RT_LIKELY(rcMsc == 0))
2525	return VINF_SUCCESS;
2526	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2527
2528	# elif ARCH_BITS == 32
2529	int rc;
2530	uint32_t val_hi, val;
2531	rc = VMXReadVmcs32(idxField, &val);
2532	rc \|= VMXReadVmcs32(idxField + 1, &val_hi);
2533	AssertRC(rc);
2534	*pData = RT_MAKE_U64(val, val_hi);
2535	return rc;
2536
2537	# else
2538	# error "Shouldn't be here..."
2539	# endif
2540	}
2541	#endif
2542
2543
2544	/**
2545	* Gets the last instruction error value from the current VMCS.
2546	*
2547	* @returns VBox status code.
2548	*/
2549	DECLINLINE(uint32_t) VMXGetLastError(void)
2550	{
2551	#if ARCH_BITS == 64
2552	uint64_t uLastError = 0;
2553	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2554	AssertRC(rc);
2555	return (uint32_t)uLastError;
2556
2557	#else /* 32-bit host: */
2558	uint32_t uLastError = 0;
2559	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2560	AssertRC(rc);
2561	return uLastError;
2562	#endif
2563	}
2564
2565	/** @} */
2566
2567	/** @} */
2568
2569	#endif
2570

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 73379

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