hm_vmx.h@ 74175

Last change on this file since 74175 was 74171, checked in by vboxsync, 6 years ago
VMM/CPUM, IEM: Nested VMX: bugref:9180 vmlaunch/vmresume bits.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# pragma warning(push)
38	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
39	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
40	# include <intrin.h>
41	# pragma warning(pop)
42	/* We always want them as intrinsics, no functions. */
43	# pragma intrinsic(__vmx_on)
44	# pragma intrinsic(__vmx_off)
45	# pragma intrinsic(__vmx_vmclear)
46	# pragma intrinsic(__vmx_vmptrld)
47	# pragma intrinsic(__vmx_vmread)
48	# pragma intrinsic(__vmx_vmwrite)
49	# define VMX_USE_MSC_INTRINSICS 1
50	#else
51	# define VMX_USE_MSC_INTRINSICS 0
52	#endif
53
54
55	/** @defgroup grp_hm_vmx VMX Types and Definitions
56	* @ingroup grp_hm
57	* @{
58	*/
59
60	/** @name Host-state restoration flags.
61	* @note If you change these values don't forget to update the assembly
62	* defines as well!
63	* @{
64	*/
65	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
66	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
67	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
68	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
69	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
70	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
71	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
72	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
73	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
74	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
75	/** @} */
76
77	/**
78	* Host-state restoration structure.
79	* This holds host-state fields that require manual restoration.
80	* Assembly version found in hm_vmx.mac (should be automatically verified).
81	*/
82	typedef struct VMXRESTOREHOST
83	{
84	RTSEL uHostSelDS; /* 0x00 */
85	RTSEL uHostSelES; /* 0x02 */
86	RTSEL uHostSelFS; /* 0x04 */
87	RTSEL uHostSelGS; /* 0x06 */
88	RTSEL uHostSelTR; /* 0x08 */
89	uint8_t abPadding0[4];
90	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
91	uint8_t abPadding1[6];
92	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
93	uint8_t abPadding2[6];
94	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
95	uint64_t uHostFSBase; /* 0x38 */
96	uint64_t uHostGSBase; /* 0x40 */
97	} VMXRESTOREHOST;
98	/** Pointer to VMXRESTOREHOST. */
99	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
100	AssertCompileSize(X86XDTR64, 10);
101	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
102	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
103	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
104	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
105	AssertCompileSize(VMXRESTOREHOST, 72);
106	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
107
108	/** @name Host-state MSR lazy-restoration flags.
109	* @{
110	*/
111	/** The host MSRs have been saved. */
112	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
113	/** The guest MSRs are loaded and in effect. */
114	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
115	/** @} */
116
117	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
118	* UFC = Unsupported Feature Combination.
119	* @{
120	*/
121	/** Unsupported pin-based VM-execution controls combo. */
122	#define VMX_UFC_CTRL_PIN_EXEC 1
123	/** Unsupported processor-based VM-execution controls combo. */
124	#define VMX_UFC_CTRL_PROC_EXEC 2
125	/** Unsupported move debug register VM-exit combo. */
126	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
127	/** Unsupported VM-entry controls combo. */
128	#define VMX_UFC_CTRL_ENTRY 4
129	/** Unsupported VM-exit controls combo. */
130	#define VMX_UFC_CTRL_EXIT 5
131	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
132	* for storing host MSRs. */
133	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
134	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
135	* for storing guest MSRs. */
136	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
137	/** Invalid VMCS size. */
138	#define VMX_UFC_INVALID_VMCS_SIZE 8
139	/** Unsupported secondary processor-based VM-execution controls combo. */
140	#define VMX_UFC_CTRL_PROC_EXEC2 9
141	/** Invalid unrestricted-guest execution controls combo. */
142	#define VMX_UFC_INVALID_UX_COMBO 10
143	/** EPT flush type not supported. */
144	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
145	/** EPT paging structure memory type is not write-back. */
146	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
147	/** EPT requires INVEPT instr. support but it's not available. */
148	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
149	/** EPT requires page-walk length of 4. */
150	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
151	/** @} */
152
153	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
154	* VCI = VMCS-field Cache Invalid.
155	* @{
156	*/
157	/** Cache of VM-entry controls invalid. */
158	#define VMX_VCI_CTRL_ENTRY 300
159	/** Cache of VM-exit controls invalid. */
160	#define VMX_VCI_CTRL_EXIT 301
161	/** Cache of pin-based VM-execution controls invalid. */
162	#define VMX_VCI_CTRL_PIN_EXEC 302
163	/** Cache of processor-based VM-execution controls invalid. */
164	#define VMX_VCI_CTRL_PROC_EXEC 303
165	/** Cache of secondary processor-based VM-execution controls invalid. */
166	#define VMX_VCI_CTRL_PROC_EXEC2 304
167	/** Cache of exception bitmap invalid. */
168	#define VMX_VCI_CTRL_XCPT_BITMAP 305
169	/** Cache of TSC offset invalid. */
170	#define VMX_VCI_CTRL_TSC_OFFSET 306
171	/** @} */
172
173	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
174	* IGS = Invalid Guest State.
175	* @{
176	*/
177	/** An error occurred while checking invalid-guest-state. */
178	#define VMX_IGS_ERROR 500
179	/** The invalid guest-state checks did not find any reason why. */
180	#define VMX_IGS_REASON_NOT_FOUND 501
181	/** CR0 fixed1 bits invalid. */
182	#define VMX_IGS_CR0_FIXED1 502
183	/** CR0 fixed0 bits invalid. */
184	#define VMX_IGS_CR0_FIXED0 503
185	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
186	#define VMX_IGS_CR0_PG_PE_COMBO 504
187	/** CR4 fixed1 bits invalid. */
188	#define VMX_IGS_CR4_FIXED1 505
189	/** CR4 fixed0 bits invalid. */
190	#define VMX_IGS_CR4_FIXED0 506
191	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
192	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
193	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
194	/** CR0.PG not set for long-mode when not using unrestricted guest. */
195	#define VMX_IGS_CR0_PG_LONGMODE 508
196	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
197	#define VMX_IGS_CR4_PAE_LONGMODE 509
198	/** CR4.PCIDE set for 32-bit guest. */
199	#define VMX_IGS_CR4_PCIDE 510
200	/** VMCS' DR7 reserved bits not set to 0. */
201	#define VMX_IGS_DR7_RESERVED 511
202	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
203	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
204	/** VMCS' EFER MSR reserved bits not set to 0. */
205	#define VMX_IGS_EFER_MSR_RESERVED 513
206	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
207	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
208	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
209	* without unrestricted guest. */
210	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
211	/** CS.Attr.P bit invalid. */
212	#define VMX_IGS_CS_ATTR_P_INVALID 516
213	/** CS.Attr reserved bits not set to 0. */
214	#define VMX_IGS_CS_ATTR_RESERVED 517
215	/** CS.Attr.G bit invalid. */
216	#define VMX_IGS_CS_ATTR_G_INVALID 518
217	/** CS is unusable. */
218	#define VMX_IGS_CS_ATTR_UNUSABLE 519
219	/** CS and SS DPL unequal. */
220	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
221	/** CS and SS DPL mismatch. */
222	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
223	/** CS Attr.Type invalid. */
224	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
225	/** CS and SS RPL unequal. */
226	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
227	/** SS.Attr.DPL and SS RPL unequal. */
228	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
229	/** SS.Attr.DPL invalid for segment type. */
230	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
231	/** SS.Attr.Type invalid. */
232	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
233	/** SS.Attr.P bit invalid. */
234	#define VMX_IGS_SS_ATTR_P_INVALID 527
235	/** SS.Attr reserved bits not set to 0. */
236	#define VMX_IGS_SS_ATTR_RESERVED 528
237	/** SS.Attr.G bit invalid. */
238	#define VMX_IGS_SS_ATTR_G_INVALID 529
239	/** DS.Attr.A bit invalid. */
240	#define VMX_IGS_DS_ATTR_A_INVALID 530
241	/** DS.Attr.P bit invalid. */
242	#define VMX_IGS_DS_ATTR_P_INVALID 531
243	/** DS.Attr.DPL and DS RPL unequal. */
244	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
245	/** DS.Attr reserved bits not set to 0. */
246	#define VMX_IGS_DS_ATTR_RESERVED 533
247	/** DS.Attr.G bit invalid. */
248	#define VMX_IGS_DS_ATTR_G_INVALID 534
249	/** DS.Attr.Type invalid. */
250	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
251	/** ES.Attr.A bit invalid. */
252	#define VMX_IGS_ES_ATTR_A_INVALID 536
253	/** ES.Attr.P bit invalid. */
254	#define VMX_IGS_ES_ATTR_P_INVALID 537
255	/** ES.Attr.DPL and DS RPL unequal. */
256	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
257	/** ES.Attr reserved bits not set to 0. */
258	#define VMX_IGS_ES_ATTR_RESERVED 539
259	/** ES.Attr.G bit invalid. */
260	#define VMX_IGS_ES_ATTR_G_INVALID 540
261	/** ES.Attr.Type invalid. */
262	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
263	/** FS.Attr.A bit invalid. */
264	#define VMX_IGS_FS_ATTR_A_INVALID 542
265	/** FS.Attr.P bit invalid. */
266	#define VMX_IGS_FS_ATTR_P_INVALID 543
267	/** FS.Attr.DPL and DS RPL unequal. */
268	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
269	/** FS.Attr reserved bits not set to 0. */
270	#define VMX_IGS_FS_ATTR_RESERVED 545
271	/** FS.Attr.G bit invalid. */
272	#define VMX_IGS_FS_ATTR_G_INVALID 546
273	/** FS.Attr.Type invalid. */
274	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
275	/** GS.Attr.A bit invalid. */
276	#define VMX_IGS_GS_ATTR_A_INVALID 548
277	/** GS.Attr.P bit invalid. */
278	#define VMX_IGS_GS_ATTR_P_INVALID 549
279	/** GS.Attr.DPL and DS RPL unequal. */
280	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
281	/** GS.Attr reserved bits not set to 0. */
282	#define VMX_IGS_GS_ATTR_RESERVED 551
283	/** GS.Attr.G bit invalid. */
284	#define VMX_IGS_GS_ATTR_G_INVALID 552
285	/** GS.Attr.Type invalid. */
286	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
287	/** V86 mode CS.Base invalid. */
288	#define VMX_IGS_V86_CS_BASE_INVALID 554
289	/** V86 mode CS.Limit invalid. */
290	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
291	/** V86 mode CS.Attr invalid. */
292	#define VMX_IGS_V86_CS_ATTR_INVALID 556
293	/** V86 mode SS.Base invalid. */
294	#define VMX_IGS_V86_SS_BASE_INVALID 557
295	/** V86 mode SS.Limit invalid. */
296	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
297	/** V86 mode SS.Attr invalid. */
298	#define VMX_IGS_V86_SS_ATTR_INVALID 559
299	/** V86 mode DS.Base invalid. */
300	#define VMX_IGS_V86_DS_BASE_INVALID 560
301	/** V86 mode DS.Limit invalid. */
302	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
303	/** V86 mode DS.Attr invalid. */
304	#define VMX_IGS_V86_DS_ATTR_INVALID 562
305	/** V86 mode ES.Base invalid. */
306	#define VMX_IGS_V86_ES_BASE_INVALID 563
307	/** V86 mode ES.Limit invalid. */
308	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
309	/** V86 mode ES.Attr invalid. */
310	#define VMX_IGS_V86_ES_ATTR_INVALID 565
311	/** V86 mode FS.Base invalid. */
312	#define VMX_IGS_V86_FS_BASE_INVALID 566
313	/** V86 mode FS.Limit invalid. */
314	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
315	/** V86 mode FS.Attr invalid. */
316	#define VMX_IGS_V86_FS_ATTR_INVALID 568
317	/** V86 mode GS.Base invalid. */
318	#define VMX_IGS_V86_GS_BASE_INVALID 569
319	/** V86 mode GS.Limit invalid. */
320	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
321	/** V86 mode GS.Attr invalid. */
322	#define VMX_IGS_V86_GS_ATTR_INVALID 571
323	/** Longmode CS.Base invalid. */
324	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
325	/** Longmode SS.Base invalid. */
326	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
327	/** Longmode DS.Base invalid. */
328	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
329	/** Longmode ES.Base invalid. */
330	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
331	/** SYSENTER ESP is not canonical. */
332	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
333	/** SYSENTER EIP is not canonical. */
334	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
335	/** PAT MSR invalid. */
336	#define VMX_IGS_PAT_MSR_INVALID 578
337	/** PAT MSR reserved bits not set to 0. */
338	#define VMX_IGS_PAT_MSR_RESERVED 579
339	/** GDTR.Base is not canonical. */
340	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
341	/** IDTR.Base is not canonical. */
342	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
343	/** GDTR.Limit invalid. */
344	#define VMX_IGS_GDTR_LIMIT_INVALID 582
345	/** IDTR.Limit invalid. */
346	#define VMX_IGS_IDTR_LIMIT_INVALID 583
347	/** Longmode RIP is invalid. */
348	#define VMX_IGS_LONGMODE_RIP_INVALID 584
349	/** RFLAGS reserved bits not set to 0. */
350	#define VMX_IGS_RFLAGS_RESERVED 585
351	/** RFLAGS RA1 reserved bits not set to 1. */
352	#define VMX_IGS_RFLAGS_RESERVED1 586
353	/** RFLAGS.VM (V86 mode) invalid. */
354	#define VMX_IGS_RFLAGS_VM_INVALID 587
355	/** RFLAGS.IF invalid. */
356	#define VMX_IGS_RFLAGS_IF_INVALID 588
357	/** Activity state invalid. */
358	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
359	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
360	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
361	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
362	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
363	/** Activity state SIPI WAIT invalid. */
364	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
365	/** Interruptibility state reserved bits not set to 0. */
366	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
367	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
368	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
369	/** Interruptibility state block-by-STI invalid for EFLAGS. */
370	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
371	/** Interruptibility state invalid while trying to deliver external
372	* interrupt. */
373	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
374	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
375	* NMI. */
376	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
377	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
378	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
379	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
380	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
381	/** Interruptibility state block-by-STI (maybe) invalid when trying to
382	* deliver an NMI. */
383	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
384	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
385	* active. */
386	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
387	/** Pending debug exceptions reserved bits not set to 0. */
388	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
389	/** Longmode pending debug exceptions reserved bits not set to 0. */
390	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
391	/** Pending debug exceptions.BS bit is not set when it should be. */
392	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
393	/** Pending debug exceptions.BS bit is not clear when it should be. */
394	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
395	/** VMCS link pointer reserved bits not set to 0. */
396	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
397	/** TR cannot index into LDT, TI bit MBZ. */
398	#define VMX_IGS_TR_TI_INVALID 607
399	/** LDTR cannot index into LDT. TI bit MBZ. */
400	#define VMX_IGS_LDTR_TI_INVALID 608
401	/** TR.Base is not canonical. */
402	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
403	/** FS.Base is not canonical. */
404	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
405	/** GS.Base is not canonical. */
406	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
407	/** LDTR.Base is not canonical. */
408	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
409	/** TR is unusable. */
410	#define VMX_IGS_TR_ATTR_UNUSABLE 613
411	/** TR.Attr.S bit invalid. */
412	#define VMX_IGS_TR_ATTR_S_INVALID 614
413	/** TR is not present. */
414	#define VMX_IGS_TR_ATTR_P_INVALID 615
415	/** TR.Attr reserved bits not set to 0. */
416	#define VMX_IGS_TR_ATTR_RESERVED 616
417	/** TR.Attr.G bit invalid. */
418	#define VMX_IGS_TR_ATTR_G_INVALID 617
419	/** Longmode TR.Attr.Type invalid. */
420	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
421	/** TR.Attr.Type invalid. */
422	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
423	/** CS.Attr.S invalid. */
424	#define VMX_IGS_CS_ATTR_S_INVALID 620
425	/** CS.Attr.DPL invalid. */
426	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
427	/** PAE PDPTE reserved bits not set to 0. */
428	#define VMX_IGS_PAE_PDPTE_RESERVED 623
429	/** @} */
430
431	/** @name VMX VMCS-Read cache indices.
432	* @{
433	*/
434	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
435	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
436	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
437	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
438	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
439	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
440	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
441	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
442	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
443	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
444	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
445	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
446	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
447	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
448	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
449	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
450	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
451	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
452	/** @} */
453
454	/** @name VMX EPT paging structures
455	* @{
456	*/
457
458	/**
459	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
460	*/
461	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
462
463	/**
464	* EPT Page Directory Pointer Entry. Bit view.
465	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
466	* this did cause trouble with one compiler/version).
467	*/
468	typedef struct EPTPML4EBITS
469	{
470	/** Present bit. */
471	uint64_t u1Present : 1;
472	/** Writable bit. */
473	uint64_t u1Write : 1;
474	/** Executable bit. */
475	uint64_t u1Execute : 1;
476	/** Reserved (must be 0). */
477	uint64_t u5Reserved : 5;
478	/** Available for software. */
479	uint64_t u4Available : 4;
480	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
481	uint64_t u40PhysAddr : 40;
482	/** Available for software. */
483	uint64_t u12Available : 12;
484	} EPTPML4EBITS;
485	AssertCompileSize(EPTPML4EBITS, 8);
486
487	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
488	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
489	/** The page shift to get the PML4 index. */
490	#define EPT_PML4_SHIFT X86_PML4_SHIFT
491	/** The PML4 index mask (apply to a shifted page address). */
492	#define EPT_PML4_MASK X86_PML4_MASK
493
494	/**
495	* EPT PML4E.
496	*/
497	typedef union EPTPML4E
498	{
499	/** Normal view. */
500	EPTPML4EBITS n;
501	/** Unsigned integer view. */
502	X86PGPAEUINT u;
503	/** 64 bit unsigned integer view. */
504	uint64_t au64[1];
505	/** 32 bit unsigned integer view. */
506	uint32_t au32[2];
507	} EPTPML4E;
508	AssertCompileSize(EPTPML4E, 8);
509	/** Pointer to a PML4 table entry. */
510	typedef EPTPML4E *PEPTPML4E;
511	/** Pointer to a const PML4 table entry. */
512	typedef const EPTPML4E *PCEPTPML4E;
513
514	/**
515	* EPT PML4 Table.
516	*/
517	typedef struct EPTPML4
518	{
519	EPTPML4E a[EPT_PG_ENTRIES];
520	} EPTPML4;
521	AssertCompileSize(EPTPML4, 0x1000);
522	/** Pointer to an EPT PML4 Table. */
523	typedef EPTPML4 *PEPTPML4;
524	/** Pointer to a const EPT PML4 Table. */
525	typedef const EPTPML4 *PCEPTPML4;
526
527	/**
528	* EPT Page Directory Pointer Entry. Bit view.
529	*/
530	typedef struct EPTPDPTEBITS
531	{
532	/** Present bit. */
533	uint64_t u1Present : 1;
534	/** Writable bit. */
535	uint64_t u1Write : 1;
536	/** Executable bit. */
537	uint64_t u1Execute : 1;
538	/** Reserved (must be 0). */
539	uint64_t u5Reserved : 5;
540	/** Available for software. */
541	uint64_t u4Available : 4;
542	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
543	uint64_t u40PhysAddr : 40;
544	/** Available for software. */
545	uint64_t u12Available : 12;
546	} EPTPDPTEBITS;
547	AssertCompileSize(EPTPDPTEBITS, 8);
548
549	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
550	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
551	/** The page shift to get the PDPT index. */
552	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
553	/** The PDPT index mask (apply to a shifted page address). */
554	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
555
556	/**
557	* EPT Page Directory Pointer.
558	*/
559	typedef union EPTPDPTE
560	{
561	/** Normal view. */
562	EPTPDPTEBITS n;
563	/** Unsigned integer view. */
564	X86PGPAEUINT u;
565	/** 64 bit unsigned integer view. */
566	uint64_t au64[1];
567	/** 32 bit unsigned integer view. */
568	uint32_t au32[2];
569	} EPTPDPTE;
570	AssertCompileSize(EPTPDPTE, 8);
571	/** Pointer to an EPT Page Directory Pointer Entry. */
572	typedef EPTPDPTE *PEPTPDPTE;
573	/** Pointer to a const EPT Page Directory Pointer Entry. */
574	typedef const EPTPDPTE *PCEPTPDPTE;
575
576	/**
577	* EPT Page Directory Pointer Table.
578	*/
579	typedef struct EPTPDPT
580	{
581	EPTPDPTE a[EPT_PG_ENTRIES];
582	} EPTPDPT;
583	AssertCompileSize(EPTPDPT, 0x1000);
584	/** Pointer to an EPT Page Directory Pointer Table. */
585	typedef EPTPDPT *PEPTPDPT;
586	/** Pointer to a const EPT Page Directory Pointer Table. */
587	typedef const EPTPDPT *PCEPTPDPT;
588
589	/**
590	* EPT Page Directory Table Entry. Bit view.
591	*/
592	typedef struct EPTPDEBITS
593	{
594	/** Present bit. */
595	uint64_t u1Present : 1;
596	/** Writable bit. */
597	uint64_t u1Write : 1;
598	/** Executable bit. */
599	uint64_t u1Execute : 1;
600	/** Reserved (must be 0). */
601	uint64_t u4Reserved : 4;
602	/** Big page (must be 0 here). */
603	uint64_t u1Size : 1;
604	/** Available for software. */
605	uint64_t u4Available : 4;
606	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
607	uint64_t u40PhysAddr : 40;
608	/** Available for software. */
609	uint64_t u12Available : 12;
610	} EPTPDEBITS;
611	AssertCompileSize(EPTPDEBITS, 8);
612
613	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
614	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
615	/** The page shift to get the PD index. */
616	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
617	/** The PD index mask (apply to a shifted page address). */
618	#define EPT_PD_MASK X86_PD_PAE_MASK
619
620	/**
621	* EPT 2MB Page Directory Table Entry. Bit view.
622	*/
623	typedef struct EPTPDE2MBITS
624	{
625	/** Present bit. */
626	uint64_t u1Present : 1;
627	/** Writable bit. */
628	uint64_t u1Write : 1;
629	/** Executable bit. */
630	uint64_t u1Execute : 1;
631	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
632	uint64_t u3EMT : 3;
633	/** Ignore PAT memory type */
634	uint64_t u1IgnorePAT : 1;
635	/** Big page (must be 1 here). */
636	uint64_t u1Size : 1;
637	/** Available for software. */
638	uint64_t u4Available : 4;
639	/** Reserved (must be 0). */
640	uint64_t u9Reserved : 9;
641	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
642	uint64_t u31PhysAddr : 31;
643	/** Available for software. */
644	uint64_t u12Available : 12;
645	} EPTPDE2MBITS;
646	AssertCompileSize(EPTPDE2MBITS, 8);
647
648	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
649	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
650
651	/**
652	* EPT Page Directory Table Entry.
653	*/
654	typedef union EPTPDE
655	{
656	/** Normal view. */
657	EPTPDEBITS n;
658	/** 2MB view (big). */
659	EPTPDE2MBITS b;
660	/** Unsigned integer view. */
661	X86PGPAEUINT u;
662	/** 64 bit unsigned integer view. */
663	uint64_t au64[1];
664	/** 32 bit unsigned integer view. */
665	uint32_t au32[2];
666	} EPTPDE;
667	AssertCompileSize(EPTPDE, 8);
668	/** Pointer to an EPT Page Directory Table Entry. */
669	typedef EPTPDE *PEPTPDE;
670	/** Pointer to a const EPT Page Directory Table Entry. */
671	typedef const EPTPDE *PCEPTPDE;
672
673	/**
674	* EPT Page Directory Table.
675	*/
676	typedef struct EPTPD
677	{
678	EPTPDE a[EPT_PG_ENTRIES];
679	} EPTPD;
680	AssertCompileSize(EPTPD, 0x1000);
681	/** Pointer to an EPT Page Directory Table. */
682	typedef EPTPD *PEPTPD;
683	/** Pointer to a const EPT Page Directory Table. */
684	typedef const EPTPD *PCEPTPD;
685
686	/**
687	* EPT Page Table Entry. Bit view.
688	*/
689	typedef struct EPTPTEBITS
690	{
691	/** 0 - Present bit.
692	* @remarks This is a convenience "misnomer". The bit actually indicates read access
693	* and the CPU will consider an entry with any of the first three bits set
694	* as present. Since all our valid entries will have this bit set, it can
695	* be used as a present indicator and allow some code sharing. */
696	uint64_t u1Present : 1;
697	/** 1 - Writable bit. */
698	uint64_t u1Write : 1;
699	/** 2 - Executable bit. */
700	uint64_t u1Execute : 1;
701	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
702	uint64_t u3EMT : 3;
703	/** 6 - Ignore PAT memory type */
704	uint64_t u1IgnorePAT : 1;
705	/** 11:7 - Available for software. */
706	uint64_t u5Available : 5;
707	/** 51:12 - Physical address of page. Restricted by maximum physical
708	* address width of the cpu. */
709	uint64_t u40PhysAddr : 40;
710	/** 63:52 - Available for software. */
711	uint64_t u12Available : 12;
712	} EPTPTEBITS;
713	AssertCompileSize(EPTPTEBITS, 8);
714
715	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
716	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
717	/** The page shift to get the EPT PTE index. */
718	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
719	/** The EPT PT index mask (apply to a shifted page address). */
720	#define EPT_PT_MASK X86_PT_PAE_MASK
721
722	/**
723	* EPT Page Table Entry.
724	*/
725	typedef union EPTPTE
726	{
727	/** Normal view. */
728	EPTPTEBITS n;
729	/** Unsigned integer view. */
730	X86PGPAEUINT u;
731	/** 64 bit unsigned integer view. */
732	uint64_t au64[1];
733	/** 32 bit unsigned integer view. */
734	uint32_t au32[2];
735	} EPTPTE;
736	AssertCompileSize(EPTPTE, 8);
737	/** Pointer to an EPT Page Directory Table Entry. */
738	typedef EPTPTE *PEPTPTE;
739	/** Pointer to a const EPT Page Directory Table Entry. */
740	typedef const EPTPTE *PCEPTPTE;
741
742	/**
743	* EPT Page Table.
744	*/
745	typedef struct EPTPT
746	{
747	EPTPTE a[EPT_PG_ENTRIES];
748	} EPTPT;
749	AssertCompileSize(EPTPT, 0x1000);
750	/** Pointer to an extended page table. */
751	typedef EPTPT *PEPTPT;
752	/** Pointer to a const extended table. */
753	typedef const EPTPT *PCEPTPT;
754
755	/** @} */
756
757	/**
758	* VMX VPID flush types.
759	* @note Valid enum members are in accordance to the VT-x spec.
760	*/
761	typedef enum
762	{
763	/** Invalidate a specific page. */
764	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
765	/** Invalidate one context (specific VPID). */
766	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
767	/** Invalidate all contexts (all VPIDs). */
768	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
769	/** Invalidate a single VPID context retaining global mappings. */
770	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
771	/** Unsupported by VirtualBox. */
772	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
773	/** Unsupported by CPU. */
774	VMXTLBFLUSHVPID_NONE = 0xbad1
775	} VMXTLBFLUSHVPID;
776	AssertCompileSize(VMXTLBFLUSHVPID, 4);
777
778	/**
779	* VMX EPT flush types.
780	* @note Valid enums values are in accordance to the VT-x spec.
781	*/
782	typedef enum
783	{
784	/** Invalidate one context (specific EPT). */
785	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
786	/* Invalidate all contexts (all EPTs) */
787	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
788	/** Unsupported by VirtualBox. */
789	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
790	/** Unsupported by CPU. */
791	VMXTLBFLUSHEPT_NONE = 0xbad1
792	} VMXTLBFLUSHEPT;
793	AssertCompileSize(VMXTLBFLUSHEPT, 4);
794
795	/**
796	* VMX Posted Interrupt Descriptor.
797	* In accordance to the VT-x spec.
798	*/
799	typedef struct VMXPOSTEDINTRDESC
800	{
801	uint32_t aVectorBitmap[8];
802	uint32_t fOutstandingNotification : 1;
803	uint32_t uReserved0 : 31;
804	uint8_t au8Reserved0[28];
805	} VMXPOSTEDINTRDESC;
806	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
807	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
808	/** Pointer to a posted interrupt descriptor. */
809	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
810	/** Pointer to a const posted interrupt descriptor. */
811	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
812
813	/**
814	* VMX VMCS revision identifier.
815	*/
816	typedef union
817	{
818	struct
819	{
820	/** Revision identifier. */
821	uint32_t u31RevisionId : 31;
822	/** Whether this is a shadow VMCS. */
823	uint32_t fIsShadowVmcs : 1;
824	} n;
825	/* The unsigned integer view. */
826	uint32_t u;
827	} VMXVMCSREVID;
828	AssertCompileSize(VMXVMCSREVID, 4);
829	/** Pointer to the VMXVMCSREVID union. */
830	typedef VMXVMCSREVID *PVMXVMCSREVID;
831	/** Pointer to a const VMXVVMCSREVID union. */
832	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
833
834	/**
835	* VMX VM-exit instruction information.
836	*/
837	typedef union
838	{
839	/** Plain unsigned int representation. */
840	uint32_t u;
841
842	/** INS and OUTS information. */
843	struct
844	{
845	uint32_t u7Reserved0 : 7;
846	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
847	uint32_t u3AddrSize : 3;
848	uint32_t u5Reserved1 : 5;
849	/** The segment register (X86_SREG_XXX). */
850	uint32_t iSegReg : 3;
851	uint32_t uReserved2 : 14;
852	} StrIo;
853
854	struct
855	{
856	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
857	uint32_t u2Scaling : 2;
858	uint32_t u5Undef0 : 5;
859	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
860	uint32_t u3AddrSize : 3;
861	/** Cleared to 0. */
862	uint32_t u1Cleared0 : 1;
863	uint32_t u4Undef0 : 4;
864	/** The segment register (X86_SREG_XXX). */
865	uint32_t iSegReg : 3;
866	/** The index register (X86_GREG_XXX). */
867	uint32_t iIdxReg : 4;
868	/** Set if index register is invalid. */
869	uint32_t fIdxRegInvalid : 1;
870	/** The base register (X86_GREG_XXX). */
871	uint32_t iBaseReg : 4;
872	/** Set if base register is invalid. */
873	uint32_t fBaseRegInvalid : 1;
874	/** Register 2 (X86_GREG_XXX). */
875	uint32_t iReg2 : 4;
876	} Inv;
877
878	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
879	struct
880	{
881	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
882	uint32_t u2Scaling : 2;
883	uint32_t u5Reserved0 : 5;
884	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
885	uint32_t u3AddrSize : 3;
886	/** Cleared to 0. */
887	uint32_t u1Cleared0 : 1;
888	uint32_t u4Reserved0 : 4;
889	/** The segment register (X86_SREG_XXX). */
890	uint32_t iSegReg : 3;
891	/** The index register (X86_GREG_XXX). */
892	uint32_t iIdxReg : 4;
893	/** Set if index register is invalid. */
894	uint32_t fIdxRegInvalid : 1;
895	/** The base register (X86_GREG_XXX). */
896	uint32_t iBaseReg : 4;
897	/** Set if base register is invalid. */
898	uint32_t fBaseRegInvalid : 1;
899	/** Register 2 (X86_GREG_XXX). */
900	uint32_t iReg2 : 4;
901	} VmxXsave;
902
903	/** LIDT, LGDT, SIDT, SGDT information. */
904	struct
905	{
906	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
907	uint32_t u2Scaling : 2;
908	uint32_t u5Undef0 : 5;
909	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
910	uint32_t u3AddrSize : 3;
911	/** Always cleared to 0. */
912	uint32_t u1Cleared0 : 1;
913	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
914	uint32_t uOperandSize : 1;
915	uint32_t u3Undef0 : 3;
916	/** The segment register (X86_SREG_XXX). */
917	uint32_t iSegReg : 3;
918	/** The index register (X86_GREG_XXX). */
919	uint32_t iIdxReg : 4;
920	/** Set if index register is invalid. */
921	uint32_t fIdxRegInvalid : 1;
922	/** The base register (X86_GREG_XXX). */
923	uint32_t iBaseReg : 4;
924	/** Set if base register is invalid. */
925	uint32_t fBaseRegInvalid : 1;
926	/** Instruction identity (VMX_INSTR_ID_XXX). */
927	uint32_t u2InstrId : 2;
928	uint32_t u2Undef0 : 2;
929	} GdtIdt;
930
931	/** LLDT, LTR, SLDT, STR information. */
932	struct
933	{
934	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
935	uint32_t u2Scaling : 2;
936	uint32_t u1Undef0 : 1;
937	/** Register 1 (X86_GREG_XXX). */
938	uint32_t iReg1 : 4;
939	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
940	uint32_t u3AddrSize : 3;
941	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
942	uint32_t fIsRegOperand : 1;
943	uint32_t u4Undef0 : 4;
944	/** The segment register (X86_SREG_XXX). */
945	uint32_t iSegReg : 3;
946	/** The index register (X86_GREG_XXX). */
947	uint32_t iIdxReg : 4;
948	/** Set if index register is invalid. */
949	uint32_t fIdxRegInvalid : 1;
950	/** The base register (X86_GREG_XXX). */
951	uint32_t iBaseReg : 4;
952	/** Set if base register is invalid. */
953	uint32_t fBaseRegInvalid : 1;
954	/** Instruction identity (VMX_INSTR_ID_XXX). */
955	uint32_t u2InstrId : 2;
956	uint32_t u2Undef0 : 2;
957	} LdtTr;
958
959	/** RDRAND, RDSEED information. */
960	struct
961	{
962	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
963	uint32_t u2Undef0 : 2;
964	/** Destination register (X86_GREG_XXX). */
965	uint32_t iReg1 : 4;
966	uint32_t u4Undef0 : 4;
967	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
968	uint32_t u2OperandSize : 2;
969	uint32_t u19Def0 : 20;
970	} RdrandRdseed;
971
972	struct
973	{
974	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
975	uint32_t u2Scaling : 2;
976	uint32_t u1Undef0 : 1;
977	/** Register 1 (X86_GREG_XXX). */
978	uint32_t iReg1 : 4;
979	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
980	uint32_t u3AddrSize : 3;
981	/** Memory or register operand. */
982	uint32_t fIsRegOperand : 1;
983	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
984	uint32_t u4Undef0 : 4;
985	/** The segment register (X86_SREG_XXX). */
986	uint32_t iSegReg : 3;
987	/** The index register (X86_GREG_XXX). */
988	uint32_t iIdxReg : 4;
989	/** Set if index register is invalid. */
990	uint32_t fIdxRegInvalid : 1;
991	/** The base register (X86_GREG_XXX). */
992	uint32_t iBaseReg : 4;
993	/** Set if base register is invalid. */
994	uint32_t fBaseRegInvalid : 1;
995	/** Register 2 (X86_GREG_XXX). */
996	uint32_t iReg2 : 4;
997	} VmreadVmwrite;
998
999	/** This is a combination field of all instruction information. Note! Not all field
1000	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1001	* specialized fields are overwritten by their generic counterparts (e.g. no
1002	* instruction identity field). */
1003	struct
1004	{
1005	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1006	uint32_t u2Scaling : 2;
1007	uint32_t u1Undef0 : 1;
1008	/** Register 1 (X86_GREG_XXX). */
1009	uint32_t iReg1 : 4;
1010	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1011	uint32_t u3AddrSize : 3;
1012	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1013	uint32_t fIsRegOperand : 1;
1014	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1015	uint32_t uOperandSize : 2;
1016	uint32_t u2Undef0 : 2;
1017	/** The segment register (X86_SREG_XXX). */
1018	uint32_t iSegReg : 3;
1019	/** The index register (X86_GREG_XXX). */
1020	uint32_t iIdxReg : 4;
1021	/** Set if index register is invalid. */
1022	uint32_t fIdxRegInvalid : 1;
1023	/** The base register (X86_GREG_XXX). */
1024	uint32_t iBaseReg : 4;
1025	/** Set if base register is invalid. */
1026	uint32_t fBaseRegInvalid : 1;
1027	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1028	uint32_t iReg2 : 4;
1029	} All;
1030	} VMXEXITINSTRINFO;
1031	AssertCompileSize(VMXEXITINSTRINFO, 4);
1032	/** Pointer to a VMX VM-exit instruction info. struct. */
1033	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1034	/** Pointer to a const VMX VM-exit instruction info. struct. */
1035	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1036
1037	/**
1038	* VMX MSR autoload/store element.
1039	* In accordance to the VT-x spec.
1040	*/
1041	typedef struct VMXAUTOMSR
1042	{
1043	/** The MSR Id. */
1044	uint32_t u32Msr;
1045	/** Reserved (MBZ). */
1046	uint32_t u32Reserved;
1047	/** The MSR value. */
1048	uint64_t u64Value;
1049	} VMXAUTOMSR;
1050	AssertCompileSize(VMXAUTOMSR, 16);
1051	/** Pointer to an MSR load/store element. */
1052	typedef VMXAUTOMSR *PVMXAUTOMSR;
1053	/** Pointer to a const MSR load/store element. */
1054	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1055
1056	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1057	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1058
1059	/**
1060	* VMX tagged-TLB flush types.
1061	*/
1062	typedef enum
1063	{
1064	VMXTLBFLUSHTYPE_EPT,
1065	VMXTLBFLUSHTYPE_VPID,
1066	VMXTLBFLUSHTYPE_EPT_VPID,
1067	VMXTLBFLUSHTYPE_NONE
1068	} VMXTLBFLUSHTYPE;
1069	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1070	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1071	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1072	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1073
1074	/**
1075	* VMX controls MSR.
1076	*/
1077	typedef union
1078	{
1079	struct
1080	{
1081	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1082	uint32_t disallowed0;
1083	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1084	* controls. */
1085	uint32_t allowed1;
1086	} n;
1087	uint64_t u;
1088	} VMXCTLSMSR;
1089	AssertCompileSize(VMXCTLSMSR, 8);
1090	/** Pointer to a VMXCTLSMSR union. */
1091	typedef VMXCTLSMSR *PVMXCTLSMSR;
1092	/** Pointer to a const VMXCTLSMSR union. */
1093	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1094
1095	/**
1096	* VMX MSRs.
1097	* @remarks Although treated as a plain-old data (POD) in several places, please
1098	* update HMVmxGetHostMsr() if new MSRs are added here.
1099	*/
1100	typedef struct VMXMSRS
1101	{
1102	uint64_t u64FeatCtrl;
1103	uint64_t u64Basic;
1104	VMXCTLSMSR PinCtls;
1105	VMXCTLSMSR ProcCtls;
1106	VMXCTLSMSR ProcCtls2;
1107	VMXCTLSMSR ExitCtls;
1108	VMXCTLSMSR EntryCtls;
1109	VMXCTLSMSR TruePinCtls;
1110	VMXCTLSMSR TrueProcCtls;
1111	VMXCTLSMSR TrueEntryCtls;
1112	VMXCTLSMSR TrueExitCtls;
1113	uint64_t u64Misc;
1114	uint64_t u64Cr0Fixed0;
1115	uint64_t u64Cr0Fixed1;
1116	uint64_t u64Cr4Fixed0;
1117	uint64_t u64Cr4Fixed1;
1118	uint64_t u64VmcsEnum;
1119	uint64_t u64VmFunc;
1120	uint64_t u64EptVpidCaps;
1121	uint64_t a_u64Reserved[2];
1122	} VMXMSRS;
1123	AssertCompileSizeAlignment(VMXMSRS, 8);
1124	AssertCompileSize(VMXMSRS, 168);
1125	/** Pointer to a VMXMSRS struct. */
1126	typedef VMXMSRS *PVMXMSRS;
1127	/** Pointer to a const VMXMSRS struct. */
1128	typedef const VMXMSRS *PCVMXMSRS;
1129
1130
1131	/** @name VMX Basic Exit Reasons.
1132	* @{
1133	*/
1134	/** -1 Invalid exit code */
1135	#define VMX_EXIT_INVALID (-1)
1136	/** 0 Exception or non-maskable interrupt (NMI). */
1137	#define VMX_EXIT_XCPT_OR_NMI 0
1138	/** 1 External interrupt. */
1139	#define VMX_EXIT_EXT_INT 1
1140	/** 2 Triple fault. */
1141	#define VMX_EXIT_TRIPLE_FAULT 2
1142	/** 3 INIT signal. */
1143	#define VMX_EXIT_INIT_SIGNAL 3
1144	/** 4 Start-up IPI (SIPI). */
1145	#define VMX_EXIT_SIPI 4
1146	/** 5 I/O system-management interrupt (SMI). */
1147	#define VMX_EXIT_IO_SMI 5
1148	/** 6 Other SMI. */
1149	#define VMX_EXIT_SMI 6
1150	/** 7 Interrupt window exiting. */
1151	#define VMX_EXIT_INT_WINDOW 7
1152	/** 8 NMI window exiting. */
1153	#define VMX_EXIT_NMI_WINDOW 8
1154	/** 9 Task switch. */
1155	#define VMX_EXIT_TASK_SWITCH 9
1156	/** 10 Guest software attempted to execute CPUID. */
1157	#define VMX_EXIT_CPUID 10
1158	/** 11 Guest software attempted to execute GETSEC. */
1159	#define VMX_EXIT_GETSEC 11
1160	/** 12 Guest software attempted to execute HLT. */
1161	#define VMX_EXIT_HLT 12
1162	/** 13 Guest software attempted to execute INVD. */
1163	#define VMX_EXIT_INVD 13
1164	/** 14 Guest software attempted to execute INVLPG. */
1165	#define VMX_EXIT_INVLPG 14
1166	/** 15 Guest software attempted to execute RDPMC. */
1167	#define VMX_EXIT_RDPMC 15
1168	/** 16 Guest software attempted to execute RDTSC. */
1169	#define VMX_EXIT_RDTSC 16
1170	/** 17 Guest software attempted to execute RSM in SMM. */
1171	#define VMX_EXIT_RSM 17
1172	/** 18 Guest software executed VMCALL. */
1173	#define VMX_EXIT_VMCALL 18
1174	/** 19 Guest software executed VMCLEAR. */
1175	#define VMX_EXIT_VMCLEAR 19
1176	/** 20 Guest software executed VMLAUNCH. */
1177	#define VMX_EXIT_VMLAUNCH 20
1178	/** 21 Guest software executed VMPTRLD. */
1179	#define VMX_EXIT_VMPTRLD 21
1180	/** 22 Guest software executed VMPTRST. */
1181	#define VMX_EXIT_VMPTRST 22
1182	/** 23 Guest software executed VMREAD. */
1183	#define VMX_EXIT_VMREAD 23
1184	/** 24 Guest software executed VMRESUME. */
1185	#define VMX_EXIT_VMRESUME 24
1186	/** 25 Guest software executed VMWRITE. */
1187	#define VMX_EXIT_VMWRITE 25
1188	/** 26 Guest software executed VMXOFF. */
1189	#define VMX_EXIT_VMXOFF 26
1190	/** 27 Guest software executed VMXON. */
1191	#define VMX_EXIT_VMXON 27
1192	/** 28 Control-register accesses. */
1193	#define VMX_EXIT_MOV_CRX 28
1194	/** 29 Debug-register accesses. */
1195	#define VMX_EXIT_MOV_DRX 29
1196	/** 30 I/O instruction. */
1197	#define VMX_EXIT_IO_INSTR 30
1198	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1199	#define VMX_EXIT_RDMSR 31
1200	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1201	#define VMX_EXIT_WRMSR 32
1202	/** 33 VM-entry failure due to invalid guest state. */
1203	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1204	/** 34 VM-entry failure due to MSR loading. */
1205	#define VMX_EXIT_ERR_MSR_LOAD 34
1206	/** 36 Guest software executed MWAIT. */
1207	#define VMX_EXIT_MWAIT 36
1208	/** 37 VM-exit due to monitor trap flag. */
1209	#define VMX_EXIT_MTF 37
1210	/** 39 Guest software attempted to execute MONITOR. */
1211	#define VMX_EXIT_MONITOR 39
1212	/** 40 Guest software attempted to execute PAUSE. */
1213	#define VMX_EXIT_PAUSE 40
1214	/** 41 VM-entry failure due to machine-check. */
1215	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1216	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1217	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1218	/** 44 APIC access. Guest software attempted to access memory at a physical
1219	* address on the APIC-access page. */
1220	#define VMX_EXIT_APIC_ACCESS 44
1221	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1222	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1223	#define VMX_EXIT_VIRTUALIZED_EOI 45
1224	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1225	* SGDT, or SIDT. */
1226	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1227	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1228	* SLDT, or STR. */
1229	#define VMX_EXIT_LDTR_TR_ACCESS 47
1230	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1231	* was disallowed by the configuration of the EPT paging structures. */
1232	#define VMX_EXIT_EPT_VIOLATION 48
1233	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1234	* address encountered a misconfigured EPT paging-structure entry. */
1235	#define VMX_EXIT_EPT_MISCONFIG 49
1236	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1237	#define VMX_EXIT_INVEPT 50
1238	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1239	#define VMX_EXIT_RDTSCP 51
1240	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1241	#define VMX_EXIT_PREEMPT_TIMER 52
1242	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1243	#define VMX_EXIT_INVVPID 53
1244	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1245	#define VMX_EXIT_WBINVD 54
1246	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1247	#define VMX_EXIT_XSETBV 55
1248	/** 56 APIC write. Guest completed write to virtual-APIC. */
1249	#define VMX_EXIT_APIC_WRITE 56
1250	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1251	#define VMX_EXIT_RDRAND 57
1252	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1253	#define VMX_EXIT_INVPCID 58
1254	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1255	#define VMX_EXIT_VMFUNC 59
1256	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1257	#define VMX_EXIT_ENCLS 60
1258	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1259	* enabled. */
1260	#define VMX_EXIT_RDSEED 61
1261	/** 62 - Page-modification log full. */
1262	#define VMX_EXIT_PML_FULL 62
1263	/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
1264	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1265	#define VMX_EXIT_XSAVES 63
1266	/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
1267	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1268	#define VMX_EXIT_XRSTORS 64
1269	/** The maximum exit value (inclusive). */
1270	#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
1271	/** @} */
1272
1273
1274	/** @name VM Instruction Errors.
1275	* See Intel spec. "30.4 VM Instruction Error Numbers"
1276	* @{
1277	*/
1278	typedef enum
1279	{
1280	/** VMCALL executed in VMX root operation. */
1281	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1282	/** VMCLEAR with invalid physical address. */
1283	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1284	/** VMCLEAR with VMXON pointer. */
1285	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1286	/** VMLAUNCH with non-clear VMCS. */
1287	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1288	/** VMRESUME with non-launched VMCS. */
1289	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1290	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1291	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1292	/** VM-entry with invalid control field(s). */
1293	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1294	/** VM-entry with invalid host-state field(s). */
1295	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1296	/** VMPTRLD with invalid physical address. */
1297	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1298	/** VMPTRLD with VMXON pointer. */
1299	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1300	/** VMPTRLD with incorrect VMCS revision identifier. */
1301	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1302	/** VMREAD from unsupported VMCS component. */
1303	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1304	/** VMWRITE to unsupported VMCS component. */
1305	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1306	/** VMWRITE to read-only VMCS component. */
1307	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1308	/** VMXON executed in VMX root operation. */
1309	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1310	/** VM-entry with invalid executive-VMCS pointer. */
1311	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1312	/** VM-entry with non-launched executive VMCS. */
1313	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1314	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1315	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1316	/** VMCALL with non-clear VMCS. */
1317	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1318	/** VMCALL with invalid VM-exit control fields. */
1319	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1320	/** VMCALL with incorrect MSEG revision identifier. */
1321	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1322	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1323	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1324	/** VMCALL with invalid SMM-monitor features. */
1325	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1326	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1327	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1328	/** VM-entry with events blocked by MOV SS. */
1329	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1330	/** Invalid operand to INVEPT/INVVPID. */
1331	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1332	} VMXINSTRERR;
1333	/** @} */
1334
1335
1336	/** @name VMX MSR - Basic VMX information.
1337	* @{
1338	*/
1339	/** VMCS (and related regions) memory type - Uncacheable. */
1340	#define VMX_BASIC_MEM_TYPE_UC 0
1341	/** VMCS (and related regions) memory type - Write back. */
1342	#define VMX_BASIC_MEM_TYPE_WB 6
1343
1344	/** Bit fields for MSR_IA32_VMX_BASIC. */
1345	/** VMCS revision identifier used by the processor. */
1346	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1347	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1348	/** Bit 31 is reserved and RAZ. */
1349	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1350	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1351	/** VMCS size in bytes. */
1352	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1353	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1354	/** Bits 45:47 are reserved. */
1355	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1356	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1357	/** Width of physical addresses used for the VMCS and associated memory regions
1358	* (always 0 on CPUs that support Intel 64 architecture). */
1359	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1360	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1361	/** Dual-monitor treatment of SMI and SMM supported. */
1362	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1363	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1364	/** Memory type that must be used for the VMCS and associated memory regions. */
1365	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1366	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1367	/** VM-exit instruction information for INS/OUTS. */
1368	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1369	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1370	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1371	* bits in VMX control MSRs. */
1372	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1373	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1374	/** Bits 56:63 are reserved and RAZ. */
1375	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 56
1376	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xff00000000000000)
1377	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1378	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1379	VMCS_INS_OUTS, TRUE_CTLS, RSVD_56_63));
1380	/** @} */
1381
1382
1383	/** @name VMX MSR - Miscellaneous data.
1384	* Bit fields for MSR_IA32_VMX_MISC.
1385	* @{
1386	*/
1387	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1388	#define VMX_MISC_EXIT_STORE_EFER_LMA RT_BIT(5)
1389	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1390	* VMWRITE cannot modify read-only VM-exit information fields. */
1391	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1392	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1393	* instructions. */
1394	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1395	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1396	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1397	/** Maximum CR3-target count supported by the CPU. */
1398	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1399	/** Relationship between the preemption timer and tsc. */
1400	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1401	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1402	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1403	#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_SHIFT 5
1404	#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1405	/** Activity states supported by the implementation. */
1406	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1407	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1408	/** Bits 9:13 is reserved and RAZ. */
1409	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1410	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1411	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1412	#define VMX_BF_MISC_PT_SHIFT 14
1413	#define VMX_BF_MISC_PT_MASK UINT64_C(0x0000000000004000)
1414	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1415	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1416	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1417	/** Number of CR3 target values supported by the processor. (0-256) */
1418	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1419	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1420	/** Maximum number of MSRs in the VMCS. */
1421	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1422	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1423	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1424	* SMIs. */
1425	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1426	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1427	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1428	* VMWRITE cannot modify read-only VM-exit information fields. */
1429	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1430	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1431	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1432	* instructions. */
1433	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1434	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1435	/** Bit 31 is reserved and RAZ. */
1436	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1437	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1438	/** 32-bit MSEG revision ID used by the processor. */
1439	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1440	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1441	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1442	(PREEMPT_TIMER_TSC, EXIT_STORE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, PT, SMM_READ_SMBASE_MSR,
1443	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1444	/** @} */
1445
1446	/** @name VMX MSR - VMCS enumeration.
1447	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1448	* @{
1449	*/
1450	/** Bit 0 is reserved and RAZ. */
1451	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1452	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1453	/** Highest index value used in VMCS field encoding. */
1454	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1455	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1456	/** Bit 10:63 is reserved and RAZ. */
1457	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1458	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1459	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1460	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1461	/** @} */
1462
1463
1464	/** @name VMX MSR - VM Functions.
1465	* Bit fields for MSR_IA32_VMX_VMFUNC.
1466	* @{
1467	*/
1468	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1469	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1470	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1471	/** Bits 1:63 are reserved and RAZ. */
1472	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1473	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1474	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1475	(EPTP_SWITCHING, RSVD_1_63));
1476	/** @} */
1477
1478
1479	/** @name VMX MSR - EPT/VPID capabilities.
1480	* @{
1481	*/
1482	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1483	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1484	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1485	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1486	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1487	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1488	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1489	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1490	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1491	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1492	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1493	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1494	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1495	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1496	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1497	/** @} */
1498
1499
1500	/** @name Extended Page Table Pointer (EPTP)
1501	* @{
1502	*/
1503	/** Uncachable EPT paging structure memory type. */
1504	#define VMX_EPT_MEMTYPE_UC 0
1505	/** Write-back EPT paging structure memory type. */
1506	#define VMX_EPT_MEMTYPE_WB 6
1507	/** Shift value to get the EPT page walk length (bits 5-3) */
1508	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1509	/** Mask value to get the EPT page walk length (bits 5-3) */
1510	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1511	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1512	* length) */
1513	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1514	/** @} */
1515
1516
1517	/** @name VMCS field encoding: 16-bit guest fields.
1518	* @{
1519	*/
1520	#define VMX_VMCS16_VPID 0x0000
1521	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1522	#define VMX_VMCS16_EPTP_INDEX 0x0004
1523	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1524	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1525	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1526	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1527	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1528	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1529	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1530	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1531	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1532	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1533	/** @} */
1534
1535
1536	/** @name VMCS field encoding: 16-bits host fields.
1537	* @{
1538	*/
1539	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1540	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1541	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1542	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1543	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1544	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1545	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1546	/** @} */
1547
1548
1549	/** @name VMCS field encoding: 64-bit control fields.
1550	* @{
1551	*/
1552	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1553	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1554	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1555	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1556	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1557	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1558	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1559	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1560	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1561	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1562	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1563	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1564	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1565	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1566	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1567	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1568	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1569	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1570	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1571	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1572	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1573	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1574	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1575	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1576	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1577	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1578	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1579	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1580	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1581	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1582	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1583	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1584	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1585	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1586	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1587	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1588	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1589	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1590	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1591	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1592	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1593	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1594	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1595	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1596	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1597	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1598	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1599	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1600	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1601	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1602	/** @} */
1603
1604
1605	/** @name VMCS field encoding: 64-bit read-only data fields.
1606	* @{
1607	*/
1608	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1609	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1610	/** @} */
1611
1612
1613	/** @name VMCS field encoding: 64-bit guest fields.
1614	* @{
1615	*/
1616	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1617	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1618	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1619	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1620	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1621	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1622	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1623	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1624	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1625	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1626	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1627	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1628	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1629	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1630	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1631	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1632	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1633	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1634	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1635	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1636	/** @} */
1637
1638
1639	/** @name VMCS field encoding: 64-bit host fields.
1640	* @{
1641	*/
1642	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1643	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1644	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1645	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1646	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1647	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1648	/** @} */
1649
1650
1651	/** @name VMCS field encoding: 32-bit control fields.
1652	* @{
1653	*/
1654	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1655	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1656	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1657	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1658	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1659	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1660	#define VMX_VMCS32_CTRL_EXIT 0x400c
1661	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1662	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1663	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1664	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1665	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1666	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1667	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1668	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1669	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1670	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1671	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1672	/** @} */
1673
1674
1675	/** @name VMCS field encoding: 32-bits read-only fields.
1676	* @{
1677	*/
1678	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1679	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1680	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1681	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1682	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1683	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1684	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1685	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1686	/** @} */
1687
1688
1689	/** @name VMCS field encoding: 32-bit guest-state fields.
1690	* @{
1691	*/
1692	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1693	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1694	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1695	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1696	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1697	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1698	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1699	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1700	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1701	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1702	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1703	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1704	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1705	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1706	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1707	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1708	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1709	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1710	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1711	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1712	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1713	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
1714	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1715	/** @} */
1716
1717
1718	/** @name VMCS field encoding: 32-bit host-state fields.
1719	* @{
1720	*/
1721	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1722	/** @} */
1723
1724
1725	/** @name Natural width control fields.
1726	* @{
1727	*/
1728	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1729	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1730	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1731	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1732	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1733	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1734	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1735	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
1736	/** @} */
1737
1738
1739	/** @name Natural width read-only data fields.
1740	* @{
1741	*/
1742	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1743	#define VMX_VMCS_RO_IO_RCX 0x6402
1744	#define VMX_VMCS_RO_IO_RSX 0x6404
1745	#define VMX_VMCS_RO_IO_RDI 0x6406
1746	#define VMX_VMCS_RO_IO_RIP 0x6408
1747	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640a
1748	/** @} */
1749
1750
1751	/** @name VMCS field encoding: Natural width guest-state fields.
1752	* @{
1753	*/
1754	#define VMX_VMCS_GUEST_CR0 0x6800
1755	#define VMX_VMCS_GUEST_CR3 0x6802
1756	#define VMX_VMCS_GUEST_CR4 0x6804
1757	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1758	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1759	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1760	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1761	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1762	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1763	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1764	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1765	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1766	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1767	#define VMX_VMCS_GUEST_DR7 0x681a
1768	#define VMX_VMCS_GUEST_RSP 0x681c
1769	#define VMX_VMCS_GUEST_RIP 0x681e
1770	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1771	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
1772	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
1773	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
1774	/** @} */
1775
1776
1777	/** @name VMCS field encoding: Natural width host-state fields.
1778	* @{
1779	*/
1780	#define VMX_VMCS_HOST_CR0 0x6c00
1781	#define VMX_VMCS_HOST_CR3 0x6c02
1782	#define VMX_VMCS_HOST_CR4 0x6c04
1783	#define VMX_VMCS_HOST_FS_BASE 0x6c06
1784	#define VMX_VMCS_HOST_GS_BASE 0x6c08
1785	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
1786	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
1787	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
1788	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
1789	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
1790	#define VMX_VMCS_HOST_RSP 0x6c14
1791	#define VMX_VMCS_HOST_RIP 0x6c16
1792	/** @} */
1793
1794
1795	/** @name VMCS field encoding: Access.
1796	* @{ */
1797	typedef enum
1798	{
1799	VMXVMCSFIELDACCESS_FULL = 0,
1800	VMXVMCSFIELDACCESS_HIGH
1801	} VMXVMCSFIELDACCESS;
1802	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
1803	/** @} */
1804
1805
1806	/** @name VMCS field encoding: Type.
1807	* @{ */
1808	typedef enum
1809	{
1810	VMXVMCSFIELDTYPE_CONTROL = 0,
1811	VMXVMCSFIELDTYPE_VMEXIT_INFO,
1812	VMXVMCSFIELDTYPE_GUEST_STATE,
1813	VMXVMCSFIELDTYPE_HOST_STATE
1814	} VMXVMCSFIELDTYPE;
1815	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
1816	/** @} */
1817
1818
1819	/** @name VMCS field encoding: Width.
1820	* @{ */
1821	typedef enum
1822	{
1823	VMXVMCSFIELDWIDTH_16BIT = 0,
1824	VMXVMCSFIELDWIDTH_64BIT,
1825	VMXVMCSFIELDWIDTH_32BIT,
1826	VMXVMCSFIELDWIDTH_NATURAL
1827	} VMXVMCSFIELDWIDTH;
1828	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
1829	/** @} */
1830
1831	/** @name VM-entry instruction length.
1832	* @{ */
1833	/** The maximum valid value for VM-entry instruction length while injecting a
1834	* software interrupt, software exception or privileged software exception. */
1835	#define VMX_ENTRY_INSTR_LEN_MAX 15
1836	/** @} */
1837
1838	/** @name Pin-based VM-execution controls.
1839	* @{
1840	*/
1841	/** External interrupt exiting. */
1842	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
1843	/** NMI exiting. */
1844	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
1845	/** Virtual NMIs. */
1846	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
1847	/** Activate VMX preemption timer. */
1848	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
1849	/** Process interrupts with the posted-interrupt notification vector. */
1850	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
1851	/** Default1 class when true capability MSRs are not supported. */
1852	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
1853
1854	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
1855	* controls field in the VMCS. */
1856	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
1857	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
1858	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
1859	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
1860	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
1861	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
1862	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
1863	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
1864	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
1865	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
1866	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
1867	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
1868	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
1869	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
1870	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
1871	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
1872	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
1873	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
1874	/** @} */
1875
1876
1877	/** @name Processor-based VM-execution controls.
1878	* @{
1879	*/
1880	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1881	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
1882	/** Use timestamp counter offset. */
1883	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
1884	/** VM-exit when executing the HLT instruction. */
1885	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
1886	/** VM-exit when executing the INVLPG instruction. */
1887	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
1888	/** VM-exit when executing the MWAIT instruction. */
1889	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
1890	/** VM-exit when executing the RDPMC instruction. */
1891	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
1892	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1893	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
1894	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
1895	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1896	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
1897	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
1898	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1899	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
1900	/** VM-exit on CR8 loads. */
1901	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
1902	/** VM-exit on CR8 stores. */
1903	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
1904	/** Use TPR shadow. */
1905	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
1906	/** VM-exit when virtual NMI blocking is disabled. */
1907	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
1908	/** VM-exit when executing a MOV DRx instruction. */
1909	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
1910	/** VM-exit when executing IO instructions. */
1911	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
1912	/** Use IO bitmaps. */
1913	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
1914	/** Monitor trap flag. */
1915	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
1916	/** Use MSR bitmaps. */
1917	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
1918	/** VM-exit when executing the MONITOR instruction. */
1919	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
1920	/** VM-exit when executing the PAUSE instruction. */
1921	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
1922	/** Whether the secondary processor based VM-execution controls are used. */
1923	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
1924	/** Default1 class when true-capability MSRs are not supported. */
1925	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
1926
1927	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
1928	* controls field in the VMCS. */
1929	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
1930	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
1931	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
1932	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
1933	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
1934	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
1935	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
1936	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
1937	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
1938	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
1939	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
1940	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
1941	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
1942	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
1943	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
1944	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
1945	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
1946	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
1947	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
1948	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
1949	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
1950	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
1951	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
1952	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
1953	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
1954	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
1955	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
1956	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
1957	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
1958	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
1959	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
1960	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
1961	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
1962	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
1963	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
1964	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
1965	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
1966	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
1967	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
1968	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
1969	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
1970	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
1971	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
1972	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
1973	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
1974	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
1975	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
1976	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
1977	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
1978	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
1979	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
1980	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
1981	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
1982	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
1983	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
1984	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
1985	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
1986	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
1987	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
1988	USE_SECONDARY_CTLS));
1989	/** @} */
1990
1991
1992	/** @name Secondary Processor-based VM-execution controls.
1993	* @{
1994	*/
1995	/** Virtualize APIC access. */
1996	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
1997	/** EPT supported/enabled. */
1998	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
1999	/** Descriptor table instructions cause VM-exits. */
2000	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2001	/** RDTSCP supported/enabled. */
2002	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2003	/** Virtualize x2APIC mode. */
2004	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2005	/** VPID supported/enabled. */
2006	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2007	/** VM-exit when executing the WBINVD instruction. */
2008	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2009	/** Unrestricted guest execution. */
2010	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2011	/** APIC register virtualization. */
2012	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2013	/** Virtual-interrupt delivery. */
2014	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2015	/** A specified number of pause loops cause a VM-exit. */
2016	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2017	/** VM-exit when executing RDRAND instructions. */
2018	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2019	/** Enables INVPCID instructions. */
2020	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2021	/** Enables VMFUNC instructions. */
2022	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2023	/** Enables VMCS shadowing. */
2024	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2025	/** Enables ENCLS VM-exits. */
2026	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2027	/** VM-exit when executing RDSEED. */
2028	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2029	/** Enables page-modification logging. */
2030	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2031	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2032	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
2033	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2034	#define VMX_PROC_CTLS2_CONCEAL_FROM_PT RT_BIT(19)
2035	/** Enables XSAVES/XRSTORS instructions. */
2036	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2037	/** Use TSC scaling. */
2038	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2039
2040	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2041	* VM-execution controls field in the VMCS. */
2042	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2043	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2044	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2045	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2046	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2047	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2048	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2049	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2050	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2051	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2052	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2053	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2054	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2055	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2056	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2057	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2058	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2059	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2060	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2061	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2062	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2063	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2064	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2065	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2066	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2067	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2068	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2069	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2070	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2071	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2072	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2073	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2074	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2075	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2076	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2077	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2078	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2079	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2080	#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_SHIFT 19
2081	#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_MASK UINT32_C(0x00080000)
2082	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2083	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2084	#define VMX_BF_PROC_CTLS2_UNDEF_21_24_SHIFT 21
2085	#define VMX_BF_PROC_CTLS2_UNDEF_21_24_MASK UINT32_C(0x01e00000)
2086	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2087	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2088	#define VMX_BF_PROC_CTLS2_UNDEF_26_31_SHIFT 26
2089	#define VMX_BF_PROC_CTLS2_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2090	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2091	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2092	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2093	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_FROM_PT, XSAVES_XRSTORS, UNDEF_21_24,
2094	TSC_SCALING, UNDEF_26_31));
2095	/** @} */
2096
2097
2098	/** @name VM-entry controls.
2099	* @{
2100	*/
2101	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2102	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2103	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2104	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2105	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2106	/** In SMM mode after VM-entry. */
2107	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2108	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2109	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2110	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2111	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2112	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2113	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2114	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2115	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2116	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2117	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2118	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2119	#define VMX_ENTRY_CTLS_CONCEAL_VMX_PT RT_BIT(17)
2120	/** Default1 class when true-capability MSRs are not supported. */
2121	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2122
2123	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2124	* VMCS. */
2125	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2126	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2127	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2128	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2129	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2130	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2131	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2132	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2133	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2134	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2135	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2136	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2137	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2138	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2139	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2140	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2141	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2142	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2143	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2144	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2145	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2146	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2147	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_PT_SHIFT 17
2148	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_PT_MASK UINT32_C(0x00020000)
2149	#define VMX_BF_ENTRY_CTLS_UNDEF_18_31_SHIFT 18
2150	#define VMX_BF_ENTRY_CTLS_UNDEF_18_31_MASK UINT32_C(0xfffc0000)
2151	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2152	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2153	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_PT, UNDEF_18_31));
2154	/** @} */
2155
2156
2157	/** @name VM-exit controls.
2158	* @{
2159	*/
2160	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2161	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2162	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2163	/** Return to long mode after a VM-exit. */
2164	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2165	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2166	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2167	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2168	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2169	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2170	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2171	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2172	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2173	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2174	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2175	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2176	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2177	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2178	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2179	/** Default1 class when true-capability MSRs are not supported. */
2180	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2181
2182	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2183	* VMCS. */
2184	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2185	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2186	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2187	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2188	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2189	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2190	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2191	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2192	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2193	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2194	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2195	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2196	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2197	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2198	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2199	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2200	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2201	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2202	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2203	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2204	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2205	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2206	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2207	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2208	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2209	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2210	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2211	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2212	#define VMX_BF_EXIT_CTLS_UNDEF_23_31_SHIFT 23
2213	#define VMX_BF_EXIT_CTLS_UNDEF_23_31_MASK UINT32_C(0xff800000)
2214	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2215	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2216	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2217	SAVE_PREEMPT_TIMER, UNDEF_23_31));
2218	/** @} */
2219
2220
2221	/** @name VM-exit reason.
2222	* @{
2223	*/
2224	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2225	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2226	/** @} */
2227
2228
2229	/** @name VM-entry interruption information.
2230	* @{
2231	*/
2232	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2233	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2234	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2235	/** @} */
2236
2237
2238	/** @name VM-entry interruption information.
2239	* @{ */
2240	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2241	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2242	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2243	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2244	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2245	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2246	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2247	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2248	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2249	/** Construct an VM-entry interruption information field from a VM-exit interruption
2250	* info value (same except that bit 12 is reserved). */
2251	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2252	/** Construct a VM-entry interruption information field from an IDT-vectoring
2253	* information field (same except that bit 12 is reserved). */
2254	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2255
2256	/** Bit fields for VM-entry interruption information. */
2257	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2258	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2259	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2260	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2261	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2262	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2263	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2264	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2265	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2266	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2267	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2268	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2269	/** @} */
2270
2271	/** @name VM-entry exception error code.
2272	* @{ */
2273	/** Error code valid mask. */
2274	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2275	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2276	* stack aligned for doubleword pushes, the upper half of the error code is
2277	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2278	* use below. */
2279	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2280	/** @} */
2281
2282	/** @name VM-entry interruption information types.
2283	* @{
2284	*/
2285	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2286	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2287	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2288	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2289	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2290	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2291	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2292	/** @} */
2293
2294
2295	/** @name VM-exit interruption information.
2296	* @{
2297	*/
2298	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2299	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2300	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2301	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2302	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2303	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2304	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2305	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2306	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2307
2308	/** Bit fields for VM-exit interruption infomration. */
2309	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2310	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2311	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2312	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2313	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2314	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2315	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2316	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2317	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2318	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2319	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2320	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2321	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2322	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2323	/** @} */
2324
2325
2326	/** @name VM-exit interruption information types.
2327	* @{
2328	*/
2329	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2330	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2331	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2332	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2333	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2334	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2335	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2336	/** @} */
2337
2338
2339	/** @name VM-exit instruction identity.
2340	*
2341	* These are found in VM-exit instruction information fields for certain
2342	* instructions.
2343	* @{ */
2344	typedef uint8_t VMXINSTRID;
2345	#define VMXINSTRID_VALID RT_BIT(7)
2346	#define VMXINSTRID_IS_VALID(a) (((a) >> 7) & 1)
2347	#define VMXINSTRID_GET_ID(a) ((a) & ~VMXINSTRID_VALID)
2348	#define VMXINSTRID_NONE 0
2349	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2350	#define VMXINSTRID_SGDT ((VMXINSTRID_VALID) \| 0)
2351	#define VMXINSTRID_SIDT ((VMXINSTRID_VALID) \| 1)
2352	#define VMXINSTRID_LGDT ((VMXINSTRID_VALID) \| 2)
2353	#define VMXINSTRID_LIDT ((VMXINSTRID_VALID) \| 3)
2354
2355	#define VMXINSTRID_SLDT ((VMXINSTRID_VALID) \| 0)
2356	#define VMXINSTRID_STR ((VMXINSTRID_VALID) \| 1)
2357	#define VMXINSTRID_LLDT ((VMXINSTRID_VALID) \| 2)
2358	#define VMXINSTRID_LTR ((VMXINSTRID_VALID) \| 3)
2359
2360	/** The following are used internally and are not based on the VT-x spec: */
2361	#define VMXINSTRID_VMLAUNCH ((VMXINSTRID_VALID) \| 50)
2362	#define VMXINSTRID_VMRESUME ((VMXINSTRID_VALID) \| 51)
2363	/** @} */
2364
2365
2366	/** @name IDT-vectoring information.
2367	* @{
2368	*/
2369	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2370	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2371	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2372	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2373
2374	/** Bit fields for IDT-vectoring information. */
2375	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2376	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2377	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2378	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2379	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2380	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2381	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2382	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2383	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2384	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2385	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2386	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2387	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2388	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2389	/** @} */
2390
2391
2392	/** @name IDT-vectoring information vector types.
2393	* @{
2394	*/
2395	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2396	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2397	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2398	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2399	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2400	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2401	#define VMX_IDT_VECTORING_INFO_TYPE_SW_UNUSED 7
2402	/** @} */
2403
2404
2405	/** @name TPR threshold.
2406	* @{ */
2407	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
2408	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
2409
2410	/** Bit fields for TPR threshold. */
2411	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
2412	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
2413	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
2414	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
2415	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
2416	(TPR, RSVD_4_31));
2417	/** @} */
2418
2419
2420	/** @name Guest-activity states.
2421	* @{
2422	*/
2423	/** The logical processor is active. */
2424	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2425	/** The logical processor is inactive, because it executed a HLT instruction. */
2426	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2427	/** The logical processor is inactive, because of a triple fault or other serious error. */
2428	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2429	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2430	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2431	/** @} */
2432
2433
2434	/** @name Guest-interruptibility states.
2435	* @{
2436	*/
2437	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2438	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2439	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2440	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2441	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
2442
2443	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
2444	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
2445	/** @} */
2446
2447
2448	/** @name Exit qualification for Mov DRx.
2449	* @{
2450	*/
2451	/** 0-2: Debug register number */
2452	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
2453	/** 3: Reserved; cleared to 0. */
2454	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
2455	/** 4: Direction of move (0 = write, 1 = read) */
2456	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
2457	/** 5-7: Reserved; cleared to 0. */
2458	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
2459	/** 8-11: General purpose register number. */
2460	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
2461	/** Rest: reserved. */
2462	/** @} */
2463
2464
2465	/** @name Exit qualification for debug exceptions types.
2466	* @{
2467	*/
2468	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
2469	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
2470	/** @} */
2471
2472
2473	/** @name Exit qualification for control-register accesses.
2474	* @{
2475	*/
2476	/** 0-3: Control register number (0 for CLTS & LMSW) */
2477	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
2478	/** 4-5: Access type. */
2479	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
2480	/** 6: LMSW operand type */
2481	#define VMX_EXIT_QUAL_CRX_LMSW_OP(a) (((a) >> 6) & 1)
2482	/** 7: Reserved; cleared to 0. */
2483	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
2484	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
2485	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
2486	/** 12-15: Reserved; cleared to 0. */
2487	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
2488	/** 16-31: LMSW source data (else 0). */
2489	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
2490	/* Rest: reserved. */
2491	/** @} */
2492
2493
2494	/** @name Exit qualification for control-register access types.
2495	* @{
2496	*/
2497	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
2498	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
2499	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
2500	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
2501	/** @} */
2502
2503
2504	/** @name Exit qualification for task switch.
2505	* @{
2506	*/
2507	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
2508	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
2509	/** Task switch caused by a call instruction. */
2510	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
2511	/** Task switch caused by an iret instruction. */
2512	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
2513	/** Task switch caused by a jmp instruction. */
2514	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
2515	/** Task switch caused by an interrupt gate. */
2516	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
2517	/** @} */
2518
2519
2520	/** @name Exit qualification for EPT violations.
2521	* @{
2522	*/
2523	/** Set if the violation was caused by a data read. */
2524	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
2525	/** Set if the violation was caused by a data write. */
2526	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
2527	/** Set if the violation was caused by an instruction fetch. */
2528	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
2529	/** AND of the present bit of all EPT structures. */
2530	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
2531	/** AND of the write bit of all EPT structures. */
2532	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
2533	/** AND of the execute bit of all EPT structures. */
2534	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
2535	/** Set if the guest linear address field contains the faulting address. */
2536	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
2537	/** If bit 7 is one: (reserved otherwise)
2538	* 1 - violation due to physical address access.
2539	* 0 - violation caused by page walk or access/dirty bit updates
2540	*/
2541	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
2542	/** @} */
2543
2544
2545	/** @name Exit qualification for I/O instructions.
2546	* @{
2547	*/
2548	/** 0-2: IO operation width. */
2549	#define VMX_EXIT_QUAL_IO_WIDTH(a) ((a) & 7)
2550	/** 3: IO operation direction. */
2551	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
2552	/** 4: String IO operation (INS / OUTS). */
2553	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
2554	/** 5: Repeated IO operation. */
2555	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
2556	/** 6: Operand encoding. */
2557	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
2558	/** 16-31: IO Port (0-0xffff). */
2559	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
2560	/* Rest reserved. */
2561	/** @} */
2562
2563
2564	/** @name Exit qualification for I/O instruction types.
2565	* @{
2566	*/
2567	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
2568	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
2569	/** @} */
2570
2571
2572	/** @name Exit qualification for I/O instruction encoding.
2573	* @{
2574	*/
2575	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
2576	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
2577	/** @} */
2578
2579
2580	/** @name Exit qualification for APIC-access VM-exits from linear and
2581	* guest-physical accesses.
2582	* @{
2583	*/
2584	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
2585	* access within the APIC page. */
2586	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
2587	/** 12-15: Access type. */
2588	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
2589	/* Rest reserved. */
2590	/** @} */
2591
2592
2593	/** @name Exit qualification for linear address APIC-access types.
2594	* @{
2595	*/
2596	/** Linear read access. */
2597	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
2598	/** Linear write access. */
2599	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
2600	/** Linear instruction fetch access. */
2601	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
2602	/** Linear read/write access during event delivery. */
2603	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
2604	/** Physical read/write access during event delivery. */
2605	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
2606	/** Physical access for an instruction fetch or during instruction execution. */
2607	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
2608	/** @} */
2609
2610
2611	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
2612	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
2613	* @{
2614	*/
2615	/** Address calculation scaling field (powers of two). */
2616	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
2617	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
2618	/** Bits 2 thru 6 are undefined. */
2619	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
2620	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
2621	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
2622	* @remarks anyone's guess why this is a 3 bit field... */
2623	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
2624	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
2625	/** Bit 10 is defined as zero. */
2626	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
2627	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
2628	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
2629	* for exits from 64-bit code as the operand size there is fixed. */
2630	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
2631	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
2632	/** Bits 12 thru 14 are undefined. */
2633	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
2634	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
2635	/** Applicable segment register (X86_SREG_XXX values). */
2636	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
2637	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
2638	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
2639	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
2640	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
2641	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
2642	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
2643	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
2644	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
2645	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
2646	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
2647	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2648	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
2649	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2650	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
2651	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
2652	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2653	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
2654	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
2655	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
2656	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
2657	/** Bits 30 & 31 are undefined. */
2658	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
2659	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
2660	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
2661	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
2662	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
2663	/** @} */
2664
2665
2666	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
2667	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
2668	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
2669	* @{
2670	*/
2671	/** Address calculation scaling field (powers of two). */
2672	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
2673	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
2674	/** Bit 2 is undefined. */
2675	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
2676	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
2677	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
2678	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
2679	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
2680	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
2681	* @remarks anyone's guess why this is a 3 bit field... */
2682	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
2683	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
2684	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
2685	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
2686	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
2687	/** Bits 11 thru 14 are undefined. */
2688	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
2689	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
2690	/** Applicable segment register (X86_SREG_XXX values). */
2691	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
2692	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
2693	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
2694	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
2695	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
2696	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
2697	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
2698	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
2699	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
2700	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
2701	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
2702	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2703	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
2704	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2705	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
2706	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
2707	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2708	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
2709	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
2710	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
2711	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
2712	/** Bits 30 & 31 are undefined. */
2713	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
2714	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
2715	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
2716	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
2717	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
2718	/** @} */
2719
2720
2721	/** @name Format of Pending-Debug-Exceptions.
2722	* Bits 4-11, 13, 15 and 17-63 are reserved.
2723	* @{
2724	*/
2725	/** Hardware breakpoint 0 was met. */
2726	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT(0)
2727	/** Hardware breakpoint 1 was met. */
2728	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT(1)
2729	/** Hardware breakpoint 2 was met. */
2730	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT(2)
2731	/** Hardware breakpoint 3 was met. */
2732	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT(3)
2733	/** At least one data or IO breakpoint was hit. */
2734	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT(12)
2735	/** A debug exception would have been triggered by single-step execution mode. */
2736	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT(14)
2737	/** A debug exception occurred inside an RTM region. */
2738	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT(16)
2739	/** @} */
2740
2741
2742	/** @name VMCS field encoding.
2743	* @{ */
2744	typedef union
2745	{
2746	struct
2747	{
2748	/** The access type; 0=full, 1=high of 64-bit fields. */
2749	uint32_t fAccessType : 1;
2750	/** The index. */
2751	uint32_t u8Index : 8;
2752	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
2753	uint32_t u2Type : 2;
2754	/** Reserved (MBZ). */
2755	uint32_t u1Reserved0 : 1;
2756	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
2757	uint32_t u2Width : 2;
2758	/** Reserved (MBZ). */
2759	uint32_t u18Reserved0 : 18;
2760	} n;
2761	/* The unsigned integer view. */
2762	uint32_t u;
2763	} VMXVMCSFIELDENC;
2764	AssertCompileSize(VMXVMCSFIELDENC, 4);
2765	/** Pointer to a VMCS field encoding. */
2766	typedef VMXVMCSFIELDENC *PVMXVMCSFIELDENC;
2767	/** Pointer to a const VMCS field encoding. */
2768	typedef const VMXVMCSFIELDENC *PCVMXVMCSFIELDENC;
2769
2770	/** VMCS field encoding type: Full. */
2771	#define VMX_VMCS_ENC_ACCESS_TYPE_FULL 0
2772	/** VMCS field encoding type: High. */
2773	#define VMX_VMCS_ENC_ACCESS_TYPE_HIGH 1
2774
2775	/** VMCS field encoding type: Control. */
2776	#define VMX_VMCS_ENC_TYPE_CONTROL 0
2777	/** VMCS field encoding type: VM-exit information / read-only fields. */
2778	#define VMX_VMCS_ENC_TYPE_VMEXIT_INFO 1
2779	/** VMCS field encoding type: Guest-state. */
2780	#define VMX_VMCS_ENC_TYPE_GUEST_STATE 2
2781	/** VMCS field encoding type: Host-state. */
2782	#define VMX_VMCS_ENC_TYPE_HOST_STATE 3
2783
2784	/** VMCS field encoding width: 16-bit. */
2785	#define VMX_VMCS_ENC_WIDTH_16BIT 0
2786	/** VMCS field encoding width: 64-bit. */
2787	#define VMX_VMCS_ENC_WIDTH_64BIT 1
2788	/** VMCS field encoding width: 32-bit. */
2789	#define VMX_VMCS_ENC_WIDTH_32BIT 2
2790	/** VMCS field encoding width: Natural width. */
2791	#define VMX_VMCS_ENC_WIDTH_NATURAL 3
2792
2793	/** Bits fields for VMCS field encoding. */
2794	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_SHIFT 0
2795	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2796	#define VMX_BF_VMCS_ENC_INDEX_SHIFT 1
2797	#define VMX_BF_VMCS_ENC_INDEX_MASK UINT32_C(0x000003fe)
2798	#define VMX_BF_VMCS_ENC_TYPE_SHIFT 10
2799	#define VMX_BF_VMCS_ENC_TYPE_MASK UINT32_C(0x00000c00)
2800	#define VMX_BF_VMCS_ENC_RSVD_12_SHIFT 12
2801	#define VMX_BF_VMCS_ENC_RSVD_12_MASK UINT32_C(0x00001000)
2802	#define VMX_BF_VMCS_ENC_WIDTH_SHIFT 13
2803	#define VMX_BF_VMCS_ENC_WIDTH_MASK UINT32_C(0x00006000)
2804	#define VMX_BF_VMCS_ENC_RSVD_15_31_SHIFT 15
2805	#define VMX_BF_VMCS_ENC_RSVD_15_31_MASK UINT32_C(0xffff8000)
2806	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENC_, UINT32_C(0), UINT32_MAX,
2807	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2808	/** @} */
2809
2810
2811	/** @defgroup grp_hm_vmx_virt VMX virtualization.
2812	* @{
2813	*/
2814
2815	/** CR0 bits set here must always be set when in VMX operation. */
2816	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
2817	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
2818	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
2819	/** CR4 bits set here must always be set when in VMX operation. */
2820	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
2821
2822	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
2823	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
2824	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x1d000001)
2825	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
2826
2827	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
2828	* complications when teleporation may be implemented). */
2829	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
2830	/** The size of the virtual VMCS region (in pages). */
2831	#define VMX_V_VMCS_PAGES 1
2832
2833	/** The size of the Virtual-APIC page (in bytes). */
2834	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
2835	/** The size of the Virtual-APIC page (in pages). */
2836	#define VMX_V_VIRT_APIC_PAGES 1
2837
2838	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
2839	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
2840	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
2841	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
2842
2843	/** The highest index value used for supported virtual VMCS field encoding. */
2844	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCS_ENC_INDEX)
2845
2846	/** @name Virtual VMX MSR - Miscellaneous data.
2847	* @{ */
2848	/** Number of CR3-target values supported. */
2849	#define VMX_V_CR3_TARGET_COUNT 4
2850	/** Activity states supported. */
2851	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
2852	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
2853	#define VMX_V_PREEMPT_TIMER_SHIFT 5
2854	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
2855	#define VMX_V_MAX_MSRS 0
2856	/** SMM MSEG revision ID. */
2857	#define VMX_V_MSEG_REV_ID 0
2858	/** @} */
2859
2860	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS state.
2861	* @{ */
2862	/** VMCS state clear. */
2863	#define VMX_V_VMCS_STATE_CLEAR RT_BIT(1)
2864	/** VMCS state launched. */
2865	#define VMX_V_VMCS_STATE_LAUNCHED RT_BIT(2)
2866	/** @} */
2867
2868	/**
2869	* Virtual VM-Exit information.
2870	*
2871	* This is a convenience structure that bundles some VM-exit information related
2872	* fields together.
2873	*/
2874	typedef struct
2875	{
2876	/** The VM-exit reason. */
2877	uint32_t uReason;
2878	/** The VM-exit instruction length. */
2879	uint32_t cbInstr;
2880	/** The VM-exit instruction information. */
2881	VMXEXITINSTRINFO InstrInfo;
2882	/** Padding. */
2883	uint32_t u32Padding0;
2884
2885	/** The VM-exit qualification field. */
2886	uint64_t u64Qual;
2887	/** The guest-linear address field. */
2888	uint64_t u64GuestLinearAddr;
2889	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
2890	* instruction VM-exit. */
2891	RTGCPTR GCPtrEffAddr;
2892
2893	/** The VM-exit instruction ID. */
2894	VMXINSTRID uInstrId;
2895	} VMXVEXITINFO;
2896	/** Pointer to the VMXVEXITINFO struct. */
2897	typedef VMXVEXITINFO *PVMXVEXITINFO;
2898	/** Pointer to a const VMXVEXITINFO struct. */
2899	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
2900
2901	/**
2902	* Virtual VMCS.
2903	* This is our custom format and merged into the actual VMCS (/shadow) when we
2904	* execute nested-guest code using hardware-assisted VMX.
2905	*
2906	* The first 8 bytes are as per Intel spec. 24.2 "Format of the VMCS Region".
2907	*
2908	* The offset and size of the VMCS state field (fVmcsState) is also fixed (not by
2909	* Intel but for our own requirements) as we use it to offset into guest memory.
2910	*
2911	* We always treat natural-width fields as 64-bit in our implementation since
2912	* it's easier, allows for teleporation in the future and does not affect guest
2913	* software.
2914	*
2915	* Although the guest is supposed to access the VMCS only through the execution of
2916	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
2917	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
2918	* for teleportation (when implemented) any newly added fields should be added to
2919	* the appropriate reserved sections or at the end of the structure.
2920	*/
2921	#pragma pack(1)
2922	typedef struct
2923	{
2924	/** 0x0 - VMX VMCS revision identifier. */
2925	VMXVMCSREVID u32VmcsRevId;
2926	/** 0x4 - VMX-abort indicator. */
2927	uint32_t u32VmxAbortId;
2928	/** 0x8 - VMCS state, see VMX_V_VMCS_STATE_XXX. */
2929	uint8_t fVmcsState;
2930	/** 0x9 - Reserved for future. */
2931	uint8_t au8Padding0[3];
2932	/** 0xc - Reserved for future. */
2933	uint32_t au32Reserved0[7];
2934
2935	/** @name 16-bit control fields.
2936	* @{ */
2937	/** 0x28 - Virtual processor ID. */
2938	uint16_t u16Vpid;
2939	/** 0x2a - Posted interrupt notify vector. */
2940	uint16_t u16PostIntNotifyVector;
2941	/** 0x2c - EPTP index. */
2942	uint16_t u16EptpIndex;
2943	/** 0x2e - Reserved for future. */
2944	uint16_t au16Reserved0[8];
2945	/** @} */
2946
2947	/** @name 16-bit Guest-state fields.
2948	* Order of [ES..GS] is important, must match X86_SREG_XXX.
2949	* @{ */
2950	/** 0x3e - Guest ES selector. */
2951	RTSEL GuestEs;
2952	/** 0x40 - Guest ES selector. */
2953	RTSEL GuestCs;
2954	/** 0x42 - Guest ES selector. */
2955	RTSEL GuestSs;
2956	/** 0x44 - Guest ES selector. */
2957	RTSEL GuestDs;
2958	/** 0x46 - Guest ES selector. */
2959	RTSEL GuestFs;
2960	/** 0x48 - Guest ES selector. */
2961	RTSEL GuestGs;
2962	/** 0x4a - Guest LDTR selector. */
2963	RTSEL GuestLdtr;
2964	/** 0x4c - Guest TR selector. */
2965	RTSEL GuestTr;
2966	/** 0x4e - Guest interrupt status (virtual-interrupt delivery). */
2967	uint16_t u16GuestIntStatus;
2968	/** 0x50 - PML index. */
2969	uint16_t u16PmlIndex;
2970	/** 0x52 - Reserved for future. */
2971	uint16_t au16Reserved1[8];
2972	/** @} */
2973
2974	/** @name 16-bit Host-state fields.
2975	* @{ */
2976	/** 0x62 - Host ES selector. */
2977	RTSEL HostEs;
2978	/** 0x64 - Host CS selector. */
2979	RTSEL HostCs;
2980	/** 0x66 - Host SS selector. */
2981	RTSEL HostSs;
2982	/** 0x68 - Host DS selector. */
2983	RTSEL HostDs;
2984	/** 0x6a - Host FS selector. */
2985	RTSEL HostFs;
2986	/** 0x6c - Host GS selector. */
2987	RTSEL HostGs;
2988	/** 0x6e - Host TR selector. */
2989	RTSEL HostTr;
2990	/** 0x70 - Reserved for future. */
2991	uint16_t au16Reserved2[10];
2992	/** @} */
2993
2994	/** @name 32-bit Control fields.
2995	* @{ */
2996	/** 0x84 - Pin-based VM-execution controls. */
2997	uint32_t u32PinCtls;
2998	/** 0x88 - Processor-based VM-execution controls. */
2999	uint32_t u32ProcCtls;
3000	/** 0x8c - Exception bitmap. */
3001	uint32_t u32XcptBitmap;
3002	/** 0x90 - Page-fault exception error mask. */
3003	uint32_t u32XcptPFMask;
3004	/** 0x94 - Page-fault exception error match. */
3005	uint32_t u32XcptPFMatch;
3006	/** 0x98 - CR3-target count. */
3007	uint32_t u32Cr3TargetCount;
3008	/** 0x9c - VM-exit controls. */
3009	uint32_t u32ExitCtls;
3010	/** 0xa0 - VM-exit MSR store count. */
3011	uint32_t u32ExitMsrStoreCount;
3012	/** 0xa4 - VM-exit MSR load count. */
3013	uint32_t u32ExitMsrLoadCount;
3014	/** 0xa8 - VM-entry controls. */
3015	uint32_t u32EntryCtls;
3016	/** 0xac - VM-entry MSR load count. */
3017	uint32_t u32EntryMsrLoadCount;
3018	/** 0xb0 - VM-entry interruption information. */
3019	uint32_t u32EntryIntInfo;
3020	/** 0xb4 - VM-entry exception error code. */
3021	uint32_t u32EntryXcptErrCode;
3022	/** 0xb8 - VM-entry instruction length. */
3023	uint32_t u32EntryInstrLen;
3024	/** 0xbc - TPR-threshold. */
3025	uint32_t u32TprThreshold;
3026	/** 0xc0 - Secondary-processor based VM-execution controls. */
3027	uint32_t u32ProcCtls2;
3028	/** 0xc4 - Pause-loop exiting Gap. */
3029	uint32_t u32PleGap;
3030	/** 0xc8 - Pause-loop exiting Window. */
3031	uint32_t u32PleWindow;
3032	/** 0xcc - Reserved for future. */
3033	uint32_t au32Reserved1[8];
3034	/** @} */
3035
3036	/** @name 32-bit Read-only Data fields.
3037	* @{ */
3038	/** 0xec - VM-instruction error. */
3039	uint32_t u32RoVmInstrError;
3040	/** 0xf0 - VM-exit reason. */
3041	uint32_t u32RoExitReason;
3042	/** 0xf4 - VM-exit interruption information. */
3043	uint32_t u32RoExitIntInfo;
3044	/** 0xf8 - VM-exit interruption error code. */
3045	uint32_t u32RoExitErrCode;
3046	/** 0xfc - IDT-vectoring information. */
3047	uint32_t u32RoIdtVectoringInfo;
3048	/** 0x100 - IDT-vectoring error code. */
3049	uint32_t u32RoIdtVectoringErrCode;
3050	/** 0x104 - VM-exit instruction length. */
3051	uint32_t u32RoExitInstrLen;
3052	/** 0x108 - VM-exit instruction information. */
3053	uint32_t u32RoExitInstrInfo;
3054	/** 0x10c - Reserved for future. */
3055	uint32_t au32RoReserved2[8];
3056	/** @} */
3057
3058	/** @name 32-bit Guest-state fields.
3059	* Order of [ES..GS] limit and attributes are important, must match X86_SREG_XXX.
3060	* @{ */
3061	/** 0x12c - Guest ES limit. */
3062	uint32_t u32GuestEsLimit;
3063	/** 0x130 - Guest CS limit. */
3064	uint32_t u32GuestCsLimit;
3065	/** 0x134 - Guest SS limit. */
3066	uint32_t u32GuestSsLimit;
3067	/** 0x138 - Guest DS limit. */
3068	uint32_t u32GuestDsLimit;
3069	/** 0x13c - Guest FS limit. */
3070	uint32_t u32GuestFsLimit;
3071	/** 0x140 - Guest GS limit. */
3072	uint32_t u32GuestGsLimit;
3073	/** 0x144 - Guest LDTR limit. */
3074	uint32_t u32GuestLdtrLimit;
3075	/** 0x148 - Guest TR limit. */
3076	uint32_t u32GuestTrLimit;
3077	/** 0x14c - Guest GDTR limit. */
3078	uint32_t u32GuestGdtrLimit;
3079	/** 0x150 - Guest IDTR limit. */
3080	uint32_t u32GuestIdtrLimit;
3081	/** 0x154 - Guest ES attributes. */
3082	uint32_t u32GuestEsAttr;
3083	/** 0x158 - Guest CS attributes. */
3084	uint32_t u32GuestCsAttr;
3085	/** 0x15c - Guest SS attributes. */
3086	uint32_t u32GuestSsAttr;
3087	/** 0x160 - Guest DS attributes. */
3088	uint32_t u32GuestDsAttr;
3089	/** 0x164 - Guest FS attributes. */
3090	uint32_t u32GuestFsAttr;
3091	/** 0x168 - Guest GS attributes. */
3092	uint32_t u32GuestGsAttr;
3093	/** 0x16c - Guest LDTR attributes. */
3094	uint32_t u32GuestLdtrAttr;
3095	/** 0x170 - Guest TR attributes. */
3096	uint32_t u32GuestTrAttr;
3097	/** 0x174 - Guest interruptibility state. */
3098	uint32_t u32GuestIntrState;
3099	/** 0x178 - Guest activity state. */
3100	uint32_t u32GuestActivityState;
3101	/** 0x17c - Guest SMBASE. */
3102	uint32_t u32GuestSmBase;
3103	/** 0x180 - Guest SYSENTER CS. */
3104	uint32_t u32GuestSysenterCS;
3105	/** 0x184 - Preemption timer value. */
3106	uint32_t u32PreemptTimer;
3107	/** 0x188 - Reserved for future. */
3108	uint32_t au32Reserved3[8];
3109	/** @} */
3110
3111	/** @name 32-bit Host-state fields.
3112	* @{ */
3113	/** 0x1a8 - Host SYSENTER CS. */
3114	uint32_t u32HostSysenterCs;
3115	/** 0x1ac - Reserved for future. */
3116	uint32_t au32Reserved4[11];
3117	/** @} */
3118
3119	/** @name 64-bit Control fields.
3120	* @{ */
3121	/** 0x1d8 - I/O bitmap A address. */
3122	RTUINT64U u64AddrIoBitmapA;
3123	/** 0x1e0 - I/O bitmap B address. */
3124	RTUINT64U u64AddrIoBitmapB;
3125	/** 0x1e8 - MSR bitmap address. */
3126	RTUINT64U u64AddrMsrBitmap;
3127	/** 0x1f0 - VM-exit MSR-store area address. */
3128	RTUINT64U u64AddrExitMsrStore;
3129	/** 0x1f8 - VM-exit MSR-load area address. */
3130	RTUINT64U u64AddrExitMsrLoad;
3131	/** 0x200 - VM-entry MSR-load area address. */
3132	RTUINT64U u64AddrEntryMsrLoad;
3133	/** 0x208 - Executive-VMCS pointer. */
3134	RTUINT64U u64ExecVmcsPtr;
3135	/** 0x210 - PML address. */
3136	RTUINT64U u64AddrPml;
3137	/** 0x218 - TSC offset. */
3138	RTUINT64U u64TscOffset;
3139	/** 0x220 - Virtual-APIC address. */
3140	RTUINT64U u64AddrVirtApic;
3141	/** 0x228 - APIC-access address. */
3142	RTUINT64U u64AddrApicAccess;
3143	/** 0x230 - Posted-interrupt descriptor address. */
3144	RTUINT64U u64AddrPostedIntDesc;
3145	/** 0x238 - VM-functions control. */
3146	RTUINT64U u64VmFuncCtls;
3147	/** 0x240 - EPTP pointer. */
3148	RTUINT64U u64EptpPtr;
3149	/** 0x248 - EOI-exit bitmap 0. */
3150	RTUINT64U u64EoiExitBitmap0;
3151	/** 0x250 - EOI-exit bitmap 1. */
3152	RTUINT64U u64EoiExitBitmap1;
3153	/** 0x258 - EOI-exit bitmap 2. */
3154	RTUINT64U u64EoiExitBitmap2;
3155	/** 0x260 - EOI-exit bitmap 3. */
3156	RTUINT64U u64EoiExitBitmap3;
3157	/** 0x268 - EPTP-list address. */
3158	RTUINT64U u64AddrEptpList;
3159	/** 0x270 - VMREAD-bitmap address. */
3160	RTUINT64U u64AddrVmreadBitmap;
3161	/** 0x278 - VMWRITE-bitmap address. */
3162	RTUINT64U u64AddrVmwriteBitmap;
3163	/** 0x280 - Virtualization-exception information address. */
3164	RTUINT64U u64AddrXcptVeInfo;
3165	/** 0x288 - XSS-exiting bitmap address. */
3166	RTUINT64U u64AddrXssBitmap;
3167	/** 0x290 - ENCLS-exiting bitmap address. */
3168	RTUINT64U u64AddrEnclsBitmap;
3169	/** 0x298 - TSC multiplier. */
3170	RTUINT64U u64TscMultiplier;
3171	/** 0x2a0 - Reserved for future. */
3172	RTUINT64U au64Reserved0[16];
3173	/** @} */
3174
3175	/** @name 64-bit Read-only Data fields.
3176	* @{ */
3177	/** 0x320 - Guest-physical address. */
3178	RTUINT64U u64GuestPhysAddr;
3179	/** 0x328 - Reserved for future. */
3180	RTUINT64U au64Reserved1[8];
3181	/** @} */
3182
3183	/** @name 64-bit Guest-state fields.
3184	* @{ */
3185	/** 0x368 - VMCS link pointer. */
3186	RTUINT64U u64VmcsLinkPtr;
3187	/** 0x370 - Guest debug-control MSR. */
3188	RTUINT64U u64GuestDebugCtlMsr;
3189	/** 0x378 - Guest PAT MSR. */
3190	RTUINT64U u64GuestPatMsr;
3191	/** 0x380 - Guest EFER MSR. */
3192	RTUINT64U u64GuestEferMsr;
3193	/** 0x388 - Guest global performance-control MSR. */
3194	RTUINT64U u64GuestPerfGlobalCtlMsr;
3195	/** 0x390 - Guest PDPTE 0. */
3196	RTUINT64U u64GuestPdpte0;
3197	/** 0x398 - Guest PDPTE 0. */
3198	RTUINT64U u64GuestPdpte1;
3199	/** 0x3a0 - Guest PDPTE 1. */
3200	RTUINT64U u64GuestPdpte2;
3201	/** 0x3a8 - Guest PDPTE 2. */
3202	RTUINT64U u64GuestPdpte3;
3203	/** 0x3b0 - Guest Bounds-config MSR (Intel MPX - Memory Protection Extensions). */
3204	RTUINT64U u64GuestBndcfgsMsr;
3205	/** 0x3b8 - Reserved for future. */
3206	RTUINT64U au64Reserved2[16];
3207	/** @} */
3208
3209	/** @name 64-bit Host-state Fields.
3210	* @{ */
3211	/** 0x438 - Host PAT MSR. */
3212	RTUINT64U u64HostPatMsr;
3213	/** 0x440 - Host EFER MSR. */
3214	RTUINT64U u64HostEferMsr;
3215	/** 0x448 - Host global performance-control MSR. */
3216	RTUINT64U u64HostPerfGlobalCtlMsr;
3217	/** 0x450 - Reserved for future. */
3218	RTUINT64U au64Reserved3[16];
3219	/** @} */
3220
3221	/** @name Natural-width Control fields.
3222	* @{ */
3223	/** 0x4d0 - CR0 guest/host Mask. */
3224	RTUINT64U u64Cr0Mask;
3225	/** 0x4d8 - CR4 guest/host Mask. */
3226	RTUINT64U u64Cr4Mask;
3227	/** 0x4e0 - CR0 read shadow. */
3228	RTUINT64U u64Cr0ReadShadow;
3229	/** 0x4e8 - CR4 read shadow. */
3230	RTUINT64U u64Cr4ReadShadow;
3231	/** 0x4f0 - CR3-target value 0. */
3232	RTUINT64U u64Cr3Target0;
3233	/** 0x4f8 - CR3-target value 1. */
3234	RTUINT64U u64Cr3Target1;
3235	/** 0x500 - CR3-target value 2. */
3236	RTUINT64U u64Cr3Target2;
3237	/** 0x508 - CR3-target value 3. */
3238	RTUINT64U u64Cr3Target3;
3239	/** 0x510 - Reserved for future. */
3240	RTUINT64U au64Reserved4[32];
3241	/** @} */
3242
3243	/** @name Natural-width Read-only Data fields. */
3244	/** 0x610 - Exit qualification. */
3245	RTUINT64U u64ExitQual;
3246	/** 0x618 - I/O RCX. */
3247	RTUINT64U u64IoRcx;
3248	/** 0x620 - I/O RSI. */
3249	RTUINT64U u64IoRsi;
3250	/** 0x628 - I/O RDI. */
3251	RTUINT64U u64IoRdi;
3252	/** 0x630 - I/O RIP. */
3253	RTUINT64U u64IoRip;
3254	/** 0x638 - Guest-linear address. */
3255	RTUINT64U u64GuestLinearAddr;
3256	/** 0x640 - Reserved for future. */
3257	RTUINT64U au64Reserved5[16];
3258	/** @} */
3259
3260	/** @name Natural-width Guest-state Fields.
3261	* Order of [ES..GS] base is important, must match X86_SREG_XXX.
3262	* @{ */
3263	/** 0x6c0 - Guest CR0. */
3264	RTUINT64U u64GuestCr0;
3265	/** 0x6c8 - Guest CR3. */
3266	RTUINT64U u64GuestCr3;
3267	/** 0x6d0 - Guest CR4. */
3268	RTUINT64U u64GuestCr4;
3269	/** 0x6d8 - Guest ES base. */
3270	RTUINT64U u64GuestEsBase;
3271	/** 0x6e0 - Guest CS base. */
3272	RTUINT64U u64GuestCsBase;
3273	/** 0x6e8 - Guest SS base. */
3274	RTUINT64U u64GuestSsBase;
3275	/** 0x6f0 - Guest DS base. */
3276	RTUINT64U u64GuestDsBase;
3277	/** 0x6f8 - Guest FS base. */
3278	RTUINT64U u64GuestFsBase;
3279	/** 0x700 - Guest GS base. */
3280	RTUINT64U u64GuestGsBase;
3281	/** 0x708 - Guest LDTR base. */
3282	RTUINT64U u64GuestLdtrBase;
3283	/** 0x710 - Guest TR base. */
3284	RTUINT64U u64GuestTrBase;
3285	/** 0x718 - Guest GDTR base. */
3286	RTUINT64U u64GuestGdtrBase;
3287	/** 0x720 - Guest IDTR base. */
3288	RTUINT64U u64GuestIdtrBase;
3289	/** 0x728 - Guest DR7. */
3290	RTUINT64U u64GuestDr7;
3291	/** 0x730 - Guest RSP. */
3292	RTUINT64U u64GuestRsp;
3293	/** 0x738 - Guest RIP. */
3294	RTUINT64U u64GuestRip;
3295	/** 0x740 - Guest RFLAGS. */
3296	RTUINT64U u64GuestRFlags;
3297	/** 0x748 - Guest pending debug exception. */
3298	RTUINT64U u64GuestPendingDbgXcpt;
3299	/** 0x750 - Guest SYSENTER ESP. */
3300	RTUINT64U u64GuestSysenterEsp;
3301	/** 0x758 - Guest SYSENTER EIP. */
3302	RTUINT64U u64GuestSysenterEip;
3303	/** 0x760 - Reserved for future. */
3304	RTUINT64U au64Reserved6[32];
3305	/** @} */
3306
3307	/** @name Natural-width Host-state fields.
3308	* @{ */
3309	/** 0x860 - Host CR0. */
3310	RTUINT64U u64HostCr0;
3311	/** 0x868 - Host CR3. */
3312	RTUINT64U u64HostCr3;
3313	/** 0x870 - Host CR4. */
3314	RTUINT64U u64HostCr4;
3315	/** 0x878 - Host FS base. */
3316	RTUINT64U u64HostFsBase;
3317	/** 0x880 - Host GS base. */
3318	RTUINT64U u64HostGsBase;
3319	/** 0x888 - Host TR base. */
3320	RTUINT64U u64HostTrBase;
3321	/** 0x890 - Host GDTR base. */
3322	RTUINT64U u64HostGdtrBase;
3323	/** 0x898 - Host IDTR base. */
3324	RTUINT64U u64HostIdtrBase;
3325	/** 0x8a0 - Host SYSENTER ESP base. */
3326	RTUINT64U u64HostSysenterEsp;
3327	/** 0x8a8 - Host SYSENTER ESP base. */
3328	RTUINT64U u64HostSysenterEip;
3329	/** 0x8b0 - Host RSP. */
3330	RTUINT64U u64HostRsp;
3331	/** 0x8b8 - Host RIP. */
3332	RTUINT64U u64HostRip;
3333	/** 0x8c0 - Reserved for future. */
3334	RTUINT64U au64Reserved7[32];
3335	/** @} */
3336
3337	/** 0x9c0 - Padding. */
3338	uint8_t abPadding[X86_PAGE_4K_SIZE - 0x9c0];
3339	} VMXVVMCS;
3340	#pragma pack()
3341	/** Pointer to the VMXVVMCS struct. */
3342	typedef VMXVVMCS *PVMXVVMCS;
3343	/** Pointer to a const VMXVVMCS struct. */
3344	typedef const VMXVVMCS *PCVMXVVMCS;
3345	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
3346	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
3347	AssertCompileMemberOffset(VMXVVMCS, u32VmxAbortId, 0x004);
3348	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
3349	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x028);
3350	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x03e);
3351	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x062);
3352	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x084);
3353	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x0ec);
3354	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x12c);
3355	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x1a8);
3356	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x1d8);
3357	AssertCompileMemberOffset(VMXVVMCS, u64GuestPhysAddr, 0x320);
3358	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x368);
3359	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x438);
3360	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x4d0);
3361	AssertCompileMemberOffset(VMXVVMCS, u64ExitQual, 0x610);
3362	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x6c0);
3363	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x860);
3364	/** @} */
3365
3366	/**
3367	* Virtual VMX-instruction and VM-exit diagnostics.
3368	*
3369	* These are not the same as VM instruction errors that are enumerated in the Intel
3370	* spec. These are purely internal, fine-grained definitions used for diagnostic
3371	* purposes and are not reported to guest software under the VM-instruction error
3372	* field in its VMCS.
3373	*
3374	* @note Members of this enum are used as array indices, so no gaps are allowed.
3375	* Please update g_apszVmxInstrDiagDesc when you add new fields to this
3376	* enum.
3377	*/
3378	typedef enum
3379	{
3380	/* Internal processing errors. */
3381	kVmxVDiag_Ipe_1 = 0,
3382	kVmxVDiag_Ipe_2,
3383	kVmxVDiag_Ipe_3,
3384	kVmxVDiag_Ipe_4,
3385	kVmxVDiag_Ipe_5,
3386	kVmxVDiag_Ipe_6,
3387	kVmxVDiag_Ipe_7,
3388	kVmxVDiag_Ipe_8,
3389	kVmxVDiag_Ipe_9,
3390	/* VMXON. */
3391	kVmxVDiag_Vmxon_A20M,
3392	kVmxVDiag_Vmxon_Cpl,
3393	kVmxVDiag_Vmxon_Cr0Fixed0,
3394	kVmxVDiag_Vmxon_Cr4Fixed0,
3395	kVmxVDiag_Vmxon_Intercept,
3396	kVmxVDiag_Vmxon_LongModeCS,
3397	kVmxVDiag_Vmxon_MsrFeatCtl,
3398	kVmxVDiag_Vmxon_PtrAbnormal,
3399	kVmxVDiag_Vmxon_PtrAlign,
3400	kVmxVDiag_Vmxon_PtrMap,
3401	kVmxVDiag_Vmxon_PtrReadPhys,
3402	kVmxVDiag_Vmxon_PtrWidth,
3403	kVmxVDiag_Vmxon_RealOrV86Mode,
3404	kVmxVDiag_Vmxon_ShadowVmcs,
3405	kVmxVDiag_Vmxon_Success,
3406	kVmxVDiag_Vmxon_VmxAlreadyRoot,
3407	kVmxVDiag_Vmxon_Vmxe,
3408	kVmxVDiag_Vmxon_VmcsRevId,
3409	kVmxVDiag_Vmxon_VmxRootCpl,
3410	/* VMXOFF. */
3411	kVmxVDiag_Vmxoff_Cpl,
3412	kVmxVDiag_Vmxoff_Intercept,
3413	kVmxVDiag_Vmxoff_LongModeCS,
3414	kVmxVDiag_Vmxoff_RealOrV86Mode,
3415	kVmxVDiag_Vmxoff_Success,
3416	kVmxVDiag_Vmxoff_Vmxe,
3417	kVmxVDiag_Vmxoff_VmxRoot,
3418	/* VMPTRLD. */
3419	kVmxVDiag_Vmptrld_Cpl,
3420	kVmxVDiag_Vmptrld_LongModeCS,
3421	kVmxVDiag_Vmptrld_PtrAbnormal,
3422	kVmxVDiag_Vmptrld_PtrAlign,
3423	kVmxVDiag_Vmptrld_PtrMap,
3424	kVmxVDiag_Vmptrld_PtrReadPhys,
3425	kVmxVDiag_Vmptrld_PtrVmxon,
3426	kVmxVDiag_Vmptrld_PtrWidth,
3427	kVmxVDiag_Vmptrld_RealOrV86Mode,
3428	kVmxVDiag_Vmptrld_ShadowVmcs,
3429	kVmxVDiag_Vmptrld_Success,
3430	kVmxVDiag_Vmptrld_VmcsRevId,
3431	kVmxVDiag_Vmptrld_VmxRoot,
3432	/* VMPTRST. */
3433	kVmxVDiag_Vmptrst_Cpl,
3434	kVmxVDiag_Vmptrst_LongModeCS,
3435	kVmxVDiag_Vmptrst_PtrMap,
3436	kVmxVDiag_Vmptrst_RealOrV86Mode,
3437	kVmxVDiag_Vmptrst_Success,
3438	kVmxVDiag_Vmptrst_VmxRoot,
3439	/* VMCLEAR. */
3440	kVmxVDiag_Vmclear_Cpl,
3441	kVmxVDiag_Vmclear_LongModeCS,
3442	kVmxVDiag_Vmclear_PtrAbnormal,
3443	kVmxVDiag_Vmclear_PtrAlign,
3444	kVmxVDiag_Vmclear_PtrMap,
3445	kVmxVDiag_Vmclear_PtrReadPhys,
3446	kVmxVDiag_Vmclear_PtrVmxon,
3447	kVmxVDiag_Vmclear_PtrWidth,
3448	kVmxVDiag_Vmclear_RealOrV86Mode,
3449	kVmxVDiag_Vmclear_Success,
3450	kVmxVDiag_Vmclear_VmxRoot,
3451	/* VMWRITE. */
3452	kVmxVDiag_Vmwrite_Cpl,
3453	kVmxVDiag_Vmwrite_FieldInvalid,
3454	kVmxVDiag_Vmwrite_FieldRo,
3455	kVmxVDiag_Vmwrite_LinkPtrInvalid,
3456	kVmxVDiag_Vmwrite_LongModeCS,
3457	kVmxVDiag_Vmwrite_PtrInvalid,
3458	kVmxVDiag_Vmwrite_PtrMap,
3459	kVmxVDiag_Vmwrite_RealOrV86Mode,
3460	kVmxVDiag_Vmwrite_Success,
3461	kVmxVDiag_Vmwrite_VmxRoot,
3462	/* VMREAD. */
3463	kVmxVDiag_Vmread_Cpl,
3464	kVmxVDiag_Vmread_FieldInvalid,
3465	kVmxVDiag_Vmread_LinkPtrInvalid,
3466	kVmxVDiag_Vmread_LongModeCS,
3467	kVmxVDiag_Vmread_PtrInvalid,
3468	kVmxVDiag_Vmread_PtrMap,
3469	kVmxVDiag_Vmread_RealOrV86Mode,
3470	kVmxVDiag_Vmread_Success,
3471	kVmxVDiag_Vmread_VmxRoot,
3472	/* VMLAUNCH/VMRESUME. */
3473	kVmxVDiag_Vmentry_AddrApicAccess,
3474	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
3475	kVmxVDiag_Vmentry_AddrExitMsrLoad,
3476	kVmxVDiag_Vmentry_AddrExitMsrStore,
3477	kVmxVDiag_Vmentry_AddrIoBitmapA,
3478	kVmxVDiag_Vmentry_AddrIoBitmapB,
3479	kVmxVDiag_Vmentry_AddrMsrBitmap,
3480	kVmxVDiag_Vmentry_AddrVirtApicPage,
3481	kVmxVDiag_Vmentry_AddrVmreadBitmap,
3482	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
3483	kVmxVDiag_Vmentry_ApicRegVirt,
3484	kVmxVDiag_Vmentry_BlocKMovSS,
3485	kVmxVDiag_Vmentry_Cpl,
3486	kVmxVDiag_Vmentry_Cr3TargetCount,
3487	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
3488	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
3489	kVmxVDiag_Vmentry_EntryInstrLen,
3490	kVmxVDiag_Vmentry_EntryInstrLenZero,
3491	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
3492	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
3493	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
3494	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
3495	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
3496	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
3497	kVmxVDiag_Vmentry_GuestActStateHlt,
3498	kVmxVDiag_Vmentry_GuestActStateRsvd,
3499	kVmxVDiag_Vmentry_GuestActStateShutdown,
3500	kVmxVDiag_Vmentry_GuestActStateSsDpl,
3501	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
3502	kVmxVDiag_Vmentry_GuestCr0Fixed0,
3503	kVmxVDiag_Vmentry_GuestCr0Fixed1,
3504	kVmxVDiag_Vmentry_GuestCr0PgPe,
3505	kVmxVDiag_Vmentry_GuestCr3,
3506	kVmxVDiag_Vmentry_GuestCr4Fixed0,
3507	kVmxVDiag_Vmentry_GuestCr4Fixed1,
3508	kVmxVDiag_Vmentry_GuestDebugCtl,
3509	kVmxVDiag_Vmentry_GuestDr7,
3510	kVmxVDiag_Vmentry_GuestEferMsr,
3511	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
3512	kVmxVDiag_Vmentry_GuestGdtrBase,
3513	kVmxVDiag_Vmentry_GuestGdtrLimit,
3514	kVmxVDiag_Vmentry_GuestIdtrBase,
3515	kVmxVDiag_Vmentry_GuestIdtrLimit,
3516	kVmxVDiag_Vmentry_GuestIntStateEnclave,
3517	kVmxVDiag_Vmentry_GuestIntStateExtInt,
3518	kVmxVDiag_Vmentry_GuestIntStateNmi,
3519	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
3520	kVmxVDiag_Vmentry_GuestIntStateRsvd,
3521	kVmxVDiag_Vmentry_GuestIntStateSmi,
3522	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
3523	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
3524	kVmxVDiag_Vmentry_GuestPae,
3525	kVmxVDiag_Vmentry_GuestPatMsr,
3526	kVmxVDiag_Vmentry_GuestPcide,
3527	kVmxVDiag_Vmentry_GuestRip,
3528	kVmxVDiag_Vmentry_GuestRipRsvd,
3529	kVmxVDiag_Vmentry_GuestRFlagsIf,
3530	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
3531	kVmxVDiag_Vmentry_GuestRFlagsVm,
3532	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
3533	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
3534	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
3535	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
3536	kVmxVDiag_Vmentry_GuestSegAttrCsType,
3537	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
3538	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
3539	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
3540	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
3541	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
3542	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
3543	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
3544	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
3545	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
3546	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
3547	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
3548	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
3549	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
3550	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
3551	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
3552	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
3553	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
3554	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
3555	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
3556	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
3557	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
3558	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
3559	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
3560	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
3561	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
3562	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
3563	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
3564	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
3565	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
3566	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
3567	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
3568	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
3569	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
3570	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
3571	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
3572	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
3573	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
3574	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
3575	kVmxVDiag_Vmentry_GuestSegAttrSsType,
3576	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
3577	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
3578	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
3579	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
3580	kVmxVDiag_Vmentry_GuestSegAttrTrType,
3581	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
3582	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
3583	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
3584	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
3585	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
3586	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
3587	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
3588	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
3589	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
3590	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
3591	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
3592	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
3593	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
3594	kVmxVDiag_Vmentry_GuestSegBaseCs,
3595	kVmxVDiag_Vmentry_GuestSegBaseDs,
3596	kVmxVDiag_Vmentry_GuestSegBaseEs,
3597	kVmxVDiag_Vmentry_GuestSegBaseFs,
3598	kVmxVDiag_Vmentry_GuestSegBaseGs,
3599	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
3600	kVmxVDiag_Vmentry_GuestSegBaseSs,
3601	kVmxVDiag_Vmentry_GuestSegBaseTr,
3602	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
3603	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
3604	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
3605	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
3606	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
3607	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
3608	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
3609	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
3610	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
3611	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
3612	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
3613	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
3614	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
3615	kVmxVDiag_Vmentry_GuestSegSelLdtr,
3616	kVmxVDiag_Vmentry_GuestSegSelTr,
3617	kVmxVDiag_Vmentry_GuestSysenterEspEip,
3618	kVmxVDiag_Vmentry_HostCr0Fixed0,
3619	kVmxVDiag_Vmentry_HostCr0Fixed1,
3620	kVmxVDiag_Vmentry_HostCr3,
3621	kVmxVDiag_Vmentry_HostCr4Fixed0,
3622	kVmxVDiag_Vmentry_HostCr4Fixed1,
3623	kVmxVDiag_Vmentry_HostCr4Pae,
3624	kVmxVDiag_Vmentry_HostCr4Pcide,
3625	kVmxVDiag_Vmentry_HostCsTr,
3626	kVmxVDiag_Vmentry_HostEferMsr,
3627	kVmxVDiag_Vmentry_HostEferMsrRsvd,
3628	kVmxVDiag_Vmentry_HostGuestLongMode,
3629	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
3630	kVmxVDiag_Vmentry_HostLongMode,
3631	kVmxVDiag_Vmentry_HostPatMsr,
3632	kVmxVDiag_Vmentry_HostRip,
3633	kVmxVDiag_Vmentry_HostRipRsvd,
3634	kVmxVDiag_Vmentry_HostSel,
3635	kVmxVDiag_Vmentry_HostSegBase,
3636	kVmxVDiag_Vmentry_HostSs,
3637	kVmxVDiag_Vmentry_HostSysenterEspEip,
3638	kVmxVDiag_Vmentry_LongModeCS,
3639	kVmxVDiag_Vmentry_NmiWindowExit,
3640	kVmxVDiag_Vmentry_PinCtlsAllowed1,
3641	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
3642	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
3643	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
3644	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
3645	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
3646	kVmxVDiag_Vmentry_PtrInvalid,
3647	kVmxVDiag_Vmentry_PtrReadPhys,
3648	kVmxVDiag_Vmentry_RealOrV86Mode,
3649	kVmxVDiag_Vmentry_SavePreemptTimer,
3650	kVmxVDiag_Vmentry_Success,
3651	kVmxVDiag_Vmentry_TprThresholdRsvd,
3652	kVmxVDiag_Vmentry_TprThresholdVTpr,
3653	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
3654	kVmxVDiag_Vmentry_VirtIntDelivery,
3655	kVmxVDiag_Vmentry_VirtNmi,
3656	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
3657	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
3658	kVmxVDiag_Vmentry_VmcsClear,
3659	kVmxVDiag_Vmentry_VmcsLaunch,
3660	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
3661	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
3662	kVmxVDiag_Vmentry_VmxRoot,
3663	kVmxVDiag_Vmentry_Vpid,
3664	/* Last member for determining array index limit. */
3665	kVmxVDiag_End
3666	} VMXVDIAG;
3667	AssertCompileSize(VMXVDIAG, 4);
3668
3669
3670	/** @defgroup grp_hm_vmx_inline VMX Inline Helpers
3671	* @{
3672	*/
3673	/**
3674	* Gets the effective width of a VMCS field given it's encoding adjusted for
3675	* HIGH/FULL access for 64-bit fields.
3676	*
3677	* @returns The effective VMCS field width.
3678	* @param uFieldEnc The VMCS field encoding.
3679	*
3680	* @remarks Warning! This function does not verify the encoding is for a valid and
3681	* supported VMCS field.
3682	*/
3683	DECLINLINE(uint8_t) HMVmxGetVmcsFieldWidthEff(uint32_t uFieldEnc)
3684	{
3685	/* Only the "HIGH" parts of all 64-bit fields have bit 0 set. */
3686	if (uFieldEnc & RT_BIT(0))
3687	return VMXVMCSFIELDWIDTH_32BIT;
3688
3689	/* Bits 13:14 contains the width of the VMCS field, see VMXVMCSFIELDWIDTH_XXX. */
3690	return (uFieldEnc >> 13) & 0x3;
3691	}
3692
3693	/**
3694	* Returns whether the given VMCS field is a read-only VMCS field or not.
3695	*
3696	* @returns @c true if it's a read-only field, @c false otherwise.
3697	* @param uFieldEnc The VMCS field encoding.
3698	*
3699	* @remarks Warning! This function does not verify the encoding is for a valid and
3700	* supported VMCS field.
3701	*/
3702	DECLINLINE(bool) HMVmxIsVmcsFieldReadOnly(uint32_t uFieldEnc)
3703	{
3704	/* See Intel spec. B.4.2 "Natural-Width Read-Only Data Fields". */
3705	return (RT_BF_GET(uFieldEnc, VMX_BF_VMCS_ENC_TYPE) == VMXVMCSFIELDTYPE_VMEXIT_INFO);
3706	}
3707
3708	/**
3709	* Returns whether the given VM-entry interruption-information type is valid or not.
3710	*
3711	* @returns @c true if it's a valid type, @c false otherwise.
3712	* @param fSupportsMTF Whether the Monitor-Trap Flag CPU feature is supported.
3713	* @param uType The VM-entry interruption-information type.
3714	*/
3715	DECLINLINE(bool) HMVmxIsEntryIntInfoTypeValid(bool fSupportsMTF, uint8_t uType)
3716	{
3717	/* See Intel spec. 26.2.1.3 "VM-Entry Control Fields". */
3718	switch (uType)
3719	{
3720	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
3721	case VMX_ENTRY_INT_INFO_TYPE_NMI:
3722	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
3723	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
3724	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
3725	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: return true;
3726	case VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT: return fSupportsMTF;
3727	default:
3728	return false;
3729	}
3730	}
3731
3732	/**
3733	* Returns whether the given VM-entry interruption-information vector and type
3734	* combination is valid or not.
3735	*
3736	* @returns @c true if it's a valid vector/type combination, @c false otherwise.
3737	* @param uVector The VM-entry interruption-information vector.
3738	* @param uType The VM-entry interruption-information type.
3739	*
3740	* @remarks Warning! This function does not validate the type field individually.
3741	* Use it after verifying type is valid using HMVmxIsEntryIntInfoTypeValid.
3742	*/
3743	DECLINLINE(bool) HMVmxIsEntryIntInfoVectorValid(uint8_t uVector, uint8_t uType)
3744	{
3745	/* See Intel spec. 26.2.1.3 "VM-Entry Control Fields". */
3746	if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
3747	&& uVector != X86_XCPT_NMI)
3748	return false;
3749	if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
3750	&& uVector > X86_XCPT_LAST)
3751	return false;
3752	if ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
3753	&& uVector != 0)
3754	return false;
3755	return true;
3756	}
3757	/** @} */
3758
3759
3760	/** @defgroup grp_hm_vmx_asm VMX Assembly Helpers
3761	* @{
3762	*/
3763
3764	/**
3765	* Restores some host-state fields that need not be done on every VM-exit.
3766	*
3767	* @returns VBox status code.
3768	* @param fRestoreHostFlags Flags of which host registers needs to be
3769	* restored.
3770	* @param pRestoreHost Pointer to the host-restore structure.
3771	*/
3772	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
3773
3774
3775	/**
3776	* Dispatches an NMI to the host.
3777	*/
3778	DECLASM(int) VMXDispatchHostNmi(void);
3779
3780
3781	/**
3782	* Executes VMXON.
3783	*
3784	* @returns VBox status code.
3785	* @param HCPhysVmxOn Physical address of VMXON structure.
3786	*/
3787	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3788	DECLASM(int) VMXEnable(RTHCPHYS HCPhysVmxOn);
3789	#else
3790	DECLINLINE(int) VMXEnable(RTHCPHYS HCPhysVmxOn)
3791	{
3792	# if RT_INLINE_ASM_GNU_STYLE
3793	int rc = VINF_SUCCESS;
3794	__asm__ __volatile__ (
3795	"push %3 \n\t"
3796	"push %2 \n\t"
3797	".byte 0xf3, 0x0f, 0xc7, 0x34, 0x24 # VMXON [esp] \n\t"
3798	"ja 2f \n\t"
3799	"je 1f \n\t"
3800	"movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
3801	"jmp 2f \n\t"
3802	"1: \n\t"
3803	"movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
3804	"2: \n\t"
3805	"add $8, %%esp \n\t"
3806	:"=rm"(rc)
3807	:"0"(VINF_SUCCESS),
3808	"ir"((uint32_t)HCPhysVmxOn), /* don't allow direct memory reference here, */
3809	"ir"((uint32_t)(HCPhysVmxOn >> 32)) /* this would not work with -fomit-frame-pointer */
3810	:"memory"
3811	);
3812	return rc;
3813
3814	# elif VMX_USE_MSC_INTRINSICS
3815	unsigned char rcMsc = __vmx_on(&HCPhysVmxOn);
3816	if (RT_LIKELY(rcMsc == 0))
3817	return VINF_SUCCESS;
3818	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
3819
3820	# else
3821	int rc = VINF_SUCCESS;
3822	__asm
3823	{
3824	push dword ptr [HCPhysVmxOn + 4]
3825	push dword ptr [HCPhysVmxOn]
3826	_emit 0xf3
3827	_emit 0x0f
3828	_emit 0xc7
3829	_emit 0x34
3830	_emit 0x24 /* VMXON [esp] */
3831	jnc vmxon_good
3832	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
3833	jmp the_end
3834
3835	vmxon_good:
3836	jnz the_end
3837	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
3838	the_end:
3839	add esp, 8
3840	}
3841	return rc;
3842	# endif
3843	}
3844	#endif
3845
3846
3847	/**
3848	* Executes VMXOFF.
3849	*/
3850	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3851	DECLASM(void) VMXDisable(void);
3852	#else
3853	DECLINLINE(void) VMXDisable(void)
3854	{
3855	# if RT_INLINE_ASM_GNU_STYLE
3856	__asm__ __volatile__ (
3857	".byte 0x0f, 0x01, 0xc4 # VMXOFF \n\t"
3858	);
3859
3860	# elif VMX_USE_MSC_INTRINSICS
3861	__vmx_off();
3862
3863	# else
3864	__asm
3865	{
3866	_emit 0x0f
3867	_emit 0x01
3868	_emit 0xc4 /* VMXOFF */
3869	}
3870	# endif
3871	}
3872	#endif
3873
3874
3875	/**
3876	* Executes VMCLEAR.
3877	*
3878	* @returns VBox status code.
3879	* @param HCPhysVmcs Physical address of VM control structure.
3880	*/
3881	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3882	DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
3883	#else
3884	DECLINLINE(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs)
3885	{
3886	# if RT_INLINE_ASM_GNU_STYLE
3887	int rc = VINF_SUCCESS;
3888	__asm__ __volatile__ (
3889	"push %3 \n\t"
3890	"push %2 \n\t"
3891	".byte 0x66, 0x0f, 0xc7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
3892	"jnc 1f \n\t"
3893	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
3894	"1: \n\t"
3895	"add $8, %%esp \n\t"
3896	:"=rm"(rc)
3897	:"0"(VINF_SUCCESS),
3898	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
3899	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this would not work with -fomit-frame-pointer */
3900	:"memory"
3901	);
3902	return rc;
3903
3904	# elif VMX_USE_MSC_INTRINSICS
3905	unsigned char rcMsc = __vmx_vmclear(&HCPhysVmcs);
3906	if (RT_LIKELY(rcMsc == 0))
3907	return VINF_SUCCESS;
3908	return VERR_VMX_INVALID_VMCS_PTR;
3909
3910	# else
3911	int rc = VINF_SUCCESS;
3912	__asm
3913	{
3914	push dword ptr [HCPhysVmcs + 4]
3915	push dword ptr [HCPhysVmcs]
3916	_emit 0x66
3917	_emit 0x0f
3918	_emit 0xc7
3919	_emit 0x34
3920	_emit 0x24 /* VMCLEAR [esp] */
3921	jnc success
3922	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
3923	success:
3924	add esp, 8
3925	}
3926	return rc;
3927	# endif
3928	}
3929	#endif
3930
3931
3932	/**
3933	* Executes VMPTRLD.
3934	*
3935	* @returns VBox status code.
3936	* @param HCPhysVmcs Physical address of VMCS structure.
3937	*/
3938	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3939	DECLASM(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs);
3940	#else
3941	DECLINLINE(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs)
3942	{
3943	# if RT_INLINE_ASM_GNU_STYLE
3944	int rc = VINF_SUCCESS;
3945	__asm__ __volatile__ (
3946	"push %3 \n\t"
3947	"push %2 \n\t"
3948	".byte 0x0f, 0xc7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
3949	"jnc 1f \n\t"
3950	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
3951	"1: \n\t"
3952	"add $8, %%esp \n\t"
3953	:"=rm"(rc)
3954	:"0"(VINF_SUCCESS),
3955	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
3956	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this will not work with -fomit-frame-pointer */
3957	);
3958	return rc;
3959
3960	# elif VMX_USE_MSC_INTRINSICS
3961	unsigned char rcMsc = __vmx_vmptrld(&HCPhysVmcs);
3962	if (RT_LIKELY(rcMsc == 0))
3963	return VINF_SUCCESS;
3964	return VERR_VMX_INVALID_VMCS_PTR;
3965
3966	# else
3967	int rc = VINF_SUCCESS;
3968	__asm
3969	{
3970	push dword ptr [HCPhysVmcs + 4]
3971	push dword ptr [HCPhysVmcs]
3972	_emit 0x0f
3973	_emit 0xc7
3974	_emit 0x34
3975	_emit 0x24 /* VMPTRLD [esp] */
3976	jnc success
3977	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
3978
3979	success:
3980	add esp, 8
3981	}
3982	return rc;
3983	# endif
3984	}
3985	#endif
3986
3987
3988	/**
3989	* Executes VMPTRST.
3990	*
3991	* @returns VBox status code.
3992	* @param pHCPhysVmcs Where to store the physical address of the current
3993	* VMCS.
3994	*/
3995	DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
3996
3997
3998	/**
3999	* Executes VMWRITE.
4000	*
4001	* @returns VBox status code.
4002	* @retval VINF_SUCCESS.
4003	* @retval VERR_VMX_INVALID_VMCS_PTR.
4004	* @retval VERR_VMX_INVALID_VMCS_FIELD.
4005	*
4006	* @param uFieldEnc VMCS field encoding.
4007	* @param u32Val The 32-bit value to set.
4008	*
4009	* @remarks The values of the two status codes can be OR'ed together, the result
4010	* will be VERR_VMX_INVALID_VMCS_PTR.
4011	*/
4012	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
4013	DECLASM(int) VMXWriteVmcs32(uint32_t uFieldEnc, uint32_t u32Val);
4014	#else
4015	DECLINLINE(int) VMXWriteVmcs32(uint32_t uFieldEnc, uint32_t u32Val)
4016	{
4017	# if RT_INLINE_ASM_GNU_STYLE
4018	int rc = VINF_SUCCESS;
4019	__asm__ __volatile__ (
4020	".byte 0x0f, 0x79, 0xc2 # VMWRITE eax, edx \n\t"
4021	"ja 2f \n\t"
4022	"je 1f \n\t"
4023	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
4024	"jmp 2f \n\t"
4025	"1: \n\t"
4026	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
4027	"2: \n\t"
4028	:"=rm"(rc)
4029	:"0"(VINF_SUCCESS),
4030	"a"(uFieldEnc),
4031	"d"(u32Val)
4032	);
4033	return rc;
4034
4035	# elif VMX_USE_MSC_INTRINSICS
4036	unsigned char rcMsc = __vmx_vmwrite(uFieldEnc, u32Val);
4037	if (RT_LIKELY(rcMsc == 0))
4038	return VINF_SUCCESS;
4039	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
4040
4041	#else
4042	int rc = VINF_SUCCESS;
4043	__asm
4044	{
4045	push dword ptr [u32Val]
4046	mov eax, [uFieldEnc]
4047	_emit 0x0f
4048	_emit 0x79
4049	_emit 0x04
4050	_emit 0x24 /* VMWRITE eax, [esp] */
4051	jnc valid_vmcs
4052	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
4053	jmp the_end
4054
4055	valid_vmcs:
4056	jnz the_end
4057	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
4058	the_end:
4059	add esp, 4
4060	}
4061	return rc;
4062	# endif
4063	}
4064	#endif
4065
4066	/**
4067	* Executes VMWRITE.
4068	*
4069	* @returns VBox status code.
4070	* @retval VINF_SUCCESS.
4071	* @retval VERR_VMX_INVALID_VMCS_PTR.
4072	* @retval VERR_VMX_INVALID_VMCS_FIELD.
4073	*
4074	* @param uFieldEnc The VMCS field encoding.
4075	* @param u64Val The 16, 32 or 64-bit value to set.
4076	*
4077	* @remarks The values of the two status codes can be OR'ed together, the result
4078	* will be VERR_VMX_INVALID_VMCS_PTR.
4079	*/
4080	#if !defined(RT_ARCH_X86)
4081	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
4082	DECLASM(int) VMXWriteVmcs64(uint32_t uFieldEnc, uint64_t u64Val);
4083	# else /* VMX_USE_MSC_INTRINSICS */
4084	DECLINLINE(int) VMXWriteVmcs64(uint32_t uFieldEnc, uint64_t u64Val)
4085	{
4086	unsigned char rcMsc = __vmx_vmwrite(uFieldEnc, u64Val);
4087	if (RT_LIKELY(rcMsc == 0))
4088	return VINF_SUCCESS;
4089	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
4090	}
4091	# endif /* VMX_USE_MSC_INTRINSICS */
4092	#else
4093	# define VMXWriteVmcs64(uFieldEnc, u64Val) VMXWriteVmcs64Ex(pVCpu, uFieldEnc, u64Val) /** @todo dead ugly, picking up pVCpu like this */
4094	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t uFieldEnc, uint64_t u64Val);
4095	#endif
4096
4097	#if ARCH_BITS == 32
4098	# define VMXWriteVmcsHstN VMXWriteVmcs32
4099	# define VMXWriteVmcsGstN(uFieldEnc, u64Val) VMXWriteVmcs64Ex(pVCpu, uFieldEnc, u64Val)
4100	#else /* ARCH_BITS == 64 */
4101	# define VMXWriteVmcsHstN VMXWriteVmcs64
4102	# define VMXWriteVmcsGstN VMXWriteVmcs64
4103	#endif
4104
4105
4106	/**
4107	* Invalidate a page using INVEPT.
4108	*
4109	* @returns VBox status code.
4110	* @param enmFlush Type of flush.
4111	* @param pDescriptor Pointer to the descriptor.
4112	*/
4113	DECLASM(int) VMXR0InvEPT(VMXTLBFLUSHEPT enmFlush, uint64_t *pDescriptor);
4114
4115
4116	/**
4117	* Invalidate a page using INVVPID.
4118	*
4119	* @returns VBox status code.
4120	* @param enmFlush Type of flush.
4121	* @param pDescriptor Pointer to the descriptor.
4122	*/
4123	DECLASM(int) VMXR0InvVPID(VMXTLBFLUSHVPID enmFlush, uint64_t *pDescriptor);
4124
4125
4126	/**
4127	* Executes VMREAD for a 32-bit field.
4128	*
4129	* @returns VBox status code.
4130	* @retval VINF_SUCCESS.
4131	* @retval VERR_VMX_INVALID_VMCS_PTR.
4132	* @retval VERR_VMX_INVALID_VMCS_FIELD.
4133	*
4134	* @param uFieldEnc The VMCS field encoding.
4135	* @param pData Where to store VMCS field value.
4136	*
4137	* @remarks The values of the two status codes can be OR'ed together, the result
4138	* will be VERR_VMX_INVALID_VMCS_PTR.
4139	*/
4140	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
4141	DECLASM(int) VMXReadVmcs32(uint32_t uFieldEnc, uint32_t *pData);
4142	#else
4143	DECLINLINE(int) VMXReadVmcs32(uint32_t uFieldEnc, uint32_t *pData)
4144	{
4145	# if RT_INLINE_ASM_GNU_STYLE
4146	int rc = VINF_SUCCESS;
4147	__asm__ __volatile__ (
4148	"movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
4149	".byte 0x0f, 0x78, 0xc2 # VMREAD eax, edx \n\t"
4150	"ja 2f \n\t"
4151	"je 1f \n\t"
4152	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
4153	"jmp 2f \n\t"
4154	"1: \n\t"
4155	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
4156	"2: \n\t"
4157	:"=&r"(rc),
4158	"=d"(*pData)
4159	:"a"(uFieldEnc),
4160	"d"(0)
4161	);
4162	return rc;
4163
4164	# elif VMX_USE_MSC_INTRINSICS
4165	unsigned char rcMsc;
4166	# if ARCH_BITS == 32
4167	rcMsc = __vmx_vmread(uFieldEnc, pData);
4168	# else
4169	uint64_t u64Tmp;
4170	rcMsc = __vmx_vmread(uFieldEnc, &u64Tmp);
4171	*pData = (uint32_t)u64Tmp;
4172	# endif
4173	if (RT_LIKELY(rcMsc == 0))
4174	return VINF_SUCCESS;
4175	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
4176
4177	#else
4178	int rc = VINF_SUCCESS;
4179	__asm
4180	{
4181	sub esp, 4
4182	mov dword ptr [esp], 0
4183	mov eax, [uFieldEnc]
4184	_emit 0x0f
4185	_emit 0x78
4186	_emit 0x04
4187	_emit 0x24 /* VMREAD eax, [esp] */
4188	mov edx, pData
4189	pop dword ptr [edx]
4190	jnc valid_vmcs
4191	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
4192	jmp the_end
4193
4194	valid_vmcs:
4195	jnz the_end
4196	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
4197	the_end:
4198	}
4199	return rc;
4200	# endif
4201	}
4202	#endif
4203
4204	/**
4205	* Executes VMREAD for a 64-bit field.
4206	*
4207	* @returns VBox status code.
4208	* @retval VINF_SUCCESS.
4209	* @retval VERR_VMX_INVALID_VMCS_PTR.
4210	* @retval VERR_VMX_INVALID_VMCS_FIELD.
4211	*
4212	* @param uFieldEnc The VMCS field encoding.
4213	* @param pData Where to store VMCS field value.
4214	*
4215	* @remarks The values of the two status codes can be OR'ed together, the result
4216	* will be VERR_VMX_INVALID_VMCS_PTR.
4217	*/
4218	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS)
4219	DECLASM(int) VMXReadVmcs64(uint32_t uFieldEnc, uint64_t *pData);
4220	#else
4221	DECLINLINE(int) VMXReadVmcs64(uint32_t uFieldEnc, uint64_t *pData)
4222	{
4223	# if VMX_USE_MSC_INTRINSICS
4224	unsigned char rcMsc;
4225	# if ARCH_BITS == 32
4226	size_t uLow;
4227	size_t uHigh;
4228	rcMsc = __vmx_vmread(uFieldEnc, &uLow);
4229	rcMsc \|= __vmx_vmread(uFieldEnc + 1, &uHigh);
4230	*pData = RT_MAKE_U64(uLow, uHigh);
4231	# else
4232	rcMsc = __vmx_vmread(uFieldEnc, pData);
4233	# endif
4234	if (RT_LIKELY(rcMsc == 0))
4235	return VINF_SUCCESS;
4236	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
4237
4238	# elif ARCH_BITS == 32
4239	int rc;
4240	uint32_t val_hi, val;
4241	rc = VMXReadVmcs32(uFieldEnc, &val);
4242	rc \|= VMXReadVmcs32(uFieldEnc + 1, &val_hi);
4243	AssertRC(rc);
4244	*pData = RT_MAKE_U64(val, val_hi);
4245	return rc;
4246
4247	# else
4248	# error "Shouldn't be here..."
4249	# endif
4250	}
4251	#endif
4252
4253
4254	/**
4255	* Gets the last instruction error value from the current VMCS.
4256	*
4257	* @returns VBox status code.
4258	*/
4259	DECLINLINE(uint32_t) VMXGetLastError(void)
4260	{
4261	#if ARCH_BITS == 64
4262	uint64_t uLastError = 0;
4263	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
4264	AssertRC(rc);
4265	return (uint32_t)uLastError;
4266
4267	#else /* 32-bit host: */
4268	uint32_t uLastError = 0;
4269	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
4270	AssertRC(rc);
4271	return uLastError;
4272	#endif
4273	}
4274
4275	/** @} */
4276
4277	/** @} */
4278
4279	#endif
4280

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 74175

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