hm_vmx.h@ 43657

Last change on this file since 43657 was 43657, checked in by vboxsync, 12 years ago
VMM: APIC refactor. Moved APIC base MSR to the VCPU (where it belongs) for lockless accesses.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 64.9 KB

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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2010 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/** @defgroup grp_vmx vmx Types and Definitions
35	* @ingroup grp_hm
36	* @{
37	*/
38
39	/** @name VMX EPT paging structures
40	* @{
41	*/
42
43	/**
44	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
45	*/
46	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
47
48	/**
49	* EPT Page Directory Pointer Entry. Bit view.
50	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
51	* this did cause trouble with one compiler/version).
52	*/
53	#pragma pack(1)
54	typedef struct EPTPML4EBITS
55	{
56	/** Present bit. */
57	uint64_t u1Present : 1;
58	/** Writable bit. */
59	uint64_t u1Write : 1;
60	/** Executable bit. */
61	uint64_t u1Execute : 1;
62	/** Reserved (must be 0). */
63	uint64_t u5Reserved : 5;
64	/** Available for software. */
65	uint64_t u4Available : 4;
66	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
67	uint64_t u40PhysAddr : 40;
68	/** Availabe for software. */
69	uint64_t u12Available : 12;
70	} EPTPML4EBITS;
71	#pragma pack()
72	AssertCompileSize(EPTPML4EBITS, 8);
73
74	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
75	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
76	/** The page shift to get the PML4 index. */
77	#define EPT_PML4_SHIFT X86_PML4_SHIFT
78	/** The PML4 index mask (apply to a shifted page address). */
79	#define EPT_PML4_MASK X86_PML4_MASK
80
81	/**
82	* EPT PML4E.
83	*/
84	#pragma pack(1)
85	typedef union EPTPML4E
86	{
87	/** Normal view. */
88	EPTPML4EBITS n;
89	/** Unsigned integer view. */
90	X86PGPAEUINT u;
91	/** 64 bit unsigned integer view. */
92	uint64_t au64[1];
93	/** 32 bit unsigned integer view. */
94	uint32_t au32[2];
95	} EPTPML4E;
96	#pragma pack()
97	/** Pointer to a PML4 table entry. */
98	typedef EPTPML4E *PEPTPML4E;
99	/** Pointer to a const PML4 table entry. */
100	typedef const EPTPML4E *PCEPTPML4E;
101	AssertCompileSize(EPTPML4E, 8);
102
103	/**
104	* EPT PML4 Table.
105	*/
106	#pragma pack(1)
107	typedef struct EPTPML4
108	{
109	EPTPML4E a[EPT_PG_ENTRIES];
110	} EPTPML4;
111	#pragma pack()
112	/** Pointer to an EPT PML4 Table. */
113	typedef EPTPML4 *PEPTPML4;
114	/** Pointer to a const EPT PML4 Table. */
115	typedef const EPTPML4 *PCEPTPML4;
116
117	/**
118	* EPT Page Directory Pointer Entry. Bit view.
119	*/
120	#pragma pack(1)
121	typedef struct EPTPDPTEBITS
122	{
123	/** Present bit. */
124	uint64_t u1Present : 1;
125	/** Writable bit. */
126	uint64_t u1Write : 1;
127	/** Executable bit. */
128	uint64_t u1Execute : 1;
129	/** Reserved (must be 0). */
130	uint64_t u5Reserved : 5;
131	/** Available for software. */
132	uint64_t u4Available : 4;
133	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
134	uint64_t u40PhysAddr : 40;
135	/** Availabe for software. */
136	uint64_t u12Available : 12;
137	} EPTPDPTEBITS;
138	#pragma pack()
139	AssertCompileSize(EPTPDPTEBITS, 8);
140
141	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
142	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
143	/** The page shift to get the PDPT index. */
144	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
145	/** The PDPT index mask (apply to a shifted page address). */
146	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
147
148	/**
149	* EPT Page Directory Pointer.
150	*/
151	#pragma pack(1)
152	typedef union EPTPDPTE
153	{
154	/** Normal view. */
155	EPTPDPTEBITS n;
156	/** Unsigned integer view. */
157	X86PGPAEUINT u;
158	/** 64 bit unsigned integer view. */
159	uint64_t au64[1];
160	/** 32 bit unsigned integer view. */
161	uint32_t au32[2];
162	} EPTPDPTE;
163	#pragma pack()
164	/** Pointer to an EPT Page Directory Pointer Entry. */
165	typedef EPTPDPTE *PEPTPDPTE;
166	/** Pointer to a const EPT Page Directory Pointer Entry. */
167	typedef const EPTPDPTE *PCEPTPDPTE;
168	AssertCompileSize(EPTPDPTE, 8);
169
170	/**
171	* EPT Page Directory Pointer Table.
172	*/
173	#pragma pack(1)
174	typedef struct EPTPDPT
175	{
176	EPTPDPTE a[EPT_PG_ENTRIES];
177	} EPTPDPT;
178	#pragma pack()
179	/** Pointer to an EPT Page Directory Pointer Table. */
180	typedef EPTPDPT *PEPTPDPT;
181	/** Pointer to a const EPT Page Directory Pointer Table. */
182	typedef const EPTPDPT *PCEPTPDPT;
183
184
185	/**
186	* EPT Page Directory Table Entry. Bit view.
187	*/
188	#pragma pack(1)
189	typedef struct EPTPDEBITS
190	{
191	/** Present bit. */
192	uint64_t u1Present : 1;
193	/** Writable bit. */
194	uint64_t u1Write : 1;
195	/** Executable bit. */
196	uint64_t u1Execute : 1;
197	/** Reserved (must be 0). */
198	uint64_t u4Reserved : 4;
199	/** Big page (must be 0 here). */
200	uint64_t u1Size : 1;
201	/** Available for software. */
202	uint64_t u4Available : 4;
203	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
204	uint64_t u40PhysAddr : 40;
205	/** Availabe for software. */
206	uint64_t u12Available : 12;
207	} EPTPDEBITS;
208	#pragma pack()
209	AssertCompileSize(EPTPDEBITS, 8);
210
211	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
212	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
213	/** The page shift to get the PD index. */
214	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
215	/** The PD index mask (apply to a shifted page address). */
216	#define EPT_PD_MASK X86_PD_PAE_MASK
217
218	/**
219	* EPT 2MB Page Directory Table Entry. Bit view.
220	*/
221	#pragma pack(1)
222	typedef struct EPTPDE2MBITS
223	{
224	/** Present bit. */
225	uint64_t u1Present : 1;
226	/** Writable bit. */
227	uint64_t u1Write : 1;
228	/** Executable bit. */
229	uint64_t u1Execute : 1;
230	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
231	uint64_t u3EMT : 3;
232	/** Ignore PAT memory type */
233	uint64_t u1IgnorePAT : 1;
234	/** Big page (must be 1 here). */
235	uint64_t u1Size : 1;
236	/** Available for software. */
237	uint64_t u4Available : 4;
238	/** Reserved (must be 0). */
239	uint64_t u9Reserved : 9;
240	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
241	uint64_t u31PhysAddr : 31;
242	/** Availabe for software. */
243	uint64_t u12Available : 12;
244	} EPTPDE2MBITS;
245	#pragma pack()
246	AssertCompileSize(EPTPDE2MBITS, 8);
247
248	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
249	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
250
251	/**
252	* EPT Page Directory Table Entry.
253	*/
254	#pragma pack(1)
255	typedef union EPTPDE
256	{
257	/** Normal view. */
258	EPTPDEBITS n;
259	/** 2MB view (big). */
260	EPTPDE2MBITS b;
261	/** Unsigned integer view. */
262	X86PGPAEUINT u;
263	/** 64 bit unsigned integer view. */
264	uint64_t au64[1];
265	/** 32 bit unsigned integer view. */
266	uint32_t au32[2];
267	} EPTPDE;
268	#pragma pack()
269	/** Pointer to an EPT Page Directory Table Entry. */
270	typedef EPTPDE *PEPTPDE;
271	/** Pointer to a const EPT Page Directory Table Entry. */
272	typedef const EPTPDE *PCEPTPDE;
273	AssertCompileSize(EPTPDE, 8);
274
275	/**
276	* EPT Page Directory Table.
277	*/
278	#pragma pack(1)
279	typedef struct EPTPD
280	{
281	EPTPDE a[EPT_PG_ENTRIES];
282	} EPTPD;
283	#pragma pack()
284	/** Pointer to an EPT Page Directory Table. */
285	typedef EPTPD *PEPTPD;
286	/** Pointer to a const EPT Page Directory Table. */
287	typedef const EPTPD *PCEPTPD;
288
289
290	/**
291	* EPT Page Table Entry. Bit view.
292	*/
293	#pragma pack(1)
294	typedef struct EPTPTEBITS
295	{
296	/** 0 - Present bit.
297	* @remark This is a convenience "misnomer". The bit actually indicates
298	* read access and the CPU will consider an entry with any of the
299	* first three bits set as present. Since all our valid entries
300	* will have this bit set, it can be used as a present indicator
301	* and allow some code sharing. */
302	uint64_t u1Present : 1;
303	/** 1 - Writable bit. */
304	uint64_t u1Write : 1;
305	/** 2 - Executable bit. */
306	uint64_t u1Execute : 1;
307	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
308	uint64_t u3EMT : 3;
309	/** 6 - Ignore PAT memory type */
310	uint64_t u1IgnorePAT : 1;
311	/** 11:7 - Available for software. */
312	uint64_t u5Available : 5;
313	/** 51:12 - Physical address of page. Restricted by maximum physical
314	* address width of the cpu. */
315	uint64_t u40PhysAddr : 40;
316	/** 63:52 - Available for software. */
317	uint64_t u12Available : 12;
318	} EPTPTEBITS;
319	#pragma pack()
320	AssertCompileSize(EPTPTEBITS, 8);
321
322	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
323	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
324	/** The page shift to get the EPT PTE index. */
325	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
326	/** The EPT PT index mask (apply to a shifted page address). */
327	#define EPT_PT_MASK X86_PT_PAE_MASK
328
329	/**
330	* EPT Page Table Entry.
331	*/
332	#pragma pack(1)
333	typedef union EPTPTE
334	{
335	/** Normal view. */
336	EPTPTEBITS n;
337	/** Unsigned integer view. */
338	X86PGPAEUINT u;
339	/** 64 bit unsigned integer view. */
340	uint64_t au64[1];
341	/** 32 bit unsigned integer view. */
342	uint32_t au32[2];
343	} EPTPTE;
344	#pragma pack()
345	/** Pointer to an EPT Page Directory Table Entry. */
346	typedef EPTPTE *PEPTPTE;
347	/** Pointer to a const EPT Page Directory Table Entry. */
348	typedef const EPTPTE *PCEPTPTE;
349	AssertCompileSize(EPTPTE, 8);
350
351	/**
352	* EPT Page Table.
353	*/
354	#pragma pack(1)
355	typedef struct EPTPT
356	{
357	EPTPTE a[EPT_PG_ENTRIES];
358	} EPTPT;
359	#pragma pack()
360	/** Pointer to an extended page table. */
361	typedef EPTPT *PEPTPT;
362	/** Pointer to a const extended table. */
363	typedef const EPTPT *PCEPTPT;
364
365	/**
366	* VPID flush types.
367	*/
368	typedef enum
369	{
370	/** Invalidate a specific page. */
371	VMX_FLUSH_VPID_INDIV_ADDR = 0,
372	/** Invalidate one context (specific VPID). */
373	VMX_FLUSH_VPID_SINGLE_CONTEXT = 1,
374	/** Invalidate all contexts (all VPIDs). */
375	VMX_FLUSH_VPID_ALL_CONTEXTS = 2,
376	/** Invalidate a single VPID context retaining global mappings. */
377	VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
378	/** Unsupported by VirtualBox. */
379	VMX_FLUSH_VPID_NOT_SUPPORTED = 0xbad,
380	/** Unsupported by CPU. */
381	VMX_FLUSH_VPID_NONE = 0xb00,
382	/** 32bit hackishness. */
383	VMX_FLUSH_VPID_32BIT_HACK = 0x7fffffff
384	} VMX_FLUSH_VPID;
385
386	/**
387	* EPT flush types.
388	*/
389	typedef enum
390	{
391	/** Invalidate one context (specific EPT). */
392	VMX_FLUSH_EPT_SINGLE_CONTEXT = 1,
393	/* Invalidate all contexts (all EPTs) */
394	VMX_FLUSH_EPT_ALL_CONTEXTS = 2,
395	/** Unsupported by VirtualBox. */
396	VMX_FLUSH_EPT_NOT_SUPPORTED = 0xbad,
397	/** Unsupported by CPU. */
398	VMX_FLUSH_EPT_NONE = 0xb00,
399	/** 32bit hackishness. */
400	VMX_FLUSH_EPT_32BIT_HACK = 0x7fffffff
401	} VMX_FLUSH_EPT;
402	/** @} */
403
404	/** @name MSR load/store elements
405	* @{
406	*/
407	#pragma pack(1)
408	typedef struct
409	{
410	uint32_t u32IndexMSR;
411	uint32_t u32Reserved;
412	uint64_t u64Value;
413	} VMXMSR;
414	#pragma pack()
415	/** Pointer to an MSR load/store element. */
416	typedef VMXMSR *PVMXMSR;
417	/** Pointer to a const MSR load/store element. */
418	typedef const VMXMSR *PCVMXMSR;
419
420	/** @} */
421
422
423	/** @name VT-x capability qword
424	* @{
425	*/
426	#pragma pack(1)
427	typedef union
428	{
429	struct
430	{
431	/** Bits set here -must- be set in the correpsonding VM-execution controls. */
432	uint32_t disallowed0;
433	/** Bits cleared here -must- be cleared in the corresponding VM-execution
434	* controls. */
435	uint32_t allowed1;
436	} n;
437	uint64_t u;
438	} VMX_CAPABILITY;
439	#pragma pack()
440	/** @} */
441
442	/** @name VMX Basic Exit Reasons.
443	* @{
444	*/
445	/** And-mask for setting reserved bits to zero */
446	#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
447	/** Or-mask for setting reserved bits to 1 */
448	#define VMX_EFLAGS_RESERVED_1 0x00000002
449	/** @} */
450
451	/** @name VMX Basic Exit Reasons.
452	* @{
453	*/
454	/** -1 Invalid exit code */
455	#define VMX_EXIT_INVALID -1
456	/** 0 Exception or non-maskable interrupt (NMI). */
457	#define VMX_EXIT_EXCEPTION 0
458	/** 1 External interrupt. */
459	#define VMX_EXIT_EXTERNAL_IRQ 1
460	/** 2 Triple fault. */
461	#define VMX_EXIT_TRIPLE_FAULT 2
462	/** 3 INIT signal. */
463	#define VMX_EXIT_INIT_SIGNAL 3
464	/** 4 Start-up IPI (SIPI). */
465	#define VMX_EXIT_SIPI 4
466	/** 5 I/O system-management interrupt (SMI). */
467	#define VMX_EXIT_IO_SMI_IRQ 5
468	/** 6 Other SMI. */
469	#define VMX_EXIT_SMI_IRQ 6
470	/** 7 Interrupt window. */
471	#define VMX_EXIT_IRQ_WINDOW 7
472	/** 9 Task switch. */
473	#define VMX_EXIT_TASK_SWITCH 9
474	/** 10 Guest software attempted to execute CPUID. */
475	#define VMX_EXIT_CPUID 10
476	/** 12 Guest software attempted to execute HLT. */
477	#define VMX_EXIT_HLT 12
478	/** 13 Guest software attempted to execute INVD. */
479	#define VMX_EXIT_INVD 13
480	/** 14 Guest software attempted to execute INVLPG. */
481	#define VMX_EXIT_INVLPG 14
482	/** 15 Guest software attempted to execute RDPMC. */
483	#define VMX_EXIT_RDPMC 15
484	/** 16 Guest software attempted to execute RDTSC. */
485	#define VMX_EXIT_RDTSC 16
486	/** 17 Guest software attempted to execute RSM in SMM. */
487	#define VMX_EXIT_RSM 17
488	/** 18 Guest software executed VMCALL. */
489	#define VMX_EXIT_VMCALL 18
490	/** 19 Guest software executed VMCLEAR. */
491	#define VMX_EXIT_VMCLEAR 19
492	/** 20 Guest software executed VMLAUNCH. */
493	#define VMX_EXIT_VMLAUNCH 20
494	/** 21 Guest software executed VMPTRLD. */
495	#define VMX_EXIT_VMPTRLD 21
496	/** 22 Guest software executed VMPTRST. */
497	#define VMX_EXIT_VMPTRST 22
498	/** 23 Guest software executed VMREAD. */
499	#define VMX_EXIT_VMREAD 23
500	/** 24 Guest software executed VMRESUME. */
501	#define VMX_EXIT_VMRESUME 24
502	/** 25 Guest software executed VMWRITE. */
503	#define VMX_EXIT_VMWRITE 25
504	/** 26 Guest software executed VMXOFF. */
505	#define VMX_EXIT_VMXOFF 26
506	/** 27 Guest software executed VMXON. */
507	#define VMX_EXIT_VMXON 27
508	/** 28 Control-register accesses. */
509	#define VMX_EXIT_CRX_MOVE 28
510	/** 29 Debug-register accesses. */
511	#define VMX_EXIT_DRX_MOVE 29
512	/** 30 I/O instruction. */
513	#define VMX_EXIT_PORT_IO 30
514	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
515	#define VMX_EXIT_RDMSR 31
516	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
517	#define VMX_EXIT_WRMSR 32
518	/** 33 VM-entry failure due to invalid guest state. */
519	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
520	/** 34 VM-entry failure due to MSR loading. */
521	#define VMX_EXIT_ERR_MSR_LOAD 34
522	/** 36 Guest software executed MWAIT. */
523	#define VMX_EXIT_MWAIT 36
524	/** 37 VM exit due to monitor trap flag. */
525	#define VMX_EXIT_MTF 37
526	/** 39 Guest software attempted to execute MONITOR. */
527	#define VMX_EXIT_MONITOR 39
528	/** 40 Guest software attempted to execute PAUSE. */
529	#define VMX_EXIT_PAUSE 40
530	/** 41 VM-entry failure due to machine-check. */
531	#define VMX_EXIT_ERR_MACHINE_CHECK 41
532	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
533	#define VMX_EXIT_TPR 43
534	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
535	#define VMX_EXIT_APIC_ACCESS 44
536	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
537	#define VMX_EXIT_XDTR_ACCESS 46
538	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
539	#define VMX_EXIT_TR_ACCESS 47
540	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
541	#define VMX_EXIT_EPT_VIOLATION 48
542	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
543	#define VMX_EXIT_EPT_MISCONFIG 49
544	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
545	#define VMX_EXIT_INVEPT 50
546	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
547	#define VMX_EXIT_RDTSCP 51
548	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
549	#define VMX_EXIT_PREEMPTION_TIMER 52
550	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
551	#define VMX_EXIT_INVVPID 53
552	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
553	#define VMX_EXIT_WBINVD 54
554	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
555	#define VMX_EXIT_XSETBV 55
556	/** @} */
557
558
559	/** @name VM Instruction Errors
560	* @{
561	*/
562	/** 1 VMCALL executed in VMX root operation. */
563	#define VMX_ERROR_VMCALL 1
564	/** 2 VMCLEAR with invalid physical address. */
565	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
566	/** 3 VMCLEAR with VMXON pointer. */
567	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
568	/** 4 VMLAUNCH with non-clear VMCS. */
569	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
570	/** 5 VMRESUME with non-launched VMCS. */
571	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
572	/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
573	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
574	/** 7 VM entry with invalid control field(s). */
575	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
576	/** 8 VM entry with invalid host-state field(s). */
577	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
578	/** 9 VMPTRLD with invalid physical address. */
579	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
580	/** 10 VMPTRLD with VMXON pointer. */
581	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
582	/** 11 VMPTRLD with incorrect VMCS revision identifier. */
583	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
584	/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
585	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
586	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
587	/** 13 VMWRITE to read-only VMCS component. */
588	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
589	/** 15 VMXON executed in VMX root operation. */
590	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
591	/** 16 VM entry with invalid executive-VMCS pointer. */
592	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
593	/** 17 VM entry with non-launched executive VMCS. */
594	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
595	/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
596	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
597	/** 19 VMCALL with non-clear VMCS. */
598	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
599	/** 20 VMCALL with invalid VM-exit control fields. */
600	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
601	/** 22 VMCALL with incorrect MSEG revision identifier. */
602	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
603	/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
604	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
605	/** 24 VMCALL with invalid SMM-monitor features. */
606	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
607	/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
608	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
609	/** 26 VM entry with events blocked by MOV SS. */
610	#define VMX_ERROR_VMENTRY_MOV_SS 26
611	/** 26 Invalid operand to INVEPT/INVVPID. */
612	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
613
614	/** @} */
615
616
617	/** @name VMX MSRs - Basic VMX information.
618	* @{
619	*/
620	/** VMCS revision identifier used by the processor. */
621	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
622	/** Size of the VMCS. */
623	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0xFFF)
624	/** Width of physical address used for the VMCS.
625	* 0 -> limited to the available amount of physical ram
626	* 1 -> within the first 4 GB
627	*/
628	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
629	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
630	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
631	/** Memory type that must be used for the VMCS. */
632	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
633	/** @} */
634
635
636	/** @name VMX MSRs - Misc VMX info.
637	* @{
638	*/
639	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
640	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
641	/** Activity states supported by the implementation. */
642	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
643	/** Number of CR3 target values supported by the processor. (0-256) */
644	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
645	/** Maximum nr of MSRs in the VMCS. (N+1)512. /
646	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
647	/** MSEG revision identifier used by the processor. */
648	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
649	/** @} */
650
651
652	/** @name VMX MSRs - VMCS enumeration field info
653	* @{
654	*/
655	/** Highest field index. */
656	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
657
658	/** @} */
659
660
661	/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
662	* @{
663	*/
664	#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
665	#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
666	#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
667	#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
668	#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
669	#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
670	#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
671	#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
672	#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
673	#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
674	#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
675	#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
676	#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
677	#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
678	#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
679	#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
680	#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
681	#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
682	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT RT_BIT_64(25)
683	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS RT_BIT_64(26)
684	#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
685	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR RT_BIT_64(40)
686	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT RT_BIT_64(41)
687	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS RT_BIT_64(42)
688	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
689
690	/** @} */
691
692	/** @name Extended Page Table Pointer (EPTP)
693	* @{
694	*/
695	/** Uncachable EPT paging structure memory type. */
696	#define VMX_EPT_MEMTYPE_UC 0
697	/** Write-back EPT paging structure memory type. */
698	#define VMX_EPT_MEMTYPE_WB 6
699	/** Shift value to get the EPT page walk length (bits 5-3) */
700	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
701	/** Mask value to get the EPT page walk length (bits 5-3) */
702	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
703	/** Default EPT page walk length */
704	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
705	/** @} */
706
707
708	/** @name VMCS field encoding - 16 bits guest fields
709	* @{
710	*/
711	#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
712	#define VMX_VMCS16_GUEST_FIELD_ES 0x800
713	#define VMX_VMCS16_GUEST_FIELD_CS 0x802
714	#define VMX_VMCS16_GUEST_FIELD_SS 0x804
715	#define VMX_VMCS16_GUEST_FIELD_DS 0x806
716	#define VMX_VMCS16_GUEST_FIELD_FS 0x808
717	#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
718	#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
719	#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
720	/** @} */
721
722	/** @name VMCS field encoding - 16 bits host fields
723	* @{
724	*/
725	#define VMX_VMCS16_HOST_FIELD_ES 0xC00
726	#define VMX_VMCS16_HOST_FIELD_CS 0xC02
727	#define VMX_VMCS16_HOST_FIELD_SS 0xC04
728	#define VMX_VMCS16_HOST_FIELD_DS 0xC06
729	#define VMX_VMCS16_HOST_FIELD_FS 0xC08
730	#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
731	#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
732	/** @} */
733
734	/** @name VMCS field encoding - 64 bits host fields
735	* @{
736	*/
737	#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
738	#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
739	#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
740	#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
741	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
742	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
743	/** @} */
744
745
746	/** @name VMCS field encoding - 64 Bits control fields
747	* @{
748	*/
749	#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
750	#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
751	#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
752	#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
753
754	/* Optional */
755	#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
756	#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
757
758	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
759	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
760	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
761	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
762
763	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
764	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
765
766	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
767	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
768
769	#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
770	#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
771
772	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
773	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
774	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
775
776	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
777	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
778	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
779
780	/** Extended page table pointer. */
781	#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
782	#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
783
784	/** VM-exit phyiscal address. */
785	#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
786	#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
787	/** @} */
788
789
790	/** @name VMCS field encoding - 64 Bits guest fields
791	* @{
792	*/
793	#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
794	#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
795	#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
796	#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
797	#define VMX_VMCS_GUEST_PAT_FULL 0x2804
798	#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
799	#define VMX_VMCS_GUEST_EFER_FULL 0x2806
800	#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
801	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
802	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
803	#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
804	#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
805	#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
806	#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
807	#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
808	#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
809	#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
810	#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
811	/** @} */
812
813
814	/** @name VMCS field encoding - 32 Bits control fields
815	* @{
816	*/
817	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
818	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
819	#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
820	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
821	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
822	#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
823	#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
824	#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
825	#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
826	#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
827	#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
828	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
829	#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
830	#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
831	/** This field exists only on processors that support the 1-setting of the use TPR shadow VM-execution control. */
832	#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
833	/** This field exists only on processors that support the 1-setting of the activate secondary controls VM-execution control. */
834	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
835	/** @} */
836
837
838	/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
839	* @{
840	*/
841	/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
842	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
843	/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
844	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
845	/** Virtual NMIs. */
846	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI RT_BIT(5)
847	/** Activate VMX preemption timer. */
848	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER RT_BIT(6)
849	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
850	/** @} */
851
852	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
853	* @{
854	*/
855	/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
856	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
857	/** Use timestamp counter offset. */
858	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
859	/** VM Exit when executing the HLT instruction. */
860	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
861	/** VM Exit when executing the INVLPG instruction. */
862	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
863	/** VM Exit when executing the MWAIT instruction. */
864	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
865	/** VM Exit when executing the RDPMC instruction. */
866	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
867	/** VM Exit when executing the RDTSC/RDTSCP instruction. */
868	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
869	/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
870	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
871	/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
872	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
873	/** VM Exit on CR8 loads. */
874	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
875	/** VM Exit on CR8 stores. */
876	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
877	/** Use TPR shadow. */
878	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
879	/** VM Exit when virtual nmi blocking is disabled. */
880	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT RT_BIT(22)
881	/** VM Exit when executing a MOV DRx instruction. */
882	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
883	/** VM Exit when executing IO instructions. */
884	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
885	/** Use IO bitmaps. */
886	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
887	/** Monitor trap flag. */
888	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
889	/** Use MSR bitmaps. */
890	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
891	/** VM Exit when executing the MONITOR instruction. */
892	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
893	/** VM Exit when executing the PAUSE instruction. */
894	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
895	/** Determines whether the secondary processor based VM-execution controls are used. */
896	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
897	/** @} */
898
899	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
900	* @{
901	*/
902	/** Virtualize APIC access. */
903	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
904	/** EPT supported/enabled. */
905	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
906	/** Descriptor table instructions cause VM-exits. */
907	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT RT_BIT(2)
908	/** RDTSCP supported/enabled. */
909	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
910	/** Virtualize x2APIC mode. */
911	#define VMX_VMCS_CTRL_PROC_EXEC2_X2APIC RT_BIT(4)
912	/** VPID supported/enabled. */
913	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
914	/** VM Exit when executing the WBINVD instruction. */
915	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
916	/** Unrestricted guest execution. */
917	#define VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE RT_BIT(7)
918	/** A specified nr of pause loops cause a VM-exit. */
919	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
920	/** @} */
921
922
923	/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
924	* @{
925	*/
926	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
927	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG RT_BIT(2)
928	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
929	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
930	/** In SMM mode after VM-entry. */
931	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
932	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
933	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
934	/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
935	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR RT_BIT(13)
936	/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
937	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR RT_BIT(14)
938	/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
939	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR RT_BIT(15)
940	/** @} */
941
942
943	/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
944	* @{
945	*/
946	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
947	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
948	/** Return to long mode after a VM-exit. */
949	#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
950	/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
951	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
952	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
953	#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
954	/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
955	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
956	/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
957	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
958	/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
959	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
960	/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
961	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
962	/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
963	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
964	/** @} */
965
966	/** @name VMCS field encoding - 32 Bits read-only fields
967	* @{
968	*/
969	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
970	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
971	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
972	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
973	#define VMX_VMCS32_RO_IDT_INFO 0x4408
974	#define VMX_VMCS32_RO_IDT_ERRCODE 0x440A
975	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
976	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
977	/** @} */
978
979	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
980	* @{
981	*/
982	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
983	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
984	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
985	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
986	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
987	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
988	#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
989	#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
990	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
991	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
992	/** @} */
993
994	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
995	* @{
996	*/
997	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
998	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
999	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
1000	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /*< int xx /
1001	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT 5 /*< Why are we getting this one?? /
1002	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
1003	/** @} */
1004
1005
1006	/** @name VMCS field encoding - 32 Bits guest state fields
1007	* @{
1008	*/
1009	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1010	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1011	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1012	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1013	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1014	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1015	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1016	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1017	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1018	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1019	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1020	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1021	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1022	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1023	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1024	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1025	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1026	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1027	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1028	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1029	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
1030	#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE 0x482E
1031	/** @} */
1032
1033
1034	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1035	* @{
1036	*/
1037	/** The logical processor is active. */
1038	#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
1039	/** The logical processor is inactive, because executed a HLT instruction. */
1040	#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
1041	/** The logical processor is inactive, because of a triple fault or other serious error. */
1042	#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
1043	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1044	#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1045	/** @} */
1046
1047
1048	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1049	* @{
1050	*/
1051	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1052	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1053	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1054	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1055	/** @} */
1056
1057
1058	/** @name VMCS field encoding - 32 Bits host state fields
1059	* @{
1060	*/
1061	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1062	/** @} */
1063
1064	/** @name Natural width control fields
1065	* @{
1066	*/
1067	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1068	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1069	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1070	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1071	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1072	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1073	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1074	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1075	/** @} */
1076
1077
1078	/** @name Natural width read-only data fields
1079	* @{
1080	*/
1081	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1082	#define VMX_VMCS_RO_IO_RCX 0x6402
1083	#define VMX_VMCS_RO_IO_RSX 0x6404
1084	#define VMX_VMCS_RO_IO_RDI 0x6406
1085	#define VMX_VMCS_RO_IO_RIP 0x6408
1086	#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
1087	/** @} */
1088
1089
1090	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1091	* @{
1092	*/
1093	/** 0-2: Debug register number */
1094	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1095	/** 3: Reserved; cleared to 0. */
1096	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1097	/** 4: Direction of move (0 = write, 1 = read) */
1098	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1099	/** 5-7: Reserved; cleared to 0. */
1100	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1101	/** 8-11: General purpose register number. */
1102	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1103	/** Rest: reserved. */
1104	/** @} */
1105
1106	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1107	* @{
1108	*/
1109	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1110	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1111	/** @} */
1112
1113
1114
1115	/** @name CRx accesses
1116	* @{
1117	*/
1118	/** 0-3: Control register number (0 for CLTS & LMSW) */
1119	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1120	/** 4-5: Access type. */
1121	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1122	/** 6: LMSW operand type */
1123	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1124	/** 7: Reserved; cleared to 0. */
1125	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1126	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1127	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1128	/** 12-15: Reserved; cleared to 0. */
1129	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1130	/** 16-31: LMSW source data (else 0). */
1131	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1132	/** Rest: reserved. */
1133	/** @} */
1134
1135	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1136	* @{
1137	*/
1138	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1139	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1140	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1141	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1142	/** @} */
1143
1144	/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1145	* @{
1146	*/
1147	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1148	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1149	/** Task switch caused by a call instruction. */
1150	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1151	/** Task switch caused by an iret instruction. */
1152	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1153	/** Task switch caused by a jmp instruction. */
1154	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1155	/** Task switch caused by an interrupt gate. */
1156	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1157
1158	/** @} */
1159
1160
1161	/** @name VMX_EXIT_EPT_VIOLATION
1162	* @{
1163	*/
1164	/** Set if the violation was caused by a data read. */
1165	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1166	/** Set if the violation was caused by a data write. */
1167	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1168	/** Set if the violation was caused by an insruction fetch. */
1169	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1170	/** AND of the present bit of all EPT structures. */
1171	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1172	/** AND of the write bit of all EPT structures. */
1173	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1174	/** AND of the execute bit of all EPT structures. */
1175	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1176	/** Set if the guest linear address field contains the faulting address. */
1177	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1178	/** If bit 7 is one: (reserved otherwise)
1179	* 1 - violation due to physical address access.
1180	* 0 - violation caused by page walk or access/dirty bit updates
1181	*/
1182	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1183	/** @} */
1184
1185
1186	/** @name VMX_EXIT_PORT_IO
1187	* @{
1188	*/
1189	/** 0-2: IO operation width. */
1190	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1191	/** 3: IO operation direction. */
1192	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1193	/** 4: String IO operation. */
1194	#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1195	/** 5: Repeated IO operation. */
1196	#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1197	/** 6: Operand encoding. */
1198	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1199	/** 16-31: IO Port (0-0xffff). */
1200	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1201	/* Rest reserved. */
1202	/** @} */
1203
1204	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1205	* @{
1206	*/
1207	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1208	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1209	/** @} */
1210
1211
1212	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1213	* @{
1214	*/
1215	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1216	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1217	/** @} */
1218
1219	/** @name VMX_EXIT_APIC_ACCESS
1220	* @{
1221	*/
1222	/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1223	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) (a & 0xfff)
1224	/** 12-15: Access type. */
1225	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a >> 12) & 0xf)
1226	/* Rest reserved. */
1227	/** @} */
1228
1229
1230	/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1231	* @{
1232	*/
1233	/** Linear read access. */
1234	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1235	/** Linear write access. */
1236	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1237	/** Linear instruction fetch access. */
1238	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1239	/** Linear read/write access during event delivery. */
1240	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1241	/** Physical read/write access during event delivery. */
1242	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1243	/** Physical access for an instruction fetch or during instruction execution. */
1244	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1245	/** @} */
1246
1247	/** @} */
1248
1249	/** @name VMCS field encoding - Natural width guest state fields
1250	* @{
1251	*/
1252	#define VMX_VMCS64_GUEST_CR0 0x6800
1253	#define VMX_VMCS64_GUEST_CR3 0x6802
1254	#define VMX_VMCS64_GUEST_CR4 0x6804
1255	#define VMX_VMCS64_GUEST_ES_BASE 0x6806
1256	#define VMX_VMCS64_GUEST_CS_BASE 0x6808
1257	#define VMX_VMCS64_GUEST_SS_BASE 0x680A
1258	#define VMX_VMCS64_GUEST_DS_BASE 0x680C
1259	#define VMX_VMCS64_GUEST_FS_BASE 0x680E
1260	#define VMX_VMCS64_GUEST_GS_BASE 0x6810
1261	#define VMX_VMCS64_GUEST_LDTR_BASE 0x6812
1262	#define VMX_VMCS64_GUEST_TR_BASE 0x6814
1263	#define VMX_VMCS64_GUEST_GDTR_BASE 0x6816
1264	#define VMX_VMCS64_GUEST_IDTR_BASE 0x6818
1265	#define VMX_VMCS64_GUEST_DR7 0x681A
1266	#define VMX_VMCS64_GUEST_RSP 0x681C
1267	#define VMX_VMCS64_GUEST_RIP 0x681E
1268	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1269	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1270	#define VMX_VMCS64_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1271	#define VMX_VMCS64_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1272	/** @} */
1273
1274
1275	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1276	* @{
1277	*/
1278	/** Hardware breakpoint 0 was met. */
1279	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1280	/** Hardware breakpoint 1 was met. */
1281	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1282	/** Hardware breakpoint 2 was met. */
1283	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1284	/** Hardware breakpoint 3 was met. */
1285	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1286	/** At least one data or IO breakpoint was hit. */
1287	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1288	/** A debug exception would have been triggered by single-step execution mode. */
1289	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1290	/** Bits 4-11, 13 and 15-63 are reserved. */
1291
1292	/** @} */
1293
1294	/** @name VMCS field encoding - Natural width host state fields
1295	* @{
1296	*/
1297	#define VMX_VMCS_HOST_CR0 0x6C00
1298	#define VMX_VMCS_HOST_CR3 0x6C02
1299	#define VMX_VMCS_HOST_CR4 0x6C04
1300	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1301	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1302	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1303	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1304	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1305	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1306	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1307	#define VMX_VMCS_HOST_RSP 0x6C14
1308	#define VMX_VMCS_HOST_RIP 0x6C16
1309	/** @} */
1310
1311	/** @} */
1312
1313
1314	#if RT_INLINE_ASM_GNU_STYLE
1315	# define __STR(x) #x
1316	# define STR(x) __STR(x)
1317	#endif
1318
1319
1320	/** @defgroup grp_vmx_asm vmx assembly helpers
1321	* @ingroup grp_vmx
1322	* @{
1323	*/
1324
1325	/**
1326	* Executes VMXON
1327	*
1328	* @returns VBox status code
1329	* @param pVMXOn Physical address of VMXON structure
1330	*/
1331	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1332	DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1333	#else
1334	DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1335	{
1336	int rc = VINF_SUCCESS;
1337	# if RT_INLINE_ASM_GNU_STYLE
1338	__asm__ __volatile__ (
1339	"push %3 \n\t"
1340	"push %2 \n\t"
1341	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1342	"ja 2f \n\t"
1343	"je 1f \n\t"
1344	"movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1345	"jmp 2f \n\t"
1346	"1: \n\t"
1347	"movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1348	"2: \n\t"
1349	"add $8, %%esp \n\t"
1350	:"=rm"(rc)
1351	:"0"(VINF_SUCCESS),
1352	"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1353	"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1354	:"memory"
1355	);
1356	# else
1357	__asm
1358	{
1359	push dword ptr [pVMXOn+4]
1360	push dword ptr [pVMXOn]
1361	_emit 0xF3
1362	_emit 0x0F
1363	_emit 0xC7
1364	_emit 0x34
1365	_emit 0x24 /* VMXON [esp] */
1366	jnc vmxon_good
1367	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1368	jmp the_end
1369
1370	vmxon_good:
1371	jnz the_end
1372	mov dword ptr [rc], VERR_VMX_GENERIC
1373	the_end:
1374	add esp, 8
1375	}
1376	# endif
1377	return rc;
1378	}
1379	#endif
1380
1381
1382	/**
1383	* Executes VMXOFF
1384	*/
1385	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1386	DECLASM(void) VMXDisable(void);
1387	#else
1388	DECLINLINE(void) VMXDisable(void)
1389	{
1390	# if RT_INLINE_ASM_GNU_STYLE
1391	__asm__ __volatile__ (
1392	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1393	);
1394	# else
1395	__asm
1396	{
1397	_emit 0x0F
1398	_emit 0x01
1399	_emit 0xC4 /* VMXOFF */
1400	}
1401	# endif
1402	}
1403	#endif
1404
1405
1406	/**
1407	* Executes VMCLEAR
1408	*
1409	* @returns VBox status code
1410	* @param pVMCS Physical address of VM control structure
1411	*/
1412	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1413	DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1414	#else
1415	DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1416	{
1417	int rc = VINF_SUCCESS;
1418	# if RT_INLINE_ASM_GNU_STYLE
1419	__asm__ __volatile__ (
1420	"push %3 \n\t"
1421	"push %2 \n\t"
1422	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1423	"jnc 1f \n\t"
1424	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1425	"1: \n\t"
1426	"add $8, %%esp \n\t"
1427	:"=rm"(rc)
1428	:"0"(VINF_SUCCESS),
1429	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1430	"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1431	:"memory"
1432	);
1433	# else
1434	__asm
1435	{
1436	push dword ptr [pVMCS+4]
1437	push dword ptr [pVMCS]
1438	_emit 0x66
1439	_emit 0x0F
1440	_emit 0xC7
1441	_emit 0x34
1442	_emit 0x24 /* VMCLEAR [esp] */
1443	jnc success
1444	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1445	success:
1446	add esp, 8
1447	}
1448	# endif
1449	return rc;
1450	}
1451	#endif
1452
1453
1454	/**
1455	* Executes VMPTRLD
1456	*
1457	* @returns VBox status code
1458	* @param pVMCS Physical address of VMCS structure
1459	*/
1460	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1461	DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1462	#else
1463	DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1464	{
1465	int rc = VINF_SUCCESS;
1466	# if RT_INLINE_ASM_GNU_STYLE
1467	__asm__ __volatile__ (
1468	"push %3 \n\t"
1469	"push %2 \n\t"
1470	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1471	"jnc 1f \n\t"
1472	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1473	"1: \n\t"
1474	"add $8, %%esp \n\t"
1475	:"=rm"(rc)
1476	:"0"(VINF_SUCCESS),
1477	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1478	"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1479	);
1480	# else
1481	__asm
1482	{
1483	push dword ptr [pVMCS+4]
1484	push dword ptr [pVMCS]
1485	_emit 0x0F
1486	_emit 0xC7
1487	_emit 0x34
1488	_emit 0x24 /* VMPTRLD [esp] */
1489	jnc success
1490	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1491
1492	success:
1493	add esp, 8
1494	}
1495	# endif
1496	return rc;
1497	}
1498	#endif
1499
1500	/**
1501	* Executes VMPTRST
1502	*
1503	* @returns VBox status code
1504	* @param pVMCS Address that will receive the current pointer
1505	*/
1506	DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1507
1508	/**
1509	* Executes VMWRITE
1510	*
1511	* @returns VBox status code
1512	* @param idxField VMCS index
1513	* @param u32Val 32 bits value
1514	*/
1515	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1516	DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1517	#else
1518	DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1519	{
1520	int rc = VINF_SUCCESS;
1521	# if RT_INLINE_ASM_GNU_STYLE
1522	__asm__ __volatile__ (
1523	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1524	"ja 2f \n\t"
1525	"je 1f \n\t"
1526	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1527	"jmp 2f \n\t"
1528	"1: \n\t"
1529	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1530	"2: \n\t"
1531	:"=rm"(rc)
1532	:"0"(VINF_SUCCESS),
1533	"a"(idxField),
1534	"d"(u32Val)
1535	);
1536	# else
1537	__asm
1538	{
1539	push dword ptr [u32Val]
1540	mov eax, [idxField]
1541	_emit 0x0F
1542	_emit 0x79
1543	_emit 0x04
1544	_emit 0x24 /* VMWRITE eax, [esp] */
1545	jnc valid_vmcs
1546	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1547	jmp the_end
1548
1549	valid_vmcs:
1550	jnz the_end
1551	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1552	the_end:
1553	add esp, 4
1554	}
1555	# endif
1556	return rc;
1557	}
1558	#endif
1559
1560	/**
1561	* Executes VMWRITE
1562	*
1563	* @returns VBox status code
1564	* @param idxField VMCS index
1565	* @param u64Val 16, 32 or 64 bits value
1566	*/
1567	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1568	DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1569	#else
1570	VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1571
1572	#define VMXWriteVMCS64(idxField, u64Val) VMXWriteVMCS64Ex(pVCpu, idxField, u64Val)
1573	#endif
1574
1575	#if HC_ARCH_BITS == 64
1576	#define VMXWriteVMCS VMXWriteVMCS64
1577	#else
1578	#define VMXWriteVMCS VMXWriteVMCS32
1579	#endif /* HC_ARCH_BITS == 64 */
1580
1581
1582	/**
1583	* Invalidate a page using invept
1584	* @returns VBox status code
1585	* @param enmFlush Type of flush
1586	* @param pDescriptor Descriptor
1587	*/
1588	DECLASM(int) VMXR0InvEPT(VMX_FLUSH_EPT enmFlush, uint64_t *pDescriptor);
1589
1590	/**
1591	* Invalidate a page using invvpid
1592	* @returns VBox status code
1593	* @param enmFlush Type of flush
1594	* @param pDescriptor Descriptor
1595	*/
1596	DECLASM(int) VMXR0InvVPID(VMX_FLUSH_VPID enmFlush, uint64_t *pDescriptor);
1597
1598	/**
1599	* Executes VMREAD
1600	*
1601	* @returns VBox status code
1602	* @param idxField VMCS index
1603	* @param pData Ptr to store VM field value
1604	*/
1605	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1606	DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1607	#else
1608	DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1609	{
1610	int rc = VINF_SUCCESS;
1611	# if RT_INLINE_ASM_GNU_STYLE
1612	__asm__ __volatile__ (
1613	"movl $"STR(VINF_SUCCESS)", %0 \n\t"
1614	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1615	"ja 2f \n\t"
1616	"je 1f \n\t"
1617	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1618	"jmp 2f \n\t"
1619	"1: \n\t"
1620	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1621	"2: \n\t"
1622	:"=&r"(rc),
1623	"=d"(*pData)
1624	:"a"(idxField),
1625	"d"(0)
1626	);
1627	# else
1628	__asm
1629	{
1630	sub esp, 4
1631	mov dword ptr [esp], 0
1632	mov eax, [idxField]
1633	_emit 0x0F
1634	_emit 0x78
1635	_emit 0x04
1636	_emit 0x24 /* VMREAD eax, [esp] */
1637	mov edx, pData
1638	pop dword ptr [edx]
1639	jnc valid_vmcs
1640	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1641	jmp the_end
1642
1643	valid_vmcs:
1644	jnz the_end
1645	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1646	the_end:
1647	}
1648	# endif
1649	return rc;
1650	}
1651	#endif
1652
1653	/**
1654	* Executes VMREAD
1655	*
1656	* @returns VBox status code
1657	* @param idxField VMCS index
1658	* @param pData Ptr to store VM field value
1659	*/
1660	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1661	DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1662	#else
1663	DECLINLINE(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData)
1664	{
1665	int rc;
1666
1667	uint32_t val_hi, val;
1668	rc = VMXReadVMCS32(idxField, &val);
1669	rc \|= VMXReadVMCS32(idxField + 1, &val_hi);
1670	AssertRC(rc);
1671	*pData = RT_MAKE_U64(val, val_hi);
1672	return rc;
1673	}
1674	#endif
1675
1676	#if HC_ARCH_BITS == 64
1677	# define VMXReadVMCS VMXReadVMCS64
1678	#else
1679	# define VMXReadVMCS VMXReadVMCS32
1680	#endif /* HC_ARCH_BITS == 64 */
1681
1682	/**
1683	* Gets the last instruction error value from the current VMCS
1684	*
1685	* @returns error value
1686	*/
1687	DECLINLINE(uint32_t) VMXGetLastError(void)
1688	{
1689	#if HC_ARCH_BITS == 64
1690	uint64_t uLastError = 0;
1691	int rc = VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1692	AssertRC(rc);
1693	return (uint32_t)uLastError;
1694
1695	#else /* 32-bit host: */
1696	uint32_t uLastError = 0;
1697	int rc = VMXReadVMCS32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1698	AssertRC(rc);
1699	return uLastError;
1700	#endif
1701	}
1702
1703	#ifdef IN_RING0
1704	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1705	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
1706	#endif /* IN_RING0 */
1707
1708	/** @} */
1709
1710	#endif
1711

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 43657

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