hm_vmx.h@ 44283

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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2010 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/** @defgroup grp_vmx vmx Types and Definitions
35	* @ingroup grp_hm
36	* @{
37	*/
38
39	/** @name VMX EPT paging structures
40	* @{
41	*/
42
43	/**
44	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
45	*/
46	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
47
48	/**
49	* EPT Page Directory Pointer Entry. Bit view.
50	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
51	* this did cause trouble with one compiler/version).
52	*/
53	#pragma pack(1)
54	typedef struct EPTPML4EBITS
55	{
56	/** Present bit. */
57	uint64_t u1Present : 1;
58	/** Writable bit. */
59	uint64_t u1Write : 1;
60	/** Executable bit. */
61	uint64_t u1Execute : 1;
62	/** Reserved (must be 0). */
63	uint64_t u5Reserved : 5;
64	/** Available for software. */
65	uint64_t u4Available : 4;
66	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
67	uint64_t u40PhysAddr : 40;
68	/** Availabe for software. */
69	uint64_t u12Available : 12;
70	} EPTPML4EBITS;
71	#pragma pack()
72	AssertCompileSize(EPTPML4EBITS, 8);
73
74	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
75	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
76	/** The page shift to get the PML4 index. */
77	#define EPT_PML4_SHIFT X86_PML4_SHIFT
78	/** The PML4 index mask (apply to a shifted page address). */
79	#define EPT_PML4_MASK X86_PML4_MASK
80
81	/**
82	* EPT PML4E.
83	*/
84	#pragma pack(1)
85	typedef union EPTPML4E
86	{
87	/** Normal view. */
88	EPTPML4EBITS n;
89	/** Unsigned integer view. */
90	X86PGPAEUINT u;
91	/** 64 bit unsigned integer view. */
92	uint64_t au64[1];
93	/** 32 bit unsigned integer view. */
94	uint32_t au32[2];
95	} EPTPML4E;
96	#pragma pack()
97	/** Pointer to a PML4 table entry. */
98	typedef EPTPML4E *PEPTPML4E;
99	/** Pointer to a const PML4 table entry. */
100	typedef const EPTPML4E *PCEPTPML4E;
101	AssertCompileSize(EPTPML4E, 8);
102
103	/**
104	* EPT PML4 Table.
105	*/
106	#pragma pack(1)
107	typedef struct EPTPML4
108	{
109	EPTPML4E a[EPT_PG_ENTRIES];
110	} EPTPML4;
111	#pragma pack()
112	/** Pointer to an EPT PML4 Table. */
113	typedef EPTPML4 *PEPTPML4;
114	/** Pointer to a const EPT PML4 Table. */
115	typedef const EPTPML4 *PCEPTPML4;
116
117	/**
118	* EPT Page Directory Pointer Entry. Bit view.
119	*/
120	#pragma pack(1)
121	typedef struct EPTPDPTEBITS
122	{
123	/** Present bit. */
124	uint64_t u1Present : 1;
125	/** Writable bit. */
126	uint64_t u1Write : 1;
127	/** Executable bit. */
128	uint64_t u1Execute : 1;
129	/** Reserved (must be 0). */
130	uint64_t u5Reserved : 5;
131	/** Available for software. */
132	uint64_t u4Available : 4;
133	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
134	uint64_t u40PhysAddr : 40;
135	/** Availabe for software. */
136	uint64_t u12Available : 12;
137	} EPTPDPTEBITS;
138	#pragma pack()
139	AssertCompileSize(EPTPDPTEBITS, 8);
140
141	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
142	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
143	/** The page shift to get the PDPT index. */
144	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
145	/** The PDPT index mask (apply to a shifted page address). */
146	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
147
148	/**
149	* EPT Page Directory Pointer.
150	*/
151	#pragma pack(1)
152	typedef union EPTPDPTE
153	{
154	/** Normal view. */
155	EPTPDPTEBITS n;
156	/** Unsigned integer view. */
157	X86PGPAEUINT u;
158	/** 64 bit unsigned integer view. */
159	uint64_t au64[1];
160	/** 32 bit unsigned integer view. */
161	uint32_t au32[2];
162	} EPTPDPTE;
163	#pragma pack()
164	/** Pointer to an EPT Page Directory Pointer Entry. */
165	typedef EPTPDPTE *PEPTPDPTE;
166	/** Pointer to a const EPT Page Directory Pointer Entry. */
167	typedef const EPTPDPTE *PCEPTPDPTE;
168	AssertCompileSize(EPTPDPTE, 8);
169
170	/**
171	* EPT Page Directory Pointer Table.
172	*/
173	#pragma pack(1)
174	typedef struct EPTPDPT
175	{
176	EPTPDPTE a[EPT_PG_ENTRIES];
177	} EPTPDPT;
178	#pragma pack()
179	/** Pointer to an EPT Page Directory Pointer Table. */
180	typedef EPTPDPT *PEPTPDPT;
181	/** Pointer to a const EPT Page Directory Pointer Table. */
182	typedef const EPTPDPT *PCEPTPDPT;
183
184
185	/**
186	* EPT Page Directory Table Entry. Bit view.
187	*/
188	#pragma pack(1)
189	typedef struct EPTPDEBITS
190	{
191	/** Present bit. */
192	uint64_t u1Present : 1;
193	/** Writable bit. */
194	uint64_t u1Write : 1;
195	/** Executable bit. */
196	uint64_t u1Execute : 1;
197	/** Reserved (must be 0). */
198	uint64_t u4Reserved : 4;
199	/** Big page (must be 0 here). */
200	uint64_t u1Size : 1;
201	/** Available for software. */
202	uint64_t u4Available : 4;
203	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
204	uint64_t u40PhysAddr : 40;
205	/** Availabe for software. */
206	uint64_t u12Available : 12;
207	} EPTPDEBITS;
208	#pragma pack()
209	AssertCompileSize(EPTPDEBITS, 8);
210
211	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
212	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
213	/** The page shift to get the PD index. */
214	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
215	/** The PD index mask (apply to a shifted page address). */
216	#define EPT_PD_MASK X86_PD_PAE_MASK
217
218	/**
219	* EPT 2MB Page Directory Table Entry. Bit view.
220	*/
221	#pragma pack(1)
222	typedef struct EPTPDE2MBITS
223	{
224	/** Present bit. */
225	uint64_t u1Present : 1;
226	/** Writable bit. */
227	uint64_t u1Write : 1;
228	/** Executable bit. */
229	uint64_t u1Execute : 1;
230	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
231	uint64_t u3EMT : 3;
232	/** Ignore PAT memory type */
233	uint64_t u1IgnorePAT : 1;
234	/** Big page (must be 1 here). */
235	uint64_t u1Size : 1;
236	/** Available for software. */
237	uint64_t u4Available : 4;
238	/** Reserved (must be 0). */
239	uint64_t u9Reserved : 9;
240	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
241	uint64_t u31PhysAddr : 31;
242	/** Availabe for software. */
243	uint64_t u12Available : 12;
244	} EPTPDE2MBITS;
245	#pragma pack()
246	AssertCompileSize(EPTPDE2MBITS, 8);
247
248	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
249	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
250
251	/**
252	* EPT Page Directory Table Entry.
253	*/
254	#pragma pack(1)
255	typedef union EPTPDE
256	{
257	/** Normal view. */
258	EPTPDEBITS n;
259	/** 2MB view (big). */
260	EPTPDE2MBITS b;
261	/** Unsigned integer view. */
262	X86PGPAEUINT u;
263	/** 64 bit unsigned integer view. */
264	uint64_t au64[1];
265	/** 32 bit unsigned integer view. */
266	uint32_t au32[2];
267	} EPTPDE;
268	#pragma pack()
269	/** Pointer to an EPT Page Directory Table Entry. */
270	typedef EPTPDE *PEPTPDE;
271	/** Pointer to a const EPT Page Directory Table Entry. */
272	typedef const EPTPDE *PCEPTPDE;
273	AssertCompileSize(EPTPDE, 8);
274
275	/**
276	* EPT Page Directory Table.
277	*/
278	#pragma pack(1)
279	typedef struct EPTPD
280	{
281	EPTPDE a[EPT_PG_ENTRIES];
282	} EPTPD;
283	#pragma pack()
284	/** Pointer to an EPT Page Directory Table. */
285	typedef EPTPD *PEPTPD;
286	/** Pointer to a const EPT Page Directory Table. */
287	typedef const EPTPD *PCEPTPD;
288
289
290	/**
291	* EPT Page Table Entry. Bit view.
292	*/
293	#pragma pack(1)
294	typedef struct EPTPTEBITS
295	{
296	/** 0 - Present bit.
297	* @remark This is a convenience "misnomer". The bit actually indicates
298	* read access and the CPU will consider an entry with any of the
299	* first three bits set as present. Since all our valid entries
300	* will have this bit set, it can be used as a present indicator
301	* and allow some code sharing. */
302	uint64_t u1Present : 1;
303	/** 1 - Writable bit. */
304	uint64_t u1Write : 1;
305	/** 2 - Executable bit. */
306	uint64_t u1Execute : 1;
307	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
308	uint64_t u3EMT : 3;
309	/** 6 - Ignore PAT memory type */
310	uint64_t u1IgnorePAT : 1;
311	/** 11:7 - Available for software. */
312	uint64_t u5Available : 5;
313	/** 51:12 - Physical address of page. Restricted by maximum physical
314	* address width of the cpu. */
315	uint64_t u40PhysAddr : 40;
316	/** 63:52 - Available for software. */
317	uint64_t u12Available : 12;
318	} EPTPTEBITS;
319	#pragma pack()
320	AssertCompileSize(EPTPTEBITS, 8);
321
322	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
323	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
324	/** The page shift to get the EPT PTE index. */
325	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
326	/** The EPT PT index mask (apply to a shifted page address). */
327	#define EPT_PT_MASK X86_PT_PAE_MASK
328
329	/**
330	* EPT Page Table Entry.
331	*/
332	#pragma pack(1)
333	typedef union EPTPTE
334	{
335	/** Normal view. */
336	EPTPTEBITS n;
337	/** Unsigned integer view. */
338	X86PGPAEUINT u;
339	/** 64 bit unsigned integer view. */
340	uint64_t au64[1];
341	/** 32 bit unsigned integer view. */
342	uint32_t au32[2];
343	} EPTPTE;
344	#pragma pack()
345	/** Pointer to an EPT Page Directory Table Entry. */
346	typedef EPTPTE *PEPTPTE;
347	/** Pointer to a const EPT Page Directory Table Entry. */
348	typedef const EPTPTE *PCEPTPTE;
349	AssertCompileSize(EPTPTE, 8);
350
351	/**
352	* EPT Page Table.
353	*/
354	#pragma pack(1)
355	typedef struct EPTPT
356	{
357	EPTPTE a[EPT_PG_ENTRIES];
358	} EPTPT;
359	#pragma pack()
360	/** Pointer to an extended page table. */
361	typedef EPTPT *PEPTPT;
362	/** Pointer to a const extended table. */
363	typedef const EPTPT *PCEPTPT;
364
365	/**
366	* VPID flush types.
367	*/
368	typedef enum
369	{
370	/** Invalidate a specific page. */
371	VMX_FLUSH_VPID_INDIV_ADDR = 0,
372	/** Invalidate one context (specific VPID). */
373	VMX_FLUSH_VPID_SINGLE_CONTEXT = 1,
374	/** Invalidate all contexts (all VPIDs). */
375	VMX_FLUSH_VPID_ALL_CONTEXTS = 2,
376	/** Invalidate a single VPID context retaining global mappings. */
377	VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
378	/** Unsupported by VirtualBox. */
379	VMX_FLUSH_VPID_NOT_SUPPORTED = 0xbad,
380	/** Unsupported by CPU. */
381	VMX_FLUSH_VPID_NONE = 0xb00,
382	/** 32bit hackishness. */
383	VMX_FLUSH_VPID_32BIT_HACK = 0x7fffffff
384	} VMX_FLUSH_VPID;
385
386	/**
387	* EPT flush types.
388	*/
389	typedef enum
390	{
391	/** Invalidate one context (specific EPT). */
392	VMX_FLUSH_EPT_SINGLE_CONTEXT = 1,
393	/* Invalidate all contexts (all EPTs) */
394	VMX_FLUSH_EPT_ALL_CONTEXTS = 2,
395	/** Unsupported by VirtualBox. */
396	VMX_FLUSH_EPT_NOT_SUPPORTED = 0xbad,
397	/** Unsupported by CPU. */
398	VMX_FLUSH_EPT_NONE = 0xb00,
399	/** 32bit hackishness. */
400	VMX_FLUSH_EPT_32BIT_HACK = 0x7fffffff
401	} VMX_FLUSH_EPT;
402	/** @} */
403
404	/** @name MSR load/store elements
405	* @{
406	*/
407	#pragma pack(1)
408	typedef struct
409	{
410	uint32_t u32IndexMSR;
411	uint32_t u32Reserved;
412	uint64_t u64Value;
413	} VMXMSR;
414	#pragma pack()
415	/** Pointer to an MSR load/store element. */
416	typedef VMXMSR *PVMXMSR;
417	/** Pointer to a const MSR load/store element. */
418	typedef const VMXMSR *PCVMXMSR;
419
420	/** @} */
421
422
423	/** @name VT-x capability qword
424	* @{
425	*/
426	#pragma pack(1)
427	typedef union
428	{
429	struct
430	{
431	/** Bits set here -must- be set in the correpsonding VM-execution controls. */
432	uint32_t disallowed0;
433	/** Bits cleared here -must- be cleared in the corresponding VM-execution
434	* controls. */
435	uint32_t allowed1;
436	} n;
437	uint64_t u;
438	} VMX_CAPABILITY;
439	#pragma pack()
440	/** @} */
441
442	/** @name VMX Basic Exit Reasons.
443	* @{
444	*/
445	/** And-mask for setting reserved bits to zero */
446	#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
447	/** Or-mask for setting reserved bits to 1 */
448	#define VMX_EFLAGS_RESERVED_1 0x00000002
449	/** @} */
450
451	/** @name VMX Basic Exit Reasons.
452	* @{
453	*/
454	/** -1 Invalid exit code */
455	#define VMX_EXIT_INVALID -1
456	/** 0 Exception or non-maskable interrupt (NMI). */
457	#define VMX_EXIT_XCPT_NMI 0
458	/** 1 External interrupt. */
459	#define VMX_EXIT_EXT_INT 1
460	/** 2 Triple fault. */
461	#define VMX_EXIT_TRIPLE_FAULT 2
462	/** 3 INIT signal. */
463	#define VMX_EXIT_INIT_SIGNAL 3
464	/** 4 Start-up IPI (SIPI). */
465	#define VMX_EXIT_SIPI 4
466	/** 5 I/O system-management interrupt (SMI). */
467	#define VMX_EXIT_IO_SMI 5
468	/** 6 Other SMI. */
469	#define VMX_EXIT_SMI 6
470	/** 7 Interrupt window exiting. */
471	#define VMX_EXIT_INT_WINDOW 7
472	/** 9 Task switch. */
473	#define VMX_EXIT_TASK_SWITCH 9
474	/** 10 Guest software attempted to execute CPUID. */
475	#define VMX_EXIT_CPUID 10
476	/** 12 Guest software attempted to execute HLT. */
477	#define VMX_EXIT_HLT 12
478	/** 13 Guest software attempted to execute INVD. */
479	#define VMX_EXIT_INVD 13
480	/** 14 Guest software attempted to execute INVLPG. */
481	#define VMX_EXIT_INVLPG 14
482	/** 15 Guest software attempted to execute RDPMC. */
483	#define VMX_EXIT_RDPMC 15
484	/** 16 Guest software attempted to execute RDTSC. */
485	#define VMX_EXIT_RDTSC 16
486	/** 17 Guest software attempted to execute RSM in SMM. */
487	#define VMX_EXIT_RSM 17
488	/** 18 Guest software executed VMCALL. */
489	#define VMX_EXIT_VMCALL 18
490	/** 19 Guest software executed VMCLEAR. */
491	#define VMX_EXIT_VMCLEAR 19
492	/** 20 Guest software executed VMLAUNCH. */
493	#define VMX_EXIT_VMLAUNCH 20
494	/** 21 Guest software executed VMPTRLD. */
495	#define VMX_EXIT_VMPTRLD 21
496	/** 22 Guest software executed VMPTRST. */
497	#define VMX_EXIT_VMPTRST 22
498	/** 23 Guest software executed VMREAD. */
499	#define VMX_EXIT_VMREAD 23
500	/** 24 Guest software executed VMRESUME. */
501	#define VMX_EXIT_VMRESUME 24
502	/** 25 Guest software executed VMWRITE. */
503	#define VMX_EXIT_VMWRITE 25
504	/** 26 Guest software executed VMXOFF. */
505	#define VMX_EXIT_VMXOFF 26
506	/** 27 Guest software executed VMXON. */
507	#define VMX_EXIT_VMXON 27
508	/** 28 Control-register accesses. */
509	#define VMX_EXIT_CRX_MOVE 28
510	/** 29 Debug-register accesses. */
511	#define VMX_EXIT_DRX_MOVE 29
512	/** 30 I/O instruction. */
513	#define VMX_EXIT_IO_INSTR 30
514	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
515	#define VMX_EXIT_RDMSR 31
516	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
517	#define VMX_EXIT_WRMSR 32
518	/** 33 VM-entry failure due to invalid guest state. */
519	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
520	/** 34 VM-entry failure due to MSR loading. */
521	#define VMX_EXIT_ERR_MSR_LOAD 34
522	/** 36 Guest software executed MWAIT. */
523	#define VMX_EXIT_MWAIT 36
524	/** 37 VM exit due to monitor trap flag. */
525	#define VMX_EXIT_MTF 37
526	/** 39 Guest software attempted to execute MONITOR. */
527	#define VMX_EXIT_MONITOR 39
528	/** 40 Guest software attempted to execute PAUSE. */
529	#define VMX_EXIT_PAUSE 40
530	/** 41 VM-entry failure due to machine-check. */
531	#define VMX_EXIT_ERR_MACHINE_CHECK 41
532	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
533	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
534	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
535	#define VMX_EXIT_APIC_ACCESS 44
536	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
537	#define VMX_EXIT_XDTR_ACCESS 46
538	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
539	#define VMX_EXIT_TR_ACCESS 47
540	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
541	#define VMX_EXIT_EPT_VIOLATION 48
542	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
543	#define VMX_EXIT_EPT_MISCONFIG 49
544	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
545	#define VMX_EXIT_INVEPT 50
546	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
547	#define VMX_EXIT_RDTSCP 51
548	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
549	#define VMX_EXIT_PREEMPTION_TIMER 52
550	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
551	#define VMX_EXIT_INVVPID 53
552	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
553	#define VMX_EXIT_WBINVD 54
554	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
555	#define VMX_EXIT_XSETBV 55
556	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
557	#define VMX_EXIT_RDRAND 57
558	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
559	#define VMX_EXIT_INVPCID 58
560	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
561	#define VMX_EXIT_VMFUNC 59
562	/** The maximum exit value (inclusive). */
563	#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
564	/** @} */
565
566
567	/** @name VM Instruction Errors
568	* @{
569	*/
570	/** 1 VMCALL executed in VMX root operation. */
571	#define VMX_ERROR_VMCALL 1
572	/** 2 VMCLEAR with invalid physical address. */
573	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
574	/** 3 VMCLEAR with VMXON pointer. */
575	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
576	/** 4 VMLAUNCH with non-clear VMCS. */
577	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
578	/** 5 VMRESUME with non-launched VMCS. */
579	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
580	/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
581	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
582	/** 7 VM entry with invalid control field(s). */
583	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
584	/** 8 VM entry with invalid host-state field(s). */
585	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
586	/** 9 VMPTRLD with invalid physical address. */
587	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
588	/** 10 VMPTRLD with VMXON pointer. */
589	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
590	/** 11 VMPTRLD with incorrect VMCS revision identifier. */
591	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
592	/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
593	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
594	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
595	/** 13 VMWRITE to read-only VMCS component. */
596	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
597	/** 15 VMXON executed in VMX root operation. */
598	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
599	/** 16 VM entry with invalid executive-VMCS pointer. */
600	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
601	/** 17 VM entry with non-launched executive VMCS. */
602	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
603	/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
604	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
605	/** 19 VMCALL with non-clear VMCS. */
606	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
607	/** 20 VMCALL with invalid VM-exit control fields. */
608	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
609	/** 22 VMCALL with incorrect MSEG revision identifier. */
610	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
611	/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
612	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
613	/** 24 VMCALL with invalid SMM-monitor features. */
614	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
615	/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
616	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
617	/** 26 VM entry with events blocked by MOV SS. */
618	#define VMX_ERROR_VMENTRY_MOV_SS 26
619	/** 26 Invalid operand to INVEPT/INVVPID. */
620	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
621
622	/** @} */
623
624
625	/** @name VMX MSRs - Basic VMX information.
626	* @{
627	*/
628	/** VMCS revision identifier used by the processor. */
629	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
630	/** Size of the VMCS. */
631	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0xFFF)
632	/** Width of physical address used for the VMCS.
633	* 0 -> limited to the available amount of physical ram
634	* 1 -> within the first 4 GB
635	*/
636	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
637	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
638	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
639	/** Memory type that must be used for the VMCS. */
640	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
641	/** @} */
642
643
644	/** @name VMX MSRs - Misc VMX info.
645	* @{
646	*/
647	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
648	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
649	/** Activity states supported by the implementation. */
650	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
651	/** Number of CR3 target values supported by the processor. (0-256) */
652	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
653	/** Maximum nr of MSRs in the VMCS. (N+1)512. /
654	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
655	/** MSEG revision identifier used by the processor. */
656	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
657	/** @} */
658
659
660	/** @name VMX MSRs - VMCS enumeration field info
661	* @{
662	*/
663	/** Highest field index. */
664	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
665
666	/** @} */
667
668
669	/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
670	* @{
671	*/
672	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
673	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
674	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
675	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
676	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
677	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
678	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
679	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
680	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
681	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
682	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
683	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
684	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
685	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
686	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
687	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
688	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
689	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
690	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
691	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
692	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
693	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
694	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
695	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
696	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
697
698	/** @} */
699
700	/** @name Extended Page Table Pointer (EPTP)
701	* @{
702	*/
703	/** Uncachable EPT paging structure memory type. */
704	#define VMX_EPT_MEMTYPE_UC 0
705	/** Write-back EPT paging structure memory type. */
706	#define VMX_EPT_MEMTYPE_WB 6
707	/** Shift value to get the EPT page walk length (bits 5-3) */
708	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
709	/** Mask value to get the EPT page walk length (bits 5-3) */
710	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
711	/** Default EPT page-walk length (1 less than the actual EPT page-walk
712	* length) */
713	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
714	/** @} */
715
716
717	/** @name VMCS field encoding - 16 bits guest fields
718	* @{
719	*/
720	#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
721	#define VMX_VMCS16_GUEST_FIELD_ES 0x800
722	#define VMX_VMCS16_GUEST_FIELD_CS 0x802
723	#define VMX_VMCS16_GUEST_FIELD_SS 0x804
724	#define VMX_VMCS16_GUEST_FIELD_DS 0x806
725	#define VMX_VMCS16_GUEST_FIELD_FS 0x808
726	#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
727	#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
728	#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
729	/** @} */
730
731	/** @name VMCS field encoding - 16 bits host fields
732	* @{
733	*/
734	#define VMX_VMCS16_HOST_FIELD_ES 0xC00
735	#define VMX_VMCS16_HOST_FIELD_CS 0xC02
736	#define VMX_VMCS16_HOST_FIELD_SS 0xC04
737	#define VMX_VMCS16_HOST_FIELD_DS 0xC06
738	#define VMX_VMCS16_HOST_FIELD_FS 0xC08
739	#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
740	#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
741	/** @} */
742
743	/** @name VMCS field encoding - 64 bits host fields
744	* @{
745	*/
746	#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
747	#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
748	#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
749	#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
750	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
751	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
752	/** @} */
753
754
755	/** @name VMCS field encoding - 64 Bits control fields
756	* @{
757	*/
758	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
759	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
760	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
761	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
762
763	/* Optional */
764	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
765	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
766
767	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
768	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
769	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
770	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
771
772	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
773	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
774
775	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
776	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
777
778	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
779	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
780
781	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
782	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
783	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
784
785	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
786	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
787	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
788
789	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
790	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
791	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
792
793	/** Extended page table pointer. */
794	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
795	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
796
797	/** Extended page table pointer lists. */
798	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
799	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
800
801	/** VM-exit guest phyiscal address. */
802	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
803	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
804	/** @} */
805
806
807	/** @name VMCS field encoding - 64 Bits guest fields
808	* @{
809	*/
810	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
811	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
812	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
813	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
814	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
815	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
816	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
817	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
818	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
819	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
820	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
821	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
822	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
823	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
824	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
825	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
826	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
827	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
828	/** @} */
829
830
831	/** @name VMCS field encoding - 32 Bits control fields
832	* @{
833	*/
834	#define VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS 0x4000
835	#define VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS 0x4002
836	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
837	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
838	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
839	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
840	#define VMX_VMCS32_CTRL_EXIT_CONTROLS 0x400C
841	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
842	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
843	#define VMX_VMCS32_CTRL_ENTRY_CONTROLS 0x4012
844	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
845	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
846	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
847	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
848	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
849	#define VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS2 0x401E
850	/** @} */
851
852
853	/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
854	* @{
855	*/
856	/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
857	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
858	/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
859	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
860	/** Virtual NMIs. */
861	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI RT_BIT(5)
862	/** Activate VMX preemption timer. */
863	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER RT_BIT(6)
864	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
865	/** @} */
866
867	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
868	* @{
869	*/
870	/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
871	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT RT_BIT(2)
872	/** Use timestamp counter offset. */
873	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
874	/** VM Exit when executing the HLT instruction. */
875	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
876	/** VM Exit when executing the INVLPG instruction. */
877	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
878	/** VM Exit when executing the MWAIT instruction. */
879	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
880	/** VM Exit when executing the RDPMC instruction. */
881	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
882	/** VM Exit when executing the RDTSC/RDTSCP instruction. */
883	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
884	/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
885	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
886	/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
887	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
888	/** VM Exit on CR8 loads. */
889	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
890	/** VM Exit on CR8 stores. */
891	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
892	/** Use TPR shadow. */
893	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
894	/** VM Exit when virtual nmi blocking is disabled. */
895	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT RT_BIT(22)
896	/** VM Exit when executing a MOV DRx instruction. */
897	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
898	/** VM Exit when executing IO instructions. */
899	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
900	/** Use IO bitmaps. */
901	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
902	/** Monitor trap flag. */
903	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
904	/** Use MSR bitmaps. */
905	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
906	/** VM Exit when executing the MONITOR instruction. */
907	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
908	/** VM Exit when executing the PAUSE instruction. */
909	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
910	/** Determines whether the secondary processor based VM-execution controls are used. */
911	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
912	/** @} */
913
914	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
915	* @{
916	*/
917	/** Virtualize APIC access. */
918	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
919	/** EPT supported/enabled. */
920	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
921	/** Descriptor table instructions cause VM-exits. */
922	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
923	/** RDTSCP supported/enabled. */
924	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
925	/** Virtualize x2APIC mode. */
926	#define VMX_VMCS_CTRL_PROC_EXEC2_X2APIC RT_BIT(4)
927	/** VPID supported/enabled. */
928	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
929	/** VM Exit when executing the WBINVD instruction. */
930	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
931	/** Unrestricted guest execution. */
932	#define VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE RT_BIT(7)
933	/** A specified nr of pause loops cause a VM-exit. */
934	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
935	/** VM Exit when executing RDRAND instructions. */
936	#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
937	/** Enables INVPCID instructions. */
938	#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
939	/** Enables VMFUNC instructions. */
940	#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
941	/** @} */
942
943
944	/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
945	* @{
946	*/
947	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
948	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG RT_BIT(2)
949	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
950	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST RT_BIT(9)
951	/** In SMM mode after VM-entry. */
952	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
953	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
954	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
955	/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
956	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR RT_BIT(13)
957	/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
958	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR RT_BIT(14)
959	/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
960	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR RT_BIT(15)
961	/** @} */
962
963
964	/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
965	* @{
966	*/
967	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
968	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
969	/** Return to long mode after a VM-exit. */
970	#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
971	/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
972	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
973	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
974	#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT RT_BIT(15)
975	/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
976	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
977	/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
978	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
979	/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
980	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
981	/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
982	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
983	/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
984	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
985	/** @} */
986
987	/** @name VMCS field encoding - 32 Bits read-only fields
988	* @{
989	*/
990	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
991	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
992	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
993	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
994	#define VMX_VMCS32_RO_IDT_INFO 0x4408
995	#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
996	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
997	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
998	/** @} */
999
1000	/** @name VMX_VMCS32_RO_EXIT_REASON
1001	* @{
1002	*/
1003	#define VMX_EXIT_REASON_BASIC(a) (a & 0xffff)
1004	#define VMX_EXIT_REASON_VMENTRY_FAILED(a) (a & RT_BIT(31))
1005	/** @} */
1006
1007	/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1008	* @{
1009	*/
1010	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
1011	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1012	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1013	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1014	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1015	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
1016	#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
1017	#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
1018	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1019	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
1020	/** @} */
1021
1022	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1023	* @{
1024	*/
1025	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1026	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1027	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1028	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4 /*< int xx /
1029	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DB_XCPT 5 /*< Why are we getting this one?? /
1030	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1031	/** @} */
1032
1033	/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1034	* @{
1035	*/
1036	#define VMX_IDT_VECTORING_INFO_VECTOR(a) (a & 0xff)
1037	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1038	#define VMX_IDT_VECTORING_INFO_TYPE(a) ((a >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1039	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1040	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1041	/** @} */
1042
1043	/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1044	* @{
1045	*/
1046	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1047	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1048	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1049	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1050	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1051	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1052	/** @} */
1053
1054
1055	/** @name VMCS field encoding - 32 Bits guest state fields
1056	* @{
1057	*/
1058	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1059	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1060	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1061	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1062	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1063	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1064	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1065	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1066	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1067	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1068	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1069	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1070	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1071	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1072	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1073	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1074	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1075	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1076	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1077	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1078	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
1079	#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE 0x482E
1080	/** @} */
1081
1082
1083	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1084	* @{
1085	*/
1086	/** The logical processor is active. */
1087	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1088	/** The logiVMCS processor is inactive, because executed a HLT instruction. */
1089	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1090	/** The logiVMCS processor is inactive, because of a triple fault or other serious error. */
1091	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1092	/** The logiVMCS processor is inactive, because it's waiting for a startup-IPI */
1093	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1094	/** @} */
1095
1096
1097	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1098	* @{
1099	*/
1100	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1101	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1102	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1103	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1104	/** @} */
1105
1106
1107	/** @name VMCS field encoding - 32 Bits host state fields
1108	* @{
1109	*/
1110	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1111	/** @} */
1112
1113	/** @name Natural width control fields
1114	* @{
1115	*/
1116	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1117	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1118	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1119	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1120	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1121	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1122	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1123	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1124	/** @} */
1125
1126
1127	/** @name Natural width read-only data fields
1128	* @{
1129	*/
1130	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1131	#define VMX_VMCS_RO_IO_RCX 0x6402
1132	#define VMX_VMCS_RO_IO_RSX 0x6404
1133	#define VMX_VMCS_RO_IO_RDI 0x6406
1134	#define VMX_VMCS_RO_IO_RIP 0x6408
1135	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1136	/** @} */
1137
1138
1139	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1140	* @{
1141	*/
1142	/** 0-2: Debug register number */
1143	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1144	/** 3: Reserved; cleared to 0. */
1145	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1146	/** 4: Direction of move (0 = write, 1 = read) */
1147	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1148	/** 5-7: Reserved; cleared to 0. */
1149	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1150	/** 8-11: General purpose register number. */
1151	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1152	/** Rest: reserved. */
1153	/** @} */
1154
1155	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1156	* @{
1157	*/
1158	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1159	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1160	/** @} */
1161
1162
1163
1164	/** @name CRx accesses
1165	* @{
1166	*/
1167	/** 0-3: Control register number (0 for CLTS & LMSW) */
1168	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1169	/** 4-5: Access type. */
1170	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1171	/** 6: LMSW operand type */
1172	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1173	/** 7: Reserved; cleared to 0. */
1174	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1175	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1176	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1177	/** 12-15: Reserved; cleared to 0. */
1178	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1179	/** 16-31: LMSW source data (else 0). */
1180	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1181	/** Rest: reserved. */
1182	/** @} */
1183
1184	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1185	* @{
1186	*/
1187	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1188	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1189	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1190	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1191	/** @} */
1192
1193	/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1194	* @{
1195	*/
1196	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1197	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1198	/** Task switch caused by a call instruction. */
1199	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1200	/** Task switch caused by an iret instruction. */
1201	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1202	/** Task switch caused by a jmp instruction. */
1203	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1204	/** Task switch caused by an interrupt gate. */
1205	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1206	/** @} */
1207
1208
1209	/** @name VMX_EXIT_EPT_VIOLATION
1210	* @{
1211	*/
1212	/** Set if the violation was caused by a data read. */
1213	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1214	/** Set if the violation was caused by a data write. */
1215	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1216	/** Set if the violation was caused by an insruction fetch. */
1217	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1218	/** AND of the present bit of all EPT structures. */
1219	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1220	/** AND of the write bit of all EPT structures. */
1221	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1222	/** AND of the execute bit of all EPT structures. */
1223	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1224	/** Set if the guest linear address field contains the faulting address. */
1225	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1226	/** If bit 7 is one: (reserved otherwise)
1227	* 1 - violation due to physical address access.
1228	* 0 - violation caused by page walk or access/dirty bit updates
1229	*/
1230	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1231	/** @} */
1232
1233
1234	/** @name VMX_EXIT_PORT_IO
1235	* @{
1236	*/
1237	/** 0-2: IO operation width. */
1238	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1239	/** 3: IO operation direction. */
1240	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1241	/** 4: String IO operation. */
1242	#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1243	/** 5: Repeated IO operation. */
1244	#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1245	/** 6: Operand encoding. */
1246	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1247	/** 16-31: IO Port (0-0xffff). */
1248	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1249	/* Rest reserved. */
1250	/** @} */
1251
1252	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1253	* @{
1254	*/
1255	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1256	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1257	/** @} */
1258
1259
1260	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1261	* @{
1262	*/
1263	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1264	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1265	/** @} */
1266
1267	/** @name VMX_EXIT_APIC_ACCESS
1268	* @{
1269	*/
1270	/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1271	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) (a & 0xfff)
1272	/** 12-15: Access type. */
1273	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a >> 12) & 0xf)
1274	/* Rest reserved. */
1275	/** @} */
1276
1277
1278	/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1279	* @{
1280	*/
1281	/** Linear read access. */
1282	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1283	/** Linear write access. */
1284	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1285	/** Linear instruction fetch access. */
1286	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1287	/** Linear read/write access during event delivery. */
1288	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1289	/** Physical read/write access during event delivery. */
1290	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1291	/** Physical access for an instruction fetch or during instruction execution. */
1292	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1293	/** @} */
1294
1295	/** @} */
1296
1297	/** @name VMCS field encoding - Natural width guest state fields
1298	* @{
1299	*/
1300	#define VMX_VMCS_GUEST_CR0 0x6800
1301	#define VMX_VMCS_GUEST_CR3 0x6802
1302	#define VMX_VMCS_GUEST_CR4 0x6804
1303	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1304	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1305	#define VMX_VMCS_GUEST_SS_BASE 0x680A
1306	#define VMX_VMCS_GUEST_DS_BASE 0x680C
1307	#define VMX_VMCS_GUEST_FS_BASE 0x680E
1308	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1309	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1310	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1311	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1312	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1313	#define VMX_VMCS_GUEST_DR7 0x681A
1314	#define VMX_VMCS_GUEST_RSP 0x681C
1315	#define VMX_VMCS_GUEST_RIP 0x681E
1316	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1317	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1318	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1319	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1320	/** @} */
1321
1322
1323	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1324	* @{
1325	*/
1326	/** Hardware breakpoint 0 was met. */
1327	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1328	/** Hardware breakpoint 1 was met. */
1329	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1330	/** Hardware breakpoint 2 was met. */
1331	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1332	/** Hardware breakpoint 3 was met. */
1333	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1334	/** At least one data or IO breakpoint was hit. */
1335	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1336	/** A debug exception would have been triggered by single-step execution mode. */
1337	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1338	/** Bits 4-11, 13 and 15-63 are reserved. */
1339
1340	/** @} */
1341
1342	/** @name VMCS field encoding - Natural width host state fields
1343	* @{
1344	*/
1345	#define VMX_VMCS_HOST_CR0 0x6C00
1346	#define VMX_VMCS_HOST_CR3 0x6C02
1347	#define VMX_VMCS_HOST_CR4 0x6C04
1348	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1349	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1350	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1351	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1352	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1353	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1354	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1355	#define VMX_VMCS_HOST_RSP 0x6C14
1356	#define VMX_VMCS_HOST_RIP 0x6C16
1357	/** @} */
1358
1359	/** @} */
1360
1361
1362	#if RT_INLINE_ASM_GNU_STYLE
1363	# define __STR(x) #x
1364	# define STR(x) __STR(x)
1365	#endif
1366
1367
1368	/** @defgroup grp_vmx_asm vmx assembly helpers
1369	* @ingroup grp_vmx
1370	* @{
1371	*/
1372
1373	/**
1374	* Executes VMXON
1375	*
1376	* @returns VBox status code
1377	* @param pVMXOn Physical address of VMXON structure
1378	*/
1379	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1380	DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1381	#else
1382	DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1383	{
1384	int rc = VINF_SUCCESS;
1385	# if RT_INLINE_ASM_GNU_STYLE
1386	__asm__ __volatile__ (
1387	"push %3 \n\t"
1388	"push %2 \n\t"
1389	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1390	"ja 2f \n\t"
1391	"je 1f \n\t"
1392	"movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1393	"jmp 2f \n\t"
1394	"1: \n\t"
1395	"movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1396	"2: \n\t"
1397	"add $8, %%esp \n\t"
1398	:"=rm"(rc)
1399	:"0"(VINF_SUCCESS),
1400	"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1401	"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1402	:"memory"
1403	);
1404	# else
1405	__asm
1406	{
1407	push dword ptr [pVMXOn+4]
1408	push dword ptr [pVMXOn]
1409	_emit 0xF3
1410	_emit 0x0F
1411	_emit 0xC7
1412	_emit 0x34
1413	_emit 0x24 /* VMXON [esp] */
1414	jnc vmxon_good
1415	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1416	jmp the_end
1417
1418	vmxon_good:
1419	jnz the_end
1420	mov dword ptr [rc], VERR_VMX_GENERIC
1421	the_end:
1422	add esp, 8
1423	}
1424	# endif
1425	return rc;
1426	}
1427	#endif
1428
1429
1430	/**
1431	* Executes VMXOFF
1432	*/
1433	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1434	DECLASM(void) VMXDisable(void);
1435	#else
1436	DECLINLINE(void) VMXDisable(void)
1437	{
1438	# if RT_INLINE_ASM_GNU_STYLE
1439	__asm__ __volatile__ (
1440	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1441	);
1442	# else
1443	__asm
1444	{
1445	_emit 0x0F
1446	_emit 0x01
1447	_emit 0xC4 /* VMXOFF */
1448	}
1449	# endif
1450	}
1451	#endif
1452
1453
1454	/**
1455	* Executes VMCLEAR
1456	*
1457	* @returns VBox status code
1458	* @param pVMCS Physical address of VM control structure
1459	*/
1460	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1461	DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1462	#else
1463	DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1464	{
1465	int rc = VINF_SUCCESS;
1466	# if RT_INLINE_ASM_GNU_STYLE
1467	__asm__ __volatile__ (
1468	"push %3 \n\t"
1469	"push %2 \n\t"
1470	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1471	"jnc 1f \n\t"
1472	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1473	"1: \n\t"
1474	"add $8, %%esp \n\t"
1475	:"=rm"(rc)
1476	:"0"(VINF_SUCCESS),
1477	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1478	"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1479	:"memory"
1480	);
1481	# else
1482	__asm
1483	{
1484	push dword ptr [pVMCS+4]
1485	push dword ptr [pVMCS]
1486	_emit 0x66
1487	_emit 0x0F
1488	_emit 0xC7
1489	_emit 0x34
1490	_emit 0x24 /* VMCLEAR [esp] */
1491	jnc success
1492	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1493	success:
1494	add esp, 8
1495	}
1496	# endif
1497	return rc;
1498	}
1499	#endif
1500
1501
1502	/**
1503	* Executes VMPTRLD
1504	*
1505	* @returns VBox status code
1506	* @param pVMCS Physical address of VMCS structure
1507	*/
1508	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1509	DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1510	#else
1511	DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1512	{
1513	int rc = VINF_SUCCESS;
1514	# if RT_INLINE_ASM_GNU_STYLE
1515	__asm__ __volatile__ (
1516	"push %3 \n\t"
1517	"push %2 \n\t"
1518	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1519	"jnc 1f \n\t"
1520	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1521	"1: \n\t"
1522	"add $8, %%esp \n\t"
1523	:"=rm"(rc)
1524	:"0"(VINF_SUCCESS),
1525	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1526	"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1527	);
1528	# else
1529	__asm
1530	{
1531	push dword ptr [pVMCS+4]
1532	push dword ptr [pVMCS]
1533	_emit 0x0F
1534	_emit 0xC7
1535	_emit 0x34
1536	_emit 0x24 /* VMPTRLD [esp] */
1537	jnc success
1538	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1539
1540	success:
1541	add esp, 8
1542	}
1543	# endif
1544	return rc;
1545	}
1546	#endif
1547
1548	/**
1549	* Executes VMPTRST
1550	*
1551	* @returns VBox status code
1552	* @param pVMCS Address that will receive the current pointer
1553	*/
1554	DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1555
1556	/**
1557	* Executes VMWRITE
1558	*
1559	* @returns VBox status code
1560	* @param idxField VMCS index
1561	* @param u32Val 32 bits value
1562	*/
1563	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1564	DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
1565	#else
1566	DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
1567	{
1568	int rc = VINF_SUCCESS;
1569	# if RT_INLINE_ASM_GNU_STYLE
1570	__asm__ __volatile__ (
1571	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1572	"ja 2f \n\t"
1573	"je 1f \n\t"
1574	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1575	"jmp 2f \n\t"
1576	"1: \n\t"
1577	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1578	"2: \n\t"
1579	:"=rm"(rc)
1580	:"0"(VINF_SUCCESS),
1581	"a"(idxField),
1582	"d"(u32Val)
1583	);
1584	# else
1585	__asm
1586	{
1587	push dword ptr [u32Val]
1588	mov eax, [idxField]
1589	_emit 0x0F
1590	_emit 0x79
1591	_emit 0x04
1592	_emit 0x24 /* VMWRITE eax, [esp] */
1593	jnc valid_vmcs
1594	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1595	jmp the_end
1596
1597	valid_vmcs:
1598	jnz the_end
1599	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1600	the_end:
1601	add esp, 4
1602	}
1603	# endif
1604	return rc;
1605	}
1606	#endif
1607
1608	/**
1609	* Executes VMWRITE
1610	*
1611	* @returns VBox status code
1612	* @param idxField VMCS index
1613	* @param u64Val 16, 32 or 64 bits value
1614	*/
1615	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1616	DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
1617	#else
1618	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1619
1620	#define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
1621	#endif
1622
1623	#if HC_ARCH_BITS == 64
1624	#define VMXWriteVmcs VMXWriteVmcs64
1625	#else
1626	#define VMXWriteVmcs VMXWriteVmcs32
1627	#endif /* HC_ARCH_BITS == 64 */
1628
1629
1630	/**
1631	* Invalidate a page using invept
1632	* @returns VBox status code
1633	* @param enmFlush Type of flush
1634	* @param pDescriptor Descriptor
1635	*/
1636	DECLASM(int) VMXR0InvEPT(VMX_FLUSH_EPT enmFlush, uint64_t *pDescriptor);
1637
1638	/**
1639	* Invalidate a page using invvpid
1640	* @returns VBox status code
1641	* @param enmFlush Type of flush
1642	* @param pDescriptor Descriptor
1643	*/
1644	DECLASM(int) VMXR0InvVPID(VMX_FLUSH_VPID enmFlush, uint64_t *pDescriptor);
1645
1646	/**
1647	* Executes VMREAD
1648	*
1649	* @returns VBox status code
1650	* @param idxField VMCS index
1651	* @param pData Ptr to store VM field value
1652	*/
1653	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1654	DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
1655	#else
1656	DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
1657	{
1658	int rc = VINF_SUCCESS;
1659	# if RT_INLINE_ASM_GNU_STYLE
1660	__asm__ __volatile__ (
1661	"movl $"STR(VINF_SUCCESS)", %0 \n\t"
1662	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1663	"ja 2f \n\t"
1664	"je 1f \n\t"
1665	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1666	"jmp 2f \n\t"
1667	"1: \n\t"
1668	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1669	"2: \n\t"
1670	:"=&r"(rc),
1671	"=d"(*pData)
1672	:"a"(idxField),
1673	"d"(0)
1674	);
1675	# else
1676	__asm
1677	{
1678	sub esp, 4
1679	mov dword ptr [esp], 0
1680	mov eax, [idxField]
1681	_emit 0x0F
1682	_emit 0x78
1683	_emit 0x04
1684	_emit 0x24 /* VMREAD eax, [esp] */
1685	mov edx, pData
1686	pop dword ptr [edx]
1687	jnc valid_vmcs
1688	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1689	jmp the_end
1690
1691	valid_vmcs:
1692	jnz the_end
1693	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1694	the_end:
1695	}
1696	# endif
1697	return rc;
1698	}
1699	#endif
1700
1701	/**
1702	* Executes VMREAD
1703	*
1704	* @returns VBox status code
1705	* @param idxField VMCS index
1706	* @param pData Ptr to store VM field value
1707	*/
1708	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1709	DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
1710	#else
1711	DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
1712	{
1713	int rc;
1714
1715	uint32_t val_hi, val;
1716	rc = VMXReadVmcs32(idxField, &val);
1717	rc \|= VMXReadVmcs32(idxField + 1, &val_hi);
1718	AssertRC(rc);
1719	*pData = RT_MAKE_U64(val, val_hi);
1720	return rc;
1721	}
1722	#endif
1723
1724	#if HC_ARCH_BITS == 64
1725	# define VMXReadVmcs VMXReadVmcs64
1726	#else
1727	# define VMXReadVmcs VMXReadVmcs32
1728	#endif /* HC_ARCH_BITS == 64 */
1729
1730	/**
1731	* Gets the last instruction error value from the current VMCS
1732	*
1733	* @returns error value
1734	*/
1735	DECLINLINE(uint32_t) VMXGetLastError(void)
1736	{
1737	#if HC_ARCH_BITS == 64
1738	uint64_t uLastError = 0;
1739	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1740	AssertRC(rc);
1741	return (uint32_t)uLastError;
1742
1743	#else /* 32-bit host: */
1744	uint32_t uLastError = 0;
1745	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1746	AssertRC(rc);
1747	return uLastError;
1748	#endif
1749	}
1750
1751	#ifdef IN_RING0
1752	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1753	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
1754	#endif /* IN_RING0 */
1755
1756	/** @} */
1757
1758	#endif
1759

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 44283

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