hm_vmx.h@ 46601

Last change on this file since 46601 was 46379, checked in by vboxsync, 12 years ago
VMM/HMVMXR0: Added VMFUNC feature recognition.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2013 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/** @defgroup grp_vmx vmx Types and Definitions
35	* @ingroup grp_hm
36	* @{
37	*/
38
39	/** @name Host-state restoration flags.
40	* @{
41	*/
42	/* If you change these values don't forget to update the assembly defines as well! */
43	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
44	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
45	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
46	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
47	#define VMX_RESTORE_HOST_GDTR RT_BIT(4)
48	#define VMX_RESTORE_HOST_IDTR RT_BIT(5)
49	#define VMX_RESTORE_HOST_LDTR RT_BIT(6)
50	/** @} */
51
52	/**
53	* Host-state restoration structure.
54	* This holds host-state fields that require manual restoration. The layout is
55	* critical as it's used from assembly code.
56	*/
57	#pragma pack(1)
58	typedef struct VMXRESTOREHOST
59	{
60	RTSEL uHostSelDS; /* 0x00 */
61	RTSEL uHostSelES; /* 0x02 */
62	RTSEL uHostSelFS; /* 0x04 */
63	RTSEL uHostSelGS; /* 0x06 */
64	uint64_t uHostFSBase; /* 0x08 */
65	uint64_t uHostGSBase; /* 0x10 */
66	X86XDTR64 HostGdtr; /* 0x18 */
67	X86XDTR64 HostIdtr; /* 0x22 */
68	} VMXRESTOREHOST;
69	#pragma pack()
70	/** Pointer to VMXRESTOREHOST. */
71	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
72	AssertCompileSize(X86XDTR64, 10);
73	AssertCompileMemberOffset(VMXRESTOREHOST, uHostSelES, 2);
74	AssertCompileMemberOffset(VMXRESTOREHOST, uHostSelFS, 4);
75	AssertCompileMemberOffset(VMXRESTOREHOST, uHostSelGS, 6);
76	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 8);
77	AssertCompileMemberOffset(VMXRESTOREHOST, uHostGSBase, 16);
78	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr, 24);
79	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr, 34);
80	AssertCompileSize(VMXRESTOREHOST, 44);
81
82	/** @name VMX VMCS-Read cache indices.
83	* @{
84	*/
85	#ifndef VBOX_WITH_OLD_VTX_CODE
86	# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
87	# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
88	# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
89	# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
90	# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
91	# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
92	# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
93	# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
94	# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
95	# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
96	# define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
97	# define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
98	# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
99	# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
100	# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
101	# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
102	# define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
103	# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
104	#else /* VBOX_WITH_OLD_VTX_CODE */
105	# define VMX_VMCS_GUEST_RIP_CACHE_IDX 0
106	# define VMX_VMCS_GUEST_RSP_CACHE_IDX 1
107	# define VMX_VMCS_GUEST_RFLAGS_CACHE_IDX 2
108	# define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE_CACHE_IDX 3
109	# define VMX_VMCS_CTRL_CR0_READ_SHADOW_CACHE_IDX 4
110	# define VMX_VMCS_GUEST_CR0_CACHE_IDX 5
111	# define VMX_VMCS_CTRL_CR4_READ_SHADOW_CACHE_IDX 6
112	# define VMX_VMCS_GUEST_CR4_CACHE_IDX 7
113	# define VMX_VMCS_GUEST_DR7_CACHE_IDX 8
114	# define VMX_VMCS32_GUEST_SYSENTER_CS_CACHE_IDX 9
115	# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 10
116	# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 11
117	# define VMX_VMCS32_GUEST_GDTR_LIMIT_CACHE_IDX 12
118	# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 13
119	# define VMX_VMCS32_GUEST_IDTR_LIMIT_CACHE_IDX 14
120	# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 15
121	# define VMX_VMCS16_GUEST_FIELD_CS_CACHE_IDX 16
122	# define VMX_VMCS32_GUEST_CS_LIMIT_CACHE_IDX 17
123	# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 18
124	# define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS_CACHE_IDX 19
125	# define VMX_VMCS16_GUEST_FIELD_DS_CACHE_IDX 20
126	# define VMX_VMCS32_GUEST_DS_LIMIT_CACHE_IDX 21
127	# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 22
128	# define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS_CACHE_IDX 23
129	# define VMX_VMCS16_GUEST_FIELD_ES_CACHE_IDX 24
130	# define VMX_VMCS32_GUEST_ES_LIMIT_CACHE_IDX 25
131	# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 26
132	# define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS_CACHE_IDX 27
133	# define VMX_VMCS16_GUEST_FIELD_FS_CACHE_IDX 28
134	# define VMX_VMCS32_GUEST_FS_LIMIT_CACHE_IDX 29
135	# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 30
136	# define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS_CACHE_IDX 31
137	# define VMX_VMCS16_GUEST_FIELD_GS_CACHE_IDX 32
138	# define VMX_VMCS32_GUEST_GS_LIMIT_CACHE_IDX 33
139	# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 34
140	# define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS_CACHE_IDX 35
141	# define VMX_VMCS16_GUEST_FIELD_SS_CACHE_IDX 36
142	# define VMX_VMCS32_GUEST_SS_LIMIT_CACHE_IDX 37
143	# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 38
144	# define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS_CACHE_IDX 39
145	# define VMX_VMCS16_GUEST_FIELD_TR_CACHE_IDX 40
146	# define VMX_VMCS32_GUEST_TR_LIMIT_CACHE_IDX 41
147	# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 42
148	# define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS_CACHE_IDX 43
149	# define VMX_VMCS16_GUEST_FIELD_LDTR_CACHE_IDX 44
150	# define VMX_VMCS32_GUEST_LDTR_LIMIT_CACHE_IDX 45
151	# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 46
152	# define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS_CACHE_IDX 47
153	# define VMX_VMCS32_RO_EXIT_REASON_CACHE_IDX 48
154	# define VMX_VMCS32_RO_VM_INSTR_ERROR_CACHE_IDX 49
155	# define VMX_VMCS32_RO_EXIT_INSTR_LENGTH_CACHE_IDX 50
156	# define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE_CACHE_IDX 51
157	# define VMX_VMCS32_RO_EXIT_INSTR_INFO_CACHE_IDX 52
158	# define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO_CACHE_IDX 53
159	# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 54
160	# define VMX_VMCS32_RO_IDT_INFO_CACHE_IDX 55
161	# define VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX 56
162	# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX + 1)
163	# define VMX_VMCS_GUEST_CR3_CACHE_IDX 57
164	# define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX 58
165	# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX + 1)
166	#endif /* VBOX_WITH_OLD_VTX_CODE */
167	/** @} */
168
169	/** @name VMX EPT paging structures
170	* @{
171	*/
172
173	/**
174	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
175	*/
176	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
177
178	/**
179	* EPT Page Directory Pointer Entry. Bit view.
180	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
181	* this did cause trouble with one compiler/version).
182	*/
183	#pragma pack(1)
184	typedef struct EPTPML4EBITS
185	{
186	/** Present bit. */
187	uint64_t u1Present : 1;
188	/** Writable bit. */
189	uint64_t u1Write : 1;
190	/** Executable bit. */
191	uint64_t u1Execute : 1;
192	/** Reserved (must be 0). */
193	uint64_t u5Reserved : 5;
194	/** Available for software. */
195	uint64_t u4Available : 4;
196	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
197	uint64_t u40PhysAddr : 40;
198	/** Availabe for software. */
199	uint64_t u12Available : 12;
200	} EPTPML4EBITS;
201	#pragma pack()
202	AssertCompileSize(EPTPML4EBITS, 8);
203
204	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
205	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
206	/** The page shift to get the PML4 index. */
207	#define EPT_PML4_SHIFT X86_PML4_SHIFT
208	/** The PML4 index mask (apply to a shifted page address). */
209	#define EPT_PML4_MASK X86_PML4_MASK
210
211	/**
212	* EPT PML4E.
213	*/
214	#pragma pack(1)
215	typedef union EPTPML4E
216	{
217	/** Normal view. */
218	EPTPML4EBITS n;
219	/** Unsigned integer view. */
220	X86PGPAEUINT u;
221	/** 64 bit unsigned integer view. */
222	uint64_t au64[1];
223	/** 32 bit unsigned integer view. */
224	uint32_t au32[2];
225	} EPTPML4E;
226	#pragma pack()
227	/** Pointer to a PML4 table entry. */
228	typedef EPTPML4E *PEPTPML4E;
229	/** Pointer to a const PML4 table entry. */
230	typedef const EPTPML4E *PCEPTPML4E;
231	AssertCompileSize(EPTPML4E, 8);
232
233	/**
234	* EPT PML4 Table.
235	*/
236	#pragma pack(1)
237	typedef struct EPTPML4
238	{
239	EPTPML4E a[EPT_PG_ENTRIES];
240	} EPTPML4;
241	#pragma pack()
242	/** Pointer to an EPT PML4 Table. */
243	typedef EPTPML4 *PEPTPML4;
244	/** Pointer to a const EPT PML4 Table. */
245	typedef const EPTPML4 *PCEPTPML4;
246
247	/**
248	* EPT Page Directory Pointer Entry. Bit view.
249	*/
250	#pragma pack(1)
251	typedef struct EPTPDPTEBITS
252	{
253	/** Present bit. */
254	uint64_t u1Present : 1;
255	/** Writable bit. */
256	uint64_t u1Write : 1;
257	/** Executable bit. */
258	uint64_t u1Execute : 1;
259	/** Reserved (must be 0). */
260	uint64_t u5Reserved : 5;
261	/** Available for software. */
262	uint64_t u4Available : 4;
263	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
264	uint64_t u40PhysAddr : 40;
265	/** Availabe for software. */
266	uint64_t u12Available : 12;
267	} EPTPDPTEBITS;
268	#pragma pack()
269	AssertCompileSize(EPTPDPTEBITS, 8);
270
271	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
272	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
273	/** The page shift to get the PDPT index. */
274	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
275	/** The PDPT index mask (apply to a shifted page address). */
276	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
277
278	/**
279	* EPT Page Directory Pointer.
280	*/
281	#pragma pack(1)
282	typedef union EPTPDPTE
283	{
284	/** Normal view. */
285	EPTPDPTEBITS n;
286	/** Unsigned integer view. */
287	X86PGPAEUINT u;
288	/** 64 bit unsigned integer view. */
289	uint64_t au64[1];
290	/** 32 bit unsigned integer view. */
291	uint32_t au32[2];
292	} EPTPDPTE;
293	#pragma pack()
294	/** Pointer to an EPT Page Directory Pointer Entry. */
295	typedef EPTPDPTE *PEPTPDPTE;
296	/** Pointer to a const EPT Page Directory Pointer Entry. */
297	typedef const EPTPDPTE *PCEPTPDPTE;
298	AssertCompileSize(EPTPDPTE, 8);
299
300	/**
301	* EPT Page Directory Pointer Table.
302	*/
303	#pragma pack(1)
304	typedef struct EPTPDPT
305	{
306	EPTPDPTE a[EPT_PG_ENTRIES];
307	} EPTPDPT;
308	#pragma pack()
309	/** Pointer to an EPT Page Directory Pointer Table. */
310	typedef EPTPDPT *PEPTPDPT;
311	/** Pointer to a const EPT Page Directory Pointer Table. */
312	typedef const EPTPDPT *PCEPTPDPT;
313
314
315	/**
316	* EPT Page Directory Table Entry. Bit view.
317	*/
318	#pragma pack(1)
319	typedef struct EPTPDEBITS
320	{
321	/** Present bit. */
322	uint64_t u1Present : 1;
323	/** Writable bit. */
324	uint64_t u1Write : 1;
325	/** Executable bit. */
326	uint64_t u1Execute : 1;
327	/** Reserved (must be 0). */
328	uint64_t u4Reserved : 4;
329	/** Big page (must be 0 here). */
330	uint64_t u1Size : 1;
331	/** Available for software. */
332	uint64_t u4Available : 4;
333	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
334	uint64_t u40PhysAddr : 40;
335	/** Availabe for software. */
336	uint64_t u12Available : 12;
337	} EPTPDEBITS;
338	#pragma pack()
339	AssertCompileSize(EPTPDEBITS, 8);
340
341	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
342	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
343	/** The page shift to get the PD index. */
344	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
345	/** The PD index mask (apply to a shifted page address). */
346	#define EPT_PD_MASK X86_PD_PAE_MASK
347
348	/**
349	* EPT 2MB Page Directory Table Entry. Bit view.
350	*/
351	#pragma pack(1)
352	typedef struct EPTPDE2MBITS
353	{
354	/** Present bit. */
355	uint64_t u1Present : 1;
356	/** Writable bit. */
357	uint64_t u1Write : 1;
358	/** Executable bit. */
359	uint64_t u1Execute : 1;
360	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
361	uint64_t u3EMT : 3;
362	/** Ignore PAT memory type */
363	uint64_t u1IgnorePAT : 1;
364	/** Big page (must be 1 here). */
365	uint64_t u1Size : 1;
366	/** Available for software. */
367	uint64_t u4Available : 4;
368	/** Reserved (must be 0). */
369	uint64_t u9Reserved : 9;
370	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
371	uint64_t u31PhysAddr : 31;
372	/** Availabe for software. */
373	uint64_t u12Available : 12;
374	} EPTPDE2MBITS;
375	#pragma pack()
376	AssertCompileSize(EPTPDE2MBITS, 8);
377
378	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
379	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
380
381	/**
382	* EPT Page Directory Table Entry.
383	*/
384	#pragma pack(1)
385	typedef union EPTPDE
386	{
387	/** Normal view. */
388	EPTPDEBITS n;
389	/** 2MB view (big). */
390	EPTPDE2MBITS b;
391	/** Unsigned integer view. */
392	X86PGPAEUINT u;
393	/** 64 bit unsigned integer view. */
394	uint64_t au64[1];
395	/** 32 bit unsigned integer view. */
396	uint32_t au32[2];
397	} EPTPDE;
398	#pragma pack()
399	/** Pointer to an EPT Page Directory Table Entry. */
400	typedef EPTPDE *PEPTPDE;
401	/** Pointer to a const EPT Page Directory Table Entry. */
402	typedef const EPTPDE *PCEPTPDE;
403	AssertCompileSize(EPTPDE, 8);
404
405	/**
406	* EPT Page Directory Table.
407	*/
408	#pragma pack(1)
409	typedef struct EPTPD
410	{
411	EPTPDE a[EPT_PG_ENTRIES];
412	} EPTPD;
413	#pragma pack()
414	/** Pointer to an EPT Page Directory Table. */
415	typedef EPTPD *PEPTPD;
416	/** Pointer to a const EPT Page Directory Table. */
417	typedef const EPTPD *PCEPTPD;
418
419
420	/**
421	* EPT Page Table Entry. Bit view.
422	*/
423	#pragma pack(1)
424	typedef struct EPTPTEBITS
425	{
426	/** 0 - Present bit.
427	* @remark This is a convenience "misnomer". The bit actually indicates
428	* read access and the CPU will consider an entry with any of the
429	* first three bits set as present. Since all our valid entries
430	* will have this bit set, it can be used as a present indicator
431	* and allow some code sharing. */
432	uint64_t u1Present : 1;
433	/** 1 - Writable bit. */
434	uint64_t u1Write : 1;
435	/** 2 - Executable bit. */
436	uint64_t u1Execute : 1;
437	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
438	uint64_t u3EMT : 3;
439	/** 6 - Ignore PAT memory type */
440	uint64_t u1IgnorePAT : 1;
441	/** 11:7 - Available for software. */
442	uint64_t u5Available : 5;
443	/** 51:12 - Physical address of page. Restricted by maximum physical
444	* address width of the cpu. */
445	uint64_t u40PhysAddr : 40;
446	/** 63:52 - Available for software. */
447	uint64_t u12Available : 12;
448	} EPTPTEBITS;
449	#pragma pack()
450	AssertCompileSize(EPTPTEBITS, 8);
451
452	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
453	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
454	/** The page shift to get the EPT PTE index. */
455	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
456	/** The EPT PT index mask (apply to a shifted page address). */
457	#define EPT_PT_MASK X86_PT_PAE_MASK
458
459	/**
460	* EPT Page Table Entry.
461	*/
462	#pragma pack(1)
463	typedef union EPTPTE
464	{
465	/** Normal view. */
466	EPTPTEBITS n;
467	/** Unsigned integer view. */
468	X86PGPAEUINT u;
469	/** 64 bit unsigned integer view. */
470	uint64_t au64[1];
471	/** 32 bit unsigned integer view. */
472	uint32_t au32[2];
473	} EPTPTE;
474	#pragma pack()
475	/** Pointer to an EPT Page Directory Table Entry. */
476	typedef EPTPTE *PEPTPTE;
477	/** Pointer to a const EPT Page Directory Table Entry. */
478	typedef const EPTPTE *PCEPTPTE;
479	AssertCompileSize(EPTPTE, 8);
480
481	/**
482	* EPT Page Table.
483	*/
484	#pragma pack(1)
485	typedef struct EPTPT
486	{
487	EPTPTE a[EPT_PG_ENTRIES];
488	} EPTPT;
489	#pragma pack()
490	/** Pointer to an extended page table. */
491	typedef EPTPT *PEPTPT;
492	/** Pointer to a const extended table. */
493	typedef const EPTPT *PCEPTPT;
494
495	/**
496	* VPID flush types.
497	*/
498	typedef enum
499	{
500	/** Invalidate a specific page. */
501	VMX_FLUSH_VPID_INDIV_ADDR = 0,
502	/** Invalidate one context (specific VPID). */
503	VMX_FLUSH_VPID_SINGLE_CONTEXT = 1,
504	/** Invalidate all contexts (all VPIDs). */
505	VMX_FLUSH_VPID_ALL_CONTEXTS = 2,
506	/** Invalidate a single VPID context retaining global mappings. */
507	VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
508	/** Unsupported by VirtualBox. */
509	VMX_FLUSH_VPID_NOT_SUPPORTED = 0xbad,
510	/** Unsupported by CPU. */
511	VMX_FLUSH_VPID_NONE = 0xb00,
512	/** 32bit hackishness. */
513	VMX_FLUSH_VPID_32BIT_HACK = 0x7fffffff
514	} VMX_FLUSH_VPID;
515
516	/**
517	* EPT flush types.
518	*/
519	typedef enum
520	{
521	/** Invalidate one context (specific EPT). */
522	VMX_FLUSH_EPT_SINGLE_CONTEXT = 1,
523	/* Invalidate all contexts (all EPTs) */
524	VMX_FLUSH_EPT_ALL_CONTEXTS = 2,
525	/** Unsupported by VirtualBox. */
526	VMX_FLUSH_EPT_NOT_SUPPORTED = 0xbad,
527	/** Unsupported by CPU. */
528	VMX_FLUSH_EPT_NONE = 0xb00,
529	/** 32bit hackishness. */
530	VMX_FLUSH_EPT_32BIT_HACK = 0x7fffffff
531	} VMX_FLUSH_EPT;
532	/** @} */
533
534	/** @name MSR autoload/store elements
535	* @{
536	*/
537	#pragma pack(1)
538	typedef struct
539	{
540	uint32_t u32IndexMSR;
541	uint32_t u32Reserved;
542	uint64_t u64Value;
543	} VMXMSR;
544	#pragma pack()
545	/** Pointer to an MSR load/store element. */
546	typedef VMXMSR *PVMXMSR;
547	/** Pointer to a const MSR load/store element. */
548	typedef const VMXMSR *PCVMXMSR;
549
550	/** @} */
551
552
553	/** @name VMX-capability qword
554	* @{
555	*/
556	#pragma pack(1)
557	typedef union
558	{
559	struct
560	{
561	/** Bits set here -must- be set in the correpsonding VM-execution controls. */
562	uint32_t disallowed0;
563	/** Bits cleared here -must- be cleared in the corresponding VM-execution
564	* controls. */
565	uint32_t allowed1;
566	} n;
567	uint64_t u;
568	} VMX_CAPABILITY;
569	#pragma pack()
570	/** @} */
571
572	/** @name VMX EFLAGS reserved bits.
573	* @{
574	*/
575	/** And-mask for setting reserved bits to zero */
576	#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
577	/** Or-mask for setting reserved bits to 1 */
578	#define VMX_EFLAGS_RESERVED_1 0x00000002
579	/** @} */
580
581	/** @name VMX Basic Exit Reasons.
582	* @{
583	*/
584	/** -1 Invalid exit code */
585	#define VMX_EXIT_INVALID -1
586	/** 0 Exception or non-maskable interrupt (NMI). */
587	#define VMX_EXIT_XCPT_NMI 0
588	/** 1 External interrupt. */
589	#define VMX_EXIT_EXT_INT 1
590	/** 2 Triple fault. */
591	#define VMX_EXIT_TRIPLE_FAULT 2
592	/** 3 INIT signal. */
593	#define VMX_EXIT_INIT_SIGNAL 3
594	/** 4 Start-up IPI (SIPI). */
595	#define VMX_EXIT_SIPI 4
596	/** 5 I/O system-management interrupt (SMI). */
597	#define VMX_EXIT_IO_SMI 5
598	/** 6 Other SMI. */
599	#define VMX_EXIT_SMI 6
600	/** 7 Interrupt window exiting. */
601	#define VMX_EXIT_INT_WINDOW 7
602	/** 8 NMI window exiting. */
603	#define VMX_EXIT_NMI_WINDOW 8
604	/** 9 Task switch. */
605	#define VMX_EXIT_TASK_SWITCH 9
606	/** 10 Guest software attempted to execute CPUID. */
607	#define VMX_EXIT_CPUID 10
608	/** 10 Guest software attempted to execute GETSEC. */
609	#define VMX_EXIT_GETSEC 11
610	/** 12 Guest software attempted to execute HLT. */
611	#define VMX_EXIT_HLT 12
612	/** 13 Guest software attempted to execute INVD. */
613	#define VMX_EXIT_INVD 13
614	/** 14 Guest software attempted to execute INVLPG. */
615	#define VMX_EXIT_INVLPG 14
616	/** 15 Guest software attempted to execute RDPMC. */
617	#define VMX_EXIT_RDPMC 15
618	/** 16 Guest software attempted to execute RDTSC. */
619	#define VMX_EXIT_RDTSC 16
620	/** 17 Guest software attempted to execute RSM in SMM. */
621	#define VMX_EXIT_RSM 17
622	/** 18 Guest software executed VMCALL. */
623	#define VMX_EXIT_VMCALL 18
624	/** 19 Guest software executed VMCLEAR. */
625	#define VMX_EXIT_VMCLEAR 19
626	/** 20 Guest software executed VMLAUNCH. */
627	#define VMX_EXIT_VMLAUNCH 20
628	/** 21 Guest software executed VMPTRLD. */
629	#define VMX_EXIT_VMPTRLD 21
630	/** 22 Guest software executed VMPTRST. */
631	#define VMX_EXIT_VMPTRST 22
632	/** 23 Guest software executed VMREAD. */
633	#define VMX_EXIT_VMREAD 23
634	/** 24 Guest software executed VMRESUME. */
635	#define VMX_EXIT_VMRESUME 24
636	/** 25 Guest software executed VMWRITE. */
637	#define VMX_EXIT_VMWRITE 25
638	/** 26 Guest software executed VMXOFF. */
639	#define VMX_EXIT_VMXOFF 26
640	/** 27 Guest software executed VMXON. */
641	#define VMX_EXIT_VMXON 27
642	/** 28 Control-register accesses. */
643	#define VMX_EXIT_MOV_CRX 28
644	/** 29 Debug-register accesses. */
645	#define VMX_EXIT_MOV_DRX 29
646	/** 30 I/O instruction. */
647	#define VMX_EXIT_IO_INSTR 30
648	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
649	#define VMX_EXIT_RDMSR 31
650	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
651	#define VMX_EXIT_WRMSR 32
652	/** 33 VM-entry failure due to invalid guest state. */
653	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
654	/** 34 VM-entry failure due to MSR loading. */
655	#define VMX_EXIT_ERR_MSR_LOAD 34
656	/** 36 Guest software executed MWAIT. */
657	#define VMX_EXIT_MWAIT 36
658	/** 37 VM exit due to monitor trap flag. */
659	#define VMX_EXIT_MTF 37
660	/** 39 Guest software attempted to execute MONITOR. */
661	#define VMX_EXIT_MONITOR 39
662	/** 40 Guest software attempted to execute PAUSE. */
663	#define VMX_EXIT_PAUSE 40
664	/** 41 VM-entry failure due to machine-check. */
665	#define VMX_EXIT_ERR_MACHINE_CHECK 41
666	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
667	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
668	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
669	#define VMX_EXIT_APIC_ACCESS 44
670	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
671	#define VMX_EXIT_XDTR_ACCESS 46
672	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
673	#define VMX_EXIT_TR_ACCESS 47
674	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
675	#define VMX_EXIT_EPT_VIOLATION 48
676	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
677	#define VMX_EXIT_EPT_MISCONFIG 49
678	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
679	#define VMX_EXIT_INVEPT 50
680	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
681	#define VMX_EXIT_RDTSCP 51
682	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
683	#define VMX_EXIT_PREEMPT_TIMER 52
684	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
685	#define VMX_EXIT_INVVPID 53
686	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
687	#define VMX_EXIT_WBINVD 54
688	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
689	#define VMX_EXIT_XSETBV 55
690	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
691	#define VMX_EXIT_RDRAND 57
692	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
693	#define VMX_EXIT_INVPCID 58
694	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
695	#define VMX_EXIT_VMFUNC 59
696	/** The maximum exit value (inclusive). */
697	#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
698	/** @} */
699
700
701	/** @name VM Instruction Errors
702	* @{
703	*/
704	/** 1 VMCALL executed in VMX root operation. */
705	#define VMX_ERROR_VMCALL 1
706	/** 2 VMCLEAR with invalid physical address. */
707	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
708	/** 3 VMCLEAR with VMXON pointer. */
709	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
710	/** 4 VMLAUNCH with non-clear VMCS. */
711	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
712	/** 5 VMRESUME with non-launched VMCS. */
713	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
714	/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
715	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
716	/** 7 VM entry with invalid control field(s). */
717	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
718	/** 8 VM entry with invalid host-state field(s). */
719	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
720	/** 9 VMPTRLD with invalid physical address. */
721	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
722	/** 10 VMPTRLD with VMXON pointer. */
723	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
724	/** 11 VMPTRLD with incorrect VMCS revision identifier. */
725	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
726	/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
727	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
728	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
729	/** 13 VMWRITE to read-only VMCS component. */
730	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
731	/** 15 VMXON executed in VMX root operation. */
732	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
733	/** 16 VM entry with invalid executive-VMCS pointer. */
734	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
735	/** 17 VM entry with non-launched executive VMCS. */
736	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
737	/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
738	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
739	/** 19 VMCALL with non-clear VMCS. */
740	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
741	/** 20 VMCALL with invalid VM-exit control fields. */
742	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
743	/** 22 VMCALL with incorrect MSEG revision identifier. */
744	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
745	/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
746	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
747	/** 24 VMCALL with invalid SMM-monitor features. */
748	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
749	/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
750	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
751	/** 26 VM entry with events blocked by MOV SS. */
752	#define VMX_ERROR_VMENTRY_MOV_SS 26
753	/** 26 Invalid operand to INVEPT/INVVPID. */
754	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
755
756	/** @} */
757
758
759	/** @name VMX MSRs - Basic VMX information.
760	* @{
761	*/
762	/** VMCS revision identifier used by the processor. */
763	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
764	/** Size of the VMCS. */
765	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0xFFF)
766	/** Width of physical address used for the VMCS.
767	* 0 -> limited to the available amount of physical ram
768	* 1 -> within the first 4 GB
769	*/
770	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
771	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
772	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
773	/** Memory type that must be used for the VMCS. */
774	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
775	/** @} */
776
777
778	/** @name VMX MSRs - Misc VMX info.
779	* @{
780	*/
781	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
782	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
783	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
784	#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
785	/** Activity states supported by the implementation. */
786	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
787	/** Number of CR3 target values supported by the processor. (0-256) */
788	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
789	/** Maximum nr of MSRs in the VMCS. (N+1)512. /
790	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
791	/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
792	#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
793	/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
794	#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
795	/** Whether VMWRITE can be used to write VM-exit information fields. */
796	#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
797	/** MSEG revision identifier used by the processor. */
798	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
799	/** @} */
800
801
802	/** @name VMX MSRs - VMCS enumeration field info
803	* @{
804	*/
805	/** Highest field index. */
806	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
807	/** @} */
808
809
810	/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
811	* @{
812	*/
813	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
814	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
815	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
816	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
817	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
818	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
819	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
820	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
821	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
822	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
823	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
824	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
825	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
826	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
827	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
828	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
829	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
830	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
831	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
832	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
833	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
834	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
835	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
836	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
837	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
838
839	/** @} */
840
841	/** @name Extended Page Table Pointer (EPTP)
842	* @{
843	*/
844	/** Uncachable EPT paging structure memory type. */
845	#define VMX_EPT_MEMTYPE_UC 0
846	/** Write-back EPT paging structure memory type. */
847	#define VMX_EPT_MEMTYPE_WB 6
848	/** Shift value to get the EPT page walk length (bits 5-3) */
849	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
850	/** Mask value to get the EPT page walk length (bits 5-3) */
851	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
852	/** Default EPT page-walk length (1 less than the actual EPT page-walk
853	* length) */
854	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
855	/** @} */
856
857
858	/** @name VMCS field encoding - 16 bits guest fields
859	* @{
860	*/
861	#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
862	#define VMX_VMCS16_GUEST_FIELD_ES 0x800
863	#define VMX_VMCS16_GUEST_FIELD_CS 0x802
864	#define VMX_VMCS16_GUEST_FIELD_SS 0x804
865	#define VMX_VMCS16_GUEST_FIELD_DS 0x806
866	#define VMX_VMCS16_GUEST_FIELD_FS 0x808
867	#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
868	#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
869	#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
870	/** @} */
871
872	/** @name VMCS field encoding - 16 bits host fields
873	* @{
874	*/
875	#define VMX_VMCS16_HOST_FIELD_ES 0xC00
876	#define VMX_VMCS16_HOST_FIELD_CS 0xC02
877	#define VMX_VMCS16_HOST_FIELD_SS 0xC04
878	#define VMX_VMCS16_HOST_FIELD_DS 0xC06
879	#define VMX_VMCS16_HOST_FIELD_FS 0xC08
880	#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
881	#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
882	/** @} */
883
884	/** @name VMCS field encoding - 64 bits host fields
885	* @{
886	*/
887	#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
888	#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
889	#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
890	#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
891	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
892	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
893	/** @} */
894
895
896	/** @name VMCS field encoding - 64 Bits control fields
897	* @{
898	*/
899	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
900	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
901	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
902	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
903
904	/* Optional */
905	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
906	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
907
908	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
909	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
910	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
911	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
912
913	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
914	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
915
916	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
917	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
918
919	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
920	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
921
922	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
923	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
924	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
925
926	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
927	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
928	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
929
930	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
931	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
932	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
933
934	/** Extended page table pointer. */
935	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
936	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
937
938	/** Extended page table pointer lists. */
939	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
940	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
941
942	/** VM-exit guest phyiscal address. */
943	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
944	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
945	/** @} */
946
947
948	/** @name VMCS field encoding - 64 Bits guest fields
949	* @{
950	*/
951	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
952	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
953	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
954	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
955	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
956	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
957	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
958	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
959	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
960	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
961	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
962	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
963	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
964	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
965	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
966	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
967	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
968	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
969	/** @} */
970
971
972	/** @name VMCS field encoding - 32 Bits control fields
973	* @{
974	*/
975	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
976	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
977	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
978	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
979	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
980	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
981	#define VMX_VMCS32_CTRL_EXIT 0x400C
982	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
983	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
984	#define VMX_VMCS32_CTRL_ENTRY 0x4012
985	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
986	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
987	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
988	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
989	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
990	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
991	/** @} */
992
993
994	/** @name VMX_VMCS_CTRL_PIN_EXEC
995	* @{
996	*/
997	/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
998	#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
999	/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1000	#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1001	/** Virtual NMIs. */
1002	#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1003	/** Activate VMX preemption timer. */
1004	#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1005	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1006	/** @} */
1007
1008	/** @name VMX_VMCS_CTRL_PROC_EXEC
1009	* @{
1010	*/
1011	/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
1012	#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1013	/** Use timestamp counter offset. */
1014	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1015	/** VM Exit when executing the HLT instruction. */
1016	#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1017	/** VM Exit when executing the INVLPG instruction. */
1018	#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1019	/** VM Exit when executing the MWAIT instruction. */
1020	#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1021	/** VM Exit when executing the RDPMC instruction. */
1022	#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1023	/** VM Exit when executing the RDTSC/RDTSCP instruction. */
1024	#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1025	/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1026	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1027	/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1028	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1029	/** VM Exit on CR8 loads. */
1030	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1031	/** VM Exit on CR8 stores. */
1032	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1033	/** Use TPR shadow. */
1034	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1035	/** VM Exit when virtual nmi blocking is disabled. */
1036	#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1037	/** VM Exit when executing a MOV DRx instruction. */
1038	#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1039	/** VM Exit when executing IO instructions. */
1040	#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1041	/** Use IO bitmaps. */
1042	#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1043	/** Monitor trap flag. */
1044	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1045	/** Use MSR bitmaps. */
1046	#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1047	/** VM Exit when executing the MONITOR instruction. */
1048	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1049	/** VM Exit when executing the PAUSE instruction. */
1050	#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1051	/** Determines whether the secondary processor based VM-execution controls are used. */
1052	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1053	/** @} */
1054
1055	/** @name VMX_VMCS_CTRL_PROC_EXEC2
1056	* @{
1057	*/
1058	/** Virtualize APIC access. */
1059	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1060	/** EPT supported/enabled. */
1061	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1062	/** Descriptor table instructions cause VM-exits. */
1063	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1064	/** RDTSCP supported/enabled. */
1065	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1066	/** Virtualize x2APIC mode. */
1067	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1068	/** VPID supported/enabled. */
1069	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1070	/** VM Exit when executing the WBINVD instruction. */
1071	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1072	/** Unrestricted guest execution. */
1073	#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1074	/** A specified nr of pause loops cause a VM-exit. */
1075	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1076	/** VM Exit when executing RDRAND instructions. */
1077	#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1078	/** Enables INVPCID instructions. */
1079	#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1080	/** Enables VMFUNC instructions. */
1081	#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1082	/** @} */
1083
1084
1085	/** @name VMX_VMCS_CTRL_ENTRY
1086	* @{
1087	*/
1088	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1089	#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1090	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1091	#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1092	/** In SMM mode after VM-entry. */
1093	#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1094	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1095	#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1096	/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
1097	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1098	/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
1099	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1100	/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
1101	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1102	/** @} */
1103
1104
1105	/** @name VMX_VMCS_CTRL_EXIT
1106	* @{
1107	*/
1108	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1109	#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1110	/** Return to long mode after a VM-exit. */
1111	#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1112	/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
1113	#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1114	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1115	#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1116	/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
1117	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1118	/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
1119	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1120	/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
1121	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1122	/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
1123	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1124	/** This control determines whether the value of the VMX preemption timer is
1125	* saved on every VM exit. */
1126	#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1127	/** @} */
1128
1129
1130	/** @name VMX_VMCS_CTRL_VMFUNC
1131	* @{
1132	*/
1133	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1134	#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1135	/** @} */
1136
1137
1138	/** @name VMCS field encoding - 32 Bits read-only fields
1139	* @{
1140	*/
1141	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1142	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1143	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1144	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1145	#define VMX_VMCS32_RO_IDT_INFO 0x4408
1146	#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1147	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1148	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1149	/** @} */
1150
1151	/** @name VMX_VMCS32_RO_EXIT_REASON
1152	* @{
1153	*/
1154	#define VMX_EXIT_REASON_BASIC(a) (a & 0xffff)
1155	/** @} */
1156
1157	/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1158	* @{
1159	*/
1160	#define VMX_ENTRY_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
1161	/** @} */
1162
1163
1164	/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1165	* @{
1166	*/
1167	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
1168	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1169	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1170	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1171	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1172	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
1173	#ifdef VBOX_WITH_OLD_VTX_CODE
1174	# define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
1175	#endif
1176	#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1177	#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) (a & RT_BIT(31))
1178	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1179	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
1180	/** @} */
1181
1182	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1183	* @{
1184	*/
1185	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1186	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1187	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1188	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4 /*< int xx /
1189	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DB_XCPT 5 /*< Why are we getting this one?? /
1190	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1191	/** @} */
1192
1193	/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1194	* @{
1195	*/
1196	#define VMX_IDT_VECTORING_INFO_VECTOR(a) (a & 0xff)
1197	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1198	#define VMX_IDT_VECTORING_INFO_TYPE(a) ((a >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1199	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1200	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1201	#define VMX_IDT_VECTORING_INFO_VALID(a) (a & RT_BIT(31))
1202	#define VMX_ENTRY_INTR_INFO_FROM_EXIT_IDT_INFO(a) (a & ~RT_BIT(12))
1203	/** @} */
1204
1205	/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1206	* @{
1207	*/
1208	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1209	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1210	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1211	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1212	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1213	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1214	/** @} */
1215
1216
1217	/** @name VMCS field encoding - 32 Bits guest state fields
1218	* @{
1219	*/
1220	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1221	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1222	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1223	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1224	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1225	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1226	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1227	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1228	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1229	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1230	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1231	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1232	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1233	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1234	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1235	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1236	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1237	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1238	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1239	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1240	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
1241	#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1242	/** @} */
1243
1244
1245	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1246	* @{
1247	*/
1248	/** The logical processor is active. */
1249	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1250	/** The logical processor is inactive, because executed a HLT instruction. */
1251	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1252	/** The logical processor is inactive, because of a triple fault or other
1253	* serious error. */
1254	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1255	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1256	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1257	/** @} */
1258
1259
1260	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1261	* @{
1262	*/
1263	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1264	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1265	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1266	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1267	/** @} */
1268
1269
1270	/** @name VMCS field encoding - 32 Bits host state fields
1271	* @{
1272	*/
1273	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1274	/** @} */
1275
1276	/** @name Natural width control fields
1277	* @{
1278	*/
1279	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1280	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1281	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1282	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1283	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1284	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1285	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1286	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1287	/** @} */
1288
1289
1290	/** @name Natural width read-only data fields
1291	* @{
1292	*/
1293	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1294	#define VMX_VMCS_RO_IO_RCX 0x6402
1295	#define VMX_VMCS_RO_IO_RSX 0x6404
1296	#define VMX_VMCS_RO_IO_RDI 0x6406
1297	#define VMX_VMCS_RO_IO_RIP 0x6408
1298	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1299	/** @} */
1300
1301
1302	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1303	* @{
1304	*/
1305	/** 0-2: Debug register number */
1306	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1307	/** 3: Reserved; cleared to 0. */
1308	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1309	/** 4: Direction of move (0 = write, 1 = read) */
1310	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1311	/** 5-7: Reserved; cleared to 0. */
1312	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1313	/** 8-11: General purpose register number. */
1314	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1315	/** Rest: reserved. */
1316	/** @} */
1317
1318	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1319	* @{
1320	*/
1321	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1322	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1323	/** @} */
1324
1325
1326
1327	/** @name CRx accesses
1328	* @{
1329	*/
1330	/** 0-3: Control register number (0 for CLTS & LMSW) */
1331	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1332	/** 4-5: Access type. */
1333	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1334	/** 6: LMSW operand type */
1335	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1336	/** 7: Reserved; cleared to 0. */
1337	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1338	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1339	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1340	/** 12-15: Reserved; cleared to 0. */
1341	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1342	/** 16-31: LMSW source data (else 0). */
1343	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1344	/** Rest: reserved. */
1345	/** @} */
1346
1347	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1348	* @{
1349	*/
1350	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1351	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1352	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1353	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1354	/** @} */
1355
1356	/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1357	* @{
1358	*/
1359	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1360	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1361	/** Task switch caused by a call instruction. */
1362	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1363	/** Task switch caused by an iret instruction. */
1364	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1365	/** Task switch caused by a jmp instruction. */
1366	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1367	/** Task switch caused by an interrupt gate. */
1368	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1369	/** @} */
1370
1371
1372	/** @name VMX_EXIT_EPT_VIOLATION
1373	* @{
1374	*/
1375	/** Set if the violation was caused by a data read. */
1376	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1377	/** Set if the violation was caused by a data write. */
1378	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1379	/** Set if the violation was caused by an insruction fetch. */
1380	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1381	/** AND of the present bit of all EPT structures. */
1382	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1383	/** AND of the write bit of all EPT structures. */
1384	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1385	/** AND of the execute bit of all EPT structures. */
1386	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1387	/** Set if the guest linear address field contains the faulting address. */
1388	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1389	/** If bit 7 is one: (reserved otherwise)
1390	* 1 - violation due to physical address access.
1391	* 0 - violation caused by page walk or access/dirty bit updates
1392	*/
1393	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1394	/** @} */
1395
1396
1397	/** @name VMX_EXIT_PORT_IO
1398	* @{
1399	*/
1400	/** 0-2: IO operation width. */
1401	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1402	/** 3: IO operation direction. */
1403	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1404	/** 4: String IO operation. */
1405	#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1406	/** 5: Repeated IO operation. */
1407	#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1408	/** 6: Operand encoding. */
1409	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1410	/** 16-31: IO Port (0-0xffff). */
1411	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1412	/* Rest reserved. */
1413	/** @} */
1414
1415	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1416	* @{
1417	*/
1418	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1419	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1420	/** @} */
1421
1422
1423	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1424	* @{
1425	*/
1426	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1427	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1428	/** @} */
1429
1430	/** @name VMX_EXIT_APIC_ACCESS
1431	* @{
1432	*/
1433	/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1434	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1435	/** 12-15: Access type. */
1436	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000)
1437	/* Rest reserved. */
1438	/** @} */
1439
1440
1441	/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1442	* @{
1443	*/
1444	/** Linear read access. */
1445	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1446	/** Linear write access. */
1447	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1448	/** Linear instruction fetch access. */
1449	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1450	/** Linear read/write access during event delivery. */
1451	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1452	/** Physical read/write access during event delivery. */
1453	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1454	/** Physical access for an instruction fetch or during instruction execution. */
1455	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1456	/** @} */
1457
1458	/** @} */
1459
1460	/** @name VMCS field encoding - Natural width guest state fields
1461	* @{
1462	*/
1463	#define VMX_VMCS_GUEST_CR0 0x6800
1464	#define VMX_VMCS_GUEST_CR3 0x6802
1465	#define VMX_VMCS_GUEST_CR4 0x6804
1466	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1467	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1468	#define VMX_VMCS_GUEST_SS_BASE 0x680A
1469	#define VMX_VMCS_GUEST_DS_BASE 0x680C
1470	#define VMX_VMCS_GUEST_FS_BASE 0x680E
1471	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1472	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1473	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1474	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1475	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1476	#define VMX_VMCS_GUEST_DR7 0x681A
1477	#define VMX_VMCS_GUEST_RSP 0x681C
1478	#define VMX_VMCS_GUEST_RIP 0x681E
1479	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1480	#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1481	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1482	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1483	/** @} */
1484
1485
1486	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1487	* @{
1488	*/
1489	/** Hardware breakpoint 0 was met. */
1490	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1491	/** Hardware breakpoint 1 was met. */
1492	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1493	/** Hardware breakpoint 2 was met. */
1494	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1495	/** Hardware breakpoint 3 was met. */
1496	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1497	/** At least one data or IO breakpoint was hit. */
1498	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1499	/** A debug exception would have been triggered by single-step execution mode. */
1500	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1501	/** Bits 4-11, 13 and 15-63 are reserved. */
1502
1503	/** @} */
1504
1505	/** @name VMCS field encoding - Natural width host state fields
1506	* @{
1507	*/
1508	#define VMX_VMCS_HOST_CR0 0x6C00
1509	#define VMX_VMCS_HOST_CR3 0x6C02
1510	#define VMX_VMCS_HOST_CR4 0x6C04
1511	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1512	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1513	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1514	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1515	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1516	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1517	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1518	#define VMX_VMCS_HOST_RSP 0x6C14
1519	#define VMX_VMCS_HOST_RIP 0x6C16
1520	/** @} */
1521
1522	/** @} */
1523
1524
1525	#if RT_INLINE_ASM_GNU_STYLE
1526	# define __STR(x) #x
1527	# define STR(x) __STR(x)
1528	#endif
1529
1530
1531	/** @defgroup grp_vmx_asm vmx assembly helpers
1532	* @ingroup grp_vmx
1533	* @{
1534	*/
1535
1536	/**
1537	* Restores some host-state fields that need not be done on every VM-exit.
1538	*
1539	* @returns VBox status code.
1540	* @param fRestoreHostFlags Flags of which host registers needs to be
1541	* restored.
1542	* @param pRestoreHost Pointer to the host-restore structure.
1543	*/
1544	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1545
1546
1547	/**
1548	* Executes VMXON
1549	*
1550	* @returns VBox status code
1551	* @param pVMXOn Physical address of VMXON structure
1552	*/
1553	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1554	DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1555	#else
1556	DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1557	{
1558	int rc = VINF_SUCCESS;
1559	# if RT_INLINE_ASM_GNU_STYLE
1560	__asm__ __volatile__ (
1561	"push %3 \n\t"
1562	"push %2 \n\t"
1563	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1564	"ja 2f \n\t"
1565	"je 1f \n\t"
1566	"movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1567	"jmp 2f \n\t"
1568	"1: \n\t"
1569	"movl $"STR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1570	"2: \n\t"
1571	"add $8, %%esp \n\t"
1572	:"=rm"(rc)
1573	:"0"(VINF_SUCCESS),
1574	"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1575	"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1576	:"memory"
1577	);
1578	# else
1579	__asm
1580	{
1581	push dword ptr [pVMXOn+4]
1582	push dword ptr [pVMXOn]
1583	_emit 0xF3
1584	_emit 0x0F
1585	_emit 0xC7
1586	_emit 0x34
1587	_emit 0x24 /* VMXON [esp] */
1588	jnc vmxon_good
1589	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1590	jmp the_end
1591
1592	vmxon_good:
1593	jnz the_end
1594	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1595	the_end:
1596	add esp, 8
1597	}
1598	# endif
1599	return rc;
1600	}
1601	#endif
1602
1603
1604	/**
1605	* Executes VMXOFF
1606	*/
1607	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1608	DECLASM(void) VMXDisable(void);
1609	#else
1610	DECLINLINE(void) VMXDisable(void)
1611	{
1612	# if RT_INLINE_ASM_GNU_STYLE
1613	__asm__ __volatile__ (
1614	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1615	);
1616	# else
1617	__asm
1618	{
1619	_emit 0x0F
1620	_emit 0x01
1621	_emit 0xC4 /* VMXOFF */
1622	}
1623	# endif
1624	}
1625	#endif
1626
1627
1628	/**
1629	* Executes VMCLEAR
1630	*
1631	* @returns VBox status code
1632	* @param pVMCS Physical address of VM control structure
1633	*/
1634	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1635	DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1636	#else
1637	DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1638	{
1639	int rc = VINF_SUCCESS;
1640	# if RT_INLINE_ASM_GNU_STYLE
1641	__asm__ __volatile__ (
1642	"push %3 \n\t"
1643	"push %2 \n\t"
1644	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1645	"jnc 1f \n\t"
1646	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1647	"1: \n\t"
1648	"add $8, %%esp \n\t"
1649	:"=rm"(rc)
1650	:"0"(VINF_SUCCESS),
1651	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1652	"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1653	:"memory"
1654	);
1655	# else
1656	__asm
1657	{
1658	push dword ptr [pVMCS+4]
1659	push dword ptr [pVMCS]
1660	_emit 0x66
1661	_emit 0x0F
1662	_emit 0xC7
1663	_emit 0x34
1664	_emit 0x24 /* VMCLEAR [esp] */
1665	jnc success
1666	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1667	success:
1668	add esp, 8
1669	}
1670	# endif
1671	return rc;
1672	}
1673	#endif
1674
1675
1676	/**
1677	* Executes VMPTRLD
1678	*
1679	* @returns VBox status code
1680	* @param pVMCS Physical address of VMCS structure
1681	*/
1682	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1683	DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1684	#else
1685	DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1686	{
1687	int rc = VINF_SUCCESS;
1688	# if RT_INLINE_ASM_GNU_STYLE
1689	__asm__ __volatile__ (
1690	"push %3 \n\t"
1691	"push %2 \n\t"
1692	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1693	"jnc 1f \n\t"
1694	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1695	"1: \n\t"
1696	"add $8, %%esp \n\t"
1697	:"=rm"(rc)
1698	:"0"(VINF_SUCCESS),
1699	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1700	"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1701	);
1702	# else
1703	__asm
1704	{
1705	push dword ptr [pVMCS+4]
1706	push dword ptr [pVMCS]
1707	_emit 0x0F
1708	_emit 0xC7
1709	_emit 0x34
1710	_emit 0x24 /* VMPTRLD [esp] */
1711	jnc success
1712	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1713
1714	success:
1715	add esp, 8
1716	}
1717	# endif
1718	return rc;
1719	}
1720	#endif
1721
1722	/**
1723	* Executes VMPTRST
1724	*
1725	* @returns VBox status code
1726	* @param pVMCS Address that will receive the current pointer
1727	*/
1728	DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1729
1730	/**
1731	* Executes VMWRITE
1732	*
1733	* @returns VBox status code
1734	* @param idxField VMCS index
1735	* @param u32Val 32 bits value
1736	*/
1737	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1738	DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
1739	#else
1740	DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
1741	{
1742	int rc = VINF_SUCCESS;
1743	# if RT_INLINE_ASM_GNU_STYLE
1744	__asm__ __volatile__ (
1745	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1746	"ja 2f \n\t"
1747	"je 1f \n\t"
1748	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1749	"jmp 2f \n\t"
1750	"1: \n\t"
1751	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1752	"2: \n\t"
1753	:"=rm"(rc)
1754	:"0"(VINF_SUCCESS),
1755	"a"(idxField),
1756	"d"(u32Val)
1757	);
1758	# else
1759	__asm
1760	{
1761	push dword ptr [u32Val]
1762	mov eax, [idxField]
1763	_emit 0x0F
1764	_emit 0x79
1765	_emit 0x04
1766	_emit 0x24 /* VMWRITE eax, [esp] */
1767	jnc valid_vmcs
1768	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1769	jmp the_end
1770
1771	valid_vmcs:
1772	jnz the_end
1773	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1774	the_end:
1775	add esp, 4
1776	}
1777	# endif
1778	return rc;
1779	}
1780	#endif
1781
1782	/**
1783	* Executes VMWRITE
1784	*
1785	* @returns VBox status code
1786	* @param idxField VMCS index
1787	* @param u64Val 16, 32 or 64 bits value
1788	*/
1789	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1790	DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
1791	#else
1792	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1793
1794	#define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
1795	#endif
1796
1797	#ifdef VBOX_WITH_OLD_VTX_CODE
1798	# if HC_ARCH_BITS == 64
1799	# define VMXWriteVmcs VMXWriteVmcs64
1800	# else
1801	# define VMXWriteVmcs VMXWriteVmcs32
1802	# endif
1803	#else /* !VBOX_WITH_OLD_VTX_CODE */
1804	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1805	# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
1806	VMXWriteVmcs64(idxField, uVal) \
1807	: VMXWriteVmcs32(idxField, uVal)
1808	# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
1809	VMXWriteVmcs64(idxField, u64Val) \
1810	: VMXWriteVmcs32(idxField, u64Val)
1811	# elif HC_ARCH_BITS == 32
1812	# define VMXWriteVmcsHstN VMXWriteVmcs32
1813	# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
1814	# else /* HC_ARCH_BITS == 64 */
1815	# define VMXWriteVmcsHstN VMXWriteVmcs64
1816	# define VMXWriteVmcsGstN VMXWriteVmcs64
1817	# endif
1818	#endif /* !VBOX_WITH_OLD_VTX_CODE */
1819
1820
1821	/**
1822	* Invalidate a page using invept
1823	* @returns VBox status code
1824	* @param enmFlush Type of flush
1825	* @param pDescriptor Descriptor
1826	*/
1827	DECLASM(int) VMXR0InvEPT(VMX_FLUSH_EPT enmFlush, uint64_t *pDescriptor);
1828
1829	/**
1830	* Invalidate a page using invvpid
1831	* @returns VBox status code
1832	* @param enmFlush Type of flush
1833	* @param pDescriptor Descriptor
1834	*/
1835	DECLASM(int) VMXR0InvVPID(VMX_FLUSH_VPID enmFlush, uint64_t *pDescriptor);
1836
1837	/**
1838	* Executes VMREAD
1839	*
1840	* @returns VBox status code
1841	* @param idxField VMCS index
1842	* @param pData Ptr to store VM field value
1843	*/
1844	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1845	DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
1846	#else
1847	DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
1848	{
1849	int rc = VINF_SUCCESS;
1850	# if RT_INLINE_ASM_GNU_STYLE
1851	__asm__ __volatile__ (
1852	"movl $"STR(VINF_SUCCESS)", %0 \n\t"
1853	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1854	"ja 2f \n\t"
1855	"je 1f \n\t"
1856	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1857	"jmp 2f \n\t"
1858	"1: \n\t"
1859	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1860	"2: \n\t"
1861	:"=&r"(rc),
1862	"=d"(*pData)
1863	:"a"(idxField),
1864	"d"(0)
1865	);
1866	# else
1867	__asm
1868	{
1869	sub esp, 4
1870	mov dword ptr [esp], 0
1871	mov eax, [idxField]
1872	_emit 0x0F
1873	_emit 0x78
1874	_emit 0x04
1875	_emit 0x24 /* VMREAD eax, [esp] */
1876	mov edx, pData
1877	pop dword ptr [edx]
1878	jnc valid_vmcs
1879	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1880	jmp the_end
1881
1882	valid_vmcs:
1883	jnz the_end
1884	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1885	the_end:
1886	}
1887	# endif
1888	return rc;
1889	}
1890	#endif
1891
1892	/**
1893	* Executes VMREAD
1894	*
1895	* @returns VBox status code
1896	* @param idxField VMCS index
1897	* @param pData Ptr to store VM field value
1898	*/
1899	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1900	DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
1901	#else
1902	DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
1903	{
1904	int rc;
1905
1906	uint32_t val_hi, val;
1907	rc = VMXReadVmcs32(idxField, &val);
1908	rc \|= VMXReadVmcs32(idxField + 1, &val_hi);
1909	AssertRC(rc);
1910	*pData = RT_MAKE_U64(val, val_hi);
1911	return rc;
1912	}
1913	#endif
1914
1915	#ifdef VBOX_WITH_OLD_VTX_CODE
1916	# if HC_ARCH_BITS == 64
1917	# define VMXReadVmcsField VMXReadVmcs64
1918	# else
1919	# define VMXReadVmcsField VMXReadVmcs32
1920	# endif
1921	#endif
1922
1923	/**
1924	* Gets the last instruction error value from the current VMCS
1925	*
1926	* @returns error value
1927	*/
1928	DECLINLINE(uint32_t) VMXGetLastError(void)
1929	{
1930	#if HC_ARCH_BITS == 64
1931	uint64_t uLastError = 0;
1932	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1933	AssertRC(rc);
1934	return (uint32_t)uLastError;
1935
1936	#else /* 32-bit host: */
1937	uint32_t uLastError = 0;
1938	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1939	AssertRC(rc);
1940	return uLastError;
1941	#endif
1942	}
1943
1944	#ifdef IN_RING0
1945	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1946	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
1947	#endif /* IN_RING0 */
1948
1949	/** @} */
1950
1951	#endif
1952

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 46601

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