hm_vmx.h@ 47445

Last change on this file since 47445 was 47445, checked in by vboxsync, 12 years ago
IEM,HM,PGM: Started on string I/O optimizations using IEM (disabled). Cleaned up confusing status code handling in hmR0VmxCheckForceFlags (involving PGM) as well as some use of incorrect doxygen groups (@name).
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File size: 83.0 KB

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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2013 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# include <intrin.h>
38	/* We always want them as intrinsics, no functions. */
39	# pragma intrinsic(__vmx_on)
40	# pragma intrinsic(__vmx_off)
41	# pragma intrinsic(__vmx_vmclear)
42	# pragma intrinsic(__vmx_vmptrld)
43	# pragma intrinsic(__vmx_vmread)
44	# pragma intrinsic(__vmx_vmwrite)
45	# define VMX_USE_MSC_INTRINSICS 1
46	#else
47	# define VMX_USE_MSC_INTRINSICS 0
48	#endif
49
50
51	/** @defgroup grp_vmx vmx Types and Definitions
52	* @ingroup grp_hm
53	* @{
54	*/
55
56	/** @name Host-state restoration flags.
57	* @{
58	*/
59	/* If you change these values don't forget to update the assembly defines as well! */
60	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
61	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
62	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
63	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
64	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
65	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
66	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
67	/** @} */
68
69	/**
70	* Host-state restoration structure.
71	* This holds host-state fields that require manual restoration.
72	* Assembly version found in hm_vmx.mac (should be automatically verified).
73	*/
74	typedef struct VMXRESTOREHOST
75	{
76	RTSEL uHostSelDS; /* 0x00 */
77	RTSEL uHostSelES; /* 0x02 */
78	RTSEL uHostSelFS; /* 0x04 */
79	RTSEL uHostSelGS; /* 0x06 */
80	RTSEL uHostSelTR; /* 0x08 */
81	uint8_t abPadding0[4];
82	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
83	uint8_t abPadding1[6];
84	X86XDTR64 HostIdtr; /*< 0x1e - should be aligned by it's 64-bit member. /
85	uint64_t uHostFSBase; /* 0x28 */
86	uint64_t uHostGSBase; /* 0x30 */
87	} VMXRESTOREHOST;
88	/** Pointer to VMXRESTOREHOST. */
89	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
90	AssertCompileSize(X86XDTR64, 10);
91	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
92	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
93	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
94	AssertCompileSize(VMXRESTOREHOST, 56);
95
96	/** @name VMX VMCS-Read cache indices.
97	* @{
98	*/
99	#ifndef VBOX_WITH_OLD_VTX_CODE
100	# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
101	# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
102	# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
103	# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
104	# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
105	# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
106	# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
107	# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
108	# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
109	# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
110	# define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
111	# define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
112	# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
113	# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
114	# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
115	# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
116	# define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
117	# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
118	#else /* VBOX_WITH_OLD_VTX_CODE */
119	# define VMX_VMCS_GUEST_RIP_CACHE_IDX 0
120	# define VMX_VMCS_GUEST_RSP_CACHE_IDX 1
121	# define VMX_VMCS_GUEST_RFLAGS_CACHE_IDX 2
122	# define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE_CACHE_IDX 3
123	# define VMX_VMCS_CTRL_CR0_READ_SHADOW_CACHE_IDX 4
124	# define VMX_VMCS_GUEST_CR0_CACHE_IDX 5
125	# define VMX_VMCS_CTRL_CR4_READ_SHADOW_CACHE_IDX 6
126	# define VMX_VMCS_GUEST_CR4_CACHE_IDX 7
127	# define VMX_VMCS_GUEST_DR7_CACHE_IDX 8
128	# define VMX_VMCS32_GUEST_SYSENTER_CS_CACHE_IDX 9
129	# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 10
130	# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 11
131	# define VMX_VMCS32_GUEST_GDTR_LIMIT_CACHE_IDX 12
132	# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 13
133	# define VMX_VMCS32_GUEST_IDTR_LIMIT_CACHE_IDX 14
134	# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 15
135	# define VMX_VMCS16_GUEST_FIELD_CS_CACHE_IDX 16
136	# define VMX_VMCS32_GUEST_CS_LIMIT_CACHE_IDX 17
137	# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 18
138	# define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS_CACHE_IDX 19
139	# define VMX_VMCS16_GUEST_FIELD_DS_CACHE_IDX 20
140	# define VMX_VMCS32_GUEST_DS_LIMIT_CACHE_IDX 21
141	# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 22
142	# define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS_CACHE_IDX 23
143	# define VMX_VMCS16_GUEST_FIELD_ES_CACHE_IDX 24
144	# define VMX_VMCS32_GUEST_ES_LIMIT_CACHE_IDX 25
145	# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 26
146	# define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS_CACHE_IDX 27
147	# define VMX_VMCS16_GUEST_FIELD_FS_CACHE_IDX 28
148	# define VMX_VMCS32_GUEST_FS_LIMIT_CACHE_IDX 29
149	# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 30
150	# define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS_CACHE_IDX 31
151	# define VMX_VMCS16_GUEST_FIELD_GS_CACHE_IDX 32
152	# define VMX_VMCS32_GUEST_GS_LIMIT_CACHE_IDX 33
153	# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 34
154	# define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS_CACHE_IDX 35
155	# define VMX_VMCS16_GUEST_FIELD_SS_CACHE_IDX 36
156	# define VMX_VMCS32_GUEST_SS_LIMIT_CACHE_IDX 37
157	# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 38
158	# define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS_CACHE_IDX 39
159	# define VMX_VMCS16_GUEST_FIELD_TR_CACHE_IDX 40
160	# define VMX_VMCS32_GUEST_TR_LIMIT_CACHE_IDX 41
161	# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 42
162	# define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS_CACHE_IDX 43
163	# define VMX_VMCS16_GUEST_FIELD_LDTR_CACHE_IDX 44
164	# define VMX_VMCS32_GUEST_LDTR_LIMIT_CACHE_IDX 45
165	# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 46
166	# define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS_CACHE_IDX 47
167	# define VMX_VMCS32_RO_EXIT_REASON_CACHE_IDX 48
168	# define VMX_VMCS32_RO_VM_INSTR_ERROR_CACHE_IDX 49
169	# define VMX_VMCS32_RO_EXIT_INSTR_LENGTH_CACHE_IDX 50
170	# define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE_CACHE_IDX 51
171	# define VMX_VMCS32_RO_EXIT_INSTR_INFO_CACHE_IDX 52
172	# define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO_CACHE_IDX 53
173	# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 54
174	# define VMX_VMCS32_RO_IDT_INFO_CACHE_IDX 55
175	# define VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX 56
176	# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX + 1)
177	# define VMX_VMCS_GUEST_CR3_CACHE_IDX 57
178	# define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX 58
179	# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX + 1)
180	#endif /* VBOX_WITH_OLD_VTX_CODE */
181	/** @} */
182
183	/** @name VMX EPT paging structures
184	* @{
185	*/
186
187	/**
188	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
189	*/
190	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
191
192	/**
193	* EPT Page Directory Pointer Entry. Bit view.
194	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
195	* this did cause trouble with one compiler/version).
196	*/
197	#pragma pack(1)
198	typedef struct EPTPML4EBITS
199	{
200	/** Present bit. */
201	uint64_t u1Present : 1;
202	/** Writable bit. */
203	uint64_t u1Write : 1;
204	/** Executable bit. */
205	uint64_t u1Execute : 1;
206	/** Reserved (must be 0). */
207	uint64_t u5Reserved : 5;
208	/** Available for software. */
209	uint64_t u4Available : 4;
210	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
211	uint64_t u40PhysAddr : 40;
212	/** Availabe for software. */
213	uint64_t u12Available : 12;
214	} EPTPML4EBITS;
215	#pragma pack()
216	AssertCompileSize(EPTPML4EBITS, 8);
217
218	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
219	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
220	/** The page shift to get the PML4 index. */
221	#define EPT_PML4_SHIFT X86_PML4_SHIFT
222	/** The PML4 index mask (apply to a shifted page address). */
223	#define EPT_PML4_MASK X86_PML4_MASK
224
225	/**
226	* EPT PML4E.
227	*/
228	#pragma pack(1)
229	typedef union EPTPML4E
230	{
231	/** Normal view. */
232	EPTPML4EBITS n;
233	/** Unsigned integer view. */
234	X86PGPAEUINT u;
235	/** 64 bit unsigned integer view. */
236	uint64_t au64[1];
237	/** 32 bit unsigned integer view. */
238	uint32_t au32[2];
239	} EPTPML4E;
240	#pragma pack()
241	/** Pointer to a PML4 table entry. */
242	typedef EPTPML4E *PEPTPML4E;
243	/** Pointer to a const PML4 table entry. */
244	typedef const EPTPML4E *PCEPTPML4E;
245	AssertCompileSize(EPTPML4E, 8);
246
247	/**
248	* EPT PML4 Table.
249	*/
250	#pragma pack(1)
251	typedef struct EPTPML4
252	{
253	EPTPML4E a[EPT_PG_ENTRIES];
254	} EPTPML4;
255	#pragma pack()
256	/** Pointer to an EPT PML4 Table. */
257	typedef EPTPML4 *PEPTPML4;
258	/** Pointer to a const EPT PML4 Table. */
259	typedef const EPTPML4 *PCEPTPML4;
260
261	/**
262	* EPT Page Directory Pointer Entry. Bit view.
263	*/
264	#pragma pack(1)
265	typedef struct EPTPDPTEBITS
266	{
267	/** Present bit. */
268	uint64_t u1Present : 1;
269	/** Writable bit. */
270	uint64_t u1Write : 1;
271	/** Executable bit. */
272	uint64_t u1Execute : 1;
273	/** Reserved (must be 0). */
274	uint64_t u5Reserved : 5;
275	/** Available for software. */
276	uint64_t u4Available : 4;
277	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
278	uint64_t u40PhysAddr : 40;
279	/** Availabe for software. */
280	uint64_t u12Available : 12;
281	} EPTPDPTEBITS;
282	#pragma pack()
283	AssertCompileSize(EPTPDPTEBITS, 8);
284
285	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
286	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
287	/** The page shift to get the PDPT index. */
288	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
289	/** The PDPT index mask (apply to a shifted page address). */
290	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
291
292	/**
293	* EPT Page Directory Pointer.
294	*/
295	#pragma pack(1)
296	typedef union EPTPDPTE
297	{
298	/** Normal view. */
299	EPTPDPTEBITS n;
300	/** Unsigned integer view. */
301	X86PGPAEUINT u;
302	/** 64 bit unsigned integer view. */
303	uint64_t au64[1];
304	/** 32 bit unsigned integer view. */
305	uint32_t au32[2];
306	} EPTPDPTE;
307	#pragma pack()
308	/** Pointer to an EPT Page Directory Pointer Entry. */
309	typedef EPTPDPTE *PEPTPDPTE;
310	/** Pointer to a const EPT Page Directory Pointer Entry. */
311	typedef const EPTPDPTE *PCEPTPDPTE;
312	AssertCompileSize(EPTPDPTE, 8);
313
314	/**
315	* EPT Page Directory Pointer Table.
316	*/
317	#pragma pack(1)
318	typedef struct EPTPDPT
319	{
320	EPTPDPTE a[EPT_PG_ENTRIES];
321	} EPTPDPT;
322	#pragma pack()
323	/** Pointer to an EPT Page Directory Pointer Table. */
324	typedef EPTPDPT *PEPTPDPT;
325	/** Pointer to a const EPT Page Directory Pointer Table. */
326	typedef const EPTPDPT *PCEPTPDPT;
327
328
329	/**
330	* EPT Page Directory Table Entry. Bit view.
331	*/
332	#pragma pack(1)
333	typedef struct EPTPDEBITS
334	{
335	/** Present bit. */
336	uint64_t u1Present : 1;
337	/** Writable bit. */
338	uint64_t u1Write : 1;
339	/** Executable bit. */
340	uint64_t u1Execute : 1;
341	/** Reserved (must be 0). */
342	uint64_t u4Reserved : 4;
343	/** Big page (must be 0 here). */
344	uint64_t u1Size : 1;
345	/** Available for software. */
346	uint64_t u4Available : 4;
347	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
348	uint64_t u40PhysAddr : 40;
349	/** Availabe for software. */
350	uint64_t u12Available : 12;
351	} EPTPDEBITS;
352	#pragma pack()
353	AssertCompileSize(EPTPDEBITS, 8);
354
355	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
356	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
357	/** The page shift to get the PD index. */
358	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
359	/** The PD index mask (apply to a shifted page address). */
360	#define EPT_PD_MASK X86_PD_PAE_MASK
361
362	/**
363	* EPT 2MB Page Directory Table Entry. Bit view.
364	*/
365	#pragma pack(1)
366	typedef struct EPTPDE2MBITS
367	{
368	/** Present bit. */
369	uint64_t u1Present : 1;
370	/** Writable bit. */
371	uint64_t u1Write : 1;
372	/** Executable bit. */
373	uint64_t u1Execute : 1;
374	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
375	uint64_t u3EMT : 3;
376	/** Ignore PAT memory type */
377	uint64_t u1IgnorePAT : 1;
378	/** Big page (must be 1 here). */
379	uint64_t u1Size : 1;
380	/** Available for software. */
381	uint64_t u4Available : 4;
382	/** Reserved (must be 0). */
383	uint64_t u9Reserved : 9;
384	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
385	uint64_t u31PhysAddr : 31;
386	/** Availabe for software. */
387	uint64_t u12Available : 12;
388	} EPTPDE2MBITS;
389	#pragma pack()
390	AssertCompileSize(EPTPDE2MBITS, 8);
391
392	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
393	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
394
395	/**
396	* EPT Page Directory Table Entry.
397	*/
398	#pragma pack(1)
399	typedef union EPTPDE
400	{
401	/** Normal view. */
402	EPTPDEBITS n;
403	/** 2MB view (big). */
404	EPTPDE2MBITS b;
405	/** Unsigned integer view. */
406	X86PGPAEUINT u;
407	/** 64 bit unsigned integer view. */
408	uint64_t au64[1];
409	/** 32 bit unsigned integer view. */
410	uint32_t au32[2];
411	} EPTPDE;
412	#pragma pack()
413	/** Pointer to an EPT Page Directory Table Entry. */
414	typedef EPTPDE *PEPTPDE;
415	/** Pointer to a const EPT Page Directory Table Entry. */
416	typedef const EPTPDE *PCEPTPDE;
417	AssertCompileSize(EPTPDE, 8);
418
419	/**
420	* EPT Page Directory Table.
421	*/
422	#pragma pack(1)
423	typedef struct EPTPD
424	{
425	EPTPDE a[EPT_PG_ENTRIES];
426	} EPTPD;
427	#pragma pack()
428	/** Pointer to an EPT Page Directory Table. */
429	typedef EPTPD *PEPTPD;
430	/** Pointer to a const EPT Page Directory Table. */
431	typedef const EPTPD *PCEPTPD;
432
433
434	/**
435	* EPT Page Table Entry. Bit view.
436	*/
437	#pragma pack(1)
438	typedef struct EPTPTEBITS
439	{
440	/** 0 - Present bit.
441	* @remark This is a convenience "misnomer". The bit actually indicates
442	* read access and the CPU will consider an entry with any of the
443	* first three bits set as present. Since all our valid entries
444	* will have this bit set, it can be used as a present indicator
445	* and allow some code sharing. */
446	uint64_t u1Present : 1;
447	/** 1 - Writable bit. */
448	uint64_t u1Write : 1;
449	/** 2 - Executable bit. */
450	uint64_t u1Execute : 1;
451	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
452	uint64_t u3EMT : 3;
453	/** 6 - Ignore PAT memory type */
454	uint64_t u1IgnorePAT : 1;
455	/** 11:7 - Available for software. */
456	uint64_t u5Available : 5;
457	/** 51:12 - Physical address of page. Restricted by maximum physical
458	* address width of the cpu. */
459	uint64_t u40PhysAddr : 40;
460	/** 63:52 - Available for software. */
461	uint64_t u12Available : 12;
462	} EPTPTEBITS;
463	#pragma pack()
464	AssertCompileSize(EPTPTEBITS, 8);
465
466	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
467	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
468	/** The page shift to get the EPT PTE index. */
469	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
470	/** The EPT PT index mask (apply to a shifted page address). */
471	#define EPT_PT_MASK X86_PT_PAE_MASK
472
473	/**
474	* EPT Page Table Entry.
475	*/
476	#pragma pack(1)
477	typedef union EPTPTE
478	{
479	/** Normal view. */
480	EPTPTEBITS n;
481	/** Unsigned integer view. */
482	X86PGPAEUINT u;
483	/** 64 bit unsigned integer view. */
484	uint64_t au64[1];
485	/** 32 bit unsigned integer view. */
486	uint32_t au32[2];
487	} EPTPTE;
488	#pragma pack()
489	/** Pointer to an EPT Page Directory Table Entry. */
490	typedef EPTPTE *PEPTPTE;
491	/** Pointer to a const EPT Page Directory Table Entry. */
492	typedef const EPTPTE *PCEPTPTE;
493	AssertCompileSize(EPTPTE, 8);
494
495	/**
496	* EPT Page Table.
497	*/
498	#pragma pack(1)
499	typedef struct EPTPT
500	{
501	EPTPTE a[EPT_PG_ENTRIES];
502	} EPTPT;
503	#pragma pack()
504	/** Pointer to an extended page table. */
505	typedef EPTPT *PEPTPT;
506	/** Pointer to a const extended table. */
507	typedef const EPTPT *PCEPTPT;
508
509	/**
510	* VPID flush types.
511	*/
512	typedef enum
513	{
514	/** Invalidate a specific page. */
515	VMX_FLUSH_VPID_INDIV_ADDR = 0,
516	/** Invalidate one context (specific VPID). */
517	VMX_FLUSH_VPID_SINGLE_CONTEXT = 1,
518	/** Invalidate all contexts (all VPIDs). */
519	VMX_FLUSH_VPID_ALL_CONTEXTS = 2,
520	/** Invalidate a single VPID context retaining global mappings. */
521	VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
522	/** Unsupported by VirtualBox. */
523	VMX_FLUSH_VPID_NOT_SUPPORTED = 0xbad,
524	/** Unsupported by CPU. */
525	VMX_FLUSH_VPID_NONE = 0xb00,
526	/** 32bit hackishness. */
527	VMX_FLUSH_VPID_32BIT_HACK = 0x7fffffff
528	} VMX_FLUSH_VPID;
529
530	/**
531	* EPT flush types.
532	*/
533	typedef enum
534	{
535	/** Invalidate one context (specific EPT). */
536	VMX_FLUSH_EPT_SINGLE_CONTEXT = 1,
537	/* Invalidate all contexts (all EPTs) */
538	VMX_FLUSH_EPT_ALL_CONTEXTS = 2,
539	/** Unsupported by VirtualBox. */
540	VMX_FLUSH_EPT_NOT_SUPPORTED = 0xbad,
541	/** Unsupported by CPU. */
542	VMX_FLUSH_EPT_NONE = 0xb00,
543	/** 32bit hackishness. */
544	VMX_FLUSH_EPT_32BIT_HACK = 0x7fffffff
545	} VMX_FLUSH_EPT;
546	/** @} */
547
548	/** @name MSR autoload/store elements
549	* @{
550	*/
551	#pragma pack(1)
552	typedef struct
553	{
554	uint32_t u32IndexMSR;
555	uint32_t u32Reserved;
556	uint64_t u64Value;
557	} VMXMSR;
558	#pragma pack()
559	/** Pointer to an MSR load/store element. */
560	typedef VMXMSR *PVMXMSR;
561	/** Pointer to a const MSR load/store element. */
562	typedef const VMXMSR *PCVMXMSR;
563
564	/** @} */
565
566
567	/** @name VMX-capability qword
568	* @{
569	*/
570	#pragma pack(1)
571	typedef union
572	{
573	struct
574	{
575	/** Bits set here -must- be set in the correpsonding VM-execution controls. */
576	uint32_t disallowed0;
577	/** Bits cleared here -must- be cleared in the corresponding VM-execution
578	* controls. */
579	uint32_t allowed1;
580	} n;
581	uint64_t u;
582	} VMX_CAPABILITY;
583	#pragma pack()
584	/** @} */
585
586	/** @name VMX EFLAGS reserved bits.
587	* @{
588	*/
589	/** And-mask for setting reserved bits to zero */
590	#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
591	/** Or-mask for setting reserved bits to 1 */
592	#define VMX_EFLAGS_RESERVED_1 0x00000002
593	/** @} */
594
595	/** @name VMX Basic Exit Reasons.
596	* @{
597	*/
598	/** -1 Invalid exit code */
599	#define VMX_EXIT_INVALID -1
600	/** 0 Exception or non-maskable interrupt (NMI). */
601	#define VMX_EXIT_XCPT_OR_NMI 0
602	/** 1 External interrupt. */
603	#define VMX_EXIT_EXT_INT 1
604	/** 2 Triple fault. */
605	#define VMX_EXIT_TRIPLE_FAULT 2
606	/** 3 INIT signal. */
607	#define VMX_EXIT_INIT_SIGNAL 3
608	/** 4 Start-up IPI (SIPI). */
609	#define VMX_EXIT_SIPI 4
610	/** 5 I/O system-management interrupt (SMI). */
611	#define VMX_EXIT_IO_SMI 5
612	/** 6 Other SMI. */
613	#define VMX_EXIT_SMI 6
614	/** 7 Interrupt window exiting. */
615	#define VMX_EXIT_INT_WINDOW 7
616	/** 8 NMI window exiting. */
617	#define VMX_EXIT_NMI_WINDOW 8
618	/** 9 Task switch. */
619	#define VMX_EXIT_TASK_SWITCH 9
620	/** 10 Guest software attempted to execute CPUID. */
621	#define VMX_EXIT_CPUID 10
622	/** 10 Guest software attempted to execute GETSEC. */
623	#define VMX_EXIT_GETSEC 11
624	/** 12 Guest software attempted to execute HLT. */
625	#define VMX_EXIT_HLT 12
626	/** 13 Guest software attempted to execute INVD. */
627	#define VMX_EXIT_INVD 13
628	/** 14 Guest software attempted to execute INVLPG. */
629	#define VMX_EXIT_INVLPG 14
630	/** 15 Guest software attempted to execute RDPMC. */
631	#define VMX_EXIT_RDPMC 15
632	/** 16 Guest software attempted to execute RDTSC. */
633	#define VMX_EXIT_RDTSC 16
634	/** 17 Guest software attempted to execute RSM in SMM. */
635	#define VMX_EXIT_RSM 17
636	/** 18 Guest software executed VMCALL. */
637	#define VMX_EXIT_VMCALL 18
638	/** 19 Guest software executed VMCLEAR. */
639	#define VMX_EXIT_VMCLEAR 19
640	/** 20 Guest software executed VMLAUNCH. */
641	#define VMX_EXIT_VMLAUNCH 20
642	/** 21 Guest software executed VMPTRLD. */
643	#define VMX_EXIT_VMPTRLD 21
644	/** 22 Guest software executed VMPTRST. */
645	#define VMX_EXIT_VMPTRST 22
646	/** 23 Guest software executed VMREAD. */
647	#define VMX_EXIT_VMREAD 23
648	/** 24 Guest software executed VMRESUME. */
649	#define VMX_EXIT_VMRESUME 24
650	/** 25 Guest software executed VMWRITE. */
651	#define VMX_EXIT_VMWRITE 25
652	/** 26 Guest software executed VMXOFF. */
653	#define VMX_EXIT_VMXOFF 26
654	/** 27 Guest software executed VMXON. */
655	#define VMX_EXIT_VMXON 27
656	/** 28 Control-register accesses. */
657	#define VMX_EXIT_MOV_CRX 28
658	/** 29 Debug-register accesses. */
659	#define VMX_EXIT_MOV_DRX 29
660	/** 30 I/O instruction. */
661	#define VMX_EXIT_IO_INSTR 30
662	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
663	#define VMX_EXIT_RDMSR 31
664	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
665	#define VMX_EXIT_WRMSR 32
666	/** 33 VM-entry failure due to invalid guest state. */
667	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
668	/** 34 VM-entry failure due to MSR loading. */
669	#define VMX_EXIT_ERR_MSR_LOAD 34
670	/** 36 Guest software executed MWAIT. */
671	#define VMX_EXIT_MWAIT 36
672	/** 37 VM exit due to monitor trap flag. */
673	#define VMX_EXIT_MTF 37
674	/** 39 Guest software attempted to execute MONITOR. */
675	#define VMX_EXIT_MONITOR 39
676	/** 40 Guest software attempted to execute PAUSE. */
677	#define VMX_EXIT_PAUSE 40
678	/** 41 VM-entry failure due to machine-check. */
679	#define VMX_EXIT_ERR_MACHINE_CHECK 41
680	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
681	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
682	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
683	#define VMX_EXIT_APIC_ACCESS 44
684	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
685	#define VMX_EXIT_XDTR_ACCESS 46
686	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
687	#define VMX_EXIT_TR_ACCESS 47
688	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
689	#define VMX_EXIT_EPT_VIOLATION 48
690	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
691	#define VMX_EXIT_EPT_MISCONFIG 49
692	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
693	#define VMX_EXIT_INVEPT 50
694	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
695	#define VMX_EXIT_RDTSCP 51
696	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
697	#define VMX_EXIT_PREEMPT_TIMER 52
698	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
699	#define VMX_EXIT_INVVPID 53
700	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
701	#define VMX_EXIT_WBINVD 54
702	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
703	#define VMX_EXIT_XSETBV 55
704	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
705	#define VMX_EXIT_RDRAND 57
706	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
707	#define VMX_EXIT_INVPCID 58
708	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
709	#define VMX_EXIT_VMFUNC 59
710	/** The maximum exit value (inclusive). */
711	#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
712	/** @} */
713
714
715	/** @name VM Instruction Errors
716	* @{
717	*/
718	/** VMCALL executed in VMX root operation. */
719	#define VMX_ERROR_VMCALL 1
720	/** VMCLEAR with invalid physical address. */
721	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
722	/** VMCLEAR with VMXON pointer. */
723	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
724	/** VMLAUNCH with non-clear VMCS. */
725	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
726	/** VMRESUME with non-launched VMCS. */
727	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
728	/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
729	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
730	/** VM-entry with invalid control field(s). */
731	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
732	/** VM-entry with invalid host-state field(s). */
733	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
734	/** VMPTRLD with invalid physical address. */
735	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
736	/** VMPTRLD with VMXON pointer. */
737	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
738	/** VMPTRLD with incorrect VMCS revision identifier. */
739	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
740	/** VMREAD/VMWRITE from/to unsupported VMCS component. */
741	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
742	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
743	/** VMWRITE to read-only VMCS component. */
744	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
745	/** VMXON executed in VMX root operation. */
746	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
747	/** VM entry with invalid executive-VMCS pointer. */
748	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
749	/** VM entry with non-launched executive VMCS. */
750	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
751	/** VM entry with executive-VMCS pointer not VMXON pointer. */
752	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
753	/** VMCALL with non-clear VMCS. */
754	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
755	/** VMCALL with invalid VM-exit control fields. */
756	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
757	/** VMCALL with incorrect MSEG revision identifier. */
758	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
759	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
760	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
761	/** VMCALL with invalid SMM-monitor features. */
762	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
763	/** VM entry with invalid VM-execution control fields in executive VMCS. */
764	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
765	/** VM entry with events blocked by MOV SS. */
766	#define VMX_ERROR_VMENTRY_MOV_SS 26
767	/** Invalid operand to INVEPT/INVVPID. */
768	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
769
770	/** @} */
771
772
773	/** @name VMX MSRs - Basic VMX information.
774	* @{
775	*/
776	/** VMCS revision identifier used by the processor. */
777	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
778	/** Size of the VMCS. */
779	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0xFFF)
780	/** Width of physical address used for the VMCS.
781	* 0 -> limited to the available amount of physical ram
782	* 1 -> within the first 4 GB
783	*/
784	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
785	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
786	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
787	/** Memory type that must be used for the VMCS. */
788	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
789	/** Whether the processor provides additional information for exits due to INS/OUTS. */
790	#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
791	/** @} */
792
793
794	/** @name VMX MSRs - Misc VMX info.
795	* @{
796	*/
797	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
798	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
799	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
800	#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
801	/** Activity states supported by the implementation. */
802	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
803	/** Number of CR3 target values supported by the processor. (0-256) */
804	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
805	/** Maximum nr of MSRs in the VMCS. (N+1)512. /
806	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
807	/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
808	#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
809	/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
810	#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
811	/** Whether VMWRITE can be used to write VM-exit information fields. */
812	#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
813	/** MSEG revision identifier used by the processor. */
814	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
815	/** @} */
816
817
818	/** @name VMX MSRs - VMCS enumeration field info
819	* @{
820	*/
821	/** Highest field index. */
822	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
823	/** @} */
824
825
826	/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
827	* @{
828	*/
829	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
830	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
831	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
832	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
833	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
834	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
835	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
836	#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
837	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
838	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
839	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
840	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
841	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
842	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
843	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
844	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
845	#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
846	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
847	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
848	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
849	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
850	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
851	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
852	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
853	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
854
855	/** @} */
856
857	/** @name Extended Page Table Pointer (EPTP)
858	* @{
859	*/
860	/** Uncachable EPT paging structure memory type. */
861	#define VMX_EPT_MEMTYPE_UC 0
862	/** Write-back EPT paging structure memory type. */
863	#define VMX_EPT_MEMTYPE_WB 6
864	/** Shift value to get the EPT page walk length (bits 5-3) */
865	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
866	/** Mask value to get the EPT page walk length (bits 5-3) */
867	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
868	/** Default EPT page-walk length (1 less than the actual EPT page-walk
869	* length) */
870	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
871	/** @} */
872
873
874	/** @name VMCS field encoding - 16 bits guest fields
875	* @{
876	*/
877	#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
878	#define VMX_VMCS16_GUEST_FIELD_ES 0x800
879	#define VMX_VMCS16_GUEST_FIELD_CS 0x802
880	#define VMX_VMCS16_GUEST_FIELD_SS 0x804
881	#define VMX_VMCS16_GUEST_FIELD_DS 0x806
882	#define VMX_VMCS16_GUEST_FIELD_FS 0x808
883	#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
884	#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
885	#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
886	/** @} */
887
888	/** @name VMCS field encoding - 16 bits host fields
889	* @{
890	*/
891	#define VMX_VMCS16_HOST_FIELD_ES 0xC00
892	#define VMX_VMCS16_HOST_FIELD_CS 0xC02
893	#define VMX_VMCS16_HOST_FIELD_SS 0xC04
894	#define VMX_VMCS16_HOST_FIELD_DS 0xC06
895	#define VMX_VMCS16_HOST_FIELD_FS 0xC08
896	#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
897	#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
898	/** @} */
899
900	/** @name VMCS field encoding - 64 bits host fields
901	* @{
902	*/
903	#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
904	#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
905	#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
906	#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
907	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
908	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
909	/** @} */
910
911
912	/** @name VMCS field encoding - 64 Bits control fields
913	* @{
914	*/
915	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
916	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
917	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
918	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
919
920	/* Optional */
921	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
922	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
923
924	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
925	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
926	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
927	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
928
929	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
930	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
931
932	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
933	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
934
935	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
936	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
937
938	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
939	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
940	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
941
942	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
943	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
944	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
945
946	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
947	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
948	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
949
950	/** Extended page table pointer. */
951	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
952	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
953
954	/** Extended page table pointer lists. */
955	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
956	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
957
958	/** VM-exit guest phyiscal address. */
959	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
960	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
961	/** @} */
962
963
964	/** @name VMCS field encoding - 64 Bits guest fields
965	* @{
966	*/
967	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
968	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
969	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
970	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
971	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
972	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
973	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
974	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
975	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
976	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
977	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
978	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
979	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
980	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
981	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
982	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
983	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
984	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
985	/** @} */
986
987
988	/** @name VMCS field encoding - 32 Bits control fields
989	* @{
990	*/
991	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
992	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
993	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
994	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
995	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
996	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
997	#define VMX_VMCS32_CTRL_EXIT 0x400C
998	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
999	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1000	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1001	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1002	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1003	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1004	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1005	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1006	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1007	/** @} */
1008
1009
1010	/** @name VMX_VMCS_CTRL_PIN_EXEC
1011	* @{
1012	*/
1013	/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1014	#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1015	/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1016	#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1017	/** Virtual NMIs. */
1018	#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1019	/** Activate VMX preemption timer. */
1020	#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1021	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1022	/** @} */
1023
1024	/** @name VMX_VMCS_CTRL_PROC_EXEC
1025	* @{
1026	*/
1027	/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
1028	#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1029	/** Use timestamp counter offset. */
1030	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1031	/** VM Exit when executing the HLT instruction. */
1032	#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1033	/** VM Exit when executing the INVLPG instruction. */
1034	#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1035	/** VM Exit when executing the MWAIT instruction. */
1036	#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1037	/** VM Exit when executing the RDPMC instruction. */
1038	#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1039	/** VM Exit when executing the RDTSC/RDTSCP instruction. */
1040	#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1041	/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1042	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1043	/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1044	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1045	/** VM Exit on CR8 loads. */
1046	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1047	/** VM Exit on CR8 stores. */
1048	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1049	/** Use TPR shadow. */
1050	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1051	/** VM Exit when virtual nmi blocking is disabled. */
1052	#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1053	/** VM Exit when executing a MOV DRx instruction. */
1054	#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1055	/** VM Exit when executing IO instructions. */
1056	#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1057	/** Use IO bitmaps. */
1058	#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1059	/** Monitor trap flag. */
1060	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1061	/** Use MSR bitmaps. */
1062	#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1063	/** VM Exit when executing the MONITOR instruction. */
1064	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1065	/** VM Exit when executing the PAUSE instruction. */
1066	#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1067	/** Determines whether the secondary processor based VM-execution controls are used. */
1068	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1069	/** @} */
1070
1071	/** @name VMX_VMCS_CTRL_PROC_EXEC2
1072	* @{
1073	*/
1074	/** Virtualize APIC access. */
1075	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1076	/** EPT supported/enabled. */
1077	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1078	/** Descriptor table instructions cause VM-exits. */
1079	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1080	/** RDTSCP supported/enabled. */
1081	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1082	/** Virtualize x2APIC mode. */
1083	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1084	/** VPID supported/enabled. */
1085	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1086	/** VM Exit when executing the WBINVD instruction. */
1087	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1088	/** Unrestricted guest execution. */
1089	#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1090	/** A specified nr of pause loops cause a VM-exit. */
1091	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1092	/** VM Exit when executing RDRAND instructions. */
1093	#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1094	/** Enables INVPCID instructions. */
1095	#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1096	/** Enables VMFUNC instructions. */
1097	#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1098	/** @} */
1099
1100
1101	/** @name VMX_VMCS_CTRL_ENTRY
1102	* @{
1103	*/
1104	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1105	#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1106	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1107	#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1108	/** In SMM mode after VM-entry. */
1109	#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1110	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1111	#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1112	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
1113	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1114	/** Whether the guest IA32_PAT MSR is loaded on VM entry. */
1115	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1116	/** Whether the guest IA32_EFER MSR is loaded on VM entry. */
1117	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1118	/** @} */
1119
1120
1121	/** @name VMX_VMCS_CTRL_EXIT
1122	* @{
1123	*/
1124	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1125	#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1126	/** Return to long mode after a VM-exit. */
1127	#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1128	/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
1129	#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1130	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1131	#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1132	/** Whether the guest IA32_PAT MSR is saved on VM exit. */
1133	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1134	/** Whether the host IA32_PAT MSR is loaded on VM exit. */
1135	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1136	/** Whether the guest IA32_EFER MSR is saved on VM exit. */
1137	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1138	/** Whether the host IA32_EFER MSR is loaded on VM exit. */
1139	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1140	/** Whether the value of the VMX preemption timer is saved on every VM exit. */
1141	#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1142	/** @} */
1143
1144
1145	/** @name VMX_VMCS_CTRL_VMFUNC
1146	* @{
1147	*/
1148	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1149	#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1150	/** @} */
1151
1152
1153	/** @name VMCS field encoding - 32 Bits read-only fields
1154	* @{
1155	*/
1156	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1157	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1158	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1159	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1160	#define VMX_VMCS32_RO_IDT_INFO 0x4408
1161	#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1162	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1163	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1164	/** @} */
1165
1166	/** @name VMX_VMCS32_RO_EXIT_REASON
1167	* @{
1168	*/
1169	#define VMX_EXIT_REASON_BASIC(a) (a & 0xffff)
1170	/** @} */
1171
1172	/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1173	* @{
1174	*/
1175	#define VMX_ENTRY_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
1176	/** @} */
1177
1178
1179	/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1180	* @{
1181	*/
1182	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
1183	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1184	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1185	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1186	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1187	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
1188	#ifdef VBOX_WITH_OLD_VTX_CODE
1189	# define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
1190	#endif
1191	#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1192	#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) (a & RT_BIT(31))
1193	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1194	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
1195	/** @} */
1196
1197	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1198	* @{
1199	*/
1200	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1201	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1202	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1203	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4 /*< int xx /
1204	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DB_XCPT 5 /*< Why are we getting this one?? /
1205	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1206	/** @} */
1207
1208	/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1209	* @{
1210	*/
1211	#define VMX_IDT_VECTORING_INFO_VECTOR(a) (a & 0xff)
1212	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1213	#define VMX_IDT_VECTORING_INFO_TYPE(a) ((a >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1214	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1215	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1216	#define VMX_IDT_VECTORING_INFO_VALID(a) (a & RT_BIT(31))
1217	#define VMX_ENTRY_INTR_INFO_FROM_EXIT_IDT_INFO(a) (a & ~RT_BIT(12))
1218	/** @} */
1219
1220	/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1221	* @{
1222	*/
1223	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1224	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1225	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1226	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1227	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1228	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1229	/** @} */
1230
1231
1232	/** @name VMCS field encoding - 32 Bits guest state fields
1233	* @{
1234	*/
1235	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1236	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1237	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1238	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1239	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1240	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1241	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1242	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1243	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1244	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1245	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1246	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1247	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1248	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1249	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1250	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1251	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1252	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1253	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1254	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1255	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
1256	#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1257	/** @} */
1258
1259
1260	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1261	* @{
1262	*/
1263	/** The logical processor is active. */
1264	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1265	/** The logical processor is inactive, because executed a HLT instruction. */
1266	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1267	/** The logical processor is inactive, because of a triple fault or other serious error. */
1268	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1269	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1270	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1271	/** @} */
1272
1273
1274	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1275	* @{
1276	*/
1277	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1278	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1279	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1280	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1281	/** @} */
1282
1283
1284	/** @name VMCS field encoding - 32 Bits host state fields
1285	* @{
1286	*/
1287	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1288	/** @} */
1289
1290	/** @name Natural width control fields
1291	* @{
1292	*/
1293	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1294	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1295	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1296	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1297	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1298	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1299	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1300	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1301	/** @} */
1302
1303
1304	/** @name Natural width read-only data fields
1305	* @{
1306	*/
1307	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1308	#define VMX_VMCS_RO_IO_RCX 0x6402
1309	#define VMX_VMCS_RO_IO_RSX 0x6404
1310	#define VMX_VMCS_RO_IO_RDI 0x6406
1311	#define VMX_VMCS_RO_IO_RIP 0x6408
1312	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1313	/** @} */
1314
1315
1316	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1317	* @{
1318	*/
1319	/** 0-2: Debug register number */
1320	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1321	/** 3: Reserved; cleared to 0. */
1322	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1323	/** 4: Direction of move (0 = write, 1 = read) */
1324	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1325	/** 5-7: Reserved; cleared to 0. */
1326	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1327	/** 8-11: General purpose register number. */
1328	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1329	/** Rest: reserved. */
1330	/** @} */
1331
1332	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1333	* @{
1334	*/
1335	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1336	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1337	/** @} */
1338
1339
1340
1341	/** @name CRx accesses
1342	* @{
1343	*/
1344	/** 0-3: Control register number (0 for CLTS & LMSW) */
1345	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1346	/** 4-5: Access type. */
1347	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1348	/** 6: LMSW operand type */
1349	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1350	/** 7: Reserved; cleared to 0. */
1351	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1352	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1353	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1354	/** 12-15: Reserved; cleared to 0. */
1355	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1356	/** 16-31: LMSW source data (else 0). */
1357	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1358	/** Rest: reserved. */
1359	/** @} */
1360
1361	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1362	* @{
1363	*/
1364	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1365	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1366	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1367	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1368	/** @} */
1369
1370	/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1371	* @{
1372	*/
1373	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1374	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1375	/** Task switch caused by a call instruction. */
1376	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1377	/** Task switch caused by an iret instruction. */
1378	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1379	/** Task switch caused by a jmp instruction. */
1380	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1381	/** Task switch caused by an interrupt gate. */
1382	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1383	/** @} */
1384
1385
1386	/** @name VMX_EXIT_EPT_VIOLATION
1387	* @{
1388	*/
1389	/** Set if the violation was caused by a data read. */
1390	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1391	/** Set if the violation was caused by a data write. */
1392	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1393	/** Set if the violation was caused by an insruction fetch. */
1394	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1395	/** AND of the present bit of all EPT structures. */
1396	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1397	/** AND of the write bit of all EPT structures. */
1398	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1399	/** AND of the execute bit of all EPT structures. */
1400	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1401	/** Set if the guest linear address field contains the faulting address. */
1402	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1403	/** If bit 7 is one: (reserved otherwise)
1404	* 1 - violation due to physical address access.
1405	* 0 - violation caused by page walk or access/dirty bit updates
1406	*/
1407	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1408	/** @} */
1409
1410
1411	/** @name VMX_EXIT_PORT_IO
1412	* @{
1413	*/
1414	/** 0-2: IO operation width. */
1415	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1416	/** 3: IO operation direction. */
1417	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1418	/** 4: String IO operation (INS / OUTS). */
1419	#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1420	/** 5: Repeated IO operation. */
1421	#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1422	/** 6: Operand encoding. */
1423	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1424	/** 16-31: IO Port (0-0xffff). */
1425	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1426	/* Rest reserved. */
1427	/** @} */
1428
1429	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1430	* @{
1431	*/
1432	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1433	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1434	/** @} */
1435
1436
1437	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1438	* @{
1439	*/
1440	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1441	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1442	/** @} */
1443
1444	/** @name VMX_EXIT_APIC_ACCESS
1445	* @{
1446	*/
1447	/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1448	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1449	/** 12-15: Access type. */
1450	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000)
1451	/* Rest reserved. */
1452	/** @} */
1453
1454
1455	/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1456	* @{
1457	*/
1458	/** Linear read access. */
1459	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1460	/** Linear write access. */
1461	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1462	/** Linear instruction fetch access. */
1463	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1464	/** Linear read/write access during event delivery. */
1465	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1466	/** Physical read/write access during event delivery. */
1467	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1468	/** Physical access for an instruction fetch or during instruction execution. */
1469	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1470	/** @} */
1471
1472	/** @} */
1473
1474	/** @name VMCS field encoding - Natural width guest state fields
1475	* @{
1476	*/
1477	#define VMX_VMCS_GUEST_CR0 0x6800
1478	#define VMX_VMCS_GUEST_CR3 0x6802
1479	#define VMX_VMCS_GUEST_CR4 0x6804
1480	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1481	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1482	#define VMX_VMCS_GUEST_SS_BASE 0x680A
1483	#define VMX_VMCS_GUEST_DS_BASE 0x680C
1484	#define VMX_VMCS_GUEST_FS_BASE 0x680E
1485	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1486	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1487	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1488	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1489	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1490	#define VMX_VMCS_GUEST_DR7 0x681A
1491	#define VMX_VMCS_GUEST_RSP 0x681C
1492	#define VMX_VMCS_GUEST_RIP 0x681E
1493	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1494	#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1495	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1496	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1497	/** @} */
1498
1499
1500	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1501	* @{
1502	*/
1503	/** Hardware breakpoint 0 was met. */
1504	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1505	/** Hardware breakpoint 1 was met. */
1506	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1507	/** Hardware breakpoint 2 was met. */
1508	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1509	/** Hardware breakpoint 3 was met. */
1510	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1511	/** At least one data or IO breakpoint was hit. */
1512	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1513	/** A debug exception would have been triggered by single-step execution mode. */
1514	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1515	/** Bits 4-11, 13 and 15-63 are reserved. */
1516
1517	/** @} */
1518
1519	/** @name VMCS field encoding - Natural width host state fields
1520	* @{
1521	*/
1522	#define VMX_VMCS_HOST_CR0 0x6C00
1523	#define VMX_VMCS_HOST_CR3 0x6C02
1524	#define VMX_VMCS_HOST_CR4 0x6C04
1525	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1526	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1527	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1528	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1529	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1530	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1531	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1532	#define VMX_VMCS_HOST_RSP 0x6C14
1533	#define VMX_VMCS_HOST_RIP 0x6C16
1534	/** @} */
1535
1536	/** @} */
1537
1538
1539	/** @defgroup grp_vmx_asm vmx assembly helpers
1540	* @ingroup grp_vmx
1541	* @{
1542	*/
1543
1544	/**
1545	* Restores some host-state fields that need not be done on every VM-exit.
1546	*
1547	* @returns VBox status code.
1548	* @param fRestoreHostFlags Flags of which host registers needs to be
1549	* restored.
1550	* @param pRestoreHost Pointer to the host-restore structure.
1551	*/
1552	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1553
1554
1555	/**
1556	* Dispatches an NMI to the host.
1557	*/
1558	DECLASM(int) VMXDispatchHostNmi(void);
1559
1560
1561	/**
1562	* Executes VMXON
1563	*
1564	* @returns VBox status code
1565	* @param pVMXOn Physical address of VMXON structure
1566	*/
1567	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1568	DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1569	#else
1570	DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1571	{
1572	# if RT_INLINE_ASM_GNU_STYLE
1573	int rc = VINF_SUCCESS;
1574	__asm__ __volatile__ (
1575	"push %3 \n\t"
1576	"push %2 \n\t"
1577	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1578	"ja 2f \n\t"
1579	"je 1f \n\t"
1580	"movl $"RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1581	"jmp 2f \n\t"
1582	"1: \n\t"
1583	"movl $"RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1584	"2: \n\t"
1585	"add $8, %%esp \n\t"
1586	:"=rm"(rc)
1587	:"0"(VINF_SUCCESS),
1588	"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1589	"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1590	:"memory"
1591	);
1592	return rc;
1593
1594	# elif VMX_USE_MSC_INTRINSICS
1595	unsigned char rcMsc = __vmx_on(&pVMXOn);
1596	if (RT_LIKELY(rcMsc == 0))
1597	return VINF_SUCCESS;
1598	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
1599
1600	# else
1601	int rc = VINF_SUCCESS;
1602	__asm
1603	{
1604	push dword ptr [pVMXOn+4]
1605	push dword ptr [pVMXOn]
1606	_emit 0xF3
1607	_emit 0x0F
1608	_emit 0xC7
1609	_emit 0x34
1610	_emit 0x24 /* VMXON [esp] */
1611	jnc vmxon_good
1612	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1613	jmp the_end
1614
1615	vmxon_good:
1616	jnz the_end
1617	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1618	the_end:
1619	add esp, 8
1620	}
1621	# endif
1622	}
1623	#endif
1624
1625
1626	/**
1627	* Executes VMXOFF
1628	*/
1629	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1630	DECLASM(void) VMXDisable(void);
1631	#else
1632	DECLINLINE(void) VMXDisable(void)
1633	{
1634	# if RT_INLINE_ASM_GNU_STYLE
1635	__asm__ __volatile__ (
1636	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1637	);
1638
1639	# elif VMX_USE_MSC_INTRINSICS
1640	__vmx_off();
1641
1642	# else
1643	__asm
1644	{
1645	_emit 0x0F
1646	_emit 0x01
1647	_emit 0xC4 /* VMXOFF */
1648	}
1649	# endif
1650	}
1651	#endif
1652
1653
1654	/**
1655	* Executes VMCLEAR
1656	*
1657	* @returns VBox status code
1658	* @param pVMCS Physical address of VM control structure
1659	*/
1660	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1661	DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1662	#else
1663	DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1664	{
1665	# if RT_INLINE_ASM_GNU_STYLE
1666	int rc = VINF_SUCCESS;
1667	__asm__ __volatile__ (
1668	"push %3 \n\t"
1669	"push %2 \n\t"
1670	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1671	"jnc 1f \n\t"
1672	"movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1673	"1: \n\t"
1674	"add $8, %%esp \n\t"
1675	:"=rm"(rc)
1676	:"0"(VINF_SUCCESS),
1677	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1678	"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1679	:"memory"
1680	);
1681	return rc;
1682
1683	# elif VMX_USE_MSC_INTRINSICS
1684	unsigned char rcMsc = __vmx_vmclear(&pVMCS);
1685	if (RT_LIKELY(rcMsc == 0))
1686	return VINF_SUCCESS;
1687	return VERR_VMX_INVALID_VMCS_PTR;
1688
1689	# else
1690	int rc = VINF_SUCCESS;
1691	__asm
1692	{
1693	push dword ptr [pVMCS+4]
1694	push dword ptr [pVMCS]
1695	_emit 0x66
1696	_emit 0x0F
1697	_emit 0xC7
1698	_emit 0x34
1699	_emit 0x24 /* VMCLEAR [esp] */
1700	jnc success
1701	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1702	success:
1703	add esp, 8
1704	}
1705	return rc;
1706	# endif
1707	}
1708	#endif
1709
1710
1711	/**
1712	* Executes VMPTRLD
1713	*
1714	* @returns VBox status code
1715	* @param pVMCS Physical address of VMCS structure
1716	*/
1717	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1718	DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1719	#else
1720	DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1721	{
1722	# if RT_INLINE_ASM_GNU_STYLE
1723	int rc = VINF_SUCCESS;
1724	__asm__ __volatile__ (
1725	"push %3 \n\t"
1726	"push %2 \n\t"
1727	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1728	"jnc 1f \n\t"
1729	"movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1730	"1: \n\t"
1731	"add $8, %%esp \n\t"
1732	:"=rm"(rc)
1733	:"0"(VINF_SUCCESS),
1734	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1735	"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1736	);
1737	return rc;
1738
1739	# elif VMX_USE_MSC_INTRINSICS
1740	unsigned char rcMsc = __vmx_vmptrld(&pVMCS);
1741	if (RT_LIKELY(rcMsc == 0))
1742	return VINF_SUCCESS;
1743	return VERR_VMX_INVALID_VMCS_PTR;
1744
1745	# else
1746	int rc = VINF_SUCCESS;
1747	__asm
1748	{
1749	push dword ptr [pVMCS+4]
1750	push dword ptr [pVMCS]
1751	_emit 0x0F
1752	_emit 0xC7
1753	_emit 0x34
1754	_emit 0x24 /* VMPTRLD [esp] */
1755	jnc success
1756	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1757
1758	success:
1759	add esp, 8
1760	}
1761	return rc;
1762	# endif
1763	}
1764	#endif
1765
1766	/**
1767	* Executes VMPTRST
1768	*
1769	* @returns VBox status code
1770	* @param pVMCS Address that will receive the current pointer
1771	*/
1772	DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1773
1774	/**
1775	* Executes VMWRITE
1776	*
1777	* @returns VBox status code
1778	* @retval VINF_SUCCESS
1779	* @retval VERR_VMX_INVALID_VMCS_PTR
1780	* @retval VERR_VMX_INVALID_VMCS_FIELD
1781	*
1782	* @param idxField VMCS index
1783	* @param u32Val 32 bits value
1784	*
1785	* @remarks The values of the two status codes can be ORed together, the result
1786	* will be VERR_VMX_INVALID_VMCS_PTR.
1787	*/
1788	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1789	DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
1790	#else
1791	DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
1792	{
1793	# if RT_INLINE_ASM_GNU_STYLE
1794	int rc = VINF_SUCCESS;
1795	__asm__ __volatile__ (
1796	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1797	"ja 2f \n\t"
1798	"je 1f \n\t"
1799	"movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1800	"jmp 2f \n\t"
1801	"1: \n\t"
1802	"movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1803	"2: \n\t"
1804	:"=rm"(rc)
1805	:"0"(VINF_SUCCESS),
1806	"a"(idxField),
1807	"d"(u32Val)
1808	);
1809	return rc;
1810
1811	# elif VMX_USE_MSC_INTRINSICS
1812	unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
1813	if (RT_LIKELY(rcMsc == 0))
1814	return VINF_SUCCESS;
1815	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
1816
1817	#else
1818	int rc = VINF_SUCCESS;
1819	__asm
1820	{
1821	push dword ptr [u32Val]
1822	mov eax, [idxField]
1823	_emit 0x0F
1824	_emit 0x79
1825	_emit 0x04
1826	_emit 0x24 /* VMWRITE eax, [esp] */
1827	jnc valid_vmcs
1828	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1829	jmp the_end
1830
1831	valid_vmcs:
1832	jnz the_end
1833	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1834	the_end:
1835	add esp, 4
1836	}
1837	return rc;
1838	# endif
1839	}
1840	#endif
1841
1842	/**
1843	* Executes VMWRITE
1844	*
1845	* @returns VBox status code
1846	* @retval VINF_SUCCESS
1847	* @retval VERR_VMX_INVALID_VMCS_PTR
1848	* @retval VERR_VMX_INVALID_VMCS_FIELD
1849	*
1850	* @param idxField VMCS index
1851	* @param u64Val 16, 32 or 64 bits value
1852	*
1853	* @remarks The values of the two status codes can be ORed together, the result
1854	* will be VERR_VMX_INVALID_VMCS_PTR.
1855	*/
1856	#if !defined(RT_ARCH_X86) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1857	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
1858	DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
1859	# else /* VMX_USE_MSC_INTRINSICS */
1860	DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
1861	{
1862	unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
1863	if (RT_LIKELY(rcMsc == 0))
1864	return VINF_SUCCESS;
1865	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
1866	}
1867	# endif /* VMX_USE_MSC_INTRINSICS */
1868	#else
1869	# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
1870	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1871	#endif
1872
1873	#ifdef VBOX_WITH_OLD_VTX_CODE
1874	# if ARCH_BITS == 64
1875	# define VMXWriteVmcs VMXWriteVmcs64
1876	# else
1877	# define VMXWriteVmcs VMXWriteVmcs32
1878	# endif
1879	#else /* !VBOX_WITH_OLD_VTX_CODE */
1880	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1881	# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
1882	VMXWriteVmcs64(idxField, uVal) \
1883	: VMXWriteVmcs32(idxField, uVal)
1884	# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
1885	VMXWriteVmcs64(idxField, u64Val) \
1886	: VMXWriteVmcs32(idxField, u64Val)
1887	# elif ARCH_BITS == 32
1888	# define VMXWriteVmcsHstN VMXWriteVmcs32
1889	# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
1890	# else /* ARCH_BITS == 64 */
1891	# define VMXWriteVmcsHstN VMXWriteVmcs64
1892	# define VMXWriteVmcsGstN VMXWriteVmcs64
1893	# endif
1894	#endif /* !VBOX_WITH_OLD_VTX_CODE */
1895
1896
1897	/**
1898	* Invalidate a page using invept
1899	* @returns VBox status code
1900	* @param enmFlush Type of flush
1901	* @param pDescriptor Descriptor
1902	*/
1903	DECLASM(int) VMXR0InvEPT(VMX_FLUSH_EPT enmFlush, uint64_t *pDescriptor);
1904
1905	/**
1906	* Invalidate a page using invvpid
1907	* @returns VBox status code
1908	* @param enmFlush Type of flush
1909	* @param pDescriptor Descriptor
1910	*/
1911	DECLASM(int) VMXR0InvVPID(VMX_FLUSH_VPID enmFlush, uint64_t *pDescriptor);
1912
1913	/**
1914	* Executes VMREAD
1915	*
1916	* @returns VBox status code
1917	* @retval VINF_SUCCESS
1918	* @retval VERR_VMX_INVALID_VMCS_PTR
1919	* @retval VERR_VMX_INVALID_VMCS_FIELD
1920	*
1921	* @param idxField VMCS index
1922	* @param pData Ptr to store VM field value
1923	*
1924	* @remarks The values of the two status codes can be ORed together, the result
1925	* will be VERR_VMX_INVALID_VMCS_PTR.
1926	*/
1927	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1928	DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
1929	#else
1930	DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
1931	{
1932	# if RT_INLINE_ASM_GNU_STYLE
1933	int rc = VINF_SUCCESS;
1934	__asm__ __volatile__ (
1935	"movl $"RT_XSTR(VINF_SUCCESS)", %0 \n\t"
1936	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1937	"ja 2f \n\t"
1938	"je 1f \n\t"
1939	"movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1940	"jmp 2f \n\t"
1941	"1: \n\t"
1942	"movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1943	"2: \n\t"
1944	:"=&r"(rc),
1945	"=d"(*pData)
1946	:"a"(idxField),
1947	"d"(0)
1948	);
1949	return rc;
1950
1951	# elif VMX_USE_MSC_INTRINSICS
1952	unsigned char rcMsc;
1953	# if ARCH_BITS == 32
1954	rcMsc = __vmx_vmread(idxField, pData);
1955	# else
1956	uint64_t u64Tmp;
1957	rcMsc = __vmx_vmread(idxField, &u64Tmp);
1958	*pData = (uint32_t)u64Tmp;
1959	# endif
1960	if (RT_LIKELY(rcMsc == 0))
1961	return VINF_SUCCESS;
1962	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
1963
1964	#else
1965	int rc = VINF_SUCCESS;
1966	__asm
1967	{
1968	sub esp, 4
1969	mov dword ptr [esp], 0
1970	mov eax, [idxField]
1971	_emit 0x0F
1972	_emit 0x78
1973	_emit 0x04
1974	_emit 0x24 /* VMREAD eax, [esp] */
1975	mov edx, pData
1976	pop dword ptr [edx]
1977	jnc valid_vmcs
1978	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1979	jmp the_end
1980
1981	valid_vmcs:
1982	jnz the_end
1983	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1984	the_end:
1985	}
1986	return rc;
1987	# endif
1988	}
1989	#endif
1990
1991	/**
1992	* Executes VMREAD
1993	*
1994	* @returns VBox status code
1995	* @retval VINF_SUCCESS
1996	* @retval VERR_VMX_INVALID_VMCS_PTR
1997	* @retval VERR_VMX_INVALID_VMCS_FIELD
1998	*
1999	* @param idxField VMCS index
2000	* @param pData Ptr to store VM field value
2001	*
2002	* @remarks The values of the two status codes can be ORed together, the result
2003	* will be VERR_VMX_INVALID_VMCS_PTR.
2004	*/
2005	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2006	DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2007	#else
2008	DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2009	{
2010	# if VMX_USE_MSC_INTRINSICS
2011	unsigned char rcMsc;
2012	# if ARCH_BITS == 32
2013	size_t uLow;
2014	size_t uHigh;
2015	rcMsc = __vmx_vmread(idxField, &uLow);
2016	rcMsc \|= __vmx_vmread(idxField + 1, &uHigh);
2017	*pData = RT_MAKE_U64(uLow, uHigh);
2018	# else
2019	rcMsc = __vmx_vmread(idxField, pData);
2020	# endif
2021	if (RT_LIKELY(rcMsc == 0))
2022	return VINF_SUCCESS;
2023	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2024
2025	# elif ARCH_BITS == 32
2026	int rc;
2027	uint32_t val_hi, val;
2028	rc = VMXReadVmcs32(idxField, &val);
2029	rc \|= VMXReadVmcs32(idxField + 1, &val_hi);
2030	AssertRC(rc);
2031	*pData = RT_MAKE_U64(val, val_hi);
2032	return rc;
2033
2034	# else
2035	# error "Shouldn't be here..."
2036	# endif
2037	}
2038	#endif
2039
2040	#ifdef VBOX_WITH_OLD_VTX_CODE
2041	# if ARCH_BITS == 64
2042	# define VMXReadVmcsField VMXReadVmcs64
2043	# else
2044	# define VMXReadVmcsField VMXReadVmcs32
2045	# endif
2046	#endif
2047
2048	/**
2049	* Gets the last instruction error value from the current VMCS
2050	*
2051	* @returns error value
2052	*/
2053	DECLINLINE(uint32_t) VMXGetLastError(void)
2054	{
2055	#if ARCH_BITS == 64
2056	uint64_t uLastError = 0;
2057	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2058	AssertRC(rc);
2059	return (uint32_t)uLastError;
2060
2061	#else /* 32-bit host: */
2062	uint32_t uLastError = 0;
2063	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2064	AssertRC(rc);
2065	return uLastError;
2066	#endif
2067	}
2068
2069	#ifdef IN_RING0
2070	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2071	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2072	#endif /* IN_RING0 */
2073
2074	/** @} */
2075
2076	#endif
2077

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 47445

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