VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 47635

Last change on this file since 47635 was 47635, checked in by vboxsync, 12 years ago

VMM/HM: Implemented VMX guest-state checks in accordance with the Intel spec.
Any errors founds now flow to the release log.
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File size: 94.8 KB
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1/** @file
2 * HM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2013 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vmx_h
27#define ___VBox_vmm_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/x86.h>
32#include <iprt/assert.h>
33
34/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35 when targeting AMD64. */
36#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37# include <intrin.h>
38/* We always want them as intrinsics, no functions. */
39# pragma intrinsic(__vmx_on)
40# pragma intrinsic(__vmx_off)
41# pragma intrinsic(__vmx_vmclear)
42# pragma intrinsic(__vmx_vmptrld)
43# pragma intrinsic(__vmx_vmread)
44# pragma intrinsic(__vmx_vmwrite)
45# define VMX_USE_MSC_INTRINSICS 1
46#else
47# define VMX_USE_MSC_INTRINSICS 0
48#endif
49
50
51/** @defgroup grp_vmx vmx Types and Definitions
52 * @ingroup grp_hm
53 * @{
54 */
55
56/** @name Host-state restoration flags.
57 * @{
58 */
59/* If you change these values don't forget to update the assembly defines as well! */
60#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
61#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
62#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
63#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
64#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
65#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
66#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
67/** @} */
68
69/**
70 * Host-state restoration structure.
71 * This holds host-state fields that require manual restoration.
72 * Assembly version found in hm_vmx.mac (should be automatically verified).
73 */
74typedef struct VMXRESTOREHOST
75{
76 RTSEL uHostSelDS; /* 0x00 */
77 RTSEL uHostSelES; /* 0x02 */
78 RTSEL uHostSelFS; /* 0x04 */
79 RTSEL uHostSelGS; /* 0x06 */
80 RTSEL uHostSelTR; /* 0x08 */
81 uint8_t abPadding0[4];
82 X86XDTR64 HostGdtr; /**< 0x0e - should be aligned by it's 64-bit member. */
83 uint8_t abPadding1[6];
84 X86XDTR64 HostIdtr; /**< 0x1e - should be aligned by it's 64-bit member. */
85 uint64_t uHostFSBase; /* 0x28 */
86 uint64_t uHostGSBase; /* 0x30 */
87} VMXRESTOREHOST;
88/** Pointer to VMXRESTOREHOST. */
89typedef VMXRESTOREHOST *PVMXRESTOREHOST;
90AssertCompileSize(X86XDTR64, 10);
91AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
92AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
93AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
94AssertCompileSize(VMXRESTOREHOST, 56);
95
96/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
97 * @{
98 */
99/** An error occurred while checking invalid-guest-state. */
100#define VMX_IGS_ERROR 0
101/** The invalid guest-state checks did not find any reason why. */
102#define VMX_IGS_REASON_NOT_FOUND 1
103/** CR0 fixed1 bits invalid. */
104#define VMX_IGS_CR0_FIXED1 2
105/** CR0 fixed0 bits invalid. */
106#define VMX_IGS_CR0_FIXED0 3
107/** CR0.PE and CR0.PE invalid VT-x/host combination. */
108#define VMX_IGS_CR0_PG_PE_COMBO 4
109/** CR4 fixed1 bits invalid. */
110#define VMX_IGS_CR4_FIXED1 5
111/** CR4 fixed0 bits invalid. */
112#define VMX_IGS_CR4_FIXED0 6
113/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
114 * VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
115#define VMX_IGS_DEBUGCTL_MSR_RESERVED 7
116/** CR0.PG not set for long-mode when not using unrestricted guest. */
117#define VMX_IGS_CR0_PG_LONGMODE 8
118/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
119#define VMX_IGS_CR4_PAE_LONGMODE 9
120/** CR4.PCIDE set for 32-bit guest. */
121#define VMX_IGS_CR4_PCIDE 10
122/** VMCS' DR7 reserved bits not set to 0. */
123#define VMX_IGS_DR7_RESERVED 11
124/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
125#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12
126/** VMCS' EFER MSR reserved bits not set to 0. */
127#define VMX_IGS_EFER_MSR_RESERVED 13
128/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
129#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14
130/** VMCS' EFER MSR.LMA does not match CR0.PG of the guest when not using
131 * unrestricted guest. */
132#define VMX_IGS_EFER_LMA_PG_MISMATCH 15
133/** CS.Attr.P bit invalid. */
134#define VMX_IGS_CS_ATTR_P_INVALID 16
135/** CS.Attr reserved bits not set to 0. */
136#define VMX_IGS_CS_ATTR_RESERVED 17
137/** CS.Attr.G bit invalid. */
138#define VMX_IGS_CS_ATTR_G_INVALID 18
139/** CS is unusable. */
140#define VMX_IGS_CS_ATTR_UNUSABLE 19
141/** CS and SS DPL unequal. */
142#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20
143/** CS and SS DPL mismatch. */
144#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21
145/** CS Attr.Type invalid. */
146#define VMX_IGS_CS_ATTR_TYPE_INVALID 22
147/** CS and SS RPL unequal. */
148#define VMX_IGS_SS_CS_RPL_UNEQUAL 23
149/** SS.Attr.DPL and SS RPL unequal. */
150#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24
151/** SS.Attr.DPL invalid for segment type. */
152#define VMX_IGS_SS_ATTR_DPL_INVALID 25
153/** SS.Attr.Type invalid. */
154#define VMX_IGS_SS_ATTR_TYPE_INVALID 26
155/** SS.Attr.P bit invalid. */
156#define VMX_IGS_SS_ATTR_P_INVALID 27
157/** SS.Attr reserved bits not set to 0. */
158#define VMX_IGS_SS_ATTR_RESERVED 28
159/** SS.Attr.G bit invalid. */
160#define VMX_IGS_SS_ATTR_G_INVALID 29
161/** DS.Attr.A bit invalid. */
162#define VMX_IGS_DS_ATTR_A_INVALID 30
163/** DS.Attr.P bit invalid. */
164#define VMX_IGS_DS_ATTR_P_INVALID 31
165/** DS.Attr.DPL and DS RPL unequal. */
166#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32
167/** DS.Attr reserved bits not set to 0. */
168#define VMX_IGS_DS_ATTR_RESERVED 33
169/** DS.Attr.G bit invalid. */
170#define VMX_IGS_DS_ATTR_G_INVALID 34
171/** DS.Attr.Type invalid. */
172#define VMX_IGS_DS_ATTR_TYPE_INVALID 35
173/** ES.Attr.A bit invalid. */
174#define VMX_IGS_ES_ATTR_A_INVALID 36
175/** ES.Attr.P bit invalid. */
176#define VMX_IGS_ES_ATTR_P_INVALID 37
177/** ES.Attr.DPL and DS RPL unequal. */
178#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38
179/** ES.Attr reserved bits not set to 0. */
180#define VMX_IGS_ES_ATTR_RESERVED 39
181/** ES.Attr.G bit invalid. */
182#define VMX_IGS_ES_ATTR_G_INVALID 40
183/** ES.Attr.Type invalid. */
184#define VMX_IGS_ES_ATTR_TYPE_INVALID 41
185/** FS.Attr.A bit invalid. */
186#define VMX_IGS_FS_ATTR_A_INVALID 42
187/** FS.Attr.P bit invalid. */
188#define VMX_IGS_FS_ATTR_P_INVALID 43
189/** FS.Attr.DPL and DS RPL unequal. */
190#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44
191/** FS.Attr reserved bits not set to 0. */
192#define VMX_IGS_FS_ATTR_RESERVED 45
193/** FS.Attr.G bit invalid. */
194#define VMX_IGS_FS_ATTR_G_INVALID 46
195/** FS.Attr.Type invalid. */
196#define VMX_IGS_FS_ATTR_TYPE_INVALID 47
197/** GS.Attr.A bit invalid. */
198#define VMX_IGS_GS_ATTR_A_INVALID 48
199/** GS.Attr.P bit invalid. */
200#define VMX_IGS_GS_ATTR_P_INVALID 49
201/** GS.Attr.DPL and DS RPL unequal. */
202#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 50
203/** GS.Attr reserved bits not set to 0. */
204#define VMX_IGS_GS_ATTR_RESERVED 51
205/** GS.Attr.G bit invalid. */
206#define VMX_IGS_GS_ATTR_G_INVALID 52
207/** GS.Attr.Type invalid. */
208#define VMX_IGS_GS_ATTR_TYPE_INVALID 53
209/** V86 mode CS.Base invalid. */
210#define VMX_IGS_V86_CS_BASE_INVALID 54
211/** V86 mode CS.Limit invalid. */
212#define VMX_IGS_V86_CS_LIMIT_INVALID 55
213/** V86 mode CS.Attr invalid. */
214#define VMX_IGS_V86_CS_ATTR_INVALID 56
215/** V86 mode SS.Base invalid. */
216#define VMX_IGS_V86_SS_BASE_INVALID 57
217/** V86 mode SS.Limit invalid. */
218#define VMX_IGS_V86_SS_LIMIT_INVALID 59
219/** V86 mode SS.Attr invalid. */
220#define VMX_IGS_V86_SS_ATTR_INVALID 59
221/** V86 mode DS.Base invalid. */
222#define VMX_IGS_V86_DS_BASE_INVALID 60
223/** V86 mode DS.Limit invalid. */
224#define VMX_IGS_V86_DS_LIMIT_INVALID 61
225/** V86 mode DS.Attr invalid. */
226#define VMX_IGS_V86_DS_ATTR_INVALID 62
227/** V86 mode ES.Base invalid. */
228#define VMX_IGS_V86_ES_BASE_INVALID 63
229/** V86 mode ES.Limit invalid. */
230#define VMX_IGS_V86_ES_LIMIT_INVALID 64
231/** V86 mode ES.Attr invalid. */
232#define VMX_IGS_V86_ES_ATTR_INVALID 65
233/** V86 mode FS.Base invalid. */
234#define VMX_IGS_V86_FS_BASE_INVALID 66
235/** V86 mode FS.Limit invalid. */
236#define VMX_IGS_V86_FS_LIMIT_INVALID 67
237/** V86 mode FS.Attr invalid. */
238#define VMX_IGS_V86_FS_ATTR_INVALID 68
239/** V86 mode GS.Base invalid. */
240#define VMX_IGS_V86_GS_BASE_INVALID 69
241/** V86 mode GS.Limit invalid. */
242#define VMX_IGS_V86_GS_LIMIT_INVALID 70
243/** V86 mode GS.Attr invalid. */
244#define VMX_IGS_V86_GS_ATTR_INVALID 71
245/** Longmode CS.Base invalid. */
246#define VMX_IGS_LONGMODE_CS_BASE_INVALID 72
247/** Longmode SS.Base invalid. */
248#define VMX_IGS_LONGMODE_SS_BASE_INVALID 73
249/** Longmode DS.Base invalid. */
250#define VMX_IGS_LONGMODE_DS_BASE_INVALID 74
251/** Longmode ES.Base invalid. */
252#define VMX_IGS_LONGMODE_ES_BASE_INVALID 75
253/** SYSENTER ESP is not canonical. */
254#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76
255/** SYSENTER EIP is not canonical. */
256#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77
257/** PAT MSR invalid. */
258#define VMX_IGS_PAT_MSR_INVALID 78
259/** PAT MSR reserved bits not set to 0. */
260#define VMX_IGS_PAT_MSR_RESERVED 79
261/** GDTR.Base is not canonical. */
262#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80
263/** IDTR.Base is not canonical. */
264#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81
265/** GDTR.Limit invalid. */
266#define VMX_IGS_GDTR_LIMIT_INVALID 82
267/** IDTR.Limit invalid. */
268#define VMX_IGS_IDTR_LIMIT_INVALID 83
269/** Longmode RIP is invalid. */
270#define VMX_IGS_LONGMODE_RIP_INVALID 84
271/** RFLAGS reserved bits not set to 0. */
272#define VMX_IGS_RFLAGS_RESERVED 85
273/** RFLAGS RA1 reserved bits not set to 1. */
274#define VMX_IGS_RFLAGS_RESERVED1 86
275/** RFLAGS.VM (V86 mode) invalid. */
276#define VMX_IGS_RFLAGS_VM_INVALID 87
277/** RFLAGS.IF invalid. */
278#define VMX_IGS_RFLAGS_IF_INVALID 88
279/** Activity state invalid. */
280#define VMX_IGS_ACTIVITY_STATE_INVALID 89
281/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
282#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90
283/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
284#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91
285/** Activity state SIPI WAIT invalid. */
286#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92
287/** Interruptibility state reserved bits not set to 0. */
288#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93
289/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
290#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94
291/** Interruptibility state block-by-STI invalid for EFLAGS. */
292#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95
293/** Interruptibility state invalid while trying to deliver external
294 * interrupt. */
295#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96
296/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
297 * NMI. */
298#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97
299/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
300#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98
301/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
302#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99
303/** Interruptibilty state block-by-STI (maybe) invalid when trying to deliver
304 * an NMI. */
305#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100
306/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
307 * active. */
308#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101
309/** Pending debug exceptions reserved bits not set to 0. */
310#define VMX_IGS_PENDING_DEBUG_RESERVED 102
311/** Longmode pending debug exceptions reserved bits not set to 0. */
312#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103
313/** Pending debug exceptions.BS bit is not set when it should be. */
314#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104
315/** Pending debug exceptions.BS bit is not clear when it should be. */
316#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105
317/** VMCS link pointer reserved bits not set to 0. */
318#define VMX_IGS_VMCS_LINK_PTR_RESERVED 106
319/** @} */
320
321/** @name VMX VMCS-Read cache indices.
322 * @{
323 */
324#ifndef VBOX_WITH_OLD_VTX_CODE
325# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
326# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
327# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
328# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
329# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
330# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
331# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
332# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
333# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
334# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
335# define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
336# define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
337# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
338# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
339# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
340# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
341# define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
342# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
343#else /* VBOX_WITH_OLD_VTX_CODE */
344# define VMX_VMCS_GUEST_RIP_CACHE_IDX 0
345# define VMX_VMCS_GUEST_RSP_CACHE_IDX 1
346# define VMX_VMCS_GUEST_RFLAGS_CACHE_IDX 2
347# define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE_CACHE_IDX 3
348# define VMX_VMCS_CTRL_CR0_READ_SHADOW_CACHE_IDX 4
349# define VMX_VMCS_GUEST_CR0_CACHE_IDX 5
350# define VMX_VMCS_CTRL_CR4_READ_SHADOW_CACHE_IDX 6
351# define VMX_VMCS_GUEST_CR4_CACHE_IDX 7
352# define VMX_VMCS_GUEST_DR7_CACHE_IDX 8
353# define VMX_VMCS32_GUEST_SYSENTER_CS_CACHE_IDX 9
354# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 10
355# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 11
356# define VMX_VMCS32_GUEST_GDTR_LIMIT_CACHE_IDX 12
357# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 13
358# define VMX_VMCS32_GUEST_IDTR_LIMIT_CACHE_IDX 14
359# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 15
360# define VMX_VMCS16_GUEST_FIELD_CS_CACHE_IDX 16
361# define VMX_VMCS32_GUEST_CS_LIMIT_CACHE_IDX 17
362# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 18
363# define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS_CACHE_IDX 19
364# define VMX_VMCS16_GUEST_FIELD_DS_CACHE_IDX 20
365# define VMX_VMCS32_GUEST_DS_LIMIT_CACHE_IDX 21
366# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 22
367# define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS_CACHE_IDX 23
368# define VMX_VMCS16_GUEST_FIELD_ES_CACHE_IDX 24
369# define VMX_VMCS32_GUEST_ES_LIMIT_CACHE_IDX 25
370# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 26
371# define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS_CACHE_IDX 27
372# define VMX_VMCS16_GUEST_FIELD_FS_CACHE_IDX 28
373# define VMX_VMCS32_GUEST_FS_LIMIT_CACHE_IDX 29
374# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 30
375# define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS_CACHE_IDX 31
376# define VMX_VMCS16_GUEST_FIELD_GS_CACHE_IDX 32
377# define VMX_VMCS32_GUEST_GS_LIMIT_CACHE_IDX 33
378# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 34
379# define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS_CACHE_IDX 35
380# define VMX_VMCS16_GUEST_FIELD_SS_CACHE_IDX 36
381# define VMX_VMCS32_GUEST_SS_LIMIT_CACHE_IDX 37
382# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 38
383# define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS_CACHE_IDX 39
384# define VMX_VMCS16_GUEST_FIELD_TR_CACHE_IDX 40
385# define VMX_VMCS32_GUEST_TR_LIMIT_CACHE_IDX 41
386# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 42
387# define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS_CACHE_IDX 43
388# define VMX_VMCS16_GUEST_FIELD_LDTR_CACHE_IDX 44
389# define VMX_VMCS32_GUEST_LDTR_LIMIT_CACHE_IDX 45
390# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 46
391# define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS_CACHE_IDX 47
392# define VMX_VMCS32_RO_EXIT_REASON_CACHE_IDX 48
393# define VMX_VMCS32_RO_VM_INSTR_ERROR_CACHE_IDX 49
394# define VMX_VMCS32_RO_EXIT_INSTR_LENGTH_CACHE_IDX 50
395# define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE_CACHE_IDX 51
396# define VMX_VMCS32_RO_EXIT_INSTR_INFO_CACHE_IDX 52
397# define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO_CACHE_IDX 53
398# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 54
399# define VMX_VMCS32_RO_IDT_INFO_CACHE_IDX 55
400# define VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX 56
401# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX + 1)
402# define VMX_VMCS_GUEST_CR3_CACHE_IDX 57
403# define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX 58
404# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX + 1)
405#endif /* VBOX_WITH_OLD_VTX_CODE */
406/** @} */
407
408/** @name VMX EPT paging structures
409 * @{
410 */
411
412/**
413 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
414 */
415#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
416
417/**
418 * EPT Page Directory Pointer Entry. Bit view.
419 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
420 * this did cause trouble with one compiler/version).
421 */
422#pragma pack(1)
423typedef struct EPTPML4EBITS
424{
425 /** Present bit. */
426 uint64_t u1Present : 1;
427 /** Writable bit. */
428 uint64_t u1Write : 1;
429 /** Executable bit. */
430 uint64_t u1Execute : 1;
431 /** Reserved (must be 0). */
432 uint64_t u5Reserved : 5;
433 /** Available for software. */
434 uint64_t u4Available : 4;
435 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
436 uint64_t u40PhysAddr : 40;
437 /** Availabe for software. */
438 uint64_t u12Available : 12;
439} EPTPML4EBITS;
440#pragma pack()
441AssertCompileSize(EPTPML4EBITS, 8);
442
443/** Bits 12-51 - - EPT - Physical Page number of the next level. */
444#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
445/** The page shift to get the PML4 index. */
446#define EPT_PML4_SHIFT X86_PML4_SHIFT
447/** The PML4 index mask (apply to a shifted page address). */
448#define EPT_PML4_MASK X86_PML4_MASK
449
450/**
451 * EPT PML4E.
452 */
453#pragma pack(1)
454typedef union EPTPML4E
455{
456 /** Normal view. */
457 EPTPML4EBITS n;
458 /** Unsigned integer view. */
459 X86PGPAEUINT u;
460 /** 64 bit unsigned integer view. */
461 uint64_t au64[1];
462 /** 32 bit unsigned integer view. */
463 uint32_t au32[2];
464} EPTPML4E;
465#pragma pack()
466/** Pointer to a PML4 table entry. */
467typedef EPTPML4E *PEPTPML4E;
468/** Pointer to a const PML4 table entry. */
469typedef const EPTPML4E *PCEPTPML4E;
470AssertCompileSize(EPTPML4E, 8);
471
472/**
473 * EPT PML4 Table.
474 */
475#pragma pack(1)
476typedef struct EPTPML4
477{
478 EPTPML4E a[EPT_PG_ENTRIES];
479} EPTPML4;
480#pragma pack()
481/** Pointer to an EPT PML4 Table. */
482typedef EPTPML4 *PEPTPML4;
483/** Pointer to a const EPT PML4 Table. */
484typedef const EPTPML4 *PCEPTPML4;
485
486/**
487 * EPT Page Directory Pointer Entry. Bit view.
488 */
489#pragma pack(1)
490typedef struct EPTPDPTEBITS
491{
492 /** Present bit. */
493 uint64_t u1Present : 1;
494 /** Writable bit. */
495 uint64_t u1Write : 1;
496 /** Executable bit. */
497 uint64_t u1Execute : 1;
498 /** Reserved (must be 0). */
499 uint64_t u5Reserved : 5;
500 /** Available for software. */
501 uint64_t u4Available : 4;
502 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
503 uint64_t u40PhysAddr : 40;
504 /** Availabe for software. */
505 uint64_t u12Available : 12;
506} EPTPDPTEBITS;
507#pragma pack()
508AssertCompileSize(EPTPDPTEBITS, 8);
509
510/** Bits 12-51 - - EPT - Physical Page number of the next level. */
511#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
512/** The page shift to get the PDPT index. */
513#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
514/** The PDPT index mask (apply to a shifted page address). */
515#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
516
517/**
518 * EPT Page Directory Pointer.
519 */
520#pragma pack(1)
521typedef union EPTPDPTE
522{
523 /** Normal view. */
524 EPTPDPTEBITS n;
525 /** Unsigned integer view. */
526 X86PGPAEUINT u;
527 /** 64 bit unsigned integer view. */
528 uint64_t au64[1];
529 /** 32 bit unsigned integer view. */
530 uint32_t au32[2];
531} EPTPDPTE;
532#pragma pack()
533/** Pointer to an EPT Page Directory Pointer Entry. */
534typedef EPTPDPTE *PEPTPDPTE;
535/** Pointer to a const EPT Page Directory Pointer Entry. */
536typedef const EPTPDPTE *PCEPTPDPTE;
537AssertCompileSize(EPTPDPTE, 8);
538
539/**
540 * EPT Page Directory Pointer Table.
541 */
542#pragma pack(1)
543typedef struct EPTPDPT
544{
545 EPTPDPTE a[EPT_PG_ENTRIES];
546} EPTPDPT;
547#pragma pack()
548/** Pointer to an EPT Page Directory Pointer Table. */
549typedef EPTPDPT *PEPTPDPT;
550/** Pointer to a const EPT Page Directory Pointer Table. */
551typedef const EPTPDPT *PCEPTPDPT;
552
553
554/**
555 * EPT Page Directory Table Entry. Bit view.
556 */
557#pragma pack(1)
558typedef struct EPTPDEBITS
559{
560 /** Present bit. */
561 uint64_t u1Present : 1;
562 /** Writable bit. */
563 uint64_t u1Write : 1;
564 /** Executable bit. */
565 uint64_t u1Execute : 1;
566 /** Reserved (must be 0). */
567 uint64_t u4Reserved : 4;
568 /** Big page (must be 0 here). */
569 uint64_t u1Size : 1;
570 /** Available for software. */
571 uint64_t u4Available : 4;
572 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
573 uint64_t u40PhysAddr : 40;
574 /** Availabe for software. */
575 uint64_t u12Available : 12;
576} EPTPDEBITS;
577#pragma pack()
578AssertCompileSize(EPTPDEBITS, 8);
579
580/** Bits 12-51 - - EPT - Physical Page number of the next level. */
581#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
582/** The page shift to get the PD index. */
583#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
584/** The PD index mask (apply to a shifted page address). */
585#define EPT_PD_MASK X86_PD_PAE_MASK
586
587/**
588 * EPT 2MB Page Directory Table Entry. Bit view.
589 */
590#pragma pack(1)
591typedef struct EPTPDE2MBITS
592{
593 /** Present bit. */
594 uint64_t u1Present : 1;
595 /** Writable bit. */
596 uint64_t u1Write : 1;
597 /** Executable bit. */
598 uint64_t u1Execute : 1;
599 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
600 uint64_t u3EMT : 3;
601 /** Ignore PAT memory type */
602 uint64_t u1IgnorePAT : 1;
603 /** Big page (must be 1 here). */
604 uint64_t u1Size : 1;
605 /** Available for software. */
606 uint64_t u4Available : 4;
607 /** Reserved (must be 0). */
608 uint64_t u9Reserved : 9;
609 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
610 uint64_t u31PhysAddr : 31;
611 /** Availabe for software. */
612 uint64_t u12Available : 12;
613} EPTPDE2MBITS;
614#pragma pack()
615AssertCompileSize(EPTPDE2MBITS, 8);
616
617/** Bits 21-51 - - EPT - Physical Page number of the next level. */
618#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
619
620/**
621 * EPT Page Directory Table Entry.
622 */
623#pragma pack(1)
624typedef union EPTPDE
625{
626 /** Normal view. */
627 EPTPDEBITS n;
628 /** 2MB view (big). */
629 EPTPDE2MBITS b;
630 /** Unsigned integer view. */
631 X86PGPAEUINT u;
632 /** 64 bit unsigned integer view. */
633 uint64_t au64[1];
634 /** 32 bit unsigned integer view. */
635 uint32_t au32[2];
636} EPTPDE;
637#pragma pack()
638/** Pointer to an EPT Page Directory Table Entry. */
639typedef EPTPDE *PEPTPDE;
640/** Pointer to a const EPT Page Directory Table Entry. */
641typedef const EPTPDE *PCEPTPDE;
642AssertCompileSize(EPTPDE, 8);
643
644/**
645 * EPT Page Directory Table.
646 */
647#pragma pack(1)
648typedef struct EPTPD
649{
650 EPTPDE a[EPT_PG_ENTRIES];
651} EPTPD;
652#pragma pack()
653/** Pointer to an EPT Page Directory Table. */
654typedef EPTPD *PEPTPD;
655/** Pointer to a const EPT Page Directory Table. */
656typedef const EPTPD *PCEPTPD;
657
658
659/**
660 * EPT Page Table Entry. Bit view.
661 */
662#pragma pack(1)
663typedef struct EPTPTEBITS
664{
665 /** 0 - Present bit.
666 * @remark This is a convenience "misnomer". The bit actually indicates
667 * read access and the CPU will consider an entry with any of the
668 * first three bits set as present. Since all our valid entries
669 * will have this bit set, it can be used as a present indicator
670 * and allow some code sharing. */
671 uint64_t u1Present : 1;
672 /** 1 - Writable bit. */
673 uint64_t u1Write : 1;
674 /** 2 - Executable bit. */
675 uint64_t u1Execute : 1;
676 /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
677 uint64_t u3EMT : 3;
678 /** 6 - Ignore PAT memory type */
679 uint64_t u1IgnorePAT : 1;
680 /** 11:7 - Available for software. */
681 uint64_t u5Available : 5;
682 /** 51:12 - Physical address of page. Restricted by maximum physical
683 * address width of the cpu. */
684 uint64_t u40PhysAddr : 40;
685 /** 63:52 - Available for software. */
686 uint64_t u12Available : 12;
687} EPTPTEBITS;
688#pragma pack()
689AssertCompileSize(EPTPTEBITS, 8);
690
691/** Bits 12-51 - - EPT - Physical Page number of the next level. */
692#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
693/** The page shift to get the EPT PTE index. */
694#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
695/** The EPT PT index mask (apply to a shifted page address). */
696#define EPT_PT_MASK X86_PT_PAE_MASK
697
698/**
699 * EPT Page Table Entry.
700 */
701#pragma pack(1)
702typedef union EPTPTE
703{
704 /** Normal view. */
705 EPTPTEBITS n;
706 /** Unsigned integer view. */
707 X86PGPAEUINT u;
708 /** 64 bit unsigned integer view. */
709 uint64_t au64[1];
710 /** 32 bit unsigned integer view. */
711 uint32_t au32[2];
712} EPTPTE;
713#pragma pack()
714/** Pointer to an EPT Page Directory Table Entry. */
715typedef EPTPTE *PEPTPTE;
716/** Pointer to a const EPT Page Directory Table Entry. */
717typedef const EPTPTE *PCEPTPTE;
718AssertCompileSize(EPTPTE, 8);
719
720/**
721 * EPT Page Table.
722 */
723#pragma pack(1)
724typedef struct EPTPT
725{
726 EPTPTE a[EPT_PG_ENTRIES];
727} EPTPT;
728#pragma pack()
729/** Pointer to an extended page table. */
730typedef EPTPT *PEPTPT;
731/** Pointer to a const extended table. */
732typedef const EPTPT *PCEPTPT;
733
734/**
735 * VPID flush types.
736 */
737typedef enum
738{
739 /** Invalidate a specific page. */
740 VMX_FLUSH_VPID_INDIV_ADDR = 0,
741 /** Invalidate one context (specific VPID). */
742 VMX_FLUSH_VPID_SINGLE_CONTEXT = 1,
743 /** Invalidate all contexts (all VPIDs). */
744 VMX_FLUSH_VPID_ALL_CONTEXTS = 2,
745 /** Invalidate a single VPID context retaining global mappings. */
746 VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
747 /** Unsupported by VirtualBox. */
748 VMX_FLUSH_VPID_NOT_SUPPORTED = 0xbad,
749 /** Unsupported by CPU. */
750 VMX_FLUSH_VPID_NONE = 0xb00,
751 /** 32bit hackishness. */
752 VMX_FLUSH_VPID_32BIT_HACK = 0x7fffffff
753} VMX_FLUSH_VPID;
754
755/**
756 * EPT flush types.
757 */
758typedef enum
759{
760 /** Invalidate one context (specific EPT). */
761 VMX_FLUSH_EPT_SINGLE_CONTEXT = 1,
762 /* Invalidate all contexts (all EPTs) */
763 VMX_FLUSH_EPT_ALL_CONTEXTS = 2,
764 /** Unsupported by VirtualBox. */
765 VMX_FLUSH_EPT_NOT_SUPPORTED = 0xbad,
766 /** Unsupported by CPU. */
767 VMX_FLUSH_EPT_NONE = 0xb00,
768 /** 32bit hackishness. */
769 VMX_FLUSH_EPT_32BIT_HACK = 0x7fffffff
770} VMX_FLUSH_EPT;
771/** @} */
772
773/** @name MSR autoload/store elements
774 * @{
775 */
776#pragma pack(1)
777typedef struct
778{
779 uint32_t u32IndexMSR;
780 uint32_t u32Reserved;
781 uint64_t u64Value;
782} VMXMSR;
783#pragma pack()
784/** Pointer to an MSR load/store element. */
785typedef VMXMSR *PVMXMSR;
786/** Pointer to a const MSR load/store element. */
787typedef const VMXMSR *PCVMXMSR;
788
789/** @} */
790
791
792/** @name VMX-capability qword
793 * @{
794 */
795#pragma pack(1)
796typedef union
797{
798 struct
799 {
800 /** Bits set here -must- be set in the correpsonding VM-execution controls. */
801 uint32_t disallowed0;
802 /** Bits cleared here -must- be cleared in the corresponding VM-execution
803 * controls. */
804 uint32_t allowed1;
805 } n;
806 uint64_t u;
807} VMX_CAPABILITY;
808#pragma pack()
809/** @} */
810
811/** @name VMX EFLAGS reserved bits.
812 * @{
813 */
814/** And-mask for setting reserved bits to zero */
815#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
816/** Or-mask for setting reserved bits to 1 */
817#define VMX_EFLAGS_RESERVED_1 0x00000002
818/** @} */
819
820/** @name VMX Basic Exit Reasons.
821 * @{
822 */
823/** -1 Invalid exit code */
824#define VMX_EXIT_INVALID -1
825/** 0 Exception or non-maskable interrupt (NMI). */
826#define VMX_EXIT_XCPT_OR_NMI 0
827/** 1 External interrupt. */
828#define VMX_EXIT_EXT_INT 1
829/** 2 Triple fault. */
830#define VMX_EXIT_TRIPLE_FAULT 2
831/** 3 INIT signal. */
832#define VMX_EXIT_INIT_SIGNAL 3
833/** 4 Start-up IPI (SIPI). */
834#define VMX_EXIT_SIPI 4
835/** 5 I/O system-management interrupt (SMI). */
836#define VMX_EXIT_IO_SMI 5
837/** 6 Other SMI. */
838#define VMX_EXIT_SMI 6
839/** 7 Interrupt window exiting. */
840#define VMX_EXIT_INT_WINDOW 7
841/** 8 NMI window exiting. */
842#define VMX_EXIT_NMI_WINDOW 8
843/** 9 Task switch. */
844#define VMX_EXIT_TASK_SWITCH 9
845/** 10 Guest software attempted to execute CPUID. */
846#define VMX_EXIT_CPUID 10
847/** 10 Guest software attempted to execute GETSEC. */
848#define VMX_EXIT_GETSEC 11
849/** 12 Guest software attempted to execute HLT. */
850#define VMX_EXIT_HLT 12
851/** 13 Guest software attempted to execute INVD. */
852#define VMX_EXIT_INVD 13
853/** 14 Guest software attempted to execute INVLPG. */
854#define VMX_EXIT_INVLPG 14
855/** 15 Guest software attempted to execute RDPMC. */
856#define VMX_EXIT_RDPMC 15
857/** 16 Guest software attempted to execute RDTSC. */
858#define VMX_EXIT_RDTSC 16
859/** 17 Guest software attempted to execute RSM in SMM. */
860#define VMX_EXIT_RSM 17
861/** 18 Guest software executed VMCALL. */
862#define VMX_EXIT_VMCALL 18
863/** 19 Guest software executed VMCLEAR. */
864#define VMX_EXIT_VMCLEAR 19
865/** 20 Guest software executed VMLAUNCH. */
866#define VMX_EXIT_VMLAUNCH 20
867/** 21 Guest software executed VMPTRLD. */
868#define VMX_EXIT_VMPTRLD 21
869/** 22 Guest software executed VMPTRST. */
870#define VMX_EXIT_VMPTRST 22
871/** 23 Guest software executed VMREAD. */
872#define VMX_EXIT_VMREAD 23
873/** 24 Guest software executed VMRESUME. */
874#define VMX_EXIT_VMRESUME 24
875/** 25 Guest software executed VMWRITE. */
876#define VMX_EXIT_VMWRITE 25
877/** 26 Guest software executed VMXOFF. */
878#define VMX_EXIT_VMXOFF 26
879/** 27 Guest software executed VMXON. */
880#define VMX_EXIT_VMXON 27
881/** 28 Control-register accesses. */
882#define VMX_EXIT_MOV_CRX 28
883/** 29 Debug-register accesses. */
884#define VMX_EXIT_MOV_DRX 29
885/** 30 I/O instruction. */
886#define VMX_EXIT_IO_INSTR 30
887/** 31 RDMSR. Guest software attempted to execute RDMSR. */
888#define VMX_EXIT_RDMSR 31
889/** 32 WRMSR. Guest software attempted to execute WRMSR. */
890#define VMX_EXIT_WRMSR 32
891/** 33 VM-entry failure due to invalid guest state. */
892#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
893/** 34 VM-entry failure due to MSR loading. */
894#define VMX_EXIT_ERR_MSR_LOAD 34
895/** 36 Guest software executed MWAIT. */
896#define VMX_EXIT_MWAIT 36
897/** 37 VM exit due to monitor trap flag. */
898#define VMX_EXIT_MTF 37
899/** 39 Guest software attempted to execute MONITOR. */
900#define VMX_EXIT_MONITOR 39
901/** 40 Guest software attempted to execute PAUSE. */
902#define VMX_EXIT_PAUSE 40
903/** 41 VM-entry failure due to machine-check. */
904#define VMX_EXIT_ERR_MACHINE_CHECK 41
905/** 43 TPR below threshold. Guest software executed MOV to CR8. */
906#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
907/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
908#define VMX_EXIT_APIC_ACCESS 44
909/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
910#define VMX_EXIT_XDTR_ACCESS 46
911/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
912#define VMX_EXIT_TR_ACCESS 47
913/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
914#define VMX_EXIT_EPT_VIOLATION 48
915/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
916#define VMX_EXIT_EPT_MISCONFIG 49
917/** 50 INVEPT. Guest software attempted to execute INVEPT. */
918#define VMX_EXIT_INVEPT 50
919/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
920#define VMX_EXIT_RDTSCP 51
921/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
922#define VMX_EXIT_PREEMPT_TIMER 52
923/** 53 INVVPID. Guest software attempted to execute INVVPID. */
924#define VMX_EXIT_INVVPID 53
925/** 54 WBINVD. Guest software attempted to execute WBINVD. */
926#define VMX_EXIT_WBINVD 54
927/** 55 XSETBV. Guest software attempted to execute XSETBV. */
928#define VMX_EXIT_XSETBV 55
929/** 57 RDRAND. Guest software attempted to execute RDRAND. */
930#define VMX_EXIT_RDRAND 57
931/** 58 INVPCID. Guest software attempted to execute INVPCID. */
932#define VMX_EXIT_INVPCID 58
933/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
934#define VMX_EXIT_VMFUNC 59
935/** The maximum exit value (inclusive). */
936#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
937/** @} */
938
939
940/** @name VM Instruction Errors
941 * @{
942 */
943/** VMCALL executed in VMX root operation. */
944#define VMX_ERROR_VMCALL 1
945/** VMCLEAR with invalid physical address. */
946#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
947/** VMCLEAR with VMXON pointer. */
948#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
949/** VMLAUNCH with non-clear VMCS. */
950#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
951/** VMRESUME with non-launched VMCS. */
952#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
953/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
954#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
955/** VM-entry with invalid control field(s). */
956#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
957/** VM-entry with invalid host-state field(s). */
958#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
959/** VMPTRLD with invalid physical address. */
960#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
961/** VMPTRLD with VMXON pointer. */
962#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
963/** VMPTRLD with incorrect VMCS revision identifier. */
964#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
965/** VMREAD/VMWRITE from/to unsupported VMCS component. */
966#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
967#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
968/** VMWRITE to read-only VMCS component. */
969#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
970/** VMXON executed in VMX root operation. */
971#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
972/** VM entry with invalid executive-VMCS pointer. */
973#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
974/** VM entry with non-launched executive VMCS. */
975#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
976/** VM entry with executive-VMCS pointer not VMXON pointer. */
977#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
978/** VMCALL with non-clear VMCS. */
979#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
980/** VMCALL with invalid VM-exit control fields. */
981#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
982/** VMCALL with incorrect MSEG revision identifier. */
983#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
984/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
985#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
986/** VMCALL with invalid SMM-monitor features. */
987#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
988/** VM entry with invalid VM-execution control fields in executive VMCS. */
989#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
990/** VM entry with events blocked by MOV SS. */
991#define VMX_ERROR_VMENTRY_MOV_SS 26
992/** Invalid operand to INVEPT/INVVPID. */
993#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
994
995/** @} */
996
997
998/** @name VMX MSRs - Basic VMX information.
999 * @{
1000 */
1001/** VMCS revision identifier used by the processor. */
1002#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
1003/** Size of the VMCS. */
1004#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0xFFF)
1005/** Width of physical address used for the VMCS.
1006 * 0 -> limited to the available amount of physical ram
1007 * 1 -> within the first 4 GB
1008 */
1009#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1010/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1011#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1012/** Memory type that must be used for the VMCS. */
1013#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1014/** Whether the processor provides additional information for exits due to INS/OUTS. */
1015#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1016/** @} */
1017
1018
1019/** @name VMX MSRs - Misc VMX info.
1020 * @{
1021 */
1022/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1023#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1024/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1025#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1026/** Activity states supported by the implementation. */
1027#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1028/** Number of CR3 target values supported by the processor. (0-256) */
1029#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1030/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
1031#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1032/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1033#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1034/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1035#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1036/** Whether VMWRITE can be used to write VM-exit information fields. */
1037#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1038/** MSEG revision identifier used by the processor. */
1039#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1040/** @} */
1041
1042
1043/** @name VMX MSRs - VMCS enumeration field info
1044 * @{
1045 */
1046/** Highest field index. */
1047#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1048/** @} */
1049
1050
1051/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1052 * @{
1053 */
1054#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1055#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
1056#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
1057#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
1058#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
1059#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
1060#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
1061#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
1062#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1063#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
1064#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
1065#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
1066#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1067#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
1068#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
1069#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
1070#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
1071#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1072#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1073#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1074#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1075#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1076#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1077#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1078#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1079
1080/** @} */
1081
1082/** @name Extended Page Table Pointer (EPTP)
1083 * @{
1084 */
1085/** Uncachable EPT paging structure memory type. */
1086#define VMX_EPT_MEMTYPE_UC 0
1087/** Write-back EPT paging structure memory type. */
1088#define VMX_EPT_MEMTYPE_WB 6
1089/** Shift value to get the EPT page walk length (bits 5-3) */
1090#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1091/** Mask value to get the EPT page walk length (bits 5-3) */
1092#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1093/** Default EPT page-walk length (1 less than the actual EPT page-walk
1094 * length) */
1095#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1096/** @} */
1097
1098
1099/** @name VMCS field encoding - 16 bits guest fields
1100 * @{
1101 */
1102#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
1103#define VMX_VMCS16_GUEST_FIELD_ES 0x800
1104#define VMX_VMCS16_GUEST_FIELD_CS 0x802
1105#define VMX_VMCS16_GUEST_FIELD_SS 0x804
1106#define VMX_VMCS16_GUEST_FIELD_DS 0x806
1107#define VMX_VMCS16_GUEST_FIELD_FS 0x808
1108#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
1109#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
1110#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
1111/** @} */
1112
1113/** @name VMCS field encoding - 16 bits host fields
1114 * @{
1115 */
1116#define VMX_VMCS16_HOST_FIELD_ES 0xC00
1117#define VMX_VMCS16_HOST_FIELD_CS 0xC02
1118#define VMX_VMCS16_HOST_FIELD_SS 0xC04
1119#define VMX_VMCS16_HOST_FIELD_DS 0xC06
1120#define VMX_VMCS16_HOST_FIELD_FS 0xC08
1121#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
1122#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
1123/** @} */
1124
1125/** @name VMCS field encoding - 64 bits host fields
1126 * @{
1127 */
1128#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
1129#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
1130#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
1131#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
1132#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
1133#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
1134/** @} */
1135
1136
1137/** @name VMCS field encoding - 64 Bits control fields
1138 * @{
1139 */
1140#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1141#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1142#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1143#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1144
1145/* Optional */
1146#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1147#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1148
1149#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1150#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1151#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1152#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1153
1154#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1155#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1156
1157#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1158#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1159
1160#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1161#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1162
1163/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1164#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1165#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1166
1167/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1168#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1169#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1170
1171/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1172#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1173#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1174
1175/** Extended page table pointer. */
1176#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1177#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1178
1179/** Extended page table pointer lists. */
1180#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1181#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1182
1183/** VM-exit guest phyiscal address. */
1184#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1185#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1186/** @} */
1187
1188
1189/** @name VMCS field encoding - 64 Bits guest fields
1190 * @{
1191 */
1192#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1193#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1194#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
1195#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
1196#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1197#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1198#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1199#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1200#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
1201#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
1202#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1203#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1204#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1205#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1206#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1207#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1208#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1209#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1210/** @} */
1211
1212
1213/** @name VMCS field encoding - 32 Bits control fields
1214 * @{
1215 */
1216#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1217#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1218#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1219#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1220#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1221#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1222#define VMX_VMCS32_CTRL_EXIT 0x400C
1223#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1224#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1225#define VMX_VMCS32_CTRL_ENTRY 0x4012
1226#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1227#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1228#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1229#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1230#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1231#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1232/** @} */
1233
1234
1235/** @name VMX_VMCS_CTRL_PIN_EXEC
1236 * @{
1237 */
1238/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1239#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1240/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1241#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1242/** Virtual NMIs. */
1243#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1244/** Activate VMX preemption timer. */
1245#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1246/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1247/** @} */
1248
1249/** @name VMX_VMCS_CTRL_PROC_EXEC
1250 * @{
1251 */
1252/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
1253#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1254/** Use timestamp counter offset. */
1255#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1256/** VM Exit when executing the HLT instruction. */
1257#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1258/** VM Exit when executing the INVLPG instruction. */
1259#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1260/** VM Exit when executing the MWAIT instruction. */
1261#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1262/** VM Exit when executing the RDPMC instruction. */
1263#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1264/** VM Exit when executing the RDTSC/RDTSCP instruction. */
1265#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1266/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1267#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1268/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1269#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1270/** VM Exit on CR8 loads. */
1271#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1272/** VM Exit on CR8 stores. */
1273#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1274/** Use TPR shadow. */
1275#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1276/** VM Exit when virtual nmi blocking is disabled. */
1277#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1278/** VM Exit when executing a MOV DRx instruction. */
1279#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1280/** VM Exit when executing IO instructions. */
1281#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1282/** Use IO bitmaps. */
1283#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1284/** Monitor trap flag. */
1285#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1286/** Use MSR bitmaps. */
1287#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1288/** VM Exit when executing the MONITOR instruction. */
1289#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1290/** VM Exit when executing the PAUSE instruction. */
1291#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1292/** Determines whether the secondary processor based VM-execution controls are used. */
1293#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1294/** @} */
1295
1296/** @name VMX_VMCS_CTRL_PROC_EXEC2
1297 * @{
1298 */
1299/** Virtualize APIC access. */
1300#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1301/** EPT supported/enabled. */
1302#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1303/** Descriptor table instructions cause VM-exits. */
1304#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1305/** RDTSCP supported/enabled. */
1306#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1307/** Virtualize x2APIC mode. */
1308#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1309/** VPID supported/enabled. */
1310#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1311/** VM Exit when executing the WBINVD instruction. */
1312#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1313/** Unrestricted guest execution. */
1314#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1315/** A specified nr of pause loops cause a VM-exit. */
1316#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1317/** VM Exit when executing RDRAND instructions. */
1318#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1319/** Enables INVPCID instructions. */
1320#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1321/** Enables VMFUNC instructions. */
1322#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1323/** @} */
1324
1325
1326/** @name VMX_VMCS_CTRL_ENTRY
1327 * @{
1328 */
1329/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1330#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1331/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1332#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1333/** In SMM mode after VM-entry. */
1334#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1335/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1336#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1337/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
1338#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1339/** Whether the guest IA32_PAT MSR is loaded on VM entry. */
1340#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1341/** Whether the guest IA32_EFER MSR is loaded on VM entry. */
1342#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1343/** @} */
1344
1345
1346/** @name VMX_VMCS_CTRL_EXIT
1347 * @{
1348 */
1349/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1350#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1351/** Return to long mode after a VM-exit. */
1352#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1353/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
1354#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1355/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1356#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1357/** Whether the guest IA32_PAT MSR is saved on VM exit. */
1358#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1359/** Whether the host IA32_PAT MSR is loaded on VM exit. */
1360#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1361/** Whether the guest IA32_EFER MSR is saved on VM exit. */
1362#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1363/** Whether the host IA32_EFER MSR is loaded on VM exit. */
1364#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1365/** Whether the value of the VMX preemption timer is saved on every VM exit. */
1366#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1367/** @} */
1368
1369
1370/** @name VMX_VMCS_CTRL_VMFUNC
1371 * @{
1372 */
1373/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1374#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1375/** @} */
1376
1377
1378/** @name VMCS field encoding - 32 Bits read-only fields
1379 * @{
1380 */
1381#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1382#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1383#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1384#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1385#define VMX_VMCS32_RO_IDT_INFO 0x4408
1386#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1387#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1388#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1389/** @} */
1390
1391/** @name VMX_VMCS32_RO_EXIT_REASON
1392 * @{
1393 */
1394#define VMX_EXIT_REASON_BASIC(a) (a & 0xffff)
1395/** @} */
1396
1397/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1398 * @{
1399 */
1400#define VMX_ENTRY_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
1401#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1402#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1403/** @} */
1404
1405
1406/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1407 * @{
1408 */
1409#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
1410#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1411#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1412#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1413#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1414#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
1415#ifdef VBOX_WITH_OLD_VTX_CODE
1416# define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
1417#endif
1418#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1419#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) (a & RT_BIT(31))
1420/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1421#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
1422/** @} */
1423
1424/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1425 * @{
1426 */
1427#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1428#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1429#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1430#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4 /**< int xx */
1431#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DB_XCPT 5 /**< Why are we getting this one?? */
1432#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1433/** @} */
1434
1435/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1436 * @{
1437 */
1438#define VMX_IDT_VECTORING_INFO_VECTOR(a) (a & 0xff)
1439#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1440#define VMX_IDT_VECTORING_INFO_TYPE(a) ((a >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1441#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1442#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1443#define VMX_IDT_VECTORING_INFO_VALID(a) (a & RT_BIT(31))
1444#define VMX_ENTRY_INTR_INFO_FROM_EXIT_IDT_INFO(a) (a & ~RT_BIT(12))
1445/** @} */
1446
1447/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1448 * @{
1449 */
1450#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1451#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1452#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1453#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1454#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1455#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1456/** @} */
1457
1458
1459/** @name VMCS field encoding - 32 Bits guest state fields
1460 * @{
1461 */
1462#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1463#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1464#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1465#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1466#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1467#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1468#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1469#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1470#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1471#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1472#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1473#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1474#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1475#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1476#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1477#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1478#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1479#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1480#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1481#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1482#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
1483#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1484/** @} */
1485
1486
1487/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1488 * @{
1489 */
1490/** The logical processor is active. */
1491#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1492/** The logical processor is inactive, because executed a HLT instruction. */
1493#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1494/** The logical processor is inactive, because of a triple fault or other serious error. */
1495#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1496/** The logical processor is inactive, because it's waiting for a startup-IPI */
1497#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1498/** @} */
1499
1500
1501/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1502 * @{
1503 */
1504#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1505#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1506#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1507#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1508/** @} */
1509
1510
1511/** @name VMCS field encoding - 32 Bits host state fields
1512 * @{
1513 */
1514#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1515/** @} */
1516
1517/** @name Natural width control fields
1518 * @{
1519 */
1520#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1521#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1522#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1523#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1524#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1525#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1526#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1527#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1528/** @} */
1529
1530
1531/** @name Natural width read-only data fields
1532 * @{
1533 */
1534#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1535#define VMX_VMCS_RO_IO_RCX 0x6402
1536#define VMX_VMCS_RO_IO_RSX 0x6404
1537#define VMX_VMCS_RO_IO_RDI 0x6406
1538#define VMX_VMCS_RO_IO_RIP 0x6408
1539#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1540/** @} */
1541
1542
1543/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1544 * @{
1545 */
1546/** 0-2: Debug register number */
1547#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1548/** 3: Reserved; cleared to 0. */
1549#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1550/** 4: Direction of move (0 = write, 1 = read) */
1551#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1552/** 5-7: Reserved; cleared to 0. */
1553#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1554/** 8-11: General purpose register number. */
1555#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1556/** Rest: reserved. */
1557/** @} */
1558
1559/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1560 * @{
1561 */
1562#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1563#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1564/** @} */
1565
1566
1567
1568/** @name CRx accesses
1569 * @{
1570 */
1571/** 0-3: Control register number (0 for CLTS & LMSW) */
1572#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1573/** 4-5: Access type. */
1574#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1575/** 6: LMSW operand type */
1576#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1577/** 7: Reserved; cleared to 0. */
1578#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1579/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1580#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1581/** 12-15: Reserved; cleared to 0. */
1582#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1583/** 16-31: LMSW source data (else 0). */
1584#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1585/** Rest: reserved. */
1586/** @} */
1587
1588/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1589 * @{
1590 */
1591#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1592#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1593#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1594#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1595/** @} */
1596
1597/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1598 * @{
1599 */
1600#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1601#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1602/** Task switch caused by a call instruction. */
1603#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1604/** Task switch caused by an iret instruction. */
1605#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1606/** Task switch caused by a jmp instruction. */
1607#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1608/** Task switch caused by an interrupt gate. */
1609#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1610/** @} */
1611
1612
1613/** @name VMX_EXIT_EPT_VIOLATION
1614 * @{
1615 */
1616/** Set if the violation was caused by a data read. */
1617#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1618/** Set if the violation was caused by a data write. */
1619#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1620/** Set if the violation was caused by an insruction fetch. */
1621#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1622/** AND of the present bit of all EPT structures. */
1623#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1624/** AND of the write bit of all EPT structures. */
1625#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1626/** AND of the execute bit of all EPT structures. */
1627#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1628/** Set if the guest linear address field contains the faulting address. */
1629#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1630/** If bit 7 is one: (reserved otherwise)
1631 * 1 - violation due to physical address access.
1632 * 0 - violation caused by page walk or access/dirty bit updates
1633 */
1634#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1635/** @} */
1636
1637
1638/** @name VMX_EXIT_PORT_IO
1639 * @{
1640 */
1641/** 0-2: IO operation width. */
1642#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1643/** 3: IO operation direction. */
1644#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1645/** 4: String IO operation (INS / OUTS). */
1646#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1647/** 5: Repeated IO operation. */
1648#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1649/** 6: Operand encoding. */
1650#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1651/** 16-31: IO Port (0-0xffff). */
1652#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1653/* Rest reserved. */
1654/** @} */
1655
1656/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1657 * @{
1658 */
1659#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1660#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1661/** @} */
1662
1663
1664/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1665 * @{
1666 */
1667#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1668#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1669/** @} */
1670
1671/** @name VMX_EXIT_APIC_ACCESS
1672 * @{
1673 */
1674/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1675#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1676/** 12-15: Access type. */
1677#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000)
1678/* Rest reserved. */
1679/** @} */
1680
1681
1682/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1683 * @{
1684 */
1685/** Linear read access. */
1686#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1687/** Linear write access. */
1688#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1689/** Linear instruction fetch access. */
1690#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1691/** Linear read/write access during event delivery. */
1692#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1693/** Physical read/write access during event delivery. */
1694#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1695/** Physical access for an instruction fetch or during instruction execution. */
1696#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1697/** @} */
1698
1699/** @} */
1700
1701/** @name VMCS field encoding - Natural width guest state fields
1702 * @{
1703 */
1704#define VMX_VMCS_GUEST_CR0 0x6800
1705#define VMX_VMCS_GUEST_CR3 0x6802
1706#define VMX_VMCS_GUEST_CR4 0x6804
1707#define VMX_VMCS_GUEST_ES_BASE 0x6806
1708#define VMX_VMCS_GUEST_CS_BASE 0x6808
1709#define VMX_VMCS_GUEST_SS_BASE 0x680A
1710#define VMX_VMCS_GUEST_DS_BASE 0x680C
1711#define VMX_VMCS_GUEST_FS_BASE 0x680E
1712#define VMX_VMCS_GUEST_GS_BASE 0x6810
1713#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1714#define VMX_VMCS_GUEST_TR_BASE 0x6814
1715#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1716#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1717#define VMX_VMCS_GUEST_DR7 0x681A
1718#define VMX_VMCS_GUEST_RSP 0x681C
1719#define VMX_VMCS_GUEST_RIP 0x681E
1720#define VMX_VMCS_GUEST_RFLAGS 0x6820
1721#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1722#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1723#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1724/** @} */
1725
1726
1727/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1728 * @{
1729 */
1730/** Hardware breakpoint 0 was met. */
1731#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1732/** Hardware breakpoint 1 was met. */
1733#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1734/** Hardware breakpoint 2 was met. */
1735#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1736/** Hardware breakpoint 3 was met. */
1737#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1738/** At least one data or IO breakpoint was hit. */
1739#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1740/** A debug exception would have been triggered by single-step execution mode. */
1741#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1742/** Bits 4-11, 13 and 15-63 are reserved. */
1743
1744/** @} */
1745
1746/** @name VMCS field encoding - Natural width host state fields
1747 * @{
1748 */
1749#define VMX_VMCS_HOST_CR0 0x6C00
1750#define VMX_VMCS_HOST_CR3 0x6C02
1751#define VMX_VMCS_HOST_CR4 0x6C04
1752#define VMX_VMCS_HOST_FS_BASE 0x6C06
1753#define VMX_VMCS_HOST_GS_BASE 0x6C08
1754#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1755#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1756#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1757#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1758#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1759#define VMX_VMCS_HOST_RSP 0x6C14
1760#define VMX_VMCS_HOST_RIP 0x6C16
1761/** @} */
1762
1763/** @} */
1764
1765
1766/** @defgroup grp_vmx_asm vmx assembly helpers
1767 * @ingroup grp_vmx
1768 * @{
1769 */
1770
1771/**
1772 * Restores some host-state fields that need not be done on every VM-exit.
1773 *
1774 * @returns VBox status code.
1775 * @param fRestoreHostFlags Flags of which host registers needs to be
1776 * restored.
1777 * @param pRestoreHost Pointer to the host-restore structure.
1778 */
1779DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1780
1781
1782/**
1783 * Dispatches an NMI to the host.
1784 */
1785DECLASM(int) VMXDispatchHostNmi(void);
1786
1787
1788/**
1789 * Executes VMXON
1790 *
1791 * @returns VBox status code
1792 * @param pVMXOn Physical address of VMXON structure
1793 */
1794#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1795DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1796#else
1797DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1798{
1799# if RT_INLINE_ASM_GNU_STYLE
1800 int rc = VINF_SUCCESS;
1801 __asm__ __volatile__ (
1802 "push %3 \n\t"
1803 "push %2 \n\t"
1804 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1805 "ja 2f \n\t"
1806 "je 1f \n\t"
1807 "movl $"RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1808 "jmp 2f \n\t"
1809 "1: \n\t"
1810 "movl $"RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1811 "2: \n\t"
1812 "add $8, %%esp \n\t"
1813 :"=rm"(rc)
1814 :"0"(VINF_SUCCESS),
1815 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1816 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1817 :"memory"
1818 );
1819 return rc;
1820
1821# elif VMX_USE_MSC_INTRINSICS
1822 unsigned char rcMsc = __vmx_on(&pVMXOn);
1823 if (RT_LIKELY(rcMsc == 0))
1824 return VINF_SUCCESS;
1825 return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
1826
1827# else
1828 int rc = VINF_SUCCESS;
1829 __asm
1830 {
1831 push dword ptr [pVMXOn+4]
1832 push dword ptr [pVMXOn]
1833 _emit 0xF3
1834 _emit 0x0F
1835 _emit 0xC7
1836 _emit 0x34
1837 _emit 0x24 /* VMXON [esp] */
1838 jnc vmxon_good
1839 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1840 jmp the_end
1841
1842vmxon_good:
1843 jnz the_end
1844 mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1845the_end:
1846 add esp, 8
1847 }
1848# endif
1849}
1850#endif
1851
1852
1853/**
1854 * Executes VMXOFF
1855 */
1856#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1857DECLASM(void) VMXDisable(void);
1858#else
1859DECLINLINE(void) VMXDisable(void)
1860{
1861# if RT_INLINE_ASM_GNU_STYLE
1862 __asm__ __volatile__ (
1863 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1864 );
1865
1866# elif VMX_USE_MSC_INTRINSICS
1867 __vmx_off();
1868
1869# else
1870 __asm
1871 {
1872 _emit 0x0F
1873 _emit 0x01
1874 _emit 0xC4 /* VMXOFF */
1875 }
1876# endif
1877}
1878#endif
1879
1880
1881/**
1882 * Executes VMCLEAR
1883 *
1884 * @returns VBox status code
1885 * @param pVMCS Physical address of VM control structure
1886 */
1887#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1888DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1889#else
1890DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1891{
1892# if RT_INLINE_ASM_GNU_STYLE
1893 int rc = VINF_SUCCESS;
1894 __asm__ __volatile__ (
1895 "push %3 \n\t"
1896 "push %2 \n\t"
1897 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1898 "jnc 1f \n\t"
1899 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1900 "1: \n\t"
1901 "add $8, %%esp \n\t"
1902 :"=rm"(rc)
1903 :"0"(VINF_SUCCESS),
1904 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1905 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1906 :"memory"
1907 );
1908 return rc;
1909
1910# elif VMX_USE_MSC_INTRINSICS
1911 unsigned char rcMsc = __vmx_vmclear(&pVMCS);
1912 if (RT_LIKELY(rcMsc == 0))
1913 return VINF_SUCCESS;
1914 return VERR_VMX_INVALID_VMCS_PTR;
1915
1916# else
1917 int rc = VINF_SUCCESS;
1918 __asm
1919 {
1920 push dword ptr [pVMCS+4]
1921 push dword ptr [pVMCS]
1922 _emit 0x66
1923 _emit 0x0F
1924 _emit 0xC7
1925 _emit 0x34
1926 _emit 0x24 /* VMCLEAR [esp] */
1927 jnc success
1928 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1929success:
1930 add esp, 8
1931 }
1932 return rc;
1933# endif
1934}
1935#endif
1936
1937
1938/**
1939 * Executes VMPTRLD
1940 *
1941 * @returns VBox status code
1942 * @param pVMCS Physical address of VMCS structure
1943 */
1944#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1945DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1946#else
1947DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1948{
1949# if RT_INLINE_ASM_GNU_STYLE
1950 int rc = VINF_SUCCESS;
1951 __asm__ __volatile__ (
1952 "push %3 \n\t"
1953 "push %2 \n\t"
1954 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1955 "jnc 1f \n\t"
1956 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1957 "1: \n\t"
1958 "add $8, %%esp \n\t"
1959 :"=rm"(rc)
1960 :"0"(VINF_SUCCESS),
1961 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1962 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1963 );
1964 return rc;
1965
1966# elif VMX_USE_MSC_INTRINSICS
1967 unsigned char rcMsc = __vmx_vmptrld(&pVMCS);
1968 if (RT_LIKELY(rcMsc == 0))
1969 return VINF_SUCCESS;
1970 return VERR_VMX_INVALID_VMCS_PTR;
1971
1972# else
1973 int rc = VINF_SUCCESS;
1974 __asm
1975 {
1976 push dword ptr [pVMCS+4]
1977 push dword ptr [pVMCS]
1978 _emit 0x0F
1979 _emit 0xC7
1980 _emit 0x34
1981 _emit 0x24 /* VMPTRLD [esp] */
1982 jnc success
1983 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1984
1985success:
1986 add esp, 8
1987 }
1988 return rc;
1989# endif
1990}
1991#endif
1992
1993/**
1994 * Executes VMPTRST
1995 *
1996 * @returns VBox status code
1997 * @param pVMCS Address that will receive the current pointer
1998 */
1999DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
2000
2001/**
2002 * Executes VMWRITE
2003 *
2004 * @returns VBox status code
2005 * @retval VINF_SUCCESS
2006 * @retval VERR_VMX_INVALID_VMCS_PTR
2007 * @retval VERR_VMX_INVALID_VMCS_FIELD
2008 *
2009 * @param idxField VMCS index
2010 * @param u32Val 32 bits value
2011 *
2012 * @remarks The values of the two status codes can be ORed together, the result
2013 * will be VERR_VMX_INVALID_VMCS_PTR.
2014 */
2015#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2016DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2017#else
2018DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2019{
2020# if RT_INLINE_ASM_GNU_STYLE
2021 int rc = VINF_SUCCESS;
2022 __asm__ __volatile__ (
2023 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2024 "ja 2f \n\t"
2025 "je 1f \n\t"
2026 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2027 "jmp 2f \n\t"
2028 "1: \n\t"
2029 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2030 "2: \n\t"
2031 :"=rm"(rc)
2032 :"0"(VINF_SUCCESS),
2033 "a"(idxField),
2034 "d"(u32Val)
2035 );
2036 return rc;
2037
2038# elif VMX_USE_MSC_INTRINSICS
2039 unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2040 if (RT_LIKELY(rcMsc == 0))
2041 return VINF_SUCCESS;
2042 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2043
2044#else
2045 int rc = VINF_SUCCESS;
2046 __asm
2047 {
2048 push dword ptr [u32Val]
2049 mov eax, [idxField]
2050 _emit 0x0F
2051 _emit 0x79
2052 _emit 0x04
2053 _emit 0x24 /* VMWRITE eax, [esp] */
2054 jnc valid_vmcs
2055 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2056 jmp the_end
2057
2058valid_vmcs:
2059 jnz the_end
2060 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2061the_end:
2062 add esp, 4
2063 }
2064 return rc;
2065# endif
2066}
2067#endif
2068
2069/**
2070 * Executes VMWRITE
2071 *
2072 * @returns VBox status code
2073 * @retval VINF_SUCCESS
2074 * @retval VERR_VMX_INVALID_VMCS_PTR
2075 * @retval VERR_VMX_INVALID_VMCS_FIELD
2076 *
2077 * @param idxField VMCS index
2078 * @param u64Val 16, 32 or 64 bits value
2079 *
2080 * @remarks The values of the two status codes can be ORed together, the result
2081 * will be VERR_VMX_INVALID_VMCS_PTR.
2082 */
2083#if !defined(RT_ARCH_X86) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2084# if !VMX_USE_MSC_INTRINSICS || ARCH_BITS != 64
2085DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2086# else /* VMX_USE_MSC_INTRINSICS */
2087DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2088{
2089 unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2090 if (RT_LIKELY(rcMsc == 0))
2091 return VINF_SUCCESS;
2092 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2093}
2094# endif /* VMX_USE_MSC_INTRINSICS */
2095#else
2096# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2097VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2098#endif
2099
2100#ifdef VBOX_WITH_OLD_VTX_CODE
2101# if ARCH_BITS == 64
2102# define VMXWriteVmcs VMXWriteVmcs64
2103# else
2104# define VMXWriteVmcs VMXWriteVmcs32
2105# endif
2106#else /* !VBOX_WITH_OLD_VTX_CODE */
2107# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2108# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
2109 VMXWriteVmcs64(idxField, uVal) \
2110 : VMXWriteVmcs32(idxField, uVal)
2111# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
2112 VMXWriteVmcs64(idxField, u64Val) \
2113 : VMXWriteVmcs32(idxField, u64Val)
2114# elif ARCH_BITS == 32
2115# define VMXWriteVmcsHstN VMXWriteVmcs32
2116# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2117# else /* ARCH_BITS == 64 */
2118# define VMXWriteVmcsHstN VMXWriteVmcs64
2119# define VMXWriteVmcsGstN VMXWriteVmcs64
2120# endif
2121#endif /* !VBOX_WITH_OLD_VTX_CODE */
2122
2123
2124/**
2125 * Invalidate a page using invept
2126 * @returns VBox status code
2127 * @param enmFlush Type of flush
2128 * @param pDescriptor Descriptor
2129 */
2130DECLASM(int) VMXR0InvEPT(VMX_FLUSH_EPT enmFlush, uint64_t *pDescriptor);
2131
2132/**
2133 * Invalidate a page using invvpid
2134 * @returns VBox status code
2135 * @param enmFlush Type of flush
2136 * @param pDescriptor Descriptor
2137 */
2138DECLASM(int) VMXR0InvVPID(VMX_FLUSH_VPID enmFlush, uint64_t *pDescriptor);
2139
2140/**
2141 * Executes VMREAD
2142 *
2143 * @returns VBox status code
2144 * @retval VINF_SUCCESS
2145 * @retval VERR_VMX_INVALID_VMCS_PTR
2146 * @retval VERR_VMX_INVALID_VMCS_FIELD
2147 *
2148 * @param idxField VMCS index
2149 * @param pData Ptr to store VM field value
2150 *
2151 * @remarks The values of the two status codes can be ORed together, the result
2152 * will be VERR_VMX_INVALID_VMCS_PTR.
2153 */
2154#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2155DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2156#else
2157DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2158{
2159# if RT_INLINE_ASM_GNU_STYLE
2160 int rc = VINF_SUCCESS;
2161 __asm__ __volatile__ (
2162 "movl $"RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2163 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2164 "ja 2f \n\t"
2165 "je 1f \n\t"
2166 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2167 "jmp 2f \n\t"
2168 "1: \n\t"
2169 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2170 "2: \n\t"
2171 :"=&r"(rc),
2172 "=d"(*pData)
2173 :"a"(idxField),
2174 "d"(0)
2175 );
2176 return rc;
2177
2178# elif VMX_USE_MSC_INTRINSICS
2179 unsigned char rcMsc;
2180# if ARCH_BITS == 32
2181 rcMsc = __vmx_vmread(idxField, pData);
2182# else
2183 uint64_t u64Tmp;
2184 rcMsc = __vmx_vmread(idxField, &u64Tmp);
2185 *pData = (uint32_t)u64Tmp;
2186# endif
2187 if (RT_LIKELY(rcMsc == 0))
2188 return VINF_SUCCESS;
2189 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2190
2191#else
2192 int rc = VINF_SUCCESS;
2193 __asm
2194 {
2195 sub esp, 4
2196 mov dword ptr [esp], 0
2197 mov eax, [idxField]
2198 _emit 0x0F
2199 _emit 0x78
2200 _emit 0x04
2201 _emit 0x24 /* VMREAD eax, [esp] */
2202 mov edx, pData
2203 pop dword ptr [edx]
2204 jnc valid_vmcs
2205 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2206 jmp the_end
2207
2208valid_vmcs:
2209 jnz the_end
2210 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2211the_end:
2212 }
2213 return rc;
2214# endif
2215}
2216#endif
2217
2218/**
2219 * Executes VMREAD
2220 *
2221 * @returns VBox status code
2222 * @retval VINF_SUCCESS
2223 * @retval VERR_VMX_INVALID_VMCS_PTR
2224 * @retval VERR_VMX_INVALID_VMCS_FIELD
2225 *
2226 * @param idxField VMCS index
2227 * @param pData Ptr to store VM field value
2228 *
2229 * @remarks The values of the two status codes can be ORed together, the result
2230 * will be VERR_VMX_INVALID_VMCS_PTR.
2231 */
2232#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2233DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2234#else
2235DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2236{
2237# if VMX_USE_MSC_INTRINSICS
2238 unsigned char rcMsc;
2239# if ARCH_BITS == 32
2240 size_t uLow;
2241 size_t uHigh;
2242 rcMsc = __vmx_vmread(idxField, &uLow);
2243 rcMsc |= __vmx_vmread(idxField + 1, &uHigh);
2244 *pData = RT_MAKE_U64(uLow, uHigh);
2245# else
2246 rcMsc = __vmx_vmread(idxField, pData);
2247# endif
2248 if (RT_LIKELY(rcMsc == 0))
2249 return VINF_SUCCESS;
2250 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2251
2252# elif ARCH_BITS == 32
2253 int rc;
2254 uint32_t val_hi, val;
2255 rc = VMXReadVmcs32(idxField, &val);
2256 rc |= VMXReadVmcs32(idxField + 1, &val_hi);
2257 AssertRC(rc);
2258 *pData = RT_MAKE_U64(val, val_hi);
2259 return rc;
2260
2261# else
2262# error "Shouldn't be here..."
2263# endif
2264}
2265#endif
2266
2267#ifdef VBOX_WITH_OLD_VTX_CODE
2268# if ARCH_BITS == 64
2269# define VMXReadVmcsField VMXReadVmcs64
2270# else
2271# define VMXReadVmcsField VMXReadVmcs32
2272# endif
2273#endif
2274
2275/**
2276 * Gets the last instruction error value from the current VMCS
2277 *
2278 * @returns error value
2279 */
2280DECLINLINE(uint32_t) VMXGetLastError(void)
2281{
2282#if ARCH_BITS == 64
2283 uint64_t uLastError = 0;
2284 int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2285 AssertRC(rc);
2286 return (uint32_t)uLastError;
2287
2288#else /* 32-bit host: */
2289 uint32_t uLastError = 0;
2290 int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2291 AssertRC(rc);
2292 return uLastError;
2293#endif
2294}
2295
2296#ifdef IN_RING0
2297VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2298VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2299#endif /* IN_RING0 */
2300
2301/** @} */
2302
2303#endif
2304
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