VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 50675

Last change on this file since 50675 was 50675, checked in by vboxsync, 11 years ago

include/VBox/vmm: C++11 fixes (thanks Genode Labs)
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1/** @file
2 * HM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2013 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vmx_h
27#define ___VBox_vmm_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/x86.h>
32#include <iprt/assert.h>
33
34/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35 when targeting AMD64. */
36#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37# include <intrin.h>
38/* We always want them as intrinsics, no functions. */
39# pragma intrinsic(__vmx_on)
40# pragma intrinsic(__vmx_off)
41# pragma intrinsic(__vmx_vmclear)
42# pragma intrinsic(__vmx_vmptrld)
43# pragma intrinsic(__vmx_vmread)
44# pragma intrinsic(__vmx_vmwrite)
45# define VMX_USE_MSC_INTRINSICS 1
46#else
47# define VMX_USE_MSC_INTRINSICS 0
48#endif
49
50
51/** @defgroup grp_vmx vmx Types and Definitions
52 * @ingroup grp_hm
53 * @{
54 */
55
56/** @def HMVMXCPU_GST_SET_UPDATED
57 * Sets a guest-state-updated flag.
58 *
59 * @param pVCpu Pointer to the VMCPU.
60 * @param fFlag The flag to set.
61 */
62#define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
63
64/** @def HMVMXCPU_GST_IS_SET
65 * Checks if all the flags in the specified guest-state-updated set is pending.
66 *
67 * @param pVCpu Pointer to the VMCPU.
68 * @param fFlag The flag to check.
69 */
70#define HMVMXCPU_GST_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
71
72/** @def HMVMXCPU_GST_IS_UPDATED
73 * Checks if one or more of the flags in the specified guest-state-updated set
74 * is updated.
75 *
76 * @param pVCpu Pointer to the VMCPU.
77 * @param fFlags The flags to check for.
78 */
79#define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
80
81/** @def HMVMXCPU_GST_RESET_TO
82 * Resets the guest-state-updated flags to the specified value.
83 *
84 * @param pVCpu Pointer to the VMCPU.
85 * @param fFlags The new value.
86 */
87#define HMVMXCPU_GST_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlags)))
88
89/** @def HMVMXCPU_GST_VALUE
90 * Returns the current guest-state-updated flags value.
91 *
92 * @param pVCpu Pointer to the VMCPU.
93 */
94#define HMVMXCPU_GST_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState))
95
96/** @name Host-state restoration flags.
97 * @{
98 */
99/* If you change these values don't forget to update the assembly defines as well! */
100#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
101#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
102#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
103#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
104#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
105#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
106#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
107#define VMX_RESTORE_HOST_REQUIRED RT_BIT(7)
108/** @} */
109
110/**
111 * Host-state restoration structure.
112 * This holds host-state fields that require manual restoration.
113 * Assembly version found in hm_vmx.mac (should be automatically verified).
114 */
115typedef struct VMXRESTOREHOST
116{
117 RTSEL uHostSelDS; /* 0x00 */
118 RTSEL uHostSelES; /* 0x02 */
119 RTSEL uHostSelFS; /* 0x04 */
120 RTSEL uHostSelGS; /* 0x06 */
121 RTSEL uHostSelTR; /* 0x08 */
122 uint8_t abPadding0[4];
123 X86XDTR64 HostGdtr; /**< 0x0e - should be aligned by it's 64-bit member. */
124 uint8_t abPadding1[6];
125 X86XDTR64 HostIdtr; /**< 0x1e - should be aligned by it's 64-bit member. */
126 uint64_t uHostFSBase; /* 0x28 */
127 uint64_t uHostGSBase; /* 0x30 */
128} VMXRESTOREHOST;
129/** Pointer to VMXRESTOREHOST. */
130typedef VMXRESTOREHOST *PVMXRESTOREHOST;
131AssertCompileSize(X86XDTR64, 10);
132AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
133AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
134AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
135AssertCompileSize(VMXRESTOREHOST, 56);
136
137/** @name Host-state MSR lazy-restoration flags.
138 * @{
139 */
140/** The host MSRs have been saved. */
141#define VMX_RESTORE_HOST_MSR_SAVED_HOST RT_BIT(0)
142/** The guest MSRs are loaded and in effect. */
143#define VMX_RESTORE_HOST_MSR_LOADED_GUEST RT_BIT(1)
144/** @} */
145
146/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
147 * UFC = Unsupported Feature Combination.
148 * @{
149 */
150/** Unsupported pin-based VM-execution controls combo. */
151#define VMX_UFC_CTRL_PIN_EXEC 0
152/** Unsupported processor-based VM-execution controls combo. */
153#define VMX_UFC_CTRL_PROC_EXEC 1
154/** Unsupported pin-based VM-execution controls combo. */
155#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 2
156/** Unsupported VM-entry controls combo. */
157#define VMX_UFC_CTRL_ENTRY 3
158/** Unsupported VM-exit controls combo. */
159#define VMX_UFC_CTRL_EXIT 4
160/** MSR storage capacity of the VMCS autoload/store area is not sufficient
161 * for storing host MSRs. */
162#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 5
163/** MSR storage capacity of the VMCS autoload/store area is not sufficient
164 * for storing guest MSRs. */
165#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 6
166/** Invalid VMCS size. */
167#define VMX_UFC_INVALID_VMCS_SIZE 7
168/** Unsupported secondary processor-based VM-execution controls combo. */
169#define VMX_UFC_CTRL_PROC_EXEC2 8
170/** Invalid unrestricted-guest execution controls combo. */
171#define VMX_UFC_INVALID_UX_COMBO 9
172/** @} */
173
174/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
175 * IGS = Invalid Guest State.
176 * @{
177 */
178/** An error occurred while checking invalid-guest-state. */
179#define VMX_IGS_ERROR 0
180/** The invalid guest-state checks did not find any reason why. */
181#define VMX_IGS_REASON_NOT_FOUND 1
182/** CR0 fixed1 bits invalid. */
183#define VMX_IGS_CR0_FIXED1 2
184/** CR0 fixed0 bits invalid. */
185#define VMX_IGS_CR0_FIXED0 3
186/** CR0.PE and CR0.PE invalid VT-x/host combination. */
187#define VMX_IGS_CR0_PG_PE_COMBO 4
188/** CR4 fixed1 bits invalid. */
189#define VMX_IGS_CR4_FIXED1 5
190/** CR4 fixed0 bits invalid. */
191#define VMX_IGS_CR4_FIXED0 6
192/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
193 * VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
194#define VMX_IGS_DEBUGCTL_MSR_RESERVED 7
195/** CR0.PG not set for long-mode when not using unrestricted guest. */
196#define VMX_IGS_CR0_PG_LONGMODE 8
197/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
198#define VMX_IGS_CR4_PAE_LONGMODE 9
199/** CR4.PCIDE set for 32-bit guest. */
200#define VMX_IGS_CR4_PCIDE 10
201/** VMCS' DR7 reserved bits not set to 0. */
202#define VMX_IGS_DR7_RESERVED 11
203/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
204#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12
205/** VMCS' EFER MSR reserved bits not set to 0. */
206#define VMX_IGS_EFER_MSR_RESERVED 13
207/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
208#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14
209/** VMCS' EFER MSR.LMA does not match CR0.PG of the guest when not using
210 * unrestricted guest. */
211#define VMX_IGS_EFER_LMA_PG_MISMATCH 15
212/** CS.Attr.P bit invalid. */
213#define VMX_IGS_CS_ATTR_P_INVALID 16
214/** CS.Attr reserved bits not set to 0. */
215#define VMX_IGS_CS_ATTR_RESERVED 17
216/** CS.Attr.G bit invalid. */
217#define VMX_IGS_CS_ATTR_G_INVALID 18
218/** CS is unusable. */
219#define VMX_IGS_CS_ATTR_UNUSABLE 19
220/** CS and SS DPL unequal. */
221#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20
222/** CS and SS DPL mismatch. */
223#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21
224/** CS Attr.Type invalid. */
225#define VMX_IGS_CS_ATTR_TYPE_INVALID 22
226/** CS and SS RPL unequal. */
227#define VMX_IGS_SS_CS_RPL_UNEQUAL 23
228/** SS.Attr.DPL and SS RPL unequal. */
229#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24
230/** SS.Attr.DPL invalid for segment type. */
231#define VMX_IGS_SS_ATTR_DPL_INVALID 25
232/** SS.Attr.Type invalid. */
233#define VMX_IGS_SS_ATTR_TYPE_INVALID 26
234/** SS.Attr.P bit invalid. */
235#define VMX_IGS_SS_ATTR_P_INVALID 27
236/** SS.Attr reserved bits not set to 0. */
237#define VMX_IGS_SS_ATTR_RESERVED 28
238/** SS.Attr.G bit invalid. */
239#define VMX_IGS_SS_ATTR_G_INVALID 29
240/** DS.Attr.A bit invalid. */
241#define VMX_IGS_DS_ATTR_A_INVALID 30
242/** DS.Attr.P bit invalid. */
243#define VMX_IGS_DS_ATTR_P_INVALID 31
244/** DS.Attr.DPL and DS RPL unequal. */
245#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32
246/** DS.Attr reserved bits not set to 0. */
247#define VMX_IGS_DS_ATTR_RESERVED 33
248/** DS.Attr.G bit invalid. */
249#define VMX_IGS_DS_ATTR_G_INVALID 34
250/** DS.Attr.Type invalid. */
251#define VMX_IGS_DS_ATTR_TYPE_INVALID 35
252/** ES.Attr.A bit invalid. */
253#define VMX_IGS_ES_ATTR_A_INVALID 36
254/** ES.Attr.P bit invalid. */
255#define VMX_IGS_ES_ATTR_P_INVALID 37
256/** ES.Attr.DPL and DS RPL unequal. */
257#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38
258/** ES.Attr reserved bits not set to 0. */
259#define VMX_IGS_ES_ATTR_RESERVED 39
260/** ES.Attr.G bit invalid. */
261#define VMX_IGS_ES_ATTR_G_INVALID 40
262/** ES.Attr.Type invalid. */
263#define VMX_IGS_ES_ATTR_TYPE_INVALID 41
264/** FS.Attr.A bit invalid. */
265#define VMX_IGS_FS_ATTR_A_INVALID 42
266/** FS.Attr.P bit invalid. */
267#define VMX_IGS_FS_ATTR_P_INVALID 43
268/** FS.Attr.DPL and DS RPL unequal. */
269#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44
270/** FS.Attr reserved bits not set to 0. */
271#define VMX_IGS_FS_ATTR_RESERVED 45
272/** FS.Attr.G bit invalid. */
273#define VMX_IGS_FS_ATTR_G_INVALID 46
274/** FS.Attr.Type invalid. */
275#define VMX_IGS_FS_ATTR_TYPE_INVALID 47
276/** GS.Attr.A bit invalid. */
277#define VMX_IGS_GS_ATTR_A_INVALID 48
278/** GS.Attr.P bit invalid. */
279#define VMX_IGS_GS_ATTR_P_INVALID 49
280/** GS.Attr.DPL and DS RPL unequal. */
281#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 50
282/** GS.Attr reserved bits not set to 0. */
283#define VMX_IGS_GS_ATTR_RESERVED 51
284/** GS.Attr.G bit invalid. */
285#define VMX_IGS_GS_ATTR_G_INVALID 52
286/** GS.Attr.Type invalid. */
287#define VMX_IGS_GS_ATTR_TYPE_INVALID 53
288/** V86 mode CS.Base invalid. */
289#define VMX_IGS_V86_CS_BASE_INVALID 54
290/** V86 mode CS.Limit invalid. */
291#define VMX_IGS_V86_CS_LIMIT_INVALID 55
292/** V86 mode CS.Attr invalid. */
293#define VMX_IGS_V86_CS_ATTR_INVALID 56
294/** V86 mode SS.Base invalid. */
295#define VMX_IGS_V86_SS_BASE_INVALID 57
296/** V86 mode SS.Limit invalid. */
297#define VMX_IGS_V86_SS_LIMIT_INVALID 59
298/** V86 mode SS.Attr invalid. */
299#define VMX_IGS_V86_SS_ATTR_INVALID 59
300/** V86 mode DS.Base invalid. */
301#define VMX_IGS_V86_DS_BASE_INVALID 60
302/** V86 mode DS.Limit invalid. */
303#define VMX_IGS_V86_DS_LIMIT_INVALID 61
304/** V86 mode DS.Attr invalid. */
305#define VMX_IGS_V86_DS_ATTR_INVALID 62
306/** V86 mode ES.Base invalid. */
307#define VMX_IGS_V86_ES_BASE_INVALID 63
308/** V86 mode ES.Limit invalid. */
309#define VMX_IGS_V86_ES_LIMIT_INVALID 64
310/** V86 mode ES.Attr invalid. */
311#define VMX_IGS_V86_ES_ATTR_INVALID 65
312/** V86 mode FS.Base invalid. */
313#define VMX_IGS_V86_FS_BASE_INVALID 66
314/** V86 mode FS.Limit invalid. */
315#define VMX_IGS_V86_FS_LIMIT_INVALID 67
316/** V86 mode FS.Attr invalid. */
317#define VMX_IGS_V86_FS_ATTR_INVALID 68
318/** V86 mode GS.Base invalid. */
319#define VMX_IGS_V86_GS_BASE_INVALID 69
320/** V86 mode GS.Limit invalid. */
321#define VMX_IGS_V86_GS_LIMIT_INVALID 70
322/** V86 mode GS.Attr invalid. */
323#define VMX_IGS_V86_GS_ATTR_INVALID 71
324/** Longmode CS.Base invalid. */
325#define VMX_IGS_LONGMODE_CS_BASE_INVALID 72
326/** Longmode SS.Base invalid. */
327#define VMX_IGS_LONGMODE_SS_BASE_INVALID 73
328/** Longmode DS.Base invalid. */
329#define VMX_IGS_LONGMODE_DS_BASE_INVALID 74
330/** Longmode ES.Base invalid. */
331#define VMX_IGS_LONGMODE_ES_BASE_INVALID 75
332/** SYSENTER ESP is not canonical. */
333#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76
334/** SYSENTER EIP is not canonical. */
335#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77
336/** PAT MSR invalid. */
337#define VMX_IGS_PAT_MSR_INVALID 78
338/** PAT MSR reserved bits not set to 0. */
339#define VMX_IGS_PAT_MSR_RESERVED 79
340/** GDTR.Base is not canonical. */
341#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80
342/** IDTR.Base is not canonical. */
343#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81
344/** GDTR.Limit invalid. */
345#define VMX_IGS_GDTR_LIMIT_INVALID 82
346/** IDTR.Limit invalid. */
347#define VMX_IGS_IDTR_LIMIT_INVALID 83
348/** Longmode RIP is invalid. */
349#define VMX_IGS_LONGMODE_RIP_INVALID 84
350/** RFLAGS reserved bits not set to 0. */
351#define VMX_IGS_RFLAGS_RESERVED 85
352/** RFLAGS RA1 reserved bits not set to 1. */
353#define VMX_IGS_RFLAGS_RESERVED1 86
354/** RFLAGS.VM (V86 mode) invalid. */
355#define VMX_IGS_RFLAGS_VM_INVALID 87
356/** RFLAGS.IF invalid. */
357#define VMX_IGS_RFLAGS_IF_INVALID 88
358/** Activity state invalid. */
359#define VMX_IGS_ACTIVITY_STATE_INVALID 89
360/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
361#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90
362/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
363#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91
364/** Activity state SIPI WAIT invalid. */
365#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92
366/** Interruptibility state reserved bits not set to 0. */
367#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93
368/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
369#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94
370/** Interruptibility state block-by-STI invalid for EFLAGS. */
371#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95
372/** Interruptibility state invalid while trying to deliver external
373 * interrupt. */
374#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96
375/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
376 * NMI. */
377#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97
378/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
379#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98
380/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
381#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99
382/** Interruptibilty state block-by-STI (maybe) invalid when trying to deliver
383 * an NMI. */
384#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100
385/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
386 * active. */
387#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101
388/** Pending debug exceptions reserved bits not set to 0. */
389#define VMX_IGS_PENDING_DEBUG_RESERVED 102
390/** Longmode pending debug exceptions reserved bits not set to 0. */
391#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103
392/** Pending debug exceptions.BS bit is not set when it should be. */
393#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104
394/** Pending debug exceptions.BS bit is not clear when it should be. */
395#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105
396/** VMCS link pointer reserved bits not set to 0. */
397#define VMX_IGS_VMCS_LINK_PTR_RESERVED 106
398/** TR cannot index into LDT, TI bit MBZ. */
399#define VMX_IGS_TR_TI_INVALID 107
400/** LDTR cannot index into LDT. TI bit MBZ. */
401#define VMX_IGS_LDTR_TI_INVALID 108
402/** TR.Base is not canonical. */
403#define VMX_IGS_TR_BASE_NOT_CANONICAL 109
404/** FS.Base is not canonical. */
405#define VMX_IGS_FS_BASE_NOT_CANONICAL 110
406/** GS.Base is not canonical. */
407#define VMX_IGS_GS_BASE_NOT_CANONICAL 111
408/** LDTR.Base is not canonical. */
409#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 112
410/** TR is unusable. */
411#define VMX_IGS_TR_ATTR_UNUSABLE 113
412/** TR.Attr.S bit invalid. */
413#define VMX_IGS_TR_ATTR_S_INVALID 114
414/** TR is not present. */
415#define VMX_IGS_TR_ATTR_P_INVALID 115
416/** TR.Attr reserved bits not set to 0. */
417#define VMX_IGS_TR_ATTR_RESERVED 116
418/** TR.Attr.G bit invalid. */
419#define VMX_IGS_TR_ATTR_G_INVALID 117
420/** Longmode TR.Attr.Type invalid. */
421#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 118
422/** TR.Attr.Type invalid. */
423#define VMX_IGS_TR_ATTR_TYPE_INVALID 119
424/** CS.Attr.S invalid. */
425#define VMX_IGS_CS_ATTR_S_INVALID 120
426/** CS.Attr.DPL invalid. */
427#define VMX_IGS_CS_ATTR_DPL_INVALID 121
428/** PAE PDPTE reserved bits not set to 0. */
429#define VMX_IGS_PAE_PDPTE_RESERVED 123
430/** @} */
431
432/** @name VMX VMCS-Read cache indices.
433 * @{
434 */
435# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
436# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
437# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
438# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
439# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
440# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
441# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
442# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
443# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
444# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
445# define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
446# define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
447# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
448# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
449# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
450# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
451# define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
452# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
453/** @} */
454
455/** @name VMX EPT paging structures
456 * @{
457 */
458
459/**
460 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
461 */
462#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
463
464/**
465 * EPT Page Directory Pointer Entry. Bit view.
466 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
467 * this did cause trouble with one compiler/version).
468 */
469#pragma pack(1)
470typedef struct EPTPML4EBITS
471{
472 /** Present bit. */
473 uint64_t u1Present : 1;
474 /** Writable bit. */
475 uint64_t u1Write : 1;
476 /** Executable bit. */
477 uint64_t u1Execute : 1;
478 /** Reserved (must be 0). */
479 uint64_t u5Reserved : 5;
480 /** Available for software. */
481 uint64_t u4Available : 4;
482 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
483 uint64_t u40PhysAddr : 40;
484 /** Availabe for software. */
485 uint64_t u12Available : 12;
486} EPTPML4EBITS;
487#pragma pack()
488AssertCompileSize(EPTPML4EBITS, 8);
489
490/** Bits 12-51 - - EPT - Physical Page number of the next level. */
491#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
492/** The page shift to get the PML4 index. */
493#define EPT_PML4_SHIFT X86_PML4_SHIFT
494/** The PML4 index mask (apply to a shifted page address). */
495#define EPT_PML4_MASK X86_PML4_MASK
496
497/**
498 * EPT PML4E.
499 */
500#pragma pack(1)
501typedef union EPTPML4E
502{
503 /** Normal view. */
504 EPTPML4EBITS n;
505 /** Unsigned integer view. */
506 X86PGPAEUINT u;
507 /** 64 bit unsigned integer view. */
508 uint64_t au64[1];
509 /** 32 bit unsigned integer view. */
510 uint32_t au32[2];
511} EPTPML4E;
512#pragma pack()
513/** Pointer to a PML4 table entry. */
514typedef EPTPML4E *PEPTPML4E;
515/** Pointer to a const PML4 table entry. */
516typedef const EPTPML4E *PCEPTPML4E;
517AssertCompileSize(EPTPML4E, 8);
518
519/**
520 * EPT PML4 Table.
521 */
522#pragma pack(1)
523typedef struct EPTPML4
524{
525 EPTPML4E a[EPT_PG_ENTRIES];
526} EPTPML4;
527#pragma pack()
528/** Pointer to an EPT PML4 Table. */
529typedef EPTPML4 *PEPTPML4;
530/** Pointer to a const EPT PML4 Table. */
531typedef const EPTPML4 *PCEPTPML4;
532
533/**
534 * EPT Page Directory Pointer Entry. Bit view.
535 */
536#pragma pack(1)
537typedef struct EPTPDPTEBITS
538{
539 /** Present bit. */
540 uint64_t u1Present : 1;
541 /** Writable bit. */
542 uint64_t u1Write : 1;
543 /** Executable bit. */
544 uint64_t u1Execute : 1;
545 /** Reserved (must be 0). */
546 uint64_t u5Reserved : 5;
547 /** Available for software. */
548 uint64_t u4Available : 4;
549 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
550 uint64_t u40PhysAddr : 40;
551 /** Availabe for software. */
552 uint64_t u12Available : 12;
553} EPTPDPTEBITS;
554#pragma pack()
555AssertCompileSize(EPTPDPTEBITS, 8);
556
557/** Bits 12-51 - - EPT - Physical Page number of the next level. */
558#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
559/** The page shift to get the PDPT index. */
560#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
561/** The PDPT index mask (apply to a shifted page address). */
562#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
563
564/**
565 * EPT Page Directory Pointer.
566 */
567#pragma pack(1)
568typedef union EPTPDPTE
569{
570 /** Normal view. */
571 EPTPDPTEBITS n;
572 /** Unsigned integer view. */
573 X86PGPAEUINT u;
574 /** 64 bit unsigned integer view. */
575 uint64_t au64[1];
576 /** 32 bit unsigned integer view. */
577 uint32_t au32[2];
578} EPTPDPTE;
579#pragma pack()
580/** Pointer to an EPT Page Directory Pointer Entry. */
581typedef EPTPDPTE *PEPTPDPTE;
582/** Pointer to a const EPT Page Directory Pointer Entry. */
583typedef const EPTPDPTE *PCEPTPDPTE;
584AssertCompileSize(EPTPDPTE, 8);
585
586/**
587 * EPT Page Directory Pointer Table.
588 */
589#pragma pack(1)
590typedef struct EPTPDPT
591{
592 EPTPDPTE a[EPT_PG_ENTRIES];
593} EPTPDPT;
594#pragma pack()
595/** Pointer to an EPT Page Directory Pointer Table. */
596typedef EPTPDPT *PEPTPDPT;
597/** Pointer to a const EPT Page Directory Pointer Table. */
598typedef const EPTPDPT *PCEPTPDPT;
599
600
601/**
602 * EPT Page Directory Table Entry. Bit view.
603 */
604#pragma pack(1)
605typedef struct EPTPDEBITS
606{
607 /** Present bit. */
608 uint64_t u1Present : 1;
609 /** Writable bit. */
610 uint64_t u1Write : 1;
611 /** Executable bit. */
612 uint64_t u1Execute : 1;
613 /** Reserved (must be 0). */
614 uint64_t u4Reserved : 4;
615 /** Big page (must be 0 here). */
616 uint64_t u1Size : 1;
617 /** Available for software. */
618 uint64_t u4Available : 4;
619 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
620 uint64_t u40PhysAddr : 40;
621 /** Availabe for software. */
622 uint64_t u12Available : 12;
623} EPTPDEBITS;
624#pragma pack()
625AssertCompileSize(EPTPDEBITS, 8);
626
627/** Bits 12-51 - - EPT - Physical Page number of the next level. */
628#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
629/** The page shift to get the PD index. */
630#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
631/** The PD index mask (apply to a shifted page address). */
632#define EPT_PD_MASK X86_PD_PAE_MASK
633
634/**
635 * EPT 2MB Page Directory Table Entry. Bit view.
636 */
637#pragma pack(1)
638typedef struct EPTPDE2MBITS
639{
640 /** Present bit. */
641 uint64_t u1Present : 1;
642 /** Writable bit. */
643 uint64_t u1Write : 1;
644 /** Executable bit. */
645 uint64_t u1Execute : 1;
646 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
647 uint64_t u3EMT : 3;
648 /** Ignore PAT memory type */
649 uint64_t u1IgnorePAT : 1;
650 /** Big page (must be 1 here). */
651 uint64_t u1Size : 1;
652 /** Available for software. */
653 uint64_t u4Available : 4;
654 /** Reserved (must be 0). */
655 uint64_t u9Reserved : 9;
656 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
657 uint64_t u31PhysAddr : 31;
658 /** Availabe for software. */
659 uint64_t u12Available : 12;
660} EPTPDE2MBITS;
661#pragma pack()
662AssertCompileSize(EPTPDE2MBITS, 8);
663
664/** Bits 21-51 - - EPT - Physical Page number of the next level. */
665#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
666
667/**
668 * EPT Page Directory Table Entry.
669 */
670#pragma pack(1)
671typedef union EPTPDE
672{
673 /** Normal view. */
674 EPTPDEBITS n;
675 /** 2MB view (big). */
676 EPTPDE2MBITS b;
677 /** Unsigned integer view. */
678 X86PGPAEUINT u;
679 /** 64 bit unsigned integer view. */
680 uint64_t au64[1];
681 /** 32 bit unsigned integer view. */
682 uint32_t au32[2];
683} EPTPDE;
684#pragma pack()
685/** Pointer to an EPT Page Directory Table Entry. */
686typedef EPTPDE *PEPTPDE;
687/** Pointer to a const EPT Page Directory Table Entry. */
688typedef const EPTPDE *PCEPTPDE;
689AssertCompileSize(EPTPDE, 8);
690
691/**
692 * EPT Page Directory Table.
693 */
694#pragma pack(1)
695typedef struct EPTPD
696{
697 EPTPDE a[EPT_PG_ENTRIES];
698} EPTPD;
699#pragma pack()
700/** Pointer to an EPT Page Directory Table. */
701typedef EPTPD *PEPTPD;
702/** Pointer to a const EPT Page Directory Table. */
703typedef const EPTPD *PCEPTPD;
704
705
706/**
707 * EPT Page Table Entry. Bit view.
708 */
709#pragma pack(1)
710typedef struct EPTPTEBITS
711{
712 /** 0 - Present bit.
713 * @remark This is a convenience "misnomer". The bit actually indicates
714 * read access and the CPU will consider an entry with any of the
715 * first three bits set as present. Since all our valid entries
716 * will have this bit set, it can be used as a present indicator
717 * and allow some code sharing. */
718 uint64_t u1Present : 1;
719 /** 1 - Writable bit. */
720 uint64_t u1Write : 1;
721 /** 2 - Executable bit. */
722 uint64_t u1Execute : 1;
723 /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
724 uint64_t u3EMT : 3;
725 /** 6 - Ignore PAT memory type */
726 uint64_t u1IgnorePAT : 1;
727 /** 11:7 - Available for software. */
728 uint64_t u5Available : 5;
729 /** 51:12 - Physical address of page. Restricted by maximum physical
730 * address width of the cpu. */
731 uint64_t u40PhysAddr : 40;
732 /** 63:52 - Available for software. */
733 uint64_t u12Available : 12;
734} EPTPTEBITS;
735#pragma pack()
736AssertCompileSize(EPTPTEBITS, 8);
737
738/** Bits 12-51 - - EPT - Physical Page number of the next level. */
739#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
740/** The page shift to get the EPT PTE index. */
741#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
742/** The EPT PT index mask (apply to a shifted page address). */
743#define EPT_PT_MASK X86_PT_PAE_MASK
744
745/**
746 * EPT Page Table Entry.
747 */
748#pragma pack(1)
749typedef union EPTPTE
750{
751 /** Normal view. */
752 EPTPTEBITS n;
753 /** Unsigned integer view. */
754 X86PGPAEUINT u;
755 /** 64 bit unsigned integer view. */
756 uint64_t au64[1];
757 /** 32 bit unsigned integer view. */
758 uint32_t au32[2];
759} EPTPTE;
760#pragma pack()
761/** Pointer to an EPT Page Directory Table Entry. */
762typedef EPTPTE *PEPTPTE;
763/** Pointer to a const EPT Page Directory Table Entry. */
764typedef const EPTPTE *PCEPTPTE;
765AssertCompileSize(EPTPTE, 8);
766
767/**
768 * EPT Page Table.
769 */
770#pragma pack(1)
771typedef struct EPTPT
772{
773 EPTPTE a[EPT_PG_ENTRIES];
774} EPTPT;
775#pragma pack()
776/** Pointer to an extended page table. */
777typedef EPTPT *PEPTPT;
778/** Pointer to a const extended table. */
779typedef const EPTPT *PCEPTPT;
780
781/**
782 * VPID flush types.
783 */
784typedef enum
785{
786 /** Invalidate a specific page. */
787 VMX_FLUSH_VPID_INDIV_ADDR = 0,
788 /** Invalidate one context (specific VPID). */
789 VMX_FLUSH_VPID_SINGLE_CONTEXT = 1,
790 /** Invalidate all contexts (all VPIDs). */
791 VMX_FLUSH_VPID_ALL_CONTEXTS = 2,
792 /** Invalidate a single VPID context retaining global mappings. */
793 VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
794 /** Unsupported by VirtualBox. */
795 VMX_FLUSH_VPID_NOT_SUPPORTED = 0xbad,
796 /** Unsupported by CPU. */
797 VMX_FLUSH_VPID_NONE = 0xb00,
798 /** 32bit hackishness. */
799 VMX_FLUSH_VPID_32BIT_HACK = 0x7fffffff
800} VMX_FLUSH_VPID;
801
802/**
803 * EPT flush types.
804 */
805typedef enum
806{
807 /** Invalidate one context (specific EPT). */
808 VMX_FLUSH_EPT_SINGLE_CONTEXT = 1,
809 /* Invalidate all contexts (all EPTs) */
810 VMX_FLUSH_EPT_ALL_CONTEXTS = 2,
811 /** Unsupported by VirtualBox. */
812 VMX_FLUSH_EPT_NOT_SUPPORTED = 0xbad,
813 /** Unsupported by CPU. */
814 VMX_FLUSH_EPT_NONE = 0xb00,
815 /** 32bit hackishness. */
816 VMX_FLUSH_EPT_32BIT_HACK = 0x7fffffff
817} VMX_FLUSH_EPT;
818/** @} */
819
820/** @name MSR autoload/store elements
821 * @{
822 */
823#pragma pack(1)
824typedef struct
825{
826 uint32_t u32Msr;
827 uint32_t u32Reserved;
828 uint64_t u64Value;
829} VMXAUTOMSR;
830#pragma pack()
831/** Pointer to an MSR load/store element. */
832typedef VMXAUTOMSR *PVMXAUTOMSR;
833/** Pointer to a const MSR load/store element. */
834typedef const VMXAUTOMSR *PCVMXAUTOMSR;
835/** @} */
836
837/** @name VMX-capability qword
838 * @{
839 */
840#pragma pack(1)
841typedef union
842{
843 struct
844 {
845 /** Bits set here -must- be set in the correpsonding VM-execution controls. */
846 uint32_t disallowed0;
847 /** Bits cleared here -must- be cleared in the corresponding VM-execution
848 * controls. */
849 uint32_t allowed1;
850 } n;
851 uint64_t u;
852} VMX_CAPABILITY;
853#pragma pack()
854/** @} */
855
856/** @name VMX MSRs.
857 * @{
858 */
859typedef struct VMXMSRS
860{
861 uint64_t u64FeatureCtrl;
862 uint64_t u64BasicInfo;
863 VMX_CAPABILITY VmxPinCtls;
864 VMX_CAPABILITY VmxProcCtls;
865 VMX_CAPABILITY VmxProcCtls2;
866 VMX_CAPABILITY VmxExit;
867 VMX_CAPABILITY VmxEntry;
868 uint64_t u64Misc;
869 uint64_t u64Cr0Fixed0;
870 uint64_t u64Cr0Fixed1;
871 uint64_t u64Cr4Fixed0;
872 uint64_t u64Cr4Fixed1;
873 uint64_t u64VmcsEnum;
874 uint64_t u64Vmfunc;
875 uint64_t u64EptVpidCaps;
876} VMXMSRS;
877/** Pointer to a VMXMSRS struct. */
878typedef VMXMSRS *PVMXMSRS;
879/** @} */
880
881/** @name VMX EFLAGS reserved bits.
882 * @{
883 */
884/** And-mask for setting reserved bits to zero */
885#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
886/** Or-mask for setting reserved bits to 1 */
887#define VMX_EFLAGS_RESERVED_1 0x00000002
888/** @} */
889
890/** @name VMX Basic Exit Reasons.
891 * @{
892 */
893/** -1 Invalid exit code */
894#define VMX_EXIT_INVALID -1
895/** 0 Exception or non-maskable interrupt (NMI). */
896#define VMX_EXIT_XCPT_OR_NMI 0
897/** 1 External interrupt. */
898#define VMX_EXIT_EXT_INT 1
899/** 2 Triple fault. */
900#define VMX_EXIT_TRIPLE_FAULT 2
901/** 3 INIT signal. */
902#define VMX_EXIT_INIT_SIGNAL 3
903/** 4 Start-up IPI (SIPI). */
904#define VMX_EXIT_SIPI 4
905/** 5 I/O system-management interrupt (SMI). */
906#define VMX_EXIT_IO_SMI 5
907/** 6 Other SMI. */
908#define VMX_EXIT_SMI 6
909/** 7 Interrupt window exiting. */
910#define VMX_EXIT_INT_WINDOW 7
911/** 8 NMI window exiting. */
912#define VMX_EXIT_NMI_WINDOW 8
913/** 9 Task switch. */
914#define VMX_EXIT_TASK_SWITCH 9
915/** 10 Guest software attempted to execute CPUID. */
916#define VMX_EXIT_CPUID 10
917/** 10 Guest software attempted to execute GETSEC. */
918#define VMX_EXIT_GETSEC 11
919/** 12 Guest software attempted to execute HLT. */
920#define VMX_EXIT_HLT 12
921/** 13 Guest software attempted to execute INVD. */
922#define VMX_EXIT_INVD 13
923/** 14 Guest software attempted to execute INVLPG. */
924#define VMX_EXIT_INVLPG 14
925/** 15 Guest software attempted to execute RDPMC. */
926#define VMX_EXIT_RDPMC 15
927/** 16 Guest software attempted to execute RDTSC. */
928#define VMX_EXIT_RDTSC 16
929/** 17 Guest software attempted to execute RSM in SMM. */
930#define VMX_EXIT_RSM 17
931/** 18 Guest software executed VMCALL. */
932#define VMX_EXIT_VMCALL 18
933/** 19 Guest software executed VMCLEAR. */
934#define VMX_EXIT_VMCLEAR 19
935/** 20 Guest software executed VMLAUNCH. */
936#define VMX_EXIT_VMLAUNCH 20
937/** 21 Guest software executed VMPTRLD. */
938#define VMX_EXIT_VMPTRLD 21
939/** 22 Guest software executed VMPTRST. */
940#define VMX_EXIT_VMPTRST 22
941/** 23 Guest software executed VMREAD. */
942#define VMX_EXIT_VMREAD 23
943/** 24 Guest software executed VMRESUME. */
944#define VMX_EXIT_VMRESUME 24
945/** 25 Guest software executed VMWRITE. */
946#define VMX_EXIT_VMWRITE 25
947/** 26 Guest software executed VMXOFF. */
948#define VMX_EXIT_VMXOFF 26
949/** 27 Guest software executed VMXON. */
950#define VMX_EXIT_VMXON 27
951/** 28 Control-register accesses. */
952#define VMX_EXIT_MOV_CRX 28
953/** 29 Debug-register accesses. */
954#define VMX_EXIT_MOV_DRX 29
955/** 30 I/O instruction. */
956#define VMX_EXIT_IO_INSTR 30
957/** 31 RDMSR. Guest software attempted to execute RDMSR. */
958#define VMX_EXIT_RDMSR 31
959/** 32 WRMSR. Guest software attempted to execute WRMSR. */
960#define VMX_EXIT_WRMSR 32
961/** 33 VM-entry failure due to invalid guest state. */
962#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
963/** 34 VM-entry failure due to MSR loading. */
964#define VMX_EXIT_ERR_MSR_LOAD 34
965/** 36 Guest software executed MWAIT. */
966#define VMX_EXIT_MWAIT 36
967/** 37 VM exit due to monitor trap flag. */
968#define VMX_EXIT_MTF 37
969/** 39 Guest software attempted to execute MONITOR. */
970#define VMX_EXIT_MONITOR 39
971/** 40 Guest software attempted to execute PAUSE. */
972#define VMX_EXIT_PAUSE 40
973/** 41 VM-entry failure due to machine-check. */
974#define VMX_EXIT_ERR_MACHINE_CHECK 41
975/** 43 TPR below threshold. Guest software executed MOV to CR8. */
976#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
977/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
978#define VMX_EXIT_APIC_ACCESS 44
979/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
980#define VMX_EXIT_XDTR_ACCESS 46
981/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
982#define VMX_EXIT_TR_ACCESS 47
983/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
984#define VMX_EXIT_EPT_VIOLATION 48
985/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
986#define VMX_EXIT_EPT_MISCONFIG 49
987/** 50 INVEPT. Guest software attempted to execute INVEPT. */
988#define VMX_EXIT_INVEPT 50
989/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
990#define VMX_EXIT_RDTSCP 51
991/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
992#define VMX_EXIT_PREEMPT_TIMER 52
993/** 53 INVVPID. Guest software attempted to execute INVVPID. */
994#define VMX_EXIT_INVVPID 53
995/** 54 WBINVD. Guest software attempted to execute WBINVD. */
996#define VMX_EXIT_WBINVD 54
997/** 55 XSETBV. Guest software attempted to execute XSETBV. */
998#define VMX_EXIT_XSETBV 55
999/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1000#define VMX_EXIT_RDRAND 57
1001/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1002#define VMX_EXIT_INVPCID 58
1003/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1004#define VMX_EXIT_VMFUNC 59
1005/** The maximum exit value (inclusive). */
1006#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
1007/** @} */
1008
1009
1010/** @name VM Instruction Errors
1011 * @{
1012 */
1013/** VMCALL executed in VMX root operation. */
1014#define VMX_ERROR_VMCALL 1
1015/** VMCLEAR with invalid physical address. */
1016#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1017/** VMCLEAR with VMXON pointer. */
1018#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1019/** VMLAUNCH with non-clear VMCS. */
1020#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1021/** VMRESUME with non-launched VMCS. */
1022#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1023/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1024#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1025/** VM-entry with invalid control field(s). */
1026#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1027/** VM-entry with invalid host-state field(s). */
1028#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1029/** VMPTRLD with invalid physical address. */
1030#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1031/** VMPTRLD with VMXON pointer. */
1032#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1033/** VMPTRLD with incorrect VMCS revision identifier. */
1034#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1035/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1036#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1037#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1038/** VMWRITE to read-only VMCS component. */
1039#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1040/** VMXON executed in VMX root operation. */
1041#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1042/** VM entry with invalid executive-VMCS pointer. */
1043#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1044/** VM entry with non-launched executive VMCS. */
1045#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1046/** VM entry with executive-VMCS pointer not VMXON pointer. */
1047#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1048/** VMCALL with non-clear VMCS. */
1049#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1050/** VMCALL with invalid VM-exit control fields. */
1051#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1052/** VMCALL with incorrect MSEG revision identifier. */
1053#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1054/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1055#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1056/** VMCALL with invalid SMM-monitor features. */
1057#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1058/** VM entry with invalid VM-execution control fields in executive VMCS. */
1059#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1060/** VM entry with events blocked by MOV SS. */
1061#define VMX_ERROR_VMENTRY_MOV_SS 26
1062/** Invalid operand to INVEPT/INVVPID. */
1063#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1064
1065/** @} */
1066
1067
1068/** @name VMX MSRs - Basic VMX information.
1069 * @{
1070 */
1071/** VMCS revision identifier used by the processor. */
1072#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) ((a) & 0x7FFFFFFF)
1073/** Size of the VMCS. */
1074#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0x1FFF)
1075/** Width of physical address used for the VMCS.
1076 * 0 -> limited to the available amount of physical ram
1077 * 1 -> within the first 4 GB
1078 */
1079#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1080/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1081#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1082/** Memory type that must be used for the VMCS. */
1083#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1084/** Whether the processor provides additional information for exits due to INS/OUTS. */
1085#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1086/** @} */
1087
1088
1089/** @name VMX MSRs - Misc VMX info.
1090 * @{
1091 */
1092/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1093#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1094/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1095#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1096/** Activity states supported by the implementation. */
1097#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1098/** Number of CR3 target values supported by the processor. (0-256) */
1099#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1100/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
1101#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1102/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1103#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1104/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1105#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1106/** Whether VMWRITE can be used to write VM-exit information fields. */
1107#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1108/** MSEG revision identifier used by the processor. */
1109#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1110/** @} */
1111
1112
1113/** @name VMX MSRs - VMCS enumeration field info
1114 * @{
1115 */
1116/** Highest field index. */
1117#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1118/** @} */
1119
1120
1121/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1122 * @{
1123 */
1124#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1125#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
1126#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
1127#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
1128#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
1129#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
1130#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
1131#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
1132#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1133#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
1134#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
1135#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
1136#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1137#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
1138#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
1139#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
1140#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
1141#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1142#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1143#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1144#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1145#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1146#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1147#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1148#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1149
1150/** @} */
1151
1152/** @name Extended Page Table Pointer (EPTP)
1153 * @{
1154 */
1155/** Uncachable EPT paging structure memory type. */
1156#define VMX_EPT_MEMTYPE_UC 0
1157/** Write-back EPT paging structure memory type. */
1158#define VMX_EPT_MEMTYPE_WB 6
1159/** Shift value to get the EPT page walk length (bits 5-3) */
1160#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1161/** Mask value to get the EPT page walk length (bits 5-3) */
1162#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1163/** Default EPT page-walk length (1 less than the actual EPT page-walk
1164 * length) */
1165#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1166/** @} */
1167
1168
1169/** @name VMCS field encoding - 16 bits guest fields
1170 * @{
1171 */
1172#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
1173#define VMX_VMCS16_GUEST_FIELD_ES 0x800
1174#define VMX_VMCS16_GUEST_FIELD_CS 0x802
1175#define VMX_VMCS16_GUEST_FIELD_SS 0x804
1176#define VMX_VMCS16_GUEST_FIELD_DS 0x806
1177#define VMX_VMCS16_GUEST_FIELD_FS 0x808
1178#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
1179#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
1180#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
1181/** @} */
1182
1183/** @name VMCS field encoding - 16 bits host fields
1184 * @{
1185 */
1186#define VMX_VMCS16_HOST_FIELD_ES 0xC00
1187#define VMX_VMCS16_HOST_FIELD_CS 0xC02
1188#define VMX_VMCS16_HOST_FIELD_SS 0xC04
1189#define VMX_VMCS16_HOST_FIELD_DS 0xC06
1190#define VMX_VMCS16_HOST_FIELD_FS 0xC08
1191#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
1192#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
1193/** @} */
1194
1195/** @name VMCS field encoding - 64 bits host fields
1196 * @{
1197 */
1198#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
1199#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
1200#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
1201#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
1202#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
1203#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
1204/** @} */
1205
1206
1207/** @name VMCS field encoding - 64 Bits control fields
1208 * @{
1209 */
1210#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1211#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1212#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1213#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1214
1215/* Optional */
1216#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1217#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1218
1219#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1220#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1221#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1222#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1223
1224#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1225#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1226
1227#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1228#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1229
1230#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1231#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1232
1233/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1234#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1235#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1236
1237/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1238#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1239#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1240
1241/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1242#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1243#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1244
1245/** Extended page table pointer. */
1246#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1247#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1248
1249/** Extended page table pointer lists. */
1250#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1251#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1252
1253/** VM-exit guest phyiscal address. */
1254#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1255#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1256/** @} */
1257
1258
1259/** @name VMCS field encoding - 64 Bits guest fields
1260 * @{
1261 */
1262#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1263#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1264#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
1265#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
1266#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1267#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1268#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1269#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1270#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
1271#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
1272#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1273#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1274#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1275#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1276#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1277#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1278#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1279#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1280/** @} */
1281
1282
1283/** @name VMCS field encoding - 32 Bits control fields
1284 * @{
1285 */
1286#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1287#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1288#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1289#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1290#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1291#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1292#define VMX_VMCS32_CTRL_EXIT 0x400C
1293#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1294#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1295#define VMX_VMCS32_CTRL_ENTRY 0x4012
1296#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1297#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1298#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1299#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1300#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1301#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1302/** @} */
1303
1304
1305/** @name VMX_VMCS_CTRL_PIN_EXEC
1306 * @{
1307 */
1308/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1309#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1310/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1311#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1312/** Virtual NMIs. */
1313#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1314/** Activate VMX preemption timer. */
1315#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1316/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1317/** @} */
1318
1319/** @name VMX_VMCS_CTRL_PROC_EXEC
1320 * @{
1321 */
1322/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
1323#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1324/** Use timestamp counter offset. */
1325#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1326/** VM Exit when executing the HLT instruction. */
1327#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1328/** VM Exit when executing the INVLPG instruction. */
1329#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1330/** VM Exit when executing the MWAIT instruction. */
1331#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1332/** VM Exit when executing the RDPMC instruction. */
1333#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1334/** VM Exit when executing the RDTSC/RDTSCP instruction. */
1335#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1336/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1337#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1338/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1339#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1340/** VM Exit on CR8 loads. */
1341#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1342/** VM Exit on CR8 stores. */
1343#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1344/** Use TPR shadow. */
1345#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1346/** VM Exit when virtual nmi blocking is disabled. */
1347#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1348/** VM Exit when executing a MOV DRx instruction. */
1349#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1350/** VM Exit when executing IO instructions. */
1351#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1352/** Use IO bitmaps. */
1353#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1354/** Monitor trap flag. */
1355#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1356/** Use MSR bitmaps. */
1357#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1358/** VM Exit when executing the MONITOR instruction. */
1359#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1360/** VM Exit when executing the PAUSE instruction. */
1361#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1362/** Determines whether the secondary processor based VM-execution controls are used. */
1363#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1364/** @} */
1365
1366/** @name VMX_VMCS_CTRL_PROC_EXEC2
1367 * @{
1368 */
1369/** Virtualize APIC access. */
1370#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1371/** EPT supported/enabled. */
1372#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1373/** Descriptor table instructions cause VM-exits. */
1374#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1375/** RDTSCP supported/enabled. */
1376#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1377/** Virtualize x2APIC mode. */
1378#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1379/** VPID supported/enabled. */
1380#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1381/** VM Exit when executing the WBINVD instruction. */
1382#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1383/** Unrestricted guest execution. */
1384#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1385/** A specified nr of pause loops cause a VM-exit. */
1386#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1387/** VM Exit when executing RDRAND instructions. */
1388#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1389/** Enables INVPCID instructions. */
1390#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1391/** Enables VMFUNC instructions. */
1392#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1393/** @} */
1394
1395
1396/** @name VMX_VMCS_CTRL_ENTRY
1397 * @{
1398 */
1399/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1400#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1401/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1402#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1403/** In SMM mode after VM-entry. */
1404#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1405/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1406#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1407/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
1408#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1409/** Whether the guest IA32_PAT MSR is loaded on VM entry. */
1410#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1411/** Whether the guest IA32_EFER MSR is loaded on VM entry. */
1412#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1413/** @} */
1414
1415
1416/** @name VMX_VMCS_CTRL_EXIT
1417 * @{
1418 */
1419/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1420#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1421/** Return to long mode after a VM-exit. */
1422#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1423/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
1424#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1425/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1426#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1427/** Whether the guest IA32_PAT MSR is saved on VM exit. */
1428#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1429/** Whether the host IA32_PAT MSR is loaded on VM exit. */
1430#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1431/** Whether the guest IA32_EFER MSR is saved on VM exit. */
1432#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1433/** Whether the host IA32_EFER MSR is loaded on VM exit. */
1434#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1435/** Whether the value of the VMX preemption timer is saved on every VM exit. */
1436#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1437/** @} */
1438
1439
1440/** @name VMX_VMCS_CTRL_VMFUNC
1441 * @{
1442 */
1443/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1444#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1445/** @} */
1446
1447
1448/** @name VMCS field encoding - 32 Bits read-only fields
1449 * @{
1450 */
1451#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1452#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1453#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1454#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1455#define VMX_VMCS32_RO_IDT_INFO 0x4408
1456#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1457#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1458#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1459/** @} */
1460
1461/** @name VMX_VMCS32_RO_EXIT_REASON
1462 * @{
1463 */
1464#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
1465/** @} */
1466
1467/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1468 * @{
1469 */
1470#define VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1471#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1472#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1473/** @} */
1474
1475
1476/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1477 * @{
1478 */
1479#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) ((a) & 0xff)
1480#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1481#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1482#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1483#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1484#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) ((a) & RT_BIT(12))
1485#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1486#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1487/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1488#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
1489/** @} */
1490
1491/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1492 * @{
1493 */
1494#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1495#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1496#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1497#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4
1498#define VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT 5
1499#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1500/** @} */
1501
1502/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1503 * @{
1504 */
1505#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
1506#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1507#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1508#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1509#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1510#define VMX_IDT_VECTORING_INFO_VALID(a) ((a) & RT_BIT(31))
1511#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
1512/** @} */
1513
1514/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1515 * @{
1516 */
1517#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1518#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1519#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1520#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1521#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1522#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1523/** @} */
1524
1525
1526/** @name VMCS field encoding - 32 Bits guest state fields
1527 * @{
1528 */
1529#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1530#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1531#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1532#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1533#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1534#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1535#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1536#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1537#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1538#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1539#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1540#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1541#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1542#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1543#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1544#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1545#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1546#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1547#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1548#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1549#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
1550#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1551/** @} */
1552
1553
1554/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1555 * @{
1556 */
1557/** The logical processor is active. */
1558#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1559/** The logical processor is inactive, because executed a HLT instruction. */
1560#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1561/** The logical processor is inactive, because of a triple fault or other serious error. */
1562#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1563/** The logical processor is inactive, because it's waiting for a startup-IPI */
1564#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1565/** @} */
1566
1567
1568/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1569 * @{
1570 */
1571#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1572#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1573#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1574#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1575/** @} */
1576
1577
1578/** @name VMCS field encoding - 32 Bits host state fields
1579 * @{
1580 */
1581#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1582/** @} */
1583
1584/** @name Natural width control fields
1585 * @{
1586 */
1587#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1588#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1589#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1590#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1591#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1592#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1593#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1594#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1595/** @} */
1596
1597
1598/** @name Natural width read-only data fields
1599 * @{
1600 */
1601#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1602#define VMX_VMCS_RO_IO_RCX 0x6402
1603#define VMX_VMCS_RO_IO_RSX 0x6404
1604#define VMX_VMCS_RO_IO_RDI 0x6406
1605#define VMX_VMCS_RO_IO_RIP 0x6408
1606#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1607/** @} */
1608
1609
1610/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1611 * @{
1612 */
1613/** 0-2: Debug register number */
1614#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) ((a) & 7)
1615/** 3: Reserved; cleared to 0. */
1616#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) (((a) >> 3) & 1)
1617/** 4: Direction of move (0 = write, 1 = read) */
1618#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) (((a) >> 4) & 1)
1619/** 5-7: Reserved; cleared to 0. */
1620#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) (((a) >> 5) & 7)
1621/** 8-11: General purpose register number. */
1622#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) (((a) >> 8) & 0xF)
1623/** Rest: reserved. */
1624/** @} */
1625
1626/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1627 * @{
1628 */
1629#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1630#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1631/** @} */
1632
1633
1634
1635/** @name CRx accesses
1636 * @{
1637 */
1638/** 0-3: Control register number (0 for CLTS & LMSW) */
1639#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) ((a) & 0xF)
1640/** 4-5: Access type. */
1641#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) (((a) >> 4) & 3)
1642/** 6: LMSW operand type */
1643#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) (((a) >> 6) & 1)
1644/** 7: Reserved; cleared to 0. */
1645#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) (((a) >> 7) & 1)
1646/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1647#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) (((a) >> 8) & 0xF)
1648/** 12-15: Reserved; cleared to 0. */
1649#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) (((a) >> 12) & 0xF)
1650/** 16-31: LMSW source data (else 0). */
1651#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) (((a) >> 16) & 0xFFFF)
1652/** Rest: reserved. */
1653/** @} */
1654
1655/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1656 * @{
1657 */
1658#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1659#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1660#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1661#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1662/** @} */
1663
1664/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1665 * @{
1666 */
1667#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
1668#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
1669/** Task switch caused by a call instruction. */
1670#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1671/** Task switch caused by an iret instruction. */
1672#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1673/** Task switch caused by a jmp instruction. */
1674#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1675/** Task switch caused by an interrupt gate. */
1676#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1677/** @} */
1678
1679
1680/** @name VMX_EXIT_EPT_VIOLATION
1681 * @{
1682 */
1683/** Set if the violation was caused by a data read. */
1684#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1685/** Set if the violation was caused by a data write. */
1686#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1687/** Set if the violation was caused by an insruction fetch. */
1688#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1689/** AND of the present bit of all EPT structures. */
1690#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1691/** AND of the write bit of all EPT structures. */
1692#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1693/** AND of the execute bit of all EPT structures. */
1694#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1695/** Set if the guest linear address field contains the faulting address. */
1696#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1697/** If bit 7 is one: (reserved otherwise)
1698 * 1 - violation due to physical address access.
1699 * 0 - violation caused by page walk or access/dirty bit updates
1700 */
1701#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1702/** @} */
1703
1704
1705/** @name VMX_EXIT_PORT_IO
1706 * @{
1707 */
1708/** 0-2: IO operation width. */
1709#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1710/** 3: IO operation direction. */
1711#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1712/** 4: String IO operation (INS / OUTS). */
1713#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1714/** 5: Repeated IO operation. */
1715#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1716/** 6: Operand encoding. */
1717#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1718/** 16-31: IO Port (0-0xffff). */
1719#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1720/* Rest reserved. */
1721/** @} */
1722
1723/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1724 * @{
1725 */
1726#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1727#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1728/** @} */
1729
1730
1731/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1732 * @{
1733 */
1734#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1735#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1736/** @} */
1737
1738/** @name VMX_EXIT_APIC_ACCESS
1739 * @{
1740 */
1741/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1742#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1743/** 12-15: Access type. */
1744#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000)
1745/* Rest reserved. */
1746/** @} */
1747
1748
1749/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1750 * @{
1751 */
1752/** Linear read access. */
1753#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1754/** Linear write access. */
1755#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1756/** Linear instruction fetch access. */
1757#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1758/** Linear read/write access during event delivery. */
1759#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1760/** Physical read/write access during event delivery. */
1761#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1762/** Physical access for an instruction fetch or during instruction execution. */
1763#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1764/** @} */
1765
1766/** @} */
1767
1768/** @name VMCS field encoding - Natural width guest state fields
1769 * @{
1770 */
1771#define VMX_VMCS_GUEST_CR0 0x6800
1772#define VMX_VMCS_GUEST_CR3 0x6802
1773#define VMX_VMCS_GUEST_CR4 0x6804
1774#define VMX_VMCS_GUEST_ES_BASE 0x6806
1775#define VMX_VMCS_GUEST_CS_BASE 0x6808
1776#define VMX_VMCS_GUEST_SS_BASE 0x680A
1777#define VMX_VMCS_GUEST_DS_BASE 0x680C
1778#define VMX_VMCS_GUEST_FS_BASE 0x680E
1779#define VMX_VMCS_GUEST_GS_BASE 0x6810
1780#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1781#define VMX_VMCS_GUEST_TR_BASE 0x6814
1782#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1783#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1784#define VMX_VMCS_GUEST_DR7 0x681A
1785#define VMX_VMCS_GUEST_RSP 0x681C
1786#define VMX_VMCS_GUEST_RIP 0x681E
1787#define VMX_VMCS_GUEST_RFLAGS 0x6820
1788#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1789#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1790#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1791/** @} */
1792
1793
1794/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1795 * @{
1796 */
1797/** Hardware breakpoint 0 was met. */
1798#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1799/** Hardware breakpoint 1 was met. */
1800#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1801/** Hardware breakpoint 2 was met. */
1802#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1803/** Hardware breakpoint 3 was met. */
1804#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1805/** At least one data or IO breakpoint was hit. */
1806#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1807/** A debug exception would have been triggered by single-step execution mode. */
1808#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1809/** Bits 4-11, 13 and 15-63 are reserved. */
1810
1811/** @} */
1812
1813/** @name VMCS field encoding - Natural width host state fields
1814 * @{
1815 */
1816#define VMX_VMCS_HOST_CR0 0x6C00
1817#define VMX_VMCS_HOST_CR3 0x6C02
1818#define VMX_VMCS_HOST_CR4 0x6C04
1819#define VMX_VMCS_HOST_FS_BASE 0x6C06
1820#define VMX_VMCS_HOST_GS_BASE 0x6C08
1821#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1822#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1823#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1824#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1825#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1826#define VMX_VMCS_HOST_RSP 0x6C14
1827#define VMX_VMCS_HOST_RIP 0x6C16
1828/** @} */
1829
1830/** @} */
1831
1832
1833/** @defgroup grp_vmx_asm vmx assembly helpers
1834 * @ingroup grp_vmx
1835 * @{
1836 */
1837
1838/**
1839 * Restores some host-state fields that need not be done on every VM-exit.
1840 *
1841 * @returns VBox status code.
1842 * @param fRestoreHostFlags Flags of which host registers needs to be
1843 * restored.
1844 * @param pRestoreHost Pointer to the host-restore structure.
1845 */
1846DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1847
1848
1849/**
1850 * Dispatches an NMI to the host.
1851 */
1852DECLASM(int) VMXDispatchHostNmi(void);
1853
1854
1855/**
1856 * Executes VMXON
1857 *
1858 * @returns VBox status code
1859 * @param pVMXOn Physical address of VMXON structure
1860 */
1861#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1862DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1863#else
1864DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1865{
1866# if RT_INLINE_ASM_GNU_STYLE
1867 int rc = VINF_SUCCESS;
1868 __asm__ __volatile__ (
1869 "push %3 \n\t"
1870 "push %2 \n\t"
1871 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1872 "ja 2f \n\t"
1873 "je 1f \n\t"
1874 "movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1875 "jmp 2f \n\t"
1876 "1: \n\t"
1877 "movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1878 "2: \n\t"
1879 "add $8, %%esp \n\t"
1880 :"=rm"(rc)
1881 :"0"(VINF_SUCCESS),
1882 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1883 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1884 :"memory"
1885 );
1886 return rc;
1887
1888# elif VMX_USE_MSC_INTRINSICS
1889 unsigned char rcMsc = __vmx_on(&pVMXOn);
1890 if (RT_LIKELY(rcMsc == 0))
1891 return VINF_SUCCESS;
1892 return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
1893
1894# else
1895 int rc = VINF_SUCCESS;
1896 __asm
1897 {
1898 push dword ptr [pVMXOn+4]
1899 push dword ptr [pVMXOn]
1900 _emit 0xF3
1901 _emit 0x0F
1902 _emit 0xC7
1903 _emit 0x34
1904 _emit 0x24 /* VMXON [esp] */
1905 jnc vmxon_good
1906 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1907 jmp the_end
1908
1909vmxon_good:
1910 jnz the_end
1911 mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1912the_end:
1913 add esp, 8
1914 }
1915 return rc;
1916# endif
1917}
1918#endif
1919
1920
1921/**
1922 * Executes VMXOFF
1923 */
1924#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1925DECLASM(void) VMXDisable(void);
1926#else
1927DECLINLINE(void) VMXDisable(void)
1928{
1929# if RT_INLINE_ASM_GNU_STYLE
1930 __asm__ __volatile__ (
1931 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1932 );
1933
1934# elif VMX_USE_MSC_INTRINSICS
1935 __vmx_off();
1936
1937# else
1938 __asm
1939 {
1940 _emit 0x0F
1941 _emit 0x01
1942 _emit 0xC4 /* VMXOFF */
1943 }
1944# endif
1945}
1946#endif
1947
1948
1949/**
1950 * Executes VMCLEAR
1951 *
1952 * @returns VBox status code
1953 * @param pVMCS Physical address of VM control structure
1954 */
1955#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1956DECLASM(int) VMXClearVmcs(RTHCPHYS pVMCS);
1957#else
1958DECLINLINE(int) VMXClearVmcs(RTHCPHYS pVMCS)
1959{
1960# if RT_INLINE_ASM_GNU_STYLE
1961 int rc = VINF_SUCCESS;
1962 __asm__ __volatile__ (
1963 "push %3 \n\t"
1964 "push %2 \n\t"
1965 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1966 "jnc 1f \n\t"
1967 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1968 "1: \n\t"
1969 "add $8, %%esp \n\t"
1970 :"=rm"(rc)
1971 :"0"(VINF_SUCCESS),
1972 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1973 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1974 :"memory"
1975 );
1976 return rc;
1977
1978# elif VMX_USE_MSC_INTRINSICS
1979 unsigned char rcMsc = __vmx_vmclear(&pVMCS);
1980 if (RT_LIKELY(rcMsc == 0))
1981 return VINF_SUCCESS;
1982 return VERR_VMX_INVALID_VMCS_PTR;
1983
1984# else
1985 int rc = VINF_SUCCESS;
1986 __asm
1987 {
1988 push dword ptr [pVMCS+4]
1989 push dword ptr [pVMCS]
1990 _emit 0x66
1991 _emit 0x0F
1992 _emit 0xC7
1993 _emit 0x34
1994 _emit 0x24 /* VMCLEAR [esp] */
1995 jnc success
1996 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1997success:
1998 add esp, 8
1999 }
2000 return rc;
2001# endif
2002}
2003#endif
2004
2005
2006/**
2007 * Executes VMPTRLD
2008 *
2009 * @returns VBox status code
2010 * @param pVMCS Physical address of VMCS structure
2011 */
2012#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2013DECLASM(int) VMXActivateVmcs(RTHCPHYS pVMCS);
2014#else
2015DECLINLINE(int) VMXActivateVmcs(RTHCPHYS pVMCS)
2016{
2017# if RT_INLINE_ASM_GNU_STYLE
2018 int rc = VINF_SUCCESS;
2019 __asm__ __volatile__ (
2020 "push %3 \n\t"
2021 "push %2 \n\t"
2022 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2023 "jnc 1f \n\t"
2024 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2025 "1: \n\t"
2026 "add $8, %%esp \n\t"
2027 :"=rm"(rc)
2028 :"0"(VINF_SUCCESS),
2029 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
2030 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
2031 );
2032 return rc;
2033
2034# elif VMX_USE_MSC_INTRINSICS
2035 unsigned char rcMsc = __vmx_vmptrld(&pVMCS);
2036 if (RT_LIKELY(rcMsc == 0))
2037 return VINF_SUCCESS;
2038 return VERR_VMX_INVALID_VMCS_PTR;
2039
2040# else
2041 int rc = VINF_SUCCESS;
2042 __asm
2043 {
2044 push dword ptr [pVMCS+4]
2045 push dword ptr [pVMCS]
2046 _emit 0x0F
2047 _emit 0xC7
2048 _emit 0x34
2049 _emit 0x24 /* VMPTRLD [esp] */
2050 jnc success
2051 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2052
2053success:
2054 add esp, 8
2055 }
2056 return rc;
2057# endif
2058}
2059#endif
2060
2061/**
2062 * Executes VMPTRST
2063 *
2064 * @returns VBox status code
2065 * @param pVMCS Address that will receive the current pointer
2066 */
2067DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pVMCS);
2068
2069/**
2070 * Executes VMWRITE
2071 *
2072 * @returns VBox status code
2073 * @retval VINF_SUCCESS
2074 * @retval VERR_VMX_INVALID_VMCS_PTR
2075 * @retval VERR_VMX_INVALID_VMCS_FIELD
2076 *
2077 * @param idxField VMCS index
2078 * @param u32Val 32 bits value
2079 *
2080 * @remarks The values of the two status codes can be ORed together, the result
2081 * will be VERR_VMX_INVALID_VMCS_PTR.
2082 */
2083#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2084DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2085#else
2086DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2087{
2088# if RT_INLINE_ASM_GNU_STYLE
2089 int rc = VINF_SUCCESS;
2090 __asm__ __volatile__ (
2091 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2092 "ja 2f \n\t"
2093 "je 1f \n\t"
2094 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2095 "jmp 2f \n\t"
2096 "1: \n\t"
2097 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2098 "2: \n\t"
2099 :"=rm"(rc)
2100 :"0"(VINF_SUCCESS),
2101 "a"(idxField),
2102 "d"(u32Val)
2103 );
2104 return rc;
2105
2106# elif VMX_USE_MSC_INTRINSICS
2107 unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2108 if (RT_LIKELY(rcMsc == 0))
2109 return VINF_SUCCESS;
2110 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2111
2112#else
2113 int rc = VINF_SUCCESS;
2114 __asm
2115 {
2116 push dword ptr [u32Val]
2117 mov eax, [idxField]
2118 _emit 0x0F
2119 _emit 0x79
2120 _emit 0x04
2121 _emit 0x24 /* VMWRITE eax, [esp] */
2122 jnc valid_vmcs
2123 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2124 jmp the_end
2125
2126valid_vmcs:
2127 jnz the_end
2128 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2129the_end:
2130 add esp, 4
2131 }
2132 return rc;
2133# endif
2134}
2135#endif
2136
2137/**
2138 * Executes VMWRITE
2139 *
2140 * @returns VBox status code
2141 * @retval VINF_SUCCESS
2142 * @retval VERR_VMX_INVALID_VMCS_PTR
2143 * @retval VERR_VMX_INVALID_VMCS_FIELD
2144 *
2145 * @param idxField VMCS index
2146 * @param u64Val 16, 32 or 64 bits value
2147 *
2148 * @remarks The values of the two status codes can be ORed together, the result
2149 * will be VERR_VMX_INVALID_VMCS_PTR.
2150 */
2151#if !defined(RT_ARCH_X86) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2152# if !VMX_USE_MSC_INTRINSICS || ARCH_BITS != 64
2153DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2154# else /* VMX_USE_MSC_INTRINSICS */
2155DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2156{
2157 unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2158 if (RT_LIKELY(rcMsc == 0))
2159 return VINF_SUCCESS;
2160 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2161}
2162# endif /* VMX_USE_MSC_INTRINSICS */
2163#else
2164# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2165VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2166#endif
2167
2168#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2169# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
2170 VMXWriteVmcs64(idxField, uVal) \
2171 : VMXWriteVmcs32(idxField, uVal)
2172# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
2173 VMXWriteVmcs64(idxField, u64Val) \
2174 : VMXWriteVmcs32(idxField, u64Val)
2175#elif ARCH_BITS == 32
2176# define VMXWriteVmcsHstN VMXWriteVmcs32
2177# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2178# else /* ARCH_BITS == 64 */
2179# define VMXWriteVmcsHstN VMXWriteVmcs64
2180# define VMXWriteVmcsGstN VMXWriteVmcs64
2181# endif
2182
2183
2184/**
2185 * Invalidate a page using invept
2186 * @returns VBox status code
2187 * @param enmFlush Type of flush
2188 * @param pDescriptor Descriptor
2189 */
2190DECLASM(int) VMXR0InvEPT(VMX_FLUSH_EPT enmFlush, uint64_t *pDescriptor);
2191
2192/**
2193 * Invalidate a page using invvpid
2194 * @returns VBox status code
2195 * @param enmFlush Type of flush
2196 * @param pDescriptor Descriptor
2197 */
2198DECLASM(int) VMXR0InvVPID(VMX_FLUSH_VPID enmFlush, uint64_t *pDescriptor);
2199
2200/**
2201 * Executes VMREAD
2202 *
2203 * @returns VBox status code
2204 * @retval VINF_SUCCESS
2205 * @retval VERR_VMX_INVALID_VMCS_PTR
2206 * @retval VERR_VMX_INVALID_VMCS_FIELD
2207 *
2208 * @param idxField VMCS index
2209 * @param pData Ptr to store VM field value
2210 *
2211 * @remarks The values of the two status codes can be ORed together, the result
2212 * will be VERR_VMX_INVALID_VMCS_PTR.
2213 */
2214#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2215DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2216#else
2217DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2218{
2219# if RT_INLINE_ASM_GNU_STYLE
2220 int rc = VINF_SUCCESS;
2221 __asm__ __volatile__ (
2222 "movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2223 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2224 "ja 2f \n\t"
2225 "je 1f \n\t"
2226 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2227 "jmp 2f \n\t"
2228 "1: \n\t"
2229 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2230 "2: \n\t"
2231 :"=&r"(rc),
2232 "=d"(*pData)
2233 :"a"(idxField),
2234 "d"(0)
2235 );
2236 return rc;
2237
2238# elif VMX_USE_MSC_INTRINSICS
2239 unsigned char rcMsc;
2240# if ARCH_BITS == 32
2241 rcMsc = __vmx_vmread(idxField, pData);
2242# else
2243 uint64_t u64Tmp;
2244 rcMsc = __vmx_vmread(idxField, &u64Tmp);
2245 *pData = (uint32_t)u64Tmp;
2246# endif
2247 if (RT_LIKELY(rcMsc == 0))
2248 return VINF_SUCCESS;
2249 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2250
2251#else
2252 int rc = VINF_SUCCESS;
2253 __asm
2254 {
2255 sub esp, 4
2256 mov dword ptr [esp], 0
2257 mov eax, [idxField]
2258 _emit 0x0F
2259 _emit 0x78
2260 _emit 0x04
2261 _emit 0x24 /* VMREAD eax, [esp] */
2262 mov edx, pData
2263 pop dword ptr [edx]
2264 jnc valid_vmcs
2265 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2266 jmp the_end
2267
2268valid_vmcs:
2269 jnz the_end
2270 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2271the_end:
2272 }
2273 return rc;
2274# endif
2275}
2276#endif
2277
2278/**
2279 * Executes VMREAD
2280 *
2281 * @returns VBox status code
2282 * @retval VINF_SUCCESS
2283 * @retval VERR_VMX_INVALID_VMCS_PTR
2284 * @retval VERR_VMX_INVALID_VMCS_FIELD
2285 *
2286 * @param idxField VMCS index
2287 * @param pData Ptr to store VM field value
2288 *
2289 * @remarks The values of the two status codes can be ORed together, the result
2290 * will be VERR_VMX_INVALID_VMCS_PTR.
2291 */
2292#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2293DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2294#else
2295DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2296{
2297# if VMX_USE_MSC_INTRINSICS
2298 unsigned char rcMsc;
2299# if ARCH_BITS == 32
2300 size_t uLow;
2301 size_t uHigh;
2302 rcMsc = __vmx_vmread(idxField, &uLow);
2303 rcMsc |= __vmx_vmread(idxField + 1, &uHigh);
2304 *pData = RT_MAKE_U64(uLow, uHigh);
2305# else
2306 rcMsc = __vmx_vmread(idxField, pData);
2307# endif
2308 if (RT_LIKELY(rcMsc == 0))
2309 return VINF_SUCCESS;
2310 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2311
2312# elif ARCH_BITS == 32
2313 int rc;
2314 uint32_t val_hi, val;
2315 rc = VMXReadVmcs32(idxField, &val);
2316 rc |= VMXReadVmcs32(idxField + 1, &val_hi);
2317 AssertRC(rc);
2318 *pData = RT_MAKE_U64(val, val_hi);
2319 return rc;
2320
2321# else
2322# error "Shouldn't be here..."
2323# endif
2324}
2325#endif
2326
2327/**
2328 * Gets the last instruction error value from the current VMCS
2329 *
2330 * @returns error value
2331 */
2332DECLINLINE(uint32_t) VMXGetLastError(void)
2333{
2334#if ARCH_BITS == 64
2335 uint64_t uLastError = 0;
2336 int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2337 AssertRC(rc);
2338 return (uint32_t)uLastError;
2339
2340#else /* 32-bit host: */
2341 uint32_t uLastError = 0;
2342 int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2343 AssertRC(rc);
2344 return uLastError;
2345#endif
2346}
2347
2348#ifdef IN_RING0
2349VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2350VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2351#endif /* IN_RING0 */
2352
2353/** @} */
2354
2355#endif
2356
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