VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 51718

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1/** @file
2 * HM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2014 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vmx_h
27#define ___VBox_vmm_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/x86.h>
32#include <iprt/assert.h>
33
34/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35 when targeting AMD64. */
36#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37# include <intrin.h>
38/* We always want them as intrinsics, no functions. */
39# pragma intrinsic(__vmx_on)
40# pragma intrinsic(__vmx_off)
41# pragma intrinsic(__vmx_vmclear)
42# pragma intrinsic(__vmx_vmptrld)
43# pragma intrinsic(__vmx_vmread)
44# pragma intrinsic(__vmx_vmwrite)
45# define VMX_USE_MSC_INTRINSICS 1
46#else
47# define VMX_USE_MSC_INTRINSICS 0
48#endif
49
50
51/** @defgroup grp_vmx vmx Types and Definitions
52 * @ingroup grp_hm
53 * @{
54 */
55
56/** @def HMVMXCPU_GST_SET_UPDATED
57 * Sets a guest-state-updated flag.
58 *
59 * @param pVCpu Pointer to the VMCPU.
60 * @param fFlag The flag to set.
61 */
62#define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
63
64/** @def HMVMXCPU_GST_IS_SET
65 * Checks if all the flags in the specified guest-state-updated set is pending.
66 *
67 * @param pVCpu Pointer to the VMCPU.
68 * @param fFlag The flag to check.
69 */
70#define HMVMXCPU_GST_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
71
72/** @def HMVMXCPU_GST_IS_UPDATED
73 * Checks if one or more of the flags in the specified guest-state-updated set
74 * is updated.
75 *
76 * @param pVCpu Pointer to the VMCPU.
77 * @param fFlags The flags to check for.
78 */
79#define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
80
81/** @def HMVMXCPU_GST_RESET_TO
82 * Resets the guest-state-updated flags to the specified value.
83 *
84 * @param pVCpu Pointer to the VMCPU.
85 * @param fFlags The new value.
86 */
87#define HMVMXCPU_GST_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlags)))
88
89/** @def HMVMXCPU_GST_VALUE
90 * Returns the current guest-state-updated flags value.
91 *
92 * @param pVCpu Pointer to the VMCPU.
93 */
94#define HMVMXCPU_GST_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState))
95
96/** @name Host-state restoration flags.
97 * @{
98 */
99/* If you change these values don't forget to update the assembly defines as well! */
100#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
101#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
102#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
103#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
104#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
105#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
106#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
107#define VMX_RESTORE_HOST_REQUIRED RT_BIT(7)
108/** @} */
109
110/**
111 * Host-state restoration structure.
112 * This holds host-state fields that require manual restoration.
113 * Assembly version found in hm_vmx.mac (should be automatically verified).
114 */
115typedef struct VMXRESTOREHOST
116{
117 RTSEL uHostSelDS; /* 0x00 */
118 RTSEL uHostSelES; /* 0x02 */
119 RTSEL uHostSelFS; /* 0x04 */
120 RTSEL uHostSelGS; /* 0x06 */
121 RTSEL uHostSelTR; /* 0x08 */
122 uint8_t abPadding0[4];
123 X86XDTR64 HostGdtr; /**< 0x0e - should be aligned by it's 64-bit member. */
124 uint8_t abPadding1[6];
125 X86XDTR64 HostIdtr; /**< 0x1e - should be aligned by it's 64-bit member. */
126 uint64_t uHostFSBase; /* 0x28 */
127 uint64_t uHostGSBase; /* 0x30 */
128} VMXRESTOREHOST;
129/** Pointer to VMXRESTOREHOST. */
130typedef VMXRESTOREHOST *PVMXRESTOREHOST;
131AssertCompileSize(X86XDTR64, 10);
132AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
133AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
134AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
135AssertCompileSize(VMXRESTOREHOST, 56);
136AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
137
138/** @name Host-state MSR lazy-restoration flags.
139 * @{
140 */
141/** The host MSRs have been saved. */
142#define VMX_RESTORE_HOST_MSR_SAVED_HOST RT_BIT(0)
143/** The guest MSRs are loaded and in effect. */
144#define VMX_RESTORE_HOST_MSR_LOADED_GUEST RT_BIT(1)
145/** @} */
146
147/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
148 * UFC = Unsupported Feature Combination.
149 * @{
150 */
151/** Unsupported pin-based VM-execution controls combo. */
152#define VMX_UFC_CTRL_PIN_EXEC 0
153/** Unsupported processor-based VM-execution controls combo. */
154#define VMX_UFC_CTRL_PROC_EXEC 1
155/** Unsupported pin-based VM-execution controls combo. */
156#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 2
157/** Unsupported VM-entry controls combo. */
158#define VMX_UFC_CTRL_ENTRY 3
159/** Unsupported VM-exit controls combo. */
160#define VMX_UFC_CTRL_EXIT 4
161/** MSR storage capacity of the VMCS autoload/store area is not sufficient
162 * for storing host MSRs. */
163#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 5
164/** MSR storage capacity of the VMCS autoload/store area is not sufficient
165 * for storing guest MSRs. */
166#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 6
167/** Invalid VMCS size. */
168#define VMX_UFC_INVALID_VMCS_SIZE 7
169/** Unsupported secondary processor-based VM-execution controls combo. */
170#define VMX_UFC_CTRL_PROC_EXEC2 8
171/** Invalid unrestricted-guest execution controls combo. */
172#define VMX_UFC_INVALID_UX_COMBO 9
173/** @} */
174
175/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
176 * IGS = Invalid Guest State.
177 * @{
178 */
179/** An error occurred while checking invalid-guest-state. */
180#define VMX_IGS_ERROR 0
181/** The invalid guest-state checks did not find any reason why. */
182#define VMX_IGS_REASON_NOT_FOUND 1
183/** CR0 fixed1 bits invalid. */
184#define VMX_IGS_CR0_FIXED1 2
185/** CR0 fixed0 bits invalid. */
186#define VMX_IGS_CR0_FIXED0 3
187/** CR0.PE and CR0.PE invalid VT-x/host combination. */
188#define VMX_IGS_CR0_PG_PE_COMBO 4
189/** CR4 fixed1 bits invalid. */
190#define VMX_IGS_CR4_FIXED1 5
191/** CR4 fixed0 bits invalid. */
192#define VMX_IGS_CR4_FIXED0 6
193/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
194 * VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
195#define VMX_IGS_DEBUGCTL_MSR_RESERVED 7
196/** CR0.PG not set for long-mode when not using unrestricted guest. */
197#define VMX_IGS_CR0_PG_LONGMODE 8
198/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
199#define VMX_IGS_CR4_PAE_LONGMODE 9
200/** CR4.PCIDE set for 32-bit guest. */
201#define VMX_IGS_CR4_PCIDE 10
202/** VMCS' DR7 reserved bits not set to 0. */
203#define VMX_IGS_DR7_RESERVED 11
204/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
205#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12
206/** VMCS' EFER MSR reserved bits not set to 0. */
207#define VMX_IGS_EFER_MSR_RESERVED 13
208/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
209#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14
210/** VMCS' EFER MSR.LMA does not match CR0.PG of the guest when not using
211 * unrestricted guest. */
212#define VMX_IGS_EFER_LMA_PG_MISMATCH 15
213/** CS.Attr.P bit invalid. */
214#define VMX_IGS_CS_ATTR_P_INVALID 16
215/** CS.Attr reserved bits not set to 0. */
216#define VMX_IGS_CS_ATTR_RESERVED 17
217/** CS.Attr.G bit invalid. */
218#define VMX_IGS_CS_ATTR_G_INVALID 18
219/** CS is unusable. */
220#define VMX_IGS_CS_ATTR_UNUSABLE 19
221/** CS and SS DPL unequal. */
222#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20
223/** CS and SS DPL mismatch. */
224#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21
225/** CS Attr.Type invalid. */
226#define VMX_IGS_CS_ATTR_TYPE_INVALID 22
227/** CS and SS RPL unequal. */
228#define VMX_IGS_SS_CS_RPL_UNEQUAL 23
229/** SS.Attr.DPL and SS RPL unequal. */
230#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24
231/** SS.Attr.DPL invalid for segment type. */
232#define VMX_IGS_SS_ATTR_DPL_INVALID 25
233/** SS.Attr.Type invalid. */
234#define VMX_IGS_SS_ATTR_TYPE_INVALID 26
235/** SS.Attr.P bit invalid. */
236#define VMX_IGS_SS_ATTR_P_INVALID 27
237/** SS.Attr reserved bits not set to 0. */
238#define VMX_IGS_SS_ATTR_RESERVED 28
239/** SS.Attr.G bit invalid. */
240#define VMX_IGS_SS_ATTR_G_INVALID 29
241/** DS.Attr.A bit invalid. */
242#define VMX_IGS_DS_ATTR_A_INVALID 30
243/** DS.Attr.P bit invalid. */
244#define VMX_IGS_DS_ATTR_P_INVALID 31
245/** DS.Attr.DPL and DS RPL unequal. */
246#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32
247/** DS.Attr reserved bits not set to 0. */
248#define VMX_IGS_DS_ATTR_RESERVED 33
249/** DS.Attr.G bit invalid. */
250#define VMX_IGS_DS_ATTR_G_INVALID 34
251/** DS.Attr.Type invalid. */
252#define VMX_IGS_DS_ATTR_TYPE_INVALID 35
253/** ES.Attr.A bit invalid. */
254#define VMX_IGS_ES_ATTR_A_INVALID 36
255/** ES.Attr.P bit invalid. */
256#define VMX_IGS_ES_ATTR_P_INVALID 37
257/** ES.Attr.DPL and DS RPL unequal. */
258#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38
259/** ES.Attr reserved bits not set to 0. */
260#define VMX_IGS_ES_ATTR_RESERVED 39
261/** ES.Attr.G bit invalid. */
262#define VMX_IGS_ES_ATTR_G_INVALID 40
263/** ES.Attr.Type invalid. */
264#define VMX_IGS_ES_ATTR_TYPE_INVALID 41
265/** FS.Attr.A bit invalid. */
266#define VMX_IGS_FS_ATTR_A_INVALID 42
267/** FS.Attr.P bit invalid. */
268#define VMX_IGS_FS_ATTR_P_INVALID 43
269/** FS.Attr.DPL and DS RPL unequal. */
270#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44
271/** FS.Attr reserved bits not set to 0. */
272#define VMX_IGS_FS_ATTR_RESERVED 45
273/** FS.Attr.G bit invalid. */
274#define VMX_IGS_FS_ATTR_G_INVALID 46
275/** FS.Attr.Type invalid. */
276#define VMX_IGS_FS_ATTR_TYPE_INVALID 47
277/** GS.Attr.A bit invalid. */
278#define VMX_IGS_GS_ATTR_A_INVALID 48
279/** GS.Attr.P bit invalid. */
280#define VMX_IGS_GS_ATTR_P_INVALID 49
281/** GS.Attr.DPL and DS RPL unequal. */
282#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 50
283/** GS.Attr reserved bits not set to 0. */
284#define VMX_IGS_GS_ATTR_RESERVED 51
285/** GS.Attr.G bit invalid. */
286#define VMX_IGS_GS_ATTR_G_INVALID 52
287/** GS.Attr.Type invalid. */
288#define VMX_IGS_GS_ATTR_TYPE_INVALID 53
289/** V86 mode CS.Base invalid. */
290#define VMX_IGS_V86_CS_BASE_INVALID 54
291/** V86 mode CS.Limit invalid. */
292#define VMX_IGS_V86_CS_LIMIT_INVALID 55
293/** V86 mode CS.Attr invalid. */
294#define VMX_IGS_V86_CS_ATTR_INVALID 56
295/** V86 mode SS.Base invalid. */
296#define VMX_IGS_V86_SS_BASE_INVALID 57
297/** V86 mode SS.Limit invalid. */
298#define VMX_IGS_V86_SS_LIMIT_INVALID 58
299/** V86 mode SS.Attr invalid. */
300#define VMX_IGS_V86_SS_ATTR_INVALID 59
301/** V86 mode DS.Base invalid. */
302#define VMX_IGS_V86_DS_BASE_INVALID 60
303/** V86 mode DS.Limit invalid. */
304#define VMX_IGS_V86_DS_LIMIT_INVALID 61
305/** V86 mode DS.Attr invalid. */
306#define VMX_IGS_V86_DS_ATTR_INVALID 62
307/** V86 mode ES.Base invalid. */
308#define VMX_IGS_V86_ES_BASE_INVALID 63
309/** V86 mode ES.Limit invalid. */
310#define VMX_IGS_V86_ES_LIMIT_INVALID 64
311/** V86 mode ES.Attr invalid. */
312#define VMX_IGS_V86_ES_ATTR_INVALID 65
313/** V86 mode FS.Base invalid. */
314#define VMX_IGS_V86_FS_BASE_INVALID 66
315/** V86 mode FS.Limit invalid. */
316#define VMX_IGS_V86_FS_LIMIT_INVALID 67
317/** V86 mode FS.Attr invalid. */
318#define VMX_IGS_V86_FS_ATTR_INVALID 68
319/** V86 mode GS.Base invalid. */
320#define VMX_IGS_V86_GS_BASE_INVALID 69
321/** V86 mode GS.Limit invalid. */
322#define VMX_IGS_V86_GS_LIMIT_INVALID 70
323/** V86 mode GS.Attr invalid. */
324#define VMX_IGS_V86_GS_ATTR_INVALID 71
325/** Longmode CS.Base invalid. */
326#define VMX_IGS_LONGMODE_CS_BASE_INVALID 72
327/** Longmode SS.Base invalid. */
328#define VMX_IGS_LONGMODE_SS_BASE_INVALID 73
329/** Longmode DS.Base invalid. */
330#define VMX_IGS_LONGMODE_DS_BASE_INVALID 74
331/** Longmode ES.Base invalid. */
332#define VMX_IGS_LONGMODE_ES_BASE_INVALID 75
333/** SYSENTER ESP is not canonical. */
334#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76
335/** SYSENTER EIP is not canonical. */
336#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77
337/** PAT MSR invalid. */
338#define VMX_IGS_PAT_MSR_INVALID 78
339/** PAT MSR reserved bits not set to 0. */
340#define VMX_IGS_PAT_MSR_RESERVED 79
341/** GDTR.Base is not canonical. */
342#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80
343/** IDTR.Base is not canonical. */
344#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81
345/** GDTR.Limit invalid. */
346#define VMX_IGS_GDTR_LIMIT_INVALID 82
347/** IDTR.Limit invalid. */
348#define VMX_IGS_IDTR_LIMIT_INVALID 83
349/** Longmode RIP is invalid. */
350#define VMX_IGS_LONGMODE_RIP_INVALID 84
351/** RFLAGS reserved bits not set to 0. */
352#define VMX_IGS_RFLAGS_RESERVED 85
353/** RFLAGS RA1 reserved bits not set to 1. */
354#define VMX_IGS_RFLAGS_RESERVED1 86
355/** RFLAGS.VM (V86 mode) invalid. */
356#define VMX_IGS_RFLAGS_VM_INVALID 87
357/** RFLAGS.IF invalid. */
358#define VMX_IGS_RFLAGS_IF_INVALID 88
359/** Activity state invalid. */
360#define VMX_IGS_ACTIVITY_STATE_INVALID 89
361/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
362#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90
363/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
364#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91
365/** Activity state SIPI WAIT invalid. */
366#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92
367/** Interruptibility state reserved bits not set to 0. */
368#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93
369/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
370#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94
371/** Interruptibility state block-by-STI invalid for EFLAGS. */
372#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95
373/** Interruptibility state invalid while trying to deliver external
374 * interrupt. */
375#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96
376/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
377 * NMI. */
378#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97
379/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
380#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98
381/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
382#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99
383/** Interruptibilty state block-by-STI (maybe) invalid when trying to deliver
384 * an NMI. */
385#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100
386/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
387 * active. */
388#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101
389/** Pending debug exceptions reserved bits not set to 0. */
390#define VMX_IGS_PENDING_DEBUG_RESERVED 102
391/** Longmode pending debug exceptions reserved bits not set to 0. */
392#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103
393/** Pending debug exceptions.BS bit is not set when it should be. */
394#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104
395/** Pending debug exceptions.BS bit is not clear when it should be. */
396#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105
397/** VMCS link pointer reserved bits not set to 0. */
398#define VMX_IGS_VMCS_LINK_PTR_RESERVED 106
399/** TR cannot index into LDT, TI bit MBZ. */
400#define VMX_IGS_TR_TI_INVALID 107
401/** LDTR cannot index into LDT. TI bit MBZ. */
402#define VMX_IGS_LDTR_TI_INVALID 108
403/** TR.Base is not canonical. */
404#define VMX_IGS_TR_BASE_NOT_CANONICAL 109
405/** FS.Base is not canonical. */
406#define VMX_IGS_FS_BASE_NOT_CANONICAL 110
407/** GS.Base is not canonical. */
408#define VMX_IGS_GS_BASE_NOT_CANONICAL 111
409/** LDTR.Base is not canonical. */
410#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 112
411/** TR is unusable. */
412#define VMX_IGS_TR_ATTR_UNUSABLE 113
413/** TR.Attr.S bit invalid. */
414#define VMX_IGS_TR_ATTR_S_INVALID 114
415/** TR is not present. */
416#define VMX_IGS_TR_ATTR_P_INVALID 115
417/** TR.Attr reserved bits not set to 0. */
418#define VMX_IGS_TR_ATTR_RESERVED 116
419/** TR.Attr.G bit invalid. */
420#define VMX_IGS_TR_ATTR_G_INVALID 117
421/** Longmode TR.Attr.Type invalid. */
422#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 118
423/** TR.Attr.Type invalid. */
424#define VMX_IGS_TR_ATTR_TYPE_INVALID 119
425/** CS.Attr.S invalid. */
426#define VMX_IGS_CS_ATTR_S_INVALID 120
427/** CS.Attr.DPL invalid. */
428#define VMX_IGS_CS_ATTR_DPL_INVALID 121
429/** PAE PDPTE reserved bits not set to 0. */
430#define VMX_IGS_PAE_PDPTE_RESERVED 123
431/** @} */
432
433/** @name VMX VMCS-Read cache indices.
434 * @{
435 */
436# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
437# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
438# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
439# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
440# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
441# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
442# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
443# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
444# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
445# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
446# define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
447# define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
448# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
449# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
450# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
451# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
452# define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
453# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
454/** @} */
455
456/** @name VMX EPT paging structures
457 * @{
458 */
459
460/**
461 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
462 */
463#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
464
465/**
466 * EPT Page Directory Pointer Entry. Bit view.
467 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
468 * this did cause trouble with one compiler/version).
469 */
470#pragma pack(1)
471typedef struct EPTPML4EBITS
472{
473 /** Present bit. */
474 uint64_t u1Present : 1;
475 /** Writable bit. */
476 uint64_t u1Write : 1;
477 /** Executable bit. */
478 uint64_t u1Execute : 1;
479 /** Reserved (must be 0). */
480 uint64_t u5Reserved : 5;
481 /** Available for software. */
482 uint64_t u4Available : 4;
483 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
484 uint64_t u40PhysAddr : 40;
485 /** Availabe for software. */
486 uint64_t u12Available : 12;
487} EPTPML4EBITS;
488#pragma pack()
489AssertCompileSize(EPTPML4EBITS, 8);
490
491/** Bits 12-51 - - EPT - Physical Page number of the next level. */
492#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
493/** The page shift to get the PML4 index. */
494#define EPT_PML4_SHIFT X86_PML4_SHIFT
495/** The PML4 index mask (apply to a shifted page address). */
496#define EPT_PML4_MASK X86_PML4_MASK
497
498/**
499 * EPT PML4E.
500 */
501#pragma pack(1)
502typedef union EPTPML4E
503{
504 /** Normal view. */
505 EPTPML4EBITS n;
506 /** Unsigned integer view. */
507 X86PGPAEUINT u;
508 /** 64 bit unsigned integer view. */
509 uint64_t au64[1];
510 /** 32 bit unsigned integer view. */
511 uint32_t au32[2];
512} EPTPML4E;
513#pragma pack()
514/** Pointer to a PML4 table entry. */
515typedef EPTPML4E *PEPTPML4E;
516/** Pointer to a const PML4 table entry. */
517typedef const EPTPML4E *PCEPTPML4E;
518AssertCompileSize(EPTPML4E, 8);
519
520/**
521 * EPT PML4 Table.
522 */
523#pragma pack(1)
524typedef struct EPTPML4
525{
526 EPTPML4E a[EPT_PG_ENTRIES];
527} EPTPML4;
528#pragma pack()
529/** Pointer to an EPT PML4 Table. */
530typedef EPTPML4 *PEPTPML4;
531/** Pointer to a const EPT PML4 Table. */
532typedef const EPTPML4 *PCEPTPML4;
533
534/**
535 * EPT Page Directory Pointer Entry. Bit view.
536 */
537#pragma pack(1)
538typedef struct EPTPDPTEBITS
539{
540 /** Present bit. */
541 uint64_t u1Present : 1;
542 /** Writable bit. */
543 uint64_t u1Write : 1;
544 /** Executable bit. */
545 uint64_t u1Execute : 1;
546 /** Reserved (must be 0). */
547 uint64_t u5Reserved : 5;
548 /** Available for software. */
549 uint64_t u4Available : 4;
550 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
551 uint64_t u40PhysAddr : 40;
552 /** Availabe for software. */
553 uint64_t u12Available : 12;
554} EPTPDPTEBITS;
555#pragma pack()
556AssertCompileSize(EPTPDPTEBITS, 8);
557
558/** Bits 12-51 - - EPT - Physical Page number of the next level. */
559#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
560/** The page shift to get the PDPT index. */
561#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
562/** The PDPT index mask (apply to a shifted page address). */
563#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
564
565/**
566 * EPT Page Directory Pointer.
567 */
568#pragma pack(1)
569typedef union EPTPDPTE
570{
571 /** Normal view. */
572 EPTPDPTEBITS n;
573 /** Unsigned integer view. */
574 X86PGPAEUINT u;
575 /** 64 bit unsigned integer view. */
576 uint64_t au64[1];
577 /** 32 bit unsigned integer view. */
578 uint32_t au32[2];
579} EPTPDPTE;
580#pragma pack()
581/** Pointer to an EPT Page Directory Pointer Entry. */
582typedef EPTPDPTE *PEPTPDPTE;
583/** Pointer to a const EPT Page Directory Pointer Entry. */
584typedef const EPTPDPTE *PCEPTPDPTE;
585AssertCompileSize(EPTPDPTE, 8);
586
587/**
588 * EPT Page Directory Pointer Table.
589 */
590#pragma pack(1)
591typedef struct EPTPDPT
592{
593 EPTPDPTE a[EPT_PG_ENTRIES];
594} EPTPDPT;
595#pragma pack()
596/** Pointer to an EPT Page Directory Pointer Table. */
597typedef EPTPDPT *PEPTPDPT;
598/** Pointer to a const EPT Page Directory Pointer Table. */
599typedef const EPTPDPT *PCEPTPDPT;
600
601
602/**
603 * EPT Page Directory Table Entry. Bit view.
604 */
605#pragma pack(1)
606typedef struct EPTPDEBITS
607{
608 /** Present bit. */
609 uint64_t u1Present : 1;
610 /** Writable bit. */
611 uint64_t u1Write : 1;
612 /** Executable bit. */
613 uint64_t u1Execute : 1;
614 /** Reserved (must be 0). */
615 uint64_t u4Reserved : 4;
616 /** Big page (must be 0 here). */
617 uint64_t u1Size : 1;
618 /** Available for software. */
619 uint64_t u4Available : 4;
620 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
621 uint64_t u40PhysAddr : 40;
622 /** Availabe for software. */
623 uint64_t u12Available : 12;
624} EPTPDEBITS;
625#pragma pack()
626AssertCompileSize(EPTPDEBITS, 8);
627
628/** Bits 12-51 - - EPT - Physical Page number of the next level. */
629#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
630/** The page shift to get the PD index. */
631#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
632/** The PD index mask (apply to a shifted page address). */
633#define EPT_PD_MASK X86_PD_PAE_MASK
634
635/**
636 * EPT 2MB Page Directory Table Entry. Bit view.
637 */
638#pragma pack(1)
639typedef struct EPTPDE2MBITS
640{
641 /** Present bit. */
642 uint64_t u1Present : 1;
643 /** Writable bit. */
644 uint64_t u1Write : 1;
645 /** Executable bit. */
646 uint64_t u1Execute : 1;
647 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
648 uint64_t u3EMT : 3;
649 /** Ignore PAT memory type */
650 uint64_t u1IgnorePAT : 1;
651 /** Big page (must be 1 here). */
652 uint64_t u1Size : 1;
653 /** Available for software. */
654 uint64_t u4Available : 4;
655 /** Reserved (must be 0). */
656 uint64_t u9Reserved : 9;
657 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
658 uint64_t u31PhysAddr : 31;
659 /** Availabe for software. */
660 uint64_t u12Available : 12;
661} EPTPDE2MBITS;
662#pragma pack()
663AssertCompileSize(EPTPDE2MBITS, 8);
664
665/** Bits 21-51 - - EPT - Physical Page number of the next level. */
666#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
667
668/**
669 * EPT Page Directory Table Entry.
670 */
671#pragma pack(1)
672typedef union EPTPDE
673{
674 /** Normal view. */
675 EPTPDEBITS n;
676 /** 2MB view (big). */
677 EPTPDE2MBITS b;
678 /** Unsigned integer view. */
679 X86PGPAEUINT u;
680 /** 64 bit unsigned integer view. */
681 uint64_t au64[1];
682 /** 32 bit unsigned integer view. */
683 uint32_t au32[2];
684} EPTPDE;
685#pragma pack()
686/** Pointer to an EPT Page Directory Table Entry. */
687typedef EPTPDE *PEPTPDE;
688/** Pointer to a const EPT Page Directory Table Entry. */
689typedef const EPTPDE *PCEPTPDE;
690AssertCompileSize(EPTPDE, 8);
691
692/**
693 * EPT Page Directory Table.
694 */
695#pragma pack(1)
696typedef struct EPTPD
697{
698 EPTPDE a[EPT_PG_ENTRIES];
699} EPTPD;
700#pragma pack()
701/** Pointer to an EPT Page Directory Table. */
702typedef EPTPD *PEPTPD;
703/** Pointer to a const EPT Page Directory Table. */
704typedef const EPTPD *PCEPTPD;
705
706
707/**
708 * EPT Page Table Entry. Bit view.
709 */
710#pragma pack(1)
711typedef struct EPTPTEBITS
712{
713 /** 0 - Present bit.
714 * @remark This is a convenience "misnomer". The bit actually indicates
715 * read access and the CPU will consider an entry with any of the
716 * first three bits set as present. Since all our valid entries
717 * will have this bit set, it can be used as a present indicator
718 * and allow some code sharing. */
719 uint64_t u1Present : 1;
720 /** 1 - Writable bit. */
721 uint64_t u1Write : 1;
722 /** 2 - Executable bit. */
723 uint64_t u1Execute : 1;
724 /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
725 uint64_t u3EMT : 3;
726 /** 6 - Ignore PAT memory type */
727 uint64_t u1IgnorePAT : 1;
728 /** 11:7 - Available for software. */
729 uint64_t u5Available : 5;
730 /** 51:12 - Physical address of page. Restricted by maximum physical
731 * address width of the cpu. */
732 uint64_t u40PhysAddr : 40;
733 /** 63:52 - Available for software. */
734 uint64_t u12Available : 12;
735} EPTPTEBITS;
736#pragma pack()
737AssertCompileSize(EPTPTEBITS, 8);
738
739/** Bits 12-51 - - EPT - Physical Page number of the next level. */
740#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
741/** The page shift to get the EPT PTE index. */
742#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
743/** The EPT PT index mask (apply to a shifted page address). */
744#define EPT_PT_MASK X86_PT_PAE_MASK
745
746/**
747 * EPT Page Table Entry.
748 */
749#pragma pack(1)
750typedef union EPTPTE
751{
752 /** Normal view. */
753 EPTPTEBITS n;
754 /** Unsigned integer view. */
755 X86PGPAEUINT u;
756 /** 64 bit unsigned integer view. */
757 uint64_t au64[1];
758 /** 32 bit unsigned integer view. */
759 uint32_t au32[2];
760} EPTPTE;
761#pragma pack()
762/** Pointer to an EPT Page Directory Table Entry. */
763typedef EPTPTE *PEPTPTE;
764/** Pointer to a const EPT Page Directory Table Entry. */
765typedef const EPTPTE *PCEPTPTE;
766AssertCompileSize(EPTPTE, 8);
767
768/**
769 * EPT Page Table.
770 */
771#pragma pack(1)
772typedef struct EPTPT
773{
774 EPTPTE a[EPT_PG_ENTRIES];
775} EPTPT;
776#pragma pack()
777/** Pointer to an extended page table. */
778typedef EPTPT *PEPTPT;
779/** Pointer to a const extended table. */
780typedef const EPTPT *PCEPTPT;
781
782/** @name VMX VPID flush types.
783 * Warning!! Valid enum members are in accordance to the VT-x spec.
784 * @{
785 */
786typedef enum
787{
788 /** Invalidate a specific page. */
789 VMXFLUSHVPID_INDIV_ADDR = 0,
790 /** Invalidate one context (specific VPID). */
791 VMXFLUSHVPID_SINGLE_CONTEXT = 1,
792 /** Invalidate all contexts (all VPIDs). */
793 VMXFLUSHVPID_ALL_CONTEXTS = 2,
794 /** Invalidate a single VPID context retaining global mappings. */
795 VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
796 /** Unsupported by VirtualBox. */
797 VMXFLUSHVPID_NOT_SUPPORTED = 0xbad0,
798 /** Unsupported by CPU. */
799 VMXFLUSHVPID_NONE = 0xbad1
800} VMXFLUSHVPID;
801AssertCompileSize(VMXFLUSHVPID, 4);
802/** @} */
803
804/** @name VMX EPT flush types.
805 * Warning!! Valid enums values below are in accordance to the VT-x spec.
806 * @{
807 */
808typedef enum
809{
810 /** Invalidate one context (specific EPT). */
811 VMXFLUSHEPT_SINGLE_CONTEXT = 1,
812 /* Invalidate all contexts (all EPTs) */
813 VMXFLUSHEPT_ALL_CONTEXTS = 2,
814 /** Unsupported by VirtualBox. */
815 VMXFLUSHEPT_NOT_SUPPORTED = 0xbad0,
816 /** Unsupported by CPU. */
817 VMXFLUSHEPT_NONE = 0xbad1
818} VMXFLUSHEPT;
819AssertCompileSize(VMXFLUSHEPT, 4);
820/** @} */
821
822/** @name VMX MSR autoload/store element.
823 * In accordance to VT-x spec.
824 * @{
825 */
826#pragma pack(1)
827typedef struct
828{
829 /** The MSR Id. */
830 uint32_t u32Msr;
831 /** Reserved (MBZ). */
832 uint32_t u32Reserved;
833 /** The MSR value. */
834 uint64_t u64Value;
835} VMXAUTOMSR;
836#pragma pack()
837/** Pointer to an MSR load/store element. */
838typedef VMXAUTOMSR *PVMXAUTOMSR;
839/** Pointer to a const MSR load/store element. */
840typedef const VMXAUTOMSR *PCVMXAUTOMSR;
841/** @} */
842
843/** @name VMX-capability qword
844 * @{
845 */
846#pragma pack(1)
847typedef union
848{
849 struct
850 {
851 /** Bits set here -must- be set in the correpsonding VM-execution controls. */
852 uint32_t disallowed0;
853 /** Bits cleared here -must- be cleared in the corresponding VM-execution
854 * controls. */
855 uint32_t allowed1;
856 } n;
857 uint64_t u;
858} VMXCAPABILITY;
859#pragma pack()
860/** @} */
861
862/** @name VMX MSRs.
863 * @{
864 */
865typedef struct VMXMSRS
866{
867 uint64_t u64FeatureCtrl;
868 uint64_t u64BasicInfo;
869 VMXCAPABILITY VmxPinCtls;
870 VMXCAPABILITY VmxProcCtls;
871 VMXCAPABILITY VmxProcCtls2;
872 VMXCAPABILITY VmxExit;
873 VMXCAPABILITY VmxEntry;
874 uint64_t u64Misc;
875 uint64_t u64Cr0Fixed0;
876 uint64_t u64Cr0Fixed1;
877 uint64_t u64Cr4Fixed0;
878 uint64_t u64Cr4Fixed1;
879 uint64_t u64VmcsEnum;
880 uint64_t u64Vmfunc;
881 uint64_t u64EptVpidCaps;
882} VMXMSRS;
883/** Pointer to a VMXMSRS struct. */
884typedef VMXMSRS *PVMXMSRS;
885AssertCompileSizeAlignment(VMXMSRS, 8);
886/** @} */
887
888/** @name VMX EFLAGS reserved bits.
889 * @{
890 */
891/** And-mask for setting reserved bits to zero */
892#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
893/** Or-mask for setting reserved bits to 1 */
894#define VMX_EFLAGS_RESERVED_1 0x00000002
895/** @} */
896
897/** @name VMX Basic Exit Reasons.
898 * @{
899 */
900/** -1 Invalid exit code */
901#define VMX_EXIT_INVALID -1
902/** 0 Exception or non-maskable interrupt (NMI). */
903#define VMX_EXIT_XCPT_OR_NMI 0
904/** 1 External interrupt. */
905#define VMX_EXIT_EXT_INT 1
906/** 2 Triple fault. */
907#define VMX_EXIT_TRIPLE_FAULT 2
908/** 3 INIT signal. */
909#define VMX_EXIT_INIT_SIGNAL 3
910/** 4 Start-up IPI (SIPI). */
911#define VMX_EXIT_SIPI 4
912/** 5 I/O system-management interrupt (SMI). */
913#define VMX_EXIT_IO_SMI 5
914/** 6 Other SMI. */
915#define VMX_EXIT_SMI 6
916/** 7 Interrupt window exiting. */
917#define VMX_EXIT_INT_WINDOW 7
918/** 8 NMI window exiting. */
919#define VMX_EXIT_NMI_WINDOW 8
920/** 9 Task switch. */
921#define VMX_EXIT_TASK_SWITCH 9
922/** 10 Guest software attempted to execute CPUID. */
923#define VMX_EXIT_CPUID 10
924/** 10 Guest software attempted to execute GETSEC. */
925#define VMX_EXIT_GETSEC 11
926/** 12 Guest software attempted to execute HLT. */
927#define VMX_EXIT_HLT 12
928/** 13 Guest software attempted to execute INVD. */
929#define VMX_EXIT_INVD 13
930/** 14 Guest software attempted to execute INVLPG. */
931#define VMX_EXIT_INVLPG 14
932/** 15 Guest software attempted to execute RDPMC. */
933#define VMX_EXIT_RDPMC 15
934/** 16 Guest software attempted to execute RDTSC. */
935#define VMX_EXIT_RDTSC 16
936/** 17 Guest software attempted to execute RSM in SMM. */
937#define VMX_EXIT_RSM 17
938/** 18 Guest software executed VMCALL. */
939#define VMX_EXIT_VMCALL 18
940/** 19 Guest software executed VMCLEAR. */
941#define VMX_EXIT_VMCLEAR 19
942/** 20 Guest software executed VMLAUNCH. */
943#define VMX_EXIT_VMLAUNCH 20
944/** 21 Guest software executed VMPTRLD. */
945#define VMX_EXIT_VMPTRLD 21
946/** 22 Guest software executed VMPTRST. */
947#define VMX_EXIT_VMPTRST 22
948/** 23 Guest software executed VMREAD. */
949#define VMX_EXIT_VMREAD 23
950/** 24 Guest software executed VMRESUME. */
951#define VMX_EXIT_VMRESUME 24
952/** 25 Guest software executed VMWRITE. */
953#define VMX_EXIT_VMWRITE 25
954/** 26 Guest software executed VMXOFF. */
955#define VMX_EXIT_VMXOFF 26
956/** 27 Guest software executed VMXON. */
957#define VMX_EXIT_VMXON 27
958/** 28 Control-register accesses. */
959#define VMX_EXIT_MOV_CRX 28
960/** 29 Debug-register accesses. */
961#define VMX_EXIT_MOV_DRX 29
962/** 30 I/O instruction. */
963#define VMX_EXIT_IO_INSTR 30
964/** 31 RDMSR. Guest software attempted to execute RDMSR. */
965#define VMX_EXIT_RDMSR 31
966/** 32 WRMSR. Guest software attempted to execute WRMSR. */
967#define VMX_EXIT_WRMSR 32
968/** 33 VM-entry failure due to invalid guest state. */
969#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
970/** 34 VM-entry failure due to MSR loading. */
971#define VMX_EXIT_ERR_MSR_LOAD 34
972/** 36 Guest software executed MWAIT. */
973#define VMX_EXIT_MWAIT 36
974/** 37 VM exit due to monitor trap flag. */
975#define VMX_EXIT_MTF 37
976/** 39 Guest software attempted to execute MONITOR. */
977#define VMX_EXIT_MONITOR 39
978/** 40 Guest software attempted to execute PAUSE. */
979#define VMX_EXIT_PAUSE 40
980/** 41 VM-entry failure due to machine-check. */
981#define VMX_EXIT_ERR_MACHINE_CHECK 41
982/** 43 TPR below threshold. Guest software executed MOV to CR8. */
983#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
984/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
985#define VMX_EXIT_APIC_ACCESS 44
986/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
987#define VMX_EXIT_XDTR_ACCESS 46
988/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
989#define VMX_EXIT_TR_ACCESS 47
990/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
991#define VMX_EXIT_EPT_VIOLATION 48
992/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
993#define VMX_EXIT_EPT_MISCONFIG 49
994/** 50 INVEPT. Guest software attempted to execute INVEPT. */
995#define VMX_EXIT_INVEPT 50
996/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
997#define VMX_EXIT_RDTSCP 51
998/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
999#define VMX_EXIT_PREEMPT_TIMER 52
1000/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1001#define VMX_EXIT_INVVPID 53
1002/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1003#define VMX_EXIT_WBINVD 54
1004/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1005#define VMX_EXIT_XSETBV 55
1006/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1007#define VMX_EXIT_RDRAND 57
1008/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1009#define VMX_EXIT_INVPCID 58
1010/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1011#define VMX_EXIT_VMFUNC 59
1012/** The maximum exit value (inclusive). */
1013#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
1014/** @} */
1015
1016
1017/** @name VM Instruction Errors
1018 * @{
1019 */
1020/** VMCALL executed in VMX root operation. */
1021#define VMX_ERROR_VMCALL 1
1022/** VMCLEAR with invalid physical address. */
1023#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1024/** VMCLEAR with VMXON pointer. */
1025#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1026/** VMLAUNCH with non-clear VMCS. */
1027#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1028/** VMRESUME with non-launched VMCS. */
1029#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1030/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1031#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1032/** VM-entry with invalid control field(s). */
1033#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1034/** VM-entry with invalid host-state field(s). */
1035#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1036/** VMPTRLD with invalid physical address. */
1037#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1038/** VMPTRLD with VMXON pointer. */
1039#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1040/** VMPTRLD with incorrect VMCS revision identifier. */
1041#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1042/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1043#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1044#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1045/** VMWRITE to read-only VMCS component. */
1046#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1047/** VMXON executed in VMX root operation. */
1048#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1049/** VM entry with invalid executive-VMCS pointer. */
1050#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1051/** VM entry with non-launched executive VMCS. */
1052#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1053/** VM entry with executive-VMCS pointer not VMXON pointer. */
1054#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1055/** VMCALL with non-clear VMCS. */
1056#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1057/** VMCALL with invalid VM-exit control fields. */
1058#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1059/** VMCALL with incorrect MSEG revision identifier. */
1060#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1061/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1062#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1063/** VMCALL with invalid SMM-monitor features. */
1064#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1065/** VM entry with invalid VM-execution control fields in executive VMCS. */
1066#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1067/** VM entry with events blocked by MOV SS. */
1068#define VMX_ERROR_VMENTRY_MOV_SS 26
1069/** Invalid operand to INVEPT/INVVPID. */
1070#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1071
1072/** @} */
1073
1074
1075/** @name VMX MSRs - Basic VMX information.
1076 * @{
1077 */
1078/** VMCS revision identifier used by the processor. */
1079#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) ((a) & 0x7FFFFFFF)
1080/** Size of the VMCS. */
1081#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0x1FFF)
1082/** Width of physical address used for the VMCS.
1083 * 0 -> limited to the available amount of physical ram
1084 * 1 -> within the first 4 GB
1085 */
1086#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1087/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1088#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1089/** Memory type that must be used for the VMCS. */
1090#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1091/** Whether the processor provides additional information for exits due to INS/OUTS. */
1092#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1093/** @} */
1094
1095
1096/** @name VMX MSRs - Misc VMX info.
1097 * @{
1098 */
1099/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1100#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1101/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1102#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1103/** Activity states supported by the implementation. */
1104#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1105/** Number of CR3 target values supported by the processor. (0-256) */
1106#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1107/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
1108#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1109/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1110#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1111/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1112#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1113/** Whether VMWRITE can be used to write VM-exit information fields. */
1114#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1115/** MSEG revision identifier used by the processor. */
1116#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1117/** @} */
1118
1119
1120/** @name VMX MSRs - VMCS enumeration field info
1121 * @{
1122 */
1123/** Highest field index. */
1124#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1125/** @} */
1126
1127
1128/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1129 * @{
1130 */
1131#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1132#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
1133#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
1134#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
1135#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
1136#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
1137#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
1138#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
1139#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1140#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
1141#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
1142#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
1143#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1144#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
1145#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
1146#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
1147#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
1148#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1149#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1150#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1151#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1152#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1153#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1154#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1155#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1156
1157/** @} */
1158
1159/** @name Extended Page Table Pointer (EPTP)
1160 * @{
1161 */
1162/** Uncachable EPT paging structure memory type. */
1163#define VMX_EPT_MEMTYPE_UC 0
1164/** Write-back EPT paging structure memory type. */
1165#define VMX_EPT_MEMTYPE_WB 6
1166/** Shift value to get the EPT page walk length (bits 5-3) */
1167#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1168/** Mask value to get the EPT page walk length (bits 5-3) */
1169#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1170/** Default EPT page-walk length (1 less than the actual EPT page-walk
1171 * length) */
1172#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1173/** @} */
1174
1175
1176/** @name VMCS field encoding - 16 bits guest fields
1177 * @{
1178 */
1179#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
1180#define VMX_VMCS16_GUEST_FIELD_ES 0x800
1181#define VMX_VMCS16_GUEST_FIELD_CS 0x802
1182#define VMX_VMCS16_GUEST_FIELD_SS 0x804
1183#define VMX_VMCS16_GUEST_FIELD_DS 0x806
1184#define VMX_VMCS16_GUEST_FIELD_FS 0x808
1185#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
1186#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
1187#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
1188/** @} */
1189
1190/** @name VMCS field encoding - 16 bits host fields
1191 * @{
1192 */
1193#define VMX_VMCS16_HOST_FIELD_ES 0xC00
1194#define VMX_VMCS16_HOST_FIELD_CS 0xC02
1195#define VMX_VMCS16_HOST_FIELD_SS 0xC04
1196#define VMX_VMCS16_HOST_FIELD_DS 0xC06
1197#define VMX_VMCS16_HOST_FIELD_FS 0xC08
1198#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
1199#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
1200/** @} */
1201
1202/** @name VMCS field encoding - 64 bits host fields
1203 * @{
1204 */
1205#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
1206#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
1207#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
1208#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
1209#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
1210#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
1211/** @} */
1212
1213
1214/** @name VMCS field encoding - 64 Bits control fields
1215 * @{
1216 */
1217#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1218#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1219#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1220#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1221
1222/* Optional */
1223#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1224#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1225
1226#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1227#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1228#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1229#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1230
1231#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1232#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1233
1234#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1235#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1236
1237#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1238#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1239
1240/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1241#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1242#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1243
1244/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1245#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1246#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1247
1248/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1249#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1250#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1251
1252/** Extended page table pointer. */
1253#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1254#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1255
1256/** Extended page table pointer lists. */
1257#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1258#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1259
1260/** VM-exit guest phyiscal address. */
1261#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1262#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1263/** @} */
1264
1265
1266/** @name VMCS field encoding - 64 Bits guest fields
1267 * @{
1268 */
1269#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1270#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1271#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
1272#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
1273#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1274#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1275#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1276#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1277#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
1278#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
1279#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1280#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1281#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1282#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1283#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1284#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1285#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1286#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1287/** @} */
1288
1289
1290/** @name VMCS field encoding - 32 Bits control fields
1291 * @{
1292 */
1293#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1294#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1295#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1296#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1297#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1298#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1299#define VMX_VMCS32_CTRL_EXIT 0x400C
1300#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1301#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1302#define VMX_VMCS32_CTRL_ENTRY 0x4012
1303#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1304#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1305#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1306#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1307#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1308#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1309/** @} */
1310
1311
1312/** @name VMX_VMCS_CTRL_PIN_EXEC
1313 * @{
1314 */
1315/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1316#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1317/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1318#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1319/** Virtual NMIs. */
1320#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1321/** Activate VMX preemption timer. */
1322#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1323/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1324/** @} */
1325
1326/** @name VMX_VMCS_CTRL_PROC_EXEC
1327 * @{
1328 */
1329/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
1330#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1331/** Use timestamp counter offset. */
1332#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1333/** VM Exit when executing the HLT instruction. */
1334#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1335/** VM Exit when executing the INVLPG instruction. */
1336#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1337/** VM Exit when executing the MWAIT instruction. */
1338#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1339/** VM Exit when executing the RDPMC instruction. */
1340#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1341/** VM Exit when executing the RDTSC/RDTSCP instruction. */
1342#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1343/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1344#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1345/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1346#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1347/** VM Exit on CR8 loads. */
1348#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1349/** VM Exit on CR8 stores. */
1350#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1351/** Use TPR shadow. */
1352#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1353/** VM Exit when virtual nmi blocking is disabled. */
1354#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1355/** VM Exit when executing a MOV DRx instruction. */
1356#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1357/** VM Exit when executing IO instructions. */
1358#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1359/** Use IO bitmaps. */
1360#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1361/** Monitor trap flag. */
1362#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1363/** Use MSR bitmaps. */
1364#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1365/** VM Exit when executing the MONITOR instruction. */
1366#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1367/** VM Exit when executing the PAUSE instruction. */
1368#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1369/** Determines whether the secondary processor based VM-execution controls are used. */
1370#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1371/** @} */
1372
1373/** @name VMX_VMCS_CTRL_PROC_EXEC2
1374 * @{
1375 */
1376/** Virtualize APIC access. */
1377#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1378/** EPT supported/enabled. */
1379#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1380/** Descriptor table instructions cause VM-exits. */
1381#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1382/** RDTSCP supported/enabled. */
1383#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1384/** Virtualize x2APIC mode. */
1385#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1386/** VPID supported/enabled. */
1387#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1388/** VM Exit when executing the WBINVD instruction. */
1389#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1390/** Unrestricted guest execution. */
1391#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1392/** A specified nr of pause loops cause a VM-exit. */
1393#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1394/** VM Exit when executing RDRAND instructions. */
1395#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1396/** Enables INVPCID instructions. */
1397#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1398/** Enables VMFUNC instructions. */
1399#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1400/** @} */
1401
1402
1403/** @name VMX_VMCS_CTRL_ENTRY
1404 * @{
1405 */
1406/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1407#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1408/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1409#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1410/** In SMM mode after VM-entry. */
1411#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1412/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1413#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1414/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
1415#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1416/** Whether the guest IA32_PAT MSR is loaded on VM entry. */
1417#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1418/** Whether the guest IA32_EFER MSR is loaded on VM entry. */
1419#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1420/** @} */
1421
1422
1423/** @name VMX_VMCS_CTRL_EXIT
1424 * @{
1425 */
1426/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1427#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1428/** Return to long mode after a VM-exit. */
1429#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1430/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
1431#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1432/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1433#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1434/** Whether the guest IA32_PAT MSR is saved on VM exit. */
1435#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1436/** Whether the host IA32_PAT MSR is loaded on VM exit. */
1437#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1438/** Whether the guest IA32_EFER MSR is saved on VM exit. */
1439#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1440/** Whether the host IA32_EFER MSR is loaded on VM exit. */
1441#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1442/** Whether the value of the VMX preemption timer is saved on every VM exit. */
1443#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1444/** @} */
1445
1446
1447/** @name VMX_VMCS_CTRL_VMFUNC
1448 * @{
1449 */
1450/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1451#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1452/** @} */
1453
1454
1455/** @name VMCS field encoding - 32 Bits read-only fields
1456 * @{
1457 */
1458#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1459#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1460#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1461#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1462#define VMX_VMCS32_RO_IDT_INFO 0x4408
1463#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1464#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1465#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1466/** @} */
1467
1468/** @name VMX_VMCS32_RO_EXIT_REASON
1469 * @{
1470 */
1471#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
1472/** @} */
1473
1474/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1475 * @{
1476 */
1477#define VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1478#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1479#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1480/** @} */
1481
1482
1483/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1484 * @{
1485 */
1486#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) ((a) & 0xff)
1487#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1488#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1489#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1490#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1491#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) ((a) & RT_BIT(12))
1492#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1493#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1494/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1495#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
1496/** @} */
1497
1498/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1499 * @{
1500 */
1501#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1502#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1503#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1504#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4
1505#define VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT 5
1506#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1507/** @} */
1508
1509/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1510 * @{
1511 */
1512#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
1513#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1514#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1515#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1516#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1517#define VMX_IDT_VECTORING_INFO_VALID(a) ((a) & RT_BIT(31))
1518#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
1519/** @} */
1520
1521/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1522 * @{
1523 */
1524#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1525#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1526#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1527#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1528#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1529#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1530/** @} */
1531
1532
1533/** @name VMCS field encoding - 32 Bits guest state fields
1534 * @{
1535 */
1536#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1537#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1538#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1539#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1540#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1541#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1542#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1543#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1544#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1545#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1546#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1547#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1548#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1549#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1550#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1551#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1552#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1553#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1554#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1555#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1556#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
1557#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1558/** @} */
1559
1560
1561/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1562 * @{
1563 */
1564/** The logical processor is active. */
1565#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1566/** The logical processor is inactive, because executed a HLT instruction. */
1567#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1568/** The logical processor is inactive, because of a triple fault or other serious error. */
1569#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1570/** The logical processor is inactive, because it's waiting for a startup-IPI */
1571#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1572/** @} */
1573
1574
1575/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1576 * @{
1577 */
1578#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1579#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1580#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1581#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1582/** @} */
1583
1584
1585/** @name VMCS field encoding - 32 Bits host state fields
1586 * @{
1587 */
1588#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1589/** @} */
1590
1591/** @name Natural width control fields
1592 * @{
1593 */
1594#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1595#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1596#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1597#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1598#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1599#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1600#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1601#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1602/** @} */
1603
1604
1605/** @name Natural width read-only data fields
1606 * @{
1607 */
1608#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1609#define VMX_VMCS_RO_IO_RCX 0x6402
1610#define VMX_VMCS_RO_IO_RSX 0x6404
1611#define VMX_VMCS_RO_IO_RDI 0x6406
1612#define VMX_VMCS_RO_IO_RIP 0x6408
1613#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1614/** @} */
1615
1616
1617/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1618 * @{
1619 */
1620/** 0-2: Debug register number */
1621#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) ((a) & 7)
1622/** 3: Reserved; cleared to 0. */
1623#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) (((a) >> 3) & 1)
1624/** 4: Direction of move (0 = write, 1 = read) */
1625#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) (((a) >> 4) & 1)
1626/** 5-7: Reserved; cleared to 0. */
1627#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) (((a) >> 5) & 7)
1628/** 8-11: General purpose register number. */
1629#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) (((a) >> 8) & 0xF)
1630/** Rest: reserved. */
1631/** @} */
1632
1633/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1634 * @{
1635 */
1636#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1637#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1638/** @} */
1639
1640
1641
1642/** @name CRx accesses
1643 * @{
1644 */
1645/** 0-3: Control register number (0 for CLTS & LMSW) */
1646#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) ((a) & 0xF)
1647/** 4-5: Access type. */
1648#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) (((a) >> 4) & 3)
1649/** 6: LMSW operand type */
1650#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) (((a) >> 6) & 1)
1651/** 7: Reserved; cleared to 0. */
1652#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) (((a) >> 7) & 1)
1653/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1654#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) (((a) >> 8) & 0xF)
1655/** 12-15: Reserved; cleared to 0. */
1656#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) (((a) >> 12) & 0xF)
1657/** 16-31: LMSW source data (else 0). */
1658#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) (((a) >> 16) & 0xFFFF)
1659/** Rest: reserved. */
1660/** @} */
1661
1662/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1663 * @{
1664 */
1665#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1666#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1667#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1668#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1669/** @} */
1670
1671/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1672 * @{
1673 */
1674#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
1675#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
1676/** Task switch caused by a call instruction. */
1677#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1678/** Task switch caused by an iret instruction. */
1679#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1680/** Task switch caused by a jmp instruction. */
1681#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1682/** Task switch caused by an interrupt gate. */
1683#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1684/** @} */
1685
1686
1687/** @name VMX_EXIT_EPT_VIOLATION
1688 * @{
1689 */
1690/** Set if the violation was caused by a data read. */
1691#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1692/** Set if the violation was caused by a data write. */
1693#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1694/** Set if the violation was caused by an insruction fetch. */
1695#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1696/** AND of the present bit of all EPT structures. */
1697#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1698/** AND of the write bit of all EPT structures. */
1699#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1700/** AND of the execute bit of all EPT structures. */
1701#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1702/** Set if the guest linear address field contains the faulting address. */
1703#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1704/** If bit 7 is one: (reserved otherwise)
1705 * 1 - violation due to physical address access.
1706 * 0 - violation caused by page walk or access/dirty bit updates
1707 */
1708#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1709/** @} */
1710
1711
1712/** @name VMX_EXIT_PORT_IO
1713 * @{
1714 */
1715/** 0-2: IO operation width. */
1716#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1717/** 3: IO operation direction. */
1718#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1719/** 4: String IO operation (INS / OUTS). */
1720#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1721/** 5: Repeated IO operation. */
1722#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1723/** 6: Operand encoding. */
1724#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1725/** 16-31: IO Port (0-0xffff). */
1726#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1727/* Rest reserved. */
1728/** @} */
1729
1730/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1731 * @{
1732 */
1733#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1734#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1735/** @} */
1736
1737
1738/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1739 * @{
1740 */
1741#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1742#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1743/** @} */
1744
1745/** @name VMX_EXIT_APIC_ACCESS
1746 * @{
1747 */
1748/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1749#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1750/** 12-15: Access type. */
1751#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000)
1752/* Rest reserved. */
1753/** @} */
1754
1755
1756/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1757 * @{
1758 */
1759/** Linear read access. */
1760#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1761/** Linear write access. */
1762#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1763/** Linear instruction fetch access. */
1764#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1765/** Linear read/write access during event delivery. */
1766#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1767/** Physical read/write access during event delivery. */
1768#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1769/** Physical access for an instruction fetch or during instruction execution. */
1770#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1771/** @} */
1772
1773/** @} */
1774
1775/** @name VMCS field encoding - Natural width guest state fields
1776 * @{
1777 */
1778#define VMX_VMCS_GUEST_CR0 0x6800
1779#define VMX_VMCS_GUEST_CR3 0x6802
1780#define VMX_VMCS_GUEST_CR4 0x6804
1781#define VMX_VMCS_GUEST_ES_BASE 0x6806
1782#define VMX_VMCS_GUEST_CS_BASE 0x6808
1783#define VMX_VMCS_GUEST_SS_BASE 0x680A
1784#define VMX_VMCS_GUEST_DS_BASE 0x680C
1785#define VMX_VMCS_GUEST_FS_BASE 0x680E
1786#define VMX_VMCS_GUEST_GS_BASE 0x6810
1787#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1788#define VMX_VMCS_GUEST_TR_BASE 0x6814
1789#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1790#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1791#define VMX_VMCS_GUEST_DR7 0x681A
1792#define VMX_VMCS_GUEST_RSP 0x681C
1793#define VMX_VMCS_GUEST_RIP 0x681E
1794#define VMX_VMCS_GUEST_RFLAGS 0x6820
1795#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1796#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1797#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1798/** @} */
1799
1800
1801/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1802 * @{
1803 */
1804/** Hardware breakpoint 0 was met. */
1805#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1806/** Hardware breakpoint 1 was met. */
1807#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1808/** Hardware breakpoint 2 was met. */
1809#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1810/** Hardware breakpoint 3 was met. */
1811#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1812/** At least one data or IO breakpoint was hit. */
1813#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1814/** A debug exception would have been triggered by single-step execution mode. */
1815#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1816/** Bits 4-11, 13 and 15-63 are reserved. */
1817
1818/** @} */
1819
1820/** @name VMCS field encoding - Natural width host state fields
1821 * @{
1822 */
1823#define VMX_VMCS_HOST_CR0 0x6C00
1824#define VMX_VMCS_HOST_CR3 0x6C02
1825#define VMX_VMCS_HOST_CR4 0x6C04
1826#define VMX_VMCS_HOST_FS_BASE 0x6C06
1827#define VMX_VMCS_HOST_GS_BASE 0x6C08
1828#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1829#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1830#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1831#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1832#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1833#define VMX_VMCS_HOST_RSP 0x6C14
1834#define VMX_VMCS_HOST_RIP 0x6C16
1835/** @} */
1836
1837/** @} */
1838
1839
1840/** @defgroup grp_vmx_asm vmx assembly helpers
1841 * @ingroup grp_vmx
1842 * @{
1843 */
1844
1845/**
1846 * Restores some host-state fields that need not be done on every VM-exit.
1847 *
1848 * @returns VBox status code.
1849 * @param fRestoreHostFlags Flags of which host registers needs to be
1850 * restored.
1851 * @param pRestoreHost Pointer to the host-restore structure.
1852 */
1853DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1854
1855
1856/**
1857 * Dispatches an NMI to the host.
1858 */
1859DECLASM(int) VMXDispatchHostNmi(void);
1860
1861
1862/**
1863 * Executes VMXON
1864 *
1865 * @returns VBox status code
1866 * @param pVMXOn Physical address of VMXON structure
1867 */
1868#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1869DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1870#else
1871DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1872{
1873# if RT_INLINE_ASM_GNU_STYLE
1874 int rc = VINF_SUCCESS;
1875 __asm__ __volatile__ (
1876 "push %3 \n\t"
1877 "push %2 \n\t"
1878 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1879 "ja 2f \n\t"
1880 "je 1f \n\t"
1881 "movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1882 "jmp 2f \n\t"
1883 "1: \n\t"
1884 "movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1885 "2: \n\t"
1886 "add $8, %%esp \n\t"
1887 :"=rm"(rc)
1888 :"0"(VINF_SUCCESS),
1889 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1890 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1891 :"memory"
1892 );
1893 return rc;
1894
1895# elif VMX_USE_MSC_INTRINSICS
1896 unsigned char rcMsc = __vmx_on(&pVMXOn);
1897 if (RT_LIKELY(rcMsc == 0))
1898 return VINF_SUCCESS;
1899 return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
1900
1901# else
1902 int rc = VINF_SUCCESS;
1903 __asm
1904 {
1905 push dword ptr [pVMXOn+4]
1906 push dword ptr [pVMXOn]
1907 _emit 0xF3
1908 _emit 0x0F
1909 _emit 0xC7
1910 _emit 0x34
1911 _emit 0x24 /* VMXON [esp] */
1912 jnc vmxon_good
1913 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1914 jmp the_end
1915
1916vmxon_good:
1917 jnz the_end
1918 mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1919the_end:
1920 add esp, 8
1921 }
1922 return rc;
1923# endif
1924}
1925#endif
1926
1927
1928/**
1929 * Executes VMXOFF
1930 */
1931#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1932DECLASM(void) VMXDisable(void);
1933#else
1934DECLINLINE(void) VMXDisable(void)
1935{
1936# if RT_INLINE_ASM_GNU_STYLE
1937 __asm__ __volatile__ (
1938 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1939 );
1940
1941# elif VMX_USE_MSC_INTRINSICS
1942 __vmx_off();
1943
1944# else
1945 __asm
1946 {
1947 _emit 0x0F
1948 _emit 0x01
1949 _emit 0xC4 /* VMXOFF */
1950 }
1951# endif
1952}
1953#endif
1954
1955
1956/**
1957 * Executes VMCLEAR
1958 *
1959 * @returns VBox status code
1960 * @param pVMCS Physical address of VM control structure
1961 */
1962#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1963DECLASM(int) VMXClearVmcs(RTHCPHYS pVMCS);
1964#else
1965DECLINLINE(int) VMXClearVmcs(RTHCPHYS pVMCS)
1966{
1967# if RT_INLINE_ASM_GNU_STYLE
1968 int rc = VINF_SUCCESS;
1969 __asm__ __volatile__ (
1970 "push %3 \n\t"
1971 "push %2 \n\t"
1972 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1973 "jnc 1f \n\t"
1974 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1975 "1: \n\t"
1976 "add $8, %%esp \n\t"
1977 :"=rm"(rc)
1978 :"0"(VINF_SUCCESS),
1979 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1980 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1981 :"memory"
1982 );
1983 return rc;
1984
1985# elif VMX_USE_MSC_INTRINSICS
1986 unsigned char rcMsc = __vmx_vmclear(&pVMCS);
1987 if (RT_LIKELY(rcMsc == 0))
1988 return VINF_SUCCESS;
1989 return VERR_VMX_INVALID_VMCS_PTR;
1990
1991# else
1992 int rc = VINF_SUCCESS;
1993 __asm
1994 {
1995 push dword ptr [pVMCS+4]
1996 push dword ptr [pVMCS]
1997 _emit 0x66
1998 _emit 0x0F
1999 _emit 0xC7
2000 _emit 0x34
2001 _emit 0x24 /* VMCLEAR [esp] */
2002 jnc success
2003 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2004success:
2005 add esp, 8
2006 }
2007 return rc;
2008# endif
2009}
2010#endif
2011
2012
2013/**
2014 * Executes VMPTRLD
2015 *
2016 * @returns VBox status code
2017 * @param pVMCS Physical address of VMCS structure
2018 */
2019#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2020DECLASM(int) VMXActivateVmcs(RTHCPHYS pVMCS);
2021#else
2022DECLINLINE(int) VMXActivateVmcs(RTHCPHYS pVMCS)
2023{
2024# if RT_INLINE_ASM_GNU_STYLE
2025 int rc = VINF_SUCCESS;
2026 __asm__ __volatile__ (
2027 "push %3 \n\t"
2028 "push %2 \n\t"
2029 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2030 "jnc 1f \n\t"
2031 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2032 "1: \n\t"
2033 "add $8, %%esp \n\t"
2034 :"=rm"(rc)
2035 :"0"(VINF_SUCCESS),
2036 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
2037 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
2038 );
2039 return rc;
2040
2041# elif VMX_USE_MSC_INTRINSICS
2042 unsigned char rcMsc = __vmx_vmptrld(&pVMCS);
2043 if (RT_LIKELY(rcMsc == 0))
2044 return VINF_SUCCESS;
2045 return VERR_VMX_INVALID_VMCS_PTR;
2046
2047# else
2048 int rc = VINF_SUCCESS;
2049 __asm
2050 {
2051 push dword ptr [pVMCS+4]
2052 push dword ptr [pVMCS]
2053 _emit 0x0F
2054 _emit 0xC7
2055 _emit 0x34
2056 _emit 0x24 /* VMPTRLD [esp] */
2057 jnc success
2058 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2059
2060success:
2061 add esp, 8
2062 }
2063 return rc;
2064# endif
2065}
2066#endif
2067
2068/**
2069 * Executes VMPTRST
2070 *
2071 * @returns VBox status code
2072 * @param pVMCS Address that will receive the current pointer
2073 */
2074DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pVMCS);
2075
2076/**
2077 * Executes VMWRITE
2078 *
2079 * @returns VBox status code
2080 * @retval VINF_SUCCESS
2081 * @retval VERR_VMX_INVALID_VMCS_PTR
2082 * @retval VERR_VMX_INVALID_VMCS_FIELD
2083 *
2084 * @param idxField VMCS index
2085 * @param u32Val 32 bits value
2086 *
2087 * @remarks The values of the two status codes can be ORed together, the result
2088 * will be VERR_VMX_INVALID_VMCS_PTR.
2089 */
2090#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2091DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2092#else
2093DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2094{
2095# if RT_INLINE_ASM_GNU_STYLE
2096 int rc = VINF_SUCCESS;
2097 __asm__ __volatile__ (
2098 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2099 "ja 2f \n\t"
2100 "je 1f \n\t"
2101 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2102 "jmp 2f \n\t"
2103 "1: \n\t"
2104 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2105 "2: \n\t"
2106 :"=rm"(rc)
2107 :"0"(VINF_SUCCESS),
2108 "a"(idxField),
2109 "d"(u32Val)
2110 );
2111 return rc;
2112
2113# elif VMX_USE_MSC_INTRINSICS
2114 unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2115 if (RT_LIKELY(rcMsc == 0))
2116 return VINF_SUCCESS;
2117 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2118
2119#else
2120 int rc = VINF_SUCCESS;
2121 __asm
2122 {
2123 push dword ptr [u32Val]
2124 mov eax, [idxField]
2125 _emit 0x0F
2126 _emit 0x79
2127 _emit 0x04
2128 _emit 0x24 /* VMWRITE eax, [esp] */
2129 jnc valid_vmcs
2130 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2131 jmp the_end
2132
2133valid_vmcs:
2134 jnz the_end
2135 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2136the_end:
2137 add esp, 4
2138 }
2139 return rc;
2140# endif
2141}
2142#endif
2143
2144/**
2145 * Executes VMWRITE
2146 *
2147 * @returns VBox status code
2148 * @retval VINF_SUCCESS
2149 * @retval VERR_VMX_INVALID_VMCS_PTR
2150 * @retval VERR_VMX_INVALID_VMCS_FIELD
2151 *
2152 * @param idxField VMCS index
2153 * @param u64Val 16, 32 or 64 bits value
2154 *
2155 * @remarks The values of the two status codes can be ORed together, the result
2156 * will be VERR_VMX_INVALID_VMCS_PTR.
2157 */
2158#if !defined(RT_ARCH_X86) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2159# if !VMX_USE_MSC_INTRINSICS || ARCH_BITS != 64
2160DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2161# else /* VMX_USE_MSC_INTRINSICS */
2162DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2163{
2164 unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2165 if (RT_LIKELY(rcMsc == 0))
2166 return VINF_SUCCESS;
2167 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2168}
2169# endif /* VMX_USE_MSC_INTRINSICS */
2170#else
2171# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2172VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2173#endif
2174
2175#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2176# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
2177 VMXWriteVmcs64(idxField, uVal) \
2178 : VMXWriteVmcs32(idxField, uVal)
2179# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
2180 VMXWriteVmcs64(idxField, u64Val) \
2181 : VMXWriteVmcs32(idxField, u64Val)
2182#elif ARCH_BITS == 32
2183# define VMXWriteVmcsHstN VMXWriteVmcs32
2184# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2185# else /* ARCH_BITS == 64 */
2186# define VMXWriteVmcsHstN VMXWriteVmcs64
2187# define VMXWriteVmcsGstN VMXWriteVmcs64
2188# endif
2189
2190
2191/**
2192 * Invalidate a page using invept
2193 * @returns VBox status code
2194 * @param enmFlush Type of flush
2195 * @param pDescriptor Descriptor
2196 */
2197DECLASM(int) VMXR0InvEPT(VMXFLUSHEPT enmFlush, uint64_t *pDescriptor);
2198
2199/**
2200 * Invalidate a page using invvpid
2201 * @returns VBox status code
2202 * @param enmFlush Type of flush
2203 * @param pDescriptor Descriptor
2204 */
2205DECLASM(int) VMXR0InvVPID(VMXFLUSHVPID enmFlush, uint64_t *pDescriptor);
2206
2207/**
2208 * Executes VMREAD
2209 *
2210 * @returns VBox status code
2211 * @retval VINF_SUCCESS
2212 * @retval VERR_VMX_INVALID_VMCS_PTR
2213 * @retval VERR_VMX_INVALID_VMCS_FIELD
2214 *
2215 * @param idxField VMCS index
2216 * @param pData Ptr to store VM field value
2217 *
2218 * @remarks The values of the two status codes can be ORed together, the result
2219 * will be VERR_VMX_INVALID_VMCS_PTR.
2220 */
2221#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2222DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2223#else
2224DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2225{
2226# if RT_INLINE_ASM_GNU_STYLE
2227 int rc = VINF_SUCCESS;
2228 __asm__ __volatile__ (
2229 "movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2230 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2231 "ja 2f \n\t"
2232 "je 1f \n\t"
2233 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2234 "jmp 2f \n\t"
2235 "1: \n\t"
2236 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2237 "2: \n\t"
2238 :"=&r"(rc),
2239 "=d"(*pData)
2240 :"a"(idxField),
2241 "d"(0)
2242 );
2243 return rc;
2244
2245# elif VMX_USE_MSC_INTRINSICS
2246 unsigned char rcMsc;
2247# if ARCH_BITS == 32
2248 rcMsc = __vmx_vmread(idxField, pData);
2249# else
2250 uint64_t u64Tmp;
2251 rcMsc = __vmx_vmread(idxField, &u64Tmp);
2252 *pData = (uint32_t)u64Tmp;
2253# endif
2254 if (RT_LIKELY(rcMsc == 0))
2255 return VINF_SUCCESS;
2256 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2257
2258#else
2259 int rc = VINF_SUCCESS;
2260 __asm
2261 {
2262 sub esp, 4
2263 mov dword ptr [esp], 0
2264 mov eax, [idxField]
2265 _emit 0x0F
2266 _emit 0x78
2267 _emit 0x04
2268 _emit 0x24 /* VMREAD eax, [esp] */
2269 mov edx, pData
2270 pop dword ptr [edx]
2271 jnc valid_vmcs
2272 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2273 jmp the_end
2274
2275valid_vmcs:
2276 jnz the_end
2277 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2278the_end:
2279 }
2280 return rc;
2281# endif
2282}
2283#endif
2284
2285/**
2286 * Executes VMREAD
2287 *
2288 * @returns VBox status code
2289 * @retval VINF_SUCCESS
2290 * @retval VERR_VMX_INVALID_VMCS_PTR
2291 * @retval VERR_VMX_INVALID_VMCS_FIELD
2292 *
2293 * @param idxField VMCS index
2294 * @param pData Ptr to store VM field value
2295 *
2296 * @remarks The values of the two status codes can be ORed together, the result
2297 * will be VERR_VMX_INVALID_VMCS_PTR.
2298 */
2299#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2300DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2301#else
2302DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2303{
2304# if VMX_USE_MSC_INTRINSICS
2305 unsigned char rcMsc;
2306# if ARCH_BITS == 32
2307 size_t uLow;
2308 size_t uHigh;
2309 rcMsc = __vmx_vmread(idxField, &uLow);
2310 rcMsc |= __vmx_vmread(idxField + 1, &uHigh);
2311 *pData = RT_MAKE_U64(uLow, uHigh);
2312# else
2313 rcMsc = __vmx_vmread(idxField, pData);
2314# endif
2315 if (RT_LIKELY(rcMsc == 0))
2316 return VINF_SUCCESS;
2317 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2318
2319# elif ARCH_BITS == 32
2320 int rc;
2321 uint32_t val_hi, val;
2322 rc = VMXReadVmcs32(idxField, &val);
2323 rc |= VMXReadVmcs32(idxField + 1, &val_hi);
2324 AssertRC(rc);
2325 *pData = RT_MAKE_U64(val, val_hi);
2326 return rc;
2327
2328# else
2329# error "Shouldn't be here..."
2330# endif
2331}
2332#endif
2333
2334/**
2335 * Gets the last instruction error value from the current VMCS
2336 *
2337 * @returns error value
2338 */
2339DECLINLINE(uint32_t) VMXGetLastError(void)
2340{
2341#if ARCH_BITS == 64
2342 uint64_t uLastError = 0;
2343 int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2344 AssertRC(rc);
2345 return (uint32_t)uLastError;
2346
2347#else /* 32-bit host: */
2348 uint32_t uLastError = 0;
2349 int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2350 AssertRC(rc);
2351 return uLastError;
2352#endif
2353}
2354
2355#ifdef IN_RING0
2356VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2357VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2358#endif /* IN_RING0 */
2359
2360/** @} */
2361
2362#endif
2363
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