VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 53615

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1/** @file
2 * HM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2014 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vmx_h
27#define ___VBox_vmm_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/x86.h>
32#include <iprt/assert.h>
33
34/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35 when targeting AMD64. */
36#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37# include <intrin.h>
38/* We always want them as intrinsics, no functions. */
39# pragma intrinsic(__vmx_on)
40# pragma intrinsic(__vmx_off)
41# pragma intrinsic(__vmx_vmclear)
42# pragma intrinsic(__vmx_vmptrld)
43# pragma intrinsic(__vmx_vmread)
44# pragma intrinsic(__vmx_vmwrite)
45# define VMX_USE_MSC_INTRINSICS 1
46#else
47# define VMX_USE_MSC_INTRINSICS 0
48#endif
49
50
51/** @defgroup grp_vmx vmx Types and Definitions
52 * @ingroup grp_hm
53 * @{
54 */
55
56/** @def HMVMXCPU_GST_SET_UPDATED
57 * Sets a guest-state-updated flag.
58 *
59 * @param pVCpu Pointer to the VMCPU.
60 * @param fFlag The flag to set.
61 */
62#define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
63
64/** @def HMVMXCPU_GST_IS_SET
65 * Checks if all the flags in the specified guest-state-updated set is pending.
66 *
67 * @param pVCpu Pointer to the VMCPU.
68 * @param fFlag The flag to check.
69 */
70#define HMVMXCPU_GST_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
71
72/** @def HMVMXCPU_GST_IS_UPDATED
73 * Checks if one or more of the flags in the specified guest-state-updated set
74 * is updated.
75 *
76 * @param pVCpu Pointer to the VMCPU.
77 * @param fFlags The flags to check for.
78 */
79#define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
80
81/** @def HMVMXCPU_GST_RESET_TO
82 * Resets the guest-state-updated flags to the specified value.
83 *
84 * @param pVCpu Pointer to the VMCPU.
85 * @param fFlags The new value.
86 */
87#define HMVMXCPU_GST_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlags)))
88
89/** @def HMVMXCPU_GST_VALUE
90 * Returns the current guest-state-updated flags value.
91 *
92 * @param pVCpu Pointer to the VMCPU.
93 */
94#define HMVMXCPU_GST_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState))
95
96/** @name Host-state restoration flags.
97 * @note If you change these values don't forget to update the assembly
98 * defines as well!
99 * @{
100 */
101#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
102#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
103#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
104#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
105#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
106#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
107#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
108#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
109#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
110/** @} */
111
112/**
113 * Host-state restoration structure.
114 * This holds host-state fields that require manual restoration.
115 * Assembly version found in hm_vmx.mac (should be automatically verified).
116 */
117typedef struct VMXRESTOREHOST
118{
119 RTSEL uHostSelDS; /* 0x00 */
120 RTSEL uHostSelES; /* 0x02 */
121 RTSEL uHostSelFS; /* 0x04 */
122 RTSEL uHostSelGS; /* 0x06 */
123 RTSEL uHostSelTR; /* 0x08 */
124 uint8_t abPadding0[4];
125 X86XDTR64 HostGdtr; /**< 0x0e - should be aligned by it's 64-bit member. */
126 uint8_t abPadding1[6];
127 X86XDTR64 HostIdtr; /**< 0x1e - should be aligned by it's 64-bit member. */
128 uint64_t uHostFSBase; /* 0x28 */
129 uint64_t uHostGSBase; /* 0x30 */
130} VMXRESTOREHOST;
131/** Pointer to VMXRESTOREHOST. */
132typedef VMXRESTOREHOST *PVMXRESTOREHOST;
133AssertCompileSize(X86XDTR64, 10);
134AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
135AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
136AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
137AssertCompileSize(VMXRESTOREHOST, 56);
138AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
139
140/** @name Host-state MSR lazy-restoration flags.
141 * @{
142 */
143/** The host MSRs have been saved. */
144#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
145/** The guest MSRs are loaded and in effect. */
146#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
147/** @} */
148
149/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
150 * UFC = Unsupported Feature Combination.
151 * @{
152 */
153/** Unsupported pin-based VM-execution controls combo. */
154#define VMX_UFC_CTRL_PIN_EXEC 0
155/** Unsupported processor-based VM-execution controls combo. */
156#define VMX_UFC_CTRL_PROC_EXEC 1
157/** Unsupported pin-based VM-execution controls combo. */
158#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 2
159/** Unsupported VM-entry controls combo. */
160#define VMX_UFC_CTRL_ENTRY 3
161/** Unsupported VM-exit controls combo. */
162#define VMX_UFC_CTRL_EXIT 4
163/** MSR storage capacity of the VMCS autoload/store area is not sufficient
164 * for storing host MSRs. */
165#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 5
166/** MSR storage capacity of the VMCS autoload/store area is not sufficient
167 * for storing guest MSRs. */
168#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 6
169/** Invalid VMCS size. */
170#define VMX_UFC_INVALID_VMCS_SIZE 7
171/** Unsupported secondary processor-based VM-execution controls combo. */
172#define VMX_UFC_CTRL_PROC_EXEC2 8
173/** Invalid unrestricted-guest execution controls combo. */
174#define VMX_UFC_INVALID_UX_COMBO 9
175/** @} */
176
177/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
178 * IGS = Invalid Guest State.
179 * @{
180 */
181/** An error occurred while checking invalid-guest-state. */
182#define VMX_IGS_ERROR 0
183/** The invalid guest-state checks did not find any reason why. */
184#define VMX_IGS_REASON_NOT_FOUND 1
185/** CR0 fixed1 bits invalid. */
186#define VMX_IGS_CR0_FIXED1 2
187/** CR0 fixed0 bits invalid. */
188#define VMX_IGS_CR0_FIXED0 3
189/** CR0.PE and CR0.PE invalid VT-x/host combination. */
190#define VMX_IGS_CR0_PG_PE_COMBO 4
191/** CR4 fixed1 bits invalid. */
192#define VMX_IGS_CR4_FIXED1 5
193/** CR4 fixed0 bits invalid. */
194#define VMX_IGS_CR4_FIXED0 6
195/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
196 * VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
197#define VMX_IGS_DEBUGCTL_MSR_RESERVED 7
198/** CR0.PG not set for long-mode when not using unrestricted guest. */
199#define VMX_IGS_CR0_PG_LONGMODE 8
200/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
201#define VMX_IGS_CR4_PAE_LONGMODE 9
202/** CR4.PCIDE set for 32-bit guest. */
203#define VMX_IGS_CR4_PCIDE 10
204/** VMCS' DR7 reserved bits not set to 0. */
205#define VMX_IGS_DR7_RESERVED 11
206/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
207#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12
208/** VMCS' EFER MSR reserved bits not set to 0. */
209#define VMX_IGS_EFER_MSR_RESERVED 13
210/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
211#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14
212/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
213 * without unrestricted guest. */
214#define VMX_IGS_EFER_LMA_LME_MISMATCH 15
215/** CS.Attr.P bit invalid. */
216#define VMX_IGS_CS_ATTR_P_INVALID 16
217/** CS.Attr reserved bits not set to 0. */
218#define VMX_IGS_CS_ATTR_RESERVED 17
219/** CS.Attr.G bit invalid. */
220#define VMX_IGS_CS_ATTR_G_INVALID 18
221/** CS is unusable. */
222#define VMX_IGS_CS_ATTR_UNUSABLE 19
223/** CS and SS DPL unequal. */
224#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20
225/** CS and SS DPL mismatch. */
226#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21
227/** CS Attr.Type invalid. */
228#define VMX_IGS_CS_ATTR_TYPE_INVALID 22
229/** CS and SS RPL unequal. */
230#define VMX_IGS_SS_CS_RPL_UNEQUAL 23
231/** SS.Attr.DPL and SS RPL unequal. */
232#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24
233/** SS.Attr.DPL invalid for segment type. */
234#define VMX_IGS_SS_ATTR_DPL_INVALID 25
235/** SS.Attr.Type invalid. */
236#define VMX_IGS_SS_ATTR_TYPE_INVALID 26
237/** SS.Attr.P bit invalid. */
238#define VMX_IGS_SS_ATTR_P_INVALID 27
239/** SS.Attr reserved bits not set to 0. */
240#define VMX_IGS_SS_ATTR_RESERVED 28
241/** SS.Attr.G bit invalid. */
242#define VMX_IGS_SS_ATTR_G_INVALID 29
243/** DS.Attr.A bit invalid. */
244#define VMX_IGS_DS_ATTR_A_INVALID 30
245/** DS.Attr.P bit invalid. */
246#define VMX_IGS_DS_ATTR_P_INVALID 31
247/** DS.Attr.DPL and DS RPL unequal. */
248#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32
249/** DS.Attr reserved bits not set to 0. */
250#define VMX_IGS_DS_ATTR_RESERVED 33
251/** DS.Attr.G bit invalid. */
252#define VMX_IGS_DS_ATTR_G_INVALID 34
253/** DS.Attr.Type invalid. */
254#define VMX_IGS_DS_ATTR_TYPE_INVALID 35
255/** ES.Attr.A bit invalid. */
256#define VMX_IGS_ES_ATTR_A_INVALID 36
257/** ES.Attr.P bit invalid. */
258#define VMX_IGS_ES_ATTR_P_INVALID 37
259/** ES.Attr.DPL and DS RPL unequal. */
260#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38
261/** ES.Attr reserved bits not set to 0. */
262#define VMX_IGS_ES_ATTR_RESERVED 39
263/** ES.Attr.G bit invalid. */
264#define VMX_IGS_ES_ATTR_G_INVALID 40
265/** ES.Attr.Type invalid. */
266#define VMX_IGS_ES_ATTR_TYPE_INVALID 41
267/** FS.Attr.A bit invalid. */
268#define VMX_IGS_FS_ATTR_A_INVALID 42
269/** FS.Attr.P bit invalid. */
270#define VMX_IGS_FS_ATTR_P_INVALID 43
271/** FS.Attr.DPL and DS RPL unequal. */
272#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44
273/** FS.Attr reserved bits not set to 0. */
274#define VMX_IGS_FS_ATTR_RESERVED 45
275/** FS.Attr.G bit invalid. */
276#define VMX_IGS_FS_ATTR_G_INVALID 46
277/** FS.Attr.Type invalid. */
278#define VMX_IGS_FS_ATTR_TYPE_INVALID 47
279/** GS.Attr.A bit invalid. */
280#define VMX_IGS_GS_ATTR_A_INVALID 48
281/** GS.Attr.P bit invalid. */
282#define VMX_IGS_GS_ATTR_P_INVALID 49
283/** GS.Attr.DPL and DS RPL unequal. */
284#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 50
285/** GS.Attr reserved bits not set to 0. */
286#define VMX_IGS_GS_ATTR_RESERVED 51
287/** GS.Attr.G bit invalid. */
288#define VMX_IGS_GS_ATTR_G_INVALID 52
289/** GS.Attr.Type invalid. */
290#define VMX_IGS_GS_ATTR_TYPE_INVALID 53
291/** V86 mode CS.Base invalid. */
292#define VMX_IGS_V86_CS_BASE_INVALID 54
293/** V86 mode CS.Limit invalid. */
294#define VMX_IGS_V86_CS_LIMIT_INVALID 55
295/** V86 mode CS.Attr invalid. */
296#define VMX_IGS_V86_CS_ATTR_INVALID 56
297/** V86 mode SS.Base invalid. */
298#define VMX_IGS_V86_SS_BASE_INVALID 57
299/** V86 mode SS.Limit invalid. */
300#define VMX_IGS_V86_SS_LIMIT_INVALID 58
301/** V86 mode SS.Attr invalid. */
302#define VMX_IGS_V86_SS_ATTR_INVALID 59
303/** V86 mode DS.Base invalid. */
304#define VMX_IGS_V86_DS_BASE_INVALID 60
305/** V86 mode DS.Limit invalid. */
306#define VMX_IGS_V86_DS_LIMIT_INVALID 61
307/** V86 mode DS.Attr invalid. */
308#define VMX_IGS_V86_DS_ATTR_INVALID 62
309/** V86 mode ES.Base invalid. */
310#define VMX_IGS_V86_ES_BASE_INVALID 63
311/** V86 mode ES.Limit invalid. */
312#define VMX_IGS_V86_ES_LIMIT_INVALID 64
313/** V86 mode ES.Attr invalid. */
314#define VMX_IGS_V86_ES_ATTR_INVALID 65
315/** V86 mode FS.Base invalid. */
316#define VMX_IGS_V86_FS_BASE_INVALID 66
317/** V86 mode FS.Limit invalid. */
318#define VMX_IGS_V86_FS_LIMIT_INVALID 67
319/** V86 mode FS.Attr invalid. */
320#define VMX_IGS_V86_FS_ATTR_INVALID 68
321/** V86 mode GS.Base invalid. */
322#define VMX_IGS_V86_GS_BASE_INVALID 69
323/** V86 mode GS.Limit invalid. */
324#define VMX_IGS_V86_GS_LIMIT_INVALID 70
325/** V86 mode GS.Attr invalid. */
326#define VMX_IGS_V86_GS_ATTR_INVALID 71
327/** Longmode CS.Base invalid. */
328#define VMX_IGS_LONGMODE_CS_BASE_INVALID 72
329/** Longmode SS.Base invalid. */
330#define VMX_IGS_LONGMODE_SS_BASE_INVALID 73
331/** Longmode DS.Base invalid. */
332#define VMX_IGS_LONGMODE_DS_BASE_INVALID 74
333/** Longmode ES.Base invalid. */
334#define VMX_IGS_LONGMODE_ES_BASE_INVALID 75
335/** SYSENTER ESP is not canonical. */
336#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76
337/** SYSENTER EIP is not canonical. */
338#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77
339/** PAT MSR invalid. */
340#define VMX_IGS_PAT_MSR_INVALID 78
341/** PAT MSR reserved bits not set to 0. */
342#define VMX_IGS_PAT_MSR_RESERVED 79
343/** GDTR.Base is not canonical. */
344#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80
345/** IDTR.Base is not canonical. */
346#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81
347/** GDTR.Limit invalid. */
348#define VMX_IGS_GDTR_LIMIT_INVALID 82
349/** IDTR.Limit invalid. */
350#define VMX_IGS_IDTR_LIMIT_INVALID 83
351/** Longmode RIP is invalid. */
352#define VMX_IGS_LONGMODE_RIP_INVALID 84
353/** RFLAGS reserved bits not set to 0. */
354#define VMX_IGS_RFLAGS_RESERVED 85
355/** RFLAGS RA1 reserved bits not set to 1. */
356#define VMX_IGS_RFLAGS_RESERVED1 86
357/** RFLAGS.VM (V86 mode) invalid. */
358#define VMX_IGS_RFLAGS_VM_INVALID 87
359/** RFLAGS.IF invalid. */
360#define VMX_IGS_RFLAGS_IF_INVALID 88
361/** Activity state invalid. */
362#define VMX_IGS_ACTIVITY_STATE_INVALID 89
363/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
364#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90
365/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
366#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91
367/** Activity state SIPI WAIT invalid. */
368#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92
369/** Interruptibility state reserved bits not set to 0. */
370#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93
371/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
372#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94
373/** Interruptibility state block-by-STI invalid for EFLAGS. */
374#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95
375/** Interruptibility state invalid while trying to deliver external
376 * interrupt. */
377#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96
378/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
379 * NMI. */
380#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97
381/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
382#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98
383/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
384#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99
385/** Interruptibilty state block-by-STI (maybe) invalid when trying to deliver
386 * an NMI. */
387#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100
388/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
389 * active. */
390#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101
391/** Pending debug exceptions reserved bits not set to 0. */
392#define VMX_IGS_PENDING_DEBUG_RESERVED 102
393/** Longmode pending debug exceptions reserved bits not set to 0. */
394#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103
395/** Pending debug exceptions.BS bit is not set when it should be. */
396#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104
397/** Pending debug exceptions.BS bit is not clear when it should be. */
398#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105
399/** VMCS link pointer reserved bits not set to 0. */
400#define VMX_IGS_VMCS_LINK_PTR_RESERVED 106
401/** TR cannot index into LDT, TI bit MBZ. */
402#define VMX_IGS_TR_TI_INVALID 107
403/** LDTR cannot index into LDT. TI bit MBZ. */
404#define VMX_IGS_LDTR_TI_INVALID 108
405/** TR.Base is not canonical. */
406#define VMX_IGS_TR_BASE_NOT_CANONICAL 109
407/** FS.Base is not canonical. */
408#define VMX_IGS_FS_BASE_NOT_CANONICAL 110
409/** GS.Base is not canonical. */
410#define VMX_IGS_GS_BASE_NOT_CANONICAL 111
411/** LDTR.Base is not canonical. */
412#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 112
413/** TR is unusable. */
414#define VMX_IGS_TR_ATTR_UNUSABLE 113
415/** TR.Attr.S bit invalid. */
416#define VMX_IGS_TR_ATTR_S_INVALID 114
417/** TR is not present. */
418#define VMX_IGS_TR_ATTR_P_INVALID 115
419/** TR.Attr reserved bits not set to 0. */
420#define VMX_IGS_TR_ATTR_RESERVED 116
421/** TR.Attr.G bit invalid. */
422#define VMX_IGS_TR_ATTR_G_INVALID 117
423/** Longmode TR.Attr.Type invalid. */
424#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 118
425/** TR.Attr.Type invalid. */
426#define VMX_IGS_TR_ATTR_TYPE_INVALID 119
427/** CS.Attr.S invalid. */
428#define VMX_IGS_CS_ATTR_S_INVALID 120
429/** CS.Attr.DPL invalid. */
430#define VMX_IGS_CS_ATTR_DPL_INVALID 121
431/** PAE PDPTE reserved bits not set to 0. */
432#define VMX_IGS_PAE_PDPTE_RESERVED 123
433/** @} */
434
435/** @name VMX VMCS-Read cache indices.
436 * @{
437 */
438#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
439#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
440#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
441#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
442#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
443#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
444#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
445#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
446#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
447#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
448#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
449#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
450#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
451#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
452#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
453#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
454#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
455#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
456/** @} */
457
458/** @name VMX EPT paging structures
459 * @{
460 */
461
462/**
463 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
464 */
465#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
466
467/**
468 * EPT Page Directory Pointer Entry. Bit view.
469 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
470 * this did cause trouble with one compiler/version).
471 */
472#pragma pack(1)
473typedef struct EPTPML4EBITS
474{
475 /** Present bit. */
476 uint64_t u1Present : 1;
477 /** Writable bit. */
478 uint64_t u1Write : 1;
479 /** Executable bit. */
480 uint64_t u1Execute : 1;
481 /** Reserved (must be 0). */
482 uint64_t u5Reserved : 5;
483 /** Available for software. */
484 uint64_t u4Available : 4;
485 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
486 uint64_t u40PhysAddr : 40;
487 /** Availabe for software. */
488 uint64_t u12Available : 12;
489} EPTPML4EBITS;
490#pragma pack()
491AssertCompileSize(EPTPML4EBITS, 8);
492
493/** Bits 12-51 - - EPT - Physical Page number of the next level. */
494#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
495/** The page shift to get the PML4 index. */
496#define EPT_PML4_SHIFT X86_PML4_SHIFT
497/** The PML4 index mask (apply to a shifted page address). */
498#define EPT_PML4_MASK X86_PML4_MASK
499
500/**
501 * EPT PML4E.
502 */
503#pragma pack(1)
504typedef union EPTPML4E
505{
506 /** Normal view. */
507 EPTPML4EBITS n;
508 /** Unsigned integer view. */
509 X86PGPAEUINT u;
510 /** 64 bit unsigned integer view. */
511 uint64_t au64[1];
512 /** 32 bit unsigned integer view. */
513 uint32_t au32[2];
514} EPTPML4E;
515#pragma pack()
516/** Pointer to a PML4 table entry. */
517typedef EPTPML4E *PEPTPML4E;
518/** Pointer to a const PML4 table entry. */
519typedef const EPTPML4E *PCEPTPML4E;
520AssertCompileSize(EPTPML4E, 8);
521
522/**
523 * EPT PML4 Table.
524 */
525#pragma pack(1)
526typedef struct EPTPML4
527{
528 EPTPML4E a[EPT_PG_ENTRIES];
529} EPTPML4;
530#pragma pack()
531/** Pointer to an EPT PML4 Table. */
532typedef EPTPML4 *PEPTPML4;
533/** Pointer to a const EPT PML4 Table. */
534typedef const EPTPML4 *PCEPTPML4;
535
536/**
537 * EPT Page Directory Pointer Entry. Bit view.
538 */
539#pragma pack(1)
540typedef struct EPTPDPTEBITS
541{
542 /** Present bit. */
543 uint64_t u1Present : 1;
544 /** Writable bit. */
545 uint64_t u1Write : 1;
546 /** Executable bit. */
547 uint64_t u1Execute : 1;
548 /** Reserved (must be 0). */
549 uint64_t u5Reserved : 5;
550 /** Available for software. */
551 uint64_t u4Available : 4;
552 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
553 uint64_t u40PhysAddr : 40;
554 /** Availabe for software. */
555 uint64_t u12Available : 12;
556} EPTPDPTEBITS;
557#pragma pack()
558AssertCompileSize(EPTPDPTEBITS, 8);
559
560/** Bits 12-51 - - EPT - Physical Page number of the next level. */
561#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
562/** The page shift to get the PDPT index. */
563#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
564/** The PDPT index mask (apply to a shifted page address). */
565#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
566
567/**
568 * EPT Page Directory Pointer.
569 */
570#pragma pack(1)
571typedef union EPTPDPTE
572{
573 /** Normal view. */
574 EPTPDPTEBITS n;
575 /** Unsigned integer view. */
576 X86PGPAEUINT u;
577 /** 64 bit unsigned integer view. */
578 uint64_t au64[1];
579 /** 32 bit unsigned integer view. */
580 uint32_t au32[2];
581} EPTPDPTE;
582#pragma pack()
583/** Pointer to an EPT Page Directory Pointer Entry. */
584typedef EPTPDPTE *PEPTPDPTE;
585/** Pointer to a const EPT Page Directory Pointer Entry. */
586typedef const EPTPDPTE *PCEPTPDPTE;
587AssertCompileSize(EPTPDPTE, 8);
588
589/**
590 * EPT Page Directory Pointer Table.
591 */
592#pragma pack(1)
593typedef struct EPTPDPT
594{
595 EPTPDPTE a[EPT_PG_ENTRIES];
596} EPTPDPT;
597#pragma pack()
598/** Pointer to an EPT Page Directory Pointer Table. */
599typedef EPTPDPT *PEPTPDPT;
600/** Pointer to a const EPT Page Directory Pointer Table. */
601typedef const EPTPDPT *PCEPTPDPT;
602
603
604/**
605 * EPT Page Directory Table Entry. Bit view.
606 */
607#pragma pack(1)
608typedef struct EPTPDEBITS
609{
610 /** Present bit. */
611 uint64_t u1Present : 1;
612 /** Writable bit. */
613 uint64_t u1Write : 1;
614 /** Executable bit. */
615 uint64_t u1Execute : 1;
616 /** Reserved (must be 0). */
617 uint64_t u4Reserved : 4;
618 /** Big page (must be 0 here). */
619 uint64_t u1Size : 1;
620 /** Available for software. */
621 uint64_t u4Available : 4;
622 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
623 uint64_t u40PhysAddr : 40;
624 /** Availabe for software. */
625 uint64_t u12Available : 12;
626} EPTPDEBITS;
627#pragma pack()
628AssertCompileSize(EPTPDEBITS, 8);
629
630/** Bits 12-51 - - EPT - Physical Page number of the next level. */
631#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
632/** The page shift to get the PD index. */
633#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
634/** The PD index mask (apply to a shifted page address). */
635#define EPT_PD_MASK X86_PD_PAE_MASK
636
637/**
638 * EPT 2MB Page Directory Table Entry. Bit view.
639 */
640#pragma pack(1)
641typedef struct EPTPDE2MBITS
642{
643 /** Present bit. */
644 uint64_t u1Present : 1;
645 /** Writable bit. */
646 uint64_t u1Write : 1;
647 /** Executable bit. */
648 uint64_t u1Execute : 1;
649 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
650 uint64_t u3EMT : 3;
651 /** Ignore PAT memory type */
652 uint64_t u1IgnorePAT : 1;
653 /** Big page (must be 1 here). */
654 uint64_t u1Size : 1;
655 /** Available for software. */
656 uint64_t u4Available : 4;
657 /** Reserved (must be 0). */
658 uint64_t u9Reserved : 9;
659 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
660 uint64_t u31PhysAddr : 31;
661 /** Availabe for software. */
662 uint64_t u12Available : 12;
663} EPTPDE2MBITS;
664#pragma pack()
665AssertCompileSize(EPTPDE2MBITS, 8);
666
667/** Bits 21-51 - - EPT - Physical Page number of the next level. */
668#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
669
670/**
671 * EPT Page Directory Table Entry.
672 */
673#pragma pack(1)
674typedef union EPTPDE
675{
676 /** Normal view. */
677 EPTPDEBITS n;
678 /** 2MB view (big). */
679 EPTPDE2MBITS b;
680 /** Unsigned integer view. */
681 X86PGPAEUINT u;
682 /** 64 bit unsigned integer view. */
683 uint64_t au64[1];
684 /** 32 bit unsigned integer view. */
685 uint32_t au32[2];
686} EPTPDE;
687#pragma pack()
688/** Pointer to an EPT Page Directory Table Entry. */
689typedef EPTPDE *PEPTPDE;
690/** Pointer to a const EPT Page Directory Table Entry. */
691typedef const EPTPDE *PCEPTPDE;
692AssertCompileSize(EPTPDE, 8);
693
694/**
695 * EPT Page Directory Table.
696 */
697#pragma pack(1)
698typedef struct EPTPD
699{
700 EPTPDE a[EPT_PG_ENTRIES];
701} EPTPD;
702#pragma pack()
703/** Pointer to an EPT Page Directory Table. */
704typedef EPTPD *PEPTPD;
705/** Pointer to a const EPT Page Directory Table. */
706typedef const EPTPD *PCEPTPD;
707
708
709/**
710 * EPT Page Table Entry. Bit view.
711 */
712#pragma pack(1)
713typedef struct EPTPTEBITS
714{
715 /** 0 - Present bit.
716 * @remark This is a convenience "misnomer". The bit actually indicates
717 * read access and the CPU will consider an entry with any of the
718 * first three bits set as present. Since all our valid entries
719 * will have this bit set, it can be used as a present indicator
720 * and allow some code sharing. */
721 uint64_t u1Present : 1;
722 /** 1 - Writable bit. */
723 uint64_t u1Write : 1;
724 /** 2 - Executable bit. */
725 uint64_t u1Execute : 1;
726 /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
727 uint64_t u3EMT : 3;
728 /** 6 - Ignore PAT memory type */
729 uint64_t u1IgnorePAT : 1;
730 /** 11:7 - Available for software. */
731 uint64_t u5Available : 5;
732 /** 51:12 - Physical address of page. Restricted by maximum physical
733 * address width of the cpu. */
734 uint64_t u40PhysAddr : 40;
735 /** 63:52 - Available for software. */
736 uint64_t u12Available : 12;
737} EPTPTEBITS;
738#pragma pack()
739AssertCompileSize(EPTPTEBITS, 8);
740
741/** Bits 12-51 - - EPT - Physical Page number of the next level. */
742#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
743/** The page shift to get the EPT PTE index. */
744#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
745/** The EPT PT index mask (apply to a shifted page address). */
746#define EPT_PT_MASK X86_PT_PAE_MASK
747
748/**
749 * EPT Page Table Entry.
750 */
751#pragma pack(1)
752typedef union EPTPTE
753{
754 /** Normal view. */
755 EPTPTEBITS n;
756 /** Unsigned integer view. */
757 X86PGPAEUINT u;
758 /** 64 bit unsigned integer view. */
759 uint64_t au64[1];
760 /** 32 bit unsigned integer view. */
761 uint32_t au32[2];
762} EPTPTE;
763#pragma pack()
764/** Pointer to an EPT Page Directory Table Entry. */
765typedef EPTPTE *PEPTPTE;
766/** Pointer to a const EPT Page Directory Table Entry. */
767typedef const EPTPTE *PCEPTPTE;
768AssertCompileSize(EPTPTE, 8);
769
770/**
771 * EPT Page Table.
772 */
773#pragma pack(1)
774typedef struct EPTPT
775{
776 EPTPTE a[EPT_PG_ENTRIES];
777} EPTPT;
778#pragma pack()
779/** Pointer to an extended page table. */
780typedef EPTPT *PEPTPT;
781/** Pointer to a const extended table. */
782typedef const EPTPT *PCEPTPT;
783
784/** @} */
785
786/** VMX VPID flush types.
787 * Warning!! Valid enum members are in accordance to the VT-x spec.
788 */
789typedef enum
790{
791 /** Invalidate a specific page. */
792 VMXFLUSHVPID_INDIV_ADDR = 0,
793 /** Invalidate one context (specific VPID). */
794 VMXFLUSHVPID_SINGLE_CONTEXT = 1,
795 /** Invalidate all contexts (all VPIDs). */
796 VMXFLUSHVPID_ALL_CONTEXTS = 2,
797 /** Invalidate a single VPID context retaining global mappings. */
798 VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
799 /** Unsupported by VirtualBox. */
800 VMXFLUSHVPID_NOT_SUPPORTED = 0xbad0,
801 /** Unsupported by CPU. */
802 VMXFLUSHVPID_NONE = 0xbad1
803} VMXFLUSHVPID;
804AssertCompileSize(VMXFLUSHVPID, 4);
805
806/** VMX EPT flush types.
807 * @note Warning!! Valid enums values below are in accordance to the VT-x spec.
808 */
809typedef enum
810{
811 /** Invalidate one context (specific EPT). */
812 VMXFLUSHEPT_SINGLE_CONTEXT = 1,
813 /* Invalidate all contexts (all EPTs) */
814 VMXFLUSHEPT_ALL_CONTEXTS = 2,
815 /** Unsupported by VirtualBox. */
816 VMXFLUSHEPT_NOT_SUPPORTED = 0xbad0,
817 /** Unsupported by CPU. */
818 VMXFLUSHEPT_NONE = 0xbad1
819} VMXFLUSHEPT;
820AssertCompileSize(VMXFLUSHEPT, 4);
821
822/** VMX MSR autoload/store element.
823 * In accordance to VT-x spec.
824 */
825typedef struct
826{
827 /** The MSR Id. */
828 uint32_t u32Msr;
829 /** Reserved (MBZ). */
830 uint32_t u32Reserved;
831 /** The MSR value. */
832 uint64_t u64Value;
833} VMXAUTOMSR;
834AssertCompileSize(VMXAUTOMSR, 8);
835/** Pointer to an MSR load/store element. */
836typedef VMXAUTOMSR *PVMXAUTOMSR;
837/** Pointer to a const MSR load/store element. */
838typedef const VMXAUTOMSR *PCVMXAUTOMSR;
839
840/**
841 * VMX-capability qword
842 */
843typedef union
844{
845 struct
846 {
847 /** Bits set here -must- be set in the correpsonding VM-execution controls. */
848 uint32_t disallowed0;
849 /** Bits cleared here -must- be cleared in the corresponding VM-execution
850 * controls. */
851 uint32_t allowed1;
852 } n;
853 uint64_t u;
854} VMXCAPABILITY;
855AssertCompileSize(VMXCAPABILITY, 8);
856
857/**
858 * VMX MSRs.
859 */
860typedef struct VMXMSRS
861{
862 uint64_t u64FeatureCtrl;
863 uint64_t u64BasicInfo;
864 VMXCAPABILITY VmxPinCtls;
865 VMXCAPABILITY VmxProcCtls;
866 VMXCAPABILITY VmxProcCtls2;
867 VMXCAPABILITY VmxExit;
868 VMXCAPABILITY VmxEntry;
869 uint64_t u64Misc;
870 uint64_t u64Cr0Fixed0;
871 uint64_t u64Cr0Fixed1;
872 uint64_t u64Cr4Fixed0;
873 uint64_t u64Cr4Fixed1;
874 uint64_t u64VmcsEnum;
875 uint64_t u64Vmfunc;
876 uint64_t u64EptVpidCaps;
877} VMXMSRS;
878AssertCompileSizeAlignment(VMXMSRS, 8);
879/** Pointer to a VMXMSRS struct. */
880typedef VMXMSRS *PVMXMSRS;
881
882/** @name VMX EFLAGS reserved bits.
883 * @{
884 */
885/** And-mask for setting reserved bits to zero */
886#define VMX_EFLAGS_RESERVED_0 (~(X86_EFL_1 | X86_EFL_LIVE_MASK))
887/** Or-mask for setting reserved bits to 1 */
888#define VMX_EFLAGS_RESERVED_1 X86_EFL_1
889/** @} */
890
891/** @name VMX Basic Exit Reasons.
892 * @{
893 */
894/** -1 Invalid exit code */
895#define VMX_EXIT_INVALID -1
896/** 0 Exception or non-maskable interrupt (NMI). */
897#define VMX_EXIT_XCPT_OR_NMI 0
898/** 1 External interrupt. */
899#define VMX_EXIT_EXT_INT 1
900/** 2 Triple fault. */
901#define VMX_EXIT_TRIPLE_FAULT 2
902/** 3 INIT signal. */
903#define VMX_EXIT_INIT_SIGNAL 3
904/** 4 Start-up IPI (SIPI). */
905#define VMX_EXIT_SIPI 4
906/** 5 I/O system-management interrupt (SMI). */
907#define VMX_EXIT_IO_SMI 5
908/** 6 Other SMI. */
909#define VMX_EXIT_SMI 6
910/** 7 Interrupt window exiting. */
911#define VMX_EXIT_INT_WINDOW 7
912/** 8 NMI window exiting. */
913#define VMX_EXIT_NMI_WINDOW 8
914/** 9 Task switch. */
915#define VMX_EXIT_TASK_SWITCH 9
916/** 10 Guest software attempted to execute CPUID. */
917#define VMX_EXIT_CPUID 10
918/** 10 Guest software attempted to execute GETSEC. */
919#define VMX_EXIT_GETSEC 11
920/** 12 Guest software attempted to execute HLT. */
921#define VMX_EXIT_HLT 12
922/** 13 Guest software attempted to execute INVD. */
923#define VMX_EXIT_INVD 13
924/** 14 Guest software attempted to execute INVLPG. */
925#define VMX_EXIT_INVLPG 14
926/** 15 Guest software attempted to execute RDPMC. */
927#define VMX_EXIT_RDPMC 15
928/** 16 Guest software attempted to execute RDTSC. */
929#define VMX_EXIT_RDTSC 16
930/** 17 Guest software attempted to execute RSM in SMM. */
931#define VMX_EXIT_RSM 17
932/** 18 Guest software executed VMCALL. */
933#define VMX_EXIT_VMCALL 18
934/** 19 Guest software executed VMCLEAR. */
935#define VMX_EXIT_VMCLEAR 19
936/** 20 Guest software executed VMLAUNCH. */
937#define VMX_EXIT_VMLAUNCH 20
938/** 21 Guest software executed VMPTRLD. */
939#define VMX_EXIT_VMPTRLD 21
940/** 22 Guest software executed VMPTRST. */
941#define VMX_EXIT_VMPTRST 22
942/** 23 Guest software executed VMREAD. */
943#define VMX_EXIT_VMREAD 23
944/** 24 Guest software executed VMRESUME. */
945#define VMX_EXIT_VMRESUME 24
946/** 25 Guest software executed VMWRITE. */
947#define VMX_EXIT_VMWRITE 25
948/** 26 Guest software executed VMXOFF. */
949#define VMX_EXIT_VMXOFF 26
950/** 27 Guest software executed VMXON. */
951#define VMX_EXIT_VMXON 27
952/** 28 Control-register accesses. */
953#define VMX_EXIT_MOV_CRX 28
954/** 29 Debug-register accesses. */
955#define VMX_EXIT_MOV_DRX 29
956/** 30 I/O instruction. */
957#define VMX_EXIT_IO_INSTR 30
958/** 31 RDMSR. Guest software attempted to execute RDMSR. */
959#define VMX_EXIT_RDMSR 31
960/** 32 WRMSR. Guest software attempted to execute WRMSR. */
961#define VMX_EXIT_WRMSR 32
962/** 33 VM-entry failure due to invalid guest state. */
963#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
964/** 34 VM-entry failure due to MSR loading. */
965#define VMX_EXIT_ERR_MSR_LOAD 34
966/** 36 Guest software executed MWAIT. */
967#define VMX_EXIT_MWAIT 36
968/** 37 VM-exit due to monitor trap flag. */
969#define VMX_EXIT_MTF 37
970/** 39 Guest software attempted to execute MONITOR. */
971#define VMX_EXIT_MONITOR 39
972/** 40 Guest software attempted to execute PAUSE. */
973#define VMX_EXIT_PAUSE 40
974/** 41 VM-entry failure due to machine-check. */
975#define VMX_EXIT_ERR_MACHINE_CHECK 41
976/** 43 TPR below threshold. Guest software executed MOV to CR8. */
977#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
978/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
979#define VMX_EXIT_APIC_ACCESS 44
980/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
981#define VMX_EXIT_XDTR_ACCESS 46
982/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
983#define VMX_EXIT_TR_ACCESS 47
984/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
985#define VMX_EXIT_EPT_VIOLATION 48
986/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
987#define VMX_EXIT_EPT_MISCONFIG 49
988/** 50 INVEPT. Guest software attempted to execute INVEPT. */
989#define VMX_EXIT_INVEPT 50
990/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
991#define VMX_EXIT_RDTSCP 51
992/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
993#define VMX_EXIT_PREEMPT_TIMER 52
994/** 53 INVVPID. Guest software attempted to execute INVVPID. */
995#define VMX_EXIT_INVVPID 53
996/** 54 WBINVD. Guest software attempted to execute WBINVD. */
997#define VMX_EXIT_WBINVD 54
998/** 55 XSETBV. Guest software attempted to execute XSETBV. */
999#define VMX_EXIT_XSETBV 55
1000/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1001#define VMX_EXIT_RDRAND 57
1002/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1003#define VMX_EXIT_INVPCID 58
1004/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1005#define VMX_EXIT_VMFUNC 59
1006/** The maximum exit value (inclusive). */
1007#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
1008/** @} */
1009
1010
1011/** @name VM Instruction Errors
1012 * @{
1013 */
1014/** VMCALL executed in VMX root operation. */
1015#define VMX_ERROR_VMCALL 1
1016/** VMCLEAR with invalid physical address. */
1017#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1018/** VMCLEAR with VMXON pointer. */
1019#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1020/** VMLAUNCH with non-clear VMCS. */
1021#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1022/** VMRESUME with non-launched VMCS. */
1023#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1024/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1025#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1026/** VM-entry with invalid control field(s). */
1027#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1028/** VM-entry with invalid host-state field(s). */
1029#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1030/** VMPTRLD with invalid physical address. */
1031#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1032/** VMPTRLD with VMXON pointer. */
1033#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1034/** VMPTRLD with incorrect VMCS revision identifier. */
1035#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1036/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1037#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1038#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1039/** VMWRITE to read-only VMCS component. */
1040#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1041/** VMXON executed in VMX root operation. */
1042#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1043/** VM-entry with invalid executive-VMCS pointer. */
1044#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1045/** VM-entry with non-launched executive VMCS. */
1046#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1047/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1048#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1049/** VMCALL with non-clear VMCS. */
1050#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1051/** VMCALL with invalid VM-exit control fields. */
1052#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1053/** VMCALL with incorrect MSEG revision identifier. */
1054#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1055/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1056#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1057/** VMCALL with invalid SMM-monitor features. */
1058#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1059/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1060#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1061/** VM-entry with events blocked by MOV SS. */
1062#define VMX_ERROR_VMENTRY_MOV_SS 26
1063/** Invalid operand to INVEPT/INVVPID. */
1064#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1065/** @} */
1066
1067
1068/** @name VMX MSRs - Basic VMX information.
1069 * @{
1070 */
1071/** VMCS revision identifier used by the processor. */
1072#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) ((a) & 0x7FFFFFFF)
1073/** Size of the VMCS. */
1074#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0x1FFF)
1075/** Width of physical address used for the VMCS.
1076 * 0 -> limited to the available amount of physical ram
1077 * 1 -> within the first 4 GB
1078 */
1079#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1080/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1081#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1082/** Memory type that must be used for the VMCS. */
1083#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1084/** Whether the processor provides additional information for exits due to INS/OUTS. */
1085#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1086/** @} */
1087
1088
1089/** @name VMX MSRs - Misc VMX info.
1090 * @{
1091 */
1092/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1093#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1094/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1095#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1096/** Activity states supported by the implementation. */
1097#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1098/** Number of CR3 target values supported by the processor. (0-256) */
1099#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1100/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
1101#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1102/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1103#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1104/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1105#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1106/** Whether VMWRITE can be used to write VM-exit information fields. */
1107#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1108/** MSEG revision identifier used by the processor. */
1109#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1110/** @} */
1111
1112
1113/** @name VMX MSRs - VMCS enumeration field info
1114 * @{
1115 */
1116/** Highest field index. */
1117#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1118/** @} */
1119
1120
1121/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1122 * @{
1123 */
1124#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1125#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
1126#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
1127#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
1128#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
1129#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
1130#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
1131#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
1132#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1133#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
1134#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
1135#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
1136#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1137#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
1138#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
1139#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
1140#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
1141#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1142#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1143#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1144#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1145#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1146#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1147#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1148#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1149/** @} */
1150
1151/** @name Extended Page Table Pointer (EPTP)
1152 * @{
1153 */
1154/** Uncachable EPT paging structure memory type. */
1155#define VMX_EPT_MEMTYPE_UC 0
1156/** Write-back EPT paging structure memory type. */
1157#define VMX_EPT_MEMTYPE_WB 6
1158/** Shift value to get the EPT page walk length (bits 5-3) */
1159#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1160/** Mask value to get the EPT page walk length (bits 5-3) */
1161#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1162/** Default EPT page-walk length (1 less than the actual EPT page-walk
1163 * length) */
1164#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1165/** @} */
1166
1167
1168/** @name VMCS field encoding - 16 bits guest fields
1169 * @{
1170 */
1171#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
1172#define VMX_VMCS16_GUEST_FIELD_ES 0x800
1173#define VMX_VMCS16_GUEST_FIELD_CS 0x802
1174#define VMX_VMCS16_GUEST_FIELD_SS 0x804
1175#define VMX_VMCS16_GUEST_FIELD_DS 0x806
1176#define VMX_VMCS16_GUEST_FIELD_FS 0x808
1177#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
1178#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
1179#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
1180/** @} */
1181
1182/** @name VMCS field encoding - 16 bits host fields
1183 * @{
1184 */
1185#define VMX_VMCS16_HOST_FIELD_ES 0xC00
1186#define VMX_VMCS16_HOST_FIELD_CS 0xC02
1187#define VMX_VMCS16_HOST_FIELD_SS 0xC04
1188#define VMX_VMCS16_HOST_FIELD_DS 0xC06
1189#define VMX_VMCS16_HOST_FIELD_FS 0xC08
1190#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
1191#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
1192/** @} */
1193
1194/** @name VMCS field encoding - 64 bits host fields
1195 * @{
1196 */
1197#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
1198#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
1199#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
1200#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
1201#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
1202#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
1203/** @} */
1204
1205
1206/** @name VMCS field encoding - 64 Bits control fields
1207 * @{
1208 */
1209#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1210#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1211#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1212#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1213
1214/* Optional */
1215#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1216#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1217
1218#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1219#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1220#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1221#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1222
1223#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1224#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1225
1226#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1227#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1228
1229#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1230#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1231
1232/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1233#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1234#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1235
1236/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1237#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1238#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1239
1240/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1241#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1242#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1243
1244/** Extended page table pointer. */
1245#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1246#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1247
1248/** Extended page table pointer lists. */
1249#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1250#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1251
1252/** VM-exit guest phyiscal address. */
1253#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1254#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1255/** @} */
1256
1257
1258/** @name VMCS field encoding - 64 Bits guest fields
1259 * @{
1260 */
1261#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1262#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1263#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
1264#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
1265#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1266#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1267#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1268#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1269#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
1270#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
1271#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1272#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1273#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1274#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1275#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1276#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1277#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1278#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1279/** @} */
1280
1281
1282/** @name VMCS field encoding - 32 Bits control fields
1283 * @{
1284 */
1285#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1286#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1287#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1288#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1289#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1290#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1291#define VMX_VMCS32_CTRL_EXIT 0x400C
1292#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1293#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1294#define VMX_VMCS32_CTRL_ENTRY 0x4012
1295#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1296#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1297#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1298#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1299#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1300#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1301/** @} */
1302
1303
1304/** @name VMX_VMCS_CTRL_PIN_EXEC
1305 * @{
1306 */
1307/** External interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1308#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1309/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1310#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1311/** Virtual NMIs. */
1312#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1313/** Activate VMX preemption timer. */
1314#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1315/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1316/** @} */
1317
1318/** @name VMX_VMCS_CTRL_PROC_EXEC
1319 * @{
1320 */
1321/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1322#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1323/** Use timestamp counter offset. */
1324#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1325/** VM-exit when executing the HLT instruction. */
1326#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1327/** VM-exit when executing the INVLPG instruction. */
1328#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1329/** VM-exit when executing the MWAIT instruction. */
1330#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1331/** VM-exit when executing the RDPMC instruction. */
1332#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1333/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1334#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1335/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1336#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1337/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1338#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1339/** VM-exit on CR8 loads. */
1340#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1341/** VM-exit on CR8 stores. */
1342#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1343/** Use TPR shadow. */
1344#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1345/** VM-exit when virtual NMI blocking is disabled. */
1346#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1347/** VM-exit when executing a MOV DRx instruction. */
1348#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1349/** VM-exit when executing IO instructions. */
1350#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1351/** Use IO bitmaps. */
1352#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1353/** Monitor trap flag. */
1354#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1355/** Use MSR bitmaps. */
1356#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1357/** VM-exit when executing the MONITOR instruction. */
1358#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1359/** VM-exit when executing the PAUSE instruction. */
1360#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1361/** Determines whether the secondary processor based VM-execution controls are used. */
1362#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1363/** @} */
1364
1365/** @name VMX_VMCS_CTRL_PROC_EXEC2
1366 * @{
1367 */
1368/** Virtualize APIC access. */
1369#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1370/** EPT supported/enabled. */
1371#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1372/** Descriptor table instructions cause VM-exits. */
1373#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1374/** RDTSCP supported/enabled. */
1375#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1376/** Virtualize x2APIC mode. */
1377#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1378/** VPID supported/enabled. */
1379#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1380/** VM-exit when executing the WBINVD instruction. */
1381#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1382/** Unrestricted guest execution. */
1383#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1384/** A specified nr of pause loops cause a VM-exit. */
1385#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1386/** VM-exit when executing RDRAND instructions. */
1387#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1388/** Enables INVPCID instructions. */
1389#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1390/** Enables VMFUNC instructions. */
1391#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1392/** @} */
1393
1394
1395/** @name VMX_VMCS_CTRL_ENTRY
1396 * @{
1397 */
1398/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1399#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1400/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1401#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1402/** In SMM mode after VM-entry. */
1403#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1404/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1405#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1406/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
1407#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1408/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
1409#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1410/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
1411#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1412/** @} */
1413
1414
1415/** @name VMX_VMCS_CTRL_EXIT
1416 * @{
1417 */
1418/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1419#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1420/** Return to long mode after a VM-exit. */
1421#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1422/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
1423#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1424/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1425#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1426/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
1427#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1428/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
1429#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1430/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
1431#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1432/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
1433#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1434/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
1435#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1436/** @} */
1437
1438
1439/** @name VMX_VMCS_CTRL_VMFUNC
1440 * @{
1441 */
1442/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1443#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1444/** @} */
1445
1446
1447/** @name VMCS field encoding - 32 Bits read-only fields
1448 * @{
1449 */
1450#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1451#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1452#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1453#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1454#define VMX_VMCS32_RO_IDT_INFO 0x4408
1455#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1456#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1457#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1458/** @} */
1459
1460/** @name VMX_VMCS32_RO_EXIT_REASON
1461 * @{
1462 */
1463#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
1464/** @} */
1465
1466/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1467 * @{
1468 */
1469#define VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1470#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1471#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1472/** @} */
1473
1474
1475/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1476 * @{
1477 */
1478#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) ((a) & 0xff)
1479#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1480#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1481#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1482#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1483#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(a) ((a) & RT_BIT(12))
1484#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1485#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1486/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1487#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
1488/** @} */
1489
1490/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1491 * @{
1492 */
1493#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1494#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1495#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1496#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4
1497#define VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT 5
1498#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1499/** @} */
1500
1501/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1502 * @{
1503 */
1504#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
1505#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1506#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1507#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1508#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1509#define VMX_IDT_VECTORING_INFO_VALID(a) ((a) & RT_BIT(31))
1510#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
1511/** @} */
1512
1513/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1514 * @{
1515 */
1516#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1517#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1518#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1519#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1520#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1521#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1522/** @} */
1523
1524
1525/** @name VMCS field encoding - 32 Bits guest state fields
1526 * @{
1527 */
1528#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1529#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1530#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1531#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1532#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1533#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1534#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1535#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1536#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1537#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1538#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1539#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1540#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1541#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1542#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1543#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1544#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1545#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1546#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1547#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1548#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
1549#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1550/** @} */
1551
1552
1553/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1554 * @{
1555 */
1556/** The logical processor is active. */
1557#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1558/** The logical processor is inactive, because executed a HLT instruction. */
1559#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1560/** The logical processor is inactive, because of a triple fault or other serious error. */
1561#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1562/** The logical processor is inactive, because it's waiting for a startup-IPI */
1563#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1564/** @} */
1565
1566
1567/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1568 * @{
1569 */
1570#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1571#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1572#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1573#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1574/** @} */
1575
1576
1577/** @name VMCS field encoding - 32 Bits host state fields
1578 * @{
1579 */
1580#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1581/** @} */
1582
1583/** @name Natural width control fields
1584 * @{
1585 */
1586#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1587#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1588#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1589#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1590#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1591#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1592#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1593#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1594/** @} */
1595
1596
1597/** @name Natural width read-only data fields
1598 * @{
1599 */
1600#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1601#define VMX_VMCS_RO_IO_RCX 0x6402
1602#define VMX_VMCS_RO_IO_RSX 0x6404
1603#define VMX_VMCS_RO_IO_RDI 0x6406
1604#define VMX_VMCS_RO_IO_RIP 0x6408
1605#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1606/** @} */
1607
1608
1609/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1610 * @{
1611 */
1612/** 0-2: Debug register number */
1613#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) ((a) & 7)
1614/** 3: Reserved; cleared to 0. */
1615#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) (((a) >> 3) & 1)
1616/** 4: Direction of move (0 = write, 1 = read) */
1617#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) (((a) >> 4) & 1)
1618/** 5-7: Reserved; cleared to 0. */
1619#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) (((a) >> 5) & 7)
1620/** 8-11: General purpose register number. */
1621#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) (((a) >> 8) & 0xF)
1622/** Rest: reserved. */
1623/** @} */
1624
1625/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1626 * @{
1627 */
1628#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1629#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1630/** @} */
1631
1632
1633
1634/** @name CRx accesses
1635 * @{
1636 */
1637/** 0-3: Control register number (0 for CLTS & LMSW) */
1638#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) ((a) & 0xF)
1639/** 4-5: Access type. */
1640#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) (((a) >> 4) & 3)
1641/** 6: LMSW operand type */
1642#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) (((a) >> 6) & 1)
1643/** 7: Reserved; cleared to 0. */
1644#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) (((a) >> 7) & 1)
1645/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1646#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) (((a) >> 8) & 0xF)
1647/** 12-15: Reserved; cleared to 0. */
1648#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) (((a) >> 12) & 0xF)
1649/** 16-31: LMSW source data (else 0). */
1650#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) (((a) >> 16) & 0xFFFF)
1651/* Rest: reserved. */
1652/** @} */
1653
1654/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1655 * @{
1656 */
1657#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1658#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1659#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1660#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1661/** @} */
1662
1663/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1664 * @{
1665 */
1666#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
1667#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
1668/** Task switch caused by a call instruction. */
1669#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1670/** Task switch caused by an iret instruction. */
1671#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1672/** Task switch caused by a jmp instruction. */
1673#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1674/** Task switch caused by an interrupt gate. */
1675#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1676/** @} */
1677
1678
1679/** @name VMX_EXIT_EPT_VIOLATION
1680 * @{
1681 */
1682/** Set if the violation was caused by a data read. */
1683#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1684/** Set if the violation was caused by a data write. */
1685#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1686/** Set if the violation was caused by an insruction fetch. */
1687#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1688/** AND of the present bit of all EPT structures. */
1689#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1690/** AND of the write bit of all EPT structures. */
1691#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1692/** AND of the execute bit of all EPT structures. */
1693#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1694/** Set if the guest linear address field contains the faulting address. */
1695#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1696/** If bit 7 is one: (reserved otherwise)
1697 * 1 - violation due to physical address access.
1698 * 0 - violation caused by page walk or access/dirty bit updates
1699 */
1700#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1701/** @} */
1702
1703
1704/** @name VMX_EXIT_PORT_IO
1705 * @{
1706 */
1707/** 0-2: IO operation width. */
1708#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1709/** 3: IO operation direction. */
1710#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1711/** 4: String IO operation (INS / OUTS). */
1712#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1713/** 5: Repeated IO operation. */
1714#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1715/** 6: Operand encoding. */
1716#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1717/** 16-31: IO Port (0-0xffff). */
1718#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1719/* Rest reserved. */
1720/** @} */
1721
1722/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1723 * @{
1724 */
1725#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1726#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1727/** @} */
1728
1729
1730/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1731 * @{
1732 */
1733#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1734#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1735/** @} */
1736
1737/** @name VMX_EXIT_APIC_ACCESS
1738 * @{
1739 */
1740/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of access within the APIC page. */
1741#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1742/** 12-15: Access type. */
1743#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
1744/* Rest reserved. */
1745/** @} */
1746
1747
1748/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE return values
1749 * @{
1750 */
1751/** Linear read access. */
1752#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1753/** Linear write access. */
1754#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1755/** Linear instruction fetch access. */
1756#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1757/** Linear read/write access during event delivery. */
1758#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1759/** Physical read/write access during event delivery. */
1760#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1761/** Physical access for an instruction fetch or during instruction execution. */
1762#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1763/** @} */
1764
1765
1766/** @name VMCS field encoding - Natural width guest state fields
1767 * @{
1768 */
1769#define VMX_VMCS_GUEST_CR0 0x6800
1770#define VMX_VMCS_GUEST_CR3 0x6802
1771#define VMX_VMCS_GUEST_CR4 0x6804
1772#define VMX_VMCS_GUEST_ES_BASE 0x6806
1773#define VMX_VMCS_GUEST_CS_BASE 0x6808
1774#define VMX_VMCS_GUEST_SS_BASE 0x680A
1775#define VMX_VMCS_GUEST_DS_BASE 0x680C
1776#define VMX_VMCS_GUEST_FS_BASE 0x680E
1777#define VMX_VMCS_GUEST_GS_BASE 0x6810
1778#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1779#define VMX_VMCS_GUEST_TR_BASE 0x6814
1780#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1781#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1782#define VMX_VMCS_GUEST_DR7 0x681A
1783#define VMX_VMCS_GUEST_RSP 0x681C
1784#define VMX_VMCS_GUEST_RIP 0x681E
1785#define VMX_VMCS_GUEST_RFLAGS 0x6820
1786#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1787#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1788#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1789/** @} */
1790
1791
1792/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1793 * Bits 4-11, 13 and 15-63 are reserved.
1794 * @{
1795 */
1796/** Hardware breakpoint 0 was met. */
1797#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1798/** Hardware breakpoint 1 was met. */
1799#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1800/** Hardware breakpoint 2 was met. */
1801#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1802/** Hardware breakpoint 3 was met. */
1803#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1804/** At least one data or IO breakpoint was hit. */
1805#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1806/** A debug exception would have been triggered by single-step execution mode. */
1807#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1808/** @} */
1809
1810/** @name VMCS field encoding - Natural width host state fields
1811 * @{
1812 */
1813#define VMX_VMCS_HOST_CR0 0x6C00
1814#define VMX_VMCS_HOST_CR3 0x6C02
1815#define VMX_VMCS_HOST_CR4 0x6C04
1816#define VMX_VMCS_HOST_FS_BASE 0x6C06
1817#define VMX_VMCS_HOST_GS_BASE 0x6C08
1818#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1819#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1820#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1821#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1822#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1823#define VMX_VMCS_HOST_RSP 0x6C14
1824#define VMX_VMCS_HOST_RIP 0x6C16
1825/** @} */
1826
1827
1828/** @defgroup grp_vmx_asm vmx assembly helpers
1829 * @{
1830 */
1831
1832/**
1833 * Restores some host-state fields that need not be done on every VM-exit.
1834 *
1835 * @returns VBox status code.
1836 * @param fRestoreHostFlags Flags of which host registers needs to be
1837 * restored.
1838 * @param pRestoreHost Pointer to the host-restore structure.
1839 */
1840DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1841
1842
1843/**
1844 * Dispatches an NMI to the host.
1845 */
1846DECLASM(int) VMXDispatchHostNmi(void);
1847
1848
1849/**
1850 * Executes VMXON
1851 *
1852 * @returns VBox status code
1853 * @param pVMXOn Physical address of VMXON structure
1854 */
1855#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1856DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1857#else
1858DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1859{
1860# if RT_INLINE_ASM_GNU_STYLE
1861 int rc = VINF_SUCCESS;
1862 __asm__ __volatile__ (
1863 "push %3 \n\t"
1864 "push %2 \n\t"
1865 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1866 "ja 2f \n\t"
1867 "je 1f \n\t"
1868 "movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1869 "jmp 2f \n\t"
1870 "1: \n\t"
1871 "movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1872 "2: \n\t"
1873 "add $8, %%esp \n\t"
1874 :"=rm"(rc)
1875 :"0"(VINF_SUCCESS),
1876 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1877 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1878 :"memory"
1879 );
1880 return rc;
1881
1882# elif VMX_USE_MSC_INTRINSICS
1883 unsigned char rcMsc = __vmx_on(&pVMXOn);
1884 if (RT_LIKELY(rcMsc == 0))
1885 return VINF_SUCCESS;
1886 return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
1887
1888# else
1889 int rc = VINF_SUCCESS;
1890 __asm
1891 {
1892 push dword ptr [pVMXOn+4]
1893 push dword ptr [pVMXOn]
1894 _emit 0xF3
1895 _emit 0x0F
1896 _emit 0xC7
1897 _emit 0x34
1898 _emit 0x24 /* VMXON [esp] */
1899 jnc vmxon_good
1900 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1901 jmp the_end
1902
1903vmxon_good:
1904 jnz the_end
1905 mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1906the_end:
1907 add esp, 8
1908 }
1909 return rc;
1910# endif
1911}
1912#endif
1913
1914
1915/**
1916 * Executes VMXOFF
1917 */
1918#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1919DECLASM(void) VMXDisable(void);
1920#else
1921DECLINLINE(void) VMXDisable(void)
1922{
1923# if RT_INLINE_ASM_GNU_STYLE
1924 __asm__ __volatile__ (
1925 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1926 );
1927
1928# elif VMX_USE_MSC_INTRINSICS
1929 __vmx_off();
1930
1931# else
1932 __asm
1933 {
1934 _emit 0x0F
1935 _emit 0x01
1936 _emit 0xC4 /* VMXOFF */
1937 }
1938# endif
1939}
1940#endif
1941
1942
1943/**
1944 * Executes VMCLEAR
1945 *
1946 * @returns VBox status code
1947 * @param pVMCS Physical address of VM control structure
1948 */
1949#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1950DECLASM(int) VMXClearVmcs(RTHCPHYS pVMCS);
1951#else
1952DECLINLINE(int) VMXClearVmcs(RTHCPHYS pVMCS)
1953{
1954# if RT_INLINE_ASM_GNU_STYLE
1955 int rc = VINF_SUCCESS;
1956 __asm__ __volatile__ (
1957 "push %3 \n\t"
1958 "push %2 \n\t"
1959 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1960 "jnc 1f \n\t"
1961 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1962 "1: \n\t"
1963 "add $8, %%esp \n\t"
1964 :"=rm"(rc)
1965 :"0"(VINF_SUCCESS),
1966 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1967 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1968 :"memory"
1969 );
1970 return rc;
1971
1972# elif VMX_USE_MSC_INTRINSICS
1973 unsigned char rcMsc = __vmx_vmclear(&pVMCS);
1974 if (RT_LIKELY(rcMsc == 0))
1975 return VINF_SUCCESS;
1976 return VERR_VMX_INVALID_VMCS_PTR;
1977
1978# else
1979 int rc = VINF_SUCCESS;
1980 __asm
1981 {
1982 push dword ptr [pVMCS+4]
1983 push dword ptr [pVMCS]
1984 _emit 0x66
1985 _emit 0x0F
1986 _emit 0xC7
1987 _emit 0x34
1988 _emit 0x24 /* VMCLEAR [esp] */
1989 jnc success
1990 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1991success:
1992 add esp, 8
1993 }
1994 return rc;
1995# endif
1996}
1997#endif
1998
1999
2000/**
2001 * Executes VMPTRLD
2002 *
2003 * @returns VBox status code
2004 * @param pVMCS Physical address of VMCS structure
2005 */
2006#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2007DECLASM(int) VMXActivateVmcs(RTHCPHYS pVMCS);
2008#else
2009DECLINLINE(int) VMXActivateVmcs(RTHCPHYS pVMCS)
2010{
2011# if RT_INLINE_ASM_GNU_STYLE
2012 int rc = VINF_SUCCESS;
2013 __asm__ __volatile__ (
2014 "push %3 \n\t"
2015 "push %2 \n\t"
2016 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2017 "jnc 1f \n\t"
2018 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2019 "1: \n\t"
2020 "add $8, %%esp \n\t"
2021 :"=rm"(rc)
2022 :"0"(VINF_SUCCESS),
2023 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
2024 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
2025 );
2026 return rc;
2027
2028# elif VMX_USE_MSC_INTRINSICS
2029 unsigned char rcMsc = __vmx_vmptrld(&pVMCS);
2030 if (RT_LIKELY(rcMsc == 0))
2031 return VINF_SUCCESS;
2032 return VERR_VMX_INVALID_VMCS_PTR;
2033
2034# else
2035 int rc = VINF_SUCCESS;
2036 __asm
2037 {
2038 push dword ptr [pVMCS+4]
2039 push dword ptr [pVMCS]
2040 _emit 0x0F
2041 _emit 0xC7
2042 _emit 0x34
2043 _emit 0x24 /* VMPTRLD [esp] */
2044 jnc success
2045 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2046
2047success:
2048 add esp, 8
2049 }
2050 return rc;
2051# endif
2052}
2053#endif
2054
2055/**
2056 * Executes VMPTRST
2057 *
2058 * @returns VBox status code
2059 * @param pVMCS Address that will receive the current pointer
2060 */
2061DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pVMCS);
2062
2063/**
2064 * Executes VMWRITE
2065 *
2066 * @returns VBox status code
2067 * @retval VINF_SUCCESS
2068 * @retval VERR_VMX_INVALID_VMCS_PTR
2069 * @retval VERR_VMX_INVALID_VMCS_FIELD
2070 *
2071 * @param idxField VMCS index
2072 * @param u32Val 32 bits value
2073 *
2074 * @remarks The values of the two status codes can be ORed together, the result
2075 * will be VERR_VMX_INVALID_VMCS_PTR.
2076 */
2077#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2078DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2079#else
2080DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2081{
2082# if RT_INLINE_ASM_GNU_STYLE
2083 int rc = VINF_SUCCESS;
2084 __asm__ __volatile__ (
2085 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2086 "ja 2f \n\t"
2087 "je 1f \n\t"
2088 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2089 "jmp 2f \n\t"
2090 "1: \n\t"
2091 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2092 "2: \n\t"
2093 :"=rm"(rc)
2094 :"0"(VINF_SUCCESS),
2095 "a"(idxField),
2096 "d"(u32Val)
2097 );
2098 return rc;
2099
2100# elif VMX_USE_MSC_INTRINSICS
2101 unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2102 if (RT_LIKELY(rcMsc == 0))
2103 return VINF_SUCCESS;
2104 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2105
2106#else
2107 int rc = VINF_SUCCESS;
2108 __asm
2109 {
2110 push dword ptr [u32Val]
2111 mov eax, [idxField]
2112 _emit 0x0F
2113 _emit 0x79
2114 _emit 0x04
2115 _emit 0x24 /* VMWRITE eax, [esp] */
2116 jnc valid_vmcs
2117 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2118 jmp the_end
2119
2120valid_vmcs:
2121 jnz the_end
2122 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2123the_end:
2124 add esp, 4
2125 }
2126 return rc;
2127# endif
2128}
2129#endif
2130
2131/**
2132 * Executes VMWRITE
2133 *
2134 * @returns VBox status code
2135 * @retval VINF_SUCCESS
2136 * @retval VERR_VMX_INVALID_VMCS_PTR
2137 * @retval VERR_VMX_INVALID_VMCS_FIELD
2138 *
2139 * @param idxField VMCS index
2140 * @param u64Val 16, 32 or 64 bits value
2141 *
2142 * @remarks The values of the two status codes can be ORed together, the result
2143 * will be VERR_VMX_INVALID_VMCS_PTR.
2144 */
2145#if !defined(RT_ARCH_X86) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2146# if !VMX_USE_MSC_INTRINSICS || ARCH_BITS != 64
2147DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2148# else /* VMX_USE_MSC_INTRINSICS */
2149DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2150{
2151 unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2152 if (RT_LIKELY(rcMsc == 0))
2153 return VINF_SUCCESS;
2154 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2155}
2156# endif /* VMX_USE_MSC_INTRINSICS */
2157#else
2158# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2159VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2160#endif
2161
2162#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2163# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
2164 VMXWriteVmcs64(idxField, uVal) \
2165 : VMXWriteVmcs32(idxField, uVal)
2166# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
2167 VMXWriteVmcs64(idxField, u64Val) \
2168 : VMXWriteVmcs32(idxField, u64Val)
2169#elif ARCH_BITS == 32
2170# define VMXWriteVmcsHstN VMXWriteVmcs32
2171# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2172#else /* ARCH_BITS == 64 */
2173# define VMXWriteVmcsHstN VMXWriteVmcs64
2174# define VMXWriteVmcsGstN VMXWriteVmcs64
2175#endif
2176
2177
2178/**
2179 * Invalidate a page using invept
2180 * @returns VBox status code
2181 * @param enmFlush Type of flush
2182 * @param pDescriptor Descriptor
2183 */
2184DECLASM(int) VMXR0InvEPT(VMXFLUSHEPT enmFlush, uint64_t *pDescriptor);
2185
2186/**
2187 * Invalidate a page using invvpid
2188 * @returns VBox status code
2189 * @param enmFlush Type of flush
2190 * @param pDescriptor Descriptor
2191 */
2192DECLASM(int) VMXR0InvVPID(VMXFLUSHVPID enmFlush, uint64_t *pDescriptor);
2193
2194/**
2195 * Executes VMREAD
2196 *
2197 * @returns VBox status code
2198 * @retval VINF_SUCCESS
2199 * @retval VERR_VMX_INVALID_VMCS_PTR
2200 * @retval VERR_VMX_INVALID_VMCS_FIELD
2201 *
2202 * @param idxField VMCS index
2203 * @param pData Ptr to store VM field value
2204 *
2205 * @remarks The values of the two status codes can be ORed together, the result
2206 * will be VERR_VMX_INVALID_VMCS_PTR.
2207 */
2208#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2209DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2210#else
2211DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2212{
2213# if RT_INLINE_ASM_GNU_STYLE
2214 int rc = VINF_SUCCESS;
2215 __asm__ __volatile__ (
2216 "movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2217 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2218 "ja 2f \n\t"
2219 "je 1f \n\t"
2220 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2221 "jmp 2f \n\t"
2222 "1: \n\t"
2223 "movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2224 "2: \n\t"
2225 :"=&r"(rc),
2226 "=d"(*pData)
2227 :"a"(idxField),
2228 "d"(0)
2229 );
2230 return rc;
2231
2232# elif VMX_USE_MSC_INTRINSICS
2233 unsigned char rcMsc;
2234# if ARCH_BITS == 32
2235 rcMsc = __vmx_vmread(idxField, pData);
2236# else
2237 uint64_t u64Tmp;
2238 rcMsc = __vmx_vmread(idxField, &u64Tmp);
2239 *pData = (uint32_t)u64Tmp;
2240# endif
2241 if (RT_LIKELY(rcMsc == 0))
2242 return VINF_SUCCESS;
2243 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2244
2245#else
2246 int rc = VINF_SUCCESS;
2247 __asm
2248 {
2249 sub esp, 4
2250 mov dword ptr [esp], 0
2251 mov eax, [idxField]
2252 _emit 0x0F
2253 _emit 0x78
2254 _emit 0x04
2255 _emit 0x24 /* VMREAD eax, [esp] */
2256 mov edx, pData
2257 pop dword ptr [edx]
2258 jnc valid_vmcs
2259 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2260 jmp the_end
2261
2262valid_vmcs:
2263 jnz the_end
2264 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2265the_end:
2266 }
2267 return rc;
2268# endif
2269}
2270#endif
2271
2272/**
2273 * Executes VMREAD
2274 *
2275 * @returns VBox status code
2276 * @retval VINF_SUCCESS
2277 * @retval VERR_VMX_INVALID_VMCS_PTR
2278 * @retval VERR_VMX_INVALID_VMCS_FIELD
2279 *
2280 * @param idxField VMCS index
2281 * @param pData Ptr to store VM field value
2282 *
2283 * @remarks The values of the two status codes can be ORed together, the result
2284 * will be VERR_VMX_INVALID_VMCS_PTR.
2285 */
2286#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2287DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2288#else
2289DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2290{
2291# if VMX_USE_MSC_INTRINSICS
2292 unsigned char rcMsc;
2293# if ARCH_BITS == 32
2294 size_t uLow;
2295 size_t uHigh;
2296 rcMsc = __vmx_vmread(idxField, &uLow);
2297 rcMsc |= __vmx_vmread(idxField + 1, &uHigh);
2298 *pData = RT_MAKE_U64(uLow, uHigh);
2299# else
2300 rcMsc = __vmx_vmread(idxField, pData);
2301# endif
2302 if (RT_LIKELY(rcMsc == 0))
2303 return VINF_SUCCESS;
2304 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2305
2306# elif ARCH_BITS == 32
2307 int rc;
2308 uint32_t val_hi, val;
2309 rc = VMXReadVmcs32(idxField, &val);
2310 rc |= VMXReadVmcs32(idxField + 1, &val_hi);
2311 AssertRC(rc);
2312 *pData = RT_MAKE_U64(val, val_hi);
2313 return rc;
2314
2315# else
2316# error "Shouldn't be here..."
2317# endif
2318}
2319#endif
2320
2321/**
2322 * Gets the last instruction error value from the current VMCS
2323 *
2324 * @returns error value
2325 */
2326DECLINLINE(uint32_t) VMXGetLastError(void)
2327{
2328#if ARCH_BITS == 64
2329 uint64_t uLastError = 0;
2330 int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2331 AssertRC(rc);
2332 return (uint32_t)uLastError;
2333
2334#else /* 32-bit host: */
2335 uint32_t uLastError = 0;
2336 int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2337 AssertRC(rc);
2338 return uLastError;
2339#endif
2340}
2341
2342#ifdef IN_RING0
2343VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2344VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2345#endif /* IN_RING0 */
2346
2347/** @} */
2348
2349/** @} */
2350
2351#endif
2352
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