hm_vmx.h@ 72490

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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# pragma warning(push)
38	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
39	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
40	# include <intrin.h>
41	# pragma warning(pop)
42	/* We always want them as intrinsics, no functions. */
43	# pragma intrinsic(__vmx_on)
44	# pragma intrinsic(__vmx_off)
45	# pragma intrinsic(__vmx_vmclear)
46	# pragma intrinsic(__vmx_vmptrld)
47	# pragma intrinsic(__vmx_vmread)
48	# pragma intrinsic(__vmx_vmwrite)
49	# define VMX_USE_MSC_INTRINSICS 1
50	#else
51	# define VMX_USE_MSC_INTRINSICS 0
52	#endif
53
54
55	/** @defgroup grp_hm_vmx VMX Types and Definitions
56	* @ingroup grp_hm
57	* @{
58	*/
59
60	/** @def HMVMXCPU_GST_SET_UPDATED
61	* Sets a guest-state-updated flag.
62	*
63	* @param pVCpu The cross context virtual CPU structure.
64	* @param fFlag The flag to set.
65	*/
66	#define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
67
68	/** @def HMVMXCPU_GST_IS_SET
69	* Checks if all the flags in the specified guest-state-updated set is pending.
70	*
71	* @param pVCpu The cross context virtual CPU structure.
72	* @param fFlag The flag to check.
73	*/
74	#define HMVMXCPU_GST_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
75
76	/** @def HMVMXCPU_GST_IS_UPDATED
77	* Checks if one or more of the flags in the specified guest-state-updated set
78	* is updated.
79	*
80	* @param pVCpu The cross context virtual CPU structure.
81	* @param fFlags The flags to check for.
82	*/
83	#define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
84
85	/** @def HMVMXCPU_GST_RESET_TO
86	* Resets the guest-state-updated flags to the specified value.
87	*
88	* @param pVCpu The cross context virtual CPU structure.
89	* @param fFlags The new value.
90	*/
91	#define HMVMXCPU_GST_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlags)))
92
93	/** @def HMVMXCPU_GST_VALUE
94	* Returns the current guest-state-updated flags value.
95	*
96	* @param pVCpu The cross context virtual CPU structure.
97	*/
98	#define HMVMXCPU_GST_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState))
99
100	/** @name Host-state restoration flags.
101	* @note If you change these values don't forget to update the assembly
102	* defines as well!
103	* @{
104	*/
105	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
106	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
107	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
108	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
109	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
110	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
111	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
112	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
113	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
114	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
115	/** @} */
116
117	/**
118	* Host-state restoration structure.
119	* This holds host-state fields that require manual restoration.
120	* Assembly version found in hm_vmx.mac (should be automatically verified).
121	*/
122	typedef struct VMXRESTOREHOST
123	{
124	RTSEL uHostSelDS; /* 0x00 */
125	RTSEL uHostSelES; /* 0x02 */
126	RTSEL uHostSelFS; /* 0x04 */
127	RTSEL uHostSelGS; /* 0x06 */
128	RTSEL uHostSelTR; /* 0x08 */
129	uint8_t abPadding0[4];
130	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
131	uint8_t abPadding1[6];
132	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
133	uint8_t abPadding2[6];
134	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
135	uint64_t uHostFSBase; /* 0x38 */
136	uint64_t uHostGSBase; /* 0x40 */
137	} VMXRESTOREHOST;
138	/** Pointer to VMXRESTOREHOST. */
139	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
140	AssertCompileSize(X86XDTR64, 10);
141	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
142	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
143	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
144	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
145	AssertCompileSize(VMXRESTOREHOST, 72);
146	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
147
148	/** @name Host-state MSR lazy-restoration flags.
149	* @{
150	*/
151	/** The host MSRs have been saved. */
152	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
153	/** The guest MSRs are loaded and in effect. */
154	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
155	/** @} */
156
157	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
158	* UFC = Unsupported Feature Combination.
159	* @{
160	*/
161	/** Unsupported pin-based VM-execution controls combo. */
162	#define VMX_UFC_CTRL_PIN_EXEC 1
163	/** Unsupported processor-based VM-execution controls combo. */
164	#define VMX_UFC_CTRL_PROC_EXEC 2
165	/** Unsupported move debug register VM-exit combo. */
166	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
167	/** Unsupported VM-entry controls combo. */
168	#define VMX_UFC_CTRL_ENTRY 4
169	/** Unsupported VM-exit controls combo. */
170	#define VMX_UFC_CTRL_EXIT 5
171	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
172	* for storing host MSRs. */
173	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
174	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
175	* for storing guest MSRs. */
176	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
177	/** Invalid VMCS size. */
178	#define VMX_UFC_INVALID_VMCS_SIZE 8
179	/** Unsupported secondary processor-based VM-execution controls combo. */
180	#define VMX_UFC_CTRL_PROC_EXEC2 9
181	/** Invalid unrestricted-guest execution controls combo. */
182	#define VMX_UFC_INVALID_UX_COMBO 10
183	/** EPT flush type not supported. */
184	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
185	/** EPT paging structure memory type is not write-back. */
186	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
187	/** EPT requires INVEPT instr. support but it's not available. */
188	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
189	/** EPT requires page-walk length of 4. */
190	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
191	/** @} */
192
193	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
194	* IGS = Invalid Guest State.
195	* @{
196	*/
197	/** An error occurred while checking invalid-guest-state. */
198	#define VMX_IGS_ERROR 500
199	/** The invalid guest-state checks did not find any reason why. */
200	#define VMX_IGS_REASON_NOT_FOUND 501
201	/** CR0 fixed1 bits invalid. */
202	#define VMX_IGS_CR0_FIXED1 502
203	/** CR0 fixed0 bits invalid. */
204	#define VMX_IGS_CR0_FIXED0 503
205	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
206	#define VMX_IGS_CR0_PG_PE_COMBO 504
207	/** CR4 fixed1 bits invalid. */
208	#define VMX_IGS_CR4_FIXED1 505
209	/** CR4 fixed0 bits invalid. */
210	#define VMX_IGS_CR4_FIXED0 506
211	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
212	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
213	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
214	/** CR0.PG not set for long-mode when not using unrestricted guest. */
215	#define VMX_IGS_CR0_PG_LONGMODE 508
216	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
217	#define VMX_IGS_CR4_PAE_LONGMODE 509
218	/** CR4.PCIDE set for 32-bit guest. */
219	#define VMX_IGS_CR4_PCIDE 510
220	/** VMCS' DR7 reserved bits not set to 0. */
221	#define VMX_IGS_DR7_RESERVED 511
222	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
223	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
224	/** VMCS' EFER MSR reserved bits not set to 0. */
225	#define VMX_IGS_EFER_MSR_RESERVED 513
226	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
227	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
228	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
229	* without unrestricted guest. */
230	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
231	/** CS.Attr.P bit invalid. */
232	#define VMX_IGS_CS_ATTR_P_INVALID 516
233	/** CS.Attr reserved bits not set to 0. */
234	#define VMX_IGS_CS_ATTR_RESERVED 517
235	/** CS.Attr.G bit invalid. */
236	#define VMX_IGS_CS_ATTR_G_INVALID 518
237	/** CS is unusable. */
238	#define VMX_IGS_CS_ATTR_UNUSABLE 519
239	/** CS and SS DPL unequal. */
240	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
241	/** CS and SS DPL mismatch. */
242	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
243	/** CS Attr.Type invalid. */
244	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
245	/** CS and SS RPL unequal. */
246	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
247	/** SS.Attr.DPL and SS RPL unequal. */
248	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
249	/** SS.Attr.DPL invalid for segment type. */
250	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
251	/** SS.Attr.Type invalid. */
252	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
253	/** SS.Attr.P bit invalid. */
254	#define VMX_IGS_SS_ATTR_P_INVALID 527
255	/** SS.Attr reserved bits not set to 0. */
256	#define VMX_IGS_SS_ATTR_RESERVED 528
257	/** SS.Attr.G bit invalid. */
258	#define VMX_IGS_SS_ATTR_G_INVALID 529
259	/** DS.Attr.A bit invalid. */
260	#define VMX_IGS_DS_ATTR_A_INVALID 530
261	/** DS.Attr.P bit invalid. */
262	#define VMX_IGS_DS_ATTR_P_INVALID 531
263	/** DS.Attr.DPL and DS RPL unequal. */
264	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
265	/** DS.Attr reserved bits not set to 0. */
266	#define VMX_IGS_DS_ATTR_RESERVED 533
267	/** DS.Attr.G bit invalid. */
268	#define VMX_IGS_DS_ATTR_G_INVALID 534
269	/** DS.Attr.Type invalid. */
270	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
271	/** ES.Attr.A bit invalid. */
272	#define VMX_IGS_ES_ATTR_A_INVALID 536
273	/** ES.Attr.P bit invalid. */
274	#define VMX_IGS_ES_ATTR_P_INVALID 537
275	/** ES.Attr.DPL and DS RPL unequal. */
276	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
277	/** ES.Attr reserved bits not set to 0. */
278	#define VMX_IGS_ES_ATTR_RESERVED 539
279	/** ES.Attr.G bit invalid. */
280	#define VMX_IGS_ES_ATTR_G_INVALID 540
281	/** ES.Attr.Type invalid. */
282	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
283	/** FS.Attr.A bit invalid. */
284	#define VMX_IGS_FS_ATTR_A_INVALID 542
285	/** FS.Attr.P bit invalid. */
286	#define VMX_IGS_FS_ATTR_P_INVALID 543
287	/** FS.Attr.DPL and DS RPL unequal. */
288	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
289	/** FS.Attr reserved bits not set to 0. */
290	#define VMX_IGS_FS_ATTR_RESERVED 545
291	/** FS.Attr.G bit invalid. */
292	#define VMX_IGS_FS_ATTR_G_INVALID 546
293	/** FS.Attr.Type invalid. */
294	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
295	/** GS.Attr.A bit invalid. */
296	#define VMX_IGS_GS_ATTR_A_INVALID 548
297	/** GS.Attr.P bit invalid. */
298	#define VMX_IGS_GS_ATTR_P_INVALID 549
299	/** GS.Attr.DPL and DS RPL unequal. */
300	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
301	/** GS.Attr reserved bits not set to 0. */
302	#define VMX_IGS_GS_ATTR_RESERVED 551
303	/** GS.Attr.G bit invalid. */
304	#define VMX_IGS_GS_ATTR_G_INVALID 552
305	/** GS.Attr.Type invalid. */
306	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
307	/** V86 mode CS.Base invalid. */
308	#define VMX_IGS_V86_CS_BASE_INVALID 554
309	/** V86 mode CS.Limit invalid. */
310	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
311	/** V86 mode CS.Attr invalid. */
312	#define VMX_IGS_V86_CS_ATTR_INVALID 556
313	/** V86 mode SS.Base invalid. */
314	#define VMX_IGS_V86_SS_BASE_INVALID 557
315	/** V86 mode SS.Limit invalid. */
316	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
317	/** V86 mode SS.Attr invalid. */
318	#define VMX_IGS_V86_SS_ATTR_INVALID 559
319	/** V86 mode DS.Base invalid. */
320	#define VMX_IGS_V86_DS_BASE_INVALID 560
321	/** V86 mode DS.Limit invalid. */
322	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
323	/** V86 mode DS.Attr invalid. */
324	#define VMX_IGS_V86_DS_ATTR_INVALID 562
325	/** V86 mode ES.Base invalid. */
326	#define VMX_IGS_V86_ES_BASE_INVALID 563
327	/** V86 mode ES.Limit invalid. */
328	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
329	/** V86 mode ES.Attr invalid. */
330	#define VMX_IGS_V86_ES_ATTR_INVALID 565
331	/** V86 mode FS.Base invalid. */
332	#define VMX_IGS_V86_FS_BASE_INVALID 566
333	/** V86 mode FS.Limit invalid. */
334	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
335	/** V86 mode FS.Attr invalid. */
336	#define VMX_IGS_V86_FS_ATTR_INVALID 568
337	/** V86 mode GS.Base invalid. */
338	#define VMX_IGS_V86_GS_BASE_INVALID 569
339	/** V86 mode GS.Limit invalid. */
340	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
341	/** V86 mode GS.Attr invalid. */
342	#define VMX_IGS_V86_GS_ATTR_INVALID 571
343	/** Longmode CS.Base invalid. */
344	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
345	/** Longmode SS.Base invalid. */
346	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
347	/** Longmode DS.Base invalid. */
348	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
349	/** Longmode ES.Base invalid. */
350	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
351	/** SYSENTER ESP is not canonical. */
352	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
353	/** SYSENTER EIP is not canonical. */
354	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
355	/** PAT MSR invalid. */
356	#define VMX_IGS_PAT_MSR_INVALID 578
357	/** PAT MSR reserved bits not set to 0. */
358	#define VMX_IGS_PAT_MSR_RESERVED 579
359	/** GDTR.Base is not canonical. */
360	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
361	/** IDTR.Base is not canonical. */
362	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
363	/** GDTR.Limit invalid. */
364	#define VMX_IGS_GDTR_LIMIT_INVALID 582
365	/** IDTR.Limit invalid. */
366	#define VMX_IGS_IDTR_LIMIT_INVALID 583
367	/** Longmode RIP is invalid. */
368	#define VMX_IGS_LONGMODE_RIP_INVALID 584
369	/** RFLAGS reserved bits not set to 0. */
370	#define VMX_IGS_RFLAGS_RESERVED 585
371	/** RFLAGS RA1 reserved bits not set to 1. */
372	#define VMX_IGS_RFLAGS_RESERVED1 586
373	/** RFLAGS.VM (V86 mode) invalid. */
374	#define VMX_IGS_RFLAGS_VM_INVALID 587
375	/** RFLAGS.IF invalid. */
376	#define VMX_IGS_RFLAGS_IF_INVALID 588
377	/** Activity state invalid. */
378	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
379	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
380	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
381	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
382	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
383	/** Activity state SIPI WAIT invalid. */
384	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
385	/** Interruptibility state reserved bits not set to 0. */
386	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
387	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
388	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
389	/** Interruptibility state block-by-STI invalid for EFLAGS. */
390	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
391	/** Interruptibility state invalid while trying to deliver external
392	* interrupt. */
393	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
394	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
395	* NMI. */
396	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
397	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
398	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
399	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
400	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
401	/** Interruptibility state block-by-STI (maybe) invalid when trying to
402	* deliver an NMI. */
403	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
404	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
405	* active. */
406	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
407	/** Pending debug exceptions reserved bits not set to 0. */
408	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
409	/** Longmode pending debug exceptions reserved bits not set to 0. */
410	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
411	/** Pending debug exceptions.BS bit is not set when it should be. */
412	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
413	/** Pending debug exceptions.BS bit is not clear when it should be. */
414	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
415	/** VMCS link pointer reserved bits not set to 0. */
416	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
417	/** TR cannot index into LDT, TI bit MBZ. */
418	#define VMX_IGS_TR_TI_INVALID 607
419	/** LDTR cannot index into LDT. TI bit MBZ. */
420	#define VMX_IGS_LDTR_TI_INVALID 608
421	/** TR.Base is not canonical. */
422	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
423	/** FS.Base is not canonical. */
424	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
425	/** GS.Base is not canonical. */
426	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
427	/** LDTR.Base is not canonical. */
428	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
429	/** TR is unusable. */
430	#define VMX_IGS_TR_ATTR_UNUSABLE 613
431	/** TR.Attr.S bit invalid. */
432	#define VMX_IGS_TR_ATTR_S_INVALID 614
433	/** TR is not present. */
434	#define VMX_IGS_TR_ATTR_P_INVALID 615
435	/** TR.Attr reserved bits not set to 0. */
436	#define VMX_IGS_TR_ATTR_RESERVED 616
437	/** TR.Attr.G bit invalid. */
438	#define VMX_IGS_TR_ATTR_G_INVALID 617
439	/** Longmode TR.Attr.Type invalid. */
440	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
441	/** TR.Attr.Type invalid. */
442	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
443	/** CS.Attr.S invalid. */
444	#define VMX_IGS_CS_ATTR_S_INVALID 620
445	/** CS.Attr.DPL invalid. */
446	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
447	/** PAE PDPTE reserved bits not set to 0. */
448	#define VMX_IGS_PAE_PDPTE_RESERVED 623
449	/** @} */
450
451	/** @name VMX VMCS-Read cache indices.
452	* @{
453	*/
454	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
455	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
456	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
457	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
458	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
459	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
460	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
461	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
462	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
463	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
464	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
465	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
466	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
467	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
468	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
469	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
470	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
471	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
472	/** @} */
473
474	/** @name VMX EPT paging structures
475	* @{
476	*/
477
478	/**
479	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
480	*/
481	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
482
483	/**
484	* EPT Page Directory Pointer Entry. Bit view.
485	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
486	* this did cause trouble with one compiler/version).
487	*/
488	typedef struct EPTPML4EBITS
489	{
490	/** Present bit. */
491	uint64_t u1Present : 1;
492	/** Writable bit. */
493	uint64_t u1Write : 1;
494	/** Executable bit. */
495	uint64_t u1Execute : 1;
496	/** Reserved (must be 0). */
497	uint64_t u5Reserved : 5;
498	/** Available for software. */
499	uint64_t u4Available : 4;
500	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
501	uint64_t u40PhysAddr : 40;
502	/** Available for software. */
503	uint64_t u12Available : 12;
504	} EPTPML4EBITS;
505	AssertCompileSize(EPTPML4EBITS, 8);
506
507	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
508	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
509	/** The page shift to get the PML4 index. */
510	#define EPT_PML4_SHIFT X86_PML4_SHIFT
511	/** The PML4 index mask (apply to a shifted page address). */
512	#define EPT_PML4_MASK X86_PML4_MASK
513
514	/**
515	* EPT PML4E.
516	*/
517	typedef union EPTPML4E
518	{
519	/** Normal view. */
520	EPTPML4EBITS n;
521	/** Unsigned integer view. */
522	X86PGPAEUINT u;
523	/** 64 bit unsigned integer view. */
524	uint64_t au64[1];
525	/** 32 bit unsigned integer view. */
526	uint32_t au32[2];
527	} EPTPML4E;
528	AssertCompileSize(EPTPML4E, 8);
529	/** Pointer to a PML4 table entry. */
530	typedef EPTPML4E *PEPTPML4E;
531	/** Pointer to a const PML4 table entry. */
532	typedef const EPTPML4E *PCEPTPML4E;
533
534	/**
535	* EPT PML4 Table.
536	*/
537	typedef struct EPTPML4
538	{
539	EPTPML4E a[EPT_PG_ENTRIES];
540	} EPTPML4;
541	AssertCompileSize(EPTPML4, 0x1000);
542	/** Pointer to an EPT PML4 Table. */
543	typedef EPTPML4 *PEPTPML4;
544	/** Pointer to a const EPT PML4 Table. */
545	typedef const EPTPML4 *PCEPTPML4;
546
547	/**
548	* EPT Page Directory Pointer Entry. Bit view.
549	*/
550	typedef struct EPTPDPTEBITS
551	{
552	/** Present bit. */
553	uint64_t u1Present : 1;
554	/** Writable bit. */
555	uint64_t u1Write : 1;
556	/** Executable bit. */
557	uint64_t u1Execute : 1;
558	/** Reserved (must be 0). */
559	uint64_t u5Reserved : 5;
560	/** Available for software. */
561	uint64_t u4Available : 4;
562	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
563	uint64_t u40PhysAddr : 40;
564	/** Available for software. */
565	uint64_t u12Available : 12;
566	} EPTPDPTEBITS;
567	AssertCompileSize(EPTPDPTEBITS, 8);
568
569	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
570	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
571	/** The page shift to get the PDPT index. */
572	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
573	/** The PDPT index mask (apply to a shifted page address). */
574	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
575
576	/**
577	* EPT Page Directory Pointer.
578	*/
579	typedef union EPTPDPTE
580	{
581	/** Normal view. */
582	EPTPDPTEBITS n;
583	/** Unsigned integer view. */
584	X86PGPAEUINT u;
585	/** 64 bit unsigned integer view. */
586	uint64_t au64[1];
587	/** 32 bit unsigned integer view. */
588	uint32_t au32[2];
589	} EPTPDPTE;
590	AssertCompileSize(EPTPDPTE, 8);
591	/** Pointer to an EPT Page Directory Pointer Entry. */
592	typedef EPTPDPTE *PEPTPDPTE;
593	/** Pointer to a const EPT Page Directory Pointer Entry. */
594	typedef const EPTPDPTE *PCEPTPDPTE;
595
596	/**
597	* EPT Page Directory Pointer Table.
598	*/
599	typedef struct EPTPDPT
600	{
601	EPTPDPTE a[EPT_PG_ENTRIES];
602	} EPTPDPT;
603	AssertCompileSize(EPTPDPT, 0x1000);
604	/** Pointer to an EPT Page Directory Pointer Table. */
605	typedef EPTPDPT *PEPTPDPT;
606	/** Pointer to a const EPT Page Directory Pointer Table. */
607	typedef const EPTPDPT *PCEPTPDPT;
608
609
610	/**
611	* EPT Page Directory Table Entry. Bit view.
612	*/
613	typedef struct EPTPDEBITS
614	{
615	/** Present bit. */
616	uint64_t u1Present : 1;
617	/** Writable bit. */
618	uint64_t u1Write : 1;
619	/** Executable bit. */
620	uint64_t u1Execute : 1;
621	/** Reserved (must be 0). */
622	uint64_t u4Reserved : 4;
623	/** Big page (must be 0 here). */
624	uint64_t u1Size : 1;
625	/** Available for software. */
626	uint64_t u4Available : 4;
627	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
628	uint64_t u40PhysAddr : 40;
629	/** Available for software. */
630	uint64_t u12Available : 12;
631	} EPTPDEBITS;
632	AssertCompileSize(EPTPDEBITS, 8);
633
634	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
635	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
636	/** The page shift to get the PD index. */
637	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
638	/** The PD index mask (apply to a shifted page address). */
639	#define EPT_PD_MASK X86_PD_PAE_MASK
640
641	/**
642	* EPT 2MB Page Directory Table Entry. Bit view.
643	*/
644	typedef struct EPTPDE2MBITS
645	{
646	/** Present bit. */
647	uint64_t u1Present : 1;
648	/** Writable bit. */
649	uint64_t u1Write : 1;
650	/** Executable bit. */
651	uint64_t u1Execute : 1;
652	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
653	uint64_t u3EMT : 3;
654	/** Ignore PAT memory type */
655	uint64_t u1IgnorePAT : 1;
656	/** Big page (must be 1 here). */
657	uint64_t u1Size : 1;
658	/** Available for software. */
659	uint64_t u4Available : 4;
660	/** Reserved (must be 0). */
661	uint64_t u9Reserved : 9;
662	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
663	uint64_t u31PhysAddr : 31;
664	/** Available for software. */
665	uint64_t u12Available : 12;
666	} EPTPDE2MBITS;
667	AssertCompileSize(EPTPDE2MBITS, 8);
668
669	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
670	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
671
672	/**
673	* EPT Page Directory Table Entry.
674	*/
675	typedef union EPTPDE
676	{
677	/** Normal view. */
678	EPTPDEBITS n;
679	/** 2MB view (big). */
680	EPTPDE2MBITS b;
681	/** Unsigned integer view. */
682	X86PGPAEUINT u;
683	/** 64 bit unsigned integer view. */
684	uint64_t au64[1];
685	/** 32 bit unsigned integer view. */
686	uint32_t au32[2];
687	} EPTPDE;
688	AssertCompileSize(EPTPDE, 8);
689	/** Pointer to an EPT Page Directory Table Entry. */
690	typedef EPTPDE *PEPTPDE;
691	/** Pointer to a const EPT Page Directory Table Entry. */
692	typedef const EPTPDE *PCEPTPDE;
693
694	/**
695	* EPT Page Directory Table.
696	*/
697	typedef struct EPTPD
698	{
699	EPTPDE a[EPT_PG_ENTRIES];
700	} EPTPD;
701	AssertCompileSize(EPTPD, 0x1000);
702	/** Pointer to an EPT Page Directory Table. */
703	typedef EPTPD *PEPTPD;
704	/** Pointer to a const EPT Page Directory Table. */
705	typedef const EPTPD *PCEPTPD;
706
707
708	/**
709	* EPT Page Table Entry. Bit view.
710	*/
711	typedef struct EPTPTEBITS
712	{
713	/** 0 - Present bit.
714	* @remark This is a convenience "misnomer". The bit actually indicates
715	* read access and the CPU will consider an entry with any of the
716	* first three bits set as present. Since all our valid entries
717	* will have this bit set, it can be used as a present indicator
718	* and allow some code sharing. */
719	uint64_t u1Present : 1;
720	/** 1 - Writable bit. */
721	uint64_t u1Write : 1;
722	/** 2 - Executable bit. */
723	uint64_t u1Execute : 1;
724	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
725	uint64_t u3EMT : 3;
726	/** 6 - Ignore PAT memory type */
727	uint64_t u1IgnorePAT : 1;
728	/** 11:7 - Available for software. */
729	uint64_t u5Available : 5;
730	/** 51:12 - Physical address of page. Restricted by maximum physical
731	* address width of the cpu. */
732	uint64_t u40PhysAddr : 40;
733	/** 63:52 - Available for software. */
734	uint64_t u12Available : 12;
735	} EPTPTEBITS;
736	AssertCompileSize(EPTPTEBITS, 8);
737
738	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
739	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
740	/** The page shift to get the EPT PTE index. */
741	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
742	/** The EPT PT index mask (apply to a shifted page address). */
743	#define EPT_PT_MASK X86_PT_PAE_MASK
744
745	/**
746	* EPT Page Table Entry.
747	*/
748	typedef union EPTPTE
749	{
750	/** Normal view. */
751	EPTPTEBITS n;
752	/** Unsigned integer view. */
753	X86PGPAEUINT u;
754	/** 64 bit unsigned integer view. */
755	uint64_t au64[1];
756	/** 32 bit unsigned integer view. */
757	uint32_t au32[2];
758	} EPTPTE;
759	AssertCompileSize(EPTPTE, 8);
760	/** Pointer to an EPT Page Directory Table Entry. */
761	typedef EPTPTE *PEPTPTE;
762	/** Pointer to a const EPT Page Directory Table Entry. */
763	typedef const EPTPTE *PCEPTPTE;
764
765	/**
766	* EPT Page Table.
767	*/
768	typedef struct EPTPT
769	{
770	EPTPTE a[EPT_PG_ENTRIES];
771	} EPTPT;
772	AssertCompileSize(EPTPT, 0x1000);
773	/** Pointer to an extended page table. */
774	typedef EPTPT *PEPTPT;
775	/** Pointer to a const extended table. */
776	typedef const EPTPT *PCEPTPT;
777
778	/** @} */
779
780	/** VMX VPID flush types.
781	* @note Valid enum members are in accordance to the VT-x spec.
782	*/
783	typedef enum
784	{
785	/** Invalidate a specific page. */
786	VMXFLUSHVPID_INDIV_ADDR = 0,
787	/** Invalidate one context (specific VPID). */
788	VMXFLUSHVPID_SINGLE_CONTEXT = 1,
789	/** Invalidate all contexts (all VPIDs). */
790	VMXFLUSHVPID_ALL_CONTEXTS = 2,
791	/** Invalidate a single VPID context retaining global mappings. */
792	VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
793	/** Unsupported by VirtualBox. */
794	VMXFLUSHVPID_NOT_SUPPORTED = 0xbad0,
795	/** Unsupported by CPU. */
796	VMXFLUSHVPID_NONE = 0xbad1
797	} VMXFLUSHVPID;
798	AssertCompileSize(VMXFLUSHVPID, 4);
799
800	/** VMX EPT flush types.
801	* @note Valid enums values are in accordance to the VT-x spec.
802	*/
803	typedef enum
804	{
805	/** Invalidate one context (specific EPT). */
806	VMXFLUSHEPT_SINGLE_CONTEXT = 1,
807	/* Invalidate all contexts (all EPTs) */
808	VMXFLUSHEPT_ALL_CONTEXTS = 2,
809	/** Unsupported by VirtualBox. */
810	VMXFLUSHEPT_NOT_SUPPORTED = 0xbad0,
811	/** Unsupported by CPU. */
812	VMXFLUSHEPT_NONE = 0xbad1
813	} VMXFLUSHEPT;
814	AssertCompileSize(VMXFLUSHEPT, 4);
815
816	/** VMX Posted Interrupt Descriptor.
817	* In accordance to the VT-x spec.
818	*/
819	typedef struct VMXPOSTEDINTRDESC
820	{
821	uint32_t aVectorBitmap[8];
822	uint32_t fOutstandingNotification : 1;
823	uint32_t uReserved0 : 31;
824	uint8_t au8Reserved0[28];
825	} VMXPOSTEDINTRDESC;
826	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
827	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
828	/** Pointer to a posted interrupt descriptor. */
829	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
830	/** Pointer to a const posted interrupt descriptor. */
831	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
832
833	/** VMX MSR autoload/store element.
834	* In accordance to the VT-x spec.
835	*/
836	typedef struct VMXAUTOMSR
837	{
838	/** The MSR Id. */
839	uint32_t u32Msr;
840	/** Reserved (MBZ). */
841	uint32_t u32Reserved;
842	/** The MSR value. */
843	uint64_t u64Value;
844	} VMXAUTOMSR;
845	AssertCompileSize(VMXAUTOMSR, 16);
846	/** Pointer to an MSR load/store element. */
847	typedef VMXAUTOMSR *PVMXAUTOMSR;
848	/** Pointer to a const MSR load/store element. */
849	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
850
851	/**
852	* VMX-capability qword
853	*/
854	typedef union
855	{
856	struct
857	{
858	/** Bits set here -must- be set in the corresponding VM-execution controls. */
859	uint32_t disallowed0;
860	/** Bits cleared here -must- be cleared in the corresponding VM-execution
861	* controls. */
862	uint32_t allowed1;
863	} n;
864	uint64_t u;
865	} VMXCAPABILITY;
866	AssertCompileSize(VMXCAPABILITY, 8);
867
868	/**
869	* VMX MSRs.
870	*/
871	typedef struct VMXMSRS
872	{
873	uint64_t u64FeatureCtrl;
874	uint64_t u64BasicInfo;
875	VMXCAPABILITY VmxPinCtls;
876	VMXCAPABILITY VmxProcCtls;
877	VMXCAPABILITY VmxProcCtls2;
878	VMXCAPABILITY VmxExit;
879	VMXCAPABILITY VmxEntry;
880	uint64_t u64Misc;
881	uint64_t u64Cr0Fixed0;
882	uint64_t u64Cr0Fixed1;
883	uint64_t u64Cr4Fixed0;
884	uint64_t u64Cr4Fixed1;
885	uint64_t u64VmcsEnum;
886	uint64_t u64Vmfunc;
887	uint64_t u64EptVpidCaps;
888	} VMXMSRS;
889	AssertCompileSizeAlignment(VMXMSRS, 8);
890	/** Pointer to a VMXMSRS struct. */
891	typedef VMXMSRS *PVMXMSRS;
892
893	/** @name VMX EFLAGS reserved bits.
894	* @{
895	*/
896	/** And-mask for setting reserved bits to zero */
897	#define VMX_EFLAGS_RESERVED_0 (X86_EFL_1 \| X86_EFL_LIVE_MASK)
898	/** Or-mask for setting reserved bits to 1 */
899	#define VMX_EFLAGS_RESERVED_1 X86_EFL_1
900	/** @} */
901
902	/** @name VMX Basic Exit Reasons.
903	* @{
904	*/
905	/** -1 Invalid exit code */
906	#define VMX_EXIT_INVALID -1
907	/** 0 Exception or non-maskable interrupt (NMI). */
908	#define VMX_EXIT_XCPT_OR_NMI 0
909	/** 1 External interrupt. */
910	#define VMX_EXIT_EXT_INT 1
911	/** 2 Triple fault. */
912	#define VMX_EXIT_TRIPLE_FAULT 2
913	/** 3 INIT signal. */
914	#define VMX_EXIT_INIT_SIGNAL 3
915	/** 4 Start-up IPI (SIPI). */
916	#define VMX_EXIT_SIPI 4
917	/** 5 I/O system-management interrupt (SMI). */
918	#define VMX_EXIT_IO_SMI 5
919	/** 6 Other SMI. */
920	#define VMX_EXIT_SMI 6
921	/** 7 Interrupt window exiting. */
922	#define VMX_EXIT_INT_WINDOW 7
923	/** 8 NMI window exiting. */
924	#define VMX_EXIT_NMI_WINDOW 8
925	/** 9 Task switch. */
926	#define VMX_EXIT_TASK_SWITCH 9
927	/** 10 Guest software attempted to execute CPUID. */
928	#define VMX_EXIT_CPUID 10
929	/** 11 Guest software attempted to execute GETSEC. */
930	#define VMX_EXIT_GETSEC 11
931	/** 12 Guest software attempted to execute HLT. */
932	#define VMX_EXIT_HLT 12
933	/** 13 Guest software attempted to execute INVD. */
934	#define VMX_EXIT_INVD 13
935	/** 14 Guest software attempted to execute INVLPG. */
936	#define VMX_EXIT_INVLPG 14
937	/** 15 Guest software attempted to execute RDPMC. */
938	#define VMX_EXIT_RDPMC 15
939	/** 16 Guest software attempted to execute RDTSC. */
940	#define VMX_EXIT_RDTSC 16
941	/** 17 Guest software attempted to execute RSM in SMM. */
942	#define VMX_EXIT_RSM 17
943	/** 18 Guest software executed VMCALL. */
944	#define VMX_EXIT_VMCALL 18
945	/** 19 Guest software executed VMCLEAR. */
946	#define VMX_EXIT_VMCLEAR 19
947	/** 20 Guest software executed VMLAUNCH. */
948	#define VMX_EXIT_VMLAUNCH 20
949	/** 21 Guest software executed VMPTRLD. */
950	#define VMX_EXIT_VMPTRLD 21
951	/** 22 Guest software executed VMPTRST. */
952	#define VMX_EXIT_VMPTRST 22
953	/** 23 Guest software executed VMREAD. */
954	#define VMX_EXIT_VMREAD 23
955	/** 24 Guest software executed VMRESUME. */
956	#define VMX_EXIT_VMRESUME 24
957	/** 25 Guest software executed VMWRITE. */
958	#define VMX_EXIT_VMWRITE 25
959	/** 26 Guest software executed VMXOFF. */
960	#define VMX_EXIT_VMXOFF 26
961	/** 27 Guest software executed VMXON. */
962	#define VMX_EXIT_VMXON 27
963	/** 28 Control-register accesses. */
964	#define VMX_EXIT_MOV_CRX 28
965	/** 29 Debug-register accesses. */
966	#define VMX_EXIT_MOV_DRX 29
967	/** 30 I/O instruction. */
968	#define VMX_EXIT_IO_INSTR 30
969	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
970	#define VMX_EXIT_RDMSR 31
971	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
972	#define VMX_EXIT_WRMSR 32
973	/** 33 VM-entry failure due to invalid guest state. */
974	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
975	/** 34 VM-entry failure due to MSR loading. */
976	#define VMX_EXIT_ERR_MSR_LOAD 34
977	/** 36 Guest software executed MWAIT. */
978	#define VMX_EXIT_MWAIT 36
979	/** 37 VM-exit due to monitor trap flag. */
980	#define VMX_EXIT_MTF 37
981	/** 39 Guest software attempted to execute MONITOR. */
982	#define VMX_EXIT_MONITOR 39
983	/** 40 Guest software attempted to execute PAUSE. */
984	#define VMX_EXIT_PAUSE 40
985	/** 41 VM-entry failure due to machine-check. */
986	#define VMX_EXIT_ERR_MACHINE_CHECK 41
987	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
988	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
989	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
990	#define VMX_EXIT_APIC_ACCESS 44
991	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual interrupt
992	whose vector indexed a bit set in the EOI-exit bitmap. */
993	#define VMX_EXIT_VIRTUALIZED_EOI 45
994	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
995	#define VMX_EXIT_XDTR_ACCESS 46
996	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
997	#define VMX_EXIT_TR_ACCESS 47
998	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
999	#define VMX_EXIT_EPT_VIOLATION 48
1000	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
1001	#define VMX_EXIT_EPT_MISCONFIG 49
1002	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1003	#define VMX_EXIT_INVEPT 50
1004	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1005	#define VMX_EXIT_RDTSCP 51
1006	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1007	#define VMX_EXIT_PREEMPT_TIMER 52
1008	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1009	#define VMX_EXIT_INVVPID 53
1010	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1011	#define VMX_EXIT_WBINVD 54
1012	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1013	#define VMX_EXIT_XSETBV 55
1014	/** 56 APIC write. Guest completed write to virtual-APIC. */
1015	#define VMX_EXIT_APIC_WRITE 56
1016	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1017	#define VMX_EXIT_RDRAND 57
1018	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1019	#define VMX_EXIT_INVPCID 58
1020	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1021	#define VMX_EXIT_VMFUNC 59
1022	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1023	#define VMX_EXIT_ENCLS 60
1024	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1025	* enabled. */
1026	#define VMX_EXIT_RDSEED 61
1027	/** 62 - Page-modification log full. */
1028	#define VMX_EXIT_PML_FULL 62
1029	/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
1030	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1031	#define VMX_EXIT_XSAVES 63
1032	/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
1033	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1034	#define VMX_EXIT_XRSTORS 64
1035	/** The maximum exit value (inclusive). */
1036	#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
1037	/** @} */
1038
1039
1040	/** @name VM Instruction Errors
1041	* @{
1042	*/
1043	/** VMCALL executed in VMX root operation. */
1044	#define VMX_ERROR_VMCALL 1
1045	/** VMCLEAR with invalid physical address. */
1046	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1047	/** VMCLEAR with VMXON pointer. */
1048	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1049	/** VMLAUNCH with non-clear VMCS. */
1050	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1051	/** VMRESUME with non-launched VMCS. */
1052	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1053	/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1054	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1055	/** VM-entry with invalid control field(s). */
1056	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1057	/** VM-entry with invalid host-state field(s). */
1058	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1059	/** VMPTRLD with invalid physical address. */
1060	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1061	/** VMPTRLD with VMXON pointer. */
1062	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1063	/** VMPTRLD with incorrect VMCS revision identifier. */
1064	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1065	/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1066	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1067	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1068	/** VMWRITE to read-only VMCS component. */
1069	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1070	/** VMXON executed in VMX root operation. */
1071	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1072	/** VM-entry with invalid executive-VMCS pointer. */
1073	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1074	/** VM-entry with non-launched executive VMCS. */
1075	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1076	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1077	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1078	/** VMCALL with non-clear VMCS. */
1079	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1080	/** VMCALL with invalid VM-exit control fields. */
1081	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1082	/** VMCALL with incorrect MSEG revision identifier. */
1083	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1084	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1085	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1086	/** VMCALL with invalid SMM-monitor features. */
1087	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1088	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1089	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1090	/** VM-entry with events blocked by MOV SS. */
1091	#define VMX_ERROR_VMENTRY_MOV_SS 26
1092	/** Invalid operand to INVEPT/INVVPID. */
1093	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1094	/** @} */
1095
1096
1097	/** @name VMX MSRs - Basic VMX information.
1098	* @{
1099	*/
1100	/** VMCS revision identifier used by the processor. */
1101	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) ((a) & 0x7FFFFFFF)
1102	/** Size of the VMCS. */
1103	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0x1FFF)
1104	/** Width of physical address used for the VMCS.
1105	* 0 -> limited to the available amount of physical ram
1106	* 1 -> within the first 4 GB
1107	*/
1108	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1109	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1110	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1111	/** Memory type that must be used for the VMCS. */
1112	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1113	/** Whether the processor provides additional information for exits due to INS/OUTS. */
1114	#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) ((a) & RT_BIT_64(54))
1115	/** Whether default 1 bits in control MSRs (pin/proc/exit/entry) may be
1116	* cleared to 0 and that 'true' control MSRs are supported. */
1117	#define MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(a) ((a) & RT_BIT_64(55))
1118	/** @} */
1119
1120
1121	/** @name VMX MSRs - Misc VMX info.
1122	* @{
1123	*/
1124	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1125	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1126	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1127	#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1128	/** Activity states supported by the implementation. */
1129	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1130	/** Number of CR3 target values supported by the processor. (0-256) */
1131	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1132	/** Maximum number of MSRs in the VMCS. (N+1)512. /
1133	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1134	/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1135	#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1136	/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1137	#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1138	/** Whether VMWRITE can be used to write VM-exit information fields. */
1139	#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1140	/** MSEG revision identifier used by the processor. */
1141	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1142	/** @} */
1143
1144
1145	/** @name VMX MSRs - VMCS enumeration field info
1146	* @{
1147	*/
1148	/** Highest field index. */
1149	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1150	/** @} */
1151
1152
1153	/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1154	* @{
1155	*/
1156	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1157	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1158	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1159	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1160	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1161	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1162	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1163	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1164	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1165	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1166	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1167	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1168	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1169	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1170	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1171	/** @} */
1172
1173	/** @name Extended Page Table Pointer (EPTP)
1174	* @{
1175	*/
1176	/** Uncachable EPT paging structure memory type. */
1177	#define VMX_EPT_MEMTYPE_UC 0
1178	/** Write-back EPT paging structure memory type. */
1179	#define VMX_EPT_MEMTYPE_WB 6
1180	/** Shift value to get the EPT page walk length (bits 5-3) */
1181	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1182	/** Mask value to get the EPT page walk length (bits 5-3) */
1183	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1184	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1185	* length) */
1186	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1187	/** @} */
1188
1189
1190	/** @name VMCS field encoding - 16 bits guest fields
1191	* @{
1192	*/
1193	#define VMX_VMCS16_VPID 0x000
1194	#define VMX_VMCS16_POSTED_INTR_NOTIFY_VECTOR 0x002
1195	#define VMX_VMCS16_EPTP_INDEX 0x004
1196	#define VMX_VMCS16_GUEST_ES_SEL 0x800
1197	#define VMX_VMCS16_GUEST_CS_SEL 0x802
1198	#define VMX_VMCS16_GUEST_SS_SEL 0x804
1199	#define VMX_VMCS16_GUEST_DS_SEL 0x806
1200	#define VMX_VMCS16_GUEST_FS_SEL 0x808
1201	#define VMX_VMCS16_GUEST_GS_SEL 0x80A
1202	#define VMX_VMCS16_GUEST_LDTR_SEL 0x80C
1203	#define VMX_VMCS16_GUEST_TR_SEL 0x80E
1204	#define VMX_VMCS16_GUEST_INTR_STATUS 0x810
1205	/** @} */
1206
1207	/** @name VMCS field encoding - 16 bits host fields
1208	* @{
1209	*/
1210	#define VMX_VMCS16_HOST_ES_SEL 0xC00
1211	#define VMX_VMCS16_HOST_CS_SEL 0xC02
1212	#define VMX_VMCS16_HOST_SS_SEL 0xC04
1213	#define VMX_VMCS16_HOST_DS_SEL 0xC06
1214	#define VMX_VMCS16_HOST_FS_SEL 0xC08
1215	#define VMX_VMCS16_HOST_GS_SEL 0xC0A
1216	#define VMX_VMCS16_HOST_TR_SEL 0xC0C
1217	/** @} */
1218
1219	/** @name VMCS field encoding - 64 bits host fields
1220	* @{
1221	*/
1222	#define VMX_VMCS64_HOST_PAT_FULL 0x2C00
1223	#define VMX_VMCS64_HOST_PAT_HIGH 0x2C01
1224	#define VMX_VMCS64_HOST_EFER_FULL 0x2C02
1225	#define VMX_VMCS64_HOST_EFER_HIGH 0x2C03
1226	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
1227	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
1228	/** @} */
1229
1230
1231	/** @name VMCS field encoding - 64 Bits control fields
1232	* @{
1233	*/
1234	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1235	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1236	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1237	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1238
1239	/* Optional */
1240	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1241	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1242
1243	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1244	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1245	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1246	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1247
1248	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1249	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1250
1251	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1252	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1253
1254	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1255	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1256
1257	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1258	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1259	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1260
1261	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1262	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1263	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1264
1265	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1266	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1267	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1268
1269	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1270	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1271	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1272
1273	/** Extended page table pointer. */
1274	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201A
1275	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201B
1276
1277	/** EOI-exit bitmap 0. */
1278	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201C
1279	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201D
1280
1281	/** EOI-exit bitmap 1. */
1282	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201E
1283	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201F
1284
1285	/** EOI-exit bitmap 2. */
1286	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1287	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1288
1289	/** EOI-exit bitmap 3. */
1290	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1291	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1292
1293	/** Extended page table pointer lists. */
1294	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1295	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1296
1297	/** VM-read bitmap. */
1298	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1299	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1300
1301	/** VM-write bitmap. */
1302	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1303	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1304
1305	/** Virtualization-exception information address. */
1306	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202A
1307	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202B
1308
1309	/** XSS-exiting bitmap. */
1310	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202C
1311	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202D
1312
1313	/** TSC multiplier. */
1314	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1315	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1316
1317	/** VM-exit guest physical address. */
1318	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1319	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1320	/** @} */
1321
1322
1323	/** @name VMCS field encoding - 64 Bits guest fields
1324	* @{
1325	*/
1326	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1327	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1328	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
1329	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
1330	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1331	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1332	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1333	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1334	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
1335	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
1336	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1337	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1338	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1339	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1340	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1341	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1342	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1343	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1344	/** @} */
1345
1346
1347	/** @name VMCS field encoding - 32 Bits control fields
1348	* @{
1349	*/
1350	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1351	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1352	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1353	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1354	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1355	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1356	#define VMX_VMCS32_CTRL_EXIT 0x400C
1357	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1358	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1359	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1360	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1361	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1362	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1363	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1364	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1365	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1366	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1367	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1368	/** @} */
1369
1370
1371	/** @name VMX_VMCS_CTRL_PIN_EXEC
1372	* @{
1373	*/
1374	/** External interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1375	#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1376	/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1377	#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1378	/** Virtual NMIs. */
1379	#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1380	/** Activate VMX preemption timer. */
1381	#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1382	/** Process interrupts with the posted-interrupt notification vector. */
1383	#define VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR RT_BIT(7)
1384	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1385	/** @} */
1386
1387	/** @name VMX_VMCS_CTRL_PROC_EXEC
1388	* @{
1389	*/
1390	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1391	#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1392	/** Use timestamp counter offset. */
1393	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1394	/** VM-exit when executing the HLT instruction. */
1395	#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1396	/** VM-exit when executing the INVLPG instruction. */
1397	#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1398	/** VM-exit when executing the MWAIT instruction. */
1399	#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1400	/** VM-exit when executing the RDPMC instruction. */
1401	#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1402	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1403	#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1404	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1405	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1406	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1407	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1408	/** VM-exit on CR8 loads. */
1409	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1410	/** VM-exit on CR8 stores. */
1411	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1412	/** Use TPR shadow. */
1413	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1414	/** VM-exit when virtual NMI blocking is disabled. */
1415	#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1416	/** VM-exit when executing a MOV DRx instruction. */
1417	#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1418	/** VM-exit when executing IO instructions. */
1419	#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1420	/** Use IO bitmaps. */
1421	#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1422	/** Monitor trap flag. */
1423	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1424	/** Use MSR bitmaps. */
1425	#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1426	/** VM-exit when executing the MONITOR instruction. */
1427	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1428	/** VM-exit when executing the PAUSE instruction. */
1429	#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1430	/** Determines whether the secondary processor based VM-execution controls are used. */
1431	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1432	/** @} */
1433
1434	/** @name VMX_VMCS_CTRL_PROC_EXEC2
1435	* @{
1436	*/
1437	/** Virtualize APIC access. */
1438	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1439	/** EPT supported/enabled. */
1440	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1441	/** Descriptor table instructions cause VM-exits. */
1442	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1443	/** RDTSCP supported/enabled. */
1444	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1445	/** Virtualize x2APIC mode. */
1446	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1447	/** VPID supported/enabled. */
1448	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1449	/** VM-exit when executing the WBINVD instruction. */
1450	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1451	/** Unrestricted guest execution. */
1452	#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1453	/** APIC register virtualization. */
1454	#define VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT RT_BIT(8)
1455	/** Virtual-interrupt delivery. */
1456	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY RT_BIT(9)
1457	/** A specified number of pause loops cause a VM-exit. */
1458	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1459	/** VM-exit when executing RDRAND instructions. */
1460	#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1461	/** Enables INVPCID instructions. */
1462	#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1463	/** Enables VMFUNC instructions. */
1464	#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1465	/** Enables VMCS shadowing. */
1466	#define VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING RT_BIT(14)
1467	/** Enables ENCLS VM-exits. */
1468	#define VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT RT_BIT(15)
1469	/** VM-exit when executing RDSEED. */
1470	#define VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT RT_BIT(16)
1471	/** Enables page-modification logging. */
1472	#define VMX_VMCS_CTRL_PROC_EXEC2_PML RT_BIT(17)
1473	/** Controls whether EPT-violations may cause \#VE instead of exits. */
1474	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE RT_BIT(18)
1475	/** Conceal VMX non-root operation from Intel processor trace (PT). */
1476	#define VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT RT_BIT(19)
1477	/** Enables XSAVES/XRSTORS instructions. */
1478	#define VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS RT_BIT(20)
1479	/** Use TSC scaling. */
1480	#define VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING RT_BIT(25)
1481
1482	/** @} */
1483
1484
1485	/** @name VMX_VMCS_CTRL_ENTRY
1486	* @{
1487	*/
1488	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1489	#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1490	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1491	#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1492	/** In SMM mode after VM-entry. */
1493	#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1494	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1495	#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1496	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
1497	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1498	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
1499	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1500	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
1501	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1502	/** @} */
1503
1504
1505	/** @name VMX_VMCS_CTRL_EXIT
1506	* @{
1507	*/
1508	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1509	#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1510	/** Return to long mode after a VM-exit. */
1511	#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1512	/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
1513	#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1514	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1515	#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1516	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
1517	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1518	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
1519	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1520	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
1521	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1522	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
1523	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1524	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
1525	#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1526	/** @} */
1527
1528
1529	/** @name VMX_VMCS_CTRL_VMFUNC
1530	* @{
1531	*/
1532	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1533	#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1534	/** @} */
1535
1536
1537	/** @name VMCS field encoding - 32 Bits read-only fields
1538	* @{
1539	*/
1540	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1541	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1542	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1543	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1544	#define VMX_VMCS32_RO_IDT_INFO 0x4408
1545	#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1546	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1547	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1548	/** @} */
1549
1550	/** @name VMX_VMCS32_RO_EXIT_REASON
1551	* @{
1552	*/
1553	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
1554	/** @} */
1555
1556	/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1557	* @{
1558	*/
1559	#define VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1560	#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1561	#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1562	/** @} */
1563
1564
1565	/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1566	* @{
1567	*/
1568	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) ((a) & 0xff)
1569	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1570	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1571	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1572	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1573	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(a) ((a) & RT_BIT(12))
1574	#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1575	#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1576	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1577	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
1578	/** @} */
1579
1580	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1581	* @{
1582	*/
1583	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1584	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1585	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1586	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4
1587	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT 5
1588	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1589	/** @} */
1590
1591	/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1592	* @{
1593	*/
1594	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
1595	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1596	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1597	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1598	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1599	#define VMX_IDT_VECTORING_INFO_VALID(a) ((a) & RT_BIT(31))
1600	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
1601	/** @} */
1602
1603	/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1604	* @{
1605	*/
1606	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1607	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1608	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1609	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1610	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1611	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1612	/** @} */
1613
1614
1615	/** @name VMCS field encoding - 32 Bits guest state fields
1616	* @{
1617	*/
1618	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1619	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1620	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1621	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1622	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1623	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1624	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1625	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1626	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1627	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1628	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1629	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1630	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1631	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1632	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1633	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1634	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1635	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1636	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1637	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1638	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
1639	#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1640	/** @} */
1641
1642
1643	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1644	* @{
1645	*/
1646	/** The logical processor is active. */
1647	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1648	/** The logical processor is inactive, because executed a HLT instruction. */
1649	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1650	/** The logical processor is inactive, because of a triple fault or other serious error. */
1651	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1652	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1653	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1654	/** @} */
1655
1656
1657	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1658	* @{
1659	*/
1660	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1661	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1662	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1663	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1664	/** @} */
1665
1666
1667	/** @name VMCS field encoding - 32 Bits host state fields
1668	* @{
1669	*/
1670	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1671	/** @} */
1672
1673	/** @name Natural width control fields
1674	* @{
1675	*/
1676	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1677	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1678	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1679	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1680	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1681	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1682	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1683	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1684	/** @} */
1685
1686
1687	/** @name Natural width read-only data fields
1688	* @{
1689	*/
1690	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1691	#define VMX_VMCS_RO_IO_RCX 0x6402
1692	#define VMX_VMCS_RO_IO_RSX 0x6404
1693	#define VMX_VMCS_RO_IO_RDI 0x6406
1694	#define VMX_VMCS_RO_IO_RIP 0x6408
1695	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1696	/** @} */
1697
1698
1699	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1700	* @{
1701	*/
1702	/** 0-2: Debug register number */
1703	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) ((a) & 7)
1704	/** 3: Reserved; cleared to 0. */
1705	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) (((a) >> 3) & 1)
1706	/** 4: Direction of move (0 = write, 1 = read) */
1707	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) (((a) >> 4) & 1)
1708	/** 5-7: Reserved; cleared to 0. */
1709	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) (((a) >> 5) & 7)
1710	/** 8-11: General purpose register number. */
1711	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) (((a) >> 8) & 0xF)
1712	/** Rest: reserved. */
1713	/** @} */
1714
1715	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1716	* @{
1717	*/
1718	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1719	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1720	/** @} */
1721
1722
1723
1724	/** @name CRx accesses
1725	* @{
1726	*/
1727	/** 0-3: Control register number (0 for CLTS & LMSW) */
1728	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) ((a) & 0xF)
1729	/** 4-5: Access type. */
1730	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) (((a) >> 4) & 3)
1731	/** 6: LMSW operand type */
1732	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) (((a) >> 6) & 1)
1733	/** 7: Reserved; cleared to 0. */
1734	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) (((a) >> 7) & 1)
1735	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1736	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) (((a) >> 8) & 0xF)
1737	/** 12-15: Reserved; cleared to 0. */
1738	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) (((a) >> 12) & 0xF)
1739	/** 16-31: LMSW source data (else 0). */
1740	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) (((a) >> 16) & 0xFFFF)
1741	/* Rest: reserved. */
1742	/** @} */
1743
1744	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1745	* @{
1746	*/
1747	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1748	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1749	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1750	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1751	/** @} */
1752
1753	/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1754	* @{
1755	*/
1756	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
1757	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
1758	/** Task switch caused by a call instruction. */
1759	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1760	/** Task switch caused by an iret instruction. */
1761	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1762	/** Task switch caused by a jmp instruction. */
1763	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1764	/** Task switch caused by an interrupt gate. */
1765	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1766	/** @} */
1767
1768
1769	/** @name VMX_EXIT_EPT_VIOLATION
1770	* @{
1771	*/
1772	/** Set if the violation was caused by a data read. */
1773	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1774	/** Set if the violation was caused by a data write. */
1775	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1776	/** Set if the violation was caused by an instruction fetch. */
1777	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1778	/** AND of the present bit of all EPT structures. */
1779	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1780	/** AND of the write bit of all EPT structures. */
1781	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1782	/** AND of the execute bit of all EPT structures. */
1783	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1784	/** Set if the guest linear address field contains the faulting address. */
1785	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1786	/** If bit 7 is one: (reserved otherwise)
1787	* 1 - violation due to physical address access.
1788	* 0 - violation caused by page walk or access/dirty bit updates
1789	*/
1790	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1791	/** @} */
1792
1793
1794	/** @name VMX_EXIT_PORT_IO
1795	* @{
1796	*/
1797	/** 0-2: IO operation width. */
1798	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1799	/** 3: IO operation direction. */
1800	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1801	/** 4: String IO operation (INS / OUTS). */
1802	#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1803	/** 5: Repeated IO operation. */
1804	#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1805	/** 6: Operand encoding. */
1806	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1807	/** 16-31: IO Port (0-0xffff). */
1808	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1809	/* Rest reserved. */
1810	/** @} */
1811
1812	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1813	* @{
1814	*/
1815	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1816	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1817	/** @} */
1818
1819
1820	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1821	* @{
1822	*/
1823	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1824	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1825	/** @} */
1826
1827	/** @name VMX_EXIT_APIC_ACCESS
1828	* @{
1829	*/
1830	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of access within the APIC page. */
1831	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1832	/** 12-15: Access type. */
1833	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
1834	/* Rest reserved. */
1835	/** @} */
1836
1837
1838	/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE return values
1839	* @{
1840	*/
1841	/** Linear read access. */
1842	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1843	/** Linear write access. */
1844	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1845	/** Linear instruction fetch access. */
1846	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1847	/** Linear read/write access during event delivery. */
1848	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1849	/** Physical read/write access during event delivery. */
1850	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1851	/** Physical access for an instruction fetch or during instruction execution. */
1852	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1853	/** @} */
1854
1855	/** @name VMX_XDTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information
1856	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
1857	* @{
1858	*/
1859	/** Address calculation scaling field (powers of two). */
1860	#define VMX_XDTR_INSINFO_SCALE_SHIFT 0
1861	#define VMX_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
1862	/** Bits 2 thru 6 are undefined. */
1863	#define VMX_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
1864	#define VMX_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
1865	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
1866	* @remarks anyone's guess why this is a 3 bit field... */
1867	#define VMX_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
1868	#define VMX_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
1869	/** Bit 10 is defined as zero. */
1870	#define VMX_XDTR_INSINFO_ZERO_10_SHIFT 10
1871	#define VMX_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
1872	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
1873	* for exits from 64-bit code as the operand size there is fixed. */
1874	#define VMX_XDTR_INSINFO_OP_SIZE_SHIFT 11
1875	#define VMX_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
1876	/** Bits 12 thru 14 are undefined. */
1877	#define VMX_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
1878	#define VMX_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
1879	/** Applicable segment register (X86_SREG_XXX values). */
1880	#define VMX_XDTR_INSINFO_SREG_SHIFT 15
1881	#define VMX_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
1882	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
1883	#define VMX_XDTR_INSINFO_INDEX_REG_SHIFT 18
1884	#define VMX_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
1885	/** Is VMX_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
1886	#define VMX_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
1887	#define VMX_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
1888	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
1889	#define VMX_XDTR_INSINFO_BASE_REG_SHIFT 23
1890	#define VMX_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
1891	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
1892	#define VMX_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
1893	#define VMX_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
1894	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values) */
1895	#define VMX_XDTR_INSINFO_INSTR_ID_SHIFT 28
1896	#define VMX_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
1897	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
1898	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
1899	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
1900	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
1901	/** Bits 30 & 31 are undefined. */
1902	#define VMX_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
1903	#define VMX_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
1904	RT_BF_ASSERT_COMPILE_CHECKS(VMX_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
1905	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
1906	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
1907	/** @} */
1908
1909
1910	/** @name VMX_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information
1911	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
1912	* This is similar to VMX_XDTR_INSINFO_XXX.
1913	* @{
1914	*/
1915	/** Address calculation scaling field (powers of two). */
1916	#define VMX_YYTR_INSINFO_SCALE_SHIFT 0
1917	#define VMX_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
1918	/** Bit 2 is undefined. */
1919	#define VMX_YYTR_INSINFO_UNDEF_2_SHIFT 2
1920	#define VMX_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
1921	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
1922	#define VMX_YYTR_INSINFO_REG1_SHIFT 3
1923	#define VMX_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
1924	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
1925	* @remarks anyone's guess why this is a 3 bit field... */
1926	#define VMX_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
1927	#define VMX_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
1928	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
1929	#define VMX_YYTR_INSINFO_HAS_REG1_SHIFT 10
1930	#define VMX_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
1931	/** Bits 11 thru 14 are undefined. */
1932	#define VMX_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
1933	#define VMX_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
1934	/** Applicable segment register (X86_SREG_XXX values). */
1935	#define VMX_YYTR_INSINFO_SREG_SHIFT 15
1936	#define VMX_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
1937	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
1938	#define VMX_YYTR_INSINFO_INDEX_REG_SHIFT 18
1939	#define VMX_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
1940	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
1941	#define VMX_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
1942	#define VMX_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
1943	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
1944	#define VMX_YYTR_INSINFO_BASE_REG_SHIFT 23
1945	#define VMX_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
1946	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
1947	#define VMX_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
1948	#define VMX_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
1949	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
1950	#define VMX_YYTR_INSINFO_INSTR_ID_SHIFT 28
1951	#define VMX_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
1952	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
1953	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
1954	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
1955	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
1956	/** Bits 30 & 31 are undefined. */
1957	#define VMX_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
1958	#define VMX_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
1959	RT_BF_ASSERT_COMPILE_CHECKS(VMX_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
1960	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
1961	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
1962	/** @} */
1963
1964
1965	/** @name VMCS field encoding - Natural width guest state fields
1966	* @{
1967	*/
1968	#define VMX_VMCS_GUEST_CR0 0x6800
1969	#define VMX_VMCS_GUEST_CR3 0x6802
1970	#define VMX_VMCS_GUEST_CR4 0x6804
1971	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1972	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1973	#define VMX_VMCS_GUEST_SS_BASE 0x680A
1974	#define VMX_VMCS_GUEST_DS_BASE 0x680C
1975	#define VMX_VMCS_GUEST_FS_BASE 0x680E
1976	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1977	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1978	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1979	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1980	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1981	#define VMX_VMCS_GUEST_DR7 0x681A
1982	#define VMX_VMCS_GUEST_RSP 0x681C
1983	#define VMX_VMCS_GUEST_RIP 0x681E
1984	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1985	#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1986	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1987	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1988	/** @} */
1989
1990
1991	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1992	* Bits 4-11, 13 and 15-63 are reserved.
1993	* @{
1994	*/
1995	/** Hardware breakpoint 0 was met. */
1996	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1997	/** Hardware breakpoint 1 was met. */
1998	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1999	/** Hardware breakpoint 2 was met. */
2000	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
2001	/** Hardware breakpoint 3 was met. */
2002	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
2003	/** At least one data or IO breakpoint was hit. */
2004	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
2005	/** A debug exception would have been triggered by single-step execution mode. */
2006	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
2007	/** @} */
2008
2009	/** @name VMCS field encoding - Natural width host state fields
2010	* @{
2011	*/
2012	#define VMX_VMCS_HOST_CR0 0x6C00
2013	#define VMX_VMCS_HOST_CR3 0x6C02
2014	#define VMX_VMCS_HOST_CR4 0x6C04
2015	#define VMX_VMCS_HOST_FS_BASE 0x6C06
2016	#define VMX_VMCS_HOST_GS_BASE 0x6C08
2017	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
2018	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
2019	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
2020	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
2021	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
2022	#define VMX_VMCS_HOST_RSP 0x6C14
2023	#define VMX_VMCS_HOST_RIP 0x6C16
2024	/** @} */
2025
2026
2027	/** @defgroup grp_hm_vmx_asm VMX Assembly Helpers
2028	* @{
2029	*/
2030
2031	/**
2032	* Restores some host-state fields that need not be done on every VM-exit.
2033	*
2034	* @returns VBox status code.
2035	* @param fRestoreHostFlags Flags of which host registers needs to be
2036	* restored.
2037	* @param pRestoreHost Pointer to the host-restore structure.
2038	*/
2039	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
2040
2041
2042	/**
2043	* Dispatches an NMI to the host.
2044	*/
2045	DECLASM(int) VMXDispatchHostNmi(void);
2046
2047
2048	/**
2049	* Executes VMXON.
2050	*
2051	* @returns VBox status code.
2052	* @param HCPhysVmxOn Physical address of VMXON structure.
2053	*/
2054	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2055	DECLASM(int) VMXEnable(RTHCPHYS HCPhysVmxOn);
2056	#else
2057	DECLINLINE(int) VMXEnable(RTHCPHYS HCPhysVmxOn)
2058	{
2059	# if RT_INLINE_ASM_GNU_STYLE
2060	int rc = VINF_SUCCESS;
2061	__asm__ __volatile__ (
2062	"push %3 \n\t"
2063	"push %2 \n\t"
2064	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
2065	"ja 2f \n\t"
2066	"je 1f \n\t"
2067	"movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
2068	"jmp 2f \n\t"
2069	"1: \n\t"
2070	"movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
2071	"2: \n\t"
2072	"add $8, %%esp \n\t"
2073	:"=rm"(rc)
2074	:"0"(VINF_SUCCESS),
2075	"ir"((uint32_t)HCPhysVmxOn), /* don't allow direct memory reference here, */
2076	"ir"((uint32_t)(HCPhysVmxOn >> 32)) /* this would not work with -fomit-frame-pointer */
2077	:"memory"
2078	);
2079	return rc;
2080
2081	# elif VMX_USE_MSC_INTRINSICS
2082	unsigned char rcMsc = __vmx_on(&HCPhysVmxOn);
2083	if (RT_LIKELY(rcMsc == 0))
2084	return VINF_SUCCESS;
2085	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
2086
2087	# else
2088	int rc = VINF_SUCCESS;
2089	__asm
2090	{
2091	push dword ptr [HCPhysVmxOn + 4]
2092	push dword ptr [HCPhysVmxOn]
2093	_emit 0xF3
2094	_emit 0x0F
2095	_emit 0xC7
2096	_emit 0x34
2097	_emit 0x24 /* VMXON [esp] */
2098	jnc vmxon_good
2099	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
2100	jmp the_end
2101
2102	vmxon_good:
2103	jnz the_end
2104	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
2105	the_end:
2106	add esp, 8
2107	}
2108	return rc;
2109	# endif
2110	}
2111	#endif
2112
2113
2114	/**
2115	* Executes VMXOFF.
2116	*/
2117	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2118	DECLASM(void) VMXDisable(void);
2119	#else
2120	DECLINLINE(void) VMXDisable(void)
2121	{
2122	# if RT_INLINE_ASM_GNU_STYLE
2123	__asm__ __volatile__ (
2124	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
2125	);
2126
2127	# elif VMX_USE_MSC_INTRINSICS
2128	__vmx_off();
2129
2130	# else
2131	__asm
2132	{
2133	_emit 0x0F
2134	_emit 0x01
2135	_emit 0xC4 /* VMXOFF */
2136	}
2137	# endif
2138	}
2139	#endif
2140
2141
2142	/**
2143	* Executes VMCLEAR.
2144	*
2145	* @returns VBox status code.
2146	* @param HCPhysVmcs Physical address of VM control structure.
2147	*/
2148	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2149	DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
2150	#else
2151	DECLINLINE(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs)
2152	{
2153	# if RT_INLINE_ASM_GNU_STYLE
2154	int rc = VINF_SUCCESS;
2155	__asm__ __volatile__ (
2156	"push %3 \n\t"
2157	"push %2 \n\t"
2158	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
2159	"jnc 1f \n\t"
2160	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2161	"1: \n\t"
2162	"add $8, %%esp \n\t"
2163	:"=rm"(rc)
2164	:"0"(VINF_SUCCESS),
2165	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2166	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this would not work with -fomit-frame-pointer */
2167	:"memory"
2168	);
2169	return rc;
2170
2171	# elif VMX_USE_MSC_INTRINSICS
2172	unsigned char rcMsc = __vmx_vmclear(&HCPhysVmcs);
2173	if (RT_LIKELY(rcMsc == 0))
2174	return VINF_SUCCESS;
2175	return VERR_VMX_INVALID_VMCS_PTR;
2176
2177	# else
2178	int rc = VINF_SUCCESS;
2179	__asm
2180	{
2181	push dword ptr [HCPhysVmcs + 4]
2182	push dword ptr [HCPhysVmcs]
2183	_emit 0x66
2184	_emit 0x0F
2185	_emit 0xC7
2186	_emit 0x34
2187	_emit 0x24 /* VMCLEAR [esp] */
2188	jnc success
2189	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2190	success:
2191	add esp, 8
2192	}
2193	return rc;
2194	# endif
2195	}
2196	#endif
2197
2198
2199	/**
2200	* Executes VMPTRLD.
2201	*
2202	* @returns VBox status code.
2203	* @param HCPhysVmcs Physical address of VMCS structure.
2204	*/
2205	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2206	DECLASM(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs);
2207	#else
2208	DECLINLINE(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs)
2209	{
2210	# if RT_INLINE_ASM_GNU_STYLE
2211	int rc = VINF_SUCCESS;
2212	__asm__ __volatile__ (
2213	"push %3 \n\t"
2214	"push %2 \n\t"
2215	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2216	"jnc 1f \n\t"
2217	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2218	"1: \n\t"
2219	"add $8, %%esp \n\t"
2220	:"=rm"(rc)
2221	:"0"(VINF_SUCCESS),
2222	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2223	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this will not work with -fomit-frame-pointer */
2224	);
2225	return rc;
2226
2227	# elif VMX_USE_MSC_INTRINSICS
2228	unsigned char rcMsc = __vmx_vmptrld(&HCPhysVmcs);
2229	if (RT_LIKELY(rcMsc == 0))
2230	return VINF_SUCCESS;
2231	return VERR_VMX_INVALID_VMCS_PTR;
2232
2233	# else
2234	int rc = VINF_SUCCESS;
2235	__asm
2236	{
2237	push dword ptr [HCPhysVmcs + 4]
2238	push dword ptr [HCPhysVmcs]
2239	_emit 0x0F
2240	_emit 0xC7
2241	_emit 0x34
2242	_emit 0x24 /* VMPTRLD [esp] */
2243	jnc success
2244	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2245
2246	success:
2247	add esp, 8
2248	}
2249	return rc;
2250	# endif
2251	}
2252	#endif
2253
2254	/**
2255	* Executes VMPTRST.
2256	*
2257	* @returns VBox status code.
2258	* @param pHCPhysVmcs Where to store the physical address of the current
2259	* VMCS.
2260	*/
2261	DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
2262
2263	/**
2264	* Executes VMWRITE.
2265	*
2266	* @returns VBox status code.
2267	* @retval VINF_SUCCESS.
2268	* @retval VERR_VMX_INVALID_VMCS_PTR.
2269	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2270	*
2271	* @param idxField VMCS index.
2272	* @param u32Val 32-bit value.
2273	*
2274	* @remarks The values of the two status codes can be OR'ed together, the result
2275	* will be VERR_VMX_INVALID_VMCS_PTR.
2276	*/
2277	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2278	DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2279	#else
2280	DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2281	{
2282	# if RT_INLINE_ASM_GNU_STYLE
2283	int rc = VINF_SUCCESS;
2284	__asm__ __volatile__ (
2285	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2286	"ja 2f \n\t"
2287	"je 1f \n\t"
2288	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2289	"jmp 2f \n\t"
2290	"1: \n\t"
2291	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2292	"2: \n\t"
2293	:"=rm"(rc)
2294	:"0"(VINF_SUCCESS),
2295	"a"(idxField),
2296	"d"(u32Val)
2297	);
2298	return rc;
2299
2300	# elif VMX_USE_MSC_INTRINSICS
2301	unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2302	if (RT_LIKELY(rcMsc == 0))
2303	return VINF_SUCCESS;
2304	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2305
2306	#else
2307	int rc = VINF_SUCCESS;
2308	__asm
2309	{
2310	push dword ptr [u32Val]
2311	mov eax, [idxField]
2312	_emit 0x0F
2313	_emit 0x79
2314	_emit 0x04
2315	_emit 0x24 /* VMWRITE eax, [esp] */
2316	jnc valid_vmcs
2317	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2318	jmp the_end
2319
2320	valid_vmcs:
2321	jnz the_end
2322	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2323	the_end:
2324	add esp, 4
2325	}
2326	return rc;
2327	# endif
2328	}
2329	#endif
2330
2331	/**
2332	* Executes VMWRITE.
2333	*
2334	* @returns VBox status code.
2335	* @retval VINF_SUCCESS.
2336	* @retval VERR_VMX_INVALID_VMCS_PTR.
2337	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2338	*
2339	* @param idxField VMCS index.
2340	* @param u64Val 16, 32 or 64-bit value.
2341	*
2342	* @remarks The values of the two status codes can be OR'ed together, the result
2343	* will be VERR_VMX_INVALID_VMCS_PTR.
2344	*/
2345	#if !defined(RT_ARCH_X86)
2346	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
2347	DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2348	# else /* VMX_USE_MSC_INTRINSICS */
2349	DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2350	{
2351	unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2352	if (RT_LIKELY(rcMsc == 0))
2353	return VINF_SUCCESS;
2354	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2355	}
2356	# endif /* VMX_USE_MSC_INTRINSICS */
2357	#else
2358	# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2359	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2360	#endif
2361
2362	#if ARCH_BITS == 32
2363	# define VMXWriteVmcsHstN VMXWriteVmcs32
2364	# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2365	#else /* ARCH_BITS == 64 */
2366	# define VMXWriteVmcsHstN VMXWriteVmcs64
2367	# define VMXWriteVmcsGstN VMXWriteVmcs64
2368	#endif
2369
2370
2371	/**
2372	* Invalidate a page using INVEPT.
2373	*
2374	* @returns VBox status code.
2375	* @param enmFlush Type of flush.
2376	* @param pDescriptor Pointer to the descriptor.
2377	*/
2378	DECLASM(int) VMXR0InvEPT(VMXFLUSHEPT enmFlush, uint64_t *pDescriptor);
2379
2380	/**
2381	* Invalidate a page using INVVPID.
2382	*
2383	* @returns VBox status code.
2384	* @param enmFlush Type of flush.
2385	* @param pDescriptor Pointer to the descriptor.
2386	*/
2387	DECLASM(int) VMXR0InvVPID(VMXFLUSHVPID enmFlush, uint64_t *pDescriptor);
2388
2389	/**
2390	* Executes VMREAD.
2391	*
2392	* @returns VBox status code.
2393	* @retval VINF_SUCCESS.
2394	* @retval VERR_VMX_INVALID_VMCS_PTR.
2395	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2396	*
2397	* @param idxField VMCS index.
2398	* @param pData Where to store VM field value.
2399	*
2400	* @remarks The values of the two status codes can be OR'ed together, the result
2401	* will be VERR_VMX_INVALID_VMCS_PTR.
2402	*/
2403	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2404	DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2405	#else
2406	DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2407	{
2408	# if RT_INLINE_ASM_GNU_STYLE
2409	int rc = VINF_SUCCESS;
2410	__asm__ __volatile__ (
2411	"movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2412	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2413	"ja 2f \n\t"
2414	"je 1f \n\t"
2415	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2416	"jmp 2f \n\t"
2417	"1: \n\t"
2418	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2419	"2: \n\t"
2420	:"=&r"(rc),
2421	"=d"(*pData)
2422	:"a"(idxField),
2423	"d"(0)
2424	);
2425	return rc;
2426
2427	# elif VMX_USE_MSC_INTRINSICS
2428	unsigned char rcMsc;
2429	# if ARCH_BITS == 32
2430	rcMsc = __vmx_vmread(idxField, pData);
2431	# else
2432	uint64_t u64Tmp;
2433	rcMsc = __vmx_vmread(idxField, &u64Tmp);
2434	*pData = (uint32_t)u64Tmp;
2435	# endif
2436	if (RT_LIKELY(rcMsc == 0))
2437	return VINF_SUCCESS;
2438	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2439
2440	#else
2441	int rc = VINF_SUCCESS;
2442	__asm
2443	{
2444	sub esp, 4
2445	mov dword ptr [esp], 0
2446	mov eax, [idxField]
2447	_emit 0x0F
2448	_emit 0x78
2449	_emit 0x04
2450	_emit 0x24 /* VMREAD eax, [esp] */
2451	mov edx, pData
2452	pop dword ptr [edx]
2453	jnc valid_vmcs
2454	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2455	jmp the_end
2456
2457	valid_vmcs:
2458	jnz the_end
2459	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2460	the_end:
2461	}
2462	return rc;
2463	# endif
2464	}
2465	#endif
2466
2467	/**
2468	* Executes VMREAD.
2469	*
2470	* @returns VBox status code.
2471	* @retval VINF_SUCCESS.
2472	* @retval VERR_VMX_INVALID_VMCS_PTR.
2473	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2474	*
2475	* @param idxField VMCS index.
2476	* @param pData Where to store VM field value.
2477	*
2478	* @remarks The values of the two status codes can be OR'ed together, the result
2479	* will be VERR_VMX_INVALID_VMCS_PTR.
2480	*/
2481	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS)
2482	DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2483	#else
2484	DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2485	{
2486	# if VMX_USE_MSC_INTRINSICS
2487	unsigned char rcMsc;
2488	# if ARCH_BITS == 32
2489	size_t uLow;
2490	size_t uHigh;
2491	rcMsc = __vmx_vmread(idxField, &uLow);
2492	rcMsc \|= __vmx_vmread(idxField + 1, &uHigh);
2493	*pData = RT_MAKE_U64(uLow, uHigh);
2494	# else
2495	rcMsc = __vmx_vmread(idxField, pData);
2496	# endif
2497	if (RT_LIKELY(rcMsc == 0))
2498	return VINF_SUCCESS;
2499	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2500
2501	# elif ARCH_BITS == 32
2502	int rc;
2503	uint32_t val_hi, val;
2504	rc = VMXReadVmcs32(idxField, &val);
2505	rc \|= VMXReadVmcs32(idxField + 1, &val_hi);
2506	AssertRC(rc);
2507	*pData = RT_MAKE_U64(val, val_hi);
2508	return rc;
2509
2510	# else
2511	# error "Shouldn't be here..."
2512	# endif
2513	}
2514	#endif
2515
2516	/**
2517	* Gets the last instruction error value from the current VMCS.
2518	*
2519	* @returns VBox status code.
2520	*/
2521	DECLINLINE(uint32_t) VMXGetLastError(void)
2522	{
2523	#if ARCH_BITS == 64
2524	uint64_t uLastError = 0;
2525	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2526	AssertRC(rc);
2527	return (uint32_t)uLastError;
2528
2529	#else /* 32-bit host: */
2530	uint32_t uLastError = 0;
2531	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2532	AssertRC(rc);
2533	return uLastError;
2534	#endif
2535	}
2536
2537	#ifdef IN_RING0
2538	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2539	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2540	#endif /* IN_RING0 */
2541
2542	/** @} */
2543
2544	/** @} */
2545
2546	#endif
2547

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 72490

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