hm_vmx.h@ 72854

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VMM/HM: spaces, cleanup.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# pragma warning(push)
38	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
39	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
40	# include <intrin.h>
41	# pragma warning(pop)
42	/* We always want them as intrinsics, no functions. */
43	# pragma intrinsic(__vmx_on)
44	# pragma intrinsic(__vmx_off)
45	# pragma intrinsic(__vmx_vmclear)
46	# pragma intrinsic(__vmx_vmptrld)
47	# pragma intrinsic(__vmx_vmread)
48	# pragma intrinsic(__vmx_vmwrite)
49	# define VMX_USE_MSC_INTRINSICS 1
50	#else
51	# define VMX_USE_MSC_INTRINSICS 0
52	#endif
53
54
55	/** @defgroup grp_hm_vmx VMX Types and Definitions
56	* @ingroup grp_hm
57	* @{
58	*/
59
60	/** @name Host-state restoration flags.
61	* @note If you change these values don't forget to update the assembly
62	* defines as well!
63	* @{
64	*/
65	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
66	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
67	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
68	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
69	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
70	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
71	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
72	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
73	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
74	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
75	/** @} */
76
77	/**
78	* Host-state restoration structure.
79	* This holds host-state fields that require manual restoration.
80	* Assembly version found in hm_vmx.mac (should be automatically verified).
81	*/
82	typedef struct VMXRESTOREHOST
83	{
84	RTSEL uHostSelDS; /* 0x00 */
85	RTSEL uHostSelES; /* 0x02 */
86	RTSEL uHostSelFS; /* 0x04 */
87	RTSEL uHostSelGS; /* 0x06 */
88	RTSEL uHostSelTR; /* 0x08 */
89	uint8_t abPadding0[4];
90	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
91	uint8_t abPadding1[6];
92	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
93	uint8_t abPadding2[6];
94	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
95	uint64_t uHostFSBase; /* 0x38 */
96	uint64_t uHostGSBase; /* 0x40 */
97	} VMXRESTOREHOST;
98	/** Pointer to VMXRESTOREHOST. */
99	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
100	AssertCompileSize(X86XDTR64, 10);
101	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
102	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
103	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
104	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
105	AssertCompileSize(VMXRESTOREHOST, 72);
106	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
107
108	/** @name Host-state MSR lazy-restoration flags.
109	* @{
110	*/
111	/** The host MSRs have been saved. */
112	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
113	/** The guest MSRs are loaded and in effect. */
114	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
115	/** @} */
116
117	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
118	* UFC = Unsupported Feature Combination.
119	* @{
120	*/
121	/** Unsupported pin-based VM-execution controls combo. */
122	#define VMX_UFC_CTRL_PIN_EXEC 1
123	/** Unsupported processor-based VM-execution controls combo. */
124	#define VMX_UFC_CTRL_PROC_EXEC 2
125	/** Unsupported move debug register VM-exit combo. */
126	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
127	/** Unsupported VM-entry controls combo. */
128	#define VMX_UFC_CTRL_ENTRY 4
129	/** Unsupported VM-exit controls combo. */
130	#define VMX_UFC_CTRL_EXIT 5
131	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
132	* for storing host MSRs. */
133	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
134	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
135	* for storing guest MSRs. */
136	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
137	/** Invalid VMCS size. */
138	#define VMX_UFC_INVALID_VMCS_SIZE 8
139	/** Unsupported secondary processor-based VM-execution controls combo. */
140	#define VMX_UFC_CTRL_PROC_EXEC2 9
141	/** Invalid unrestricted-guest execution controls combo. */
142	#define VMX_UFC_INVALID_UX_COMBO 10
143	/** EPT flush type not supported. */
144	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
145	/** EPT paging structure memory type is not write-back. */
146	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
147	/** EPT requires INVEPT instr. support but it's not available. */
148	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
149	/** EPT requires page-walk length of 4. */
150	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
151	/** @} */
152
153	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
154	* IGS = Invalid Guest State.
155	* @{
156	*/
157	/** An error occurred while checking invalid-guest-state. */
158	#define VMX_IGS_ERROR 500
159	/** The invalid guest-state checks did not find any reason why. */
160	#define VMX_IGS_REASON_NOT_FOUND 501
161	/** CR0 fixed1 bits invalid. */
162	#define VMX_IGS_CR0_FIXED1 502
163	/** CR0 fixed0 bits invalid. */
164	#define VMX_IGS_CR0_FIXED0 503
165	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
166	#define VMX_IGS_CR0_PG_PE_COMBO 504
167	/** CR4 fixed1 bits invalid. */
168	#define VMX_IGS_CR4_FIXED1 505
169	/** CR4 fixed0 bits invalid. */
170	#define VMX_IGS_CR4_FIXED0 506
171	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
172	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
173	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
174	/** CR0.PG not set for long-mode when not using unrestricted guest. */
175	#define VMX_IGS_CR0_PG_LONGMODE 508
176	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
177	#define VMX_IGS_CR4_PAE_LONGMODE 509
178	/** CR4.PCIDE set for 32-bit guest. */
179	#define VMX_IGS_CR4_PCIDE 510
180	/** VMCS' DR7 reserved bits not set to 0. */
181	#define VMX_IGS_DR7_RESERVED 511
182	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
183	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
184	/** VMCS' EFER MSR reserved bits not set to 0. */
185	#define VMX_IGS_EFER_MSR_RESERVED 513
186	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
187	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
188	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
189	* without unrestricted guest. */
190	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
191	/** CS.Attr.P bit invalid. */
192	#define VMX_IGS_CS_ATTR_P_INVALID 516
193	/** CS.Attr reserved bits not set to 0. */
194	#define VMX_IGS_CS_ATTR_RESERVED 517
195	/** CS.Attr.G bit invalid. */
196	#define VMX_IGS_CS_ATTR_G_INVALID 518
197	/** CS is unusable. */
198	#define VMX_IGS_CS_ATTR_UNUSABLE 519
199	/** CS and SS DPL unequal. */
200	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
201	/** CS and SS DPL mismatch. */
202	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
203	/** CS Attr.Type invalid. */
204	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
205	/** CS and SS RPL unequal. */
206	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
207	/** SS.Attr.DPL and SS RPL unequal. */
208	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
209	/** SS.Attr.DPL invalid for segment type. */
210	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
211	/** SS.Attr.Type invalid. */
212	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
213	/** SS.Attr.P bit invalid. */
214	#define VMX_IGS_SS_ATTR_P_INVALID 527
215	/** SS.Attr reserved bits not set to 0. */
216	#define VMX_IGS_SS_ATTR_RESERVED 528
217	/** SS.Attr.G bit invalid. */
218	#define VMX_IGS_SS_ATTR_G_INVALID 529
219	/** DS.Attr.A bit invalid. */
220	#define VMX_IGS_DS_ATTR_A_INVALID 530
221	/** DS.Attr.P bit invalid. */
222	#define VMX_IGS_DS_ATTR_P_INVALID 531
223	/** DS.Attr.DPL and DS RPL unequal. */
224	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
225	/** DS.Attr reserved bits not set to 0. */
226	#define VMX_IGS_DS_ATTR_RESERVED 533
227	/** DS.Attr.G bit invalid. */
228	#define VMX_IGS_DS_ATTR_G_INVALID 534
229	/** DS.Attr.Type invalid. */
230	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
231	/** ES.Attr.A bit invalid. */
232	#define VMX_IGS_ES_ATTR_A_INVALID 536
233	/** ES.Attr.P bit invalid. */
234	#define VMX_IGS_ES_ATTR_P_INVALID 537
235	/** ES.Attr.DPL and DS RPL unequal. */
236	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
237	/** ES.Attr reserved bits not set to 0. */
238	#define VMX_IGS_ES_ATTR_RESERVED 539
239	/** ES.Attr.G bit invalid. */
240	#define VMX_IGS_ES_ATTR_G_INVALID 540
241	/** ES.Attr.Type invalid. */
242	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
243	/** FS.Attr.A bit invalid. */
244	#define VMX_IGS_FS_ATTR_A_INVALID 542
245	/** FS.Attr.P bit invalid. */
246	#define VMX_IGS_FS_ATTR_P_INVALID 543
247	/** FS.Attr.DPL and DS RPL unequal. */
248	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
249	/** FS.Attr reserved bits not set to 0. */
250	#define VMX_IGS_FS_ATTR_RESERVED 545
251	/** FS.Attr.G bit invalid. */
252	#define VMX_IGS_FS_ATTR_G_INVALID 546
253	/** FS.Attr.Type invalid. */
254	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
255	/** GS.Attr.A bit invalid. */
256	#define VMX_IGS_GS_ATTR_A_INVALID 548
257	/** GS.Attr.P bit invalid. */
258	#define VMX_IGS_GS_ATTR_P_INVALID 549
259	/** GS.Attr.DPL and DS RPL unequal. */
260	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
261	/** GS.Attr reserved bits not set to 0. */
262	#define VMX_IGS_GS_ATTR_RESERVED 551
263	/** GS.Attr.G bit invalid. */
264	#define VMX_IGS_GS_ATTR_G_INVALID 552
265	/** GS.Attr.Type invalid. */
266	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
267	/** V86 mode CS.Base invalid. */
268	#define VMX_IGS_V86_CS_BASE_INVALID 554
269	/** V86 mode CS.Limit invalid. */
270	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
271	/** V86 mode CS.Attr invalid. */
272	#define VMX_IGS_V86_CS_ATTR_INVALID 556
273	/** V86 mode SS.Base invalid. */
274	#define VMX_IGS_V86_SS_BASE_INVALID 557
275	/** V86 mode SS.Limit invalid. */
276	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
277	/** V86 mode SS.Attr invalid. */
278	#define VMX_IGS_V86_SS_ATTR_INVALID 559
279	/** V86 mode DS.Base invalid. */
280	#define VMX_IGS_V86_DS_BASE_INVALID 560
281	/** V86 mode DS.Limit invalid. */
282	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
283	/** V86 mode DS.Attr invalid. */
284	#define VMX_IGS_V86_DS_ATTR_INVALID 562
285	/** V86 mode ES.Base invalid. */
286	#define VMX_IGS_V86_ES_BASE_INVALID 563
287	/** V86 mode ES.Limit invalid. */
288	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
289	/** V86 mode ES.Attr invalid. */
290	#define VMX_IGS_V86_ES_ATTR_INVALID 565
291	/** V86 mode FS.Base invalid. */
292	#define VMX_IGS_V86_FS_BASE_INVALID 566
293	/** V86 mode FS.Limit invalid. */
294	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
295	/** V86 mode FS.Attr invalid. */
296	#define VMX_IGS_V86_FS_ATTR_INVALID 568
297	/** V86 mode GS.Base invalid. */
298	#define VMX_IGS_V86_GS_BASE_INVALID 569
299	/** V86 mode GS.Limit invalid. */
300	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
301	/** V86 mode GS.Attr invalid. */
302	#define VMX_IGS_V86_GS_ATTR_INVALID 571
303	/** Longmode CS.Base invalid. */
304	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
305	/** Longmode SS.Base invalid. */
306	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
307	/** Longmode DS.Base invalid. */
308	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
309	/** Longmode ES.Base invalid. */
310	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
311	/** SYSENTER ESP is not canonical. */
312	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
313	/** SYSENTER EIP is not canonical. */
314	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
315	/** PAT MSR invalid. */
316	#define VMX_IGS_PAT_MSR_INVALID 578
317	/** PAT MSR reserved bits not set to 0. */
318	#define VMX_IGS_PAT_MSR_RESERVED 579
319	/** GDTR.Base is not canonical. */
320	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
321	/** IDTR.Base is not canonical. */
322	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
323	/** GDTR.Limit invalid. */
324	#define VMX_IGS_GDTR_LIMIT_INVALID 582
325	/** IDTR.Limit invalid. */
326	#define VMX_IGS_IDTR_LIMIT_INVALID 583
327	/** Longmode RIP is invalid. */
328	#define VMX_IGS_LONGMODE_RIP_INVALID 584
329	/** RFLAGS reserved bits not set to 0. */
330	#define VMX_IGS_RFLAGS_RESERVED 585
331	/** RFLAGS RA1 reserved bits not set to 1. */
332	#define VMX_IGS_RFLAGS_RESERVED1 586
333	/** RFLAGS.VM (V86 mode) invalid. */
334	#define VMX_IGS_RFLAGS_VM_INVALID 587
335	/** RFLAGS.IF invalid. */
336	#define VMX_IGS_RFLAGS_IF_INVALID 588
337	/** Activity state invalid. */
338	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
339	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
340	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
341	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
342	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
343	/** Activity state SIPI WAIT invalid. */
344	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
345	/** Interruptibility state reserved bits not set to 0. */
346	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
347	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
348	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
349	/** Interruptibility state block-by-STI invalid for EFLAGS. */
350	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
351	/** Interruptibility state invalid while trying to deliver external
352	* interrupt. */
353	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
354	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
355	* NMI. */
356	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
357	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
358	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
359	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
360	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
361	/** Interruptibility state block-by-STI (maybe) invalid when trying to
362	* deliver an NMI. */
363	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
364	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
365	* active. */
366	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
367	/** Pending debug exceptions reserved bits not set to 0. */
368	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
369	/** Longmode pending debug exceptions reserved bits not set to 0. */
370	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
371	/** Pending debug exceptions.BS bit is not set when it should be. */
372	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
373	/** Pending debug exceptions.BS bit is not clear when it should be. */
374	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
375	/** VMCS link pointer reserved bits not set to 0. */
376	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
377	/** TR cannot index into LDT, TI bit MBZ. */
378	#define VMX_IGS_TR_TI_INVALID 607
379	/** LDTR cannot index into LDT. TI bit MBZ. */
380	#define VMX_IGS_LDTR_TI_INVALID 608
381	/** TR.Base is not canonical. */
382	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
383	/** FS.Base is not canonical. */
384	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
385	/** GS.Base is not canonical. */
386	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
387	/** LDTR.Base is not canonical. */
388	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
389	/** TR is unusable. */
390	#define VMX_IGS_TR_ATTR_UNUSABLE 613
391	/** TR.Attr.S bit invalid. */
392	#define VMX_IGS_TR_ATTR_S_INVALID 614
393	/** TR is not present. */
394	#define VMX_IGS_TR_ATTR_P_INVALID 615
395	/** TR.Attr reserved bits not set to 0. */
396	#define VMX_IGS_TR_ATTR_RESERVED 616
397	/** TR.Attr.G bit invalid. */
398	#define VMX_IGS_TR_ATTR_G_INVALID 617
399	/** Longmode TR.Attr.Type invalid. */
400	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
401	/** TR.Attr.Type invalid. */
402	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
403	/** CS.Attr.S invalid. */
404	#define VMX_IGS_CS_ATTR_S_INVALID 620
405	/** CS.Attr.DPL invalid. */
406	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
407	/** PAE PDPTE reserved bits not set to 0. */
408	#define VMX_IGS_PAE_PDPTE_RESERVED 623
409	/** @} */
410
411	/** @name VMX VMCS-Read cache indices.
412	* @{
413	*/
414	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
415	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
416	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
417	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
418	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
419	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
420	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
421	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
422	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
423	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
424	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
425	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
426	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
427	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
428	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
429	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
430	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
431	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
432	/** @} */
433
434	/** @name VMX EPT paging structures
435	* @{
436	*/
437
438	/**
439	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
440	*/
441	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
442
443	/**
444	* EPT Page Directory Pointer Entry. Bit view.
445	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
446	* this did cause trouble with one compiler/version).
447	*/
448	typedef struct EPTPML4EBITS
449	{
450	/** Present bit. */
451	uint64_t u1Present : 1;
452	/** Writable bit. */
453	uint64_t u1Write : 1;
454	/** Executable bit. */
455	uint64_t u1Execute : 1;
456	/** Reserved (must be 0). */
457	uint64_t u5Reserved : 5;
458	/** Available for software. */
459	uint64_t u4Available : 4;
460	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
461	uint64_t u40PhysAddr : 40;
462	/** Available for software. */
463	uint64_t u12Available : 12;
464	} EPTPML4EBITS;
465	AssertCompileSize(EPTPML4EBITS, 8);
466
467	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
468	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
469	/** The page shift to get the PML4 index. */
470	#define EPT_PML4_SHIFT X86_PML4_SHIFT
471	/** The PML4 index mask (apply to a shifted page address). */
472	#define EPT_PML4_MASK X86_PML4_MASK
473
474	/**
475	* EPT PML4E.
476	*/
477	typedef union EPTPML4E
478	{
479	/** Normal view. */
480	EPTPML4EBITS n;
481	/** Unsigned integer view. */
482	X86PGPAEUINT u;
483	/** 64 bit unsigned integer view. */
484	uint64_t au64[1];
485	/** 32 bit unsigned integer view. */
486	uint32_t au32[2];
487	} EPTPML4E;
488	AssertCompileSize(EPTPML4E, 8);
489	/** Pointer to a PML4 table entry. */
490	typedef EPTPML4E *PEPTPML4E;
491	/** Pointer to a const PML4 table entry. */
492	typedef const EPTPML4E *PCEPTPML4E;
493
494	/**
495	* EPT PML4 Table.
496	*/
497	typedef struct EPTPML4
498	{
499	EPTPML4E a[EPT_PG_ENTRIES];
500	} EPTPML4;
501	AssertCompileSize(EPTPML4, 0x1000);
502	/** Pointer to an EPT PML4 Table. */
503	typedef EPTPML4 *PEPTPML4;
504	/** Pointer to a const EPT PML4 Table. */
505	typedef const EPTPML4 *PCEPTPML4;
506
507	/**
508	* EPT Page Directory Pointer Entry. Bit view.
509	*/
510	typedef struct EPTPDPTEBITS
511	{
512	/** Present bit. */
513	uint64_t u1Present : 1;
514	/** Writable bit. */
515	uint64_t u1Write : 1;
516	/** Executable bit. */
517	uint64_t u1Execute : 1;
518	/** Reserved (must be 0). */
519	uint64_t u5Reserved : 5;
520	/** Available for software. */
521	uint64_t u4Available : 4;
522	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
523	uint64_t u40PhysAddr : 40;
524	/** Available for software. */
525	uint64_t u12Available : 12;
526	} EPTPDPTEBITS;
527	AssertCompileSize(EPTPDPTEBITS, 8);
528
529	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
530	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
531	/** The page shift to get the PDPT index. */
532	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
533	/** The PDPT index mask (apply to a shifted page address). */
534	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
535
536	/**
537	* EPT Page Directory Pointer.
538	*/
539	typedef union EPTPDPTE
540	{
541	/** Normal view. */
542	EPTPDPTEBITS n;
543	/** Unsigned integer view. */
544	X86PGPAEUINT u;
545	/** 64 bit unsigned integer view. */
546	uint64_t au64[1];
547	/** 32 bit unsigned integer view. */
548	uint32_t au32[2];
549	} EPTPDPTE;
550	AssertCompileSize(EPTPDPTE, 8);
551	/** Pointer to an EPT Page Directory Pointer Entry. */
552	typedef EPTPDPTE *PEPTPDPTE;
553	/** Pointer to a const EPT Page Directory Pointer Entry. */
554	typedef const EPTPDPTE *PCEPTPDPTE;
555
556	/**
557	* EPT Page Directory Pointer Table.
558	*/
559	typedef struct EPTPDPT
560	{
561	EPTPDPTE a[EPT_PG_ENTRIES];
562	} EPTPDPT;
563	AssertCompileSize(EPTPDPT, 0x1000);
564	/** Pointer to an EPT Page Directory Pointer Table. */
565	typedef EPTPDPT *PEPTPDPT;
566	/** Pointer to a const EPT Page Directory Pointer Table. */
567	typedef const EPTPDPT *PCEPTPDPT;
568
569	/**
570	* EPT Page Directory Table Entry. Bit view.
571	*/
572	typedef struct EPTPDEBITS
573	{
574	/** Present bit. */
575	uint64_t u1Present : 1;
576	/** Writable bit. */
577	uint64_t u1Write : 1;
578	/** Executable bit. */
579	uint64_t u1Execute : 1;
580	/** Reserved (must be 0). */
581	uint64_t u4Reserved : 4;
582	/** Big page (must be 0 here). */
583	uint64_t u1Size : 1;
584	/** Available for software. */
585	uint64_t u4Available : 4;
586	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
587	uint64_t u40PhysAddr : 40;
588	/** Available for software. */
589	uint64_t u12Available : 12;
590	} EPTPDEBITS;
591	AssertCompileSize(EPTPDEBITS, 8);
592
593	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
594	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
595	/** The page shift to get the PD index. */
596	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
597	/** The PD index mask (apply to a shifted page address). */
598	#define EPT_PD_MASK X86_PD_PAE_MASK
599
600	/**
601	* EPT 2MB Page Directory Table Entry. Bit view.
602	*/
603	typedef struct EPTPDE2MBITS
604	{
605	/** Present bit. */
606	uint64_t u1Present : 1;
607	/** Writable bit. */
608	uint64_t u1Write : 1;
609	/** Executable bit. */
610	uint64_t u1Execute : 1;
611	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
612	uint64_t u3EMT : 3;
613	/** Ignore PAT memory type */
614	uint64_t u1IgnorePAT : 1;
615	/** Big page (must be 1 here). */
616	uint64_t u1Size : 1;
617	/** Available for software. */
618	uint64_t u4Available : 4;
619	/** Reserved (must be 0). */
620	uint64_t u9Reserved : 9;
621	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
622	uint64_t u31PhysAddr : 31;
623	/** Available for software. */
624	uint64_t u12Available : 12;
625	} EPTPDE2MBITS;
626	AssertCompileSize(EPTPDE2MBITS, 8);
627
628	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
629	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
630
631	/**
632	* EPT Page Directory Table Entry.
633	*/
634	typedef union EPTPDE
635	{
636	/** Normal view. */
637	EPTPDEBITS n;
638	/** 2MB view (big). */
639	EPTPDE2MBITS b;
640	/** Unsigned integer view. */
641	X86PGPAEUINT u;
642	/** 64 bit unsigned integer view. */
643	uint64_t au64[1];
644	/** 32 bit unsigned integer view. */
645	uint32_t au32[2];
646	} EPTPDE;
647	AssertCompileSize(EPTPDE, 8);
648	/** Pointer to an EPT Page Directory Table Entry. */
649	typedef EPTPDE *PEPTPDE;
650	/** Pointer to a const EPT Page Directory Table Entry. */
651	typedef const EPTPDE *PCEPTPDE;
652
653	/**
654	* EPT Page Directory Table.
655	*/
656	typedef struct EPTPD
657	{
658	EPTPDE a[EPT_PG_ENTRIES];
659	} EPTPD;
660	AssertCompileSize(EPTPD, 0x1000);
661	/** Pointer to an EPT Page Directory Table. */
662	typedef EPTPD *PEPTPD;
663	/** Pointer to a const EPT Page Directory Table. */
664	typedef const EPTPD *PCEPTPD;
665
666	/**
667	* EPT Page Table Entry. Bit view.
668	*/
669	typedef struct EPTPTEBITS
670	{
671	/** 0 - Present bit.
672	* @remarks This is a convenience "misnomer". The bit actually indicates read access
673	* and the CPU will consider an entry with any of the first three bits set
674	* as present. Since all our valid entries will have this bit set, it can
675	* be used as a present indicator and allow some code sharing. */
676	uint64_t u1Present : 1;
677	/** 1 - Writable bit. */
678	uint64_t u1Write : 1;
679	/** 2 - Executable bit. */
680	uint64_t u1Execute : 1;
681	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
682	uint64_t u3EMT : 3;
683	/** 6 - Ignore PAT memory type */
684	uint64_t u1IgnorePAT : 1;
685	/** 11:7 - Available for software. */
686	uint64_t u5Available : 5;
687	/** 51:12 - Physical address of page. Restricted by maximum physical
688	* address width of the cpu. */
689	uint64_t u40PhysAddr : 40;
690	/** 63:52 - Available for software. */
691	uint64_t u12Available : 12;
692	} EPTPTEBITS;
693	AssertCompileSize(EPTPTEBITS, 8);
694
695	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
696	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
697	/** The page shift to get the EPT PTE index. */
698	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
699	/** The EPT PT index mask (apply to a shifted page address). */
700	#define EPT_PT_MASK X86_PT_PAE_MASK
701
702	/**
703	* EPT Page Table Entry.
704	*/
705	typedef union EPTPTE
706	{
707	/** Normal view. */
708	EPTPTEBITS n;
709	/** Unsigned integer view. */
710	X86PGPAEUINT u;
711	/** 64 bit unsigned integer view. */
712	uint64_t au64[1];
713	/** 32 bit unsigned integer view. */
714	uint32_t au32[2];
715	} EPTPTE;
716	AssertCompileSize(EPTPTE, 8);
717	/** Pointer to an EPT Page Directory Table Entry. */
718	typedef EPTPTE *PEPTPTE;
719	/** Pointer to a const EPT Page Directory Table Entry. */
720	typedef const EPTPTE *PCEPTPTE;
721
722	/**
723	* EPT Page Table.
724	*/
725	typedef struct EPTPT
726	{
727	EPTPTE a[EPT_PG_ENTRIES];
728	} EPTPT;
729	AssertCompileSize(EPTPT, 0x1000);
730	/** Pointer to an extended page table. */
731	typedef EPTPT *PEPTPT;
732	/** Pointer to a const extended table. */
733	typedef const EPTPT *PCEPTPT;
734
735	/** @} */
736
737	/**
738	* VMX VPID flush types.
739	* @note Valid enum members are in accordance to the VT-x spec.
740	*/
741	typedef enum
742	{
743	/** Invalidate a specific page. */
744	VMXFLUSHVPID_INDIV_ADDR = 0,
745	/** Invalidate one context (specific VPID). */
746	VMXFLUSHVPID_SINGLE_CONTEXT = 1,
747	/** Invalidate all contexts (all VPIDs). */
748	VMXFLUSHVPID_ALL_CONTEXTS = 2,
749	/** Invalidate a single VPID context retaining global mappings. */
750	VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
751	/** Unsupported by VirtualBox. */
752	VMXFLUSHVPID_NOT_SUPPORTED = 0xbad0,
753	/** Unsupported by CPU. */
754	VMXFLUSHVPID_NONE = 0xbad1
755	} VMXFLUSHVPID;
756	AssertCompileSize(VMXFLUSHVPID, 4);
757
758	/**
759	* VMX EPT flush types.
760	* @note Valid enums values are in accordance to the VT-x spec.
761	*/
762	typedef enum
763	{
764	/** Invalidate one context (specific EPT). */
765	VMXFLUSHEPT_SINGLE_CONTEXT = 1,
766	/* Invalidate all contexts (all EPTs) */
767	VMXFLUSHEPT_ALL_CONTEXTS = 2,
768	/** Unsupported by VirtualBox. */
769	VMXFLUSHEPT_NOT_SUPPORTED = 0xbad0,
770	/** Unsupported by CPU. */
771	VMXFLUSHEPT_NONE = 0xbad1
772	} VMXFLUSHEPT;
773	AssertCompileSize(VMXFLUSHEPT, 4);
774
775	/**
776	* VMX Posted Interrupt Descriptor.
777	* In accordance to the VT-x spec.
778	*/
779	typedef struct VMXPOSTEDINTRDESC
780	{
781	uint32_t aVectorBitmap[8];
782	uint32_t fOutstandingNotification : 1;
783	uint32_t uReserved0 : 31;
784	uint8_t au8Reserved0[28];
785	} VMXPOSTEDINTRDESC;
786	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
787	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
788	/** Pointer to a posted interrupt descriptor. */
789	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
790	/** Pointer to a const posted interrupt descriptor. */
791	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
792
793	/**
794	* VMX MSR autoload/store element.
795	* In accordance to the VT-x spec.
796	*/
797	typedef struct VMXAUTOMSR
798	{
799	/** The MSR Id. */
800	uint32_t u32Msr;
801	/** Reserved (MBZ). */
802	uint32_t u32Reserved;
803	/** The MSR value. */
804	uint64_t u64Value;
805	} VMXAUTOMSR;
806	AssertCompileSize(VMXAUTOMSR, 16);
807	/** Pointer to an MSR load/store element. */
808	typedef VMXAUTOMSR *PVMXAUTOMSR;
809	/** Pointer to a const MSR load/store element. */
810	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
811
812	/**
813	* VMX-capability qword.
814	*/
815	typedef union
816	{
817	struct
818	{
819	/** Bits set here -must- be set in the corresponding VM-execution controls. */
820	uint32_t disallowed0;
821	/** Bits cleared here -must- be cleared in the corresponding VM-execution
822	* controls. */
823	uint32_t allowed1;
824	} n;
825	uint64_t u;
826	} VMXCAPABILITY;
827	AssertCompileSize(VMXCAPABILITY, 8);
828
829	/**
830	* VMX MSRs.
831	*/
832	typedef struct VMXMSRS
833	{
834	uint64_t u64FeatureCtrl;
835	uint64_t u64BasicInfo;
836	VMXCAPABILITY VmxPinCtls;
837	VMXCAPABILITY VmxProcCtls;
838	VMXCAPABILITY VmxProcCtls2;
839	VMXCAPABILITY VmxExit;
840	VMXCAPABILITY VmxEntry;
841	uint64_t u64Misc;
842	uint64_t u64Cr0Fixed0;
843	uint64_t u64Cr0Fixed1;
844	uint64_t u64Cr4Fixed0;
845	uint64_t u64Cr4Fixed1;
846	uint64_t u64VmcsEnum;
847	uint64_t u64Vmfunc;
848	uint64_t u64EptVpidCaps;
849	} VMXMSRS;
850	AssertCompileSizeAlignment(VMXMSRS, 8);
851	/** Pointer to a VMXMSRS struct. */
852	typedef VMXMSRS *PVMXMSRS;
853
854	/** @name VMX Basic Exit Reasons.
855	* @{
856	*/
857	/** -1 Invalid exit code */
858	#define VMX_EXIT_INVALID -1
859	/** 0 Exception or non-maskable interrupt (NMI). */
860	#define VMX_EXIT_XCPT_OR_NMI 0
861	/** 1 External interrupt. */
862	#define VMX_EXIT_EXT_INT 1
863	/** 2 Triple fault. */
864	#define VMX_EXIT_TRIPLE_FAULT 2
865	/** 3 INIT signal. */
866	#define VMX_EXIT_INIT_SIGNAL 3
867	/** 4 Start-up IPI (SIPI). */
868	#define VMX_EXIT_SIPI 4
869	/** 5 I/O system-management interrupt (SMI). */
870	#define VMX_EXIT_IO_SMI 5
871	/** 6 Other SMI. */
872	#define VMX_EXIT_SMI 6
873	/** 7 Interrupt window exiting. */
874	#define VMX_EXIT_INT_WINDOW 7
875	/** 8 NMI window exiting. */
876	#define VMX_EXIT_NMI_WINDOW 8
877	/** 9 Task switch. */
878	#define VMX_EXIT_TASK_SWITCH 9
879	/** 10 Guest software attempted to execute CPUID. */
880	#define VMX_EXIT_CPUID 10
881	/** 11 Guest software attempted to execute GETSEC. */
882	#define VMX_EXIT_GETSEC 11
883	/** 12 Guest software attempted to execute HLT. */
884	#define VMX_EXIT_HLT 12
885	/** 13 Guest software attempted to execute INVD. */
886	#define VMX_EXIT_INVD 13
887	/** 14 Guest software attempted to execute INVLPG. */
888	#define VMX_EXIT_INVLPG 14
889	/** 15 Guest software attempted to execute RDPMC. */
890	#define VMX_EXIT_RDPMC 15
891	/** 16 Guest software attempted to execute RDTSC. */
892	#define VMX_EXIT_RDTSC 16
893	/** 17 Guest software attempted to execute RSM in SMM. */
894	#define VMX_EXIT_RSM 17
895	/** 18 Guest software executed VMCALL. */
896	#define VMX_EXIT_VMCALL 18
897	/** 19 Guest software executed VMCLEAR. */
898	#define VMX_EXIT_VMCLEAR 19
899	/** 20 Guest software executed VMLAUNCH. */
900	#define VMX_EXIT_VMLAUNCH 20
901	/** 21 Guest software executed VMPTRLD. */
902	#define VMX_EXIT_VMPTRLD 21
903	/** 22 Guest software executed VMPTRST. */
904	#define VMX_EXIT_VMPTRST 22
905	/** 23 Guest software executed VMREAD. */
906	#define VMX_EXIT_VMREAD 23
907	/** 24 Guest software executed VMRESUME. */
908	#define VMX_EXIT_VMRESUME 24
909	/** 25 Guest software executed VMWRITE. */
910	#define VMX_EXIT_VMWRITE 25
911	/** 26 Guest software executed VMXOFF. */
912	#define VMX_EXIT_VMXOFF 26
913	/** 27 Guest software executed VMXON. */
914	#define VMX_EXIT_VMXON 27
915	/** 28 Control-register accesses. */
916	#define VMX_EXIT_MOV_CRX 28
917	/** 29 Debug-register accesses. */
918	#define VMX_EXIT_MOV_DRX 29
919	/** 30 I/O instruction. */
920	#define VMX_EXIT_IO_INSTR 30
921	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
922	#define VMX_EXIT_RDMSR 31
923	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
924	#define VMX_EXIT_WRMSR 32
925	/** 33 VM-entry failure due to invalid guest state. */
926	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
927	/** 34 VM-entry failure due to MSR loading. */
928	#define VMX_EXIT_ERR_MSR_LOAD 34
929	/** 36 Guest software executed MWAIT. */
930	#define VMX_EXIT_MWAIT 36
931	/** 37 VM-exit due to monitor trap flag. */
932	#define VMX_EXIT_MTF 37
933	/** 39 Guest software attempted to execute MONITOR. */
934	#define VMX_EXIT_MONITOR 39
935	/** 40 Guest software attempted to execute PAUSE. */
936	#define VMX_EXIT_PAUSE 40
937	/** 41 VM-entry failure due to machine-check. */
938	#define VMX_EXIT_ERR_MACHINE_CHECK 41
939	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
940	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
941	/** 44 APIC access. Guest software attempted to access memory at a physical
942	* address on the APIC-access page. */
943	#define VMX_EXIT_APIC_ACCESS 44
944	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
945	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
946	#define VMX_EXIT_VIRTUALIZED_EOI 45
947	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
948	* SGDT, or SIDT. */
949	#define VMX_EXIT_XDTR_ACCESS 46
950	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
951	* SLDT, or STR. */
952	#define VMX_EXIT_TR_ACCESS 47
953	/** 48 EPT violation. An attempt to access memory with a guest-physical address
954	* was disallowed by the configuration of the EPT paging structures. */
955	#define VMX_EXIT_EPT_VIOLATION 48
956	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
957	* address encountered a misconfigured EPT paging-structure entry. */
958	#define VMX_EXIT_EPT_MISCONFIG 49
959	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
960	#define VMX_EXIT_INVEPT 50
961	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
962	#define VMX_EXIT_RDTSCP 51
963	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
964	#define VMX_EXIT_PREEMPT_TIMER 52
965	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
966	#define VMX_EXIT_INVVPID 53
967	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
968	#define VMX_EXIT_WBINVD 54
969	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
970	#define VMX_EXIT_XSETBV 55
971	/** 56 APIC write. Guest completed write to virtual-APIC. */
972	#define VMX_EXIT_APIC_WRITE 56
973	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
974	#define VMX_EXIT_RDRAND 57
975	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
976	#define VMX_EXIT_INVPCID 58
977	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
978	#define VMX_EXIT_VMFUNC 59
979	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
980	#define VMX_EXIT_ENCLS 60
981	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
982	* enabled. */
983	#define VMX_EXIT_RDSEED 61
984	/** 62 - Page-modification log full. */
985	#define VMX_EXIT_PML_FULL 62
986	/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
987	* enabled (XSAVES/XRSTORS was enabled too, of course). */
988	#define VMX_EXIT_XSAVES 63
989	/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
990	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
991	#define VMX_EXIT_XRSTORS 64
992	/** The maximum exit value (inclusive). */
993	#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
994	/** @} */
995
996
997	/** @name VM Instruction Errors
998	* @{
999	*/
1000	/** VMCALL executed in VMX root operation. */
1001	#define VMX_ERROR_VMCALL 1
1002	/** VMCLEAR with invalid physical address. */
1003	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1004	/** VMCLEAR with VMXON pointer. */
1005	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1006	/** VMLAUNCH with non-clear VMCS. */
1007	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1008	/** VMRESUME with non-launched VMCS. */
1009	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1010	/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1011	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1012	/** VM-entry with invalid control field(s). */
1013	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1014	/** VM-entry with invalid host-state field(s). */
1015	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1016	/** VMPTRLD with invalid physical address. */
1017	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1018	/** VMPTRLD with VMXON pointer. */
1019	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1020	/** VMPTRLD with incorrect VMCS revision identifier. */
1021	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1022	/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1023	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1024	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1025	/** VMWRITE to read-only VMCS component. */
1026	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1027	/** VMXON executed in VMX root operation. */
1028	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1029	/** VM-entry with invalid executive-VMCS pointer. */
1030	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1031	/** VM-entry with non-launched executive VMCS. */
1032	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1033	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1034	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1035	/** VMCALL with non-clear VMCS. */
1036	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1037	/** VMCALL with invalid VM-exit control fields. */
1038	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1039	/** VMCALL with incorrect MSEG revision identifier. */
1040	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1041	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1042	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1043	/** VMCALL with invalid SMM-monitor features. */
1044	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1045	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1046	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1047	/** VM-entry with events blocked by MOV SS. */
1048	#define VMX_ERROR_VMENTRY_MOV_SS 26
1049	/** Invalid operand to INVEPT/INVVPID. */
1050	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1051	/** @} */
1052
1053
1054	/** @name VMX MSRs - Basic VMX information.
1055	* @{
1056	*/
1057	/** VMCS revision identifier used by the processor. */
1058	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) ((a) & 0x7FFFFFFF)
1059	/** Size of the VMCS. */
1060	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0x1FFF)
1061	/** Width of physical address used for the VMCS.
1062	* 0 -> limited to the available amount of physical ram
1063	* 1 -> within the first 4 GB
1064	*/
1065	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1066	/** Whether the processor supports the dual-monitor treatment of
1067	* system-management interrupts and system-management code. (always 1) */
1068	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1069	/** Memory type that must be used for the VMCS. */
1070	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1071	/** Whether the processor provides additional information for exits due to
1072	* INS/OUTS. */
1073	#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) ((a) & RT_BIT_64(54))
1074	/** Whether default 1 bits in control MSRs (pin/proc/exit/entry) may be
1075	* cleared to 0 and that 'true' control MSRs are supported. */
1076	#define MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(a) ((a) & RT_BIT_64(55))
1077	/** @} */
1078
1079
1080	/** @name VMX MSRs - Misc VMX info.
1081	* @{
1082	*/
1083	/** Relationship between the preemption timer and tsc; count down every time bit
1084	* x of the tsc changes. */
1085	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1086	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1087	#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1088	/** Activity states supported by the implementation. */
1089	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1090	/** Number of CR3 target values supported by the processor. (0-256) */
1091	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1092	/** Maximum number of MSRs in the VMCS. (N+1)512. /
1093	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1094	/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1095	#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1096	/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1097	#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1098	/** Whether VMWRITE can be used to write VM-exit information fields. */
1099	#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1100	/** MSEG revision identifier used by the processor. */
1101	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1102	/** @} */
1103
1104
1105	/** @name VMX MSRs - VMCS enumeration field info
1106	* @{
1107	*/
1108	/** Highest field index. */
1109	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1110	/** @} */
1111
1112
1113	/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1114	* @{
1115	*/
1116	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1117	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1118	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1119	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1120	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1121	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1122	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1123	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1124	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1125	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1126	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1127	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1128	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1129	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1130	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1131	/** @} */
1132
1133	/** @name Extended Page Table Pointer (EPTP)
1134	* @{
1135	*/
1136	/** Uncachable EPT paging structure memory type. */
1137	#define VMX_EPT_MEMTYPE_UC 0
1138	/** Write-back EPT paging structure memory type. */
1139	#define VMX_EPT_MEMTYPE_WB 6
1140	/** Shift value to get the EPT page walk length (bits 5-3) */
1141	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1142	/** Mask value to get the EPT page walk length (bits 5-3) */
1143	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1144	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1145	* length) */
1146	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1147	/** @} */
1148
1149
1150	/** @name VMCS field encoding: 16-bit guest fields.
1151	* @{
1152	*/
1153	#define VMX_VMCS16_VPID 0x000
1154	#define VMX_VMCS16_POSTED_INTR_NOTIFY_VECTOR 0x002
1155	#define VMX_VMCS16_EPTP_INDEX 0x004
1156	#define VMX_VMCS16_GUEST_ES_SEL 0x800
1157	#define VMX_VMCS16_GUEST_CS_SEL 0x802
1158	#define VMX_VMCS16_GUEST_SS_SEL 0x804
1159	#define VMX_VMCS16_GUEST_DS_SEL 0x806
1160	#define VMX_VMCS16_GUEST_FS_SEL 0x808
1161	#define VMX_VMCS16_GUEST_GS_SEL 0x80A
1162	#define VMX_VMCS16_GUEST_LDTR_SEL 0x80C
1163	#define VMX_VMCS16_GUEST_TR_SEL 0x80E
1164	#define VMX_VMCS16_GUEST_INTR_STATUS 0x810
1165	/** @} */
1166
1167	/** @name VMCS field encoding: 16-bits host fields.
1168	* @{
1169	*/
1170	#define VMX_VMCS16_HOST_ES_SEL 0xC00
1171	#define VMX_VMCS16_HOST_CS_SEL 0xC02
1172	#define VMX_VMCS16_HOST_SS_SEL 0xC04
1173	#define VMX_VMCS16_HOST_DS_SEL 0xC06
1174	#define VMX_VMCS16_HOST_FS_SEL 0xC08
1175	#define VMX_VMCS16_HOST_GS_SEL 0xC0A
1176	#define VMX_VMCS16_HOST_TR_SEL 0xC0C
1177	/** @} */
1178
1179	/** @name VMCS field encoding: 64-bit host fields.
1180	* @{
1181	*/
1182	#define VMX_VMCS64_HOST_PAT_FULL 0x2C00
1183	#define VMX_VMCS64_HOST_PAT_HIGH 0x2C01
1184	#define VMX_VMCS64_HOST_EFER_FULL 0x2C02
1185	#define VMX_VMCS64_HOST_EFER_HIGH 0x2C03
1186	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
1187	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
1188	/** @} */
1189
1190
1191	/** @name VMCS field encoding: 64-bit control fields.
1192	* @{
1193	*/
1194	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1195	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1196	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1197	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1198	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1199	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1200	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1201	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1202	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1203	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1204	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1205	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1206	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1207	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1208	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1209	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1210	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1211	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1212	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1213	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1214	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1215	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1216	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1217	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1218	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201A
1219	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201B
1220	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201C
1221	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201D
1222	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201E
1223	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201F
1224	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1225	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1226	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1227	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1228	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1229	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1230	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1231	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1232	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1233	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1234	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202A
1235	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202B
1236	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202C
1237	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202D
1238	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1239	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1240	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1241	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1242	/** @} */
1243
1244
1245	/** @name VMCS field encoding: 64-bit guest fields.
1246	* @{
1247	*/
1248	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1249	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1250	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
1251	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
1252	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1253	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1254	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1255	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1256	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
1257	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
1258	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1259	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1260	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1261	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1262	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1263	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1264	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1265	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1266	/** @} */
1267
1268
1269	/** @name VMCS field encoding: 32-bit control fields.
1270	* @{
1271	*/
1272	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1273	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1274	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1275	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1276	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1277	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1278	#define VMX_VMCS32_CTRL_EXIT 0x400C
1279	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1280	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1281	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1282	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1283	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1284	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1285	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1286	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1287	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1288	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1289	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1290	/** @} */
1291
1292
1293	/** @name VMX_VMCS_CTRL_PIN_EXEC
1294	* @{
1295	*/
1296	/** External interrupts cause VM-exits if set; otherwise dispatched through the
1297	* guest's IDT. */
1298	#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1299	/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through
1300	* the guest's IDT. */
1301	#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1302	/** Virtual NMIs. */
1303	#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1304	/** Activate VMX preemption timer. */
1305	#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1306	/** Process interrupts with the posted-interrupt notification vector. */
1307	#define VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR RT_BIT(7)
1308	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1309	/** @} */
1310
1311
1312	/** @name VMX_VMCS_CTRL_PROC_EXEC
1313	* @{
1314	*/
1315	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1316	#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1317	/** Use timestamp counter offset. */
1318	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1319	/** VM-exit when executing the HLT instruction. */
1320	#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1321	/** VM-exit when executing the INVLPG instruction. */
1322	#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1323	/** VM-exit when executing the MWAIT instruction. */
1324	#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1325	/** VM-exit when executing the RDPMC instruction. */
1326	#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1327	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1328	#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1329	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
1330	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1331	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1332	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
1333	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1334	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1335	/** VM-exit on CR8 loads. */
1336	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1337	/** VM-exit on CR8 stores. */
1338	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1339	/** Use TPR shadow. */
1340	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1341	/** VM-exit when virtual NMI blocking is disabled. */
1342	#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1343	/** VM-exit when executing a MOV DRx instruction. */
1344	#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1345	/** VM-exit when executing IO instructions. */
1346	#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1347	/** Use IO bitmaps. */
1348	#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1349	/** Monitor trap flag. */
1350	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1351	/** Use MSR bitmaps. */
1352	#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1353	/** VM-exit when executing the MONITOR instruction. */
1354	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1355	/** VM-exit when executing the PAUSE instruction. */
1356	#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1357	/** Whether the secondary processor based VM-execution controls are used. */
1358	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1359	/** @} */
1360
1361
1362	/** @name VMX_VMCS_CTRL_PROC_EXEC2
1363	* @{
1364	*/
1365	/** Virtualize APIC access. */
1366	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1367	/** EPT supported/enabled. */
1368	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1369	/** Descriptor table instructions cause VM-exits. */
1370	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1371	/** RDTSCP supported/enabled. */
1372	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1373	/** Virtualize x2APIC mode. */
1374	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1375	/** VPID supported/enabled. */
1376	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1377	/** VM-exit when executing the WBINVD instruction. */
1378	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1379	/** Unrestricted guest execution. */
1380	#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1381	/** APIC register virtualization. */
1382	#define VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT RT_BIT(8)
1383	/** Virtual-interrupt delivery. */
1384	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY RT_BIT(9)
1385	/** A specified number of pause loops cause a VM-exit. */
1386	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1387	/** VM-exit when executing RDRAND instructions. */
1388	#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1389	/** Enables INVPCID instructions. */
1390	#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1391	/** Enables VMFUNC instructions. */
1392	#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1393	/** Enables VMCS shadowing. */
1394	#define VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING RT_BIT(14)
1395	/** Enables ENCLS VM-exits. */
1396	#define VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT RT_BIT(15)
1397	/** VM-exit when executing RDSEED. */
1398	#define VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT RT_BIT(16)
1399	/** Enables page-modification logging. */
1400	#define VMX_VMCS_CTRL_PROC_EXEC2_PML RT_BIT(17)
1401	/** Controls whether EPT-violations may cause \#VE instead of exits. */
1402	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE RT_BIT(18)
1403	/** Conceal VMX non-root operation from Intel processor trace (PT). */
1404	#define VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT RT_BIT(19)
1405	/** Enables XSAVES/XRSTORS instructions. */
1406	#define VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS RT_BIT(20)
1407	/** Use TSC scaling. */
1408	#define VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING RT_BIT(25)
1409	/** @} */
1410
1411
1412	/** @name VMX_VMCS_CTRL_ENTRY
1413	* @{
1414	*/
1415	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
1416	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1417	#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1418	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1419	#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1420	/** In SMM mode after VM-entry. */
1421	#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1422	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1423	#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1424	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
1425	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1426	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
1427	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1428	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
1429	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1430	/** @} */
1431
1432
1433	/** @name VMX_VMCS_CTRL_EXIT
1434	* @{
1435	*/
1436	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
1437	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1438	#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1439	/** Return to long mode after a VM-exit. */
1440	#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1441	/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
1442	#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1443	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1444	#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1445	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
1446	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1447	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
1448	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1449	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
1450	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1451	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
1452	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1453	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
1454	#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1455	/** @} */
1456
1457
1458	/** @name VMX_VMCS_CTRL_VMFUNC
1459	* @{
1460	*/
1461	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1462	#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1463	/** @} */
1464
1465
1466	/** @name VMCS field encoding: 32-bits read-only fields.
1467	* @{
1468	*/
1469	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1470	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1471	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1472	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1473	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1474	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440A
1475	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1476	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1477	/** @} */
1478
1479
1480	/** @name VMX_VMCS32_RO_EXIT_REASON
1481	* @{
1482	*/
1483	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
1484	/** @} */
1485
1486
1487	/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1488	* @{
1489	*/
1490	#define VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1491	#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1492	#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1493	/** @} */
1494
1495
1496	/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1497	* @{
1498	*/
1499	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) ((a) & 0xff)
1500	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1501	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1502	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1503	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1504	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(a) ((a) & RT_BIT(12))
1505	#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1506	#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1507	/** Construct an irq event injection value from the exit interruption info value
1508	* (same except that bit 12 is reserved). */
1509	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
1510	/** @} */
1511
1512
1513	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1514	* @{
1515	*/
1516	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1517	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1518	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1519	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4
1520	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT 5
1521	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1522	/** @} */
1523
1524
1525	/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1526	* @{
1527	*/
1528	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
1529	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1530	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1531	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1532	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1533	#define VMX_IDT_VECTORING_INFO_VALID(a) ((a) & RT_BIT(31))
1534	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
1535	/** @} */
1536
1537
1538	/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1539	* @{
1540	*/
1541	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1542	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1543	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1544	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1545	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1546	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1547	/** @} */
1548
1549
1550	/** @name VMCS field encoding: 32-bit guest-state fields.
1551	* @{
1552	*/
1553	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1554	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1555	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1556	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1557	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1558	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1559	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1560	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1561	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1562	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1563	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1564	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1565	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1566	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1567	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1568	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1569	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1570	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1571	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1572	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1573	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
1574	#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1575	/** @} */
1576
1577
1578	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1579	* @{
1580	*/
1581	/** The logical processor is active. */
1582	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1583	/** The logical processor is inactive, because executed a HLT instruction. */
1584	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1585	/** The logical processor is inactive, because of a triple fault or other serious error. */
1586	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1587	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1588	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1589	/** @} */
1590
1591
1592	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1593	* @{
1594	*/
1595	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1596	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1597	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1598	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1599	/** @} */
1600
1601
1602	/** @name VMCS field encoding: 32-bit host-state fields.
1603	* @{
1604	*/
1605	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1606	/** @} */
1607
1608
1609	/** @name Natural width control fields
1610	* @{
1611	*/
1612	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1613	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1614	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1615	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1616	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1617	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1618	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1619	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1620	/** @} */
1621
1622
1623	/** @name Natural width read-only data fields
1624	* @{
1625	*/
1626	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1627	#define VMX_VMCS_RO_IO_RCX 0x6402
1628	#define VMX_VMCS_RO_IO_RSX 0x6404
1629	#define VMX_VMCS_RO_IO_RDI 0x6406
1630	#define VMX_VMCS_RO_IO_RIP 0x6408
1631	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1632	/** @} */
1633
1634
1635	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1636	* @{
1637	*/
1638	/** 0-2: Debug register number */
1639	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
1640	/** 3: Reserved; cleared to 0. */
1641	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
1642	/** 4: Direction of move (0 = write, 1 = read) */
1643	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
1644	/** 5-7: Reserved; cleared to 0. */
1645	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
1646	/** 8-11: General purpose register number. */
1647	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xF)
1648	/** Rest: reserved. */
1649	/** @} */
1650
1651
1652	/** @name VMX_EXIT_QUAL_DRX_DIRECTION values
1653	* @{
1654	*/
1655	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
1656	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
1657	/** @} */
1658
1659
1660	/** @name CRx accesses
1661	* @{
1662	*/
1663	/** 0-3: Control register number (0 for CLTS & LMSW) */
1664	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xF)
1665	/** 4-5: Access type. */
1666	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
1667	/** 6: LMSW operand type */
1668	#define VMX_EXIT_QUAL_CRX_LMSW_OP(a) (((a) >> 6) & 1)
1669	/** 7: Reserved; cleared to 0. */
1670	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
1671	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1672	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xF)
1673	/** 12-15: Reserved; cleared to 0. */
1674	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xF)
1675	/** 16-31: LMSW source data (else 0). */
1676	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xFFFF)
1677	/* Rest: reserved. */
1678	/** @} */
1679
1680
1681	/** @name VMX_EXIT_QUAL_CRX_ACCESS
1682	* @{
1683	*/
1684	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
1685	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
1686	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
1687	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
1688	/** @} */
1689
1690
1691	/** @name VMX_EXIT_QUAL_TASK_SWITCH
1692	* @{
1693	*/
1694	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
1695	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
1696	/** Task switch caused by a call instruction. */
1697	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
1698	/** Task switch caused by an iret instruction. */
1699	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
1700	/** Task switch caused by a jmp instruction. */
1701	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
1702	/** Task switch caused by an interrupt gate. */
1703	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
1704	/** @} */
1705
1706
1707	/** @name VMX_EXIT_EPT_VIOLATION
1708	* @{
1709	*/
1710	/** Set if the violation was caused by a data read. */
1711	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
1712	/** Set if the violation was caused by a data write. */
1713	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
1714	/** Set if the violation was caused by an instruction fetch. */
1715	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
1716	/** AND of the present bit of all EPT structures. */
1717	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
1718	/** AND of the write bit of all EPT structures. */
1719	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
1720	/** AND of the execute bit of all EPT structures. */
1721	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
1722	/** Set if the guest linear address field contains the faulting address. */
1723	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
1724	/** If bit 7 is one: (reserved otherwise)
1725	* 1 - violation due to physical address access.
1726	* 0 - violation caused by page walk or access/dirty bit updates
1727	*/
1728	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
1729	/** @} */
1730
1731
1732	/** @name VMX_EXIT_PORT_IO
1733	* @{
1734	*/
1735	/** 0-2: IO operation width. */
1736	#define VMX_EXIT_QUAL_IO_WIDTH(a) ((a) & 7)
1737	/** 3: IO operation direction. */
1738	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
1739	/** 4: String IO operation (INS / OUTS). */
1740	#define VMX_EXIT_QUAL_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1741	/** 5: Repeated IO operation. */
1742	#define VMX_EXIT_QUAL_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1743	/** 6: Operand encoding. */
1744	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
1745	/** 16-31: IO Port (0-0xffff). */
1746	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
1747	/* Rest reserved. */
1748	/** @} */
1749
1750
1751	/** @name VMX_EXIT_QUAL_IO_DIRECTION
1752	* @{
1753	*/
1754	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
1755	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
1756	/** @} */
1757
1758
1759	/** @name VMX_EXIT_QUAL_IO_ENCODING
1760	* @{
1761	*/
1762	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
1763	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
1764	/** @} */
1765
1766
1767	/** @name VMX_EXIT_APIC_ACCESS
1768	* @{
1769	*/
1770	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
1771	* access within the APIC page. */
1772	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1773	/** 12-15: Access type. */
1774	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
1775	/* Rest reserved. */
1776	/** @} */
1777
1778
1779	/** @name VMX_EXIT_QUAL_APIC_ACCESS_TYPE return values
1780	* @{
1781	*/
1782	/** Linear read access. */
1783	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1784	/** Linear write access. */
1785	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1786	/** Linear instruction fetch access. */
1787	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1788	/** Linear read/write access during event delivery. */
1789	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1790	/** Physical read/write access during event delivery. */
1791	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1792	/** Physical access for an instruction fetch or during instruction execution. */
1793	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1794	/** @} */
1795
1796
1797	/** @name VMX_XDTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information
1798	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
1799	* @{
1800	*/
1801	/** Address calculation scaling field (powers of two). */
1802	#define VMX_XDTR_INSINFO_SCALE_SHIFT 0
1803	#define VMX_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
1804	/** Bits 2 thru 6 are undefined. */
1805	#define VMX_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
1806	#define VMX_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
1807	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
1808	* @remarks anyone's guess why this is a 3 bit field... */
1809	#define VMX_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
1810	#define VMX_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
1811	/** Bit 10 is defined as zero. */
1812	#define VMX_XDTR_INSINFO_ZERO_10_SHIFT 10
1813	#define VMX_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
1814	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
1815	* for exits from 64-bit code as the operand size there is fixed. */
1816	#define VMX_XDTR_INSINFO_OP_SIZE_SHIFT 11
1817	#define VMX_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
1818	/** Bits 12 thru 14 are undefined. */
1819	#define VMX_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
1820	#define VMX_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
1821	/** Applicable segment register (X86_SREG_XXX values). */
1822	#define VMX_XDTR_INSINFO_SREG_SHIFT 15
1823	#define VMX_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
1824	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
1825	#define VMX_XDTR_INSINFO_INDEX_REG_SHIFT 18
1826	#define VMX_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
1827	/** Is VMX_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
1828	#define VMX_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
1829	#define VMX_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
1830	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
1831	#define VMX_XDTR_INSINFO_BASE_REG_SHIFT 23
1832	#define VMX_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
1833	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
1834	#define VMX_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
1835	#define VMX_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
1836	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values) */
1837	#define VMX_XDTR_INSINFO_INSTR_ID_SHIFT 28
1838	#define VMX_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
1839	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
1840	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
1841	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
1842	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
1843	/** Bits 30 & 31 are undefined. */
1844	#define VMX_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
1845	#define VMX_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
1846	RT_BF_ASSERT_COMPILE_CHECKS(VMX_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
1847	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
1848	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
1849	/** @} */
1850
1851
1852	/** @name VMX_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information
1853	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
1854	* This is similar to VMX_XDTR_INSINFO_XXX.
1855	* @{
1856	*/
1857	/** Address calculation scaling field (powers of two). */
1858	#define VMX_YYTR_INSINFO_SCALE_SHIFT 0
1859	#define VMX_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
1860	/** Bit 2 is undefined. */
1861	#define VMX_YYTR_INSINFO_UNDEF_2_SHIFT 2
1862	#define VMX_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
1863	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
1864	#define VMX_YYTR_INSINFO_REG1_SHIFT 3
1865	#define VMX_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
1866	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
1867	* @remarks anyone's guess why this is a 3 bit field... */
1868	#define VMX_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
1869	#define VMX_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
1870	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
1871	#define VMX_YYTR_INSINFO_HAS_REG1_SHIFT 10
1872	#define VMX_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
1873	/** Bits 11 thru 14 are undefined. */
1874	#define VMX_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
1875	#define VMX_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
1876	/** Applicable segment register (X86_SREG_XXX values). */
1877	#define VMX_YYTR_INSINFO_SREG_SHIFT 15
1878	#define VMX_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
1879	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
1880	#define VMX_YYTR_INSINFO_INDEX_REG_SHIFT 18
1881	#define VMX_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
1882	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
1883	#define VMX_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
1884	#define VMX_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
1885	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
1886	#define VMX_YYTR_INSINFO_BASE_REG_SHIFT 23
1887	#define VMX_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
1888	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
1889	#define VMX_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
1890	#define VMX_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
1891	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
1892	#define VMX_YYTR_INSINFO_INSTR_ID_SHIFT 28
1893	#define VMX_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
1894	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
1895	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
1896	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
1897	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
1898	/** Bits 30 & 31 are undefined. */
1899	#define VMX_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
1900	#define VMX_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
1901	RT_BF_ASSERT_COMPILE_CHECKS(VMX_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
1902	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
1903	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
1904	/** @} */
1905
1906
1907	/** @name VMCS field encoding: Natural width guest-state fields.
1908	* @{
1909	*/
1910	#define VMX_VMCS_GUEST_CR0 0x6800
1911	#define VMX_VMCS_GUEST_CR3 0x6802
1912	#define VMX_VMCS_GUEST_CR4 0x6804
1913	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1914	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1915	#define VMX_VMCS_GUEST_SS_BASE 0x680A
1916	#define VMX_VMCS_GUEST_DS_BASE 0x680C
1917	#define VMX_VMCS_GUEST_FS_BASE 0x680E
1918	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1919	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1920	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1921	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1922	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1923	#define VMX_VMCS_GUEST_DR7 0x681A
1924	#define VMX_VMCS_GUEST_RSP 0x681C
1925	#define VMX_VMCS_GUEST_RIP 0x681E
1926	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1927	#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1928	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1929	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1930	/** @} */
1931
1932
1933	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1934	* Bits 4-11, 13 and 15-63 are reserved.
1935	* @{
1936	*/
1937	/** Hardware breakpoint 0 was met. */
1938	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1939	/** Hardware breakpoint 1 was met. */
1940	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1941	/** Hardware breakpoint 2 was met. */
1942	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1943	/** Hardware breakpoint 3 was met. */
1944	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1945	/** At least one data or IO breakpoint was hit. */
1946	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1947	/** A debug exception would have been triggered by single-step execution mode. */
1948	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1949	/** @} */
1950
1951
1952	/** @name VMCS field encoding: Natural width host-state fields.
1953	* @{
1954	*/
1955	#define VMX_VMCS_HOST_CR0 0x6C00
1956	#define VMX_VMCS_HOST_CR3 0x6C02
1957	#define VMX_VMCS_HOST_CR4 0x6C04
1958	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1959	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1960	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1961	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1962	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1963	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1964	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1965	#define VMX_VMCS_HOST_RSP 0x6C14
1966	#define VMX_VMCS_HOST_RIP 0x6C16
1967	/** @} */
1968
1969
1970	/** @defgroup grp_hm_vmx_asm VMX Assembly Helpers
1971	* @{
1972	*/
1973
1974	/**
1975	* Restores some host-state fields that need not be done on every VM-exit.
1976	*
1977	* @returns VBox status code.
1978	* @param fRestoreHostFlags Flags of which host registers needs to be
1979	* restored.
1980	* @param pRestoreHost Pointer to the host-restore structure.
1981	*/
1982	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1983
1984
1985	/**
1986	* Dispatches an NMI to the host.
1987	*/
1988	DECLASM(int) VMXDispatchHostNmi(void);
1989
1990
1991	/**
1992	* Executes VMXON.
1993	*
1994	* @returns VBox status code.
1995	* @param HCPhysVmxOn Physical address of VMXON structure.
1996	*/
1997	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
1998	DECLASM(int) VMXEnable(RTHCPHYS HCPhysVmxOn);
1999	#else
2000	DECLINLINE(int) VMXEnable(RTHCPHYS HCPhysVmxOn)
2001	{
2002	# if RT_INLINE_ASM_GNU_STYLE
2003	int rc = VINF_SUCCESS;
2004	__asm__ __volatile__ (
2005	"push %3 \n\t"
2006	"push %2 \n\t"
2007	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
2008	"ja 2f \n\t"
2009	"je 1f \n\t"
2010	"movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
2011	"jmp 2f \n\t"
2012	"1: \n\t"
2013	"movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
2014	"2: \n\t"
2015	"add $8, %%esp \n\t"
2016	:"=rm"(rc)
2017	:"0"(VINF_SUCCESS),
2018	"ir"((uint32_t)HCPhysVmxOn), /* don't allow direct memory reference here, */
2019	"ir"((uint32_t)(HCPhysVmxOn >> 32)) /* this would not work with -fomit-frame-pointer */
2020	:"memory"
2021	);
2022	return rc;
2023
2024	# elif VMX_USE_MSC_INTRINSICS
2025	unsigned char rcMsc = __vmx_on(&HCPhysVmxOn);
2026	if (RT_LIKELY(rcMsc == 0))
2027	return VINF_SUCCESS;
2028	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
2029
2030	# else
2031	int rc = VINF_SUCCESS;
2032	__asm
2033	{
2034	push dword ptr [HCPhysVmxOn + 4]
2035	push dword ptr [HCPhysVmxOn]
2036	_emit 0xF3
2037	_emit 0x0F
2038	_emit 0xC7
2039	_emit 0x34
2040	_emit 0x24 /* VMXON [esp] */
2041	jnc vmxon_good
2042	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
2043	jmp the_end
2044
2045	vmxon_good:
2046	jnz the_end
2047	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
2048	the_end:
2049	add esp, 8
2050	}
2051	return rc;
2052	# endif
2053	}
2054	#endif
2055
2056
2057	/**
2058	* Executes VMXOFF.
2059	*/
2060	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2061	DECLASM(void) VMXDisable(void);
2062	#else
2063	DECLINLINE(void) VMXDisable(void)
2064	{
2065	# if RT_INLINE_ASM_GNU_STYLE
2066	__asm__ __volatile__ (
2067	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
2068	);
2069
2070	# elif VMX_USE_MSC_INTRINSICS
2071	__vmx_off();
2072
2073	# else
2074	__asm
2075	{
2076	_emit 0x0F
2077	_emit 0x01
2078	_emit 0xC4 /* VMXOFF */
2079	}
2080	# endif
2081	}
2082	#endif
2083
2084
2085	/**
2086	* Executes VMCLEAR.
2087	*
2088	* @returns VBox status code.
2089	* @param HCPhysVmcs Physical address of VM control structure.
2090	*/
2091	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2092	DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
2093	#else
2094	DECLINLINE(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs)
2095	{
2096	# if RT_INLINE_ASM_GNU_STYLE
2097	int rc = VINF_SUCCESS;
2098	__asm__ __volatile__ (
2099	"push %3 \n\t"
2100	"push %2 \n\t"
2101	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
2102	"jnc 1f \n\t"
2103	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2104	"1: \n\t"
2105	"add $8, %%esp \n\t"
2106	:"=rm"(rc)
2107	:"0"(VINF_SUCCESS),
2108	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2109	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this would not work with -fomit-frame-pointer */
2110	:"memory"
2111	);
2112	return rc;
2113
2114	# elif VMX_USE_MSC_INTRINSICS
2115	unsigned char rcMsc = __vmx_vmclear(&HCPhysVmcs);
2116	if (RT_LIKELY(rcMsc == 0))
2117	return VINF_SUCCESS;
2118	return VERR_VMX_INVALID_VMCS_PTR;
2119
2120	# else
2121	int rc = VINF_SUCCESS;
2122	__asm
2123	{
2124	push dword ptr [HCPhysVmcs + 4]
2125	push dword ptr [HCPhysVmcs]
2126	_emit 0x66
2127	_emit 0x0F
2128	_emit 0xC7
2129	_emit 0x34
2130	_emit 0x24 /* VMCLEAR [esp] */
2131	jnc success
2132	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2133	success:
2134	add esp, 8
2135	}
2136	return rc;
2137	# endif
2138	}
2139	#endif
2140
2141
2142	/**
2143	* Executes VMPTRLD.
2144	*
2145	* @returns VBox status code.
2146	* @param HCPhysVmcs Physical address of VMCS structure.
2147	*/
2148	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2149	DECLASM(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs);
2150	#else
2151	DECLINLINE(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs)
2152	{
2153	# if RT_INLINE_ASM_GNU_STYLE
2154	int rc = VINF_SUCCESS;
2155	__asm__ __volatile__ (
2156	"push %3 \n\t"
2157	"push %2 \n\t"
2158	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2159	"jnc 1f \n\t"
2160	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2161	"1: \n\t"
2162	"add $8, %%esp \n\t"
2163	:"=rm"(rc)
2164	:"0"(VINF_SUCCESS),
2165	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2166	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this will not work with -fomit-frame-pointer */
2167	);
2168	return rc;
2169
2170	# elif VMX_USE_MSC_INTRINSICS
2171	unsigned char rcMsc = __vmx_vmptrld(&HCPhysVmcs);
2172	if (RT_LIKELY(rcMsc == 0))
2173	return VINF_SUCCESS;
2174	return VERR_VMX_INVALID_VMCS_PTR;
2175
2176	# else
2177	int rc = VINF_SUCCESS;
2178	__asm
2179	{
2180	push dword ptr [HCPhysVmcs + 4]
2181	push dword ptr [HCPhysVmcs]
2182	_emit 0x0F
2183	_emit 0xC7
2184	_emit 0x34
2185	_emit 0x24 /* VMPTRLD [esp] */
2186	jnc success
2187	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2188
2189	success:
2190	add esp, 8
2191	}
2192	return rc;
2193	# endif
2194	}
2195	#endif
2196
2197
2198	/**
2199	* Executes VMPTRST.
2200	*
2201	* @returns VBox status code.
2202	* @param pHCPhysVmcs Where to store the physical address of the current
2203	* VMCS.
2204	*/
2205	DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
2206
2207
2208	/**
2209	* Executes VMWRITE.
2210	*
2211	* @returns VBox status code.
2212	* @retval VINF_SUCCESS.
2213	* @retval VERR_VMX_INVALID_VMCS_PTR.
2214	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2215	*
2216	* @param idxField VMCS index.
2217	* @param u32Val 32-bit value.
2218	*
2219	* @remarks The values of the two status codes can be OR'ed together, the result
2220	* will be VERR_VMX_INVALID_VMCS_PTR.
2221	*/
2222	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2223	DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2224	#else
2225	DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2226	{
2227	# if RT_INLINE_ASM_GNU_STYLE
2228	int rc = VINF_SUCCESS;
2229	__asm__ __volatile__ (
2230	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2231	"ja 2f \n\t"
2232	"je 1f \n\t"
2233	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2234	"jmp 2f \n\t"
2235	"1: \n\t"
2236	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2237	"2: \n\t"
2238	:"=rm"(rc)
2239	:"0"(VINF_SUCCESS),
2240	"a"(idxField),
2241	"d"(u32Val)
2242	);
2243	return rc;
2244
2245	# elif VMX_USE_MSC_INTRINSICS
2246	unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2247	if (RT_LIKELY(rcMsc == 0))
2248	return VINF_SUCCESS;
2249	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2250
2251	#else
2252	int rc = VINF_SUCCESS;
2253	__asm
2254	{
2255	push dword ptr [u32Val]
2256	mov eax, [idxField]
2257	_emit 0x0F
2258	_emit 0x79
2259	_emit 0x04
2260	_emit 0x24 /* VMWRITE eax, [esp] */
2261	jnc valid_vmcs
2262	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2263	jmp the_end
2264
2265	valid_vmcs:
2266	jnz the_end
2267	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2268	the_end:
2269	add esp, 4
2270	}
2271	return rc;
2272	# endif
2273	}
2274	#endif
2275
2276	/**
2277	* Executes VMWRITE.
2278	*
2279	* @returns VBox status code.
2280	* @retval VINF_SUCCESS.
2281	* @retval VERR_VMX_INVALID_VMCS_PTR.
2282	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2283	*
2284	* @param idxField VMCS index.
2285	* @param u64Val 16, 32 or 64-bit value.
2286	*
2287	* @remarks The values of the two status codes can be OR'ed together, the result
2288	* will be VERR_VMX_INVALID_VMCS_PTR.
2289	*/
2290	#if !defined(RT_ARCH_X86)
2291	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
2292	DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2293	# else /* VMX_USE_MSC_INTRINSICS */
2294	DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2295	{
2296	unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2297	if (RT_LIKELY(rcMsc == 0))
2298	return VINF_SUCCESS;
2299	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2300	}
2301	# endif /* VMX_USE_MSC_INTRINSICS */
2302	#else
2303	# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2304	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2305	#endif
2306
2307	#if ARCH_BITS == 32
2308	# define VMXWriteVmcsHstN VMXWriteVmcs32
2309	# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2310	#else /* ARCH_BITS == 64 */
2311	# define VMXWriteVmcsHstN VMXWriteVmcs64
2312	# define VMXWriteVmcsGstN VMXWriteVmcs64
2313	#endif
2314
2315
2316	/**
2317	* Invalidate a page using INVEPT.
2318	*
2319	* @returns VBox status code.
2320	* @param enmFlush Type of flush.
2321	* @param pDescriptor Pointer to the descriptor.
2322	*/
2323	DECLASM(int) VMXR0InvEPT(VMXFLUSHEPT enmFlush, uint64_t *pDescriptor);
2324
2325
2326	/**
2327	* Invalidate a page using INVVPID.
2328	*
2329	* @returns VBox status code.
2330	* @param enmFlush Type of flush.
2331	* @param pDescriptor Pointer to the descriptor.
2332	*/
2333	DECLASM(int) VMXR0InvVPID(VMXFLUSHVPID enmFlush, uint64_t *pDescriptor);
2334
2335
2336	/**
2337	* Executes VMREAD.
2338	*
2339	* @returns VBox status code.
2340	* @retval VINF_SUCCESS.
2341	* @retval VERR_VMX_INVALID_VMCS_PTR.
2342	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2343	*
2344	* @param idxField VMCS index.
2345	* @param pData Where to store VM field value.
2346	*
2347	* @remarks The values of the two status codes can be OR'ed together, the result
2348	* will be VERR_VMX_INVALID_VMCS_PTR.
2349	*/
2350	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2351	DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2352	#else
2353	DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2354	{
2355	# if RT_INLINE_ASM_GNU_STYLE
2356	int rc = VINF_SUCCESS;
2357	__asm__ __volatile__ (
2358	"movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2359	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2360	"ja 2f \n\t"
2361	"je 1f \n\t"
2362	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2363	"jmp 2f \n\t"
2364	"1: \n\t"
2365	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2366	"2: \n\t"
2367	:"=&r"(rc),
2368	"=d"(*pData)
2369	:"a"(idxField),
2370	"d"(0)
2371	);
2372	return rc;
2373
2374	# elif VMX_USE_MSC_INTRINSICS
2375	unsigned char rcMsc;
2376	# if ARCH_BITS == 32
2377	rcMsc = __vmx_vmread(idxField, pData);
2378	# else
2379	uint64_t u64Tmp;
2380	rcMsc = __vmx_vmread(idxField, &u64Tmp);
2381	*pData = (uint32_t)u64Tmp;
2382	# endif
2383	if (RT_LIKELY(rcMsc == 0))
2384	return VINF_SUCCESS;
2385	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2386
2387	#else
2388	int rc = VINF_SUCCESS;
2389	__asm
2390	{
2391	sub esp, 4
2392	mov dword ptr [esp], 0
2393	mov eax, [idxField]
2394	_emit 0x0F
2395	_emit 0x78
2396	_emit 0x04
2397	_emit 0x24 /* VMREAD eax, [esp] */
2398	mov edx, pData
2399	pop dword ptr [edx]
2400	jnc valid_vmcs
2401	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2402	jmp the_end
2403
2404	valid_vmcs:
2405	jnz the_end
2406	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2407	the_end:
2408	}
2409	return rc;
2410	# endif
2411	}
2412	#endif
2413
2414	/**
2415	* Executes VMREAD.
2416	*
2417	* @returns VBox status code.
2418	* @retval VINF_SUCCESS.
2419	* @retval VERR_VMX_INVALID_VMCS_PTR.
2420	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2421	*
2422	* @param idxField VMCS index.
2423	* @param pData Where to store VM field value.
2424	*
2425	* @remarks The values of the two status codes can be OR'ed together, the result
2426	* will be VERR_VMX_INVALID_VMCS_PTR.
2427	*/
2428	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS)
2429	DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2430	#else
2431	DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2432	{
2433	# if VMX_USE_MSC_INTRINSICS
2434	unsigned char rcMsc;
2435	# if ARCH_BITS == 32
2436	size_t uLow;
2437	size_t uHigh;
2438	rcMsc = __vmx_vmread(idxField, &uLow);
2439	rcMsc \|= __vmx_vmread(idxField + 1, &uHigh);
2440	*pData = RT_MAKE_U64(uLow, uHigh);
2441	# else
2442	rcMsc = __vmx_vmread(idxField, pData);
2443	# endif
2444	if (RT_LIKELY(rcMsc == 0))
2445	return VINF_SUCCESS;
2446	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2447
2448	# elif ARCH_BITS == 32
2449	int rc;
2450	uint32_t val_hi, val;
2451	rc = VMXReadVmcs32(idxField, &val);
2452	rc \|= VMXReadVmcs32(idxField + 1, &val_hi);
2453	AssertRC(rc);
2454	*pData = RT_MAKE_U64(val, val_hi);
2455	return rc;
2456
2457	# else
2458	# error "Shouldn't be here..."
2459	# endif
2460	}
2461	#endif
2462
2463
2464	/**
2465	* Gets the last instruction error value from the current VMCS.
2466	*
2467	* @returns VBox status code.
2468	*/
2469	DECLINLINE(uint32_t) VMXGetLastError(void)
2470	{
2471	#if ARCH_BITS == 64
2472	uint64_t uLastError = 0;
2473	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2474	AssertRC(rc);
2475	return (uint32_t)uLastError;
2476
2477	#else /* 32-bit host: */
2478	uint32_t uLastError = 0;
2479	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2480	AssertRC(rc);
2481	return uLastError;
2482	#endif
2483	}
2484
2485	/** @} */
2486
2487	/** @} */
2488
2489	#endif
2490

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 72854

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