hm_vmx.h@ 73756

Last change on this file since 73756 was 73756, checked in by vboxsync, 6 years ago
VMM/IEM: Nested VMX: bugref:9180 VMCLEAR skeleton.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# pragma warning(push)
38	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
39	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
40	# include <intrin.h>
41	# pragma warning(pop)
42	/* We always want them as intrinsics, no functions. */
43	# pragma intrinsic(__vmx_on)
44	# pragma intrinsic(__vmx_off)
45	# pragma intrinsic(__vmx_vmclear)
46	# pragma intrinsic(__vmx_vmptrld)
47	# pragma intrinsic(__vmx_vmread)
48	# pragma intrinsic(__vmx_vmwrite)
49	# define VMX_USE_MSC_INTRINSICS 1
50	#else
51	# define VMX_USE_MSC_INTRINSICS 0
52	#endif
53
54
55	/** @defgroup grp_hm_vmx VMX Types and Definitions
56	* @ingroup grp_hm
57	* @{
58	*/
59
60	/** @name Host-state restoration flags.
61	* @note If you change these values don't forget to update the assembly
62	* defines as well!
63	* @{
64	*/
65	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
66	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
67	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
68	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
69	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
70	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
71	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
72	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
73	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
74	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
75	/** @} */
76
77	/**
78	* Host-state restoration structure.
79	* This holds host-state fields that require manual restoration.
80	* Assembly version found in hm_vmx.mac (should be automatically verified).
81	*/
82	typedef struct VMXRESTOREHOST
83	{
84	RTSEL uHostSelDS; /* 0x00 */
85	RTSEL uHostSelES; /* 0x02 */
86	RTSEL uHostSelFS; /* 0x04 */
87	RTSEL uHostSelGS; /* 0x06 */
88	RTSEL uHostSelTR; /* 0x08 */
89	uint8_t abPadding0[4];
90	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
91	uint8_t abPadding1[6];
92	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
93	uint8_t abPadding2[6];
94	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
95	uint64_t uHostFSBase; /* 0x38 */
96	uint64_t uHostGSBase; /* 0x40 */
97	} VMXRESTOREHOST;
98	/** Pointer to VMXRESTOREHOST. */
99	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
100	AssertCompileSize(X86XDTR64, 10);
101	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
102	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
103	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
104	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
105	AssertCompileSize(VMXRESTOREHOST, 72);
106	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
107
108	/** @name Host-state MSR lazy-restoration flags.
109	* @{
110	*/
111	/** The host MSRs have been saved. */
112	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
113	/** The guest MSRs are loaded and in effect. */
114	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
115	/** @} */
116
117	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
118	* UFC = Unsupported Feature Combination.
119	* @{
120	*/
121	/** Unsupported pin-based VM-execution controls combo. */
122	#define VMX_UFC_CTRL_PIN_EXEC 1
123	/** Unsupported processor-based VM-execution controls combo. */
124	#define VMX_UFC_CTRL_PROC_EXEC 2
125	/** Unsupported move debug register VM-exit combo. */
126	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
127	/** Unsupported VM-entry controls combo. */
128	#define VMX_UFC_CTRL_ENTRY 4
129	/** Unsupported VM-exit controls combo. */
130	#define VMX_UFC_CTRL_EXIT 5
131	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
132	* for storing host MSRs. */
133	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
134	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
135	* for storing guest MSRs. */
136	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
137	/** Invalid VMCS size. */
138	#define VMX_UFC_INVALID_VMCS_SIZE 8
139	/** Unsupported secondary processor-based VM-execution controls combo. */
140	#define VMX_UFC_CTRL_PROC_EXEC2 9
141	/** Invalid unrestricted-guest execution controls combo. */
142	#define VMX_UFC_INVALID_UX_COMBO 10
143	/** EPT flush type not supported. */
144	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
145	/** EPT paging structure memory type is not write-back. */
146	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
147	/** EPT requires INVEPT instr. support but it's not available. */
148	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
149	/** EPT requires page-walk length of 4. */
150	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
151	/** @} */
152
153	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
154	* VCI = VMCS-field Cache Invalid.
155	* @{
156	*/
157	/** Cache of VM-entry controls invalid. */
158	#define VMX_VCI_CTRL_ENTRY 300
159	/** Cache of VM-exit controls invalid. */
160	#define VMX_VCI_CTRL_EXIT 301
161	/** Cache of pin-based VM-execution controls invalid. */
162	#define VMX_VCI_CTRL_PIN_EXEC 302
163	/** Cache of processor-based VM-execution controls invalid. */
164	#define VMX_VCI_CTRL_PROC_EXEC 303
165	/** Cache of secondary processor-based VM-execution controls invalid. */
166	#define VMX_VCI_CTRL_PROC_EXEC2 304
167	/** Cache of exception bitmap invalid. */
168	#define VMX_VCI_CTRL_XCPT_BITMAP 305
169	/** Cache of TSC offset invalid. */
170	#define VMX_VCI_CTRL_TSC_OFFSET 306
171	/** @} */
172
173	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
174	* IGS = Invalid Guest State.
175	* @{
176	*/
177	/** An error occurred while checking invalid-guest-state. */
178	#define VMX_IGS_ERROR 500
179	/** The invalid guest-state checks did not find any reason why. */
180	#define VMX_IGS_REASON_NOT_FOUND 501
181	/** CR0 fixed1 bits invalid. */
182	#define VMX_IGS_CR0_FIXED1 502
183	/** CR0 fixed0 bits invalid. */
184	#define VMX_IGS_CR0_FIXED0 503
185	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
186	#define VMX_IGS_CR0_PG_PE_COMBO 504
187	/** CR4 fixed1 bits invalid. */
188	#define VMX_IGS_CR4_FIXED1 505
189	/** CR4 fixed0 bits invalid. */
190	#define VMX_IGS_CR4_FIXED0 506
191	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
192	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
193	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
194	/** CR0.PG not set for long-mode when not using unrestricted guest. */
195	#define VMX_IGS_CR0_PG_LONGMODE 508
196	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
197	#define VMX_IGS_CR4_PAE_LONGMODE 509
198	/** CR4.PCIDE set for 32-bit guest. */
199	#define VMX_IGS_CR4_PCIDE 510
200	/** VMCS' DR7 reserved bits not set to 0. */
201	#define VMX_IGS_DR7_RESERVED 511
202	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
203	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
204	/** VMCS' EFER MSR reserved bits not set to 0. */
205	#define VMX_IGS_EFER_MSR_RESERVED 513
206	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
207	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
208	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
209	* without unrestricted guest. */
210	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
211	/** CS.Attr.P bit invalid. */
212	#define VMX_IGS_CS_ATTR_P_INVALID 516
213	/** CS.Attr reserved bits not set to 0. */
214	#define VMX_IGS_CS_ATTR_RESERVED 517
215	/** CS.Attr.G bit invalid. */
216	#define VMX_IGS_CS_ATTR_G_INVALID 518
217	/** CS is unusable. */
218	#define VMX_IGS_CS_ATTR_UNUSABLE 519
219	/** CS and SS DPL unequal. */
220	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
221	/** CS and SS DPL mismatch. */
222	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
223	/** CS Attr.Type invalid. */
224	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
225	/** CS and SS RPL unequal. */
226	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
227	/** SS.Attr.DPL and SS RPL unequal. */
228	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
229	/** SS.Attr.DPL invalid for segment type. */
230	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
231	/** SS.Attr.Type invalid. */
232	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
233	/** SS.Attr.P bit invalid. */
234	#define VMX_IGS_SS_ATTR_P_INVALID 527
235	/** SS.Attr reserved bits not set to 0. */
236	#define VMX_IGS_SS_ATTR_RESERVED 528
237	/** SS.Attr.G bit invalid. */
238	#define VMX_IGS_SS_ATTR_G_INVALID 529
239	/** DS.Attr.A bit invalid. */
240	#define VMX_IGS_DS_ATTR_A_INVALID 530
241	/** DS.Attr.P bit invalid. */
242	#define VMX_IGS_DS_ATTR_P_INVALID 531
243	/** DS.Attr.DPL and DS RPL unequal. */
244	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
245	/** DS.Attr reserved bits not set to 0. */
246	#define VMX_IGS_DS_ATTR_RESERVED 533
247	/** DS.Attr.G bit invalid. */
248	#define VMX_IGS_DS_ATTR_G_INVALID 534
249	/** DS.Attr.Type invalid. */
250	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
251	/** ES.Attr.A bit invalid. */
252	#define VMX_IGS_ES_ATTR_A_INVALID 536
253	/** ES.Attr.P bit invalid. */
254	#define VMX_IGS_ES_ATTR_P_INVALID 537
255	/** ES.Attr.DPL and DS RPL unequal. */
256	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
257	/** ES.Attr reserved bits not set to 0. */
258	#define VMX_IGS_ES_ATTR_RESERVED 539
259	/** ES.Attr.G bit invalid. */
260	#define VMX_IGS_ES_ATTR_G_INVALID 540
261	/** ES.Attr.Type invalid. */
262	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
263	/** FS.Attr.A bit invalid. */
264	#define VMX_IGS_FS_ATTR_A_INVALID 542
265	/** FS.Attr.P bit invalid. */
266	#define VMX_IGS_FS_ATTR_P_INVALID 543
267	/** FS.Attr.DPL and DS RPL unequal. */
268	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
269	/** FS.Attr reserved bits not set to 0. */
270	#define VMX_IGS_FS_ATTR_RESERVED 545
271	/** FS.Attr.G bit invalid. */
272	#define VMX_IGS_FS_ATTR_G_INVALID 546
273	/** FS.Attr.Type invalid. */
274	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
275	/** GS.Attr.A bit invalid. */
276	#define VMX_IGS_GS_ATTR_A_INVALID 548
277	/** GS.Attr.P bit invalid. */
278	#define VMX_IGS_GS_ATTR_P_INVALID 549
279	/** GS.Attr.DPL and DS RPL unequal. */
280	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
281	/** GS.Attr reserved bits not set to 0. */
282	#define VMX_IGS_GS_ATTR_RESERVED 551
283	/** GS.Attr.G bit invalid. */
284	#define VMX_IGS_GS_ATTR_G_INVALID 552
285	/** GS.Attr.Type invalid. */
286	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
287	/** V86 mode CS.Base invalid. */
288	#define VMX_IGS_V86_CS_BASE_INVALID 554
289	/** V86 mode CS.Limit invalid. */
290	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
291	/** V86 mode CS.Attr invalid. */
292	#define VMX_IGS_V86_CS_ATTR_INVALID 556
293	/** V86 mode SS.Base invalid. */
294	#define VMX_IGS_V86_SS_BASE_INVALID 557
295	/** V86 mode SS.Limit invalid. */
296	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
297	/** V86 mode SS.Attr invalid. */
298	#define VMX_IGS_V86_SS_ATTR_INVALID 559
299	/** V86 mode DS.Base invalid. */
300	#define VMX_IGS_V86_DS_BASE_INVALID 560
301	/** V86 mode DS.Limit invalid. */
302	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
303	/** V86 mode DS.Attr invalid. */
304	#define VMX_IGS_V86_DS_ATTR_INVALID 562
305	/** V86 mode ES.Base invalid. */
306	#define VMX_IGS_V86_ES_BASE_INVALID 563
307	/** V86 mode ES.Limit invalid. */
308	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
309	/** V86 mode ES.Attr invalid. */
310	#define VMX_IGS_V86_ES_ATTR_INVALID 565
311	/** V86 mode FS.Base invalid. */
312	#define VMX_IGS_V86_FS_BASE_INVALID 566
313	/** V86 mode FS.Limit invalid. */
314	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
315	/** V86 mode FS.Attr invalid. */
316	#define VMX_IGS_V86_FS_ATTR_INVALID 568
317	/** V86 mode GS.Base invalid. */
318	#define VMX_IGS_V86_GS_BASE_INVALID 569
319	/** V86 mode GS.Limit invalid. */
320	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
321	/** V86 mode GS.Attr invalid. */
322	#define VMX_IGS_V86_GS_ATTR_INVALID 571
323	/** Longmode CS.Base invalid. */
324	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
325	/** Longmode SS.Base invalid. */
326	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
327	/** Longmode DS.Base invalid. */
328	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
329	/** Longmode ES.Base invalid. */
330	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
331	/** SYSENTER ESP is not canonical. */
332	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
333	/** SYSENTER EIP is not canonical. */
334	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
335	/** PAT MSR invalid. */
336	#define VMX_IGS_PAT_MSR_INVALID 578
337	/** PAT MSR reserved bits not set to 0. */
338	#define VMX_IGS_PAT_MSR_RESERVED 579
339	/** GDTR.Base is not canonical. */
340	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
341	/** IDTR.Base is not canonical. */
342	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
343	/** GDTR.Limit invalid. */
344	#define VMX_IGS_GDTR_LIMIT_INVALID 582
345	/** IDTR.Limit invalid. */
346	#define VMX_IGS_IDTR_LIMIT_INVALID 583
347	/** Longmode RIP is invalid. */
348	#define VMX_IGS_LONGMODE_RIP_INVALID 584
349	/** RFLAGS reserved bits not set to 0. */
350	#define VMX_IGS_RFLAGS_RESERVED 585
351	/** RFLAGS RA1 reserved bits not set to 1. */
352	#define VMX_IGS_RFLAGS_RESERVED1 586
353	/** RFLAGS.VM (V86 mode) invalid. */
354	#define VMX_IGS_RFLAGS_VM_INVALID 587
355	/** RFLAGS.IF invalid. */
356	#define VMX_IGS_RFLAGS_IF_INVALID 588
357	/** Activity state invalid. */
358	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
359	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
360	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
361	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
362	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
363	/** Activity state SIPI WAIT invalid. */
364	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
365	/** Interruptibility state reserved bits not set to 0. */
366	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
367	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
368	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
369	/** Interruptibility state block-by-STI invalid for EFLAGS. */
370	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
371	/** Interruptibility state invalid while trying to deliver external
372	* interrupt. */
373	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
374	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
375	* NMI. */
376	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
377	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
378	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
379	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
380	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
381	/** Interruptibility state block-by-STI (maybe) invalid when trying to
382	* deliver an NMI. */
383	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
384	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
385	* active. */
386	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
387	/** Pending debug exceptions reserved bits not set to 0. */
388	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
389	/** Longmode pending debug exceptions reserved bits not set to 0. */
390	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
391	/** Pending debug exceptions.BS bit is not set when it should be. */
392	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
393	/** Pending debug exceptions.BS bit is not clear when it should be. */
394	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
395	/** VMCS link pointer reserved bits not set to 0. */
396	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
397	/** TR cannot index into LDT, TI bit MBZ. */
398	#define VMX_IGS_TR_TI_INVALID 607
399	/** LDTR cannot index into LDT. TI bit MBZ. */
400	#define VMX_IGS_LDTR_TI_INVALID 608
401	/** TR.Base is not canonical. */
402	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
403	/** FS.Base is not canonical. */
404	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
405	/** GS.Base is not canonical. */
406	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
407	/** LDTR.Base is not canonical. */
408	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
409	/** TR is unusable. */
410	#define VMX_IGS_TR_ATTR_UNUSABLE 613
411	/** TR.Attr.S bit invalid. */
412	#define VMX_IGS_TR_ATTR_S_INVALID 614
413	/** TR is not present. */
414	#define VMX_IGS_TR_ATTR_P_INVALID 615
415	/** TR.Attr reserved bits not set to 0. */
416	#define VMX_IGS_TR_ATTR_RESERVED 616
417	/** TR.Attr.G bit invalid. */
418	#define VMX_IGS_TR_ATTR_G_INVALID 617
419	/** Longmode TR.Attr.Type invalid. */
420	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
421	/** TR.Attr.Type invalid. */
422	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
423	/** CS.Attr.S invalid. */
424	#define VMX_IGS_CS_ATTR_S_INVALID 620
425	/** CS.Attr.DPL invalid. */
426	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
427	/** PAE PDPTE reserved bits not set to 0. */
428	#define VMX_IGS_PAE_PDPTE_RESERVED 623
429	/** @} */
430
431	/** @name VMX VMCS-Read cache indices.
432	* @{
433	*/
434	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
435	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
436	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
437	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
438	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
439	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
440	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
441	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
442	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
443	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
444	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
445	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
446	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
447	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
448	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
449	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
450	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
451	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
452	/** @} */
453
454	/** @name VMX EPT paging structures
455	* @{
456	*/
457
458	/**
459	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
460	*/
461	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
462
463	/**
464	* EPT Page Directory Pointer Entry. Bit view.
465	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
466	* this did cause trouble with one compiler/version).
467	*/
468	typedef struct EPTPML4EBITS
469	{
470	/** Present bit. */
471	uint64_t u1Present : 1;
472	/** Writable bit. */
473	uint64_t u1Write : 1;
474	/** Executable bit. */
475	uint64_t u1Execute : 1;
476	/** Reserved (must be 0). */
477	uint64_t u5Reserved : 5;
478	/** Available for software. */
479	uint64_t u4Available : 4;
480	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
481	uint64_t u40PhysAddr : 40;
482	/** Available for software. */
483	uint64_t u12Available : 12;
484	} EPTPML4EBITS;
485	AssertCompileSize(EPTPML4EBITS, 8);
486
487	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
488	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
489	/** The page shift to get the PML4 index. */
490	#define EPT_PML4_SHIFT X86_PML4_SHIFT
491	/** The PML4 index mask (apply to a shifted page address). */
492	#define EPT_PML4_MASK X86_PML4_MASK
493
494	/**
495	* EPT PML4E.
496	*/
497	typedef union EPTPML4E
498	{
499	/** Normal view. */
500	EPTPML4EBITS n;
501	/** Unsigned integer view. */
502	X86PGPAEUINT u;
503	/** 64 bit unsigned integer view. */
504	uint64_t au64[1];
505	/** 32 bit unsigned integer view. */
506	uint32_t au32[2];
507	} EPTPML4E;
508	AssertCompileSize(EPTPML4E, 8);
509	/** Pointer to a PML4 table entry. */
510	typedef EPTPML4E *PEPTPML4E;
511	/** Pointer to a const PML4 table entry. */
512	typedef const EPTPML4E *PCEPTPML4E;
513
514	/**
515	* EPT PML4 Table.
516	*/
517	typedef struct EPTPML4
518	{
519	EPTPML4E a[EPT_PG_ENTRIES];
520	} EPTPML4;
521	AssertCompileSize(EPTPML4, 0x1000);
522	/** Pointer to an EPT PML4 Table. */
523	typedef EPTPML4 *PEPTPML4;
524	/** Pointer to a const EPT PML4 Table. */
525	typedef const EPTPML4 *PCEPTPML4;
526
527	/**
528	* EPT Page Directory Pointer Entry. Bit view.
529	*/
530	typedef struct EPTPDPTEBITS
531	{
532	/** Present bit. */
533	uint64_t u1Present : 1;
534	/** Writable bit. */
535	uint64_t u1Write : 1;
536	/** Executable bit. */
537	uint64_t u1Execute : 1;
538	/** Reserved (must be 0). */
539	uint64_t u5Reserved : 5;
540	/** Available for software. */
541	uint64_t u4Available : 4;
542	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
543	uint64_t u40PhysAddr : 40;
544	/** Available for software. */
545	uint64_t u12Available : 12;
546	} EPTPDPTEBITS;
547	AssertCompileSize(EPTPDPTEBITS, 8);
548
549	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
550	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
551	/** The page shift to get the PDPT index. */
552	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
553	/** The PDPT index mask (apply to a shifted page address). */
554	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
555
556	/**
557	* EPT Page Directory Pointer.
558	*/
559	typedef union EPTPDPTE
560	{
561	/** Normal view. */
562	EPTPDPTEBITS n;
563	/** Unsigned integer view. */
564	X86PGPAEUINT u;
565	/** 64 bit unsigned integer view. */
566	uint64_t au64[1];
567	/** 32 bit unsigned integer view. */
568	uint32_t au32[2];
569	} EPTPDPTE;
570	AssertCompileSize(EPTPDPTE, 8);
571	/** Pointer to an EPT Page Directory Pointer Entry. */
572	typedef EPTPDPTE *PEPTPDPTE;
573	/** Pointer to a const EPT Page Directory Pointer Entry. */
574	typedef const EPTPDPTE *PCEPTPDPTE;
575
576	/**
577	* EPT Page Directory Pointer Table.
578	*/
579	typedef struct EPTPDPT
580	{
581	EPTPDPTE a[EPT_PG_ENTRIES];
582	} EPTPDPT;
583	AssertCompileSize(EPTPDPT, 0x1000);
584	/** Pointer to an EPT Page Directory Pointer Table. */
585	typedef EPTPDPT *PEPTPDPT;
586	/** Pointer to a const EPT Page Directory Pointer Table. */
587	typedef const EPTPDPT *PCEPTPDPT;
588
589	/**
590	* EPT Page Directory Table Entry. Bit view.
591	*/
592	typedef struct EPTPDEBITS
593	{
594	/** Present bit. */
595	uint64_t u1Present : 1;
596	/** Writable bit. */
597	uint64_t u1Write : 1;
598	/** Executable bit. */
599	uint64_t u1Execute : 1;
600	/** Reserved (must be 0). */
601	uint64_t u4Reserved : 4;
602	/** Big page (must be 0 here). */
603	uint64_t u1Size : 1;
604	/** Available for software. */
605	uint64_t u4Available : 4;
606	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
607	uint64_t u40PhysAddr : 40;
608	/** Available for software. */
609	uint64_t u12Available : 12;
610	} EPTPDEBITS;
611	AssertCompileSize(EPTPDEBITS, 8);
612
613	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
614	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
615	/** The page shift to get the PD index. */
616	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
617	/** The PD index mask (apply to a shifted page address). */
618	#define EPT_PD_MASK X86_PD_PAE_MASK
619
620	/**
621	* EPT 2MB Page Directory Table Entry. Bit view.
622	*/
623	typedef struct EPTPDE2MBITS
624	{
625	/** Present bit. */
626	uint64_t u1Present : 1;
627	/** Writable bit. */
628	uint64_t u1Write : 1;
629	/** Executable bit. */
630	uint64_t u1Execute : 1;
631	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
632	uint64_t u3EMT : 3;
633	/** Ignore PAT memory type */
634	uint64_t u1IgnorePAT : 1;
635	/** Big page (must be 1 here). */
636	uint64_t u1Size : 1;
637	/** Available for software. */
638	uint64_t u4Available : 4;
639	/** Reserved (must be 0). */
640	uint64_t u9Reserved : 9;
641	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
642	uint64_t u31PhysAddr : 31;
643	/** Available for software. */
644	uint64_t u12Available : 12;
645	} EPTPDE2MBITS;
646	AssertCompileSize(EPTPDE2MBITS, 8);
647
648	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
649	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
650
651	/**
652	* EPT Page Directory Table Entry.
653	*/
654	typedef union EPTPDE
655	{
656	/** Normal view. */
657	EPTPDEBITS n;
658	/** 2MB view (big). */
659	EPTPDE2MBITS b;
660	/** Unsigned integer view. */
661	X86PGPAEUINT u;
662	/** 64 bit unsigned integer view. */
663	uint64_t au64[1];
664	/** 32 bit unsigned integer view. */
665	uint32_t au32[2];
666	} EPTPDE;
667	AssertCompileSize(EPTPDE, 8);
668	/** Pointer to an EPT Page Directory Table Entry. */
669	typedef EPTPDE *PEPTPDE;
670	/** Pointer to a const EPT Page Directory Table Entry. */
671	typedef const EPTPDE *PCEPTPDE;
672
673	/**
674	* EPT Page Directory Table.
675	*/
676	typedef struct EPTPD
677	{
678	EPTPDE a[EPT_PG_ENTRIES];
679	} EPTPD;
680	AssertCompileSize(EPTPD, 0x1000);
681	/** Pointer to an EPT Page Directory Table. */
682	typedef EPTPD *PEPTPD;
683	/** Pointer to a const EPT Page Directory Table. */
684	typedef const EPTPD *PCEPTPD;
685
686	/**
687	* EPT Page Table Entry. Bit view.
688	*/
689	typedef struct EPTPTEBITS
690	{
691	/** 0 - Present bit.
692	* @remarks This is a convenience "misnomer". The bit actually indicates read access
693	* and the CPU will consider an entry with any of the first three bits set
694	* as present. Since all our valid entries will have this bit set, it can
695	* be used as a present indicator and allow some code sharing. */
696	uint64_t u1Present : 1;
697	/** 1 - Writable bit. */
698	uint64_t u1Write : 1;
699	/** 2 - Executable bit. */
700	uint64_t u1Execute : 1;
701	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
702	uint64_t u3EMT : 3;
703	/** 6 - Ignore PAT memory type */
704	uint64_t u1IgnorePAT : 1;
705	/** 11:7 - Available for software. */
706	uint64_t u5Available : 5;
707	/** 51:12 - Physical address of page. Restricted by maximum physical
708	* address width of the cpu. */
709	uint64_t u40PhysAddr : 40;
710	/** 63:52 - Available for software. */
711	uint64_t u12Available : 12;
712	} EPTPTEBITS;
713	AssertCompileSize(EPTPTEBITS, 8);
714
715	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
716	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
717	/** The page shift to get the EPT PTE index. */
718	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
719	/** The EPT PT index mask (apply to a shifted page address). */
720	#define EPT_PT_MASK X86_PT_PAE_MASK
721
722	/**
723	* EPT Page Table Entry.
724	*/
725	typedef union EPTPTE
726	{
727	/** Normal view. */
728	EPTPTEBITS n;
729	/** Unsigned integer view. */
730	X86PGPAEUINT u;
731	/** 64 bit unsigned integer view. */
732	uint64_t au64[1];
733	/** 32 bit unsigned integer view. */
734	uint32_t au32[2];
735	} EPTPTE;
736	AssertCompileSize(EPTPTE, 8);
737	/** Pointer to an EPT Page Directory Table Entry. */
738	typedef EPTPTE *PEPTPTE;
739	/** Pointer to a const EPT Page Directory Table Entry. */
740	typedef const EPTPTE *PCEPTPTE;
741
742	/**
743	* EPT Page Table.
744	*/
745	typedef struct EPTPT
746	{
747	EPTPTE a[EPT_PG_ENTRIES];
748	} EPTPT;
749	AssertCompileSize(EPTPT, 0x1000);
750	/** Pointer to an extended page table. */
751	typedef EPTPT *PEPTPT;
752	/** Pointer to a const extended table. */
753	typedef const EPTPT *PCEPTPT;
754
755	/** @} */
756
757	/**
758	* VMX VPID flush types.
759	* @note Valid enum members are in accordance to the VT-x spec.
760	*/
761	typedef enum
762	{
763	/** Invalidate a specific page. */
764	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
765	/** Invalidate one context (specific VPID). */
766	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
767	/** Invalidate all contexts (all VPIDs). */
768	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
769	/** Invalidate a single VPID context retaining global mappings. */
770	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
771	/** Unsupported by VirtualBox. */
772	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
773	/** Unsupported by CPU. */
774	VMXTLBFLUSHVPID_NONE = 0xbad1
775	} VMXTLBFLUSHVPID;
776	AssertCompileSize(VMXTLBFLUSHVPID, 4);
777
778	/**
779	* VMX EPT flush types.
780	* @note Valid enums values are in accordance to the VT-x spec.
781	*/
782	typedef enum
783	{
784	/** Invalidate one context (specific EPT). */
785	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
786	/* Invalidate all contexts (all EPTs) */
787	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
788	/** Unsupported by VirtualBox. */
789	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
790	/** Unsupported by CPU. */
791	VMXTLBFLUSHEPT_NONE = 0xbad1
792	} VMXTLBFLUSHEPT;
793	AssertCompileSize(VMXTLBFLUSHEPT, 4);
794
795	/**
796	* VMX Posted Interrupt Descriptor.
797	* In accordance to the VT-x spec.
798	*/
799	typedef struct VMXPOSTEDINTRDESC
800	{
801	uint32_t aVectorBitmap[8];
802	uint32_t fOutstandingNotification : 1;
803	uint32_t uReserved0 : 31;
804	uint8_t au8Reserved0[28];
805	} VMXPOSTEDINTRDESC;
806	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
807	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
808	/** Pointer to a posted interrupt descriptor. */
809	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
810	/** Pointer to a const posted interrupt descriptor. */
811	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
812
813	/**
814	* VMX VMCS revision identifier.
815	*/
816	typedef union
817	{
818	struct
819	{
820	/** Revision identifier. */
821	uint32_t u31RevisionId : 31;
822	/** Whether this is a shadow VMCS. */
823	uint32_t fIsShadowVmcs : 1;
824	} n;
825	/* The unsigned integer view. */
826	uint32_t u;
827	} VMXVMCSREVID;
828	AssertCompileSize(VMXVMCSREVID, 4);
829	/** Pointer to the VMXVMCSREVID union. */
830	typedef VMXVMCSREVID *PVMXVMCSREVID;
831	/** Pointer to a const VMXVVMCSREVID union. */
832	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
833
834	/**
835	* VMX VM-exit instruction information.
836	*/
837	typedef union
838	{
839	/** Plain unsigned int representation. */
840	uint32_t u;
841	/** INS and OUTS information. */
842	struct
843	{
844	uint32_t u7Reserved0 : 7;
845	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
846	uint32_t u3AddrSize : 3;
847	uint32_t u5Reserved1 : 5;
848	/** The segment register (X86_SREG_XXX). */
849	uint32_t iSegReg : 3;
850	uint32_t uReserved2 : 14;
851	} StrIo;
852	struct
853	{
854	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
855	uint32_t u2Scaling : 2;
856	uint32_t u5Undef0 : 5;
857	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
858	uint32_t u3AddrSize : 3;
859	/** Cleared to 0. */
860	uint32_t u1Cleared0 : 1;
861	uint32_t u4Undef0 : 4;
862	/** The segment register (X86_SREG_XXX). */
863	uint32_t iSegReg : 3;
864	/** The index register (X86_GREG_XXX). */
865	uint32_t iIdxReg : 4;
866	/** Set if index register is invalid. */
867	uint32_t fIdxRegInvalid : 1;
868	/** The base register (X86_GREG_XXX). */
869	uint32_t iBaseReg : 4;
870	/** Set if base register is invalid. */
871	uint32_t fBaseRegInvalid : 1;
872	/** Register 2 (X86_GREG_XXX). */
873	uint32_t iReg2 : 4;
874	} Inv;
875	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
876	struct
877	{
878	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
879	uint32_t u2Scaling : 2;
880	uint32_t u5Reserved0 : 5;
881	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
882	uint32_t u3AddrSize : 3;
883	/** Cleared to 0. */
884	uint32_t u1Cleared0 : 1;
885	uint32_t u4Reserved0 : 4;
886	/** The segment register (X86_SREG_XXX). */
887	uint32_t iSegReg : 3;
888	/** The index register (X86_GREG_XXX). */
889	uint32_t iIdxReg : 4;
890	/** Set if index register is invalid. */
891	uint32_t fIdxRegInvalid : 1;
892	/** The base register (X86_GREG_XXX). */
893	uint32_t iBaseReg : 4;
894	/** Set if base register is invalid. */
895	uint32_t fBaseRegInvalid : 1;
896	/** Register 2 (X86_GREG_XXX). */
897	uint32_t iReg2 : 4;
898	} VmxXsave;
899	/** LIDT, LGDT, SIDT, SGDT information. */
900	struct
901	{
902	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
903	uint32_t u2Scaling : 2;
904	uint32_t u5Undef0 : 5;
905	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
906	uint32_t u3AddrSize : 3;
907	/** Always cleared to 0. */
908	uint32_t u1Cleared0 : 1;
909	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
910	uint32_t uOperandSize : 1;
911	uint32_t u3Undef0 : 3;
912	/** The segment register (X86_SREG_XXX). */
913	uint32_t iSegReg : 3;
914	/** The index register (X86_GREG_XXX). */
915	uint32_t iIdxReg : 4;
916	/** Set if index register is invalid. */
917	uint32_t fIdxRegInvalid : 1;
918	/** The base register (X86_GREG_XXX). */
919	uint32_t iBaseReg : 4;
920	/** Set if base register is invalid. */
921	uint32_t fBaseRegInvalid : 1;
922	/** Instruction identity (VMX_INSTR_ID_XXX). */
923	uint32_t u2InstrId : 2;
924	uint32_t u2Undef0 : 2;
925	} GdtIdt;
926	/** LLDT, LTR, SLDT, STR information. */
927	struct
928	{
929	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
930	uint32_t u2Scaling : 2;
931	uint32_t u1Undef0 : 1;
932	/** Register 1 (X86_GREG_XXX). */
933	uint32_t iReg1 : 4;
934	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
935	uint32_t u3AddrSize : 3;
936	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
937	uint32_t fIsRegOperand : 1;
938	uint32_t u4Undef0 : 4;
939	/** The segment register (X86_SREG_XXX). */
940	uint32_t iSegReg : 3;
941	/** The index register (X86_GREG_XXX). */
942	uint32_t iIdxReg : 4;
943	/** Set if index register is invalid. */
944	uint32_t fIdxRegInvalid : 1;
945	/** The base register (X86_GREG_XXX). */
946	uint32_t iBaseReg : 4;
947	/** Set if base register is invalid. */
948	uint32_t fBaseRegInvalid : 1;
949	/** Instruction identity (VMX_INSTR_ID_XXX). */
950	uint32_t u2InstrId : 2;
951	uint32_t u2Undef0 : 2;
952	} LdtTr;
953	/** RDRAND, RDSEED information. */
954	struct
955	{
956	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
957	uint32_t u2Undef0 : 2;
958	/** Destination register (X86_GREG_XXX). */
959	uint32_t iReg1 : 4;
960	uint32_t u4Undef0 : 4;
961	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
962	uint32_t u2OperandSize : 2;
963	uint32_t u19Def0 : 20;
964	} RdrandRdseed;
965	struct
966	{
967	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
968	uint32_t u2Scaling : 2;
969	uint32_t u1Undef0 : 1;
970	/** Register 1 (X86_GREG_XXX). */
971	uint32_t iReg1 : 4;
972	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
973	uint32_t u3AddrSize : 3;
974	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
975	uint32_t fIsRegOperand : 1;
976	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
977	uint32_t u4Undef0 : 4;
978	/** The segment register (X86_SREG_XXX). */
979	uint32_t iSegReg : 3;
980	/** The index register (X86_GREG_XXX). */
981	uint32_t iIdxReg : 4;
982	/** Set if index register is invalid. */
983	uint32_t fIdxRegInvalid : 1;
984	/** The base register (X86_GREG_XXX). */
985	uint32_t iBaseReg : 4;
986	/** Set if base register is invalid. */
987	uint32_t fBaseRegInvalid : 1;
988	/** Register 2 (X86_GREG_XXX). */
989	uint32_t iReg2 : 4;
990	} VmreadVmwrite;
991	/** This is a combination field of all instruction information. Note! Not all field
992	* combinations are valid (e.g., iReg1 is undefined for memory operands). */
993	struct
994	{
995	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
996	uint32_t u2Scaling : 2;
997	uint32_t u1Undef0 : 1;
998	/** Register 1 (X86_GREG_XXX). */
999	uint32_t iReg1 : 4;
1000	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1001	uint32_t u3AddrSize : 3;
1002	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1003	uint32_t fIsRegOperand : 1;
1004	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1005	uint32_t uOperandSize : 2;
1006	uint32_t u2Undef0 : 2;
1007	/** The segment register (X86_SREG_XXX). */
1008	uint32_t iSegReg : 3;
1009	/** The index register (X86_GREG_XXX). */
1010	uint32_t iIdxReg : 4;
1011	/** Set if index register is invalid. */
1012	uint32_t fIdxRegInvalid : 1;
1013	/** The base register (X86_GREG_XXX). */
1014	uint32_t iBaseReg : 4;
1015	/** Set if base register is invalid. */
1016	uint32_t fBaseRegInvalid : 1;
1017	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1018	uint32_t iReg2 : 4;
1019	} All;
1020	} VMXEXITINSTRINFO;
1021	AssertCompileSize(VMXEXITINSTRINFO, 4);
1022	/** Pointer to a VMX VM-exit instruction info. struct. */
1023	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1024	/** Pointer to a const VMX VM-exit instruction info. struct. */
1025	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1026
1027	/**
1028	* VMX MSR autoload/store element.
1029	* In accordance to the VT-x spec.
1030	*/
1031	typedef struct VMXAUTOMSR
1032	{
1033	/** The MSR Id. */
1034	uint32_t u32Msr;
1035	/** Reserved (MBZ). */
1036	uint32_t u32Reserved;
1037	/** The MSR value. */
1038	uint64_t u64Value;
1039	} VMXAUTOMSR;
1040	AssertCompileSize(VMXAUTOMSR, 16);
1041	/** Pointer to an MSR load/store element. */
1042	typedef VMXAUTOMSR *PVMXAUTOMSR;
1043	/** Pointer to a const MSR load/store element. */
1044	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1045
1046	/**
1047	* VMX tagged-TLB flush types.
1048	*/
1049	typedef enum
1050	{
1051	VMXTLBFLUSHTYPE_EPT,
1052	VMXTLBFLUSHTYPE_VPID,
1053	VMXTLBFLUSHTYPE_EPT_VPID,
1054	VMXTLBFLUSHTYPE_NONE
1055	} VMXTLBFLUSHTYPE;
1056	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1057	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1058	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1059	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1060
1061	/**
1062	* VMX controls MSR.
1063	*/
1064	typedef union
1065	{
1066	struct
1067	{
1068	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1069	uint32_t disallowed0;
1070	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1071	* controls. */
1072	uint32_t allowed1;
1073	} n;
1074	uint64_t u;
1075	} VMXCTLSMSR;
1076	AssertCompileSize(VMXCTLSMSR, 8);
1077	/** Pointer to a VMXCTLSMSR union. */
1078	typedef VMXCTLSMSR *PVMXCTLSMSR;
1079	/** Pointer to a const VMXCTLSMSR union. */
1080	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1081
1082	/**
1083	* VMX MSRs.
1084	* @remarks Although treated as a plain-old data (POD) in several places, please
1085	* update HMVmxGetHostMsr() if new MSRs are added here.
1086	*/
1087	typedef struct VMXMSRS
1088	{
1089	uint64_t u64FeatCtrl;
1090	uint64_t u64Basic;
1091	VMXCTLSMSR PinCtls;
1092	VMXCTLSMSR ProcCtls;
1093	VMXCTLSMSR ProcCtls2;
1094	VMXCTLSMSR ExitCtls;
1095	VMXCTLSMSR EntryCtls;
1096	VMXCTLSMSR TruePinCtls;
1097	VMXCTLSMSR TrueProcCtls;
1098	VMXCTLSMSR TrueEntryCtls;
1099	VMXCTLSMSR TrueExitCtls;
1100	uint64_t u64Misc;
1101	uint64_t u64Cr0Fixed0;
1102	uint64_t u64Cr0Fixed1;
1103	uint64_t u64Cr4Fixed0;
1104	uint64_t u64Cr4Fixed1;
1105	uint64_t u64VmcsEnum;
1106	uint64_t u64VmFunc;
1107	uint64_t u64EptVpidCaps;
1108	uint64_t a_u64Reserved[2];
1109	} VMXMSRS;
1110	AssertCompileSizeAlignment(VMXMSRS, 8);
1111	AssertCompileSize(VMXMSRS, 168);
1112	/** Pointer to a VMXMSRS struct. */
1113	typedef VMXMSRS *PVMXMSRS;
1114	/** Pointer to a const VMXMSRS struct. */
1115	typedef const VMXMSRS *PCVMXMSRS;
1116
1117
1118	/** @name VMX Basic Exit Reasons.
1119	* @{
1120	*/
1121	/** -1 Invalid exit code */
1122	#define VMX_EXIT_INVALID (-1)
1123	/** 0 Exception or non-maskable interrupt (NMI). */
1124	#define VMX_EXIT_XCPT_OR_NMI 0
1125	/** 1 External interrupt. */
1126	#define VMX_EXIT_EXT_INT 1
1127	/** 2 Triple fault. */
1128	#define VMX_EXIT_TRIPLE_FAULT 2
1129	/** 3 INIT signal. */
1130	#define VMX_EXIT_INIT_SIGNAL 3
1131	/** 4 Start-up IPI (SIPI). */
1132	#define VMX_EXIT_SIPI 4
1133	/** 5 I/O system-management interrupt (SMI). */
1134	#define VMX_EXIT_IO_SMI 5
1135	/** 6 Other SMI. */
1136	#define VMX_EXIT_SMI 6
1137	/** 7 Interrupt window exiting. */
1138	#define VMX_EXIT_INT_WINDOW 7
1139	/** 8 NMI window exiting. */
1140	#define VMX_EXIT_NMI_WINDOW 8
1141	/** 9 Task switch. */
1142	#define VMX_EXIT_TASK_SWITCH 9
1143	/** 10 Guest software attempted to execute CPUID. */
1144	#define VMX_EXIT_CPUID 10
1145	/** 11 Guest software attempted to execute GETSEC. */
1146	#define VMX_EXIT_GETSEC 11
1147	/** 12 Guest software attempted to execute HLT. */
1148	#define VMX_EXIT_HLT 12
1149	/** 13 Guest software attempted to execute INVD. */
1150	#define VMX_EXIT_INVD 13
1151	/** 14 Guest software attempted to execute INVLPG. */
1152	#define VMX_EXIT_INVLPG 14
1153	/** 15 Guest software attempted to execute RDPMC. */
1154	#define VMX_EXIT_RDPMC 15
1155	/** 16 Guest software attempted to execute RDTSC. */
1156	#define VMX_EXIT_RDTSC 16
1157	/** 17 Guest software attempted to execute RSM in SMM. */
1158	#define VMX_EXIT_RSM 17
1159	/** 18 Guest software executed VMCALL. */
1160	#define VMX_EXIT_VMCALL 18
1161	/** 19 Guest software executed VMCLEAR. */
1162	#define VMX_EXIT_VMCLEAR 19
1163	/** 20 Guest software executed VMLAUNCH. */
1164	#define VMX_EXIT_VMLAUNCH 20
1165	/** 21 Guest software executed VMPTRLD. */
1166	#define VMX_EXIT_VMPTRLD 21
1167	/** 22 Guest software executed VMPTRST. */
1168	#define VMX_EXIT_VMPTRST 22
1169	/** 23 Guest software executed VMREAD. */
1170	#define VMX_EXIT_VMREAD 23
1171	/** 24 Guest software executed VMRESUME. */
1172	#define VMX_EXIT_VMRESUME 24
1173	/** 25 Guest software executed VMWRITE. */
1174	#define VMX_EXIT_VMWRITE 25
1175	/** 26 Guest software executed VMXOFF. */
1176	#define VMX_EXIT_VMXOFF 26
1177	/** 27 Guest software executed VMXON. */
1178	#define VMX_EXIT_VMXON 27
1179	/** 28 Control-register accesses. */
1180	#define VMX_EXIT_MOV_CRX 28
1181	/** 29 Debug-register accesses. */
1182	#define VMX_EXIT_MOV_DRX 29
1183	/** 30 I/O instruction. */
1184	#define VMX_EXIT_IO_INSTR 30
1185	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1186	#define VMX_EXIT_RDMSR 31
1187	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1188	#define VMX_EXIT_WRMSR 32
1189	/** 33 VM-entry failure due to invalid guest state. */
1190	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1191	/** 34 VM-entry failure due to MSR loading. */
1192	#define VMX_EXIT_ERR_MSR_LOAD 34
1193	/** 36 Guest software executed MWAIT. */
1194	#define VMX_EXIT_MWAIT 36
1195	/** 37 VM-exit due to monitor trap flag. */
1196	#define VMX_EXIT_MTF 37
1197	/** 39 Guest software attempted to execute MONITOR. */
1198	#define VMX_EXIT_MONITOR 39
1199	/** 40 Guest software attempted to execute PAUSE. */
1200	#define VMX_EXIT_PAUSE 40
1201	/** 41 VM-entry failure due to machine-check. */
1202	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1203	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1204	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1205	/** 44 APIC access. Guest software attempted to access memory at a physical
1206	* address on the APIC-access page. */
1207	#define VMX_EXIT_APIC_ACCESS 44
1208	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1209	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1210	#define VMX_EXIT_VIRTUALIZED_EOI 45
1211	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1212	* SGDT, or SIDT. */
1213	#define VMX_EXIT_XDTR_ACCESS 46
1214	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1215	* SLDT, or STR. */
1216	#define VMX_EXIT_TR_ACCESS 47
1217	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1218	* was disallowed by the configuration of the EPT paging structures. */
1219	#define VMX_EXIT_EPT_VIOLATION 48
1220	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1221	* address encountered a misconfigured EPT paging-structure entry. */
1222	#define VMX_EXIT_EPT_MISCONFIG 49
1223	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1224	#define VMX_EXIT_INVEPT 50
1225	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1226	#define VMX_EXIT_RDTSCP 51
1227	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1228	#define VMX_EXIT_PREEMPT_TIMER 52
1229	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1230	#define VMX_EXIT_INVVPID 53
1231	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1232	#define VMX_EXIT_WBINVD 54
1233	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1234	#define VMX_EXIT_XSETBV 55
1235	/** 56 APIC write. Guest completed write to virtual-APIC. */
1236	#define VMX_EXIT_APIC_WRITE 56
1237	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1238	#define VMX_EXIT_RDRAND 57
1239	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1240	#define VMX_EXIT_INVPCID 58
1241	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1242	#define VMX_EXIT_VMFUNC 59
1243	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1244	#define VMX_EXIT_ENCLS 60
1245	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1246	* enabled. */
1247	#define VMX_EXIT_RDSEED 61
1248	/** 62 - Page-modification log full. */
1249	#define VMX_EXIT_PML_FULL 62
1250	/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
1251	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1252	#define VMX_EXIT_XSAVES 63
1253	/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
1254	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1255	#define VMX_EXIT_XRSTORS 64
1256	/** The maximum exit value (inclusive). */
1257	#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
1258	/** @} */
1259
1260
1261	/** @name VM Instruction Errors.
1262	* See Intel spec. "30.4 VM Instruction Error Numbers"
1263	* @{
1264	*/
1265	typedef enum
1266	{
1267	/** VMCALL executed in VMX root operation. */
1268	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1269	/** VMCLEAR with invalid physical address. */
1270	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1271	/** VMCLEAR with VMXON pointer. */
1272	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1273	/** VMLAUNCH with non-clear VMCS. */
1274	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1275	/** VMRESUME with non-launched VMCS. */
1276	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1277	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1278	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1279	/** VM-entry with invalid control field(s). */
1280	VMXINSTRERR_VMENTRY_INVALID_CTL = 7,
1281	/** VM-entry with invalid host-state field(s). */
1282	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1283	/** VMPTRLD with invalid physical address. */
1284	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1285	/** VMPTRLD with VMXON pointer. */
1286	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1287	/** VMPTRLD with incorrect VMCS revision identifier. */
1288	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1289	/** VMREAD from unsupported VMCS component. */
1290	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1291	/** VMWRITE to unsupported VMCS component. */
1292	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1293	/** VMWRITE to read-only VMCS component. */
1294	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1295	/** VMXON executed in VMX root operation. */
1296	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1297	/** VM-entry with invalid executive-VMCS pointer. */
1298	VMXINSTRERR_VMENTRY_INVALID_VMCS_PTR = 16,
1299	/** VM-entry with non-launched executive VMCS. */
1300	VMXINSTRERR_VMENTRY_NON_LAUNCHED_VMCS = 17,
1301	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1302	VMXINSTRERR_VMENTRY_VMCS_PTR = 18,
1303	/** VMCALL with non-clear VMCS. */
1304	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1305	/** VMCALL with invalid VM-exit control fields. */
1306	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1307	/** VMCALL with incorrect MSEG revision identifier. */
1308	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1309	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1310	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1311	/** VMCALL with invalid SMM-monitor features. */
1312	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1313	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1314	VMXINSTRERR_VMENTRY_INVALID_EXECTLS = 25,
1315	/** VM-entry with events blocked by MOV SS. */
1316	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1317	/** Invalid operand to INVEPT/INVVPID. */
1318	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1319	} VMXINSTRERR;
1320	/** @} */
1321
1322
1323	/** @name VMX MSR - Basic VMX information.
1324	* @{
1325	*/
1326	/** VMCS (and related regions) memory type - Uncacheable. */
1327	#define VMX_BASIC_MEM_TYPE_UC 0
1328	/** VMCS (and related regions) memory type - Write back. */
1329	#define VMX_BASIC_MEM_TYPE_WB 6
1330
1331	/** Bit fields for MSR_IA32_VMX_BASIC. */
1332	/** VMCS revision identifier used by the processor. */
1333	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1334	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1335	/** Bit 31 is reserved and RAZ. */
1336	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1337	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1338	/** VMCS size in bytes. */
1339	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1340	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1341	/** Bits 45:47 are reserved. */
1342	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1343	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1344	/** Width of physical addresses used for the VMCS and associated memory regions
1345	* (always 0 on CPUs that support Intel 64 architecture). */
1346	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1347	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1348	/** Dual-monitor treatment of SMI and SMM supported. */
1349	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1350	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1351	/** Memory type that must be used for the VMCS and associated memory regions. */
1352	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1353	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1354	/** VM-exit instruction information for INS/OUTS. */
1355	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1356	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1357	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1358	* bits in VMX control MSRs. */
1359	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1360	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1361	/** Bits 56:63 are reserved and RAZ. */
1362	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 56
1363	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xff00000000000000)
1364	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1365	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1366	VMCS_INS_OUTS, TRUE_CTLS, RSVD_56_63));
1367	/** @} */
1368
1369
1370	/** @name VMX MSR - Miscellaneous data.
1371	* Bit fields for MSR_IA32_VMX_MISC.
1372	* @{
1373	*/
1374	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1375	#define VMX_MISC_EXIT_STORE_EFER_LMA RT_BIT(5)
1376	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1377	* VMWRITE cannot modify read-only VM-exit information fields. */
1378	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1379	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1380	* instructions. */
1381	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1382	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1383	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1384	/** Maximum CR3-target count supported by the CPU. */
1385	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1386	/** Relationship between the preemption timer and tsc. */
1387	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1388	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1389	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1390	#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_SHIFT 5
1391	#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1392	/** Activity states supported by the implementation. */
1393	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1394	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1395	/** Bits 9:13 is reserved and RAZ. */
1396	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1397	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1398	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1399	#define VMX_BF_MISC_PT_SHIFT 14
1400	#define VMX_BF_MISC_PT_MASK UINT64_C(0x0000000000004000)
1401	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1402	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1403	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1404	/** Number of CR3 target values supported by the processor. (0-256) */
1405	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1406	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1407	/** Maximum number of MSRs in the VMCS. */
1408	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1409	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1410	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1411	* SMIs. */
1412	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1413	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1414	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1415	* VMWRITE cannot modify read-only VM-exit information fields. */
1416	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1417	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1418	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1419	* instructions. */
1420	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1421	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1422	/** Bit 31 is reserved and RAZ. */
1423	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1424	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1425	/** 32-bit MSEG revision ID used by the processor. */
1426	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1427	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1428	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1429	(PREEMPT_TIMER_TSC, EXIT_STORE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, PT, SMM_READ_SMBASE_MSR,
1430	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1431	/** @} */
1432
1433	/** Maximum number of CR3 target supported by VT-x */
1434	#define VMX_VMCS_CTRL_CR3_TARGET_COUNT_MAX 4
1435
1436	/** @name VMX MSR - VMCS enumeration.
1437	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1438	* @{
1439	*/
1440	/** Bit 0 is reserved and RAZ. */
1441	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1442	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1443	/** Highest index value used in VMCS field encoding. */
1444	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1445	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1446	/** Bit 10:63 is reserved and RAZ. */
1447	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1448	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1449	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1450	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1451	/** @} */
1452
1453
1454	/** @name VMX MSR - VM Functions.
1455	* Bit fields for MSR_IA32_VMX_VMFUNC.
1456	* @{
1457	*/
1458	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1459	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1460	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1461	/** Bits 1:63 are reserved and RAZ. */
1462	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1463	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1464	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1465	(EPTP_SWITCHING, RSVD_1_63));
1466	/** @} */
1467
1468
1469	/** @name VMX MSR - EPT/VPID capabilities.
1470	* @{
1471	*/
1472	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1473	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1474	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1475	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1476	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1477	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1478	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1479	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1480	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1481	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1482	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1483	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1484	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1485	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1486	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1487	/** @} */
1488
1489
1490	/** @name Extended Page Table Pointer (EPTP)
1491	* @{
1492	*/
1493	/** Uncachable EPT paging structure memory type. */
1494	#define VMX_EPT_MEMTYPE_UC 0
1495	/** Write-back EPT paging structure memory type. */
1496	#define VMX_EPT_MEMTYPE_WB 6
1497	/** Shift value to get the EPT page walk length (bits 5-3) */
1498	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1499	/** Mask value to get the EPT page walk length (bits 5-3) */
1500	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1501	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1502	* length) */
1503	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1504	/** @} */
1505
1506
1507	/** @name VMCS field encoding: 16-bit guest fields.
1508	* @{
1509	*/
1510	#define VMX_VMCS16_VPID 0x0000
1511	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1512	#define VMX_VMCS16_EPTP_INDEX 0x0004
1513	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1514	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1515	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1516	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1517	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1518	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1519	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1520	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1521	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1522	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1523	/** @} */
1524
1525
1526	/** @name VMCS field encoding: 16-bits host fields.
1527	* @{
1528	*/
1529	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1530	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1531	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1532	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1533	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1534	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1535	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1536	/** @} */
1537
1538
1539	/** @name VMCS field encoding: 64-bit control fields.
1540	* @{
1541	*/
1542	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1543	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1544	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1545	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1546	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1547	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1548	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1549	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1550	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1551	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1552	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1553	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1554	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1555	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1556	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1557	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1558	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1559	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1560	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1561	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1562	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1563	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1564	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1565	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1566	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1567	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1568	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1569	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1570	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1571	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1572	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1573	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1574	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1575	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1576	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1577	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1578	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1579	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1580	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1581	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1582	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1583	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1584	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1585	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1586	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1587	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1588	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1589	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1590	/** @} */
1591
1592
1593	/** @name VMCS field encoding: 64-bit read-only data fields.
1594	* @{
1595	*/
1596	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1597	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1598	/** @} */
1599
1600
1601	/** @name VMCS field encoding: 64-bit guest fields.
1602	* @{
1603	*/
1604	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1605	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1606	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1607	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1608	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1609	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1610	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1611	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1612	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1613	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1614	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1615	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1616	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1617	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1618	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1619	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1620	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1621	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1622	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1623	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1624	/** @} */
1625
1626
1627	/** @name VMCS field encoding: 64-bit host fields.
1628	* @{
1629	*/
1630	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1631	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1632	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1633	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1634	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1635	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1636	/** @} */
1637
1638
1639	/** @name VMCS field encoding: 32-bit control fields.
1640	* @{
1641	*/
1642	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1643	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1644	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1645	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1646	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1647	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1648	#define VMX_VMCS32_CTRL_EXIT 0x400c
1649	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1650	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1651	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1652	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1653	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1654	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1655	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1656	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1657	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1658	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1659	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1660	/** @} */
1661
1662
1663	/** @name VMCS field encoding: 32-bits read-only fields.
1664	* @{
1665	*/
1666	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1667	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1668	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1669	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1670	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1671	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1672	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1673	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1674	/** @} */
1675
1676
1677	/** @name VMCS field encoding: 32-bit guest-state fields.
1678	* @{
1679	*/
1680	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1681	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1682	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1683	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1684	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1685	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1686	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1687	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1688	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1689	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1690	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1691	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1692	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1693	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1694	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1695	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1696	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1697	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1698	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1699	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1700	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1701	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
1702	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1703	/** @} */
1704
1705
1706	/** @name VMCS field encoding: 32-bit host-state fields.
1707	* @{
1708	*/
1709	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1710	/** @} */
1711
1712
1713	/** @name Natural width control fields.
1714	* @{
1715	*/
1716	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1717	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1718	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1719	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1720	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1721	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1722	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1723	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
1724	/** @} */
1725
1726
1727	/** @name Natural width read-only data fields.
1728	* @{
1729	*/
1730	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1731	#define VMX_VMCS_RO_IO_RCX 0x6402
1732	#define VMX_VMCS_RO_IO_RSX 0x6404
1733	#define VMX_VMCS_RO_IO_RDI 0x6406
1734	#define VMX_VMCS_RO_IO_RIP 0x6408
1735	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640a
1736	/** @} */
1737
1738
1739	/** @name VMCS field encoding: Natural width guest-state fields.
1740	* @{
1741	*/
1742	#define VMX_VMCS_GUEST_CR0 0x6800
1743	#define VMX_VMCS_GUEST_CR3 0x6802
1744	#define VMX_VMCS_GUEST_CR4 0x6804
1745	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1746	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1747	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1748	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1749	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1750	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1751	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1752	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1753	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1754	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1755	#define VMX_VMCS_GUEST_DR7 0x681a
1756	#define VMX_VMCS_GUEST_RSP 0x681c
1757	#define VMX_VMCS_GUEST_RIP 0x681e
1758	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1759	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
1760	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
1761	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
1762	/** @} */
1763
1764
1765	/** @name VMCS field encoding: Natural width host-state fields.
1766	* @{
1767	*/
1768	#define VMX_VMCS_HOST_CR0 0x6c00
1769	#define VMX_VMCS_HOST_CR3 0x6c02
1770	#define VMX_VMCS_HOST_CR4 0x6c04
1771	#define VMX_VMCS_HOST_FS_BASE 0x6c06
1772	#define VMX_VMCS_HOST_GS_BASE 0x6c08
1773	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
1774	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
1775	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
1776	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
1777	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
1778	#define VMX_VMCS_HOST_RSP 0x6c14
1779	#define VMX_VMCS_HOST_RIP 0x6c16
1780	/** @} */
1781
1782
1783	/** @name Pin-based VM-execution controls.
1784	* @{
1785	*/
1786	/** External interrupts cause VM-exits if set; otherwise dispatched through the
1787	* guest's IDT. */
1788	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
1789	/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through
1790	* the guest's IDT. */
1791	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
1792	/** Virtual NMIs. */
1793	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
1794	/** Activate VMX preemption timer. */
1795	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
1796	/** Process interrupts with the posted-interrupt notification vector. */
1797	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
1798	/** Default1 class when true capability MSRs are not supported. */
1799	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
1800
1801	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
1802	* controls field in the VMCS. */
1803	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
1804	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
1805	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
1806	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
1807	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
1808	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
1809	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
1810	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
1811	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
1812	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
1813	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
1814	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
1815	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
1816	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
1817	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
1818	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
1819	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
1820	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
1821	/** @} */
1822
1823
1824	/** @name Processor-based VM-execution controls.
1825	* @{
1826	*/
1827	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1828	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
1829	/** Use timestamp counter offset. */
1830	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
1831	/** VM-exit when executing the HLT instruction. */
1832	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
1833	/** VM-exit when executing the INVLPG instruction. */
1834	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
1835	/** VM-exit when executing the MWAIT instruction. */
1836	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
1837	/** VM-exit when executing the RDPMC instruction. */
1838	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
1839	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1840	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
1841	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
1842	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1843	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
1844	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
1845	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1846	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
1847	/** VM-exit on CR8 loads. */
1848	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
1849	/** VM-exit on CR8 stores. */
1850	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
1851	/** Use TPR shadow. */
1852	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
1853	/** VM-exit when virtual NMI blocking is disabled. */
1854	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
1855	/** VM-exit when executing a MOV DRx instruction. */
1856	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
1857	/** VM-exit when executing IO instructions. */
1858	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
1859	/** Use IO bitmaps. */
1860	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
1861	/** Monitor trap flag. */
1862	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
1863	/** Use MSR bitmaps. */
1864	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
1865	/** VM-exit when executing the MONITOR instruction. */
1866	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
1867	/** VM-exit when executing the PAUSE instruction. */
1868	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
1869	/** Whether the secondary processor based VM-execution controls are used. */
1870	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
1871	/** Default1 class when true-capability MSRs are not supported. */
1872	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
1873
1874	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
1875	* controls field in the VMCS. */
1876	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
1877	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
1878	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
1879	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
1880	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
1881	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
1882	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
1883	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
1884	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
1885	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
1886	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
1887	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
1888	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
1889	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
1890	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
1891	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
1892	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
1893	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
1894	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
1895	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
1896	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
1897	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
1898	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
1899	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
1900	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
1901	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
1902	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
1903	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
1904	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
1905	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
1906	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
1907	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
1908	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
1909	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
1910	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
1911	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
1912	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
1913	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
1914	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
1915	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
1916	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
1917	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
1918	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
1919	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
1920	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
1921	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
1922	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
1923	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
1924	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
1925	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
1926	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
1927	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
1928	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
1929	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
1930	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
1931	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
1932	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
1933	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
1934	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
1935	USE_SECONDARY_CTLS));
1936	/** @} */
1937
1938
1939	/** @name Secondary Processor-based VM-execution controls.
1940	* @{
1941	*/
1942	/** Virtualize APIC access. */
1943	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
1944	/** EPT supported/enabled. */
1945	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
1946	/** Descriptor table instructions cause VM-exits. */
1947	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
1948	/** RDTSCP supported/enabled. */
1949	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
1950	/** Virtualize x2APIC mode. */
1951	#define VMX_PROC_CTLS2_VIRT_X2APIC_ACCESS RT_BIT(4)
1952	/** VPID supported/enabled. */
1953	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
1954	/** VM-exit when executing the WBINVD instruction. */
1955	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
1956	/** Unrestricted guest execution. */
1957	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
1958	/** APIC register virtualization. */
1959	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
1960	/** Virtual-interrupt delivery. */
1961	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
1962	/** A specified number of pause loops cause a VM-exit. */
1963	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
1964	/** VM-exit when executing RDRAND instructions. */
1965	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
1966	/** Enables INVPCID instructions. */
1967	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
1968	/** Enables VMFUNC instructions. */
1969	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
1970	/** Enables VMCS shadowing. */
1971	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
1972	/** Enables ENCLS VM-exits. */
1973	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
1974	/** VM-exit when executing RDSEED. */
1975	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
1976	/** Enables page-modification logging. */
1977	#define VMX_PROC_CTLS2_PML RT_BIT(17)
1978	/** Controls whether EPT-violations may cause \#VE instead of exits. */
1979	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
1980	/** Conceal VMX non-root operation from Intel processor trace (PT). */
1981	#define VMX_PROC_CTLS2_CONCEAL_FROM_PT RT_BIT(19)
1982	/** Enables XSAVES/XRSTORS instructions. */
1983	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
1984	/** Use TSC scaling. */
1985	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
1986
1987	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
1988	* VM-execution controls field in the VMCS. */
1989	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
1990	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
1991	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
1992	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
1993	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
1994	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
1995	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
1996	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
1997	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_ACCESS_SHIFT 4
1998	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_ACCESS_MASK UINT32_C(0x00000010)
1999	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2000	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2001	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2002	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2003	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2004	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2005	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2006	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2007	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2008	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2009	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2010	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2011	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2012	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2013	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2014	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2015	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2016	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2017	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2018	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2019	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2020	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2021	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2022	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2023	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2024	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2025	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2026	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2027	#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_SHIFT 19
2028	#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_MASK UINT32_C(0x00080000)
2029	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2030	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2031	#define VMX_BF_PROC_CTLS2_UNDEF_21_24_SHIFT 21
2032	#define VMX_BF_PROC_CTLS2_UNDEF_21_24_MASK UINT32_C(0x01e00000)
2033	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2034	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2035	#define VMX_BF_PROC_CTLS2_UNDEF_26_31_SHIFT 26
2036	#define VMX_BF_PROC_CTLS2_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2037	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2038	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_ACCESS, VPID, WBINVD_EXIT,
2039	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2040	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_FROM_PT, XSAVES_XRSTORS, UNDEF_21_24,
2041	TSC_SCALING, UNDEF_26_31));
2042	/** @} */
2043
2044
2045	/** @name VM-entry controls.
2046	* @{
2047	*/
2048	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2049	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2050	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2051	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2052	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2053	/** In SMM mode after VM-entry. */
2054	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2055	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2056	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2057	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2058	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2059	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2060	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2061	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2062	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2063	/** Default1 class when true-capability MSRs are not supported. */
2064	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2065
2066	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2067	* VMCS. */
2068	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2069	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2070	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2071	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2072	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2073	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2074	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2075	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2076	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2077	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2078	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2079	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2080	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2081	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2082	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2083	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2084	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2085	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2086	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2087	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2088	#define VMX_BF_ENTRY_CTLS_UNDEF_16_31_SHIFT 16
2089	#define VMX_BF_ENTRY_CTLS_UNDEF_16_31_MASK UINT32_C(0xffff0000)
2090	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2091	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2092	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, UNDEF_16_31));
2093	/** @} */
2094
2095
2096	/** @name VM-exit controls.
2097	* @{
2098	*/
2099	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2100	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2101	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2102	/** Return to long mode after a VM-exit. */
2103	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2104	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2105	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2106	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2107	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2108	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2109	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2110	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2111	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2112	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2113	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2114	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2115	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2116	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2117	#define VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
2118	/** Default1 class when true-capability MSRs are not supported. */
2119	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2120
2121	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2122	* VMCS. */
2123	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2124	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2125	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2126	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2127	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2128	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2129	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2130	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2131	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2132	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2133	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2134	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2135	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2136	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2137	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2138	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2139	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2140	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2141	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2142	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2143	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2144	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2145	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2146	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2147	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2148	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2149	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2150	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2151	#define VMX_BF_EXIT_CTLS_UNDEF_23_31_SHIFT 23
2152	#define VMX_BF_EXIT_CTLS_UNDEF_23_31_MASK UINT32_C(0xff800000)
2153	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2154	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2155	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2156	SAVE_PREEMPT_TIMER, UNDEF_23_31));
2157	/** @} */
2158
2159
2160	/** @name VM-exit reason.
2161	* @{
2162	*/
2163	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2164	/** @} */
2165
2166
2167	/** @name VM-entry interruption information.
2168	* @{
2169	*/
2170	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2171	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2172	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2173	/** @} */
2174
2175
2176	/** @name VM-entry interruption information.
2177	* @{ */
2178	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2179	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2180	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2181	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2182	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2183	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2184	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2185	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2186	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2187	/** Construct an VM-entry interruption information field from a VM-exit interruption
2188	* info value (same except that bit 12 is reserved). */
2189	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2190	/** Construct a VM-entry interruption information field from an IDT-vectoring
2191	* information field (same except that bit 12 is reserved). */
2192	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2193
2194	/** Bit fields for VM-entry interruption information. */
2195	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2196	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2197	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2198	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2199	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2200	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2201	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2202	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2203	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2204	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2205	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2206	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2207	/** @} */
2208
2209
2210	/** @name VM-entry interruption information types.
2211	* @{
2212	*/
2213	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2214	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2215	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2216	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2217	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2218	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2219	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2220	/** @} */
2221
2222
2223	/** @name VM-exit interruption information.
2224	* @{
2225	*/
2226	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2227	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2228	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2229	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2230	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2231	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2232	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2233	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2234	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2235
2236	/** Bit fields for VM-exit interruption infomration. */
2237	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2238	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2239	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2240	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2241	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2242	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2243	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2244	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2245	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2246	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2247	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2248	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2249	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2250	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2251	/** @} */
2252
2253
2254	/** @name VM-exit interruption information types.
2255	* @{
2256	*/
2257	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2258	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2259	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2260	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2261	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2262	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2263	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2264	/** @} */
2265
2266
2267	/** @name VM-exit instruction identity.
2268	*
2269	* These are found in VM-exit instruction information fields for certain
2270	* instructions.
2271	* @{ */
2272	typedef uint8_t VMXINSTRID;
2273	#define VMX_INSTR_ID_VALID RT_BIT(7)
2274	#define VMX_INSTR_ID_IS_VALID(a) (((a) >> 7) & 1)
2275	#define VMX_INSTR_ID_GET_ID(a) ((a) & ~VMX_INSTR_ID_VALID)
2276	#define VMX_INSTR_ID_NONE 0x7f
2277	/** The following values are in accordance to the VT-x spec: */
2278	#define VMX_INSTR_ID_SGDT ((VMX_INSTR_ID_VALID) \| 0)
2279	#define VMX_INSTR_ID_SIDT ((VMX_INSTR_ID_VALID) \| 1)
2280	#define VMX_INSTR_ID_LGDT ((VMX_INSTR_ID_VALID) \| 2)
2281	#define VMX_INSTR_ID_LIDT ((VMX_INSTR_ID_VALID) \| 3)
2282
2283	#define VMX_INSTR_ID_SLDT ((VMX_INSTR_ID_VALID) \| 0)
2284	#define VMX_INSTR_ID_STR ((VMX_INSTR_ID_VALID) \| 1)
2285	#define VMX_INSTR_ID_LLDT ((VMX_INSTR_ID_VALID) \| 2)
2286	#define VMX_INSTR_ID_LTR ((VMX_INSTR_ID_VALID) \| 3)
2287	/** @} */
2288
2289
2290	/** @name IDT-vectoring information.
2291	* @{
2292	*/
2293	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2294	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2295	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2296	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2297
2298	/** Bit fields for IDT-vectoring information. */
2299	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2300	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2301	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2302	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2303	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2304	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2305	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2306	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2307	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2308	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2309	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2310	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2311	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2312	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2313	/** @} */
2314
2315
2316	/** @name IDT-vectoring information vector types.
2317	* @{
2318	*/
2319	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2320	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2321	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2322	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2323	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2324	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2325	#define VMX_IDT_VECTORING_INFO_TYPE_SW_UNUSED 7
2326	/** @} */
2327
2328
2329	/** @name Guest-activity states.
2330	* @{
2331	*/
2332	/** The logical processor is active. */
2333	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2334	/** The logical processor is inactive, because executed a HLT instruction. */
2335	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2336	/** The logical processor is inactive, because of a triple fault or other serious error. */
2337	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2338	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2339	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2340	/** @} */
2341
2342
2343	/** @name Guest-interruptibility states.
2344	* @{
2345	*/
2346	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2347	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2348	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2349	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2350	/** @} */
2351
2352
2353	/** @name Exit qualification for Mov DRx.
2354	* @{
2355	*/
2356	/** 0-2: Debug register number */
2357	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
2358	/** 3: Reserved; cleared to 0. */
2359	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
2360	/** 4: Direction of move (0 = write, 1 = read) */
2361	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
2362	/** 5-7: Reserved; cleared to 0. */
2363	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
2364	/** 8-11: General purpose register number. */
2365	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
2366	/** Rest: reserved. */
2367	/** @} */
2368
2369
2370	/** @name Exit qualification for debug exceptions types.
2371	* @{
2372	*/
2373	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
2374	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
2375	/** @} */
2376
2377
2378	/** @name Exit qualification for control-register accesses.
2379	* @{
2380	*/
2381	/** 0-3: Control register number (0 for CLTS & LMSW) */
2382	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
2383	/** 4-5: Access type. */
2384	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
2385	/** 6: LMSW operand type */
2386	#define VMX_EXIT_QUAL_CRX_LMSW_OP(a) (((a) >> 6) & 1)
2387	/** 7: Reserved; cleared to 0. */
2388	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
2389	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
2390	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
2391	/** 12-15: Reserved; cleared to 0. */
2392	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
2393	/** 16-31: LMSW source data (else 0). */
2394	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
2395	/* Rest: reserved. */
2396	/** @} */
2397
2398
2399	/** @name Exit qualification for control-register access types.
2400	* @{
2401	*/
2402	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
2403	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
2404	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
2405	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
2406	/** @} */
2407
2408
2409	/** @name Exit qualification for task switch.
2410	* @{
2411	*/
2412	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
2413	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
2414	/** Task switch caused by a call instruction. */
2415	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
2416	/** Task switch caused by an iret instruction. */
2417	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
2418	/** Task switch caused by a jmp instruction. */
2419	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
2420	/** Task switch caused by an interrupt gate. */
2421	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
2422	/** @} */
2423
2424
2425	/** @name Exit qualification for EPT violations.
2426	* @{
2427	*/
2428	/** Set if the violation was caused by a data read. */
2429	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
2430	/** Set if the violation was caused by a data write. */
2431	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
2432	/** Set if the violation was caused by an instruction fetch. */
2433	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
2434	/** AND of the present bit of all EPT structures. */
2435	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
2436	/** AND of the write bit of all EPT structures. */
2437	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
2438	/** AND of the execute bit of all EPT structures. */
2439	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
2440	/** Set if the guest linear address field contains the faulting address. */
2441	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
2442	/** If bit 7 is one: (reserved otherwise)
2443	* 1 - violation due to physical address access.
2444	* 0 - violation caused by page walk or access/dirty bit updates
2445	*/
2446	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
2447	/** @} */
2448
2449
2450	/** @name Exit qualification for I/O instructions.
2451	* @{
2452	*/
2453	/** 0-2: IO operation width. */
2454	#define VMX_EXIT_QUAL_IO_WIDTH(a) ((a) & 7)
2455	/** 3: IO operation direction. */
2456	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
2457	/** 4: String IO operation (INS / OUTS). */
2458	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
2459	/** 5: Repeated IO operation. */
2460	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
2461	/** 6: Operand encoding. */
2462	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
2463	/** 16-31: IO Port (0-0xffff). */
2464	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
2465	/* Rest reserved. */
2466	/** @} */
2467
2468
2469	/** @name Exit qualification for I/O instruction types.
2470	* @{
2471	*/
2472	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
2473	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
2474	/** @} */
2475
2476
2477	/** @name Exit qualification for I/O instruction encoding.
2478	* @{
2479	*/
2480	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
2481	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
2482	/** @} */
2483
2484
2485	/** @name Exit qualification for APIC-access VM-exits from linear and
2486	* guest-physical accesses.
2487	* @{
2488	*/
2489	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
2490	* access within the APIC page. */
2491	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
2492	/** 12-15: Access type. */
2493	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
2494	/* Rest reserved. */
2495	/** @} */
2496
2497
2498	/** @name Exit qualification for linear address APIC-access types.
2499	* @{
2500	*/
2501	/** Linear read access. */
2502	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
2503	/** Linear write access. */
2504	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
2505	/** Linear instruction fetch access. */
2506	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
2507	/** Linear read/write access during event delivery. */
2508	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
2509	/** Physical read/write access during event delivery. */
2510	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
2511	/** Physical access for an instruction fetch or during instruction execution. */
2512	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
2513	/** @} */
2514
2515
2516	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
2517	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
2518	* @{
2519	*/
2520	/** Address calculation scaling field (powers of two). */
2521	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
2522	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
2523	/** Bits 2 thru 6 are undefined. */
2524	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
2525	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
2526	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
2527	* @remarks anyone's guess why this is a 3 bit field... */
2528	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
2529	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
2530	/** Bit 10 is defined as zero. */
2531	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
2532	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
2533	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
2534	* for exits from 64-bit code as the operand size there is fixed. */
2535	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
2536	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
2537	/** Bits 12 thru 14 are undefined. */
2538	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
2539	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
2540	/** Applicable segment register (X86_SREG_XXX values). */
2541	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
2542	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
2543	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
2544	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
2545	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
2546	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
2547	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
2548	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
2549	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
2550	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
2551	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
2552	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2553	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
2554	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2555	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
2556	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
2557	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2558	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
2559	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
2560	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
2561	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
2562	/** Bits 30 & 31 are undefined. */
2563	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
2564	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
2565	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
2566	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
2567	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
2568	/** @} */
2569
2570
2571	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
2572	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
2573	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
2574	* @{
2575	*/
2576	/** Address calculation scaling field (powers of two). */
2577	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
2578	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
2579	/** Bit 2 is undefined. */
2580	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
2581	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
2582	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
2583	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
2584	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
2585	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
2586	* @remarks anyone's guess why this is a 3 bit field... */
2587	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
2588	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
2589	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
2590	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
2591	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
2592	/** Bits 11 thru 14 are undefined. */
2593	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
2594	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
2595	/** Applicable segment register (X86_SREG_XXX values). */
2596	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
2597	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
2598	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
2599	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
2600	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
2601	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
2602	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
2603	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
2604	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
2605	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
2606	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
2607	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2608	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
2609	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2610	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
2611	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
2612	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2613	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
2614	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
2615	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
2616	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
2617	/** Bits 30 & 31 are undefined. */
2618	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
2619	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
2620	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
2621	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
2622	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
2623	/** @} */
2624
2625
2626	/** @name Format of Pending-Debug-Exceptions.
2627	* Bits 4-11, 13, 15 and 17-63 are reserved.
2628	* @{
2629	*/
2630	/** Hardware breakpoint 0 was met. */
2631	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT(0)
2632	/** Hardware breakpoint 1 was met. */
2633	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT(1)
2634	/** Hardware breakpoint 2 was met. */
2635	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT(2)
2636	/** Hardware breakpoint 3 was met. */
2637	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT(3)
2638	/** At least one data or IO breakpoint was hit. */
2639	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT(12)
2640	/** A debug exception would have been triggered by single-step execution mode. */
2641	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT(14)
2642	/** A debug exception occurred inside an RTM region. */
2643	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT(16)
2644	/** @} */
2645
2646
2647	/** @name VMCS field encoding.
2648	* @{ */
2649	#define VMX_VMCS_ENC_GET_INDEX(a)
2650
2651	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_SHIFT 0
2652	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2653	#define VMX_BF_VMCS_ENC_INDEX_SHIFT 1
2654	#define VMX_BF_VMCS_ENC_INDEX_MASK UINT32_C(0x000003fe)
2655	#define VMX_BF_VMCS_ENC_TYPE_SHIFT 10
2656	#define VMX_BF_VMCS_ENC_TYPE_MASK UINT32_C(0x00000c00)
2657	#define VMX_BF_VMCS_ENC_RSVD_12_SHIFT 12
2658	#define VMX_BF_VMCS_ENC_RSVD_12_MASK UINT32_C(0x00001000)
2659	#define VMX_BF_VMCS_ENC_WIDTH_SHIFT 13
2660	#define VMX_BF_VMCS_ENC_WIDTH_MASK UINT32_C(0x00006000)
2661	#define VMX_BF_VMCS_ENC_RSVD_15_31_SHIFT 15
2662	#define VMX_BF_VMCS_ENC_RSVD_15_31_MASK UINT32_C(0xffff8000)
2663	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENC_, UINT32_C(0), UINT32_MAX,
2664	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2665	/** @} */
2666
2667
2668	/** @defgroup grp_hm_vmx_virt VMX virtualization.
2669	* @{
2670	*/
2671
2672	/** CR0 bits set here must always be set when in VMX operation. */
2673	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
2674	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
2675	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
2676	/** CR4 bits set here must always be set when in VMX operation. */
2677	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
2678
2679	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
2680	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
2681	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x1d000001)
2682	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
2683
2684	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
2685	* complications when teleporation may be implemented). */
2686	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
2687	/** The size of the virtual VMCS region (in pages). */
2688	#define VMX_V_VMCS_PAGES 1
2689
2690	/** The highest index value used for supported virtual VMCS field encoding. */
2691	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS32_PREEMPT_TIMER_VALUE, VMX_BF_VMCS_ENC_INDEX)
2692
2693	/** Whether physical addresses of VMXON and VMCS related structures (I/O bitmap
2694	* etc.) are limited to 32-bits (4G). Always 0 on 64-bit CPUs. */
2695	#define VMX_V_VMCS_PHYSADDR_4G_LIMIT 0
2696
2697	/** @name Virtual VMX MSR - Miscellaneous data.
2698	* @{ */
2699	/** Number of CR3-target values supported. */
2700	#define VMX_V_CR3_TARGET_COUNT 4
2701	/** Activity states supported. */
2702	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT)
2703	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
2704	#define VMX_V_PREEMPT_TIMER_SHIFT 5
2705	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
2706	#define VMX_V_MAX_MSRS 0
2707	/** SMM MSEG revision ID. */
2708	#define VMX_V_MSEG_REV_ID 0
2709	/** @} */
2710
2711	/**
2712	* Virtual VMX-instruction diagnostics.
2713	*
2714	* These are not the same as VM instruction errors that are enumerated in the Intel
2715	* spec. These are purely internal, fine-grained definitions used for diagnostic
2716	* purposes and are not reported to guest software under the VM-instruction error
2717	* field in its VMCS.
2718	*
2719	* @note Members of this enum are used as array indices, so no gaps are allowed.
2720	* Please update g_apszVmxInstrDiagDesc when you add new fields to this
2721	* enum.
2722	*/
2723	typedef enum
2724	{
2725	/* Internal processing errors. */
2726	kVmxVInstrDiag_Ipe_1 = 0,
2727	kVmxVInstrDiag_Ipe_2,
2728	kVmxVInstrDiag_Ipe_3,
2729	kVmxVInstrDiag_Ipe_4,
2730	kVmxVInstrDiag_Ipe_5,
2731	kVmxVInstrDiag_Ipe_6,
2732	kVmxVInstrDiag_Ipe_7,
2733	kVmxVInstrDiag_Ipe_8,
2734	kVmxVInstrDiag_Ipe_9,
2735	/* VMXON. */
2736	kVmxVInstrDiag_Vmxon_A20M,
2737	kVmxVInstrDiag_Vmxon_Cpl,
2738	kVmxVInstrDiag_Vmxon_Cr0Fixed0,
2739	kVmxVInstrDiag_Vmxon_Cr4Fixed0,
2740	kVmxVInstrDiag_Vmxon_Intercept,
2741	kVmxVInstrDiag_Vmxon_LongModeCS,
2742	kVmxVInstrDiag_Vmxon_MsrFeatCtl,
2743	kVmxVInstrDiag_Vmxon_PtrAbnormal,
2744	kVmxVInstrDiag_Vmxon_PtrAlign,
2745	kVmxVInstrDiag_Vmxon_PtrMap,
2746	kVmxVInstrDiag_Vmxon_PtrReadPhys,
2747	kVmxVInstrDiag_Vmxon_PtrWidth,
2748	kVmxVInstrDiag_Vmxon_RealOrV86Mode,
2749	kVmxVInstrDiag_Vmxon_ShadowVmcs,
2750	kVmxVInstrDiag_Vmxon_Success,
2751	kVmxVInstrDiag_Vmxon_Vmxe,
2752	kVmxVInstrDiag_Vmxon_VmcsRevId,
2753	kVmxVInstrDiag_Vmxon_VmxRoot,
2754	kVmxVInstrDiag_Vmxon_VmxRootCpl,
2755	/* VMXOFF. */
2756	kVmxVInstrDiag_Vmxoff_Cpl,
2757	kVmxVInstrDiag_Vmxoff_Intercept,
2758	kVmxVInstrDiag_Vmxoff_LongModeCS,
2759	kVmxVInstrDiag_Vmxoff_RealOrV86Mode,
2760	kVmxVInstrDiag_Vmxoff_Success,
2761	kVmxVInstrDiag_Vmxoff_Vmxe,
2762	kVmxVInstrDiag_Vmxoff_VmxRoot,
2763	/* VMPTRLD. */
2764	kVmxVInstrDiag_Vmptrld_Cpl,
2765	kVmxVInstrDiag_Vmptrld_PtrAbnormal,
2766	kVmxVInstrDiag_Vmptrld_PtrAlign,
2767	kVmxVInstrDiag_Vmptrld_PtrMap,
2768	kVmxVInstrDiag_Vmptrld_PtrReadPhys,
2769	kVmxVInstrDiag_Vmptrld_PtrVmxon,
2770	kVmxVInstrDiag_Vmptrld_PtrWidth,
2771	kVmxVInstrDiag_Vmptrld_ShadowVmcs,
2772	kVmxVInstrDiag_Vmptrld_Success,
2773	kVmxVInstrDiag_Vmptrld_VmcsRevId,
2774	/* VMPTRST. */
2775	kVmxVInstrDiag_Vmptrst_Cpl,
2776	kVmxVInstrDiag_Vmptrst_PtrMap,
2777	/* VMCLEAR. */
2778	kVmxVInstrDiag_Vmclear_Cpl,
2779	/* Last member for determining array index limit. */
2780	kVmxVInstrDiag_Last
2781	} VMXVINSTRDIAG;
2782	AssertCompileSize(VMXVINSTRDIAG, 4);
2783
2784	/**
2785	* Virtual VMCS.
2786	* This is our custom format and merged into the actual VMCS (/shadow) when we
2787	* execute nested-guest code using hardware-assisted VMX.
2788	*
2789	* The first 8 bytes are as per Intel spec. 24.2 "Format of the VMCS Region".
2790	*/
2791	#pragma pack(1)
2792	typedef struct
2793	{
2794	/** VMX VMCS revision identifier. */
2795	VMXVMCSREVID u32VmcsRevId;
2796	/** VMX-abort indicator. */
2797	uint32_t u32VmxAbortId;
2798	/** @todo VMCS data. We can use RTUINT64U for the full/high 64-bit VMCS fields. */
2799	uint8_t abPadding0[X86_PAGE_4K_SIZE - 8];
2800	} VMXVVMCS;
2801	#pragma pack()
2802	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
2803	AssertCompileMemberOffset(VMXVVMCS, u32VmxAbortId, 4);
2804	/** Pointer to the VMXVVMCS struct. */
2805	typedef VMXVVMCS *PVMXVVMCS;
2806	/** Pointer to a const VMXVVMCS struct. */
2807	typedef const VMXVVMCS *PCVMXVVMCS;
2808
2809	/** @} */
2810
2811
2812	/** @defgroup grp_hm_vmx_asm VMX Assembly Helpers
2813	* @{
2814	*/
2815
2816	/**
2817	* Restores some host-state fields that need not be done on every VM-exit.
2818	*
2819	* @returns VBox status code.
2820	* @param fRestoreHostFlags Flags of which host registers needs to be
2821	* restored.
2822	* @param pRestoreHost Pointer to the host-restore structure.
2823	*/
2824	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
2825
2826
2827	/**
2828	* Dispatches an NMI to the host.
2829	*/
2830	DECLASM(int) VMXDispatchHostNmi(void);
2831
2832
2833	/**
2834	* Executes VMXON.
2835	*
2836	* @returns VBox status code.
2837	* @param HCPhysVmxOn Physical address of VMXON structure.
2838	*/
2839	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2840	DECLASM(int) VMXEnable(RTHCPHYS HCPhysVmxOn);
2841	#else
2842	DECLINLINE(int) VMXEnable(RTHCPHYS HCPhysVmxOn)
2843	{
2844	# if RT_INLINE_ASM_GNU_STYLE
2845	int rc = VINF_SUCCESS;
2846	__asm__ __volatile__ (
2847	"push %3 \n\t"
2848	"push %2 \n\t"
2849	".byte 0xf3, 0x0f, 0xc7, 0x34, 0x24 # VMXON [esp] \n\t"
2850	"ja 2f \n\t"
2851	"je 1f \n\t"
2852	"movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
2853	"jmp 2f \n\t"
2854	"1: \n\t"
2855	"movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
2856	"2: \n\t"
2857	"add $8, %%esp \n\t"
2858	:"=rm"(rc)
2859	:"0"(VINF_SUCCESS),
2860	"ir"((uint32_t)HCPhysVmxOn), /* don't allow direct memory reference here, */
2861	"ir"((uint32_t)(HCPhysVmxOn >> 32)) /* this would not work with -fomit-frame-pointer */
2862	:"memory"
2863	);
2864	return rc;
2865
2866	# elif VMX_USE_MSC_INTRINSICS
2867	unsigned char rcMsc = __vmx_on(&HCPhysVmxOn);
2868	if (RT_LIKELY(rcMsc == 0))
2869	return VINF_SUCCESS;
2870	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
2871
2872	# else
2873	int rc = VINF_SUCCESS;
2874	__asm
2875	{
2876	push dword ptr [HCPhysVmxOn + 4]
2877	push dword ptr [HCPhysVmxOn]
2878	_emit 0xf3
2879	_emit 0x0f
2880	_emit 0xc7
2881	_emit 0x34
2882	_emit 0x24 /* VMXON [esp] */
2883	jnc vmxon_good
2884	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
2885	jmp the_end
2886
2887	vmxon_good:
2888	jnz the_end
2889	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
2890	the_end:
2891	add esp, 8
2892	}
2893	return rc;
2894	# endif
2895	}
2896	#endif
2897
2898
2899	/**
2900	* Executes VMXOFF.
2901	*/
2902	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2903	DECLASM(void) VMXDisable(void);
2904	#else
2905	DECLINLINE(void) VMXDisable(void)
2906	{
2907	# if RT_INLINE_ASM_GNU_STYLE
2908	__asm__ __volatile__ (
2909	".byte 0x0f, 0x01, 0xc4 # VMXOFF \n\t"
2910	);
2911
2912	# elif VMX_USE_MSC_INTRINSICS
2913	__vmx_off();
2914
2915	# else
2916	__asm
2917	{
2918	_emit 0x0f
2919	_emit 0x01
2920	_emit 0xc4 /* VMXOFF */
2921	}
2922	# endif
2923	}
2924	#endif
2925
2926
2927	/**
2928	* Executes VMCLEAR.
2929	*
2930	* @returns VBox status code.
2931	* @param HCPhysVmcs Physical address of VM control structure.
2932	*/
2933	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2934	DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
2935	#else
2936	DECLINLINE(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs)
2937	{
2938	# if RT_INLINE_ASM_GNU_STYLE
2939	int rc = VINF_SUCCESS;
2940	__asm__ __volatile__ (
2941	"push %3 \n\t"
2942	"push %2 \n\t"
2943	".byte 0x66, 0x0f, 0xc7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
2944	"jnc 1f \n\t"
2945	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2946	"1: \n\t"
2947	"add $8, %%esp \n\t"
2948	:"=rm"(rc)
2949	:"0"(VINF_SUCCESS),
2950	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2951	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this would not work with -fomit-frame-pointer */
2952	:"memory"
2953	);
2954	return rc;
2955
2956	# elif VMX_USE_MSC_INTRINSICS
2957	unsigned char rcMsc = __vmx_vmclear(&HCPhysVmcs);
2958	if (RT_LIKELY(rcMsc == 0))
2959	return VINF_SUCCESS;
2960	return VERR_VMX_INVALID_VMCS_PTR;
2961
2962	# else
2963	int rc = VINF_SUCCESS;
2964	__asm
2965	{
2966	push dword ptr [HCPhysVmcs + 4]
2967	push dword ptr [HCPhysVmcs]
2968	_emit 0x66
2969	_emit 0x0f
2970	_emit 0xc7
2971	_emit 0x34
2972	_emit 0x24 /* VMCLEAR [esp] */
2973	jnc success
2974	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2975	success:
2976	add esp, 8
2977	}
2978	return rc;
2979	# endif
2980	}
2981	#endif
2982
2983
2984	/**
2985	* Executes VMPTRLD.
2986	*
2987	* @returns VBox status code.
2988	* @param HCPhysVmcs Physical address of VMCS structure.
2989	*/
2990	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2991	DECLASM(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs);
2992	#else
2993	DECLINLINE(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs)
2994	{
2995	# if RT_INLINE_ASM_GNU_STYLE
2996	int rc = VINF_SUCCESS;
2997	__asm__ __volatile__ (
2998	"push %3 \n\t"
2999	"push %2 \n\t"
3000	".byte 0x0f, 0xc7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
3001	"jnc 1f \n\t"
3002	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
3003	"1: \n\t"
3004	"add $8, %%esp \n\t"
3005	:"=rm"(rc)
3006	:"0"(VINF_SUCCESS),
3007	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
3008	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this will not work with -fomit-frame-pointer */
3009	);
3010	return rc;
3011
3012	# elif VMX_USE_MSC_INTRINSICS
3013	unsigned char rcMsc = __vmx_vmptrld(&HCPhysVmcs);
3014	if (RT_LIKELY(rcMsc == 0))
3015	return VINF_SUCCESS;
3016	return VERR_VMX_INVALID_VMCS_PTR;
3017
3018	# else
3019	int rc = VINF_SUCCESS;
3020	__asm
3021	{
3022	push dword ptr [HCPhysVmcs + 4]
3023	push dword ptr [HCPhysVmcs]
3024	_emit 0x0f
3025	_emit 0xc7
3026	_emit 0x34
3027	_emit 0x24 /* VMPTRLD [esp] */
3028	jnc success
3029	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
3030
3031	success:
3032	add esp, 8
3033	}
3034	return rc;
3035	# endif
3036	}
3037	#endif
3038
3039
3040	/**
3041	* Executes VMPTRST.
3042	*
3043	* @returns VBox status code.
3044	* @param pHCPhysVmcs Where to store the physical address of the current
3045	* VMCS.
3046	*/
3047	DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
3048
3049
3050	/**
3051	* Executes VMWRITE.
3052	*
3053	* @returns VBox status code.
3054	* @retval VINF_SUCCESS.
3055	* @retval VERR_VMX_INVALID_VMCS_PTR.
3056	* @retval VERR_VMX_INVALID_VMCS_FIELD.
3057	*
3058	* @param idxField VMCS index.
3059	* @param u32Val 32-bit value.
3060	*
3061	* @remarks The values of the two status codes can be OR'ed together, the result
3062	* will be VERR_VMX_INVALID_VMCS_PTR.
3063	*/
3064	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3065	DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
3066	#else
3067	DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
3068	{
3069	# if RT_INLINE_ASM_GNU_STYLE
3070	int rc = VINF_SUCCESS;
3071	__asm__ __volatile__ (
3072	".byte 0x0f, 0x79, 0xc2 # VMWRITE eax, edx \n\t"
3073	"ja 2f \n\t"
3074	"je 1f \n\t"
3075	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
3076	"jmp 2f \n\t"
3077	"1: \n\t"
3078	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
3079	"2: \n\t"
3080	:"=rm"(rc)
3081	:"0"(VINF_SUCCESS),
3082	"a"(idxField),
3083	"d"(u32Val)
3084	);
3085	return rc;
3086
3087	# elif VMX_USE_MSC_INTRINSICS
3088	unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
3089	if (RT_LIKELY(rcMsc == 0))
3090	return VINF_SUCCESS;
3091	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
3092
3093	#else
3094	int rc = VINF_SUCCESS;
3095	__asm
3096	{
3097	push dword ptr [u32Val]
3098	mov eax, [idxField]
3099	_emit 0x0f
3100	_emit 0x79
3101	_emit 0x04
3102	_emit 0x24 /* VMWRITE eax, [esp] */
3103	jnc valid_vmcs
3104	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
3105	jmp the_end
3106
3107	valid_vmcs:
3108	jnz the_end
3109	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
3110	the_end:
3111	add esp, 4
3112	}
3113	return rc;
3114	# endif
3115	}
3116	#endif
3117
3118	/**
3119	* Executes VMWRITE.
3120	*
3121	* @returns VBox status code.
3122	* @retval VINF_SUCCESS.
3123	* @retval VERR_VMX_INVALID_VMCS_PTR.
3124	* @retval VERR_VMX_INVALID_VMCS_FIELD.
3125	*
3126	* @param idxField VMCS index.
3127	* @param u64Val 16, 32 or 64-bit value.
3128	*
3129	* @remarks The values of the two status codes can be OR'ed together, the result
3130	* will be VERR_VMX_INVALID_VMCS_PTR.
3131	*/
3132	#if !defined(RT_ARCH_X86)
3133	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
3134	DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
3135	# else /* VMX_USE_MSC_INTRINSICS */
3136	DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
3137	{
3138	unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
3139	if (RT_LIKELY(rcMsc == 0))
3140	return VINF_SUCCESS;
3141	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
3142	}
3143	# endif /* VMX_USE_MSC_INTRINSICS */
3144	#else
3145	# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
3146	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
3147	#endif
3148
3149	#if ARCH_BITS == 32
3150	# define VMXWriteVmcsHstN VMXWriteVmcs32
3151	# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
3152	#else /* ARCH_BITS == 64 */
3153	# define VMXWriteVmcsHstN VMXWriteVmcs64
3154	# define VMXWriteVmcsGstN VMXWriteVmcs64
3155	#endif
3156
3157
3158	/**
3159	* Invalidate a page using INVEPT.
3160	*
3161	* @returns VBox status code.
3162	* @param enmFlush Type of flush.
3163	* @param pDescriptor Pointer to the descriptor.
3164	*/
3165	DECLASM(int) VMXR0InvEPT(VMXTLBFLUSHEPT enmFlush, uint64_t *pDescriptor);
3166
3167
3168	/**
3169	* Invalidate a page using INVVPID.
3170	*
3171	* @returns VBox status code.
3172	* @param enmFlush Type of flush.
3173	* @param pDescriptor Pointer to the descriptor.
3174	*/
3175	DECLASM(int) VMXR0InvVPID(VMXTLBFLUSHVPID enmFlush, uint64_t *pDescriptor);
3176
3177
3178	/**
3179	* Executes VMREAD.
3180	*
3181	* @returns VBox status code.
3182	* @retval VINF_SUCCESS.
3183	* @retval VERR_VMX_INVALID_VMCS_PTR.
3184	* @retval VERR_VMX_INVALID_VMCS_FIELD.
3185	*
3186	* @param idxField VMCS index.
3187	* @param pData Where to store VM field value.
3188	*
3189	* @remarks The values of the two status codes can be OR'ed together, the result
3190	* will be VERR_VMX_INVALID_VMCS_PTR.
3191	*/
3192	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3193	DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
3194	#else
3195	DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
3196	{
3197	# if RT_INLINE_ASM_GNU_STYLE
3198	int rc = VINF_SUCCESS;
3199	__asm__ __volatile__ (
3200	"movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
3201	".byte 0x0f, 0x78, 0xc2 # VMREAD eax, edx \n\t"
3202	"ja 2f \n\t"
3203	"je 1f \n\t"
3204	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
3205	"jmp 2f \n\t"
3206	"1: \n\t"
3207	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
3208	"2: \n\t"
3209	:"=&r"(rc),
3210	"=d"(*pData)
3211	:"a"(idxField),
3212	"d"(0)
3213	);
3214	return rc;
3215
3216	# elif VMX_USE_MSC_INTRINSICS
3217	unsigned char rcMsc;
3218	# if ARCH_BITS == 32
3219	rcMsc = __vmx_vmread(idxField, pData);
3220	# else
3221	uint64_t u64Tmp;
3222	rcMsc = __vmx_vmread(idxField, &u64Tmp);
3223	*pData = (uint32_t)u64Tmp;
3224	# endif
3225	if (RT_LIKELY(rcMsc == 0))
3226	return VINF_SUCCESS;
3227	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
3228
3229	#else
3230	int rc = VINF_SUCCESS;
3231	__asm
3232	{
3233	sub esp, 4
3234	mov dword ptr [esp], 0
3235	mov eax, [idxField]
3236	_emit 0x0f
3237	_emit 0x78
3238	_emit 0x04
3239	_emit 0x24 /* VMREAD eax, [esp] */
3240	mov edx, pData
3241	pop dword ptr [edx]
3242	jnc valid_vmcs
3243	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
3244	jmp the_end
3245
3246	valid_vmcs:
3247	jnz the_end
3248	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
3249	the_end:
3250	}
3251	return rc;
3252	# endif
3253	}
3254	#endif
3255
3256	/**
3257	* Executes VMREAD.
3258	*
3259	* @returns VBox status code.
3260	* @retval VINF_SUCCESS.
3261	* @retval VERR_VMX_INVALID_VMCS_PTR.
3262	* @retval VERR_VMX_INVALID_VMCS_FIELD.
3263	*
3264	* @param idxField VMCS index.
3265	* @param pData Where to store VM field value.
3266	*
3267	* @remarks The values of the two status codes can be OR'ed together, the result
3268	* will be VERR_VMX_INVALID_VMCS_PTR.
3269	*/
3270	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS)
3271	DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
3272	#else
3273	DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
3274	{
3275	# if VMX_USE_MSC_INTRINSICS
3276	unsigned char rcMsc;
3277	# if ARCH_BITS == 32
3278	size_t uLow;
3279	size_t uHigh;
3280	rcMsc = __vmx_vmread(idxField, &uLow);
3281	rcMsc \|= __vmx_vmread(idxField + 1, &uHigh);
3282	*pData = RT_MAKE_U64(uLow, uHigh);
3283	# else
3284	rcMsc = __vmx_vmread(idxField, pData);
3285	# endif
3286	if (RT_LIKELY(rcMsc == 0))
3287	return VINF_SUCCESS;
3288	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
3289
3290	# elif ARCH_BITS == 32
3291	int rc;
3292	uint32_t val_hi, val;
3293	rc = VMXReadVmcs32(idxField, &val);
3294	rc \|= VMXReadVmcs32(idxField + 1, &val_hi);
3295	AssertRC(rc);
3296	*pData = RT_MAKE_U64(val, val_hi);
3297	return rc;
3298
3299	# else
3300	# error "Shouldn't be here..."
3301	# endif
3302	}
3303	#endif
3304
3305
3306	/**
3307	* Gets the last instruction error value from the current VMCS.
3308	*
3309	* @returns VBox status code.
3310	*/
3311	DECLINLINE(uint32_t) VMXGetLastError(void)
3312	{
3313	#if ARCH_BITS == 64
3314	uint64_t uLastError = 0;
3315	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
3316	AssertRC(rc);
3317	return (uint32_t)uLastError;
3318
3319	#else /* 32-bit host: */
3320	uint32_t uLastError = 0;
3321	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
3322	AssertRC(rc);
3323	return uLastError;
3324	#endif
3325	}
3326
3327	/** @} */
3328
3329	/** @} */
3330
3331	#endif
3332

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 73756

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