hm_vmx.h@ 73937

Last change on this file since 73937 was 73937, checked in by vboxsync, 6 years ago
VMM/IEM, HM: Nested VMX: bugref:9180 Implemented VMWRITE instruction.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# pragma warning(push)
38	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
39	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
40	# include <intrin.h>
41	# pragma warning(pop)
42	/* We always want them as intrinsics, no functions. */
43	# pragma intrinsic(__vmx_on)
44	# pragma intrinsic(__vmx_off)
45	# pragma intrinsic(__vmx_vmclear)
46	# pragma intrinsic(__vmx_vmptrld)
47	# pragma intrinsic(__vmx_vmread)
48	# pragma intrinsic(__vmx_vmwrite)
49	# define VMX_USE_MSC_INTRINSICS 1
50	#else
51	# define VMX_USE_MSC_INTRINSICS 0
52	#endif
53
54
55	/** @defgroup grp_hm_vmx VMX Types and Definitions
56	* @ingroup grp_hm
57	* @{
58	*/
59
60	/** @name Host-state restoration flags.
61	* @note If you change these values don't forget to update the assembly
62	* defines as well!
63	* @{
64	*/
65	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
66	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
67	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
68	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
69	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
70	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
71	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
72	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
73	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
74	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
75	/** @} */
76
77	/**
78	* Host-state restoration structure.
79	* This holds host-state fields that require manual restoration.
80	* Assembly version found in hm_vmx.mac (should be automatically verified).
81	*/
82	typedef struct VMXRESTOREHOST
83	{
84	RTSEL uHostSelDS; /* 0x00 */
85	RTSEL uHostSelES; /* 0x02 */
86	RTSEL uHostSelFS; /* 0x04 */
87	RTSEL uHostSelGS; /* 0x06 */
88	RTSEL uHostSelTR; /* 0x08 */
89	uint8_t abPadding0[4];
90	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
91	uint8_t abPadding1[6];
92	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
93	uint8_t abPadding2[6];
94	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
95	uint64_t uHostFSBase; /* 0x38 */
96	uint64_t uHostGSBase; /* 0x40 */
97	} VMXRESTOREHOST;
98	/** Pointer to VMXRESTOREHOST. */
99	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
100	AssertCompileSize(X86XDTR64, 10);
101	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
102	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
103	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
104	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
105	AssertCompileSize(VMXRESTOREHOST, 72);
106	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
107
108	/** @name Host-state MSR lazy-restoration flags.
109	* @{
110	*/
111	/** The host MSRs have been saved. */
112	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
113	/** The guest MSRs are loaded and in effect. */
114	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
115	/** @} */
116
117	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
118	* UFC = Unsupported Feature Combination.
119	* @{
120	*/
121	/** Unsupported pin-based VM-execution controls combo. */
122	#define VMX_UFC_CTRL_PIN_EXEC 1
123	/** Unsupported processor-based VM-execution controls combo. */
124	#define VMX_UFC_CTRL_PROC_EXEC 2
125	/** Unsupported move debug register VM-exit combo. */
126	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
127	/** Unsupported VM-entry controls combo. */
128	#define VMX_UFC_CTRL_ENTRY 4
129	/** Unsupported VM-exit controls combo. */
130	#define VMX_UFC_CTRL_EXIT 5
131	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
132	* for storing host MSRs. */
133	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
134	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
135	* for storing guest MSRs. */
136	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
137	/** Invalid VMCS size. */
138	#define VMX_UFC_INVALID_VMCS_SIZE 8
139	/** Unsupported secondary processor-based VM-execution controls combo. */
140	#define VMX_UFC_CTRL_PROC_EXEC2 9
141	/** Invalid unrestricted-guest execution controls combo. */
142	#define VMX_UFC_INVALID_UX_COMBO 10
143	/** EPT flush type not supported. */
144	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
145	/** EPT paging structure memory type is not write-back. */
146	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
147	/** EPT requires INVEPT instr. support but it's not available. */
148	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
149	/** EPT requires page-walk length of 4. */
150	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
151	/** @} */
152
153	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
154	* VCI = VMCS-field Cache Invalid.
155	* @{
156	*/
157	/** Cache of VM-entry controls invalid. */
158	#define VMX_VCI_CTRL_ENTRY 300
159	/** Cache of VM-exit controls invalid. */
160	#define VMX_VCI_CTRL_EXIT 301
161	/** Cache of pin-based VM-execution controls invalid. */
162	#define VMX_VCI_CTRL_PIN_EXEC 302
163	/** Cache of processor-based VM-execution controls invalid. */
164	#define VMX_VCI_CTRL_PROC_EXEC 303
165	/** Cache of secondary processor-based VM-execution controls invalid. */
166	#define VMX_VCI_CTRL_PROC_EXEC2 304
167	/** Cache of exception bitmap invalid. */
168	#define VMX_VCI_CTRL_XCPT_BITMAP 305
169	/** Cache of TSC offset invalid. */
170	#define VMX_VCI_CTRL_TSC_OFFSET 306
171	/** @} */
172
173	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
174	* IGS = Invalid Guest State.
175	* @{
176	*/
177	/** An error occurred while checking invalid-guest-state. */
178	#define VMX_IGS_ERROR 500
179	/** The invalid guest-state checks did not find any reason why. */
180	#define VMX_IGS_REASON_NOT_FOUND 501
181	/** CR0 fixed1 bits invalid. */
182	#define VMX_IGS_CR0_FIXED1 502
183	/** CR0 fixed0 bits invalid. */
184	#define VMX_IGS_CR0_FIXED0 503
185	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
186	#define VMX_IGS_CR0_PG_PE_COMBO 504
187	/** CR4 fixed1 bits invalid. */
188	#define VMX_IGS_CR4_FIXED1 505
189	/** CR4 fixed0 bits invalid. */
190	#define VMX_IGS_CR4_FIXED0 506
191	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
192	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
193	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
194	/** CR0.PG not set for long-mode when not using unrestricted guest. */
195	#define VMX_IGS_CR0_PG_LONGMODE 508
196	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
197	#define VMX_IGS_CR4_PAE_LONGMODE 509
198	/** CR4.PCIDE set for 32-bit guest. */
199	#define VMX_IGS_CR4_PCIDE 510
200	/** VMCS' DR7 reserved bits not set to 0. */
201	#define VMX_IGS_DR7_RESERVED 511
202	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
203	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
204	/** VMCS' EFER MSR reserved bits not set to 0. */
205	#define VMX_IGS_EFER_MSR_RESERVED 513
206	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
207	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
208	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
209	* without unrestricted guest. */
210	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
211	/** CS.Attr.P bit invalid. */
212	#define VMX_IGS_CS_ATTR_P_INVALID 516
213	/** CS.Attr reserved bits not set to 0. */
214	#define VMX_IGS_CS_ATTR_RESERVED 517
215	/** CS.Attr.G bit invalid. */
216	#define VMX_IGS_CS_ATTR_G_INVALID 518
217	/** CS is unusable. */
218	#define VMX_IGS_CS_ATTR_UNUSABLE 519
219	/** CS and SS DPL unequal. */
220	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
221	/** CS and SS DPL mismatch. */
222	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
223	/** CS Attr.Type invalid. */
224	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
225	/** CS and SS RPL unequal. */
226	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
227	/** SS.Attr.DPL and SS RPL unequal. */
228	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
229	/** SS.Attr.DPL invalid for segment type. */
230	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
231	/** SS.Attr.Type invalid. */
232	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
233	/** SS.Attr.P bit invalid. */
234	#define VMX_IGS_SS_ATTR_P_INVALID 527
235	/** SS.Attr reserved bits not set to 0. */
236	#define VMX_IGS_SS_ATTR_RESERVED 528
237	/** SS.Attr.G bit invalid. */
238	#define VMX_IGS_SS_ATTR_G_INVALID 529
239	/** DS.Attr.A bit invalid. */
240	#define VMX_IGS_DS_ATTR_A_INVALID 530
241	/** DS.Attr.P bit invalid. */
242	#define VMX_IGS_DS_ATTR_P_INVALID 531
243	/** DS.Attr.DPL and DS RPL unequal. */
244	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
245	/** DS.Attr reserved bits not set to 0. */
246	#define VMX_IGS_DS_ATTR_RESERVED 533
247	/** DS.Attr.G bit invalid. */
248	#define VMX_IGS_DS_ATTR_G_INVALID 534
249	/** DS.Attr.Type invalid. */
250	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
251	/** ES.Attr.A bit invalid. */
252	#define VMX_IGS_ES_ATTR_A_INVALID 536
253	/** ES.Attr.P bit invalid. */
254	#define VMX_IGS_ES_ATTR_P_INVALID 537
255	/** ES.Attr.DPL and DS RPL unequal. */
256	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
257	/** ES.Attr reserved bits not set to 0. */
258	#define VMX_IGS_ES_ATTR_RESERVED 539
259	/** ES.Attr.G bit invalid. */
260	#define VMX_IGS_ES_ATTR_G_INVALID 540
261	/** ES.Attr.Type invalid. */
262	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
263	/** FS.Attr.A bit invalid. */
264	#define VMX_IGS_FS_ATTR_A_INVALID 542
265	/** FS.Attr.P bit invalid. */
266	#define VMX_IGS_FS_ATTR_P_INVALID 543
267	/** FS.Attr.DPL and DS RPL unequal. */
268	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
269	/** FS.Attr reserved bits not set to 0. */
270	#define VMX_IGS_FS_ATTR_RESERVED 545
271	/** FS.Attr.G bit invalid. */
272	#define VMX_IGS_FS_ATTR_G_INVALID 546
273	/** FS.Attr.Type invalid. */
274	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
275	/** GS.Attr.A bit invalid. */
276	#define VMX_IGS_GS_ATTR_A_INVALID 548
277	/** GS.Attr.P bit invalid. */
278	#define VMX_IGS_GS_ATTR_P_INVALID 549
279	/** GS.Attr.DPL and DS RPL unequal. */
280	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
281	/** GS.Attr reserved bits not set to 0. */
282	#define VMX_IGS_GS_ATTR_RESERVED 551
283	/** GS.Attr.G bit invalid. */
284	#define VMX_IGS_GS_ATTR_G_INVALID 552
285	/** GS.Attr.Type invalid. */
286	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
287	/** V86 mode CS.Base invalid. */
288	#define VMX_IGS_V86_CS_BASE_INVALID 554
289	/** V86 mode CS.Limit invalid. */
290	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
291	/** V86 mode CS.Attr invalid. */
292	#define VMX_IGS_V86_CS_ATTR_INVALID 556
293	/** V86 mode SS.Base invalid. */
294	#define VMX_IGS_V86_SS_BASE_INVALID 557
295	/** V86 mode SS.Limit invalid. */
296	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
297	/** V86 mode SS.Attr invalid. */
298	#define VMX_IGS_V86_SS_ATTR_INVALID 559
299	/** V86 mode DS.Base invalid. */
300	#define VMX_IGS_V86_DS_BASE_INVALID 560
301	/** V86 mode DS.Limit invalid. */
302	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
303	/** V86 mode DS.Attr invalid. */
304	#define VMX_IGS_V86_DS_ATTR_INVALID 562
305	/** V86 mode ES.Base invalid. */
306	#define VMX_IGS_V86_ES_BASE_INVALID 563
307	/** V86 mode ES.Limit invalid. */
308	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
309	/** V86 mode ES.Attr invalid. */
310	#define VMX_IGS_V86_ES_ATTR_INVALID 565
311	/** V86 mode FS.Base invalid. */
312	#define VMX_IGS_V86_FS_BASE_INVALID 566
313	/** V86 mode FS.Limit invalid. */
314	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
315	/** V86 mode FS.Attr invalid. */
316	#define VMX_IGS_V86_FS_ATTR_INVALID 568
317	/** V86 mode GS.Base invalid. */
318	#define VMX_IGS_V86_GS_BASE_INVALID 569
319	/** V86 mode GS.Limit invalid. */
320	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
321	/** V86 mode GS.Attr invalid. */
322	#define VMX_IGS_V86_GS_ATTR_INVALID 571
323	/** Longmode CS.Base invalid. */
324	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
325	/** Longmode SS.Base invalid. */
326	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
327	/** Longmode DS.Base invalid. */
328	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
329	/** Longmode ES.Base invalid. */
330	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
331	/** SYSENTER ESP is not canonical. */
332	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
333	/** SYSENTER EIP is not canonical. */
334	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
335	/** PAT MSR invalid. */
336	#define VMX_IGS_PAT_MSR_INVALID 578
337	/** PAT MSR reserved bits not set to 0. */
338	#define VMX_IGS_PAT_MSR_RESERVED 579
339	/** GDTR.Base is not canonical. */
340	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
341	/** IDTR.Base is not canonical. */
342	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
343	/** GDTR.Limit invalid. */
344	#define VMX_IGS_GDTR_LIMIT_INVALID 582
345	/** IDTR.Limit invalid. */
346	#define VMX_IGS_IDTR_LIMIT_INVALID 583
347	/** Longmode RIP is invalid. */
348	#define VMX_IGS_LONGMODE_RIP_INVALID 584
349	/** RFLAGS reserved bits not set to 0. */
350	#define VMX_IGS_RFLAGS_RESERVED 585
351	/** RFLAGS RA1 reserved bits not set to 1. */
352	#define VMX_IGS_RFLAGS_RESERVED1 586
353	/** RFLAGS.VM (V86 mode) invalid. */
354	#define VMX_IGS_RFLAGS_VM_INVALID 587
355	/** RFLAGS.IF invalid. */
356	#define VMX_IGS_RFLAGS_IF_INVALID 588
357	/** Activity state invalid. */
358	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
359	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
360	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
361	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
362	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
363	/** Activity state SIPI WAIT invalid. */
364	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
365	/** Interruptibility state reserved bits not set to 0. */
366	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
367	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
368	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
369	/** Interruptibility state block-by-STI invalid for EFLAGS. */
370	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
371	/** Interruptibility state invalid while trying to deliver external
372	* interrupt. */
373	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
374	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
375	* NMI. */
376	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
377	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
378	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
379	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
380	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
381	/** Interruptibility state block-by-STI (maybe) invalid when trying to
382	* deliver an NMI. */
383	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
384	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
385	* active. */
386	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
387	/** Pending debug exceptions reserved bits not set to 0. */
388	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
389	/** Longmode pending debug exceptions reserved bits not set to 0. */
390	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
391	/** Pending debug exceptions.BS bit is not set when it should be. */
392	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
393	/** Pending debug exceptions.BS bit is not clear when it should be. */
394	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
395	/** VMCS link pointer reserved bits not set to 0. */
396	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
397	/** TR cannot index into LDT, TI bit MBZ. */
398	#define VMX_IGS_TR_TI_INVALID 607
399	/** LDTR cannot index into LDT. TI bit MBZ. */
400	#define VMX_IGS_LDTR_TI_INVALID 608
401	/** TR.Base is not canonical. */
402	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
403	/** FS.Base is not canonical. */
404	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
405	/** GS.Base is not canonical. */
406	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
407	/** LDTR.Base is not canonical. */
408	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
409	/** TR is unusable. */
410	#define VMX_IGS_TR_ATTR_UNUSABLE 613
411	/** TR.Attr.S bit invalid. */
412	#define VMX_IGS_TR_ATTR_S_INVALID 614
413	/** TR is not present. */
414	#define VMX_IGS_TR_ATTR_P_INVALID 615
415	/** TR.Attr reserved bits not set to 0. */
416	#define VMX_IGS_TR_ATTR_RESERVED 616
417	/** TR.Attr.G bit invalid. */
418	#define VMX_IGS_TR_ATTR_G_INVALID 617
419	/** Longmode TR.Attr.Type invalid. */
420	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
421	/** TR.Attr.Type invalid. */
422	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
423	/** CS.Attr.S invalid. */
424	#define VMX_IGS_CS_ATTR_S_INVALID 620
425	/** CS.Attr.DPL invalid. */
426	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
427	/** PAE PDPTE reserved bits not set to 0. */
428	#define VMX_IGS_PAE_PDPTE_RESERVED 623
429	/** @} */
430
431	/** @name VMX VMCS-Read cache indices.
432	* @{
433	*/
434	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
435	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
436	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
437	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
438	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
439	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
440	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
441	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
442	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
443	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
444	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
445	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
446	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
447	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
448	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
449	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
450	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
451	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
452	/** @} */
453
454	/** @name VMX EPT paging structures
455	* @{
456	*/
457
458	/**
459	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
460	*/
461	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
462
463	/**
464	* EPT Page Directory Pointer Entry. Bit view.
465	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
466	* this did cause trouble with one compiler/version).
467	*/
468	typedef struct EPTPML4EBITS
469	{
470	/** Present bit. */
471	uint64_t u1Present : 1;
472	/** Writable bit. */
473	uint64_t u1Write : 1;
474	/** Executable bit. */
475	uint64_t u1Execute : 1;
476	/** Reserved (must be 0). */
477	uint64_t u5Reserved : 5;
478	/** Available for software. */
479	uint64_t u4Available : 4;
480	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
481	uint64_t u40PhysAddr : 40;
482	/** Available for software. */
483	uint64_t u12Available : 12;
484	} EPTPML4EBITS;
485	AssertCompileSize(EPTPML4EBITS, 8);
486
487	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
488	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
489	/** The page shift to get the PML4 index. */
490	#define EPT_PML4_SHIFT X86_PML4_SHIFT
491	/** The PML4 index mask (apply to a shifted page address). */
492	#define EPT_PML4_MASK X86_PML4_MASK
493
494	/**
495	* EPT PML4E.
496	*/
497	typedef union EPTPML4E
498	{
499	/** Normal view. */
500	EPTPML4EBITS n;
501	/** Unsigned integer view. */
502	X86PGPAEUINT u;
503	/** 64 bit unsigned integer view. */
504	uint64_t au64[1];
505	/** 32 bit unsigned integer view. */
506	uint32_t au32[2];
507	} EPTPML4E;
508	AssertCompileSize(EPTPML4E, 8);
509	/** Pointer to a PML4 table entry. */
510	typedef EPTPML4E *PEPTPML4E;
511	/** Pointer to a const PML4 table entry. */
512	typedef const EPTPML4E *PCEPTPML4E;
513
514	/**
515	* EPT PML4 Table.
516	*/
517	typedef struct EPTPML4
518	{
519	EPTPML4E a[EPT_PG_ENTRIES];
520	} EPTPML4;
521	AssertCompileSize(EPTPML4, 0x1000);
522	/** Pointer to an EPT PML4 Table. */
523	typedef EPTPML4 *PEPTPML4;
524	/** Pointer to a const EPT PML4 Table. */
525	typedef const EPTPML4 *PCEPTPML4;
526
527	/**
528	* EPT Page Directory Pointer Entry. Bit view.
529	*/
530	typedef struct EPTPDPTEBITS
531	{
532	/** Present bit. */
533	uint64_t u1Present : 1;
534	/** Writable bit. */
535	uint64_t u1Write : 1;
536	/** Executable bit. */
537	uint64_t u1Execute : 1;
538	/** Reserved (must be 0). */
539	uint64_t u5Reserved : 5;
540	/** Available for software. */
541	uint64_t u4Available : 4;
542	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
543	uint64_t u40PhysAddr : 40;
544	/** Available for software. */
545	uint64_t u12Available : 12;
546	} EPTPDPTEBITS;
547	AssertCompileSize(EPTPDPTEBITS, 8);
548
549	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
550	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
551	/** The page shift to get the PDPT index. */
552	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
553	/** The PDPT index mask (apply to a shifted page address). */
554	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
555
556	/**
557	* EPT Page Directory Pointer.
558	*/
559	typedef union EPTPDPTE
560	{
561	/** Normal view. */
562	EPTPDPTEBITS n;
563	/** Unsigned integer view. */
564	X86PGPAEUINT u;
565	/** 64 bit unsigned integer view. */
566	uint64_t au64[1];
567	/** 32 bit unsigned integer view. */
568	uint32_t au32[2];
569	} EPTPDPTE;
570	AssertCompileSize(EPTPDPTE, 8);
571	/** Pointer to an EPT Page Directory Pointer Entry. */
572	typedef EPTPDPTE *PEPTPDPTE;
573	/** Pointer to a const EPT Page Directory Pointer Entry. */
574	typedef const EPTPDPTE *PCEPTPDPTE;
575
576	/**
577	* EPT Page Directory Pointer Table.
578	*/
579	typedef struct EPTPDPT
580	{
581	EPTPDPTE a[EPT_PG_ENTRIES];
582	} EPTPDPT;
583	AssertCompileSize(EPTPDPT, 0x1000);
584	/** Pointer to an EPT Page Directory Pointer Table. */
585	typedef EPTPDPT *PEPTPDPT;
586	/** Pointer to a const EPT Page Directory Pointer Table. */
587	typedef const EPTPDPT *PCEPTPDPT;
588
589	/**
590	* EPT Page Directory Table Entry. Bit view.
591	*/
592	typedef struct EPTPDEBITS
593	{
594	/** Present bit. */
595	uint64_t u1Present : 1;
596	/** Writable bit. */
597	uint64_t u1Write : 1;
598	/** Executable bit. */
599	uint64_t u1Execute : 1;
600	/** Reserved (must be 0). */
601	uint64_t u4Reserved : 4;
602	/** Big page (must be 0 here). */
603	uint64_t u1Size : 1;
604	/** Available for software. */
605	uint64_t u4Available : 4;
606	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
607	uint64_t u40PhysAddr : 40;
608	/** Available for software. */
609	uint64_t u12Available : 12;
610	} EPTPDEBITS;
611	AssertCompileSize(EPTPDEBITS, 8);
612
613	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
614	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
615	/** The page shift to get the PD index. */
616	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
617	/** The PD index mask (apply to a shifted page address). */
618	#define EPT_PD_MASK X86_PD_PAE_MASK
619
620	/**
621	* EPT 2MB Page Directory Table Entry. Bit view.
622	*/
623	typedef struct EPTPDE2MBITS
624	{
625	/** Present bit. */
626	uint64_t u1Present : 1;
627	/** Writable bit. */
628	uint64_t u1Write : 1;
629	/** Executable bit. */
630	uint64_t u1Execute : 1;
631	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
632	uint64_t u3EMT : 3;
633	/** Ignore PAT memory type */
634	uint64_t u1IgnorePAT : 1;
635	/** Big page (must be 1 here). */
636	uint64_t u1Size : 1;
637	/** Available for software. */
638	uint64_t u4Available : 4;
639	/** Reserved (must be 0). */
640	uint64_t u9Reserved : 9;
641	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
642	uint64_t u31PhysAddr : 31;
643	/** Available for software. */
644	uint64_t u12Available : 12;
645	} EPTPDE2MBITS;
646	AssertCompileSize(EPTPDE2MBITS, 8);
647
648	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
649	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
650
651	/**
652	* EPT Page Directory Table Entry.
653	*/
654	typedef union EPTPDE
655	{
656	/** Normal view. */
657	EPTPDEBITS n;
658	/** 2MB view (big). */
659	EPTPDE2MBITS b;
660	/** Unsigned integer view. */
661	X86PGPAEUINT u;
662	/** 64 bit unsigned integer view. */
663	uint64_t au64[1];
664	/** 32 bit unsigned integer view. */
665	uint32_t au32[2];
666	} EPTPDE;
667	AssertCompileSize(EPTPDE, 8);
668	/** Pointer to an EPT Page Directory Table Entry. */
669	typedef EPTPDE *PEPTPDE;
670	/** Pointer to a const EPT Page Directory Table Entry. */
671	typedef const EPTPDE *PCEPTPDE;
672
673	/**
674	* EPT Page Directory Table.
675	*/
676	typedef struct EPTPD
677	{
678	EPTPDE a[EPT_PG_ENTRIES];
679	} EPTPD;
680	AssertCompileSize(EPTPD, 0x1000);
681	/** Pointer to an EPT Page Directory Table. */
682	typedef EPTPD *PEPTPD;
683	/** Pointer to a const EPT Page Directory Table. */
684	typedef const EPTPD *PCEPTPD;
685
686	/**
687	* EPT Page Table Entry. Bit view.
688	*/
689	typedef struct EPTPTEBITS
690	{
691	/** 0 - Present bit.
692	* @remarks This is a convenience "misnomer". The bit actually indicates read access
693	* and the CPU will consider an entry with any of the first three bits set
694	* as present. Since all our valid entries will have this bit set, it can
695	* be used as a present indicator and allow some code sharing. */
696	uint64_t u1Present : 1;
697	/** 1 - Writable bit. */
698	uint64_t u1Write : 1;
699	/** 2 - Executable bit. */
700	uint64_t u1Execute : 1;
701	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
702	uint64_t u3EMT : 3;
703	/** 6 - Ignore PAT memory type */
704	uint64_t u1IgnorePAT : 1;
705	/** 11:7 - Available for software. */
706	uint64_t u5Available : 5;
707	/** 51:12 - Physical address of page. Restricted by maximum physical
708	* address width of the cpu. */
709	uint64_t u40PhysAddr : 40;
710	/** 63:52 - Available for software. */
711	uint64_t u12Available : 12;
712	} EPTPTEBITS;
713	AssertCompileSize(EPTPTEBITS, 8);
714
715	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
716	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
717	/** The page shift to get the EPT PTE index. */
718	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
719	/** The EPT PT index mask (apply to a shifted page address). */
720	#define EPT_PT_MASK X86_PT_PAE_MASK
721
722	/**
723	* EPT Page Table Entry.
724	*/
725	typedef union EPTPTE
726	{
727	/** Normal view. */
728	EPTPTEBITS n;
729	/** Unsigned integer view. */
730	X86PGPAEUINT u;
731	/** 64 bit unsigned integer view. */
732	uint64_t au64[1];
733	/** 32 bit unsigned integer view. */
734	uint32_t au32[2];
735	} EPTPTE;
736	AssertCompileSize(EPTPTE, 8);
737	/** Pointer to an EPT Page Directory Table Entry. */
738	typedef EPTPTE *PEPTPTE;
739	/** Pointer to a const EPT Page Directory Table Entry. */
740	typedef const EPTPTE *PCEPTPTE;
741
742	/**
743	* EPT Page Table.
744	*/
745	typedef struct EPTPT
746	{
747	EPTPTE a[EPT_PG_ENTRIES];
748	} EPTPT;
749	AssertCompileSize(EPTPT, 0x1000);
750	/** Pointer to an extended page table. */
751	typedef EPTPT *PEPTPT;
752	/** Pointer to a const extended table. */
753	typedef const EPTPT *PCEPTPT;
754
755	/** @} */
756
757	/**
758	* VMX VPID flush types.
759	* @note Valid enum members are in accordance to the VT-x spec.
760	*/
761	typedef enum
762	{
763	/** Invalidate a specific page. */
764	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
765	/** Invalidate one context (specific VPID). */
766	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
767	/** Invalidate all contexts (all VPIDs). */
768	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
769	/** Invalidate a single VPID context retaining global mappings. */
770	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
771	/** Unsupported by VirtualBox. */
772	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
773	/** Unsupported by CPU. */
774	VMXTLBFLUSHVPID_NONE = 0xbad1
775	} VMXTLBFLUSHVPID;
776	AssertCompileSize(VMXTLBFLUSHVPID, 4);
777
778	/**
779	* VMX EPT flush types.
780	* @note Valid enums values are in accordance to the VT-x spec.
781	*/
782	typedef enum
783	{
784	/** Invalidate one context (specific EPT). */
785	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
786	/* Invalidate all contexts (all EPTs) */
787	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
788	/** Unsupported by VirtualBox. */
789	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
790	/** Unsupported by CPU. */
791	VMXTLBFLUSHEPT_NONE = 0xbad1
792	} VMXTLBFLUSHEPT;
793	AssertCompileSize(VMXTLBFLUSHEPT, 4);
794
795	/**
796	* VMX Posted Interrupt Descriptor.
797	* In accordance to the VT-x spec.
798	*/
799	typedef struct VMXPOSTEDINTRDESC
800	{
801	uint32_t aVectorBitmap[8];
802	uint32_t fOutstandingNotification : 1;
803	uint32_t uReserved0 : 31;
804	uint8_t au8Reserved0[28];
805	} VMXPOSTEDINTRDESC;
806	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
807	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
808	/** Pointer to a posted interrupt descriptor. */
809	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
810	/** Pointer to a const posted interrupt descriptor. */
811	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
812
813	/**
814	* VMX VMCS revision identifier.
815	*/
816	typedef union
817	{
818	struct
819	{
820	/** Revision identifier. */
821	uint32_t u31RevisionId : 31;
822	/** Whether this is a shadow VMCS. */
823	uint32_t fIsShadowVmcs : 1;
824	} n;
825	/* The unsigned integer view. */
826	uint32_t u;
827	} VMXVMCSREVID;
828	AssertCompileSize(VMXVMCSREVID, 4);
829	/** Pointer to the VMXVMCSREVID union. */
830	typedef VMXVMCSREVID *PVMXVMCSREVID;
831	/** Pointer to a const VMXVVMCSREVID union. */
832	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
833
834	/**
835	* VMX VM-exit instruction information.
836	*/
837	typedef union
838	{
839	/** Plain unsigned int representation. */
840	uint32_t u;
841	/** INS and OUTS information. */
842	struct
843	{
844	uint32_t u7Reserved0 : 7;
845	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
846	uint32_t u3AddrSize : 3;
847	uint32_t u5Reserved1 : 5;
848	/** The segment register (X86_SREG_XXX). */
849	uint32_t iSegReg : 3;
850	uint32_t uReserved2 : 14;
851	} StrIo;
852	struct
853	{
854	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
855	uint32_t u2Scaling : 2;
856	uint32_t u5Undef0 : 5;
857	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
858	uint32_t u3AddrSize : 3;
859	/** Cleared to 0. */
860	uint32_t u1Cleared0 : 1;
861	uint32_t u4Undef0 : 4;
862	/** The segment register (X86_SREG_XXX). */
863	uint32_t iSegReg : 3;
864	/** The index register (X86_GREG_XXX). */
865	uint32_t iIdxReg : 4;
866	/** Set if index register is invalid. */
867	uint32_t fIdxRegInvalid : 1;
868	/** The base register (X86_GREG_XXX). */
869	uint32_t iBaseReg : 4;
870	/** Set if base register is invalid. */
871	uint32_t fBaseRegInvalid : 1;
872	/** Register 2 (X86_GREG_XXX). */
873	uint32_t iReg2 : 4;
874	} Inv;
875	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
876	struct
877	{
878	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
879	uint32_t u2Scaling : 2;
880	uint32_t u5Reserved0 : 5;
881	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
882	uint32_t u3AddrSize : 3;
883	/** Cleared to 0. */
884	uint32_t u1Cleared0 : 1;
885	uint32_t u4Reserved0 : 4;
886	/** The segment register (X86_SREG_XXX). */
887	uint32_t iSegReg : 3;
888	/** The index register (X86_GREG_XXX). */
889	uint32_t iIdxReg : 4;
890	/** Set if index register is invalid. */
891	uint32_t fIdxRegInvalid : 1;
892	/** The base register (X86_GREG_XXX). */
893	uint32_t iBaseReg : 4;
894	/** Set if base register is invalid. */
895	uint32_t fBaseRegInvalid : 1;
896	/** Register 2 (X86_GREG_XXX). */
897	uint32_t iReg2 : 4;
898	} VmxXsave;
899	/** LIDT, LGDT, SIDT, SGDT information. */
900	struct
901	{
902	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
903	uint32_t u2Scaling : 2;
904	uint32_t u5Undef0 : 5;
905	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
906	uint32_t u3AddrSize : 3;
907	/** Always cleared to 0. */
908	uint32_t u1Cleared0 : 1;
909	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
910	uint32_t uOperandSize : 1;
911	uint32_t u3Undef0 : 3;
912	/** The segment register (X86_SREG_XXX). */
913	uint32_t iSegReg : 3;
914	/** The index register (X86_GREG_XXX). */
915	uint32_t iIdxReg : 4;
916	/** Set if index register is invalid. */
917	uint32_t fIdxRegInvalid : 1;
918	/** The base register (X86_GREG_XXX). */
919	uint32_t iBaseReg : 4;
920	/** Set if base register is invalid. */
921	uint32_t fBaseRegInvalid : 1;
922	/** Instruction identity (VMX_INSTR_ID_XXX). */
923	uint32_t u2InstrId : 2;
924	uint32_t u2Undef0 : 2;
925	} GdtIdt;
926	/** LLDT, LTR, SLDT, STR information. */
927	struct
928	{
929	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
930	uint32_t u2Scaling : 2;
931	uint32_t u1Undef0 : 1;
932	/** Register 1 (X86_GREG_XXX). */
933	uint32_t iReg1 : 4;
934	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
935	uint32_t u3AddrSize : 3;
936	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
937	uint32_t fIsRegOperand : 1;
938	uint32_t u4Undef0 : 4;
939	/** The segment register (X86_SREG_XXX). */
940	uint32_t iSegReg : 3;
941	/** The index register (X86_GREG_XXX). */
942	uint32_t iIdxReg : 4;
943	/** Set if index register is invalid. */
944	uint32_t fIdxRegInvalid : 1;
945	/** The base register (X86_GREG_XXX). */
946	uint32_t iBaseReg : 4;
947	/** Set if base register is invalid. */
948	uint32_t fBaseRegInvalid : 1;
949	/** Instruction identity (VMX_INSTR_ID_XXX). */
950	uint32_t u2InstrId : 2;
951	uint32_t u2Undef0 : 2;
952	} LdtTr;
953	/** RDRAND, RDSEED information. */
954	struct
955	{
956	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
957	uint32_t u2Undef0 : 2;
958	/** Destination register (X86_GREG_XXX). */
959	uint32_t iReg1 : 4;
960	uint32_t u4Undef0 : 4;
961	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
962	uint32_t u2OperandSize : 2;
963	uint32_t u19Def0 : 20;
964	} RdrandRdseed;
965	struct
966	{
967	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
968	uint32_t u2Scaling : 2;
969	uint32_t u1Undef0 : 1;
970	/** Register 1 (X86_GREG_XXX). */
971	uint32_t iReg1 : 4;
972	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
973	uint32_t u3AddrSize : 3;
974	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
975	uint32_t fIsRegOperand : 1;
976	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
977	uint32_t u4Undef0 : 4;
978	/** The segment register (X86_SREG_XXX). */
979	uint32_t iSegReg : 3;
980	/** The index register (X86_GREG_XXX). */
981	uint32_t iIdxReg : 4;
982	/** Set if index register is invalid. */
983	uint32_t fIdxRegInvalid : 1;
984	/** The base register (X86_GREG_XXX). */
985	uint32_t iBaseReg : 4;
986	/** Set if base register is invalid. */
987	uint32_t fBaseRegInvalid : 1;
988	/** Register 2 (X86_GREG_XXX). */
989	uint32_t iReg2 : 4;
990	} VmreadVmwrite;
991	/** This is a combination field of all instruction information. Note! Not all field
992	* combinations are valid (e.g., iReg1 is undefined for memory operands). */
993	struct
994	{
995	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
996	uint32_t u2Scaling : 2;
997	uint32_t u1Undef0 : 1;
998	/** Register 1 (X86_GREG_XXX). */
999	uint32_t iReg1 : 4;
1000	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1001	uint32_t u3AddrSize : 3;
1002	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1003	uint32_t fIsRegOperand : 1;
1004	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1005	uint32_t uOperandSize : 2;
1006	uint32_t u2Undef0 : 2;
1007	/** The segment register (X86_SREG_XXX). */
1008	uint32_t iSegReg : 3;
1009	/** The index register (X86_GREG_XXX). */
1010	uint32_t iIdxReg : 4;
1011	/** Set if index register is invalid. */
1012	uint32_t fIdxRegInvalid : 1;
1013	/** The base register (X86_GREG_XXX). */
1014	uint32_t iBaseReg : 4;
1015	/** Set if base register is invalid. */
1016	uint32_t fBaseRegInvalid : 1;
1017	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1018	uint32_t iReg2 : 4;
1019	} All;
1020	} VMXEXITINSTRINFO;
1021	AssertCompileSize(VMXEXITINSTRINFO, 4);
1022	/** Pointer to a VMX VM-exit instruction info. struct. */
1023	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1024	/** Pointer to a const VMX VM-exit instruction info. struct. */
1025	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1026
1027	/**
1028	* VMX MSR autoload/store element.
1029	* In accordance to the VT-x spec.
1030	*/
1031	typedef struct VMXAUTOMSR
1032	{
1033	/** The MSR Id. */
1034	uint32_t u32Msr;
1035	/** Reserved (MBZ). */
1036	uint32_t u32Reserved;
1037	/** The MSR value. */
1038	uint64_t u64Value;
1039	} VMXAUTOMSR;
1040	AssertCompileSize(VMXAUTOMSR, 16);
1041	/** Pointer to an MSR load/store element. */
1042	typedef VMXAUTOMSR *PVMXAUTOMSR;
1043	/** Pointer to a const MSR load/store element. */
1044	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1045
1046	/**
1047	* VMX tagged-TLB flush types.
1048	*/
1049	typedef enum
1050	{
1051	VMXTLBFLUSHTYPE_EPT,
1052	VMXTLBFLUSHTYPE_VPID,
1053	VMXTLBFLUSHTYPE_EPT_VPID,
1054	VMXTLBFLUSHTYPE_NONE
1055	} VMXTLBFLUSHTYPE;
1056	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1057	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1058	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1059	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1060
1061	/**
1062	* VMX controls MSR.
1063	*/
1064	typedef union
1065	{
1066	struct
1067	{
1068	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1069	uint32_t disallowed0;
1070	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1071	* controls. */
1072	uint32_t allowed1;
1073	} n;
1074	uint64_t u;
1075	} VMXCTLSMSR;
1076	AssertCompileSize(VMXCTLSMSR, 8);
1077	/** Pointer to a VMXCTLSMSR union. */
1078	typedef VMXCTLSMSR *PVMXCTLSMSR;
1079	/** Pointer to a const VMXCTLSMSR union. */
1080	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1081
1082	/**
1083	* VMX MSRs.
1084	* @remarks Although treated as a plain-old data (POD) in several places, please
1085	* update HMVmxGetHostMsr() if new MSRs are added here.
1086	*/
1087	typedef struct VMXMSRS
1088	{
1089	uint64_t u64FeatCtrl;
1090	uint64_t u64Basic;
1091	VMXCTLSMSR PinCtls;
1092	VMXCTLSMSR ProcCtls;
1093	VMXCTLSMSR ProcCtls2;
1094	VMXCTLSMSR ExitCtls;
1095	VMXCTLSMSR EntryCtls;
1096	VMXCTLSMSR TruePinCtls;
1097	VMXCTLSMSR TrueProcCtls;
1098	VMXCTLSMSR TrueEntryCtls;
1099	VMXCTLSMSR TrueExitCtls;
1100	uint64_t u64Misc;
1101	uint64_t u64Cr0Fixed0;
1102	uint64_t u64Cr0Fixed1;
1103	uint64_t u64Cr4Fixed0;
1104	uint64_t u64Cr4Fixed1;
1105	uint64_t u64VmcsEnum;
1106	uint64_t u64VmFunc;
1107	uint64_t u64EptVpidCaps;
1108	uint64_t a_u64Reserved[2];
1109	} VMXMSRS;
1110	AssertCompileSizeAlignment(VMXMSRS, 8);
1111	AssertCompileSize(VMXMSRS, 168);
1112	/** Pointer to a VMXMSRS struct. */
1113	typedef VMXMSRS *PVMXMSRS;
1114	/** Pointer to a const VMXMSRS struct. */
1115	typedef const VMXMSRS *PCVMXMSRS;
1116
1117
1118	/** @name VMX Basic Exit Reasons.
1119	* @{
1120	*/
1121	/** -1 Invalid exit code */
1122	#define VMX_EXIT_INVALID (-1)
1123	/** 0 Exception or non-maskable interrupt (NMI). */
1124	#define VMX_EXIT_XCPT_OR_NMI 0
1125	/** 1 External interrupt. */
1126	#define VMX_EXIT_EXT_INT 1
1127	/** 2 Triple fault. */
1128	#define VMX_EXIT_TRIPLE_FAULT 2
1129	/** 3 INIT signal. */
1130	#define VMX_EXIT_INIT_SIGNAL 3
1131	/** 4 Start-up IPI (SIPI). */
1132	#define VMX_EXIT_SIPI 4
1133	/** 5 I/O system-management interrupt (SMI). */
1134	#define VMX_EXIT_IO_SMI 5
1135	/** 6 Other SMI. */
1136	#define VMX_EXIT_SMI 6
1137	/** 7 Interrupt window exiting. */
1138	#define VMX_EXIT_INT_WINDOW 7
1139	/** 8 NMI window exiting. */
1140	#define VMX_EXIT_NMI_WINDOW 8
1141	/** 9 Task switch. */
1142	#define VMX_EXIT_TASK_SWITCH 9
1143	/** 10 Guest software attempted to execute CPUID. */
1144	#define VMX_EXIT_CPUID 10
1145	/** 11 Guest software attempted to execute GETSEC. */
1146	#define VMX_EXIT_GETSEC 11
1147	/** 12 Guest software attempted to execute HLT. */
1148	#define VMX_EXIT_HLT 12
1149	/** 13 Guest software attempted to execute INVD. */
1150	#define VMX_EXIT_INVD 13
1151	/** 14 Guest software attempted to execute INVLPG. */
1152	#define VMX_EXIT_INVLPG 14
1153	/** 15 Guest software attempted to execute RDPMC. */
1154	#define VMX_EXIT_RDPMC 15
1155	/** 16 Guest software attempted to execute RDTSC. */
1156	#define VMX_EXIT_RDTSC 16
1157	/** 17 Guest software attempted to execute RSM in SMM. */
1158	#define VMX_EXIT_RSM 17
1159	/** 18 Guest software executed VMCALL. */
1160	#define VMX_EXIT_VMCALL 18
1161	/** 19 Guest software executed VMCLEAR. */
1162	#define VMX_EXIT_VMCLEAR 19
1163	/** 20 Guest software executed VMLAUNCH. */
1164	#define VMX_EXIT_VMLAUNCH 20
1165	/** 21 Guest software executed VMPTRLD. */
1166	#define VMX_EXIT_VMPTRLD 21
1167	/** 22 Guest software executed VMPTRST. */
1168	#define VMX_EXIT_VMPTRST 22
1169	/** 23 Guest software executed VMREAD. */
1170	#define VMX_EXIT_VMREAD 23
1171	/** 24 Guest software executed VMRESUME. */
1172	#define VMX_EXIT_VMRESUME 24
1173	/** 25 Guest software executed VMWRITE. */
1174	#define VMX_EXIT_VMWRITE 25
1175	/** 26 Guest software executed VMXOFF. */
1176	#define VMX_EXIT_VMXOFF 26
1177	/** 27 Guest software executed VMXON. */
1178	#define VMX_EXIT_VMXON 27
1179	/** 28 Control-register accesses. */
1180	#define VMX_EXIT_MOV_CRX 28
1181	/** 29 Debug-register accesses. */
1182	#define VMX_EXIT_MOV_DRX 29
1183	/** 30 I/O instruction. */
1184	#define VMX_EXIT_IO_INSTR 30
1185	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1186	#define VMX_EXIT_RDMSR 31
1187	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1188	#define VMX_EXIT_WRMSR 32
1189	/** 33 VM-entry failure due to invalid guest state. */
1190	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1191	/** 34 VM-entry failure due to MSR loading. */
1192	#define VMX_EXIT_ERR_MSR_LOAD 34
1193	/** 36 Guest software executed MWAIT. */
1194	#define VMX_EXIT_MWAIT 36
1195	/** 37 VM-exit due to monitor trap flag. */
1196	#define VMX_EXIT_MTF 37
1197	/** 39 Guest software attempted to execute MONITOR. */
1198	#define VMX_EXIT_MONITOR 39
1199	/** 40 Guest software attempted to execute PAUSE. */
1200	#define VMX_EXIT_PAUSE 40
1201	/** 41 VM-entry failure due to machine-check. */
1202	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1203	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1204	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1205	/** 44 APIC access. Guest software attempted to access memory at a physical
1206	* address on the APIC-access page. */
1207	#define VMX_EXIT_APIC_ACCESS 44
1208	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1209	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1210	#define VMX_EXIT_VIRTUALIZED_EOI 45
1211	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1212	* SGDT, or SIDT. */
1213	#define VMX_EXIT_XDTR_ACCESS 46
1214	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1215	* SLDT, or STR. */
1216	#define VMX_EXIT_TR_ACCESS 47
1217	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1218	* was disallowed by the configuration of the EPT paging structures. */
1219	#define VMX_EXIT_EPT_VIOLATION 48
1220	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1221	* address encountered a misconfigured EPT paging-structure entry. */
1222	#define VMX_EXIT_EPT_MISCONFIG 49
1223	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1224	#define VMX_EXIT_INVEPT 50
1225	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1226	#define VMX_EXIT_RDTSCP 51
1227	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1228	#define VMX_EXIT_PREEMPT_TIMER 52
1229	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1230	#define VMX_EXIT_INVVPID 53
1231	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1232	#define VMX_EXIT_WBINVD 54
1233	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1234	#define VMX_EXIT_XSETBV 55
1235	/** 56 APIC write. Guest completed write to virtual-APIC. */
1236	#define VMX_EXIT_APIC_WRITE 56
1237	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1238	#define VMX_EXIT_RDRAND 57
1239	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1240	#define VMX_EXIT_INVPCID 58
1241	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1242	#define VMX_EXIT_VMFUNC 59
1243	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1244	#define VMX_EXIT_ENCLS 60
1245	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1246	* enabled. */
1247	#define VMX_EXIT_RDSEED 61
1248	/** 62 - Page-modification log full. */
1249	#define VMX_EXIT_PML_FULL 62
1250	/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
1251	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1252	#define VMX_EXIT_XSAVES 63
1253	/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
1254	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1255	#define VMX_EXIT_XRSTORS 64
1256	/** The maximum exit value (inclusive). */
1257	#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
1258	/** @} */
1259
1260
1261	/** @name VM Instruction Errors.
1262	* See Intel spec. "30.4 VM Instruction Error Numbers"
1263	* @{
1264	*/
1265	typedef enum
1266	{
1267	/** VMCALL executed in VMX root operation. */
1268	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1269	/** VMCLEAR with invalid physical address. */
1270	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1271	/** VMCLEAR with VMXON pointer. */
1272	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1273	/** VMLAUNCH with non-clear VMCS. */
1274	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1275	/** VMRESUME with non-launched VMCS. */
1276	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1277	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1278	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1279	/** VM-entry with invalid control field(s). */
1280	VMXINSTRERR_VMENTRY_INVALID_CTL = 7,
1281	/** VM-entry with invalid host-state field(s). */
1282	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1283	/** VMPTRLD with invalid physical address. */
1284	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1285	/** VMPTRLD with VMXON pointer. */
1286	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1287	/** VMPTRLD with incorrect VMCS revision identifier. */
1288	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1289	/** VMREAD from unsupported VMCS component. */
1290	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1291	/** VMWRITE to unsupported VMCS component. */
1292	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1293	/** VMWRITE to read-only VMCS component. */
1294	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1295	/** VMXON executed in VMX root operation. */
1296	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1297	/** VM-entry with invalid executive-VMCS pointer. */
1298	VMXINSTRERR_VMENTRY_INVALID_VMCS_PTR = 16,
1299	/** VM-entry with non-launched executive VMCS. */
1300	VMXINSTRERR_VMENTRY_NON_LAUNCHED_VMCS = 17,
1301	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1302	VMXINSTRERR_VMENTRY_VMCS_PTR = 18,
1303	/** VMCALL with non-clear VMCS. */
1304	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1305	/** VMCALL with invalid VM-exit control fields. */
1306	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1307	/** VMCALL with incorrect MSEG revision identifier. */
1308	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1309	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1310	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1311	/** VMCALL with invalid SMM-monitor features. */
1312	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1313	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1314	VMXINSTRERR_VMENTRY_INVALID_EXECTLS = 25,
1315	/** VM-entry with events blocked by MOV SS. */
1316	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1317	/** Invalid operand to INVEPT/INVVPID. */
1318	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1319	} VMXINSTRERR;
1320	/** @} */
1321
1322
1323	/** @name VMX MSR - Basic VMX information.
1324	* @{
1325	*/
1326	/** VMCS (and related regions) memory type - Uncacheable. */
1327	#define VMX_BASIC_MEM_TYPE_UC 0
1328	/** VMCS (and related regions) memory type - Write back. */
1329	#define VMX_BASIC_MEM_TYPE_WB 6
1330
1331	/** Bit fields for MSR_IA32_VMX_BASIC. */
1332	/** VMCS revision identifier used by the processor. */
1333	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1334	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1335	/** Bit 31 is reserved and RAZ. */
1336	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1337	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1338	/** VMCS size in bytes. */
1339	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1340	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1341	/** Bits 45:47 are reserved. */
1342	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1343	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1344	/** Width of physical addresses used for the VMCS and associated memory regions
1345	* (always 0 on CPUs that support Intel 64 architecture). */
1346	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1347	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1348	/** Dual-monitor treatment of SMI and SMM supported. */
1349	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1350	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1351	/** Memory type that must be used for the VMCS and associated memory regions. */
1352	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1353	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1354	/** VM-exit instruction information for INS/OUTS. */
1355	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1356	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1357	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1358	* bits in VMX control MSRs. */
1359	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1360	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1361	/** Bits 56:63 are reserved and RAZ. */
1362	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 56
1363	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xff00000000000000)
1364	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1365	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1366	VMCS_INS_OUTS, TRUE_CTLS, RSVD_56_63));
1367	/** @} */
1368
1369
1370	/** @name VMX MSR - Miscellaneous data.
1371	* Bit fields for MSR_IA32_VMX_MISC.
1372	* @{
1373	*/
1374	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1375	#define VMX_MISC_EXIT_STORE_EFER_LMA RT_BIT(5)
1376	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1377	* VMWRITE cannot modify read-only VM-exit information fields. */
1378	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1379	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1380	* instructions. */
1381	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1382	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1383	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1384	/** Maximum CR3-target count supported by the CPU. */
1385	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1386	/** Relationship between the preemption timer and tsc. */
1387	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1388	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1389	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1390	#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_SHIFT 5
1391	#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1392	/** Activity states supported by the implementation. */
1393	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1394	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1395	/** Bits 9:13 is reserved and RAZ. */
1396	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1397	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1398	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1399	#define VMX_BF_MISC_PT_SHIFT 14
1400	#define VMX_BF_MISC_PT_MASK UINT64_C(0x0000000000004000)
1401	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1402	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1403	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1404	/** Number of CR3 target values supported by the processor. (0-256) */
1405	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1406	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1407	/** Maximum number of MSRs in the VMCS. */
1408	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1409	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1410	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1411	* SMIs. */
1412	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1413	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1414	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1415	* VMWRITE cannot modify read-only VM-exit information fields. */
1416	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1417	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1418	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1419	* instructions. */
1420	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1421	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1422	/** Bit 31 is reserved and RAZ. */
1423	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1424	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1425	/** 32-bit MSEG revision ID used by the processor. */
1426	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1427	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1428	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1429	(PREEMPT_TIMER_TSC, EXIT_STORE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, PT, SMM_READ_SMBASE_MSR,
1430	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1431	/** @} */
1432
1433	/** Maximum number of CR3 target supported by VT-x */
1434	#define VMX_VMCS_CTRL_CR3_TARGET_COUNT_MAX 4
1435
1436	/** @name VMX MSR - VMCS enumeration.
1437	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1438	* @{
1439	*/
1440	/** Bit 0 is reserved and RAZ. */
1441	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1442	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1443	/** Highest index value used in VMCS field encoding. */
1444	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1445	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1446	/** Bit 10:63 is reserved and RAZ. */
1447	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1448	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1449	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1450	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1451	/** @} */
1452
1453
1454	/** @name VMX MSR - VM Functions.
1455	* Bit fields for MSR_IA32_VMX_VMFUNC.
1456	* @{
1457	*/
1458	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1459	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1460	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1461	/** Bits 1:63 are reserved and RAZ. */
1462	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1463	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1464	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1465	(EPTP_SWITCHING, RSVD_1_63));
1466	/** @} */
1467
1468
1469	/** @name VMX MSR - EPT/VPID capabilities.
1470	* @{
1471	*/
1472	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1473	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1474	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1475	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1476	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1477	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1478	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1479	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1480	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1481	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1482	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1483	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1484	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1485	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1486	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1487	/** @} */
1488
1489
1490	/** @name Extended Page Table Pointer (EPTP)
1491	* @{
1492	*/
1493	/** Uncachable EPT paging structure memory type. */
1494	#define VMX_EPT_MEMTYPE_UC 0
1495	/** Write-back EPT paging structure memory type. */
1496	#define VMX_EPT_MEMTYPE_WB 6
1497	/** Shift value to get the EPT page walk length (bits 5-3) */
1498	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1499	/** Mask value to get the EPT page walk length (bits 5-3) */
1500	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1501	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1502	* length) */
1503	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1504	/** @} */
1505
1506
1507	/** @name VMCS field encoding: 16-bit guest fields.
1508	* @{
1509	*/
1510	#define VMX_VMCS16_VPID 0x0000
1511	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1512	#define VMX_VMCS16_EPTP_INDEX 0x0004
1513	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1514	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1515	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1516	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1517	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1518	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1519	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1520	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1521	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1522	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1523	/** @} */
1524
1525
1526	/** @name VMCS field encoding: 16-bits host fields.
1527	* @{
1528	*/
1529	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1530	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1531	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1532	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1533	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1534	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1535	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1536	/** @} */
1537
1538
1539	/** @name VMCS field encoding: 64-bit control fields.
1540	* @{
1541	*/
1542	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1543	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1544	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1545	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1546	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1547	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1548	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1549	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1550	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1551	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1552	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1553	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1554	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1555	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1556	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1557	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1558	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1559	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1560	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1561	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1562	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1563	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1564	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1565	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1566	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1567	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1568	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1569	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1570	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1571	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1572	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1573	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1574	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1575	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1576	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1577	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1578	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1579	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1580	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1581	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1582	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1583	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1584	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1585	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1586	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1587	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1588	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1589	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1590	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1591	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1592	/** @} */
1593
1594
1595	/** @name VMCS field encoding: 64-bit read-only data fields.
1596	* @{
1597	*/
1598	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1599	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1600	/** @} */
1601
1602
1603	/** @name VMCS field encoding: 64-bit guest fields.
1604	* @{
1605	*/
1606	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1607	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1608	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1609	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1610	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1611	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1612	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1613	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1614	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1615	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1616	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1617	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1618	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1619	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1620	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1621	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1622	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1623	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1624	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1625	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1626	/** @} */
1627
1628
1629	/** @name VMCS field encoding: 64-bit host fields.
1630	* @{
1631	*/
1632	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1633	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1634	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1635	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1636	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1637	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1638	/** @} */
1639
1640
1641	/** @name VMCS field encoding: 32-bit control fields.
1642	* @{
1643	*/
1644	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1645	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1646	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1647	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1648	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1649	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1650	#define VMX_VMCS32_CTRL_EXIT 0x400c
1651	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1652	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1653	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1654	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1655	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1656	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1657	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1658	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1659	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1660	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1661	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1662	/** @} */
1663
1664
1665	/** @name VMCS field encoding: 32-bits read-only fields.
1666	* @{
1667	*/
1668	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1669	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1670	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1671	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1672	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1673	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1674	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1675	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1676	/** @} */
1677
1678
1679	/** @name VMCS field encoding: 32-bit guest-state fields.
1680	* @{
1681	*/
1682	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1683	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1684	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1685	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1686	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1687	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1688	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1689	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1690	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1691	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1692	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1693	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1694	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1695	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1696	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1697	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1698	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1699	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1700	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1701	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1702	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1703	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
1704	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1705	/** @} */
1706
1707
1708	/** @name VMCS field encoding: 32-bit host-state fields.
1709	* @{
1710	*/
1711	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1712	/** @} */
1713
1714
1715	/** @name Natural width control fields.
1716	* @{
1717	*/
1718	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1719	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1720	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1721	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1722	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1723	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1724	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1725	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
1726	/** @} */
1727
1728
1729	/** @name Natural width read-only data fields.
1730	* @{
1731	*/
1732	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1733	#define VMX_VMCS_RO_IO_RCX 0x6402
1734	#define VMX_VMCS_RO_IO_RSX 0x6404
1735	#define VMX_VMCS_RO_IO_RDI 0x6406
1736	#define VMX_VMCS_RO_IO_RIP 0x6408
1737	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640a
1738	/** @} */
1739
1740
1741	/** @name VMCS field encoding: Natural width guest-state fields.
1742	* @{
1743	*/
1744	#define VMX_VMCS_GUEST_CR0 0x6800
1745	#define VMX_VMCS_GUEST_CR3 0x6802
1746	#define VMX_VMCS_GUEST_CR4 0x6804
1747	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1748	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1749	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1750	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1751	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1752	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1753	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1754	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1755	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1756	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1757	#define VMX_VMCS_GUEST_DR7 0x681a
1758	#define VMX_VMCS_GUEST_RSP 0x681c
1759	#define VMX_VMCS_GUEST_RIP 0x681e
1760	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1761	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
1762	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
1763	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
1764	/** @} */
1765
1766
1767	/** @name VMCS field encoding: Natural width host-state fields.
1768	* @{
1769	*/
1770	#define VMX_VMCS_HOST_CR0 0x6c00
1771	#define VMX_VMCS_HOST_CR3 0x6c02
1772	#define VMX_VMCS_HOST_CR4 0x6c04
1773	#define VMX_VMCS_HOST_FS_BASE 0x6c06
1774	#define VMX_VMCS_HOST_GS_BASE 0x6c08
1775	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
1776	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
1777	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
1778	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
1779	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
1780	#define VMX_VMCS_HOST_RSP 0x6c14
1781	#define VMX_VMCS_HOST_RIP 0x6c16
1782	/** @} */
1783
1784
1785	/** @name VMCS field encoding: Access.
1786	* @{ */
1787	typedef enum
1788	{
1789	VMXVMCSFIELDACCESS_FULL = 0,
1790	VMXVMCSFIELDACCESS_HIGH
1791	} VMXVMCSFIELDACCESS;
1792	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
1793	/** @} */
1794
1795
1796	/** @name VMCS field encoding: Type.
1797	* @{ */
1798	typedef enum
1799	{
1800	VMXVMCSFIELDTYPE_CONTROL = 0,
1801	VMXVMCSFIELDTYPE_VMEXIT_INFO,
1802	VMXVMCSFIELDTYPE_GUEST_STATE,
1803	VMXVMCSFIELDTYPE_HOST_STATE
1804	} VMXVMCSFIELDTYPE;
1805	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
1806	/** @} */
1807
1808
1809	/** @name VMCS field encoding: Width.
1810	* @{ */
1811	typedef enum
1812	{
1813	VMXVMCSFIELDWIDTH_16BIT = 0,
1814	VMXVMCSFIELDWIDTH_64BIT,
1815	VMXVMCSFIELDWIDTH_32BIT,
1816	VMXVMCSFIELDWIDTH_NATURAL
1817	} VMXVMCSFIELDWIDTH;
1818	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
1819	/** @} */
1820
1821
1822	/** @name Pin-based VM-execution controls.
1823	* @{
1824	*/
1825	/** External interrupts cause VM-exits if set; otherwise dispatched through the
1826	* guest's IDT. */
1827	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
1828	/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through
1829	* the guest's IDT. */
1830	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
1831	/** Virtual NMIs. */
1832	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
1833	/** Activate VMX preemption timer. */
1834	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
1835	/** Process interrupts with the posted-interrupt notification vector. */
1836	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
1837	/** Default1 class when true capability MSRs are not supported. */
1838	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
1839
1840	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
1841	* controls field in the VMCS. */
1842	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
1843	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
1844	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
1845	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
1846	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
1847	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
1848	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
1849	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
1850	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
1851	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
1852	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
1853	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
1854	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
1855	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
1856	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
1857	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
1858	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
1859	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
1860	/** @} */
1861
1862
1863	/** @name Processor-based VM-execution controls.
1864	* @{
1865	*/
1866	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1867	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
1868	/** Use timestamp counter offset. */
1869	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
1870	/** VM-exit when executing the HLT instruction. */
1871	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
1872	/** VM-exit when executing the INVLPG instruction. */
1873	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
1874	/** VM-exit when executing the MWAIT instruction. */
1875	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
1876	/** VM-exit when executing the RDPMC instruction. */
1877	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
1878	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1879	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
1880	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
1881	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1882	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
1883	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
1884	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1885	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
1886	/** VM-exit on CR8 loads. */
1887	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
1888	/** VM-exit on CR8 stores. */
1889	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
1890	/** Use TPR shadow. */
1891	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
1892	/** VM-exit when virtual NMI blocking is disabled. */
1893	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
1894	/** VM-exit when executing a MOV DRx instruction. */
1895	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
1896	/** VM-exit when executing IO instructions. */
1897	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
1898	/** Use IO bitmaps. */
1899	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
1900	/** Monitor trap flag. */
1901	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
1902	/** Use MSR bitmaps. */
1903	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
1904	/** VM-exit when executing the MONITOR instruction. */
1905	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
1906	/** VM-exit when executing the PAUSE instruction. */
1907	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
1908	/** Whether the secondary processor based VM-execution controls are used. */
1909	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
1910	/** Default1 class when true-capability MSRs are not supported. */
1911	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
1912
1913	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
1914	* controls field in the VMCS. */
1915	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
1916	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
1917	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
1918	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
1919	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
1920	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
1921	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
1922	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
1923	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
1924	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
1925	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
1926	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
1927	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
1928	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
1929	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
1930	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
1931	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
1932	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
1933	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
1934	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
1935	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
1936	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
1937	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
1938	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
1939	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
1940	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
1941	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
1942	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
1943	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
1944	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
1945	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
1946	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
1947	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
1948	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
1949	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
1950	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
1951	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
1952	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
1953	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
1954	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
1955	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
1956	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
1957	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
1958	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
1959	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
1960	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
1961	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
1962	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
1963	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
1964	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
1965	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
1966	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
1967	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
1968	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
1969	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
1970	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
1971	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
1972	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
1973	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
1974	USE_SECONDARY_CTLS));
1975	/** @} */
1976
1977
1978	/** @name Secondary Processor-based VM-execution controls.
1979	* @{
1980	*/
1981	/** Virtualize APIC access. */
1982	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
1983	/** EPT supported/enabled. */
1984	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
1985	/** Descriptor table instructions cause VM-exits. */
1986	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
1987	/** RDTSCP supported/enabled. */
1988	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
1989	/** Virtualize x2APIC mode. */
1990	#define VMX_PROC_CTLS2_VIRT_X2APIC_ACCESS RT_BIT(4)
1991	/** VPID supported/enabled. */
1992	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
1993	/** VM-exit when executing the WBINVD instruction. */
1994	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
1995	/** Unrestricted guest execution. */
1996	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
1997	/** APIC register virtualization. */
1998	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
1999	/** Virtual-interrupt delivery. */
2000	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2001	/** A specified number of pause loops cause a VM-exit. */
2002	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2003	/** VM-exit when executing RDRAND instructions. */
2004	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2005	/** Enables INVPCID instructions. */
2006	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2007	/** Enables VMFUNC instructions. */
2008	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2009	/** Enables VMCS shadowing. */
2010	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2011	/** Enables ENCLS VM-exits. */
2012	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2013	/** VM-exit when executing RDSEED. */
2014	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2015	/** Enables page-modification logging. */
2016	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2017	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2018	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
2019	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2020	#define VMX_PROC_CTLS2_CONCEAL_FROM_PT RT_BIT(19)
2021	/** Enables XSAVES/XRSTORS instructions. */
2022	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2023	/** Use TSC scaling. */
2024	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2025
2026	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2027	* VM-execution controls field in the VMCS. */
2028	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2029	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2030	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2031	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2032	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2033	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2034	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2035	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2036	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_ACCESS_SHIFT 4
2037	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_ACCESS_MASK UINT32_C(0x00000010)
2038	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2039	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2040	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2041	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2042	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2043	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2044	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2045	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2046	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2047	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2048	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2049	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2050	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2051	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2052	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2053	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2054	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2055	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2056	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2057	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2058	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2059	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2060	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2061	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2062	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2063	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2064	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2065	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2066	#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_SHIFT 19
2067	#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_MASK UINT32_C(0x00080000)
2068	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2069	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2070	#define VMX_BF_PROC_CTLS2_UNDEF_21_24_SHIFT 21
2071	#define VMX_BF_PROC_CTLS2_UNDEF_21_24_MASK UINT32_C(0x01e00000)
2072	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2073	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2074	#define VMX_BF_PROC_CTLS2_UNDEF_26_31_SHIFT 26
2075	#define VMX_BF_PROC_CTLS2_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2076	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2077	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_ACCESS, VPID, WBINVD_EXIT,
2078	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2079	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_FROM_PT, XSAVES_XRSTORS, UNDEF_21_24,
2080	TSC_SCALING, UNDEF_26_31));
2081	/** @} */
2082
2083
2084	/** @name VM-entry controls.
2085	* @{
2086	*/
2087	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2088	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2089	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2090	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2091	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2092	/** In SMM mode after VM-entry. */
2093	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2094	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2095	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2096	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2097	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2098	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2099	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2100	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2101	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2102	/** Default1 class when true-capability MSRs are not supported. */
2103	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2104
2105	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2106	* VMCS. */
2107	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2108	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2109	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2110	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2111	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2112	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2113	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2114	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2115	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2116	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2117	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2118	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2119	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2120	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2121	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2122	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2123	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2124	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2125	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2126	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2127	#define VMX_BF_ENTRY_CTLS_UNDEF_16_31_SHIFT 16
2128	#define VMX_BF_ENTRY_CTLS_UNDEF_16_31_MASK UINT32_C(0xffff0000)
2129	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2130	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2131	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, UNDEF_16_31));
2132	/** @} */
2133
2134
2135	/** @name VM-exit controls.
2136	* @{
2137	*/
2138	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2139	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2140	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2141	/** Return to long mode after a VM-exit. */
2142	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2143	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2144	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2145	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2146	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2147	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2148	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2149	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2150	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2151	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2152	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2153	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2154	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2155	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2156	#define VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
2157	/** Default1 class when true-capability MSRs are not supported. */
2158	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2159
2160	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2161	* VMCS. */
2162	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2163	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2164	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2165	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2166	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2167	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2168	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2169	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2170	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2171	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2172	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2173	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2174	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2175	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2176	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2177	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2178	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2179	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2180	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2181	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2182	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2183	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2184	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2185	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2186	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2187	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2188	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2189	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2190	#define VMX_BF_EXIT_CTLS_UNDEF_23_31_SHIFT 23
2191	#define VMX_BF_EXIT_CTLS_UNDEF_23_31_MASK UINT32_C(0xff800000)
2192	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2193	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2194	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2195	SAVE_PREEMPT_TIMER, UNDEF_23_31));
2196	/** @} */
2197
2198
2199	/** @name VM-exit reason.
2200	* @{
2201	*/
2202	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2203	/** @} */
2204
2205
2206	/** @name VM-entry interruption information.
2207	* @{
2208	*/
2209	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2210	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2211	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2212	/** @} */
2213
2214
2215	/** @name VM-entry interruption information.
2216	* @{ */
2217	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2218	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2219	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2220	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2221	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2222	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2223	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2224	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2225	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2226	/** Construct an VM-entry interruption information field from a VM-exit interruption
2227	* info value (same except that bit 12 is reserved). */
2228	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2229	/** Construct a VM-entry interruption information field from an IDT-vectoring
2230	* information field (same except that bit 12 is reserved). */
2231	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2232
2233	/** Bit fields for VM-entry interruption information. */
2234	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2235	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2236	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2237	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2238	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2239	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2240	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2241	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2242	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2243	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2244	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2245	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2246	/** @} */
2247
2248
2249	/** @name VM-entry interruption information types.
2250	* @{
2251	*/
2252	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2253	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2254	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2255	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2256	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2257	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2258	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2259	/** @} */
2260
2261
2262	/** @name VM-exit interruption information.
2263	* @{
2264	*/
2265	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2266	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2267	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2268	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2269	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2270	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2271	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2272	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2273	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2274
2275	/** Bit fields for VM-exit interruption infomration. */
2276	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2277	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2278	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2279	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2280	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2281	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2282	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2283	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2284	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2285	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2286	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2287	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2288	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2289	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2290	/** @} */
2291
2292
2293	/** @name VM-exit interruption information types.
2294	* @{
2295	*/
2296	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2297	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2298	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2299	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2300	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2301	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2302	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2303	/** @} */
2304
2305
2306	/** @name VM-exit instruction identity.
2307	*
2308	* These are found in VM-exit instruction information fields for certain
2309	* instructions.
2310	* @{ */
2311	typedef uint8_t VMXINSTRID;
2312	#define VMX_INSTR_ID_VALID RT_BIT(7)
2313	#define VMX_INSTR_ID_IS_VALID(a) (((a) >> 7) & 1)
2314	#define VMX_INSTR_ID_GET_ID(a) ((a) & ~VMX_INSTR_ID_VALID)
2315	#define VMX_INSTR_ID_NONE 0x7f
2316	/** The following values are in accordance to the VT-x spec: */
2317	#define VMX_INSTR_ID_SGDT ((VMX_INSTR_ID_VALID) \| 0)
2318	#define VMX_INSTR_ID_SIDT ((VMX_INSTR_ID_VALID) \| 1)
2319	#define VMX_INSTR_ID_LGDT ((VMX_INSTR_ID_VALID) \| 2)
2320	#define VMX_INSTR_ID_LIDT ((VMX_INSTR_ID_VALID) \| 3)
2321
2322	#define VMX_INSTR_ID_SLDT ((VMX_INSTR_ID_VALID) \| 0)
2323	#define VMX_INSTR_ID_STR ((VMX_INSTR_ID_VALID) \| 1)
2324	#define VMX_INSTR_ID_LLDT ((VMX_INSTR_ID_VALID) \| 2)
2325	#define VMX_INSTR_ID_LTR ((VMX_INSTR_ID_VALID) \| 3)
2326	/** @} */
2327
2328
2329	/** @name IDT-vectoring information.
2330	* @{
2331	*/
2332	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2333	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2334	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2335	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2336
2337	/** Bit fields for IDT-vectoring information. */
2338	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2339	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2340	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2341	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2342	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2343	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2344	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2345	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2346	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2347	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2348	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2349	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2350	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2351	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2352	/** @} */
2353
2354
2355	/** @name IDT-vectoring information vector types.
2356	* @{
2357	*/
2358	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2359	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2360	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2361	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2362	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2363	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2364	#define VMX_IDT_VECTORING_INFO_TYPE_SW_UNUSED 7
2365	/** @} */
2366
2367
2368	/** @name Guest-activity states.
2369	* @{
2370	*/
2371	/** The logical processor is active. */
2372	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2373	/** The logical processor is inactive, because executed a HLT instruction. */
2374	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2375	/** The logical processor is inactive, because of a triple fault or other serious error. */
2376	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2377	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2378	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2379	/** @} */
2380
2381
2382	/** @name Guest-interruptibility states.
2383	* @{
2384	*/
2385	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2386	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2387	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2388	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2389	/** @} */
2390
2391
2392	/** @name Exit qualification for Mov DRx.
2393	* @{
2394	*/
2395	/** 0-2: Debug register number */
2396	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
2397	/** 3: Reserved; cleared to 0. */
2398	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
2399	/** 4: Direction of move (0 = write, 1 = read) */
2400	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
2401	/** 5-7: Reserved; cleared to 0. */
2402	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
2403	/** 8-11: General purpose register number. */
2404	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
2405	/** Rest: reserved. */
2406	/** @} */
2407
2408
2409	/** @name Exit qualification for debug exceptions types.
2410	* @{
2411	*/
2412	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
2413	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
2414	/** @} */
2415
2416
2417	/** @name Exit qualification for control-register accesses.
2418	* @{
2419	*/
2420	/** 0-3: Control register number (0 for CLTS & LMSW) */
2421	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
2422	/** 4-5: Access type. */
2423	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
2424	/** 6: LMSW operand type */
2425	#define VMX_EXIT_QUAL_CRX_LMSW_OP(a) (((a) >> 6) & 1)
2426	/** 7: Reserved; cleared to 0. */
2427	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
2428	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
2429	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
2430	/** 12-15: Reserved; cleared to 0. */
2431	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
2432	/** 16-31: LMSW source data (else 0). */
2433	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
2434	/* Rest: reserved. */
2435	/** @} */
2436
2437
2438	/** @name Exit qualification for control-register access types.
2439	* @{
2440	*/
2441	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
2442	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
2443	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
2444	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
2445	/** @} */
2446
2447
2448	/** @name Exit qualification for task switch.
2449	* @{
2450	*/
2451	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
2452	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
2453	/** Task switch caused by a call instruction. */
2454	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
2455	/** Task switch caused by an iret instruction. */
2456	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
2457	/** Task switch caused by a jmp instruction. */
2458	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
2459	/** Task switch caused by an interrupt gate. */
2460	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
2461	/** @} */
2462
2463
2464	/** @name Exit qualification for EPT violations.
2465	* @{
2466	*/
2467	/** Set if the violation was caused by a data read. */
2468	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
2469	/** Set if the violation was caused by a data write. */
2470	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
2471	/** Set if the violation was caused by an instruction fetch. */
2472	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
2473	/** AND of the present bit of all EPT structures. */
2474	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
2475	/** AND of the write bit of all EPT structures. */
2476	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
2477	/** AND of the execute bit of all EPT structures. */
2478	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
2479	/** Set if the guest linear address field contains the faulting address. */
2480	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
2481	/** If bit 7 is one: (reserved otherwise)
2482	* 1 - violation due to physical address access.
2483	* 0 - violation caused by page walk or access/dirty bit updates
2484	*/
2485	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
2486	/** @} */
2487
2488
2489	/** @name Exit qualification for I/O instructions.
2490	* @{
2491	*/
2492	/** 0-2: IO operation width. */
2493	#define VMX_EXIT_QUAL_IO_WIDTH(a) ((a) & 7)
2494	/** 3: IO operation direction. */
2495	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
2496	/** 4: String IO operation (INS / OUTS). */
2497	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
2498	/** 5: Repeated IO operation. */
2499	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
2500	/** 6: Operand encoding. */
2501	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
2502	/** 16-31: IO Port (0-0xffff). */
2503	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
2504	/* Rest reserved. */
2505	/** @} */
2506
2507
2508	/** @name Exit qualification for I/O instruction types.
2509	* @{
2510	*/
2511	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
2512	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
2513	/** @} */
2514
2515
2516	/** @name Exit qualification for I/O instruction encoding.
2517	* @{
2518	*/
2519	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
2520	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
2521	/** @} */
2522
2523
2524	/** @name Exit qualification for APIC-access VM-exits from linear and
2525	* guest-physical accesses.
2526	* @{
2527	*/
2528	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
2529	* access within the APIC page. */
2530	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
2531	/** 12-15: Access type. */
2532	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
2533	/* Rest reserved. */
2534	/** @} */
2535
2536
2537	/** @name Exit qualification for linear address APIC-access types.
2538	* @{
2539	*/
2540	/** Linear read access. */
2541	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
2542	/** Linear write access. */
2543	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
2544	/** Linear instruction fetch access. */
2545	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
2546	/** Linear read/write access during event delivery. */
2547	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
2548	/** Physical read/write access during event delivery. */
2549	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
2550	/** Physical access for an instruction fetch or during instruction execution. */
2551	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
2552	/** @} */
2553
2554
2555	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
2556	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
2557	* @{
2558	*/
2559	/** Address calculation scaling field (powers of two). */
2560	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
2561	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
2562	/** Bits 2 thru 6 are undefined. */
2563	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
2564	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
2565	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
2566	* @remarks anyone's guess why this is a 3 bit field... */
2567	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
2568	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
2569	/** Bit 10 is defined as zero. */
2570	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
2571	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
2572	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
2573	* for exits from 64-bit code as the operand size there is fixed. */
2574	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
2575	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
2576	/** Bits 12 thru 14 are undefined. */
2577	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
2578	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
2579	/** Applicable segment register (X86_SREG_XXX values). */
2580	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
2581	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
2582	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
2583	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
2584	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
2585	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
2586	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
2587	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
2588	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
2589	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
2590	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
2591	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2592	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
2593	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2594	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
2595	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
2596	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2597	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
2598	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
2599	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
2600	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
2601	/** Bits 30 & 31 are undefined. */
2602	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
2603	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
2604	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
2605	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
2606	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
2607	/** @} */
2608
2609
2610	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
2611	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
2612	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
2613	* @{
2614	*/
2615	/** Address calculation scaling field (powers of two). */
2616	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
2617	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
2618	/** Bit 2 is undefined. */
2619	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
2620	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
2621	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
2622	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
2623	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
2624	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
2625	* @remarks anyone's guess why this is a 3 bit field... */
2626	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
2627	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
2628	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
2629	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
2630	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
2631	/** Bits 11 thru 14 are undefined. */
2632	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
2633	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
2634	/** Applicable segment register (X86_SREG_XXX values). */
2635	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
2636	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
2637	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
2638	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
2639	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
2640	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
2641	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
2642	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
2643	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
2644	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
2645	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
2646	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2647	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
2648	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2649	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
2650	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
2651	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2652	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
2653	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
2654	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
2655	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
2656	/** Bits 30 & 31 are undefined. */
2657	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
2658	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
2659	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
2660	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
2661	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
2662	/** @} */
2663
2664
2665	/** @name Format of Pending-Debug-Exceptions.
2666	* Bits 4-11, 13, 15 and 17-63 are reserved.
2667	* @{
2668	*/
2669	/** Hardware breakpoint 0 was met. */
2670	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT(0)
2671	/** Hardware breakpoint 1 was met. */
2672	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT(1)
2673	/** Hardware breakpoint 2 was met. */
2674	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT(2)
2675	/** Hardware breakpoint 3 was met. */
2676	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT(3)
2677	/** At least one data or IO breakpoint was hit. */
2678	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT(12)
2679	/** A debug exception would have been triggered by single-step execution mode. */
2680	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT(14)
2681	/** A debug exception occurred inside an RTM region. */
2682	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT(16)
2683	/** @} */
2684
2685
2686	/** @name VMCS field encoding.
2687	* @{ */
2688	typedef union
2689	{
2690	struct
2691	{
2692	/** The access type; 0=full, 1=high of 64-bit fields. */
2693	uint32_t fAccessType : 1;
2694	/** The index. */
2695	uint32_t u8Index : 8;
2696	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
2697	uint32_t u2Type : 2;
2698	/** Reserved (MBZ). */
2699	uint32_t u1Reserved0 : 1;
2700	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
2701	uint32_t u2Width : 2;
2702	/** Reserved (MBZ). */
2703	uint32_t u18Reserved0 : 18;
2704	} n;
2705	/* The unsigned integer view. */
2706	uint32_t u;
2707	} VMXVMCSFIELDENC;
2708	AssertCompileSize(VMXVMCSFIELDENC, 4);
2709	/** Pointer to a VMCS field encoding. */
2710	typedef VMXVMCSFIELDENC *PVMXVMCSFIELDENC;
2711	/** Pointer to a const VMCS field encoding. */
2712	typedef const VMXVMCSFIELDENC *PCVMXVMCSFIELDENC;
2713
2714	/** VMCS field encoding type: Full. */
2715	#define VMX_VMCS_ENC_ACCESS_TYPE_FULL 0
2716	/** VMCS field encoding type: High. */
2717	#define VMX_VMCS_ENC_ACCESS_TYPE_HIGH 1
2718
2719	/** VMCS field encoding type: Control. */
2720	#define VMX_VMCS_ENC_TYPE_CONTROL 0
2721	/** VMCS field encoding type: VM-exit information / read-only fields. */
2722	#define VMX_VMCS_ENC_TYPE_VMEXIT_INFO 1
2723	/** VMCS field encoding type: Guest-state. */
2724	#define VMX_VMCS_ENC_TYPE_GUEST_STATE 2
2725	/** VMCS field encoding type: Host-state. */
2726	#define VMX_VMCS_ENC_TYPE_HOST_STATE 3
2727
2728	/** VMCS field encoding width: 16-bit. */
2729	#define VMX_VMCS_ENC_WIDTH_16BIT 0
2730	/** VMCS field encoding width: 64-bit. */
2731	#define VMX_VMCS_ENC_WIDTH_64BIT 1
2732	/** VMCS field encoding width: 32-bit. */
2733	#define VMX_VMCS_ENC_WIDTH_32BIT 2
2734	/** VMCS field encoding width: Natural width. */
2735	#define VMX_VMCS_ENC_WIDTH_NATURAL 3
2736
2737	/** Bits fields for VMCS field encoding. */
2738	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_SHIFT 0
2739	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2740	#define VMX_BF_VMCS_ENC_INDEX_SHIFT 1
2741	#define VMX_BF_VMCS_ENC_INDEX_MASK UINT32_C(0x000003fe)
2742	#define VMX_BF_VMCS_ENC_TYPE_SHIFT 10
2743	#define VMX_BF_VMCS_ENC_TYPE_MASK UINT32_C(0x00000c00)
2744	#define VMX_BF_VMCS_ENC_RSVD_12_SHIFT 12
2745	#define VMX_BF_VMCS_ENC_RSVD_12_MASK UINT32_C(0x00001000)
2746	#define VMX_BF_VMCS_ENC_WIDTH_SHIFT 13
2747	#define VMX_BF_VMCS_ENC_WIDTH_MASK UINT32_C(0x00006000)
2748	#define VMX_BF_VMCS_ENC_RSVD_15_31_SHIFT 15
2749	#define VMX_BF_VMCS_ENC_RSVD_15_31_MASK UINT32_C(0xffff8000)
2750	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENC_, UINT32_C(0), UINT32_MAX,
2751	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2752	/** @} */
2753
2754
2755	/** @defgroup grp_hm_vmx_virt VMX virtualization.
2756	* @{
2757	*/
2758
2759	/** CR0 bits set here must always be set when in VMX operation. */
2760	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
2761	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
2762	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
2763	/** CR4 bits set here must always be set when in VMX operation. */
2764	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
2765
2766	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
2767	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
2768	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x1d000001)
2769	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
2770
2771	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
2772	* complications when teleporation may be implemented). */
2773	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
2774	/** The size of the virtual VMCS region (in pages). */
2775	#define VMX_V_VMCS_PAGES 1
2776
2777	/** The highest index value used for supported virtual VMCS field encoding. */
2778	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCS_ENC_INDEX)
2779
2780	/** Whether physical addresses of VMXON and VMCS related structures (I/O bitmap
2781	* etc.) are limited to 32-bits (4G). Always 0 on 64-bit CPUs. */
2782	#define VMX_V_VMCS_PHYSADDR_4G_LIMIT 0
2783
2784	/** @name Virtual VMX MSR - Miscellaneous data.
2785	* @{ */
2786	/** Number of CR3-target values supported. */
2787	#define VMX_V_CR3_TARGET_COUNT 4
2788	/** Activity states supported. */
2789	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT)
2790	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
2791	#define VMX_V_PREEMPT_TIMER_SHIFT 5
2792	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
2793	#define VMX_V_MAX_MSRS 0
2794	/** SMM MSEG revision ID. */
2795	#define VMX_V_MSEG_REV_ID 0
2796	/** @} */
2797
2798	/**
2799	* Virtual VMX-instruction diagnostics.
2800	*
2801	* These are not the same as VM instruction errors that are enumerated in the Intel
2802	* spec. These are purely internal, fine-grained definitions used for diagnostic
2803	* purposes and are not reported to guest software under the VM-instruction error
2804	* field in its VMCS.
2805	*
2806	* @note Members of this enum are used as array indices, so no gaps are allowed.
2807	* Please update g_apszVmxInstrDiagDesc when you add new fields to this
2808	* enum.
2809	*/
2810	typedef enum
2811	{
2812	/* Internal processing errors. */
2813	kVmxVInstrDiag_Ipe_1 = 0,
2814	kVmxVInstrDiag_Ipe_2,
2815	kVmxVInstrDiag_Ipe_3,
2816	kVmxVInstrDiag_Ipe_4,
2817	kVmxVInstrDiag_Ipe_5,
2818	kVmxVInstrDiag_Ipe_6,
2819	kVmxVInstrDiag_Ipe_7,
2820	kVmxVInstrDiag_Ipe_8,
2821	kVmxVInstrDiag_Ipe_9,
2822	/* VMXON. */
2823	kVmxVInstrDiag_Vmxon_A20M,
2824	kVmxVInstrDiag_Vmxon_Cpl,
2825	kVmxVInstrDiag_Vmxon_Cr0Fixed0,
2826	kVmxVInstrDiag_Vmxon_Cr4Fixed0,
2827	kVmxVInstrDiag_Vmxon_Intercept,
2828	kVmxVInstrDiag_Vmxon_LongModeCS,
2829	kVmxVInstrDiag_Vmxon_MsrFeatCtl,
2830	kVmxVInstrDiag_Vmxon_PtrAbnormal,
2831	kVmxVInstrDiag_Vmxon_PtrAlign,
2832	kVmxVInstrDiag_Vmxon_PtrMap,
2833	kVmxVInstrDiag_Vmxon_PtrReadPhys,
2834	kVmxVInstrDiag_Vmxon_PtrWidth,
2835	kVmxVInstrDiag_Vmxon_RealOrV86Mode,
2836	kVmxVInstrDiag_Vmxon_ShadowVmcs,
2837	kVmxVInstrDiag_Vmxon_Success,
2838	kVmxVInstrDiag_Vmxon_Vmxe,
2839	kVmxVInstrDiag_Vmxon_VmcsRevId,
2840	kVmxVInstrDiag_Vmxon_VmxRoot,
2841	kVmxVInstrDiag_Vmxon_VmxRootCpl,
2842	/* VMXOFF. */
2843	kVmxVInstrDiag_Vmxoff_Cpl,
2844	kVmxVInstrDiag_Vmxoff_Intercept,
2845	kVmxVInstrDiag_Vmxoff_LongModeCS,
2846	kVmxVInstrDiag_Vmxoff_RealOrV86Mode,
2847	kVmxVInstrDiag_Vmxoff_Success,
2848	kVmxVInstrDiag_Vmxoff_Vmxe,
2849	kVmxVInstrDiag_Vmxoff_VmxRoot,
2850	/* VMPTRLD. */
2851	kVmxVInstrDiag_Vmptrld_Cpl,
2852	kVmxVInstrDiag_Vmptrld_PtrAbnormal,
2853	kVmxVInstrDiag_Vmptrld_PtrAlign,
2854	kVmxVInstrDiag_Vmptrld_PtrMap,
2855	kVmxVInstrDiag_Vmptrld_PtrReadPhys,
2856	kVmxVInstrDiag_Vmptrld_PtrVmxon,
2857	kVmxVInstrDiag_Vmptrld_PtrWidth,
2858	kVmxVInstrDiag_Vmptrld_ShadowVmcs,
2859	kVmxVInstrDiag_Vmptrld_Success,
2860	kVmxVInstrDiag_Vmptrld_VmcsRevId,
2861	/* VMPTRST. */
2862	kVmxVInstrDiag_Vmptrst_Cpl,
2863	kVmxVInstrDiag_Vmptrst_PtrMap,
2864	kVmxVInstrDiag_Vmptrst_Success,
2865	/* VMCLEAR. */
2866	kVmxVInstrDiag_Vmclear_Cpl,
2867	kVmxVInstrDiag_Vmclear_PtrAbnormal,
2868	kVmxVInstrDiag_Vmclear_PtrAlign,
2869	kVmxVInstrDiag_Vmclear_PtrMap,
2870	kVmxVInstrDiag_Vmclear_PtrReadPhys,
2871	kVmxVInstrDiag_Vmclear_PtrVmxon,
2872	kVmxVInstrDiag_Vmclear_PtrWidth,
2873	kVmxVInstrDiag_Vmclear_Success,
2874	/* VMWRITE. */
2875	kVmxVInstrDiag_Vmwrite_Cpl,
2876	kVmxVInstrDiag_Vmwrite_FieldInvalid,
2877	kVmxVInstrDiag_Vmwrite_FieldRo,
2878	kVmxVInstrDiag_Vmwrite_LinkPtrInvalid,
2879	kVmxVInstrDiag_Vmwrite_PtrInvalid,
2880	kVmxVInstrDiag_Vmwrite_PtrMap,
2881	kVmxVInstrDiag_Vmwrite_Success,
2882	/* Last member for determining array index limit. */
2883	kVmxVInstrDiag_Last
2884	} VMXVINSTRDIAG;
2885	AssertCompileSize(VMXVINSTRDIAG, 4);
2886
2887	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS state.
2888	* @{ */
2889	/** VMCS state clear. */
2890	#define VMX_V_VMCS_STATE_CLEAR RT_BIT(0)
2891	/** VMCS state launched. */
2892	#define VMX_V_VMCS_STATE_LAUNCHED RT_BIT(1)
2893	/** @} */
2894
2895	/**
2896	* Virtual VMCS.
2897	* This is our custom format and merged into the actual VMCS (/shadow) when we
2898	* execute nested-guest code using hardware-assisted VMX.
2899	*
2900	* The first 8 bytes are as per Intel spec. 24.2 "Format of the VMCS Region".
2901	*
2902	* The offset and size of the VMCS state field (fVmcsState) is also fixed (not by
2903	* Intel but for our own requirements) as we use it to offset into guest memory.
2904	*
2905	* We always treat natural-width fields as 64-bit in our implementation since
2906	* it's easier, allows for teleporation in the future and does not affect guest
2907	* software.
2908	*
2909	* Although the guest is supposed to access the VMCS only through the execution of
2910	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
2911	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
2912	* for teleportation (when implemented) any newly added fields should be added to
2913	* the appropriate reserved portions or at the end of the structure.
2914	*/
2915	#pragma pack(1)
2916	typedef struct
2917	{
2918	/** 0x0 - VMX VMCS revision identifier. */
2919	VMXVMCSREVID u32VmcsRevId;
2920	/** 0x4 - VMX-abort indicator. */
2921	uint32_t u32VmxAbortId;
2922	/** 0x8 - VMCS state, see VMX_V_VMCS_STATE_XXX. */
2923	uint8_t fVmcsState;
2924	/** 0x9 - Reserved for future. */
2925	uint8_t au8Padding0[3];
2926	/** 0xc - Reserved for future. */
2927	uint32_t au32Reserved0[7];
2928
2929	/** @name 16-bit control fields.
2930	* @{ */
2931	/** 0x28 - Virtual processor ID. */
2932	uint16_t u16Vpid;
2933	/** 0x2a - Posted interrupt notify vector. */
2934	uint16_t u16PostIntNotifyVector;
2935	/** 0x2c - EPTP index. */
2936	uint16_t u16EptpIndex;
2937	/** 0x2e - Reserved for future. */
2938	uint16_t au16Reserved0[8];
2939	/** @} */
2940
2941	/** @name 16-bit Guest-state fields.
2942	* @{ */
2943	/** 0x3e - Guest ES selector. */
2944	RTSEL GuestEs;
2945	/** 0x40 - Guest ES selector. */
2946	RTSEL GuestCs;
2947	/** 0x42 - Guest ES selector. */
2948	RTSEL GuestSs;
2949	/** 0x44 - Guest ES selector. */
2950	RTSEL GuestDs;
2951	/** 0x46 - Guest ES selector. */
2952	RTSEL GuestFs;
2953	/** 0x48 - Guest ES selector. */
2954	RTSEL GuestGs;
2955	/** 0x4a - Guest LDTR selector. */
2956	RTSEL GuestLdtr;
2957	/** 0x4c - Guest TR selector. */
2958	RTSEL GuestTr;
2959	/** 0x4e - Guest interrupt status (virtual-interrupt delivery). */
2960	uint16_t u16GuestIntStatus;
2961	/** 0x50 - PML index. */
2962	uint16_t u16PmlIndex;
2963	/** 0x52 - Reserved for future. */
2964	uint16_t au16Reserved1[8];
2965	/** @} */
2966
2967	/** name 16-bit Host-state fields.
2968	* @{ */
2969	/** 0x62 - Host ES selector. */
2970	RTSEL HostEs;
2971	/** 0x64 - Host CS selector. */
2972	RTSEL HostCs;
2973	/** 0x66 - Host SS selector. */
2974	RTSEL HostSs;
2975	/** 0x68 - Host DS selector. */
2976	RTSEL HostDs;
2977	/** 0x6a - Host FS selector. */
2978	RTSEL HostFs;
2979	/** 0x6c - Host GS selector. */
2980	RTSEL HostGs;
2981	/** 0x6e - Host TR selector. */
2982	RTSEL HostTr;
2983	/** 0x70 - Reserved for future. */
2984	uint16_t au16Reserved2[10];
2985	/** @} */
2986
2987	/** @name 32-bit Control fields.
2988	* @{ */
2989	/** 0x84 - Pin-based VM-execution controls. */
2990	uint32_t u32PinCtls;
2991	/** 0x88 - Processor-based VM-execution controls. */
2992	uint32_t u32ProcCtls;
2993	/** 0x8c - Exception bitmap. */
2994	uint32_t u32XcptBitmap;
2995	/** 0x90 - Page-fault exception error mask. */
2996	uint32_t u32XcptPFMask;
2997	/** 0x94 - Page-fault exception error match. */
2998	uint32_t u32XcptPFMatch;
2999	/** 0x98 - CR3-target count. */
3000	uint32_t u32Cr3TargetCount;
3001	/** 0x9c - VM-exit controls. */
3002	uint32_t u32ExitCtls;
3003	/** 0xa0 - VM-exit MSR store count. */
3004	uint32_t u32ExitMsrStoreCount;
3005	/** 0xa4 - VM-exit MSR load count. */
3006	uint32_t u32ExitMsrLoadCount;
3007	/** 0xa8 - VM-entry controls. */
3008	uint32_t u32EntryCtls;
3009	/** 0xac - VM-entry MSR load count. */
3010	uint32_t u32EntryMsrLoadCount;
3011	/** 0xb0 - VM-entry interruption information. */
3012	uint32_t u32EntryIntInfo;
3013	/** 0xb4 - VM-entry exception error code. */
3014	uint32_t u32EntryXcptErrCode;
3015	/** 0xb8 - VM-entry instruction length. */
3016	uint32_t u32EntryInstrLen;
3017	/** 0xbc - TPR-treshold. */
3018	uint32_t u32TprTreshold;
3019	/** 0xc0 - Secondary-processor based VM-execution controls. */
3020	uint32_t u32ProcCtls2;
3021	/** 0xc4 - Pause-loop exiting Gap. */
3022	uint32_t u32PleGap;
3023	/** 0xc8 - Pause-loop exiting Window. */
3024	uint32_t u32PleWindow;
3025	/** 0xcc - Reserved for future. */
3026	uint32_t au32Reserved1[8];
3027	/** @} */
3028
3029	/** @name 32-bit Read-only Data fields.
3030	* @{ */
3031	/** 0xec - VM-instruction error. */
3032	uint32_t u32RoVmInstrError;
3033	/** 0xf0 - VM-exit reason. */
3034	uint32_t u32RoVmExitReason;
3035	/** 0xf4 - VM-exit interruption information. */
3036	uint32_t u32RoVmExitIntInfo;
3037	/** 0xf8 - VM-exit interruption error code. */
3038	uint32_t u32RoVmExitErrCode;
3039	/** 0xfc - IDT-vectoring information. */
3040	uint32_t u32RoIdtVectoringInfo;
3041	/** 0x100 - IDT-vectoring error code. */
3042	uint32_t u32RoIdtVectoringErrCode;
3043	/** 0x104 - VM-exit instruction length. */
3044	uint32_t u32RoVmExitInstrLen;
3045	/** 0x108 - VM-exit instruction information. */
3046	uint32_t u32RoVmExitInstrInfo;
3047	/** 0x10c - Reserved for future. */
3048	uint32_t au32RoReserved2[8];
3049	/** @} */
3050
3051	/** @name 32-bit Guest-state fields.
3052	* @{ */
3053	/** 0x12c - Guest ES limit. */
3054	uint32_t u32GuestEsLimit;
3055	/** 0x130 - Guest CS limit. */
3056	uint32_t u32GuestCsLimit;
3057	/** 0x134 - Guest SS limit. */
3058	uint32_t u32GuestSsLimit;
3059	/** 0x138 - Guest DS limit. */
3060	uint32_t u32GuestDsLimit;
3061	/** 0x13c - Guest FS limit. */
3062	uint32_t u32GuestFsLimit;
3063	/** 0x140 - Guest GS limit. */
3064	uint32_t u32GuestGsLimit;
3065	/** 0x144 - Guest LDTR limit. */
3066	uint32_t u32GuestLdtrLimit;
3067	/** 0x148 - Guest TR limit. */
3068	uint32_t u32GuestTrLimit;
3069	/** 0x14c - Guest GDTR limit. */
3070	uint32_t u32GuestGdtrLimit;
3071	/** 0x150 - Guest IDTR limit. */
3072	uint32_t u32GuestIdtrLimit;
3073	/** 0x154 - Guest ES attributes. */
3074	uint32_t u32GuestEsAttr;
3075	/** 0x158 - Guest CS attributes. */
3076	uint32_t u32GuestCsAttr;
3077	/** 0x15c - Guest SS attributes. */
3078	uint32_t u32GuestSsAttr;
3079	/** 0x160 - Guest DS attributes. */
3080	uint32_t u32GuestDsAttr;
3081	/** 0x164 - Guest FS attributes. */
3082	uint32_t u32GuestFsAttr;
3083	/** 0x168 - Guest GS attributes. */
3084	uint32_t u32GuestGsAttr;
3085	/** 0x16c - Guest LDTR attributes. */
3086	uint32_t u32GuestLdtrAttr;
3087	/** 0x170 - Guest TR attributes. */
3088	uint32_t u32GuestTrAttr;
3089	/** 0x174 - Guest interruptibility state. */
3090	uint32_t u32GuestIntrState;
3091	/** 0x178 - Guest activity state. */
3092	uint32_t u32GuestActivityState;
3093	/** 0x17c - Guest SMBASE. */
3094	uint32_t u32GuestSmBase;
3095	/** 0x180 - Guest SYSENTER CS. */
3096	uint32_t u32GuestSysenterCS;
3097	/** 0x184 - Preemption timer value. */
3098	uint32_t u32PreemptTimer;
3099	/** 0x188 - Reserved for future. */
3100	uint32_t au32Reserved3[8];
3101	/** @} */
3102
3103	/** @name 32-bit Host-state fields.
3104	* @{ */
3105	/** 0x1a8 - Host SYSENTER CS. */
3106	uint32_t u32HostSysenterCs;
3107	/** 0x1ac - Reserved for future. */
3108	uint32_t au32Reserved4[11];
3109	/** @} */
3110
3111	/** @name 64-bit Control fields.
3112	* @{ */
3113	/** 0x1d8 - I/O bitmap A address. */
3114	RTUINT64U u64AddrIoBitmapA;
3115	/** 0x1e0 - I/O bitmap B address. */
3116	RTUINT64U u64AddrIoBitmapB;
3117	/** 0x1e8 - MSR bitmap address. */
3118	RTUINT64U u64AddrMsrBitmap;
3119	/** 0x1f0 - VM-exit MSR-store area address. */
3120	RTUINT64U u64AddrVmExitMsrStore;
3121	/** 0x1f8 - VM-exit MSR-load area address. */
3122	RTUINT64U u64AddrVmExitMsrLoad;
3123	/** 0x200 - VM-entry MSR-load area address. */
3124	RTUINT64U u64AddrVmEntryMsrLoad;
3125	/** 0x208 - Executive-VMCS pointer. */
3126	RTUINT64U u64ExecVmcsPtr;
3127	/** 0x210 - PML address. */
3128	RTUINT64U u64AddrPml;
3129	/** 0x218 - TSC offset. */
3130	RTUINT64U u64TscOffset;
3131	/** 0x220 - Virtual-APIC address. */
3132	RTUINT64U u64AddrVirtApic;
3133	/** 0x228 - APIC-access address. */
3134	RTUINT64U u64AddrApicAccess;
3135	/** 0x230 - Posted-interrupt descriptor address. */
3136	RTUINT64U u64AddrPostedIntDesc;
3137	/** 0x238 - VM-functions control. */
3138	RTUINT64U u64VmFuncCtls;
3139	/** 0x240 - EPTP pointer. */
3140	RTUINT64U u64EptpPtr;
3141	/** 0x248 - EOI-exit bitmap 0. */
3142	RTUINT64U u64EoiExitBitmap0;
3143	/** 0x250 - EOI-exit bitmap 1. */
3144	RTUINT64U u64EoiExitBitmap1;
3145	/** 0x258 - EOI-exit bitmap 2. */
3146	RTUINT64U u64EoiExitBitmap2;
3147	/** 0x260 - EOI-exit bitmap 3. */
3148	RTUINT64U u64EoiExitBitmap3;
3149	/** 0x268 - EPTP-list address. */
3150	RTUINT64U u64AddrEptpList;
3151	/** 0x270 - VMREAD-bitmap address. */
3152	RTUINT64U u64AddrVmreadBitmap;
3153	/** 0x278 - VMWRITE-bitmap address. */
3154	RTUINT64U u64AddrVmwriteBitmap;
3155	/** 0x280 - Virtualization-exception information address. */
3156	RTUINT64U u64AddrXcptVeInfo;
3157	/** 0x288 - XSS-exiting bitmap address. */
3158	RTUINT64U u64AddrXssBitmap;
3159	/** 0x290 - ENCLS-exiting bitmap address. */
3160	RTUINT64U u64AddrEnclsBitmap;
3161	/** 0x298 - TSC multiplier. */
3162	RTUINT64U u64TscMultiplier;
3163	/** 0x2a0 - Reserved for future. */
3164	RTUINT64U au64Reserved0[16];
3165	/** @} */
3166
3167	/** @name 64-bit Read-only Data fields.
3168	* @{ */
3169	/** 0x320 - Guest-physical address. */
3170	RTUINT64U u64GuestPhysAddr;
3171	/** 0x328 - Reserved for future. */
3172	RTUINT64U au64Reserved1[8];
3173	/** @} */
3174
3175	/** @name 64-bit Guest-state fields.
3176	* @{ */
3177	/** 0x368 - VMCS link pointer. */
3178	RTUINT64U u64VmcsLinkPtr;
3179	/** 0x370 - Guest debug-control MSR. */
3180	RTUINT64U u64GuestDebugCtlMsr;
3181	/** 0x378 - Guest PAT MSR. */
3182	RTUINT64U u64GuestPatMsr;
3183	/** 0x380 - Guest EFER MSR. */
3184	RTUINT64U u64GuestEferMsr;
3185	/** 0x388 - Guest global performance-control MSR. */
3186	RTUINT64U u64GuestPerfGlobalCtlMsr;
3187	/** 0x390 - Guest PDPTE 0. */
3188	RTUINT64U u64GuestPdpte0;
3189	/** 0x398 - Guest PDPTE 0. */
3190	RTUINT64U u64GuestPdpte1;
3191	/** 0x3a0 - Guest PDPTE 1. */
3192	RTUINT64U u64GuestPdpte2;
3193	/** 0x3a8 - Guest PDPTE 2. */
3194	RTUINT64U u64GuestPdpte3;
3195	/** 0x3b0 - Guest Bounds-config MSR (Intel MPX - Memory Protection Extensions). */
3196	RTUINT64U u64GuestBndcfgsMsr;
3197	/** 0x3b8 - Reserved for future. */
3198	RTUINT64U au64Reserved2[16];
3199	/** @} */
3200
3201	/** @name 64-bit Host-state Fields.
3202	* @{ */
3203	/** 0x438 - Host PAT MSR. */
3204	RTUINT64U u64HostPatMsr;
3205	/** 0x440 - Host EFER MSR. */
3206	RTUINT64U u64HostEferMsr;
3207	/** 0x448 - Host global performance-control MSR. */
3208	RTUINT64U u64HostPerfGlobalCtlMsr;
3209	/** 0x450 - Reserved for future. */
3210	RTUINT64U au64Reserved3[16];
3211	/** @} */
3212
3213	/** @name Natural-width Control fields.
3214	* @{ */
3215	/** 0x4d0 - CR0 guest/host Mask. */
3216	RTUINT64U u64Cr0Mask;
3217	/** 0x4d8 - CR4 guest/host Mask. */
3218	RTUINT64U u64Cr4Mask;
3219	/** 0x4e0 - CR0 read shadow. */
3220	RTUINT64U u64Cr0ReadShadow;
3221	/** 0x4e8 - CR4 read shadow. */
3222	RTUINT64U u64Cr4ReadShadow;
3223	/** 0x4f0 - CR3-target value 0. */
3224	RTUINT64U u64Cr3Target0;
3225	/** 0x4f8 - CR3-target value 1. */
3226	RTUINT64U u64Cr3Target1;
3227	/** 0x500 - CR3-target value 2. */
3228	RTUINT64U u64Cr3Target2;
3229	/** 0x508 - CR3-target value 3. */
3230	RTUINT64U u64Cr3Target3;
3231	/** 0x510 - Reserved for future. */
3232	RTUINT64U au64Reserved4[32];
3233	/** @} */
3234
3235	/** @name Natural-width Read-only Data fields. */
3236	/** 0x610 - Exit qualification. */
3237	RTUINT64U u64ExitQual;
3238	/** 0x618 - I/O RCX. */
3239	RTUINT64U u64IoRcx;
3240	/** 0x620 - I/O RSI. */
3241	RTUINT64U u64IoRsi;
3242	/** 0x628 - I/O RDI. */
3243	RTUINT64U u64IoRdi;
3244	/** 0x630 - I/O RIP. */
3245	RTUINT64U u64IoRip;
3246	/** 0x638 - Guest-linear address. */
3247	RTUINT64U u64GuestLinearAddr;
3248	/** 0x640 - Reserved for future. */
3249	RTUINT64U au64Reserved5[16];
3250	/** @} */
3251
3252	/** @name Natural-width Guest-state Fields.
3253	* @{ */
3254	/** 0x6c0 - Guest CR0. */
3255	RTUINT64U u64GuestCr0;
3256	/** 0x6c8 - Guest CR3. */
3257	RTUINT64U u64GuestCr3;
3258	/** 0x6d0 - Guest CR4. */
3259	RTUINT64U u64GuestCr4;
3260	/** 0x6d8 - Guest ES base. */
3261	RTUINT64U u64GuestEsBase;
3262	/** 0x6e0 - Guest CS base. */
3263	RTUINT64U u64GuestCsBase;
3264	/** 0x6e8 - Guest SS base. */
3265	RTUINT64U u64GuestSsBase;
3266	/** 0x6f0 - Guest DS base. */
3267	RTUINT64U u64GuestDsBase;
3268	/** 0x6f8 - Guest FS base. */
3269	RTUINT64U u64GuestFsBase;
3270	/** 0x700 - Guest GS base. */
3271	RTUINT64U u64GuestGsBase;
3272	/** 0x708 - Guest LDTR base. */
3273	RTUINT64U u64GuestLdtrBase;
3274	/** 0x710 - Guest TR base. */
3275	RTUINT64U u64GuestTrBase;
3276	/** 0x718 - Guest GDTR base. */
3277	RTUINT64U u64GuestGdtrBase;
3278	/** 0x720 - Guest IDTR base. */
3279	RTUINT64U u64GuestIdtrBase;
3280	/** 0x728 - Guest DR7. */
3281	RTUINT64U u64GuestDr7;
3282	/** 0x730 - Guest RSP. */
3283	RTUINT64U u64GuestRsp;
3284	/** 0x738 - Guest RIP. */
3285	RTUINT64U u64GuestRip;
3286	/** 0x740 - Guest RFLAGS. */
3287	RTUINT64U u64GuestRFlags;
3288	/** 0x748 - Guest pending debug exception. */
3289	RTUINT64U u64GuestPendingDbgXcpt;
3290	/** 0x750 - Guest SYSENTER ESP. */
3291	RTUINT64U u64GuestSysenterEsp;
3292	/** 0x758 - Guest SYSENTER EIP. */
3293	RTUINT64U u64GuestSysenterEip;
3294	/** 0x760 - Reserved for future. */
3295	RTUINT64U au64Reserved6[32];
3296	/** @} */
3297
3298	/** @name Natural-width Host-state fields.
3299	* @{ */
3300	/** 0x860 - Host CR0. */
3301	RTUINT64U u64HostCr0;
3302	/** 0x868 - Host CR3. */
3303	RTUINT64U u64HostCr3;
3304	/** 0x870 - Host CR4. */
3305	RTUINT64U u64HostCr4;
3306	/** 0x878 - Host FS base. */
3307	RTUINT64U u64HostFsBase;
3308	/** 0x880 - Host GS base. */
3309	RTUINT64U u64HostGsBase;
3310	/** 0x888 - Host TR base. */
3311	RTUINT64U u64HostTrBase;
3312	/** 0x890 - Host GDTR base. */
3313	RTUINT64U u64HostGdtrBase;
3314	/** 0x898 - Host IDTR base. */
3315	RTUINT64U u64HostIdtrBase;
3316	/** 0x8a0 - Host SYSENTER ESP base. */
3317	RTUINT64U u64HostSysenterEsp;
3318	/** 0x8a8 - Host SYSENTER ESP base. */
3319	RTUINT64U u64HostSysenterEip;
3320	/** 0x8b0 - Host RSP. */
3321	RTUINT64U u64HostRsp;
3322	/** 0x8b8 - Host RIP. */
3323	RTUINT64U u64HostRip;
3324	/** 0x8c0 - Reserved for future. */
3325	RTUINT64U au64Reserved7[32];
3326	/** @} */
3327
3328	/** 0x9c0 - Padding. */
3329	uint8_t abPadding[X86_PAGE_4K_SIZE - 0x9c0];
3330	} VMXVVMCS;
3331	#pragma pack()
3332	/** Pointer to the VMXVVMCS struct. */
3333	typedef VMXVVMCS *PVMXVVMCS;
3334	/** Pointer to a const VMXVVMCS struct. */
3335	typedef const VMXVVMCS *PCVMXVVMCS;
3336	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
3337	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
3338	AssertCompileMemberOffset(VMXVVMCS, u32VmxAbortId, 0x004);
3339	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
3340	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x028);
3341	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x03e);
3342	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x062);
3343	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x084);
3344	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x0ec);
3345	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x12c);
3346	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x1a8);
3347	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x1d8);
3348	AssertCompileMemberOffset(VMXVVMCS, u64GuestPhysAddr, 0x320);
3349	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x368);
3350	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x438);
3351	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x4d0);
3352	AssertCompileMemberOffset(VMXVVMCS, u64ExitQual, 0x610);
3353	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x6c0);
3354	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x860);
3355	/** @} */
3356
3357
3358	/** @defgroup grp_hm_vmx_inline VMX Inline Helpers
3359	* @{
3360	*/
3361	/**
3362	* Gets the effective width of a VMCS field given it's encoding adjusted for
3363	* HIGH/FULL access for 64-bit fields.
3364	*
3365	* @returns The effective VMCS field width.
3366	* @param uFieldEnc The VMCS field encoding.
3367	*
3368	* @remarks Warning! This function does not verify the encoding is for a valid and
3369	* supported VMCS field.
3370	*/
3371	DECLINLINE(uint8_t) HMVmxGetVmcsFieldWidthEff(uint32_t uFieldEnc)
3372	{
3373	/* Only the "HIGH" parts of all 64-bit fields have bit 0 set. */
3374	if (uFieldEnc & RT_BIT(0))
3375	return VMXVMCSFIELDWIDTH_32BIT;
3376
3377	/* Bits 13:14 contains the width of the VMCS field, see VMXVMCSFIELDWIDTH_XXX. */
3378	return (uFieldEnc >> 13) & 0x3;
3379	}
3380
3381
3382	/**
3383	* Returns whether the given VMCS field is a read-only VMCS field or not.
3384	*
3385	* @returns @c true if it's a read-only field, @c false otherwise.
3386	* @param uFieldEnc The VMCS field encoding.
3387	*
3388	* @remarks Warning! This function does not verify the encoding is for a valid and
3389	* supported VMCS field.
3390	*/
3391	DECLINLINE(bool) HMVmxIsVmcsFieldReadOnly(uint32_t uFieldEnc)
3392	{
3393	/* See Intel spec. B.4.2 "Natural-Width Read-Only Data Fields". */
3394	return (RT_BF_GET(uFieldEnc, VMX_BF_VMCS_ENC_TYPE) == VMXVMCSFIELDTYPE_VMEXIT_INFO);
3395	}
3396	/** @} */
3397
3398
3399	/** @defgroup grp_hm_vmx_asm VMX Assembly Helpers
3400	* @{
3401	*/
3402
3403	/**
3404	* Restores some host-state fields that need not be done on every VM-exit.
3405	*
3406	* @returns VBox status code.
3407	* @param fRestoreHostFlags Flags of which host registers needs to be
3408	* restored.
3409	* @param pRestoreHost Pointer to the host-restore structure.
3410	*/
3411	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
3412
3413
3414	/**
3415	* Dispatches an NMI to the host.
3416	*/
3417	DECLASM(int) VMXDispatchHostNmi(void);
3418
3419
3420	/**
3421	* Executes VMXON.
3422	*
3423	* @returns VBox status code.
3424	* @param HCPhysVmxOn Physical address of VMXON structure.
3425	*/
3426	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3427	DECLASM(int) VMXEnable(RTHCPHYS HCPhysVmxOn);
3428	#else
3429	DECLINLINE(int) VMXEnable(RTHCPHYS HCPhysVmxOn)
3430	{
3431	# if RT_INLINE_ASM_GNU_STYLE
3432	int rc = VINF_SUCCESS;
3433	__asm__ __volatile__ (
3434	"push %3 \n\t"
3435	"push %2 \n\t"
3436	".byte 0xf3, 0x0f, 0xc7, 0x34, 0x24 # VMXON [esp] \n\t"
3437	"ja 2f \n\t"
3438	"je 1f \n\t"
3439	"movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
3440	"jmp 2f \n\t"
3441	"1: \n\t"
3442	"movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
3443	"2: \n\t"
3444	"add $8, %%esp \n\t"
3445	:"=rm"(rc)
3446	:"0"(VINF_SUCCESS),
3447	"ir"((uint32_t)HCPhysVmxOn), /* don't allow direct memory reference here, */
3448	"ir"((uint32_t)(HCPhysVmxOn >> 32)) /* this would not work with -fomit-frame-pointer */
3449	:"memory"
3450	);
3451	return rc;
3452
3453	# elif VMX_USE_MSC_INTRINSICS
3454	unsigned char rcMsc = __vmx_on(&HCPhysVmxOn);
3455	if (RT_LIKELY(rcMsc == 0))
3456	return VINF_SUCCESS;
3457	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
3458
3459	# else
3460	int rc = VINF_SUCCESS;
3461	__asm
3462	{
3463	push dword ptr [HCPhysVmxOn + 4]
3464	push dword ptr [HCPhysVmxOn]
3465	_emit 0xf3
3466	_emit 0x0f
3467	_emit 0xc7
3468	_emit 0x34
3469	_emit 0x24 /* VMXON [esp] */
3470	jnc vmxon_good
3471	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
3472	jmp the_end
3473
3474	vmxon_good:
3475	jnz the_end
3476	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
3477	the_end:
3478	add esp, 8
3479	}
3480	return rc;
3481	# endif
3482	}
3483	#endif
3484
3485
3486	/**
3487	* Executes VMXOFF.
3488	*/
3489	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3490	DECLASM(void) VMXDisable(void);
3491	#else
3492	DECLINLINE(void) VMXDisable(void)
3493	{
3494	# if RT_INLINE_ASM_GNU_STYLE
3495	__asm__ __volatile__ (
3496	".byte 0x0f, 0x01, 0xc4 # VMXOFF \n\t"
3497	);
3498
3499	# elif VMX_USE_MSC_INTRINSICS
3500	__vmx_off();
3501
3502	# else
3503	__asm
3504	{
3505	_emit 0x0f
3506	_emit 0x01
3507	_emit 0xc4 /* VMXOFF */
3508	}
3509	# endif
3510	}
3511	#endif
3512
3513
3514	/**
3515	* Executes VMCLEAR.
3516	*
3517	* @returns VBox status code.
3518	* @param HCPhysVmcs Physical address of VM control structure.
3519	*/
3520	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3521	DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
3522	#else
3523	DECLINLINE(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs)
3524	{
3525	# if RT_INLINE_ASM_GNU_STYLE
3526	int rc = VINF_SUCCESS;
3527	__asm__ __volatile__ (
3528	"push %3 \n\t"
3529	"push %2 \n\t"
3530	".byte 0x66, 0x0f, 0xc7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
3531	"jnc 1f \n\t"
3532	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
3533	"1: \n\t"
3534	"add $8, %%esp \n\t"
3535	:"=rm"(rc)
3536	:"0"(VINF_SUCCESS),
3537	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
3538	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this would not work with -fomit-frame-pointer */
3539	:"memory"
3540	);
3541	return rc;
3542
3543	# elif VMX_USE_MSC_INTRINSICS
3544	unsigned char rcMsc = __vmx_vmclear(&HCPhysVmcs);
3545	if (RT_LIKELY(rcMsc == 0))
3546	return VINF_SUCCESS;
3547	return VERR_VMX_INVALID_VMCS_PTR;
3548
3549	# else
3550	int rc = VINF_SUCCESS;
3551	__asm
3552	{
3553	push dword ptr [HCPhysVmcs + 4]
3554	push dword ptr [HCPhysVmcs]
3555	_emit 0x66
3556	_emit 0x0f
3557	_emit 0xc7
3558	_emit 0x34
3559	_emit 0x24 /* VMCLEAR [esp] */
3560	jnc success
3561	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
3562	success:
3563	add esp, 8
3564	}
3565	return rc;
3566	# endif
3567	}
3568	#endif
3569
3570
3571	/**
3572	* Executes VMPTRLD.
3573	*
3574	* @returns VBox status code.
3575	* @param HCPhysVmcs Physical address of VMCS structure.
3576	*/
3577	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3578	DECLASM(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs);
3579	#else
3580	DECLINLINE(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs)
3581	{
3582	# if RT_INLINE_ASM_GNU_STYLE
3583	int rc = VINF_SUCCESS;
3584	__asm__ __volatile__ (
3585	"push %3 \n\t"
3586	"push %2 \n\t"
3587	".byte 0x0f, 0xc7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
3588	"jnc 1f \n\t"
3589	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
3590	"1: \n\t"
3591	"add $8, %%esp \n\t"
3592	:"=rm"(rc)
3593	:"0"(VINF_SUCCESS),
3594	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
3595	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this will not work with -fomit-frame-pointer */
3596	);
3597	return rc;
3598
3599	# elif VMX_USE_MSC_INTRINSICS
3600	unsigned char rcMsc = __vmx_vmptrld(&HCPhysVmcs);
3601	if (RT_LIKELY(rcMsc == 0))
3602	return VINF_SUCCESS;
3603	return VERR_VMX_INVALID_VMCS_PTR;
3604
3605	# else
3606	int rc = VINF_SUCCESS;
3607	__asm
3608	{
3609	push dword ptr [HCPhysVmcs + 4]
3610	push dword ptr [HCPhysVmcs]
3611	_emit 0x0f
3612	_emit 0xc7
3613	_emit 0x34
3614	_emit 0x24 /* VMPTRLD [esp] */
3615	jnc success
3616	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
3617
3618	success:
3619	add esp, 8
3620	}
3621	return rc;
3622	# endif
3623	}
3624	#endif
3625
3626
3627	/**
3628	* Executes VMPTRST.
3629	*
3630	* @returns VBox status code.
3631	* @param pHCPhysVmcs Where to store the physical address of the current
3632	* VMCS.
3633	*/
3634	DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
3635
3636
3637	/**
3638	* Executes VMWRITE.
3639	*
3640	* @returns VBox status code.
3641	* @retval VINF_SUCCESS.
3642	* @retval VERR_VMX_INVALID_VMCS_PTR.
3643	* @retval VERR_VMX_INVALID_VMCS_FIELD.
3644	*
3645	* @param uFieldEnc VMCS field encoding.
3646	* @param u32Val The 32-bit value to set.
3647	*
3648	* @remarks The values of the two status codes can be OR'ed together, the result
3649	* will be VERR_VMX_INVALID_VMCS_PTR.
3650	*/
3651	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3652	DECLASM(int) VMXWriteVmcs32(uint32_t uFieldEnc, uint32_t u32Val);
3653	#else
3654	DECLINLINE(int) VMXWriteVmcs32(uint32_t uFieldEnc, uint32_t u32Val)
3655	{
3656	# if RT_INLINE_ASM_GNU_STYLE
3657	int rc = VINF_SUCCESS;
3658	__asm__ __volatile__ (
3659	".byte 0x0f, 0x79, 0xc2 # VMWRITE eax, edx \n\t"
3660	"ja 2f \n\t"
3661	"je 1f \n\t"
3662	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
3663	"jmp 2f \n\t"
3664	"1: \n\t"
3665	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
3666	"2: \n\t"
3667	:"=rm"(rc)
3668	:"0"(VINF_SUCCESS),
3669	"a"(uFieldEnc),
3670	"d"(u32Val)
3671	);
3672	return rc;
3673
3674	# elif VMX_USE_MSC_INTRINSICS
3675	unsigned char rcMsc = __vmx_vmwrite(uFieldEnc, u32Val);
3676	if (RT_LIKELY(rcMsc == 0))
3677	return VINF_SUCCESS;
3678	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
3679
3680	#else
3681	int rc = VINF_SUCCESS;
3682	__asm
3683	{
3684	push dword ptr [u32Val]
3685	mov eax, [uFieldEnc]
3686	_emit 0x0f
3687	_emit 0x79
3688	_emit 0x04
3689	_emit 0x24 /* VMWRITE eax, [esp] */
3690	jnc valid_vmcs
3691	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
3692	jmp the_end
3693
3694	valid_vmcs:
3695	jnz the_end
3696	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
3697	the_end:
3698	add esp, 4
3699	}
3700	return rc;
3701	# endif
3702	}
3703	#endif
3704
3705	/**
3706	* Executes VMWRITE.
3707	*
3708	* @returns VBox status code.
3709	* @retval VINF_SUCCESS.
3710	* @retval VERR_VMX_INVALID_VMCS_PTR.
3711	* @retval VERR_VMX_INVALID_VMCS_FIELD.
3712	*
3713	* @param uFieldEnc The VMCS field encoding.
3714	* @param u64Val The 16, 32 or 64-bit value to set.
3715	*
3716	* @remarks The values of the two status codes can be OR'ed together, the result
3717	* will be VERR_VMX_INVALID_VMCS_PTR.
3718	*/
3719	#if !defined(RT_ARCH_X86)
3720	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
3721	DECLASM(int) VMXWriteVmcs64(uint32_t uFieldEnc, uint64_t u64Val);
3722	# else /* VMX_USE_MSC_INTRINSICS */
3723	DECLINLINE(int) VMXWriteVmcs64(uint32_t uFieldEnc, uint64_t u64Val)
3724	{
3725	unsigned char rcMsc = __vmx_vmwrite(uFieldEnc, u64Val);
3726	if (RT_LIKELY(rcMsc == 0))
3727	return VINF_SUCCESS;
3728	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
3729	}
3730	# endif /* VMX_USE_MSC_INTRINSICS */
3731	#else
3732	# define VMXWriteVmcs64(uFieldEnc, u64Val) VMXWriteVmcs64Ex(pVCpu, uFieldEnc, u64Val) /** @todo dead ugly, picking up pVCpu like this */
3733	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t uFieldEnc, uint64_t u64Val);
3734	#endif
3735
3736	#if ARCH_BITS == 32
3737	# define VMXWriteVmcsHstN VMXWriteVmcs32
3738	# define VMXWriteVmcsGstN(uFieldEnc, u64Val) VMXWriteVmcs64Ex(pVCpu, uFieldEnc, u64Val)
3739	#else /* ARCH_BITS == 64 */
3740	# define VMXWriteVmcsHstN VMXWriteVmcs64
3741	# define VMXWriteVmcsGstN VMXWriteVmcs64
3742	#endif
3743
3744
3745	/**
3746	* Invalidate a page using INVEPT.
3747	*
3748	* @returns VBox status code.
3749	* @param enmFlush Type of flush.
3750	* @param pDescriptor Pointer to the descriptor.
3751	*/
3752	DECLASM(int) VMXR0InvEPT(VMXTLBFLUSHEPT enmFlush, uint64_t *pDescriptor);
3753
3754
3755	/**
3756	* Invalidate a page using INVVPID.
3757	*
3758	* @returns VBox status code.
3759	* @param enmFlush Type of flush.
3760	* @param pDescriptor Pointer to the descriptor.
3761	*/
3762	DECLASM(int) VMXR0InvVPID(VMXTLBFLUSHVPID enmFlush, uint64_t *pDescriptor);
3763
3764
3765	/**
3766	* Executes VMREAD for a 32-bit field.
3767	*
3768	* @returns VBox status code.
3769	* @retval VINF_SUCCESS.
3770	* @retval VERR_VMX_INVALID_VMCS_PTR.
3771	* @retval VERR_VMX_INVALID_VMCS_FIELD.
3772	*
3773	* @param uFieldEnc The VMCS field encoding.
3774	* @param pData Where to store VMCS field value.
3775	*
3776	* @remarks The values of the two status codes can be OR'ed together, the result
3777	* will be VERR_VMX_INVALID_VMCS_PTR.
3778	*/
3779	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
3780	DECLASM(int) VMXReadVmcs32(uint32_t uFieldEnc, uint32_t *pData);
3781	#else
3782	DECLINLINE(int) VMXReadVmcs32(uint32_t uFieldEnc, uint32_t *pData)
3783	{
3784	# if RT_INLINE_ASM_GNU_STYLE
3785	int rc = VINF_SUCCESS;
3786	__asm__ __volatile__ (
3787	"movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
3788	".byte 0x0f, 0x78, 0xc2 # VMREAD eax, edx \n\t"
3789	"ja 2f \n\t"
3790	"je 1f \n\t"
3791	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
3792	"jmp 2f \n\t"
3793	"1: \n\t"
3794	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
3795	"2: \n\t"
3796	:"=&r"(rc),
3797	"=d"(*pData)
3798	:"a"(uFieldEnc),
3799	"d"(0)
3800	);
3801	return rc;
3802
3803	# elif VMX_USE_MSC_INTRINSICS
3804	unsigned char rcMsc;
3805	# if ARCH_BITS == 32
3806	rcMsc = __vmx_vmread(uFieldEnc, pData);
3807	# else
3808	uint64_t u64Tmp;
3809	rcMsc = __vmx_vmread(uFieldEnc, &u64Tmp);
3810	*pData = (uint32_t)u64Tmp;
3811	# endif
3812	if (RT_LIKELY(rcMsc == 0))
3813	return VINF_SUCCESS;
3814	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
3815
3816	#else
3817	int rc = VINF_SUCCESS;
3818	__asm
3819	{
3820	sub esp, 4
3821	mov dword ptr [esp], 0
3822	mov eax, [uFieldEnc]
3823	_emit 0x0f
3824	_emit 0x78
3825	_emit 0x04
3826	_emit 0x24 /* VMREAD eax, [esp] */
3827	mov edx, pData
3828	pop dword ptr [edx]
3829	jnc valid_vmcs
3830	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
3831	jmp the_end
3832
3833	valid_vmcs:
3834	jnz the_end
3835	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
3836	the_end:
3837	}
3838	return rc;
3839	# endif
3840	}
3841	#endif
3842
3843	/**
3844	* Executes VMREAD for a 64-bit field.
3845	*
3846	* @returns VBox status code.
3847	* @retval VINF_SUCCESS.
3848	* @retval VERR_VMX_INVALID_VMCS_PTR.
3849	* @retval VERR_VMX_INVALID_VMCS_FIELD.
3850	*
3851	* @param uFieldEnc The VMCS field encoding.
3852	* @param pData Where to store VMCS field value.
3853	*
3854	* @remarks The values of the two status codes can be OR'ed together, the result
3855	* will be VERR_VMX_INVALID_VMCS_PTR.
3856	*/
3857	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS)
3858	DECLASM(int) VMXReadVmcs64(uint32_t uFieldEnc, uint64_t *pData);
3859	#else
3860	DECLINLINE(int) VMXReadVmcs64(uint32_t uFieldEnc, uint64_t *pData)
3861	{
3862	# if VMX_USE_MSC_INTRINSICS
3863	unsigned char rcMsc;
3864	# if ARCH_BITS == 32
3865	size_t uLow;
3866	size_t uHigh;
3867	rcMsc = __vmx_vmread(uFieldEnc, &uLow);
3868	rcMsc \|= __vmx_vmread(uFieldEnc + 1, &uHigh);
3869	*pData = RT_MAKE_U64(uLow, uHigh);
3870	# else
3871	rcMsc = __vmx_vmread(uFieldEnc, pData);
3872	# endif
3873	if (RT_LIKELY(rcMsc == 0))
3874	return VINF_SUCCESS;
3875	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
3876
3877	# elif ARCH_BITS == 32
3878	int rc;
3879	uint32_t val_hi, val;
3880	rc = VMXReadVmcs32(uFieldEnc, &val);
3881	rc \|= VMXReadVmcs32(uFieldEnc + 1, &val_hi);
3882	AssertRC(rc);
3883	*pData = RT_MAKE_U64(val, val_hi);
3884	return rc;
3885
3886	# else
3887	# error "Shouldn't be here..."
3888	# endif
3889	}
3890	#endif
3891
3892
3893	/**
3894	* Gets the last instruction error value from the current VMCS.
3895	*
3896	* @returns VBox status code.
3897	*/
3898	DECLINLINE(uint32_t) VMXGetLastError(void)
3899	{
3900	#if ARCH_BITS == 64
3901	uint64_t uLastError = 0;
3902	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
3903	AssertRC(rc);
3904	return (uint32_t)uLastError;
3905
3906	#else /* 32-bit host: */
3907	uint32_t uLastError = 0;
3908	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
3909	AssertRC(rc);
3910	return uLastError;
3911	#endif
3912	}
3913
3914	/** @} */
3915
3916	/** @} */
3917
3918	#endif
3919

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 73937

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