hm_vmx.h@ 78650

Last change on this file since 78650 was 78650, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 Added RTIT_CTL MSR to the virtual VMCS. Brought up rest of HM definitions to the latest VT-x specs. Spaces.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_hm_vmx_h
27	#define VBOX_INCLUDED_vmm_hm_vmx_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <iprt/x86.h>
34	#include <iprt/assertcompile.h>
35
36	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
37	when targeting AMD64. */
38	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
39	# pragma warning(push)
40	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
41	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
42	# include <intrin.h>
43	# pragma warning(pop)
44	/* We always want them as intrinsics, no functions. */
45	# pragma intrinsic(__vmx_on)
46	# pragma intrinsic(__vmx_off)
47	# pragma intrinsic(__vmx_vmclear)
48	# pragma intrinsic(__vmx_vmptrld)
49	# pragma intrinsic(__vmx_vmread)
50	# pragma intrinsic(__vmx_vmwrite)
51	# define VMX_USE_MSC_INTRINSICS 1
52	#else
53	# define VMX_USE_MSC_INTRINSICS 0
54	#endif
55
56
57	/** @defgroup grp_hm_vmx VMX Types and Definitions
58	* @ingroup grp_hm
59	* @{
60	*/
61
62	/** @name Host-state restoration flags.
63	* @note If you change these values don't forget to update the assembly
64	* defines as well!
65	* @{
66	*/
67	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
68	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
69	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
70	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
71	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
72	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
73	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
74	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
75	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
76	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
77	/** @} */
78
79	/**
80	* Host-state restoration structure.
81	* This holds host-state fields that require manual restoration.
82	* Assembly version found in hm_vmx.mac (should be automatically verified).
83	*/
84	typedef struct VMXRESTOREHOST
85	{
86	RTSEL uHostSelDS; /* 0x00 */
87	RTSEL uHostSelES; /* 0x02 */
88	RTSEL uHostSelFS; /* 0x04 */
89	RTSEL uHostSelGS; /* 0x06 */
90	RTSEL uHostSelTR; /* 0x08 */
91	uint8_t abPadding0[4];
92	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
93	uint8_t abPadding1[6];
94	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
95	uint8_t abPadding2[6];
96	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
97	uint64_t uHostFSBase; /* 0x38 */
98	uint64_t uHostGSBase; /* 0x40 */
99	} VMXRESTOREHOST;
100	/** Pointer to VMXRESTOREHOST. */
101	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
102	AssertCompileSize(X86XDTR64, 10);
103	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
104	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
105	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
106	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
107	AssertCompileSize(VMXRESTOREHOST, 72);
108	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
109
110	/** @name Host-state MSR lazy-restoration flags.
111	* @{
112	*/
113	/** The host MSRs have been saved. */
114	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
115	/** The guest MSRs are loaded and in effect. */
116	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
117	/** @} */
118
119	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
120	* UFC = Unsupported Feature Combination.
121	* @{
122	*/
123	/** Unsupported pin-based VM-execution controls combo. */
124	#define VMX_UFC_CTRL_PIN_EXEC 1
125	/** Unsupported processor-based VM-execution controls combo. */
126	#define VMX_UFC_CTRL_PROC_EXEC 2
127	/** Unsupported move debug register VM-exit combo. */
128	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
129	/** Unsupported VM-entry controls combo. */
130	#define VMX_UFC_CTRL_ENTRY 4
131	/** Unsupported VM-exit controls combo. */
132	#define VMX_UFC_CTRL_EXIT 5
133	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
134	* for storing host MSRs. */
135	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
136	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
137	* for storing guest MSRs. */
138	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
139	/** Invalid VMCS size. */
140	#define VMX_UFC_INVALID_VMCS_SIZE 8
141	/** Unsupported secondary processor-based VM-execution controls combo. */
142	#define VMX_UFC_CTRL_PROC_EXEC2 9
143	/** Invalid unrestricted-guest execution controls combo. */
144	#define VMX_UFC_INVALID_UX_COMBO 10
145	/** EPT flush type not supported. */
146	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
147	/** EPT paging structure memory type is not write-back. */
148	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
149	/** EPT requires INVEPT instr. support but it's not available. */
150	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
151	/** EPT requires page-walk length of 4. */
152	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
153	/** @} */
154
155	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
156	* VCI = VMCS-field Cache Invalid.
157	* @{
158	*/
159	/** Cache of VM-entry controls invalid. */
160	#define VMX_VCI_CTRL_ENTRY 300
161	/** Cache of VM-exit controls invalid. */
162	#define VMX_VCI_CTRL_EXIT 301
163	/** Cache of pin-based VM-execution controls invalid. */
164	#define VMX_VCI_CTRL_PIN_EXEC 302
165	/** Cache of processor-based VM-execution controls invalid. */
166	#define VMX_VCI_CTRL_PROC_EXEC 303
167	/** Cache of secondary processor-based VM-execution controls invalid. */
168	#define VMX_VCI_CTRL_PROC_EXEC2 304
169	/** Cache of exception bitmap invalid. */
170	#define VMX_VCI_CTRL_XCPT_BITMAP 305
171	/** Cache of TSC offset invalid. */
172	#define VMX_VCI_CTRL_TSC_OFFSET 306
173	/** @} */
174
175	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
176	* IGS = Invalid Guest State.
177	* @{
178	*/
179	/** An error occurred while checking invalid-guest-state. */
180	#define VMX_IGS_ERROR 500
181	/** The invalid guest-state checks did not find any reason why. */
182	#define VMX_IGS_REASON_NOT_FOUND 501
183	/** CR0 fixed1 bits invalid. */
184	#define VMX_IGS_CR0_FIXED1 502
185	/** CR0 fixed0 bits invalid. */
186	#define VMX_IGS_CR0_FIXED0 503
187	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
188	#define VMX_IGS_CR0_PG_PE_COMBO 504
189	/** CR4 fixed1 bits invalid. */
190	#define VMX_IGS_CR4_FIXED1 505
191	/** CR4 fixed0 bits invalid. */
192	#define VMX_IGS_CR4_FIXED0 506
193	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
194	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
195	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
196	/** CR0.PG not set for long-mode when not using unrestricted guest. */
197	#define VMX_IGS_CR0_PG_LONGMODE 508
198	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
199	#define VMX_IGS_CR4_PAE_LONGMODE 509
200	/** CR4.PCIDE set for 32-bit guest. */
201	#define VMX_IGS_CR4_PCIDE 510
202	/** VMCS' DR7 reserved bits not set to 0. */
203	#define VMX_IGS_DR7_RESERVED 511
204	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
205	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
206	/** VMCS' EFER MSR reserved bits not set to 0. */
207	#define VMX_IGS_EFER_MSR_RESERVED 513
208	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
209	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
210	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
211	* without unrestricted guest. */
212	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
213	/** CS.Attr.P bit invalid. */
214	#define VMX_IGS_CS_ATTR_P_INVALID 516
215	/** CS.Attr reserved bits not set to 0. */
216	#define VMX_IGS_CS_ATTR_RESERVED 517
217	/** CS.Attr.G bit invalid. */
218	#define VMX_IGS_CS_ATTR_G_INVALID 518
219	/** CS is unusable. */
220	#define VMX_IGS_CS_ATTR_UNUSABLE 519
221	/** CS and SS DPL unequal. */
222	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
223	/** CS and SS DPL mismatch. */
224	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
225	/** CS Attr.Type invalid. */
226	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
227	/** CS and SS RPL unequal. */
228	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
229	/** SS.Attr.DPL and SS RPL unequal. */
230	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
231	/** SS.Attr.DPL invalid for segment type. */
232	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
233	/** SS.Attr.Type invalid. */
234	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
235	/** SS.Attr.P bit invalid. */
236	#define VMX_IGS_SS_ATTR_P_INVALID 527
237	/** SS.Attr reserved bits not set to 0. */
238	#define VMX_IGS_SS_ATTR_RESERVED 528
239	/** SS.Attr.G bit invalid. */
240	#define VMX_IGS_SS_ATTR_G_INVALID 529
241	/** DS.Attr.A bit invalid. */
242	#define VMX_IGS_DS_ATTR_A_INVALID 530
243	/** DS.Attr.P bit invalid. */
244	#define VMX_IGS_DS_ATTR_P_INVALID 531
245	/** DS.Attr.DPL and DS RPL unequal. */
246	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
247	/** DS.Attr reserved bits not set to 0. */
248	#define VMX_IGS_DS_ATTR_RESERVED 533
249	/** DS.Attr.G bit invalid. */
250	#define VMX_IGS_DS_ATTR_G_INVALID 534
251	/** DS.Attr.Type invalid. */
252	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
253	/** ES.Attr.A bit invalid. */
254	#define VMX_IGS_ES_ATTR_A_INVALID 536
255	/** ES.Attr.P bit invalid. */
256	#define VMX_IGS_ES_ATTR_P_INVALID 537
257	/** ES.Attr.DPL and DS RPL unequal. */
258	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
259	/** ES.Attr reserved bits not set to 0. */
260	#define VMX_IGS_ES_ATTR_RESERVED 539
261	/** ES.Attr.G bit invalid. */
262	#define VMX_IGS_ES_ATTR_G_INVALID 540
263	/** ES.Attr.Type invalid. */
264	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
265	/** FS.Attr.A bit invalid. */
266	#define VMX_IGS_FS_ATTR_A_INVALID 542
267	/** FS.Attr.P bit invalid. */
268	#define VMX_IGS_FS_ATTR_P_INVALID 543
269	/** FS.Attr.DPL and DS RPL unequal. */
270	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
271	/** FS.Attr reserved bits not set to 0. */
272	#define VMX_IGS_FS_ATTR_RESERVED 545
273	/** FS.Attr.G bit invalid. */
274	#define VMX_IGS_FS_ATTR_G_INVALID 546
275	/** FS.Attr.Type invalid. */
276	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
277	/** GS.Attr.A bit invalid. */
278	#define VMX_IGS_GS_ATTR_A_INVALID 548
279	/** GS.Attr.P bit invalid. */
280	#define VMX_IGS_GS_ATTR_P_INVALID 549
281	/** GS.Attr.DPL and DS RPL unequal. */
282	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
283	/** GS.Attr reserved bits not set to 0. */
284	#define VMX_IGS_GS_ATTR_RESERVED 551
285	/** GS.Attr.G bit invalid. */
286	#define VMX_IGS_GS_ATTR_G_INVALID 552
287	/** GS.Attr.Type invalid. */
288	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
289	/** V86 mode CS.Base invalid. */
290	#define VMX_IGS_V86_CS_BASE_INVALID 554
291	/** V86 mode CS.Limit invalid. */
292	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
293	/** V86 mode CS.Attr invalid. */
294	#define VMX_IGS_V86_CS_ATTR_INVALID 556
295	/** V86 mode SS.Base invalid. */
296	#define VMX_IGS_V86_SS_BASE_INVALID 557
297	/** V86 mode SS.Limit invalid. */
298	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
299	/** V86 mode SS.Attr invalid. */
300	#define VMX_IGS_V86_SS_ATTR_INVALID 559
301	/** V86 mode DS.Base invalid. */
302	#define VMX_IGS_V86_DS_BASE_INVALID 560
303	/** V86 mode DS.Limit invalid. */
304	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
305	/** V86 mode DS.Attr invalid. */
306	#define VMX_IGS_V86_DS_ATTR_INVALID 562
307	/** V86 mode ES.Base invalid. */
308	#define VMX_IGS_V86_ES_BASE_INVALID 563
309	/** V86 mode ES.Limit invalid. */
310	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
311	/** V86 mode ES.Attr invalid. */
312	#define VMX_IGS_V86_ES_ATTR_INVALID 565
313	/** V86 mode FS.Base invalid. */
314	#define VMX_IGS_V86_FS_BASE_INVALID 566
315	/** V86 mode FS.Limit invalid. */
316	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
317	/** V86 mode FS.Attr invalid. */
318	#define VMX_IGS_V86_FS_ATTR_INVALID 568
319	/** V86 mode GS.Base invalid. */
320	#define VMX_IGS_V86_GS_BASE_INVALID 569
321	/** V86 mode GS.Limit invalid. */
322	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
323	/** V86 mode GS.Attr invalid. */
324	#define VMX_IGS_V86_GS_ATTR_INVALID 571
325	/** Longmode CS.Base invalid. */
326	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
327	/** Longmode SS.Base invalid. */
328	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
329	/** Longmode DS.Base invalid. */
330	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
331	/** Longmode ES.Base invalid. */
332	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
333	/** SYSENTER ESP is not canonical. */
334	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
335	/** SYSENTER EIP is not canonical. */
336	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
337	/** PAT MSR invalid. */
338	#define VMX_IGS_PAT_MSR_INVALID 578
339	/** PAT MSR reserved bits not set to 0. */
340	#define VMX_IGS_PAT_MSR_RESERVED 579
341	/** GDTR.Base is not canonical. */
342	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
343	/** IDTR.Base is not canonical. */
344	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
345	/** GDTR.Limit invalid. */
346	#define VMX_IGS_GDTR_LIMIT_INVALID 582
347	/** IDTR.Limit invalid. */
348	#define VMX_IGS_IDTR_LIMIT_INVALID 583
349	/** Longmode RIP is invalid. */
350	#define VMX_IGS_LONGMODE_RIP_INVALID 584
351	/** RFLAGS reserved bits not set to 0. */
352	#define VMX_IGS_RFLAGS_RESERVED 585
353	/** RFLAGS RA1 reserved bits not set to 1. */
354	#define VMX_IGS_RFLAGS_RESERVED1 586
355	/** RFLAGS.VM (V86 mode) invalid. */
356	#define VMX_IGS_RFLAGS_VM_INVALID 587
357	/** RFLAGS.IF invalid. */
358	#define VMX_IGS_RFLAGS_IF_INVALID 588
359	/** Activity state invalid. */
360	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
361	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
362	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
363	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
364	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
365	/** Activity state SIPI WAIT invalid. */
366	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
367	/** Interruptibility state reserved bits not set to 0. */
368	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
369	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
370	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
371	/** Interruptibility state block-by-STI invalid for EFLAGS. */
372	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
373	/** Interruptibility state invalid while trying to deliver external
374	* interrupt. */
375	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
376	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
377	* NMI. */
378	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
379	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
380	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
381	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
382	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
383	/** Interruptibility state block-by-STI (maybe) invalid when trying to
384	* deliver an NMI. */
385	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
386	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
387	* active. */
388	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
389	/** Pending debug exceptions reserved bits not set to 0. */
390	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
391	/** Longmode pending debug exceptions reserved bits not set to 0. */
392	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
393	/** Pending debug exceptions.BS bit is not set when it should be. */
394	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
395	/** Pending debug exceptions.BS bit is not clear when it should be. */
396	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
397	/** VMCS link pointer reserved bits not set to 0. */
398	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
399	/** TR cannot index into LDT, TI bit MBZ. */
400	#define VMX_IGS_TR_TI_INVALID 607
401	/** LDTR cannot index into LDT. TI bit MBZ. */
402	#define VMX_IGS_LDTR_TI_INVALID 608
403	/** TR.Base is not canonical. */
404	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
405	/** FS.Base is not canonical. */
406	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
407	/** GS.Base is not canonical. */
408	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
409	/** LDTR.Base is not canonical. */
410	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
411	/** TR is unusable. */
412	#define VMX_IGS_TR_ATTR_UNUSABLE 613
413	/** TR.Attr.S bit invalid. */
414	#define VMX_IGS_TR_ATTR_S_INVALID 614
415	/** TR is not present. */
416	#define VMX_IGS_TR_ATTR_P_INVALID 615
417	/** TR.Attr reserved bits not set to 0. */
418	#define VMX_IGS_TR_ATTR_RESERVED 616
419	/** TR.Attr.G bit invalid. */
420	#define VMX_IGS_TR_ATTR_G_INVALID 617
421	/** Longmode TR.Attr.Type invalid. */
422	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
423	/** TR.Attr.Type invalid. */
424	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
425	/** CS.Attr.S invalid. */
426	#define VMX_IGS_CS_ATTR_S_INVALID 620
427	/** CS.Attr.DPL invalid. */
428	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
429	/** PAE PDPTE reserved bits not set to 0. */
430	#define VMX_IGS_PAE_PDPTE_RESERVED 623
431	/** @} */
432
433	/** @name VMX VMCS-Read cache indices.
434	* @{
435	*/
436	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
437	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
438	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
439	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
440	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
441	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
442	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
443	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
444	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
445	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
446	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
447	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
448	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
449	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
450	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
451	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
452	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
453	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
454	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
455	/** @} */
456
457	/** @name VMX EPT paging structures
458	* @{
459	*/
460
461	/**
462	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
463	*/
464	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
465
466	/**
467	* EPT Page Directory Pointer Entry. Bit view.
468	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
469	* this did cause trouble with one compiler/version).
470	*/
471	typedef struct EPTPML4EBITS
472	{
473	/** Present bit. */
474	RT_GCC_EXTENSION uint64_t u1Present : 1;
475	/** Writable bit. */
476	RT_GCC_EXTENSION uint64_t u1Write : 1;
477	/** Executable bit. */
478	RT_GCC_EXTENSION uint64_t u1Execute : 1;
479	/** Reserved (must be 0). */
480	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
481	/** Available for software. */
482	RT_GCC_EXTENSION uint64_t u4Available : 4;
483	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
484	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
485	/** Available for software. */
486	RT_GCC_EXTENSION uint64_t u12Available : 12;
487	} EPTPML4EBITS;
488	AssertCompileSize(EPTPML4EBITS, 8);
489
490	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
491	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
492	/** The page shift to get the PML4 index. */
493	#define EPT_PML4_SHIFT X86_PML4_SHIFT
494	/** The PML4 index mask (apply to a shifted page address). */
495	#define EPT_PML4_MASK X86_PML4_MASK
496
497	/**
498	* EPT PML4E.
499	*/
500	typedef union EPTPML4E
501	{
502	/** Normal view. */
503	EPTPML4EBITS n;
504	/** Unsigned integer view. */
505	X86PGPAEUINT u;
506	/** 64 bit unsigned integer view. */
507	uint64_t au64[1];
508	/** 32 bit unsigned integer view. */
509	uint32_t au32[2];
510	} EPTPML4E;
511	AssertCompileSize(EPTPML4E, 8);
512	/** Pointer to a PML4 table entry. */
513	typedef EPTPML4E *PEPTPML4E;
514	/** Pointer to a const PML4 table entry. */
515	typedef const EPTPML4E *PCEPTPML4E;
516
517	/**
518	* EPT PML4 Table.
519	*/
520	typedef struct EPTPML4
521	{
522	EPTPML4E a[EPT_PG_ENTRIES];
523	} EPTPML4;
524	AssertCompileSize(EPTPML4, 0x1000);
525	/** Pointer to an EPT PML4 Table. */
526	typedef EPTPML4 *PEPTPML4;
527	/** Pointer to a const EPT PML4 Table. */
528	typedef const EPTPML4 *PCEPTPML4;
529
530	/**
531	* EPT Page Directory Pointer Entry. Bit view.
532	*/
533	typedef struct EPTPDPTEBITS
534	{
535	/** Present bit. */
536	RT_GCC_EXTENSION uint64_t u1Present : 1;
537	/** Writable bit. */
538	RT_GCC_EXTENSION uint64_t u1Write : 1;
539	/** Executable bit. */
540	RT_GCC_EXTENSION uint64_t u1Execute : 1;
541	/** Reserved (must be 0). */
542	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
543	/** Available for software. */
544	RT_GCC_EXTENSION uint64_t u4Available : 4;
545	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
546	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
547	/** Available for software. */
548	RT_GCC_EXTENSION uint64_t u12Available : 12;
549	} EPTPDPTEBITS;
550	AssertCompileSize(EPTPDPTEBITS, 8);
551
552	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
553	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
554	/** The page shift to get the PDPT index. */
555	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
556	/** The PDPT index mask (apply to a shifted page address). */
557	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
558
559	/**
560	* EPT Page Directory Pointer.
561	*/
562	typedef union EPTPDPTE
563	{
564	/** Normal view. */
565	EPTPDPTEBITS n;
566	/** Unsigned integer view. */
567	X86PGPAEUINT u;
568	/** 64 bit unsigned integer view. */
569	uint64_t au64[1];
570	/** 32 bit unsigned integer view. */
571	uint32_t au32[2];
572	} EPTPDPTE;
573	AssertCompileSize(EPTPDPTE, 8);
574	/** Pointer to an EPT Page Directory Pointer Entry. */
575	typedef EPTPDPTE *PEPTPDPTE;
576	/** Pointer to a const EPT Page Directory Pointer Entry. */
577	typedef const EPTPDPTE *PCEPTPDPTE;
578
579	/**
580	* EPT Page Directory Pointer Table.
581	*/
582	typedef struct EPTPDPT
583	{
584	EPTPDPTE a[EPT_PG_ENTRIES];
585	} EPTPDPT;
586	AssertCompileSize(EPTPDPT, 0x1000);
587	/** Pointer to an EPT Page Directory Pointer Table. */
588	typedef EPTPDPT *PEPTPDPT;
589	/** Pointer to a const EPT Page Directory Pointer Table. */
590	typedef const EPTPDPT *PCEPTPDPT;
591
592	/**
593	* EPT Page Directory Table Entry. Bit view.
594	*/
595	typedef struct EPTPDEBITS
596	{
597	/** Present bit. */
598	RT_GCC_EXTENSION uint64_t u1Present : 1;
599	/** Writable bit. */
600	RT_GCC_EXTENSION uint64_t u1Write : 1;
601	/** Executable bit. */
602	RT_GCC_EXTENSION uint64_t u1Execute : 1;
603	/** Reserved (must be 0). */
604	RT_GCC_EXTENSION uint64_t u4Reserved : 4;
605	/** Big page (must be 0 here). */
606	RT_GCC_EXTENSION uint64_t u1Size : 1;
607	/** Available for software. */
608	RT_GCC_EXTENSION uint64_t u4Available : 4;
609	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
610	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
611	/** Available for software. */
612	RT_GCC_EXTENSION uint64_t u12Available : 12;
613	} EPTPDEBITS;
614	AssertCompileSize(EPTPDEBITS, 8);
615
616	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
617	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
618	/** The page shift to get the PD index. */
619	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
620	/** The PD index mask (apply to a shifted page address). */
621	#define EPT_PD_MASK X86_PD_PAE_MASK
622
623	/**
624	* EPT 2MB Page Directory Table Entry. Bit view.
625	*/
626	typedef struct EPTPDE2MBITS
627	{
628	/** Present bit. */
629	RT_GCC_EXTENSION uint64_t u1Present : 1;
630	/** Writable bit. */
631	RT_GCC_EXTENSION uint64_t u1Write : 1;
632	/** Executable bit. */
633	RT_GCC_EXTENSION uint64_t u1Execute : 1;
634	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
635	RT_GCC_EXTENSION uint64_t u3EMT : 3;
636	/** Ignore PAT memory type */
637	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
638	/** Big page (must be 1 here). */
639	RT_GCC_EXTENSION uint64_t u1Size : 1;
640	/** Available for software. */
641	RT_GCC_EXTENSION uint64_t u4Available : 4;
642	/** Reserved (must be 0). */
643	RT_GCC_EXTENSION uint64_t u9Reserved : 9;
644	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
645	RT_GCC_EXTENSION uint64_t u31PhysAddr : 31;
646	/** Available for software. */
647	RT_GCC_EXTENSION uint64_t u12Available : 12;
648	} EPTPDE2MBITS;
649	AssertCompileSize(EPTPDE2MBITS, 8);
650
651	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
652	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
653
654	/**
655	* EPT Page Directory Table Entry.
656	*/
657	typedef union EPTPDE
658	{
659	/** Normal view. */
660	EPTPDEBITS n;
661	/** 2MB view (big). */
662	EPTPDE2MBITS b;
663	/** Unsigned integer view. */
664	X86PGPAEUINT u;
665	/** 64 bit unsigned integer view. */
666	uint64_t au64[1];
667	/** 32 bit unsigned integer view. */
668	uint32_t au32[2];
669	} EPTPDE;
670	AssertCompileSize(EPTPDE, 8);
671	/** Pointer to an EPT Page Directory Table Entry. */
672	typedef EPTPDE *PEPTPDE;
673	/** Pointer to a const EPT Page Directory Table Entry. */
674	typedef const EPTPDE *PCEPTPDE;
675
676	/**
677	* EPT Page Directory Table.
678	*/
679	typedef struct EPTPD
680	{
681	EPTPDE a[EPT_PG_ENTRIES];
682	} EPTPD;
683	AssertCompileSize(EPTPD, 0x1000);
684	/** Pointer to an EPT Page Directory Table. */
685	typedef EPTPD *PEPTPD;
686	/** Pointer to a const EPT Page Directory Table. */
687	typedef const EPTPD *PCEPTPD;
688
689	/**
690	* EPT Page Table Entry. Bit view.
691	*/
692	typedef struct EPTPTEBITS
693	{
694	/** 0 - Present bit.
695	* @remarks This is a convenience "misnomer". The bit actually indicates read access
696	* and the CPU will consider an entry with any of the first three bits set
697	* as present. Since all our valid entries will have this bit set, it can
698	* be used as a present indicator and allow some code sharing. */
699	RT_GCC_EXTENSION uint64_t u1Present : 1;
700	/** 1 - Writable bit. */
701	RT_GCC_EXTENSION uint64_t u1Write : 1;
702	/** 2 - Executable bit. */
703	RT_GCC_EXTENSION uint64_t u1Execute : 1;
704	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
705	RT_GCC_EXTENSION uint64_t u3EMT : 3;
706	/** 6 - Ignore PAT memory type */
707	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
708	/** 11:7 - Available for software. */
709	RT_GCC_EXTENSION uint64_t u5Available : 5;
710	/** 51:12 - Physical address of page. Restricted by maximum physical
711	* address width of the cpu. */
712	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
713	/** 63:52 - Available for software. */
714	RT_GCC_EXTENSION uint64_t u12Available : 12;
715	} EPTPTEBITS;
716	AssertCompileSize(EPTPTEBITS, 8);
717
718	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
719	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
720	/** The page shift to get the EPT PTE index. */
721	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
722	/** The EPT PT index mask (apply to a shifted page address). */
723	#define EPT_PT_MASK X86_PT_PAE_MASK
724
725	/**
726	* EPT Page Table Entry.
727	*/
728	typedef union EPTPTE
729	{
730	/** Normal view. */
731	EPTPTEBITS n;
732	/** Unsigned integer view. */
733	X86PGPAEUINT u;
734	/** 64 bit unsigned integer view. */
735	uint64_t au64[1];
736	/** 32 bit unsigned integer view. */
737	uint32_t au32[2];
738	} EPTPTE;
739	AssertCompileSize(EPTPTE, 8);
740	/** Pointer to an EPT Page Directory Table Entry. */
741	typedef EPTPTE *PEPTPTE;
742	/** Pointer to a const EPT Page Directory Table Entry. */
743	typedef const EPTPTE *PCEPTPTE;
744
745	/**
746	* EPT Page Table.
747	*/
748	typedef struct EPTPT
749	{
750	EPTPTE a[EPT_PG_ENTRIES];
751	} EPTPT;
752	AssertCompileSize(EPTPT, 0x1000);
753	/** Pointer to an extended page table. */
754	typedef EPTPT *PEPTPT;
755	/** Pointer to a const extended table. */
756	typedef const EPTPT *PCEPTPT;
757
758	/** @} */
759
760	/**
761	* VMX VPID flush types.
762	* @note Valid enum members are in accordance to the VT-x spec.
763	*/
764	typedef enum
765	{
766	/** Invalidate a specific page. */
767	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
768	/** Invalidate one context (specific VPID). */
769	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
770	/** Invalidate all contexts (all VPIDs). */
771	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
772	/** Invalidate a single VPID context retaining global mappings. */
773	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
774	/** Unsupported by VirtualBox. */
775	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
776	/** Unsupported by CPU. */
777	VMXTLBFLUSHVPID_NONE = 0xbad1
778	} VMXTLBFLUSHVPID;
779	AssertCompileSize(VMXTLBFLUSHVPID, 4);
780
781	/**
782	* VMX EPT flush types.
783	* @note Valid enums values are in accordance to the VT-x spec.
784	*/
785	typedef enum
786	{
787	/** Invalidate one context (specific EPT). */
788	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
789	/* Invalidate all contexts (all EPTs) */
790	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
791	/** Unsupported by VirtualBox. */
792	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
793	/** Unsupported by CPU. */
794	VMXTLBFLUSHEPT_NONE = 0xbad1
795	} VMXTLBFLUSHEPT;
796	AssertCompileSize(VMXTLBFLUSHEPT, 4);
797
798	/**
799	* VMX Posted Interrupt Descriptor.
800	* In accordance to the VT-x spec.
801	*/
802	typedef struct VMXPOSTEDINTRDESC
803	{
804	uint32_t aVectorBitmap[8];
805	uint32_t fOutstandingNotification : 1;
806	uint32_t uReserved0 : 31;
807	uint8_t au8Reserved0[28];
808	} VMXPOSTEDINTRDESC;
809	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
810	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
811	/** Pointer to a posted interrupt descriptor. */
812	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
813	/** Pointer to a const posted interrupt descriptor. */
814	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
815
816	/**
817	* VMX VMCS revision identifier.
818	*/
819	typedef union
820	{
821	struct
822	{
823	/** Revision identifier. */
824	uint32_t u31RevisionId : 31;
825	/** Whether this is a shadow VMCS. */
826	uint32_t fIsShadowVmcs : 1;
827	} n;
828	/* The unsigned integer view. */
829	uint32_t u;
830	} VMXVMCSREVID;
831	AssertCompileSize(VMXVMCSREVID, 4);
832	/** Pointer to the VMXVMCSREVID union. */
833	typedef VMXVMCSREVID *PVMXVMCSREVID;
834	/** Pointer to a const VMXVMCSREVID union. */
835	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
836
837	/**
838	* VMX VM-exit instruction information.
839	*/
840	typedef union
841	{
842	/** Plain unsigned int representation. */
843	uint32_t u;
844
845	/** INS and OUTS information. */
846	struct
847	{
848	uint32_t u7Reserved0 : 7;
849	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
850	uint32_t u3AddrSize : 3;
851	uint32_t u5Reserved1 : 5;
852	/** The segment register (X86_SREG_XXX). */
853	uint32_t iSegReg : 3;
854	uint32_t uReserved2 : 14;
855	} StrIo;
856
857	/** INVEPT, INVPCID, INVVPID information. */
858	struct
859	{
860	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
861	uint32_t u2Scaling : 2;
862	uint32_t u5Undef0 : 5;
863	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
864	uint32_t u3AddrSize : 3;
865	/** Cleared to 0. */
866	uint32_t u1Cleared0 : 1;
867	uint32_t u4Undef0 : 4;
868	/** The segment register (X86_SREG_XXX). */
869	uint32_t iSegReg : 3;
870	/** The index register (X86_GREG_XXX). */
871	uint32_t iIdxReg : 4;
872	/** Set if index register is invalid. */
873	uint32_t fIdxRegInvalid : 1;
874	/** The base register (X86_GREG_XXX). */
875	uint32_t iBaseReg : 4;
876	/** Set if base register is invalid. */
877	uint32_t fBaseRegInvalid : 1;
878	/** Register 2 (X86_GREG_XXX). */
879	uint32_t iReg2 : 4;
880	} Inv;
881
882	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
883	struct
884	{
885	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
886	uint32_t u2Scaling : 2;
887	uint32_t u5Reserved0 : 5;
888	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
889	uint32_t u3AddrSize : 3;
890	/** Cleared to 0. */
891	uint32_t u1Cleared0 : 1;
892	uint32_t u4Reserved0 : 4;
893	/** The segment register (X86_SREG_XXX). */
894	uint32_t iSegReg : 3;
895	/** The index register (X86_GREG_XXX). */
896	uint32_t iIdxReg : 4;
897	/** Set if index register is invalid. */
898	uint32_t fIdxRegInvalid : 1;
899	/** The base register (X86_GREG_XXX). */
900	uint32_t iBaseReg : 4;
901	/** Set if base register is invalid. */
902	uint32_t fBaseRegInvalid : 1;
903	/** Register 2 (X86_GREG_XXX). */
904	uint32_t iReg2 : 4;
905	} VmxXsave;
906
907	/** LIDT, LGDT, SIDT, SGDT information. */
908	struct
909	{
910	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
911	uint32_t u2Scaling : 2;
912	uint32_t u5Undef0 : 5;
913	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
914	uint32_t u3AddrSize : 3;
915	/** Always cleared to 0. */
916	uint32_t u1Cleared0 : 1;
917	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
918	uint32_t uOperandSize : 1;
919	uint32_t u3Undef0 : 3;
920	/** The segment register (X86_SREG_XXX). */
921	uint32_t iSegReg : 3;
922	/** The index register (X86_GREG_XXX). */
923	uint32_t iIdxReg : 4;
924	/** Set if index register is invalid. */
925	uint32_t fIdxRegInvalid : 1;
926	/** The base register (X86_GREG_XXX). */
927	uint32_t iBaseReg : 4;
928	/** Set if base register is invalid. */
929	uint32_t fBaseRegInvalid : 1;
930	/** Instruction identity (VMX_INSTR_ID_XXX). */
931	uint32_t u2InstrId : 2;
932	uint32_t u2Undef0 : 2;
933	} GdtIdt;
934
935	/** LLDT, LTR, SLDT, STR information. */
936	struct
937	{
938	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
939	uint32_t u2Scaling : 2;
940	uint32_t u1Undef0 : 1;
941	/** Register 1 (X86_GREG_XXX). */
942	uint32_t iReg1 : 4;
943	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
944	uint32_t u3AddrSize : 3;
945	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
946	uint32_t fIsRegOperand : 1;
947	uint32_t u4Undef0 : 4;
948	/** The segment register (X86_SREG_XXX). */
949	uint32_t iSegReg : 3;
950	/** The index register (X86_GREG_XXX). */
951	uint32_t iIdxReg : 4;
952	/** Set if index register is invalid. */
953	uint32_t fIdxRegInvalid : 1;
954	/** The base register (X86_GREG_XXX). */
955	uint32_t iBaseReg : 4;
956	/** Set if base register is invalid. */
957	uint32_t fBaseRegInvalid : 1;
958	/** Instruction identity (VMX_INSTR_ID_XXX). */
959	uint32_t u2InstrId : 2;
960	uint32_t u2Undef0 : 2;
961	} LdtTr;
962
963	/** RDRAND, RDSEED information. */
964	struct
965	{
966	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
967	uint32_t u2Undef0 : 2;
968	/** Destination register (X86_GREG_XXX). */
969	uint32_t iReg1 : 4;
970	uint32_t u4Undef0 : 4;
971	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
972	uint32_t u2OperandSize : 2;
973	uint32_t u19Def0 : 20;
974	} RdrandRdseed;
975
976	/** VMREAD, VMWRITE information. */
977	struct
978	{
979	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
980	uint32_t u2Scaling : 2;
981	uint32_t u1Undef0 : 1;
982	/** Register 1 (X86_GREG_XXX). */
983	uint32_t iReg1 : 4;
984	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
985	uint32_t u3AddrSize : 3;
986	/** Memory or register operand. */
987	uint32_t fIsRegOperand : 1;
988	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
989	uint32_t u4Undef0 : 4;
990	/** The segment register (X86_SREG_XXX). */
991	uint32_t iSegReg : 3;
992	/** The index register (X86_GREG_XXX). */
993	uint32_t iIdxReg : 4;
994	/** Set if index register is invalid. */
995	uint32_t fIdxRegInvalid : 1;
996	/** The base register (X86_GREG_XXX). */
997	uint32_t iBaseReg : 4;
998	/** Set if base register is invalid. */
999	uint32_t fBaseRegInvalid : 1;
1000	/** Register 2 (X86_GREG_XXX). */
1001	uint32_t iReg2 : 4;
1002	} VmreadVmwrite;
1003
1004	/** This is a combination field of all instruction information. Note! Not all field
1005	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1006	* specialized fields are overwritten by their generic counterparts (e.g. no
1007	* instruction identity field). */
1008	struct
1009	{
1010	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1011	uint32_t u2Scaling : 2;
1012	uint32_t u1Undef0 : 1;
1013	/** Register 1 (X86_GREG_XXX). */
1014	uint32_t iReg1 : 4;
1015	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1016	uint32_t u3AddrSize : 3;
1017	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1018	uint32_t fIsRegOperand : 1;
1019	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1020	uint32_t uOperandSize : 2;
1021	uint32_t u2Undef0 : 2;
1022	/** The segment register (X86_SREG_XXX). */
1023	uint32_t iSegReg : 3;
1024	/** The index register (X86_GREG_XXX). */
1025	uint32_t iIdxReg : 4;
1026	/** Set if index register is invalid. */
1027	uint32_t fIdxRegInvalid : 1;
1028	/** The base register (X86_GREG_XXX). */
1029	uint32_t iBaseReg : 4;
1030	/** Set if base register is invalid. */
1031	uint32_t fBaseRegInvalid : 1;
1032	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1033	uint32_t iReg2 : 4;
1034	} All;
1035	} VMXEXITINSTRINFO;
1036	AssertCompileSize(VMXEXITINSTRINFO, 4);
1037	/** Pointer to a VMX VM-exit instruction info. struct. */
1038	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1039	/** Pointer to a const VMX VM-exit instruction info. struct. */
1040	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1041
1042
1043	/** @name VM-entry failure reported in VM-exit qualification.
1044	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1045	* @{
1046	*/
1047	/** No errors during VM-entry. */
1048	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1049	/** Not used. */
1050	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1051	/** Error while loading PDPTEs. */
1052	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1053	/** NMI injection when blocking-by-STI is set. */
1054	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1055	/** Invalid VMCS link pointer. */
1056	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1057	/** @} */
1058
1059
1060	/** @name VMXMSRPM_XXX - VMX MSR-bitmap permissions.
1061	* These are not in accordance to the Intel spec. but used internally by VirtualBox.
1062	* @{ */
1063	/** Guest software reads of this MSR must not cause a VM-exit. */
1064	#define VMXMSRPM_ALLOW_RD RT_BIT(0)
1065	/** Guest software reads of this MSR must cause a VM-exit. */
1066	#define VMXMSRPM_EXIT_RD RT_BIT(1)
1067	/** Guest software writes to this MSR must not cause a VM-exit. */
1068	#define VMXMSRPM_ALLOW_WR RT_BIT(2)
1069	/** Guest software writes to this MSR must cause a VM-exit. */
1070	#define VMXMSRPM_EXIT_WR RT_BIT(3)
1071	/** Guest software reads or writes of this MSR must not cause a VM-exit. */
1072	#define VMXMSRPM_ALLOW_RD_WR (VMXMSRPM_ALLOW_RD \| VMXMSRPM_ALLOW_WR)
1073	/** Guest software reads or writes of this MSR must cause a VM-exit. */
1074	#define VMXMSRPM_EXIT_RD_WR (VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR)
1075	/** Mask of valid MSR read permissions. */
1076	#define VMXMSRPM_RD_MASK (VMXMSRPM_ALLOW_RD \| VMXMSRPM_EXIT_RD)
1077	/** Mask of valid MSR write permissions. */
1078	#define VMXMSRPM_WR_MASK (VMXMSRPM_ALLOW_WR \| VMXMSRPM_EXIT_WR)
1079	/** Mask of valid MSR permissions. */
1080	#define VMXMSRPM_MASK (VMXMSRPM_RD_MASK \| VMXMSRPM_WR_MASK)
1081	/** */
1082	/** Gets whether the MSR permission is valid or not. */
1083	#define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \
1084	&& ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \
1085	&& ((a_Msrpm) & VMXMSRPM_RD_MASK) != VMXMSRPM_RD_MASK \
1086	&& ((a_Msrpm) & VMXMSRPM_WR_MASK) != VMXMSRPM_WR_MASK)
1087	/** @} */
1088
1089	/**
1090	* VMX MSR autoload/store slot.
1091	* In accordance to the VT-x spec.
1092	*/
1093	typedef struct VMXAUTOMSR
1094	{
1095	/** The MSR Id. */
1096	uint32_t u32Msr;
1097	/** Reserved (MBZ). */
1098	uint32_t u32Reserved;
1099	/** The MSR value. */
1100	uint64_t u64Value;
1101	} VMXAUTOMSR;
1102	AssertCompileSize(VMXAUTOMSR, 16);
1103	/** Pointer to an MSR load/store element. */
1104	typedef VMXAUTOMSR *PVMXAUTOMSR;
1105	/** Pointer to a const MSR load/store element. */
1106	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1107
1108	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1109	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1110
1111	/**
1112	* VMX tagged-TLB flush types.
1113	*/
1114	typedef enum
1115	{
1116	VMXTLBFLUSHTYPE_EPT,
1117	VMXTLBFLUSHTYPE_VPID,
1118	VMXTLBFLUSHTYPE_EPT_VPID,
1119	VMXTLBFLUSHTYPE_NONE
1120	} VMXTLBFLUSHTYPE;
1121	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1122	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1123	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1124	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1125
1126	/**
1127	* VMX controls MSR.
1128	*/
1129	typedef union
1130	{
1131	struct
1132	{
1133	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1134	uint32_t allowed0;
1135	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1136	* controls. */
1137	uint32_t allowed1;
1138	} n;
1139	uint64_t u;
1140	} VMXCTLSMSR;
1141	AssertCompileSize(VMXCTLSMSR, 8);
1142	/** Pointer to a VMXCTLSMSR union. */
1143	typedef VMXCTLSMSR *PVMXCTLSMSR;
1144	/** Pointer to a const VMXCTLSMSR union. */
1145	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1146
1147	/**
1148	* VMX MSRs.
1149	*/
1150	typedef struct VMXMSRS
1151	{
1152	/** VMX/SMX Feature control. */
1153	uint64_t u64FeatCtrl;
1154	/** Basic information. */
1155	uint64_t u64Basic;
1156	/** Pin-based VM-execution controls. */
1157	VMXCTLSMSR PinCtls;
1158	/** Processor-based VM-execution controls. */
1159	VMXCTLSMSR ProcCtls;
1160	/** Secondary processor-based VM-execution controls. */
1161	VMXCTLSMSR ProcCtls2;
1162	/** VM-exit controls. */
1163	VMXCTLSMSR ExitCtls;
1164	/** VM-entry controls. */
1165	VMXCTLSMSR EntryCtls;
1166	/** True pin-based VM-execution controls. */
1167	VMXCTLSMSR TruePinCtls;
1168	/** True processor-based VM-execution controls. */
1169	VMXCTLSMSR TrueProcCtls;
1170	/** True VM-entry controls. */
1171	VMXCTLSMSR TrueEntryCtls;
1172	/** True VM-exit controls. */
1173	VMXCTLSMSR TrueExitCtls;
1174	/** Miscellaneous data. */
1175	uint64_t u64Misc;
1176	/** CR0 fixed-0 - bits set here must be set in VMX operation. */
1177	uint64_t u64Cr0Fixed0;
1178	/** CR0 fixed-1 - bits clear here must be clear in VMX operation. */
1179	uint64_t u64Cr0Fixed1;
1180	/** CR4 fixed-0 - bits set here must be set in VMX operation. */
1181	uint64_t u64Cr4Fixed0;
1182	/** CR4 fixed-1 - bits clear here must be clear in VMX operation. */
1183	uint64_t u64Cr4Fixed1;
1184	/** VMCS enumeration. */
1185	uint64_t u64VmcsEnum;
1186	/** VM Functions. */
1187	uint64_t u64VmFunc;
1188	/** EPT, VPID capabilities. */
1189	uint64_t u64EptVpidCaps;
1190	/** Reserved for future. */
1191	uint64_t a_u64Reserved[9];
1192	} VMXMSRS;
1193	AssertCompileSizeAlignment(VMXMSRS, 8);
1194	AssertCompileSize(VMXMSRS, 224);
1195	/** Pointer to a VMXMSRS struct. */
1196	typedef VMXMSRS *PVMXMSRS;
1197	/** Pointer to a const VMXMSRS struct. */
1198	typedef const VMXMSRS *PCVMXMSRS;
1199
1200
1201	/** @name VMX Basic Exit Reasons.
1202	* @{
1203	*/
1204	/** -1 Invalid exit code */
1205	#define VMX_EXIT_INVALID (-1)
1206	/** 0 Exception or non-maskable interrupt (NMI). */
1207	#define VMX_EXIT_XCPT_OR_NMI 0
1208	/** 1 External interrupt. */
1209	#define VMX_EXIT_EXT_INT 1
1210	/** 2 Triple fault. */
1211	#define VMX_EXIT_TRIPLE_FAULT 2
1212	/** 3 INIT signal. */
1213	#define VMX_EXIT_INIT_SIGNAL 3
1214	/** 4 Start-up IPI (SIPI). */
1215	#define VMX_EXIT_SIPI 4
1216	/** 5 I/O system-management interrupt (SMI). */
1217	#define VMX_EXIT_IO_SMI 5
1218	/** 6 Other SMI. */
1219	#define VMX_EXIT_SMI 6
1220	/** 7 Interrupt window exiting. */
1221	#define VMX_EXIT_INT_WINDOW 7
1222	/** 8 NMI window exiting. */
1223	#define VMX_EXIT_NMI_WINDOW 8
1224	/** 9 Task switch. */
1225	#define VMX_EXIT_TASK_SWITCH 9
1226	/** 10 Guest software attempted to execute CPUID. */
1227	#define VMX_EXIT_CPUID 10
1228	/** 11 Guest software attempted to execute GETSEC. */
1229	#define VMX_EXIT_GETSEC 11
1230	/** 12 Guest software attempted to execute HLT. */
1231	#define VMX_EXIT_HLT 12
1232	/** 13 Guest software attempted to execute INVD. */
1233	#define VMX_EXIT_INVD 13
1234	/** 14 Guest software attempted to execute INVLPG. */
1235	#define VMX_EXIT_INVLPG 14
1236	/** 15 Guest software attempted to execute RDPMC. */
1237	#define VMX_EXIT_RDPMC 15
1238	/** 16 Guest software attempted to execute RDTSC. */
1239	#define VMX_EXIT_RDTSC 16
1240	/** 17 Guest software attempted to execute RSM in SMM. */
1241	#define VMX_EXIT_RSM 17
1242	/** 18 Guest software executed VMCALL. */
1243	#define VMX_EXIT_VMCALL 18
1244	/** 19 Guest software executed VMCLEAR. */
1245	#define VMX_EXIT_VMCLEAR 19
1246	/** 20 Guest software executed VMLAUNCH. */
1247	#define VMX_EXIT_VMLAUNCH 20
1248	/** 21 Guest software executed VMPTRLD. */
1249	#define VMX_EXIT_VMPTRLD 21
1250	/** 22 Guest software executed VMPTRST. */
1251	#define VMX_EXIT_VMPTRST 22
1252	/** 23 Guest software executed VMREAD. */
1253	#define VMX_EXIT_VMREAD 23
1254	/** 24 Guest software executed VMRESUME. */
1255	#define VMX_EXIT_VMRESUME 24
1256	/** 25 Guest software executed VMWRITE. */
1257	#define VMX_EXIT_VMWRITE 25
1258	/** 26 Guest software executed VMXOFF. */
1259	#define VMX_EXIT_VMXOFF 26
1260	/** 27 Guest software executed VMXON. */
1261	#define VMX_EXIT_VMXON 27
1262	/** 28 Control-register accesses. */
1263	#define VMX_EXIT_MOV_CRX 28
1264	/** 29 Debug-register accesses. */
1265	#define VMX_EXIT_MOV_DRX 29
1266	/** 30 I/O instruction. */
1267	#define VMX_EXIT_IO_INSTR 30
1268	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1269	#define VMX_EXIT_RDMSR 31
1270	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1271	#define VMX_EXIT_WRMSR 32
1272	/** 33 VM-entry failure due to invalid guest state. */
1273	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1274	/** 34 VM-entry failure due to MSR loading. */
1275	#define VMX_EXIT_ERR_MSR_LOAD 34
1276	/** 36 Guest software executed MWAIT. */
1277	#define VMX_EXIT_MWAIT 36
1278	/** 37 VM-exit due to monitor trap flag. */
1279	#define VMX_EXIT_MTF 37
1280	/** 39 Guest software attempted to execute MONITOR. */
1281	#define VMX_EXIT_MONITOR 39
1282	/** 40 Guest software attempted to execute PAUSE. */
1283	#define VMX_EXIT_PAUSE 40
1284	/** 41 VM-entry failure due to machine-check. */
1285	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1286	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1287	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1288	/** 44 APIC access. Guest software attempted to access memory at a physical
1289	* address on the APIC-access page. */
1290	#define VMX_EXIT_APIC_ACCESS 44
1291	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1292	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1293	#define VMX_EXIT_VIRTUALIZED_EOI 45
1294	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1295	* SGDT, or SIDT. */
1296	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1297	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1298	* SLDT, or STR. */
1299	#define VMX_EXIT_LDTR_TR_ACCESS 47
1300	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1301	* was disallowed by the configuration of the EPT paging structures. */
1302	#define VMX_EXIT_EPT_VIOLATION 48
1303	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1304	* address encountered a misconfigured EPT paging-structure entry. */
1305	#define VMX_EXIT_EPT_MISCONFIG 49
1306	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1307	#define VMX_EXIT_INVEPT 50
1308	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1309	#define VMX_EXIT_RDTSCP 51
1310	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1311	#define VMX_EXIT_PREEMPT_TIMER 52
1312	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1313	#define VMX_EXIT_INVVPID 53
1314	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1315	#define VMX_EXIT_WBINVD 54
1316	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1317	#define VMX_EXIT_XSETBV 55
1318	/** 56 APIC write. Guest completed write to virtual-APIC. */
1319	#define VMX_EXIT_APIC_WRITE 56
1320	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1321	#define VMX_EXIT_RDRAND 57
1322	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1323	#define VMX_EXIT_INVPCID 58
1324	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1325	#define VMX_EXIT_VMFUNC 59
1326	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1327	#define VMX_EXIT_ENCLS 60
1328	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1329	* enabled. */
1330	#define VMX_EXIT_RDSEED 61
1331	/** 62 - Page-modification log full. */
1332	#define VMX_EXIT_PML_FULL 62
1333	/** 63 - XSAVES. Guest software attempted to execute XSAVES and exiting was
1334	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1335	#define VMX_EXIT_XSAVES 63
1336	/** 64 - XRSTORS. Guest software attempted to execute XRSTORS and exiting
1337	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1338	#define VMX_EXIT_XRSTORS 64
1339	/** 66 - SPP-related event. Attempt to determine an access' sub-page write
1340	* permission encountered an SPP miss or misconfiguration. */
1341	#define VMX_EXIT_SPP_EVENT 66
1342	/* 67 - UMWAIT. Guest software attempted to execute UMWAIT and exiting was enabled. */
1343	#define VMX_EXIT_UMWAIT 67
1344	/** 68 - TPAUSE. Guest software attempted to execute TPAUSE and exiting was
1345	* enabled. */
1346	#define VMX_EXIT_TPAUSE 68
1347	/** The maximum exit value (inclusive). */
1348	#define VMX_EXIT_MAX (VMX_EXIT_TPAUSE)
1349	/** @} */
1350
1351
1352	/** @name VM Instruction Errors.
1353	* See Intel spec. "30.4 VM Instruction Error Numbers"
1354	* @{
1355	*/
1356	typedef enum
1357	{
1358	/** VMCALL executed in VMX root operation. */
1359	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1360	/** VMCLEAR with invalid physical address. */
1361	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1362	/** VMCLEAR with VMXON pointer. */
1363	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1364	/** VMLAUNCH with non-clear VMCS. */
1365	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1366	/** VMRESUME with non-launched VMCS. */
1367	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1368	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1369	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1370	/** VM-entry with invalid control field(s). */
1371	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1372	/** VM-entry with invalid host-state field(s). */
1373	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1374	/** VMPTRLD with invalid physical address. */
1375	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1376	/** VMPTRLD with VMXON pointer. */
1377	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1378	/** VMPTRLD with incorrect VMCS revision identifier. */
1379	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1380	/** VMREAD from unsupported VMCS component. */
1381	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1382	/** VMWRITE to unsupported VMCS component. */
1383	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1384	/** VMWRITE to read-only VMCS component. */
1385	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1386	/** VMXON executed in VMX root operation. */
1387	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1388	/** VM-entry with invalid executive-VMCS pointer. */
1389	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1390	/** VM-entry with non-launched executive VMCS. */
1391	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1392	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1393	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1394	/** VMCALL with non-clear VMCS. */
1395	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1396	/** VMCALL with invalid VM-exit control fields. */
1397	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1398	/** VMCALL with incorrect MSEG revision identifier. */
1399	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1400	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1401	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1402	/** VMCALL with invalid SMM-monitor features. */
1403	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1404	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1405	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1406	/** VM-entry with events blocked by MOV SS. */
1407	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1408	/** Invalid operand to INVEPT/INVVPID. */
1409	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1410	} VMXINSTRERR;
1411	/** @} */
1412
1413
1414	/** @name VMX abort reasons.
1415	* See Intel spec. "27.7 VMX Aborts".
1416	* Update HMGetVmxAbortDesc() if new reasons are added. @{
1417	*/
1418	typedef enum
1419	{
1420	/** None - don't use this / uninitialized value. */
1421	VMXABORT_NONE = 0,
1422	/** VMX abort caused during saving of guest MSRs. */
1423	VMXABORT_SAVE_GUEST_MSRS = 1,
1424	/** VMX abort caused during host PDPTE checks. */
1425	VMXBOART_HOST_PDPTE = 2,
1426	/** VMX abort caused due to current VMCS being corrupted. */
1427	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1428	/** VMX abort caused during loading of host MSRs. */
1429	VMXABORT_LOAD_HOST_MSR = 4,
1430	/** VMX abort caused due to a machine-check exception during VM-exit. */
1431	VMXABORT_MACHINE_CHECK_XCPT = 5,
1432	/** VMX abort caused due to invalid return from long mode. */
1433	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1434	/* Type size hack. */
1435	VMXABORT_32BIT_HACK = 0x7fffffff
1436	} VMXABORT;
1437	AssertCompileSize(VMXABORT, 4);
1438	/** @} */
1439
1440
1441	/** @name VMX MSR - Basic VMX information.
1442	* @{
1443	*/
1444	/** VMCS (and related regions) memory type - Uncacheable. */
1445	#define VMX_BASIC_MEM_TYPE_UC 0
1446	/** VMCS (and related regions) memory type - Write back. */
1447	#define VMX_BASIC_MEM_TYPE_WB 6
1448
1449	/** Bit fields for MSR_IA32_VMX_BASIC. */
1450	/** VMCS revision identifier used by the processor. */
1451	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1452	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1453	/** Bit 31 is reserved and RAZ. */
1454	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1455	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1456	/** VMCS size in bytes. */
1457	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1458	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1459	/** Bits 45:47 are reserved. */
1460	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1461	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1462	/** Width of physical addresses used for the VMCS and associated memory regions
1463	* (always 0 on CPUs that support Intel 64 architecture). */
1464	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1465	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1466	/** Dual-monitor treatment of SMI and SMM supported. */
1467	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1468	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1469	/** Memory type that must be used for the VMCS and associated memory regions. */
1470	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1471	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1472	/** VM-exit instruction information for INS/OUTS. */
1473	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1474	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1475	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1476	* bits in VMX control MSRs. */
1477	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1478	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1479	/** Bits 56:63 are reserved and RAZ. */
1480	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 56
1481	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xff00000000000000)
1482	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1483	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1484	VMCS_INS_OUTS, TRUE_CTLS, RSVD_56_63));
1485	/** @} */
1486
1487
1488	/** @name VMX MSR - Miscellaneous data.
1489	* @{
1490	*/
1491	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1492	#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1493	/** Whether Intel PT is supported in VMX operation. */
1494	#define VMX_MISC_INTEL_PT RT_BIT(14)
1495	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1496	* VMWRITE cannot modify read-only VM-exit information fields. */
1497	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1498	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1499	* instructions. */
1500	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1501	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1502	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1503	/** Maximum CR3-target count supported by the CPU. */
1504	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1505
1506	/** Bit fields for MSR_IA32_VMX_MISC. */
1507	/** Relationship between the preemption timer and tsc. */
1508	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1509	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1510	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1511	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1512	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1513	/** Activity states supported by the implementation. */
1514	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1515	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1516	/** Bits 9:13 is reserved and RAZ. */
1517	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1518	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1519	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1520	#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1521	#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1522	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1523	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1524	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1525	/** Number of CR3 target values supported by the processor. (0-256) */
1526	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1527	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1528	/** Maximum number of MSRs in the VMCS. */
1529	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1530	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1531	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1532	* SMIs. */
1533	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1534	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1535	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1536	* VMWRITE cannot modify read-only VM-exit information fields. */
1537	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1538	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1539	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1540	* instructions. */
1541	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1542	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1543	/** Bit 31 is reserved and RAZ. */
1544	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1545	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1546	/** 32-bit MSEG revision ID used by the processor. */
1547	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1548	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1549	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1550	(PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1551	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1552	/** @} */
1553
1554	/** @name VMX MSR - VMCS enumeration.
1555	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1556	* @{
1557	*/
1558	/** Bit 0 is reserved and RAZ. */
1559	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1560	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1561	/** Highest index value used in VMCS field encoding. */
1562	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1563	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1564	/** Bit 10:63 is reserved and RAZ. */
1565	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1566	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1567	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1568	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1569	/** @} */
1570
1571
1572	/** @name VMX MSR - VM Functions.
1573	* Bit fields for MSR_IA32_VMX_VMFUNC.
1574	* @{
1575	*/
1576	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1577	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1578	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1579	/** Bits 1:63 are reserved and RAZ. */
1580	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1581	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1582	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1583	(EPTP_SWITCHING, RSVD_1_63));
1584	/** @} */
1585
1586
1587	/** @name VMX MSR - EPT/VPID capabilities.
1588	* @{
1589	*/
1590	/** Supports execute-only translations by EPT. */
1591	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1592	/** Supports page-walk length of 4. */
1593	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1594	/** Supports EPT paging-structure memory type to be uncacheable. */
1595	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1596	/** Supports EPT paging structure memory type to be write-back. */
1597	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1598	/** Supports EPT PDE to map a 2 MB page. */
1599	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1600	/** Supports EPT PDPTE to map a 1 GB page. */
1601	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1602	/** Supports INVEPT instruction. */
1603	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1604	/** Supports accessed and dirty flags for EPT. */
1605	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1606	/** Supports single-context INVEPT type. */
1607	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1608	/** Supports all-context INVEPT type. */
1609	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1610	/** Supports INVVPID instruction. */
1611	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1612	/** Supports individual-address INVVPID type. */
1613	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1614	/** Supports single-context INVVPID type. */
1615	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1616	/** Supports all-context INVVPID type. */
1617	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1618	/** Supports singe-context-retaining-globals INVVPID type. */
1619	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1620
1621	/** Bit fields for MSR_IA32_VMX_EPT_VPID_CAP. */
1622	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_SHIFT 0
1623	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_MASK UINT64_C(0x0000000000000001)
1624	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_SHIFT 1
1625	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_MASK UINT64_C(0x000000000000003e)
1626	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_SHIFT 6
1627	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_MASK UINT64_C(0x0000000000000040)
1628	#define VMX_BF_EPT_VPID_CAP_RSVD_7_SHIFT 7
1629	#define VMX_BF_EPT_VPID_CAP_RSVD_7_MASK UINT64_C(0x0000000000000080)
1630	#define VMX_BF_EPT_VPID_CAP_EMT_UC_SHIFT 8
1631	#define VMX_BF_EPT_VPID_CAP_EMT_UC_MASK UINT64_C(0x0000000000000100)
1632	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_SHIFT 9
1633	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1634	#define VMX_BF_EPT_VPID_CAP_EMT_WB_SHIFT 14
1635	#define VMX_BF_EPT_VPID_CAP_EMT_WB_MASK UINT64_C(0x0000000000004000)
1636	#define VMX_BF_EPT_VPID_CAP_RSVD_15_SHIFT 15
1637	#define VMX_BF_EPT_VPID_CAP_RSVD_15_MASK UINT64_C(0x0000000000008000)
1638	#define VMX_BF_EPT_VPID_CAP_PDE_2M_SHIFT 16
1639	#define VMX_BF_EPT_VPID_CAP_PDE_2M_MASK UINT64_C(0x0000000000010000)
1640	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_SHIFT 17
1641	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_MASK UINT64_C(0x0000000000020000)
1642	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_SHIFT 18
1643	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_MASK UINT64_C(0x00000000000c0000)
1644	#define VMX_BF_EPT_VPID_CAP_INVEPT_SHIFT 20
1645	#define VMX_BF_EPT_VPID_CAP_INVEPT_MASK UINT64_C(0x0000000000100000)
1646	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_SHIFT 21
1647	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_MASK UINT64_C(0x0000000000200000)
1648	#define VMX_BF_EPT_VPID_CAP_RSVD_22_24_SHIFT 22
1649	#define VMX_BF_EPT_VPID_CAP_RSVD_22_24_MASK UINT64_C(0x0000000001c00000)
1650	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_SHIFT 25
1651	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_MASK UINT64_C(0x0000000002000000)
1652	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_SHIFT 26
1653	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_MASK UINT64_C(0x0000000004000000)
1654	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_SHIFT 27
1655	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_MASK UINT64_C(0x00000000f8000000)
1656	#define VMX_BF_EPT_VPID_CAP_INVVPID_SHIFT 32
1657	#define VMX_BF_EPT_VPID_CAP_INVVPID_MASK UINT64_C(0x0000000100000000)
1658	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_SHIFT 33
1659	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_MASK UINT64_C(0x000000fe00000000)
1660	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_SHIFT 40
1661	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_MASK UINT64_C(0x0000010000000000)
1662	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_SHIFT 41
1663	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_MASK UINT64_C(0x0000020000000000)
1664	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_SHIFT 42
1665	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_MASK UINT64_C(0x0000040000000000)
1666	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_SHIFT 43
1667	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_MASK UINT64_C(0x0000080000000000)
1668	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_SHIFT 44
1669	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_MASK UINT64_C(0xfffff00000000000)
1670	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_VPID_CAP_, UINT64_C(0), UINT64_MAX,
1671	(RWX_X_ONLY, RSVD_1_5, PAGE_WALK_LENGTH_4, RSVD_7, EMT_UC, RSVD_9_13, EMT_WB, RSVD_15, PDE_2M,
1672	PDPTE_1G, RSVD_18_19, INVEPT, EPT_ACCESS_DIRTY, RSVD_22_24, INVEPT_SINGLE_CTX,
1673	INVEPT_ALL_CTX, RSVD_27_31, INVVPID, RSVD_33_39, INVVPID_INDIV_ADDR, INVVPID_SINGLE_CTX,
1674	INVVPID_ALL_CTX, INVVPID_SINGLE_CTX_RETAIN_GLOBALS, RSVD_44_63));
1675	/** @} */
1676
1677
1678	/** @name Extended Page Table Pointer (EPTP)
1679	* @{
1680	*/
1681	/** Uncachable EPT paging structure memory type. */
1682	#define VMX_EPT_MEMTYPE_UC 0
1683	/** Write-back EPT paging structure memory type. */
1684	#define VMX_EPT_MEMTYPE_WB 6
1685	/** Shift value to get the EPT page walk length (bits 5-3) */
1686	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1687	/** Mask value to get the EPT page walk length (bits 5-3) */
1688	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1689	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1690	* length) */
1691	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1692	/** @} */
1693
1694
1695	/** @name VMCS field encoding: 16-bit guest fields.
1696	* @{
1697	*/
1698	#define VMX_VMCS16_VPID 0x0000
1699	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1700	#define VMX_VMCS16_EPTP_INDEX 0x0004
1701	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1702	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1703	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1704	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1705	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1706	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1707	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1708	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1709	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1710	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1711	/** @} */
1712
1713
1714	/** @name VMCS field encoding: 16-bits host fields.
1715	* @{
1716	*/
1717	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1718	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1719	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1720	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1721	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1722	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1723	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1724	/** @} */
1725
1726
1727	/** @name VMCS field encoding: 64-bit control fields.
1728	* @{
1729	*/
1730	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1731	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1732	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1733	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1734	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1735	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1736	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1737	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1738	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1739	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1740	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1741	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1742	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1743	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1744	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1745	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1746	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1747	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1748	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1749	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1750	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1751	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1752	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1753	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1754	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1755	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1756	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1757	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1758	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1759	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1760	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1761	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1762	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1763	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1764	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1765	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1766	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1767	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1768	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1769	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1770	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1771	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1772	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1773	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1774	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1775	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1776	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1777	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1778	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1779	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1780	/** @} */
1781
1782
1783	/** @name VMCS field encoding: 64-bit read-only data fields.
1784	* @{
1785	*/
1786	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1787	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1788	/** @} */
1789
1790
1791	/** @name VMCS field encoding: 64-bit guest fields.
1792	* @{
1793	*/
1794	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1795	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1796	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1797	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1798	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1799	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1800	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1801	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1802	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1803	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1804	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1805	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1806	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1807	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1808	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1809	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1810	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1811	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1812	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1813	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1814	/** @} */
1815
1816
1817	/** @name VMCS field encoding: 64-bit host fields.
1818	* @{
1819	*/
1820	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1821	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1822	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1823	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1824	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1825	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1826	/** @} */
1827
1828
1829	/** @name VMCS field encoding: 32-bit control fields.
1830	* @{
1831	*/
1832	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1833	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1834	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1835	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1836	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1837	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1838	#define VMX_VMCS32_CTRL_EXIT 0x400c
1839	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1840	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1841	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1842	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1843	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1844	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1845	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1846	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1847	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1848	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1849	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1850	/** @} */
1851
1852
1853	/** @name VMCS field encoding: 32-bits read-only fields.
1854	* @{
1855	*/
1856	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1857	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1858	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1859	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1860	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1861	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1862	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1863	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1864	/** @} */
1865
1866
1867	/** @name VMCS field encoding: 32-bit guest-state fields.
1868	* @{
1869	*/
1870	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1871	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1872	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1873	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1874	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1875	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1876	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1877	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1878	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1879	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1880	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1881	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1882	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1883	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1884	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1885	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1886	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1887	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1888	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1889	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1890	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1891	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
1892	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1893	/** @} */
1894
1895
1896	/** @name VMCS field encoding: 32-bit host-state fields.
1897	* @{
1898	*/
1899	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1900	/** @} */
1901
1902
1903	/** @name Natural width control fields.
1904	* @{
1905	*/
1906	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1907	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1908	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1909	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1910	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1911	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1912	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1913	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
1914	/** @} */
1915
1916
1917	/** @name Natural width read-only data fields.
1918	* @{
1919	*/
1920	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1921	#define VMX_VMCS_RO_IO_RCX 0x6402
1922	#define VMX_VMCS_RO_IO_RSI 0x6404
1923	#define VMX_VMCS_RO_IO_RDI 0x6406
1924	#define VMX_VMCS_RO_IO_RIP 0x6408
1925	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
1926	/** @} */
1927
1928
1929	/** @name VMCS field encoding: Natural width guest-state fields.
1930	* @{
1931	*/
1932	#define VMX_VMCS_GUEST_CR0 0x6800
1933	#define VMX_VMCS_GUEST_CR3 0x6802
1934	#define VMX_VMCS_GUEST_CR4 0x6804
1935	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1936	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1937	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1938	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1939	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1940	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1941	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1942	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1943	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1944	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1945	#define VMX_VMCS_GUEST_DR7 0x681a
1946	#define VMX_VMCS_GUEST_RSP 0x681c
1947	#define VMX_VMCS_GUEST_RIP 0x681e
1948	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1949	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
1950	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
1951	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
1952	/** @} */
1953
1954
1955	/** @name VMCS field encoding: Natural width host-state fields.
1956	* @{
1957	*/
1958	#define VMX_VMCS_HOST_CR0 0x6c00
1959	#define VMX_VMCS_HOST_CR3 0x6c02
1960	#define VMX_VMCS_HOST_CR4 0x6c04
1961	#define VMX_VMCS_HOST_FS_BASE 0x6c06
1962	#define VMX_VMCS_HOST_GS_BASE 0x6c08
1963	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
1964	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
1965	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
1966	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
1967	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
1968	#define VMX_VMCS_HOST_RSP 0x6c14
1969	#define VMX_VMCS_HOST_RIP 0x6c16
1970	/** @} */
1971
1972
1973	/** @name VMCS field encoding: Access.
1974	* @{ */
1975	typedef enum
1976	{
1977	VMXVMCSFIELDACCESS_FULL = 0,
1978	VMXVMCSFIELDACCESS_HIGH
1979	} VMXVMCSFIELDACCESS;
1980	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
1981	/** @} */
1982
1983
1984	/** @name VMCS field encoding: Type.
1985	* @{ */
1986	typedef enum
1987	{
1988	VMXVMCSFIELDTYPE_CONTROL = 0,
1989	VMXVMCSFIELDTYPE_VMEXIT_INFO,
1990	VMXVMCSFIELDTYPE_GUEST_STATE,
1991	VMXVMCSFIELDTYPE_HOST_STATE
1992	} VMXVMCSFIELDTYPE;
1993	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
1994	/** @} */
1995
1996
1997	/** @name VMCS field encoding: Width.
1998	* @{ */
1999	typedef enum
2000	{
2001	VMXVMCSFIELDWIDTH_16BIT = 0,
2002	VMXVMCSFIELDWIDTH_64BIT,
2003	VMXVMCSFIELDWIDTH_32BIT,
2004	VMXVMCSFIELDWIDTH_NATURAL
2005	} VMXVMCSFIELDWIDTH;
2006	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
2007	/** @} */
2008
2009	/** @name VM-entry instruction length.
2010	* @{ */
2011	/** The maximum valid value for VM-entry instruction length while injecting a
2012	* software interrupt, software exception or privileged software exception. */
2013	#define VMX_ENTRY_INSTR_LEN_MAX 15
2014	/** @} */
2015
2016
2017	/** @name VM-entry register masks.
2018	* @{ */
2019	/** CR0 bits ignored on VM-entry (ET, NW, CD and reserved bits bits 6:15, bit 17,
2020	* bits 19:28). */
2021	#define VMX_ENTRY_CR0_IGNORE_MASK UINT64_C(0x7ffaffd0)
2022	/** DR7 bits set here are always cleared on VM-entry (bit 12, bits 14:15). */
2023	#define VMX_ENTRY_DR7_MBZ_MASK UINT64_C(0xd000)
2024	/** DR7 bits set here are always set on VM-entry (bit 10). */
2025	#define VMX_ENTRY_DR7_MB1_MASK UINT64_C(0x400)
2026	/** @} */
2027
2028
2029	/** @name Pin-based VM-execution controls.
2030	* @{
2031	*/
2032	/** External interrupt exiting. */
2033	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
2034	/** NMI exiting. */
2035	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
2036	/** Virtual NMIs. */
2037	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
2038	/** Activate VMX preemption timer. */
2039	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
2040	/** Process interrupts with the posted-interrupt notification vector. */
2041	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
2042	/** Default1 class when true capability MSRs are not supported. */
2043	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
2044
2045	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
2046	* controls field in the VMCS. */
2047	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
2048	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
2049	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
2050	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
2051	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
2052	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
2053	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
2054	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
2055	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
2056	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
2057	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
2058	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
2059	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
2060	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
2061	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
2062	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
2063	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
2064	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
2065	/** @} */
2066
2067
2068	/** @name Processor-based VM-execution controls.
2069	* @{
2070	*/
2071	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
2072	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
2073	/** Use timestamp counter offset. */
2074	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
2075	/** VM-exit when executing the HLT instruction. */
2076	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
2077	/** VM-exit when executing the INVLPG instruction. */
2078	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
2079	/** VM-exit when executing the MWAIT instruction. */
2080	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
2081	/** VM-exit when executing the RDPMC instruction. */
2082	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
2083	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
2084	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
2085	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
2086	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2087	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
2088	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
2089	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2090	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
2091	/** VM-exit on CR8 loads. */
2092	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
2093	/** VM-exit on CR8 stores. */
2094	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
2095	/** Use TPR shadow. */
2096	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
2097	/** VM-exit when virtual NMI blocking is disabled. */
2098	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
2099	/** VM-exit when executing a MOV DRx instruction. */
2100	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
2101	/** VM-exit when executing IO instructions. */
2102	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
2103	/** Use IO bitmaps. */
2104	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
2105	/** Monitor trap flag. */
2106	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2107	/** Use MSR bitmaps. */
2108	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2109	/** VM-exit when executing the MONITOR instruction. */
2110	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2111	/** VM-exit when executing the PAUSE instruction. */
2112	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2113	/** Whether the secondary processor based VM-execution controls are used. */
2114	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2115	/** Default1 class when true-capability MSRs are not supported. */
2116	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2117
2118	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2119	* controls field in the VMCS. */
2120	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
2121	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2122	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2123	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2124	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2125	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2126	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
2127	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
2128	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2129	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2130	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
2131	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
2132	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2133	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2134	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2135	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2136	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2137	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2138	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2139	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2140	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
2141	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2142	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2143	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2144	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2145	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2146	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
2147	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
2148	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2149	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2150	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2151	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2152	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2153	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2154	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2155	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2156	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2157	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2158	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2159	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2160	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2161	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2162	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
2163	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
2164	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2165	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2166	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2167	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2168	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2169	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2170	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2171	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2172	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2173	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2174	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2175	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
2176	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
2177	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2178	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2179	USE_SECONDARY_CTLS));
2180	/** @} */
2181
2182
2183	/** @name Secondary Processor-based VM-execution controls.
2184	* @{
2185	*/
2186	/** Virtualize APIC accesses. */
2187	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2188	/** EPT supported/enabled. */
2189	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2190	/** Descriptor table instructions cause VM-exits. */
2191	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2192	/** RDTSCP supported/enabled. */
2193	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2194	/** Virtualize x2APIC mode. */
2195	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2196	/** VPID supported/enabled. */
2197	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2198	/** VM-exit when executing the WBINVD instruction. */
2199	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2200	/** Unrestricted guest execution. */
2201	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2202	/** APIC register virtualization. */
2203	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2204	/** Virtual-interrupt delivery. */
2205	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2206	/** A specified number of pause loops cause a VM-exit. */
2207	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2208	/** VM-exit when executing RDRAND instructions. */
2209	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2210	/** Enables INVPCID instructions. */
2211	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2212	/** Enables VMFUNC instructions. */
2213	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2214	/** Enables VMCS shadowing. */
2215	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2216	/** Enables ENCLS VM-exits. */
2217	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2218	/** VM-exit when executing RDSEED. */
2219	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2220	/** Enables page-modification logging. */
2221	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2222	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2223	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
2224	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2225	#define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19)
2226	/** Enables XSAVES/XRSTORS instructions. */
2227	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2228	/** Enables supervisor/user mode based EPT execute permission for linear
2229	* addresses. */
2230	#define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22)
2231	/** Enables EPT permissions to be specified at granularity of 128 bytes. */
2232	#define VMX_PROC_CTLS2_SPPTP_EPT RT_BIT(23)
2233	/** Intel PT output addresses are treated as guest-physical addresses and
2234	* translated using EPT. */
2235	#define VMX_PROC_CTLS2_PT_EPT RT_BIT(24)
2236	/** Use TSC scaling. */
2237	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2238	/** Enables TPAUSE, UMONITOR and UMWAIT instructions. */
2239	#define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26)
2240	/** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */
2241	#define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28)
2242
2243	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2244	* VM-execution controls field in the VMCS. */
2245	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2246	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2247	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2248	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2249	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2250	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2251	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2252	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2253	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2254	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2255	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2256	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2257	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2258	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2259	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2260	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2261	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2262	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2263	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2264	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2265	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2266	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2267	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2268	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2269	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2270	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2271	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2272	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2273	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2274	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2275	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2276	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2277	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2278	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2279	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2280	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2281	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2282	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2283	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19
2284	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000)
2285	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2286	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2287	#define VMX_BF_PROC_CTLS2_UNDEF_21_SHIFT 21
2288	#define VMX_BF_PROC_CTLS2_UNDEF_21_MASK UINT32_C(0x00200000)
2289	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22
2290	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000)
2291	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_SHIFT 23
2292	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_MASK UINT32_C(0x00800000)
2293	#define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24
2294	#define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000)
2295	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2296	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2297	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26
2298	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000)
2299	#define VMX_BF_PROC_CTLS2_UNDEF_27_SHIFT 27
2300	#define VMX_BF_PROC_CTLS2_UNDEF_27_MASK UINT32_C(0x08000000)
2301	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28
2302	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000)
2303	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_SHIFT 29
2304	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_MASK UINT32_C(0xe0000000)
2305
2306	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2307	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2308	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2309	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, UNDEF_21,
2310	MODE_BASED_EPT_PERM, SPPTP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, UNDEF_27, ENCLV_EXIT,
2311	UNDEF_29_31));
2312	/** @} */
2313
2314
2315	/** @name VM-entry controls.
2316	* @{
2317	*/
2318	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2319	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2320	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2321	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2322	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2323	/** In SMM mode after VM-entry. */
2324	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2325	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2326	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2327	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2328	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2329	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2330	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2331	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2332	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2333	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2334	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2335	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2336	#define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17)
2337	/** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
2338	#define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18)
2339	/** Default1 class when true-capability MSRs are not supported. */
2340	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2341
2342	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2343	* VMCS. */
2344	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2345	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2346	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2347	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2348	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2349	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2350	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2351	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2352	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2353	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2354	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2355	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2356	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2357	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2358	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2359	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2360	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2361	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2362	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2363	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2364	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2365	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2366	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17
2367	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000)
2368	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18
2369	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000)
2370	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_SHIFT 19
2371	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_MASK UINT32_C(0xfff80000)
2372	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2373	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2374	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
2375	LOAD_RTIT_CTL_MSR, UNDEF_19_31));
2376	/** @} */
2377
2378
2379	/** @name VM-exit controls.
2380	* @{
2381	*/
2382	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2383	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2384	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2385	/** Return to long mode after a VM-exit. */
2386	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2387	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2388	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2389	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2390	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2391	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2392	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2393	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2394	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2395	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2396	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2397	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2398	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2399	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2400	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2401	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2402	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2403	/** Whether to conceal VMX from Intel PT. */
2404	#define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24)
2405	/** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
2406	#define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25)
2407	/** Default1 class when true-capability MSRs are not supported. */
2408	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2409
2410	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2411	* VMCS. */
2412	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2413	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2414	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2415	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2416	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2417	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2418	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2419	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2420	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2421	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2422	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2423	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2424	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2425	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2426	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2427	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2428	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2429	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2430	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2431	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2432	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2433	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2434	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2435	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2436	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2437	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2438	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2439	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2440	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23
2441	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000)
2442	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24
2443	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000)
2444	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25
2445	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000)
2446	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_SHIFT 26
2447	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2448	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2449	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2450	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2451	SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, UNDEF_26_31));
2452	/** @} */
2453
2454
2455	/** @name VM-exit reason.
2456	* @{
2457	*/
2458	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2459	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2460	#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2461
2462	/** Bit fields for VM-exit reason. */
2463	/** The exit reason. */
2464	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2465	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2466	/** Bits 16:26 are reseved and MBZ. */
2467	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2468	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2469	/** Whether the VM-exit was incident to enclave mode. */
2470	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2471	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2472	/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2473	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2474	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2475	/** VM-exit from VMX root operation (only possible with SMM). */
2476	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2477	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2478	/** Bit 30 is reserved and MBZ. */
2479	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2480	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2481	/** Whether VM-entry failed (currently only happens during loading guest-state
2482	* or MSRs or machine check exceptions). */
2483	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2484	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2485	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2486	(BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2487	/** @} */
2488
2489
2490	/** @name VM-entry interruption information.
2491	* @{
2492	*/
2493	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2494	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2495	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2496	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2497	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2498	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2499	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2500	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2501	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2502	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2503	/** Construct an VM-entry interruption information field from a VM-exit interruption
2504	* info value (same except that bit 12 is reserved). */
2505	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2506	/** Construct a VM-entry interruption information field from an IDT-vectoring
2507	* information field (same except that bit 12 is reserved). */
2508	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2509
2510	/** Bit fields for VM-entry interruption information. */
2511	/** The VM-entry interruption vector. */
2512	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2513	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2514	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2515	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2516	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2517	/** Whether this event has an error code. */
2518	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2519	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2520	/** Bits 12:30 are reserved and MBZ. */
2521	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2522	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2523	/** Whether this VM-entry interruption info is valid. */
2524	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2525	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2526	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2527	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2528	/** @} */
2529
2530	/** @name VM-entry exception error code.
2531	* @{ */
2532	/** Error code valid mask. */
2533	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2534	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2535	* stack aligned for doubleword pushes, the upper half of the error code is
2536	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2537	* use below. */
2538	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2539	/** @} */
2540
2541	/** @name VM-entry interruption information types.
2542	* @{
2543	*/
2544	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2545	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2546	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2547	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2548	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2549	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2550	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2551	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2552	/** @} */
2553
2554
2555	/** @name VM-entry interruption information vector types for
2556	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2557	* @{ */
2558	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2559	/** @} */
2560
2561
2562	/** @name VM-exit interruption information.
2563	* @{
2564	*/
2565	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2566	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2567	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2568	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2569	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2570	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2571	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2572	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2573	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2574
2575	/** Bit fields for VM-exit interruption infomration. */
2576	/** The VM-exit interruption vector. */
2577	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2578	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2579	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2580	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2581	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2582	/** Whether this event has an error code. */
2583	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2584	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2585	/** Whether NMI-unblocking due to IRET is active. */
2586	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2587	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2588	/** Bits 13:30 is reserved (MBZ). */
2589	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2590	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2591	/** Whether this VM-exit interruption info is valid. */
2592	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2593	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2594	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2595	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2596	/** @} */
2597
2598
2599	/** @name VM-exit interruption information types.
2600	* @{
2601	*/
2602	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2603	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2604	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2605	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2606	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2607	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2608	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2609	/** @} */
2610
2611
2612	/** @name VM-exit instruction identity.
2613	*
2614	* These are found in VM-exit instruction information fields for certain
2615	* instructions.
2616	* @{ */
2617	typedef uint32_t VMXINSTRID;
2618	/** Whether the instruction ID field is valid. */
2619	#define VMXINSTRID_VALID RT_BIT_32(31)
2620	/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
2621	* read or write. */
2622	#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
2623	/** Gets whether the instruction ID is valid or not. */
2624	#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
2625	#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
2626	/** Gets the instruction ID. */
2627	#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W))
2628	/** No instruction ID info. */
2629	#define VMXINSTRID_NONE 0
2630
2631	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2632	#define VMXINSTRID_SGDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2633	#define VMXINSTRID_SIDT (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2634	#define VMXINSTRID_LGDT (0x2 \| VMXINSTRID_VALID)
2635	#define VMXINSTRID_LIDT (0x3 \| VMXINSTRID_VALID)
2636
2637	#define VMXINSTRID_SLDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2638	#define VMXINSTRID_STR (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2639	#define VMXINSTRID_LLDT (0x2 \| VMXINSTRID_VALID)
2640	#define VMXINSTRID_LTR (0x3 \| VMXINSTRID_VALID)
2641
2642	/** The following IDs are used internally (some for logging, others for conveying
2643	* the ModR/M primary operand write bit): */
2644	#define VMXINSTRID_VMLAUNCH (0x10 \| VMXINSTRID_VALID)
2645	#define VMXINSTRID_VMRESUME (0x11 \| VMXINSTRID_VALID)
2646	#define VMXINSTRID_VMREAD (0x12 \| VMXINSTRID_VALID)
2647	#define VMXINSTRID_VMWRITE (0x13 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2648	#define VMXINSTRID_IO_IN (0x14 \| VMXINSTRID_VALID)
2649	#define VMXINSTRID_IO_INS (0x15 \| VMXINSTRID_VALID)
2650	#define VMXINSTRID_IO_OUT (0x16 \| VMXINSTRID_VALID)
2651	#define VMXINSTRID_IO_OUTS (0x17 \| VMXINSTRID_VALID)
2652	#define VMXINSTRID_MOV_TO_DRX (0x18 \| VMXINSTRID_VALID)
2653	#define VMXINSTRID_MOV_FROM_DRX (0x19 \| VMXINSTRID_VALID)
2654	/** @} */
2655
2656
2657	/** @name IDT-vectoring information.
2658	* @{
2659	*/
2660	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2661	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2662	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2663	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2664
2665	/** Construct an IDT-vectoring information field from an VM-entry interruption
2666	* information field (same except that bit 12 is reserved). */
2667	#define VMX_EXIT_IDT_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
2668
2669	/** Bit fields for IDT-vectoring information. */
2670	/** The IDT-vectoring info vector. */
2671	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2672	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2673	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
2674	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2675	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2676	/** Whether the event has an error code. */
2677	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2678	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2679	/** Bit 12 is undefined. */
2680	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2681	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2682	/** Bits 13:30 is reserved (MBZ). */
2683	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2684	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2685	/** Whether this IDT-vectoring info is valid. */
2686	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2687	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2688	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2689	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2690	/** @} */
2691
2692
2693	/** @name IDT-vectoring information vector types.
2694	* @{
2695	*/
2696	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2697	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2698	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2699	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2700	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2701	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2702	#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
2703	/** @} */
2704
2705
2706	/** @name TPR threshold.
2707	* @{ */
2708	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
2709	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
2710
2711	/** Bit fields for TPR threshold. */
2712	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
2713	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
2714	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
2715	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
2716	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
2717	(TPR, RSVD_4_31));
2718	/** @} */
2719
2720
2721	/** @name Guest-activity states.
2722	* @{
2723	*/
2724	/** The logical processor is active. */
2725	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2726	/** The logical processor is inactive, because it executed a HLT instruction. */
2727	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2728	/** The logical processor is inactive, because of a triple fault or other serious error. */
2729	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2730	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2731	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2732	/** @} */
2733
2734
2735	/** @name Guest-interruptibility states.
2736	* @{
2737	*/
2738	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2739	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2740	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2741	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2742	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
2743
2744	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
2745	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
2746	/** @} */
2747
2748
2749	/** @name Exit qualification for debug exceptions.
2750	* @{
2751	*/
2752	/** Hardware breakpoint 0 was met. */
2753	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
2754	/** Hardware breakpoint 1 was met. */
2755	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
2756	/** Hardware breakpoint 2 was met. */
2757	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
2758	/** Hardware breakpoint 3 was met. */
2759	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
2760	/** Debug register access detected. */
2761	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
2762	/** A debug exception would have been triggered by single-step execution mode. */
2763	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
2764	/** Mask of all valid bits. */
2765	#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
2766	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
2767	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
2768	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
2769	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
2770	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
2771
2772	/** Bit fields for Exit qualifications due to debug exceptions. */
2773	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
2774	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
2775	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
2776	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
2777	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
2778	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
2779	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
2780	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
2781	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
2782	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
2783	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
2784	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
2785	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
2786	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
2787	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
2788	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
2789	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
2790	(BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
2791	/** @} */
2792
2793	/** @name Exit qualification for Mov DRx.
2794	* @{
2795	*/
2796	/** 0-2: Debug register number */
2797	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
2798	/** 3: Reserved; cleared to 0. */
2799	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
2800	/** 4: Direction of move (0 = write, 1 = read) */
2801	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
2802	/** 5-7: Reserved; cleared to 0. */
2803	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
2804	/** 8-11: General purpose register number. */
2805	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
2806
2807	/** Bit fields for Exit qualification due to Mov DRx. */
2808	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
2809	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
2810	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
2811	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
2812	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
2813	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
2814	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
2815	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
2816	#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
2817	#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
2818	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
2819	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
2820	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
2821	(REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
2822	/** @} */
2823
2824
2825	/** @name Exit qualification for debug exceptions types.
2826	* @{
2827	*/
2828	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
2829	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
2830	/** @} */
2831
2832
2833	/** @name Exit qualification for control-register accesses.
2834	* @{
2835	*/
2836	/** 0-3: Control register number (0 for CLTS & LMSW) */
2837	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
2838	/** 4-5: Access type. */
2839	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
2840	/** 6: LMSW operand type */
2841	#define VMX_EXIT_QUAL_CRX_LMSW_OP(a) (((a) >> 6) & 1)
2842	/** 7: Reserved; cleared to 0. */
2843	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
2844	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
2845	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
2846	/** 12-15: Reserved; cleared to 0. */
2847	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
2848	/** 16-31: LMSW source data (else 0). */
2849	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
2850
2851	/** Bit fields for Exit qualification for control-register accesses. */
2852	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
2853	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
2854	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
2855	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
2856	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
2857	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
2858	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
2859	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
2860	#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
2861	#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
2862	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
2863	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
2864	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
2865	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
2866	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
2867	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
2868	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
2869	(REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
2870	/** @} */
2871
2872
2873	/** @name Exit qualification for control-register access types.
2874	* @{
2875	*/
2876	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
2877	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
2878	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
2879	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
2880	/** @} */
2881
2882
2883	/** @name Exit qualification for task switch.
2884	* @{
2885	*/
2886	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
2887	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
2888	/** Task switch caused by a call instruction. */
2889	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
2890	/** Task switch caused by an iret instruction. */
2891	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
2892	/** Task switch caused by a jmp instruction. */
2893	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
2894	/** Task switch caused by an interrupt gate. */
2895	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
2896
2897	/** Bit fields for Exit qualification for task switches. */
2898	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
2899	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
2900	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
2901	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
2902	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
2903	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
2904	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
2905	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
2906	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
2907	(NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
2908	/** @} */
2909
2910
2911	/** @name Exit qualification for EPT violations.
2912	* @{
2913	*/
2914	/** Set if the violation was caused by a data read. */
2915	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
2916	/** Set if the violation was caused by a data write. */
2917	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
2918	/** Set if the violation was caused by an instruction fetch. */
2919	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
2920	/** AND of the present bit of all EPT structures. */
2921	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
2922	/** AND of the write bit of all EPT structures. */
2923	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
2924	/** AND of the execute bit of all EPT structures. */
2925	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
2926	/** Set if the guest linear address field contains the faulting address. */
2927	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
2928	/** If bit 7 is one: (reserved otherwise)
2929	* 1 - violation due to physical address access.
2930	* 0 - violation caused by page walk or access/dirty bit updates
2931	*/
2932	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
2933	/** @} */
2934
2935
2936	/** @name Exit qualification for I/O instructions.
2937	* @{
2938	*/
2939	/** 0-2: IO operation size 0(=1 byte), 1(=2 bytes) and 3(=4 bytes). */
2940	#define VMX_EXIT_QUAL_IO_SIZE(a) ((a) & 7)
2941	/** 3: IO operation direction. */
2942	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
2943	/** 4: String IO operation (INS / OUTS). */
2944	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
2945	/** 5: Repeated IO operation. */
2946	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
2947	/** 6: Operand encoding. */
2948	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
2949	/** 16-31: IO Port (0-0xffff). */
2950	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
2951
2952	/** Bit fields for Exit qualification for I/O instructions. */
2953	#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
2954	#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
2955	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
2956	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
2957	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
2958	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
2959	#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
2960	#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
2961	#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
2962	#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
2963	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
2964	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
2965	#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
2966	#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
2967	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
2968	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
2969	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
2970	(WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
2971	/** @} */
2972
2973
2974	/** @name Exit qualification for I/O instruction types.
2975	* @{
2976	*/
2977	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
2978	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
2979	/** @} */
2980
2981
2982	/** @name Exit qualification for I/O instruction encoding.
2983	* @{
2984	*/
2985	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
2986	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
2987	/** @} */
2988
2989
2990	/** @name Exit qualification for APIC-access VM-exits from linear and
2991	* guest-physical accesses.
2992	* @{
2993	*/
2994	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
2995	* access within the APIC page. */
2996	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
2997	/** 12-15: Access type. */
2998	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
2999	/* Rest reserved. */
3000
3001	/** Bit fields for Exit qualification for APIC-access VM-exits. */
3002	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
3003	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
3004	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
3005	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
3006	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
3007	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
3008	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
3009	(OFFSET, TYPE, RSVD_16_63));
3010	/** @} */
3011
3012
3013	/** @name Exit qualification for linear address APIC-access types.
3014	* @{
3015	*/
3016	/** Linear access for a data read during instruction execution. */
3017	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
3018	/** Linear access for a data write during instruction execution. */
3019	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
3020	/** Linear access for an instruction fetch. */
3021	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
3022	/** Linear read/write access during event delivery. */
3023	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
3024	/** Physical read/write access during event delivery. */
3025	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
3026	/** Physical access for an instruction fetch or during instruction execution. */
3027	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
3028
3029	/**
3030	* APIC-access type.
3031	*/
3032	typedef enum
3033	{
3034	VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
3035	VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
3036	VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
3037	VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
3038	VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
3039	VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
3040	} VMXAPICACCESS;
3041	AssertCompileSize(VMXAPICACCESS, 4);
3042	/** @} */
3043
3044
3045	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
3046	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3047	* @{
3048	*/
3049	/** Address calculation scaling field (powers of two). */
3050	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
3051	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3052	/** Bits 2 thru 6 are undefined. */
3053	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
3054	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
3055	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3056	* @remarks anyone's guess why this is a 3 bit field... */
3057	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
3058	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3059	/** Bit 10 is defined as zero. */
3060	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
3061	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
3062	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
3063	* for exits from 64-bit code as the operand size there is fixed. */
3064	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
3065	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
3066	/** Bits 12 thru 14 are undefined. */
3067	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
3068	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
3069	/** Applicable segment register (X86_SREG_XXX values). */
3070	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
3071	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3072	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3073	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
3074	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3075	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3076	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3077	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3078	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3079	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
3080	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3081	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3082	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
3083	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3084	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
3085	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
3086	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3087	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
3088	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
3089	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
3090	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
3091	/** Bits 30 & 31 are undefined. */
3092	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
3093	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3094	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3095	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
3096	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3097	/** @} */
3098
3099
3100	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
3101	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3102	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
3103	* @{
3104	*/
3105	/** Address calculation scaling field (powers of two). */
3106	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
3107	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3108	/** Bit 2 is undefined. */
3109	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
3110	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
3111	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
3112	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
3113	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
3114	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3115	* @remarks anyone's guess why this is a 3 bit field... */
3116	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
3117	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3118	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
3119	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
3120	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
3121	/** Bits 11 thru 14 are undefined. */
3122	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
3123	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
3124	/** Applicable segment register (X86_SREG_XXX values). */
3125	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
3126	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3127	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3128	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
3129	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3130	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3131	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3132	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3133	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3134	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
3135	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3136	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3137	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
3138	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3139	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
3140	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
3141	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3142	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
3143	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
3144	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
3145	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
3146	/** Bits 30 & 31 are undefined. */
3147	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3148	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3149	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3150	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3151	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3152	/** @} */
3153
3154
3155	/** @name Format of Pending-Debug-Exceptions.
3156	* Bits 4-11, 13, 15 and 17-63 are reserved.
3157	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3158	* possibly valid here but not in DR6.
3159	* @{
3160	*/
3161	/** Hardware breakpoint 0 was met. */
3162	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3163	/** Hardware breakpoint 1 was met. */
3164	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3165	/** Hardware breakpoint 2 was met. */
3166	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3167	/** Hardware breakpoint 3 was met. */
3168	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3169	/** At least one data or IO breakpoint was hit. */
3170	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3171	/** A debug exception would have been triggered by single-step execution mode. */
3172	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3173	/** A debug exception occurred inside an RTM region. */
3174	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3175	/** Mask of valid bits. */
3176	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3177	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3178	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3179	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3180	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3181	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3182	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3183	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3184	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3185	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3186	/** Bit fields for Pending debug exceptions. */
3187	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3188	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3189	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3190	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3191	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3192	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3193	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3194	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3195	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3196	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3197	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3198	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3199	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3200	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3201	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3202	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3203	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3204	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3205	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3206	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3207	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3208	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3209	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3210	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3211	/** @} */
3212
3213
3214	/** @name VMCS field encoding.
3215	* @{ */
3216	typedef union
3217	{
3218	struct
3219	{
3220	/** The access type; 0=full, 1=high of 64-bit fields. */
3221	uint32_t fAccessType : 1;
3222	/** The index. */
3223	uint32_t u8Index : 8;
3224	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
3225	uint32_t u2Type : 2;
3226	/** Reserved (MBZ). */
3227	uint32_t u1Reserved0 : 1;
3228	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
3229	uint32_t u2Width : 2;
3230	/** Reserved (MBZ). */
3231	uint32_t u18Reserved0 : 18;
3232	} n;
3233	/* The unsigned integer view. */
3234	uint32_t u;
3235	} VMXVMCSFIELDENC;
3236	AssertCompileSize(VMXVMCSFIELDENC, 4);
3237	/** Pointer to a VMCS field encoding. */
3238	typedef VMXVMCSFIELDENC *PVMXVMCSFIELDENC;
3239	/** Pointer to a const VMCS field encoding. */
3240	typedef const VMXVMCSFIELDENC *PCVMXVMCSFIELDENC;
3241
3242	/** VMCS field encoding type: Full. */
3243	#define VMX_VMCS_ENC_ACCESS_TYPE_FULL 0
3244	/** VMCS field encoding type: High. */
3245	#define VMX_VMCS_ENC_ACCESS_TYPE_HIGH 1
3246
3247	/** VMCS field encoding type: Control. */
3248	#define VMX_VMCS_ENC_TYPE_CONTROL 0
3249	/** VMCS field encoding type: VM-exit information / read-only fields. */
3250	#define VMX_VMCS_ENC_TYPE_VMEXIT_INFO 1
3251	/** VMCS field encoding type: Guest-state. */
3252	#define VMX_VMCS_ENC_TYPE_GUEST_STATE 2
3253	/** VMCS field encoding type: Host-state. */
3254	#define VMX_VMCS_ENC_TYPE_HOST_STATE 3
3255
3256	/** VMCS field encoding width: 16-bit. */
3257	#define VMX_VMCS_ENC_WIDTH_16BIT 0
3258	/** VMCS field encoding width: 64-bit. */
3259	#define VMX_VMCS_ENC_WIDTH_64BIT 1
3260	/** VMCS field encoding width: 32-bit. */
3261	#define VMX_VMCS_ENC_WIDTH_32BIT 2
3262	/** VMCS field encoding width: Natural width. */
3263	#define VMX_VMCS_ENC_WIDTH_NATURAL 3
3264
3265	/** VMCS field encoding: Mask of reserved bits (bits 63:15 MBZ), bit 12 is
3266	* not included! */
3267	#define VMX_VMCS_ENC_RSVD_MASK UINT64_C(0xffffffffffff8000)
3268
3269	/** Bits fields for VMCS field encoding. */
3270	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_SHIFT 0
3271	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_MASK UINT32_C(0x00000001)
3272	#define VMX_BF_VMCS_ENC_INDEX_SHIFT 1
3273	#define VMX_BF_VMCS_ENC_INDEX_MASK UINT32_C(0x000003fe)
3274	#define VMX_BF_VMCS_ENC_TYPE_SHIFT 10
3275	#define VMX_BF_VMCS_ENC_TYPE_MASK UINT32_C(0x00000c00)
3276	#define VMX_BF_VMCS_ENC_RSVD_12_SHIFT 12
3277	#define VMX_BF_VMCS_ENC_RSVD_12_MASK UINT32_C(0x00001000)
3278	#define VMX_BF_VMCS_ENC_WIDTH_SHIFT 13
3279	#define VMX_BF_VMCS_ENC_WIDTH_MASK UINT32_C(0x00006000)
3280	#define VMX_BF_VMCS_ENC_RSVD_15_31_SHIFT 15
3281	#define VMX_BF_VMCS_ENC_RSVD_15_31_MASK UINT32_C(0xffff8000)
3282	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENC_, UINT32_C(0), UINT32_MAX,
3283	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
3284	/** @} */
3285
3286
3287	/** @defgroup grp_hm_vmx_virt VMX virtualization.
3288	* @{
3289	*/
3290
3291	/** @name Virtual VMX MSR - Miscellaneous data.
3292	* @{ */
3293	/** Number of CR3-target values supported. */
3294	#define VMX_V_CR3_TARGET_COUNT 4
3295	/** Activity states supported. */
3296	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3297	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3298	#define VMX_V_PREEMPT_TIMER_SHIFT 5
3299	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3300	#define VMX_V_AUTOMSR_COUNT_MAX 0
3301	/** SMM MSEG revision ID. */
3302	#define VMX_V_MSEG_REV_ID 0
3303	/** @} */
3304
3305	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS launch state.
3306	* @{ */
3307	/** VMCS launch state clear. */
3308	#define VMX_V_VMCS_LAUNCH_STATE_CLEAR RT_BIT(0)
3309	/** VMCS launch state active. */
3310	#define VMX_V_VMCS_LAUNCH_STATE_ACTIVE RT_BIT(1)
3311	/** VMCS launch state current. */
3312	#define VMX_V_VMCS_LAUNCH_STATE_CURRENT RT_BIT(2)
3313	/** VMCS launch state launched. */
3314	#define VMX_V_VMCS_LAUNCH_STATE_LAUNCHED RT_BIT(3)
3315	/** The mask of valid VMCS launch states. */
3316	#define VMX_V_VMCS_LAUNCH_STATE_MASK ( VMX_V_VMCS_LAUNCH_STATE_CLEAR \
3317	\| VMX_V_VMCS_LAUNCH_STATE_ACTIVE \
3318	\| VMX_V_VMCS_LAUNCH_STATE_CURRENT \
3319	\| VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
3320	/** @} */
3321
3322	/** CR0 bits set here must always be set when in VMX operation. */
3323	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
3324	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
3325	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
3326	/** CR4 bits set here must always be set when in VMX operation. */
3327	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3328
3329	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3330	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3331	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001)
3332	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3333
3334	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3335	* complications when teleporation may be implemented). */
3336	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3337	/** The size of the virtual VMCS region (in pages). */
3338	#define VMX_V_VMCS_PAGES 1
3339
3340	/** The size of the Virtual-APIC page (in bytes). */
3341	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3342	/** The size of the Virtual-APIC page (in pages). */
3343	#define VMX_V_VIRT_APIC_PAGES 1
3344
3345	/** Virtual X2APIC MSR range start. */
3346	#define VMX_V_VIRT_APIC_MSR_START 0x800
3347	/** Virtual X2APIC MSR range end. */
3348	#define VMX_V_VIRT_APIC_MSR_END 0x8ff
3349
3350	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3351	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3352	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3353	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3354
3355	/** The size of the MSR bitmap (in bytes). */
3356	#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3357	/** The size of the MSR bitmap (in pages). */
3358	#define VMX_V_MSR_BITMAP_PAGES 1
3359
3360	/** The size of I/O bitmap A (in bytes). */
3361	#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3362	/** The size of I/O bitmap A (in pages). */
3363	#define VMX_V_IO_BITMAP_A_PAGES 1
3364
3365	/** The size of I/O bitmap B (in bytes). */
3366	#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3367	/** The size of I/O bitmap B (in pages). */
3368	#define VMX_V_IO_BITMAP_B_PAGES 1
3369
3370	/** The size of the auto-load/store MSR area (in bytes). */
3371	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3372	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3373	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3374	/** The size of the auto-load/store MSR area (in pages). */
3375	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3376
3377	/** The highest index value used for supported virtual VMCS field encoding. */
3378	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCS_ENC_INDEX)
3379
3380	/**
3381	* Virtual VM-exit information.
3382	*
3383	* This is a convenience structure that bundles some VM-exit information related
3384	* fields together.
3385	*/
3386	typedef struct
3387	{
3388	/** The VM-exit reason. */
3389	uint32_t uReason;
3390	/** The VM-exit instruction length. */
3391	uint32_t cbInstr;
3392	/** The VM-exit instruction information. */
3393	VMXEXITINSTRINFO InstrInfo;
3394	/** The VM-exit instruction ID. */
3395	VMXINSTRID uInstrId;
3396
3397	/** The VM-exit qualification field. */
3398	uint64_t u64Qual;
3399	/** The guest-linear address field. */
3400	uint64_t u64GuestLinearAddr;
3401	/** The guest-physical address field. */
3402	uint64_t u64GuestPhysAddr;
3403	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3404	* instruction VM-exit. */
3405	RTGCPTR GCPtrEffAddr;
3406	} VMXVEXITINFO;
3407	/** Pointer to the VMXVEXITINFO struct. */
3408	typedef VMXVEXITINFO *PVMXVEXITINFO;
3409	/** Pointer to a const VMXVEXITINFO struct. */
3410	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3411	AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3412
3413	/**
3414	* Virtual VM-exit information for events.
3415	*
3416	* This is a convenience structure that bundles some event-based VM-exit information
3417	* related fields together that are not included in VMXVEXITINFO.
3418	*
3419	* This is kept as a separate structure and not included in VMXVEXITINFO, to make it
3420	* easier to distinguish that IEM VM-exit handlers will set one or more of the
3421	* following fields in the virtual VMCS. Including it in the VMXVEXITINFO will not
3422	* make it ovbious which fields may get set (or cleared).
3423	*/
3424	typedef struct
3425	{
3426	/** VM-exit interruption information. */
3427	uint32_t uExitIntInfo;
3428	/** VM-exit interruption error code. */
3429	uint32_t uExitIntErrCode;
3430	/** IDT-vectoring information. */
3431	uint32_t uIdtVectoringInfo;
3432	/** IDT-vectoring error code. */
3433	uint32_t uIdtVectoringErrCode;
3434	} VMXVEXITEVENTINFO;
3435	/** Pointer to the VMXVEXITINFO2 struct. */
3436	typedef VMXVEXITEVENTINFO *PVMXVEXITEVENTINFO;
3437	/** Pointer to a const VMXVEXITINFO2 struct. */
3438	typedef const VMXVEXITEVENTINFO *PCVMXVEXITEVENTINFO;
3439
3440	/**
3441	* Virtual VMCS.
3442	* This is our custom format and merged into the actual VMCS (/shadow) when we
3443	* execute nested-guest code using hardware-assisted VMX.
3444	*
3445	* The first 8 bytes are as per Intel spec. 24.2 "Format of the VMCS Region".
3446	*
3447	* The offset and size of the VMCS state field (fVmcsState) is also fixed (not by
3448	* Intel but for our own requirements) as we use it to offset into guest memory.
3449	*
3450	* Although the guest is supposed to access the VMCS only through the execution of
3451	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3452	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
3453	* for teleportation purposes, any newly added fields should be added to the
3454	* appropriate reserved sections or at the end of the structure.
3455	*
3456	* We always treat natural-width fields as 64-bit in our implementation since
3457	* it's easier, allows for teleporation in the future and does not affect guest
3458	* software.
3459	*/
3460	#pragma pack(1)
3461	typedef struct
3462	{
3463	/** 0x0 - VMX VMCS revision identifier. */
3464	VMXVMCSREVID u32VmcsRevId;
3465	/** 0x4 - VMX-abort indicator. */
3466	VMXABORT enmVmxAbort;
3467	/** 0x8 - VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
3468	uint8_t fVmcsState;
3469	/** 0x9 - Reserved for future. */
3470	uint8_t au8Padding0[3];
3471	/** 0xc - Reserved for future. */
3472	uint32_t au32Reserved0[7];
3473
3474	/** @name 16-bit control fields.
3475	* @{ */
3476	/** 0x28 - Virtual processor ID. */
3477	uint16_t u16Vpid;
3478	/** 0x2a - Posted interrupt notify vector. */
3479	uint16_t u16PostIntNotifyVector;
3480	/** 0x2c - EPTP index. */
3481	uint16_t u16EptpIndex;
3482	/** 0x2e - Reserved for future. */
3483	uint16_t au16Reserved0[8];
3484	/** @} */
3485
3486	/** @name 16-bit Guest-state fields.
3487	* Order of [ES..GS] is important, must match X86_SREG_XXX.
3488	* @{ */
3489	/** 0x3e - Guest ES selector. */
3490	RTSEL GuestEs;
3491	/** 0x40 - Guest ES selector. */
3492	RTSEL GuestCs;
3493	/** 0x42 - Guest ES selector. */
3494	RTSEL GuestSs;
3495	/** 0x44 - Guest ES selector. */
3496	RTSEL GuestDs;
3497	/** 0x46 - Guest ES selector. */
3498	RTSEL GuestFs;
3499	/** 0x48 - Guest ES selector. */
3500	RTSEL GuestGs;
3501	/** 0x4a - Guest LDTR selector. */
3502	RTSEL GuestLdtr;
3503	/** 0x4c - Guest TR selector. */
3504	RTSEL GuestTr;
3505	/** 0x4e - Guest interrupt status (virtual-interrupt delivery). */
3506	uint16_t u16GuestIntStatus;
3507	/** 0x50 - PML index. */
3508	uint16_t u16PmlIndex;
3509	/** 0x52 - Reserved for future. */
3510	uint16_t au16Reserved1[8];
3511	/** @} */
3512
3513	/** @name 16-bit Host-state fields.
3514	* @{ */
3515	/** 0x62 - Host ES selector. */
3516	RTSEL HostEs;
3517	/** 0x64 - Host CS selector. */
3518	RTSEL HostCs;
3519	/** 0x66 - Host SS selector. */
3520	RTSEL HostSs;
3521	/** 0x68 - Host DS selector. */
3522	RTSEL HostDs;
3523	/** 0x6a - Host FS selector. */
3524	RTSEL HostFs;
3525	/** 0x6c - Host GS selector. */
3526	RTSEL HostGs;
3527	/** 0x6e - Host TR selector. */
3528	RTSEL HostTr;
3529	/** 0x70 - Reserved for future. */
3530	uint16_t au16Reserved2[10];
3531	/** @} */
3532
3533	/** @name 32-bit Control fields.
3534	* @{ */
3535	/** 0x84 - Pin-based VM-execution controls. */
3536	uint32_t u32PinCtls;
3537	/** 0x88 - Processor-based VM-execution controls. */
3538	uint32_t u32ProcCtls;
3539	/** 0x8c - Exception bitmap. */
3540	uint32_t u32XcptBitmap;
3541	/** 0x90 - Page-fault exception error mask. */
3542	uint32_t u32XcptPFMask;
3543	/** 0x94 - Page-fault exception error match. */
3544	uint32_t u32XcptPFMatch;
3545	/** 0x98 - CR3-target count. */
3546	uint32_t u32Cr3TargetCount;
3547	/** 0x9c - VM-exit controls. */
3548	uint32_t u32ExitCtls;
3549	/** 0xa0 - VM-exit MSR store count. */
3550	uint32_t u32ExitMsrStoreCount;
3551	/** 0xa4 - VM-exit MSR load count. */
3552	uint32_t u32ExitMsrLoadCount;
3553	/** 0xa8 - VM-entry controls. */
3554	uint32_t u32EntryCtls;
3555	/** 0xac - VM-entry MSR load count. */
3556	uint32_t u32EntryMsrLoadCount;
3557	/** 0xb0 - VM-entry interruption information. */
3558	uint32_t u32EntryIntInfo;
3559	/** 0xb4 - VM-entry exception error code. */
3560	uint32_t u32EntryXcptErrCode;
3561	/** 0xb8 - VM-entry instruction length. */
3562	uint32_t u32EntryInstrLen;
3563	/** 0xbc - TPR-threshold. */
3564	uint32_t u32TprThreshold;
3565	/** 0xc0 - Secondary-processor based VM-execution controls. */
3566	uint32_t u32ProcCtls2;
3567	/** 0xc4 - Pause-loop exiting Gap. */
3568	uint32_t u32PleGap;
3569	/** 0xc8 - Pause-loop exiting Window. */
3570	uint32_t u32PleWindow;
3571	/** 0xcc - Reserved for future. */
3572	uint32_t au32Reserved1[8];
3573	/** @} */
3574
3575	/** @name 32-bit Read-only Data fields.
3576	* @{ */
3577	/** 0xec - VM-instruction error. */
3578	uint32_t u32RoVmInstrError;
3579	/** 0xf0 - VM-exit reason. */
3580	uint32_t u32RoExitReason;
3581	/** 0xf4 - VM-exit interruption information. */
3582	uint32_t u32RoExitIntInfo;
3583	/** 0xf8 - VM-exit interruption error code. */
3584	uint32_t u32RoExitIntErrCode;
3585	/** 0xfc - IDT-vectoring information. */
3586	uint32_t u32RoIdtVectoringInfo;
3587	/** 0x100 - IDT-vectoring error code. */
3588	uint32_t u32RoIdtVectoringErrCode;
3589	/** 0x104 - VM-exit instruction length. */
3590	uint32_t u32RoExitInstrLen;
3591	/** 0x108 - VM-exit instruction information. */
3592	uint32_t u32RoExitInstrInfo;
3593	/** 0x10c - Reserved for future. */
3594	uint32_t au32RoReserved2[8];
3595	/** @} */
3596
3597	/** @name 32-bit Guest-state fields.
3598	* Order of [ES..GS] limit and attributes are important, must match X86_SREG_XXX.
3599	* @{ */
3600	/** 0x12c - Guest ES limit. */
3601	uint32_t u32GuestEsLimit;
3602	/** 0x130 - Guest CS limit. */
3603	uint32_t u32GuestCsLimit;
3604	/** 0x134 - Guest SS limit. */
3605	uint32_t u32GuestSsLimit;
3606	/** 0x138 - Guest DS limit. */
3607	uint32_t u32GuestDsLimit;
3608	/** 0x13c - Guest FS limit. */
3609	uint32_t u32GuestFsLimit;
3610	/** 0x140 - Guest GS limit. */
3611	uint32_t u32GuestGsLimit;
3612	/** 0x144 - Guest LDTR limit. */
3613	uint32_t u32GuestLdtrLimit;
3614	/** 0x148 - Guest TR limit. */
3615	uint32_t u32GuestTrLimit;
3616	/** 0x14c - Guest GDTR limit. */
3617	uint32_t u32GuestGdtrLimit;
3618	/** 0x150 - Guest IDTR limit. */
3619	uint32_t u32GuestIdtrLimit;
3620	/** 0x154 - Guest ES attributes. */
3621	uint32_t u32GuestEsAttr;
3622	/** 0x158 - Guest CS attributes. */
3623	uint32_t u32GuestCsAttr;
3624	/** 0x15c - Guest SS attributes. */
3625	uint32_t u32GuestSsAttr;
3626	/** 0x160 - Guest DS attributes. */
3627	uint32_t u32GuestDsAttr;
3628	/** 0x164 - Guest FS attributes. */
3629	uint32_t u32GuestFsAttr;
3630	/** 0x168 - Guest GS attributes. */
3631	uint32_t u32GuestGsAttr;
3632	/** 0x16c - Guest LDTR attributes. */
3633	uint32_t u32GuestLdtrAttr;
3634	/** 0x170 - Guest TR attributes. */
3635	uint32_t u32GuestTrAttr;
3636	/** 0x174 - Guest interruptibility state. */
3637	uint32_t u32GuestIntrState;
3638	/** 0x178 - Guest activity state. */
3639	uint32_t u32GuestActivityState;
3640	/** 0x17c - Guest SMBASE. */
3641	uint32_t u32GuestSmBase;
3642	/** 0x180 - Guest SYSENTER CS. */
3643	uint32_t u32GuestSysenterCS;
3644	/** 0x184 - Preemption timer value. */
3645	uint32_t u32PreemptTimer;
3646	/** 0x188 - Reserved for future. */
3647	uint32_t au32Reserved3[8];
3648	/** @} */
3649
3650	/** @name 32-bit Host-state fields.
3651	* @{ */
3652	/** 0x1a8 - Host SYSENTER CS. */
3653	uint32_t u32HostSysenterCs;
3654	/** 0x1ac - Reserved for future. */
3655	uint32_t au32Reserved4[11];
3656	/** @} */
3657
3658	/** @name 64-bit Control fields.
3659	* @{ */
3660	/** 0x1d8 - I/O bitmap A address. */
3661	RTUINT64U u64AddrIoBitmapA;
3662	/** 0x1e0 - I/O bitmap B address. */
3663	RTUINT64U u64AddrIoBitmapB;
3664	/** 0x1e8 - MSR bitmap address. */
3665	RTUINT64U u64AddrMsrBitmap;
3666	/** 0x1f0 - VM-exit MSR-store area address. */
3667	RTUINT64U u64AddrExitMsrStore;
3668	/** 0x1f8 - VM-exit MSR-load area address. */
3669	RTUINT64U u64AddrExitMsrLoad;
3670	/** 0x200 - VM-entry MSR-load area address. */
3671	RTUINT64U u64AddrEntryMsrLoad;
3672	/** 0x208 - Executive-VMCS pointer. */
3673	RTUINT64U u64ExecVmcsPtr;
3674	/** 0x210 - PML address. */
3675	RTUINT64U u64AddrPml;
3676	/** 0x218 - TSC offset. */
3677	RTUINT64U u64TscOffset;
3678	/** 0x220 - Virtual-APIC address. */
3679	RTUINT64U u64AddrVirtApic;
3680	/** 0x228 - APIC-access address. */
3681	RTUINT64U u64AddrApicAccess;
3682	/** 0x230 - Posted-interrupt descriptor address. */
3683	RTUINT64U u64AddrPostedIntDesc;
3684	/** 0x238 - VM-functions control. */
3685	RTUINT64U u64VmFuncCtls;
3686	/** 0x240 - EPTP pointer. */
3687	RTUINT64U u64EptpPtr;
3688	/** 0x248 - EOI-exit bitmap 0. */
3689	RTUINT64U u64EoiExitBitmap0;
3690	/** 0x250 - EOI-exit bitmap 1. */
3691	RTUINT64U u64EoiExitBitmap1;
3692	/** 0x258 - EOI-exit bitmap 2. */
3693	RTUINT64U u64EoiExitBitmap2;
3694	/** 0x260 - EOI-exit bitmap 3. */
3695	RTUINT64U u64EoiExitBitmap3;
3696	/** 0x268 - EPTP-list address. */
3697	RTUINT64U u64AddrEptpList;
3698	/** 0x270 - VMREAD-bitmap address. */
3699	RTUINT64U u64AddrVmreadBitmap;
3700	/** 0x278 - VMWRITE-bitmap address. */
3701	RTUINT64U u64AddrVmwriteBitmap;
3702	/** 0x280 - Virtualization-exception information address. */
3703	RTUINT64U u64AddrXcptVeInfo;
3704	/** 0x288 - XSS-exiting bitmap. */
3705	RTUINT64U u64XssBitmap;
3706	/** 0x290 - ENCLS-exiting bitmap address. */
3707	RTUINT64U u64EnclsBitmap;
3708	/** 0x298 - Sub-page-permission-table pointer. */
3709	RTUINT64U u64SpptPtr;
3710	/** 0x2a0 - TSC multiplier. */
3711	RTUINT64U u64TscMultiplier;
3712	/** 0x2a8 - Reserved for future. */
3713	RTUINT64U au64Reserved0[15];
3714	/** @} */
3715
3716	/** @name 64-bit Read-only Data fields.
3717	* @{ */
3718	/** 0x320 - Guest-physical address. */
3719	RTUINT64U u64RoGuestPhysAddr;
3720	/** 0x328 - Reserved for future. */
3721	RTUINT64U au64Reserved1[8];
3722	/** @} */
3723
3724	/** @name 64-bit Guest-state fields.
3725	* @{ */
3726	/** 0x368 - VMCS link pointer. */
3727	RTUINT64U u64VmcsLinkPtr;
3728	/** 0x370 - Guest debug-control MSR. */
3729	RTUINT64U u64GuestDebugCtlMsr;
3730	/** 0x378 - Guest PAT MSR. */
3731	RTUINT64U u64GuestPatMsr;
3732	/** 0x380 - Guest EFER MSR. */
3733	RTUINT64U u64GuestEferMsr;
3734	/** 0x388 - Guest global performance-control MSR. */
3735	RTUINT64U u64GuestPerfGlobalCtlMsr;
3736	/** 0x390 - Guest PDPTE 0. */
3737	RTUINT64U u64GuestPdpte0;
3738	/** 0x398 - Guest PDPTE 0. */
3739	RTUINT64U u64GuestPdpte1;
3740	/** 0x3a0 - Guest PDPTE 1. */
3741	RTUINT64U u64GuestPdpte2;
3742	/** 0x3a8 - Guest PDPTE 2. */
3743	RTUINT64U u64GuestPdpte3;
3744	/** 0x3b0 - Guest Bounds-config MSR (Intel MPX - Memory Protection Extensions). */
3745	RTUINT64U u64GuestBndcfgsMsr;
3746	/** 0x3b8 - Guest RTIT control MSR (Intel Real Time Instruction Trace). */
3747	RTUINT64U u64GuestRtitCtlMsr;
3748	/** 0x3c0 - Reserved for future. */
3749	RTUINT64U au64Reserved2[15];
3750	/** @} */
3751
3752	/** @name 64-bit Host-state Fields.
3753	* @{ */
3754	/** 0x438 - Host PAT MSR. */
3755	RTUINT64U u64HostPatMsr;
3756	/** 0x440 - Host EFER MSR. */
3757	RTUINT64U u64HostEferMsr;
3758	/** 0x448 - Host global performance-control MSR. */
3759	RTUINT64U u64HostPerfGlobalCtlMsr;
3760	/** 0x450 - Reserved for future. */
3761	RTUINT64U au64Reserved3[16];
3762	/** @} */
3763
3764	/** @name Natural-width Control fields.
3765	* @{ */
3766	/** 0x4d0 - CR0 guest/host Mask. */
3767	RTUINT64U u64Cr0Mask;
3768	/** 0x4d8 - CR4 guest/host Mask. */
3769	RTUINT64U u64Cr4Mask;
3770	/** 0x4e0 - CR0 read shadow. */
3771	RTUINT64U u64Cr0ReadShadow;
3772	/** 0x4e8 - CR4 read shadow. */
3773	RTUINT64U u64Cr4ReadShadow;
3774	/** 0x4f0 - CR3-target value 0. */
3775	RTUINT64U u64Cr3Target0;
3776	/** 0x4f8 - CR3-target value 1. */
3777	RTUINT64U u64Cr3Target1;
3778	/** 0x500 - CR3-target value 2. */
3779	RTUINT64U u64Cr3Target2;
3780	/** 0x508 - CR3-target value 3. */
3781	RTUINT64U u64Cr3Target3;
3782	/** 0x510 - Reserved for future. */
3783	RTUINT64U au64Reserved4[32];
3784	/** @} */
3785
3786	/** @name Natural-width Read-only Data fields.
3787	* @{ */
3788	/** 0x610 - Exit qualification. */
3789	RTUINT64U u64RoExitQual;
3790	/** 0x618 - I/O RCX. */
3791	RTUINT64U u64RoIoRcx;
3792	/** 0x620 - I/O RSI. */
3793	RTUINT64U u64RoIoRsi;
3794	/** 0x628 - I/O RDI. */
3795	RTUINT64U u64RoIoRdi;
3796	/** 0x630 - I/O RIP. */
3797	RTUINT64U u64RoIoRip;
3798	/** 0x638 - Guest-linear address. */
3799	RTUINT64U u64RoGuestLinearAddr;
3800	/** 0x640 - Reserved for future. */
3801	RTUINT64U au64Reserved5[16];
3802	/** @} */
3803
3804	/** @name Natural-width Guest-state Fields.
3805	* Order of [ES..GS] base is important, must match X86_SREG_XXX.
3806	* @{ */
3807	/** 0x6c0 - Guest CR0. */
3808	RTUINT64U u64GuestCr0;
3809	/** 0x6c8 - Guest CR3. */
3810	RTUINT64U u64GuestCr3;
3811	/** 0x6d0 - Guest CR4. */
3812	RTUINT64U u64GuestCr4;
3813	/** 0x6d8 - Guest ES base. */
3814	RTUINT64U u64GuestEsBase;
3815	/** 0x6e0 - Guest CS base. */
3816	RTUINT64U u64GuestCsBase;
3817	/** 0x6e8 - Guest SS base. */
3818	RTUINT64U u64GuestSsBase;
3819	/** 0x6f0 - Guest DS base. */
3820	RTUINT64U u64GuestDsBase;
3821	/** 0x6f8 - Guest FS base. */
3822	RTUINT64U u64GuestFsBase;
3823	/** 0x700 - Guest GS base. */
3824	RTUINT64U u64GuestGsBase;
3825	/** 0x708 - Guest LDTR base. */
3826	RTUINT64U u64GuestLdtrBase;
3827	/** 0x710 - Guest TR base. */
3828	RTUINT64U u64GuestTrBase;
3829	/** 0x718 - Guest GDTR base. */
3830	RTUINT64U u64GuestGdtrBase;
3831	/** 0x720 - Guest IDTR base. */
3832	RTUINT64U u64GuestIdtrBase;
3833	/** 0x728 - Guest DR7. */
3834	RTUINT64U u64GuestDr7;
3835	/** 0x730 - Guest RSP. */
3836	RTUINT64U u64GuestRsp;
3837	/** 0x738 - Guest RIP. */
3838	RTUINT64U u64GuestRip;
3839	/** 0x740 - Guest RFLAGS. */
3840	RTUINT64U u64GuestRFlags;
3841	/** 0x748 - Guest pending debug exception. */
3842	RTUINT64U u64GuestPendingDbgXcpt;
3843	/** 0x750 - Guest SYSENTER ESP. */
3844	RTUINT64U u64GuestSysenterEsp;
3845	/** 0x758 - Guest SYSENTER EIP. */
3846	RTUINT64U u64GuestSysenterEip;
3847	/** 0x760 - Reserved for future. */
3848	RTUINT64U au64Reserved6[32];
3849	/** @} */
3850
3851	/** @name Natural-width Host-state fields.
3852	* @{ */
3853	/** 0x860 - Host CR0. */
3854	RTUINT64U u64HostCr0;
3855	/** 0x868 - Host CR3. */
3856	RTUINT64U u64HostCr3;
3857	/** 0x870 - Host CR4. */
3858	RTUINT64U u64HostCr4;
3859	/** 0x878 - Host FS base. */
3860	RTUINT64U u64HostFsBase;
3861	/** 0x880 - Host GS base. */
3862	RTUINT64U u64HostGsBase;
3863	/** 0x888 - Host TR base. */
3864	RTUINT64U u64HostTrBase;
3865	/** 0x890 - Host GDTR base. */
3866	RTUINT64U u64HostGdtrBase;
3867	/** 0x898 - Host IDTR base. */
3868	RTUINT64U u64HostIdtrBase;
3869	/** 0x8a0 - Host SYSENTER ESP base. */
3870	RTUINT64U u64HostSysenterEsp;
3871	/** 0x8a8 - Host SYSENTER ESP base. */
3872	RTUINT64U u64HostSysenterEip;
3873	/** 0x8b0 - Host RSP. */
3874	RTUINT64U u64HostRsp;
3875	/** 0x8b8 - Host RIP. */
3876	RTUINT64U u64HostRip;
3877	/** 0x8c0 - Reserved for future. */
3878	RTUINT64U au64Reserved7[32];
3879	/** @} */
3880
3881	/** 0x9c0 - Padding. */
3882	uint8_t abPadding[X86_PAGE_4K_SIZE - 0x9c0];
3883	} VMXVVMCS;
3884	#pragma pack()
3885	/** Pointer to the VMXVVMCS struct. */
3886	typedef VMXVVMCS *PVMXVVMCS;
3887	/** Pointer to a const VMXVVMCS struct. */
3888	typedef const VMXVVMCS *PCVMXVVMCS;
3889	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
3890	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
3891	AssertCompileMemberOffset(VMXVVMCS, enmVmxAbort, 0x004);
3892	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
3893	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x028);
3894	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x03e);
3895	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x062);
3896	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x084);
3897	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x0ec);
3898	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x12c);
3899	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x1a8);
3900	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x1d8);
3901	AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x320);
3902	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x368);
3903	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x438);
3904	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x4d0);
3905	AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x610);
3906	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x6c0);
3907	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x860);
3908
3909	/**
3910	* Virtual VMX-instruction and VM-exit diagnostics.
3911	*
3912	* These are not the same as VM instruction errors that are enumerated in the Intel
3913	* spec. These are purely internal, fine-grained definitions used for diagnostic
3914	* purposes and are not reported to guest software under the VM-instruction error
3915	* field in its VMCS.
3916	*
3917	* @note Members of this enum are used as array indices, so no gaps are allowed.
3918	* Please update g_apszVmxVDiagDesc when you add new fields to this enum.
3919	*/
3920	typedef enum
3921	{
3922	/* Internal processing errors. */
3923	kVmxVDiag_None = 0,
3924	kVmxVDiag_Ipe_1,
3925	kVmxVDiag_Ipe_2,
3926	kVmxVDiag_Ipe_3,
3927	kVmxVDiag_Ipe_4,
3928	kVmxVDiag_Ipe_5,
3929	kVmxVDiag_Ipe_6,
3930	kVmxVDiag_Ipe_7,
3931	kVmxVDiag_Ipe_8,
3932	kVmxVDiag_Ipe_9,
3933	kVmxVDiag_Ipe_10,
3934	kVmxVDiag_Ipe_11,
3935	kVmxVDiag_Ipe_12,
3936	kVmxVDiag_Ipe_13,
3937	kVmxVDiag_Ipe_14,
3938	kVmxVDiag_Ipe_15,
3939	kVmxVDiag_Ipe_16,
3940	/* VMXON. */
3941	kVmxVDiag_Vmxon_A20M,
3942	kVmxVDiag_Vmxon_Cpl,
3943	kVmxVDiag_Vmxon_Cr0Fixed0,
3944	kVmxVDiag_Vmxon_Cr0Fixed1,
3945	kVmxVDiag_Vmxon_Cr4Fixed0,
3946	kVmxVDiag_Vmxon_Cr4Fixed1,
3947	kVmxVDiag_Vmxon_Intercept,
3948	kVmxVDiag_Vmxon_LongModeCS,
3949	kVmxVDiag_Vmxon_MsrFeatCtl,
3950	kVmxVDiag_Vmxon_PtrAbnormal,
3951	kVmxVDiag_Vmxon_PtrAlign,
3952	kVmxVDiag_Vmxon_PtrMap,
3953	kVmxVDiag_Vmxon_PtrReadPhys,
3954	kVmxVDiag_Vmxon_PtrWidth,
3955	kVmxVDiag_Vmxon_RealOrV86Mode,
3956	kVmxVDiag_Vmxon_ShadowVmcs,
3957	kVmxVDiag_Vmxon_VmxAlreadyRoot,
3958	kVmxVDiag_Vmxon_Vmxe,
3959	kVmxVDiag_Vmxon_VmcsRevId,
3960	kVmxVDiag_Vmxon_VmxRootCpl,
3961	/* VMXOFF. */
3962	kVmxVDiag_Vmxoff_Cpl,
3963	kVmxVDiag_Vmxoff_Intercept,
3964	kVmxVDiag_Vmxoff_LongModeCS,
3965	kVmxVDiag_Vmxoff_RealOrV86Mode,
3966	kVmxVDiag_Vmxoff_Vmxe,
3967	kVmxVDiag_Vmxoff_VmxRoot,
3968	/* VMPTRLD. */
3969	kVmxVDiag_Vmptrld_Cpl,
3970	kVmxVDiag_Vmptrld_LongModeCS,
3971	kVmxVDiag_Vmptrld_PtrAbnormal,
3972	kVmxVDiag_Vmptrld_PtrAlign,
3973	kVmxVDiag_Vmptrld_PtrMap,
3974	kVmxVDiag_Vmptrld_PtrReadPhys,
3975	kVmxVDiag_Vmptrld_PtrVmxon,
3976	kVmxVDiag_Vmptrld_PtrWidth,
3977	kVmxVDiag_Vmptrld_RealOrV86Mode,
3978	kVmxVDiag_Vmptrld_RevPtrReadPhys,
3979	kVmxVDiag_Vmptrld_ShadowVmcs,
3980	kVmxVDiag_Vmptrld_VmcsRevId,
3981	kVmxVDiag_Vmptrld_VmxRoot,
3982	/* VMPTRST. */
3983	kVmxVDiag_Vmptrst_Cpl,
3984	kVmxVDiag_Vmptrst_LongModeCS,
3985	kVmxVDiag_Vmptrst_PtrMap,
3986	kVmxVDiag_Vmptrst_RealOrV86Mode,
3987	kVmxVDiag_Vmptrst_VmxRoot,
3988	/* VMCLEAR. */
3989	kVmxVDiag_Vmclear_Cpl,
3990	kVmxVDiag_Vmclear_LongModeCS,
3991	kVmxVDiag_Vmclear_PtrAbnormal,
3992	kVmxVDiag_Vmclear_PtrAlign,
3993	kVmxVDiag_Vmclear_PtrMap,
3994	kVmxVDiag_Vmclear_PtrReadPhys,
3995	kVmxVDiag_Vmclear_PtrVmxon,
3996	kVmxVDiag_Vmclear_PtrWidth,
3997	kVmxVDiag_Vmclear_RealOrV86Mode,
3998	kVmxVDiag_Vmclear_VmxRoot,
3999	/* VMWRITE. */
4000	kVmxVDiag_Vmwrite_Cpl,
4001	kVmxVDiag_Vmwrite_FieldInvalid,
4002	kVmxVDiag_Vmwrite_FieldRo,
4003	kVmxVDiag_Vmwrite_LinkPtrInvalid,
4004	kVmxVDiag_Vmwrite_LongModeCS,
4005	kVmxVDiag_Vmwrite_PtrInvalid,
4006	kVmxVDiag_Vmwrite_PtrMap,
4007	kVmxVDiag_Vmwrite_RealOrV86Mode,
4008	kVmxVDiag_Vmwrite_VmxRoot,
4009	/* VMREAD. */
4010	kVmxVDiag_Vmread_Cpl,
4011	kVmxVDiag_Vmread_FieldInvalid,
4012	kVmxVDiag_Vmread_LinkPtrInvalid,
4013	kVmxVDiag_Vmread_LongModeCS,
4014	kVmxVDiag_Vmread_PtrInvalid,
4015	kVmxVDiag_Vmread_PtrMap,
4016	kVmxVDiag_Vmread_RealOrV86Mode,
4017	kVmxVDiag_Vmread_VmxRoot,
4018	/* INVVPID. */
4019	kVmxVDiag_Invvpid_Cpl,
4020	kVmxVDiag_Invvpid_DescRsvd,
4021	kVmxVDiag_Invvpid_LongModeCS,
4022	kVmxVDiag_Invvpid_RealOrV86Mode,
4023	kVmxVDiag_Invvpid_TypeInvalid,
4024	kVmxVDiag_Invvpid_Type0InvalidAddr,
4025	kVmxVDiag_Invvpid_Type0InvalidVpid,
4026	kVmxVDiag_Invvpid_Type1InvalidVpid,
4027	kVmxVDiag_Invvpid_Type3InvalidVpid,
4028	kVmxVDiag_Invvpid_VmxRoot,
4029	/* VMLAUNCH/VMRESUME. */
4030	kVmxVDiag_Vmentry_AddrApicAccess,
4031	kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
4032	kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
4033	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
4034	kVmxVDiag_Vmentry_AddrExitMsrLoad,
4035	kVmxVDiag_Vmentry_AddrExitMsrStore,
4036	kVmxVDiag_Vmentry_AddrIoBitmapA,
4037	kVmxVDiag_Vmentry_AddrIoBitmapB,
4038	kVmxVDiag_Vmentry_AddrMsrBitmap,
4039	kVmxVDiag_Vmentry_AddrVirtApicPage,
4040	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
4041	kVmxVDiag_Vmentry_AddrVmreadBitmap,
4042	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
4043	kVmxVDiag_Vmentry_ApicRegVirt,
4044	kVmxVDiag_Vmentry_BlocKMovSS,
4045	kVmxVDiag_Vmentry_Cpl,
4046	kVmxVDiag_Vmentry_Cr3TargetCount,
4047	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
4048	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
4049	kVmxVDiag_Vmentry_EntryInstrLen,
4050	kVmxVDiag_Vmentry_EntryInstrLenZero,
4051	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
4052	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
4053	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
4054	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
4055	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
4056	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
4057	kVmxVDiag_Vmentry_GuestActStateHlt,
4058	kVmxVDiag_Vmentry_GuestActStateRsvd,
4059	kVmxVDiag_Vmentry_GuestActStateShutdown,
4060	kVmxVDiag_Vmentry_GuestActStateSsDpl,
4061	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
4062	kVmxVDiag_Vmentry_GuestCr0Fixed0,
4063	kVmxVDiag_Vmentry_GuestCr0Fixed1,
4064	kVmxVDiag_Vmentry_GuestCr0PgPe,
4065	kVmxVDiag_Vmentry_GuestCr3,
4066	kVmxVDiag_Vmentry_GuestCr4Fixed0,
4067	kVmxVDiag_Vmentry_GuestCr4Fixed1,
4068	kVmxVDiag_Vmentry_GuestDebugCtl,
4069	kVmxVDiag_Vmentry_GuestDr7,
4070	kVmxVDiag_Vmentry_GuestEferMsr,
4071	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
4072	kVmxVDiag_Vmentry_GuestGdtrBase,
4073	kVmxVDiag_Vmentry_GuestGdtrLimit,
4074	kVmxVDiag_Vmentry_GuestIdtrBase,
4075	kVmxVDiag_Vmentry_GuestIdtrLimit,
4076	kVmxVDiag_Vmentry_GuestIntStateEnclave,
4077	kVmxVDiag_Vmentry_GuestIntStateExtInt,
4078	kVmxVDiag_Vmentry_GuestIntStateNmi,
4079	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
4080	kVmxVDiag_Vmentry_GuestIntStateRsvd,
4081	kVmxVDiag_Vmentry_GuestIntStateSmi,
4082	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
4083	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
4084	kVmxVDiag_Vmentry_GuestPae,
4085	kVmxVDiag_Vmentry_GuestPatMsr,
4086	kVmxVDiag_Vmentry_GuestPcide,
4087	kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys,
4088	kVmxVDiag_Vmentry_GuestPdpte0Rsvd,
4089	kVmxVDiag_Vmentry_GuestPdpte1Rsvd,
4090	kVmxVDiag_Vmentry_GuestPdpte2Rsvd,
4091	kVmxVDiag_Vmentry_GuestPdpte3Rsvd,
4092	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
4093	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
4094	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
4095	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
4096	kVmxVDiag_Vmentry_GuestRip,
4097	kVmxVDiag_Vmentry_GuestRipRsvd,
4098	kVmxVDiag_Vmentry_GuestRFlagsIf,
4099	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
4100	kVmxVDiag_Vmentry_GuestRFlagsVm,
4101	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
4102	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
4103	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
4104	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
4105	kVmxVDiag_Vmentry_GuestSegAttrCsType,
4106	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
4107	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
4108	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
4109	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
4110	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
4111	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
4112	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
4113	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
4114	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
4115	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
4116	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
4117	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
4118	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
4119	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
4120	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
4121	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
4122	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
4123	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
4124	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
4125	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
4126	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
4127	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
4128	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
4129	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
4130	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
4131	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
4132	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
4133	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
4134	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
4135	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
4136	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
4137	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
4138	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
4139	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
4140	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
4141	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
4142	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
4143	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
4144	kVmxVDiag_Vmentry_GuestSegAttrSsType,
4145	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
4146	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
4147	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
4148	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
4149	kVmxVDiag_Vmentry_GuestSegAttrTrType,
4150	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
4151	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
4152	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
4153	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
4154	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
4155	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
4156	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
4157	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
4158	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
4159	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
4160	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
4161	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
4162	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
4163	kVmxVDiag_Vmentry_GuestSegBaseCs,
4164	kVmxVDiag_Vmentry_GuestSegBaseDs,
4165	kVmxVDiag_Vmentry_GuestSegBaseEs,
4166	kVmxVDiag_Vmentry_GuestSegBaseFs,
4167	kVmxVDiag_Vmentry_GuestSegBaseGs,
4168	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
4169	kVmxVDiag_Vmentry_GuestSegBaseSs,
4170	kVmxVDiag_Vmentry_GuestSegBaseTr,
4171	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
4172	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
4173	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
4174	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
4175	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
4176	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
4177	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
4178	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
4179	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
4180	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
4181	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
4182	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
4183	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
4184	kVmxVDiag_Vmentry_GuestSegSelLdtr,
4185	kVmxVDiag_Vmentry_GuestSegSelTr,
4186	kVmxVDiag_Vmentry_GuestSysenterEspEip,
4187	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
4188	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
4189	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
4190	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
4191	kVmxVDiag_Vmentry_HostCr0Fixed0,
4192	kVmxVDiag_Vmentry_HostCr0Fixed1,
4193	kVmxVDiag_Vmentry_HostCr3,
4194	kVmxVDiag_Vmentry_HostCr4Fixed0,
4195	kVmxVDiag_Vmentry_HostCr4Fixed1,
4196	kVmxVDiag_Vmentry_HostCr4Pae,
4197	kVmxVDiag_Vmentry_HostCr4Pcide,
4198	kVmxVDiag_Vmentry_HostCsTr,
4199	kVmxVDiag_Vmentry_HostEferMsr,
4200	kVmxVDiag_Vmentry_HostEferMsrRsvd,
4201	kVmxVDiag_Vmentry_HostGuestLongMode,
4202	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4203	kVmxVDiag_Vmentry_HostLongMode,
4204	kVmxVDiag_Vmentry_HostPatMsr,
4205	kVmxVDiag_Vmentry_HostRip,
4206	kVmxVDiag_Vmentry_HostRipRsvd,
4207	kVmxVDiag_Vmentry_HostSel,
4208	kVmxVDiag_Vmentry_HostSegBase,
4209	kVmxVDiag_Vmentry_HostSs,
4210	kVmxVDiag_Vmentry_HostSysenterEspEip,
4211	kVmxVDiag_Vmentry_LongModeCS,
4212	kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4213	kVmxVDiag_Vmentry_MsrLoad,
4214	kVmxVDiag_Vmentry_MsrLoadCount,
4215	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4216	kVmxVDiag_Vmentry_MsrLoadRing3,
4217	kVmxVDiag_Vmentry_MsrLoadRsvd,
4218	kVmxVDiag_Vmentry_NmiWindowExit,
4219	kVmxVDiag_Vmentry_PinCtlsAllowed1,
4220	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4221	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4222	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4223	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4224	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4225	kVmxVDiag_Vmentry_PtrInvalid,
4226	kVmxVDiag_Vmentry_PtrShadowVmcs,
4227	kVmxVDiag_Vmentry_RealOrV86Mode,
4228	kVmxVDiag_Vmentry_SavePreemptTimer,
4229	kVmxVDiag_Vmentry_TprThresholdRsvd,
4230	kVmxVDiag_Vmentry_TprThresholdVTpr,
4231	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4232	kVmxVDiag_Vmentry_VirtIntDelivery,
4233	kVmxVDiag_Vmentry_VirtNmi,
4234	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4235	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4236	kVmxVDiag_Vmentry_VmcsClear,
4237	kVmxVDiag_Vmentry_VmcsLaunch,
4238	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4239	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4240	kVmxVDiag_Vmentry_VmxRoot,
4241	kVmxVDiag_Vmentry_Vpid,
4242	kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys,
4243	kVmxVDiag_Vmexit_HostPdpte0Rsvd,
4244	kVmxVDiag_Vmexit_HostPdpte1Rsvd,
4245	kVmxVDiag_Vmexit_HostPdpte2Rsvd,
4246	kVmxVDiag_Vmexit_HostPdpte3Rsvd,
4247	kVmxVDiag_Vmexit_MsrLoad,
4248	kVmxVDiag_Vmexit_MsrLoadCount,
4249	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4250	kVmxVDiag_Vmexit_MsrLoadRing3,
4251	kVmxVDiag_Vmexit_MsrLoadRsvd,
4252	kVmxVDiag_Vmexit_MsrStore,
4253	kVmxVDiag_Vmexit_MsrStoreCount,
4254	kVmxVDiag_Vmexit_MsrStorePtrReadPhys,
4255	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4256	kVmxVDiag_Vmexit_MsrStoreRing3,
4257	kVmxVDiag_Vmexit_MsrStoreRsvd,
4258	/* Last member for determining array index limit. */
4259	kVmxVDiag_End
4260	} VMXVDIAG;
4261	AssertCompileSize(VMXVDIAG, 4);
4262
4263	/** @} */
4264
4265	/** @} */
4266
4267	#endif /* !VBOX_INCLUDED_vmm_hm_vmx_h */
4268

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 78650

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