hm_vmx.h@ 79221

Last change on this file since 79221 was 79221, checked in by vboxsync, 6 years ago
hm_vmx.h: Nested VMX: bugref:9180 Add invalid-guest state reason related to VMCS shadowing for upcoming changes.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_hm_vmx_h
27	#define VBOX_INCLUDED_vmm_hm_vmx_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <iprt/x86.h>
34	#include <iprt/assertcompile.h>
35
36	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
37	when targeting AMD64. */
38	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
39	# pragma warning(push)
40	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
41	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
42	# include <intrin.h>
43	# pragma warning(pop)
44	/* We always want them as intrinsics, no functions. */
45	# pragma intrinsic(__vmx_on)
46	# pragma intrinsic(__vmx_off)
47	# pragma intrinsic(__vmx_vmclear)
48	# pragma intrinsic(__vmx_vmptrld)
49	# pragma intrinsic(__vmx_vmread)
50	# pragma intrinsic(__vmx_vmwrite)
51	# define VMX_USE_MSC_INTRINSICS 1
52	#else
53	# define VMX_USE_MSC_INTRINSICS 0
54	#endif
55
56
57	/** @defgroup grp_hm_vmx VMX Types and Definitions
58	* @ingroup grp_hm
59	* @{
60	*/
61
62	/** @name Host-state restoration flags.
63	* @note If you change these values don't forget to update the assembly
64	* defines as well!
65	* @{
66	*/
67	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
68	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
69	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
70	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
71	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
72	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
73	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
74	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
75	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
76	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
77	/** @} */
78
79	/**
80	* Host-state restoration structure.
81	* This holds host-state fields that require manual restoration.
82	* Assembly version found in hm_vmx.mac (should be automatically verified).
83	*/
84	typedef struct VMXRESTOREHOST
85	{
86	RTSEL uHostSelDS; /* 0x00 */
87	RTSEL uHostSelES; /* 0x02 */
88	RTSEL uHostSelFS; /* 0x04 */
89	RTSEL uHostSelGS; /* 0x06 */
90	RTSEL uHostSelTR; /* 0x08 */
91	uint8_t abPadding0[4];
92	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
93	uint8_t abPadding1[6];
94	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
95	uint8_t abPadding2[6];
96	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
97	uint64_t uHostFSBase; /* 0x38 */
98	uint64_t uHostGSBase; /* 0x40 */
99	} VMXRESTOREHOST;
100	/** Pointer to VMXRESTOREHOST. */
101	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
102	AssertCompileSize(X86XDTR64, 10);
103	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
104	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
105	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
106	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
107	AssertCompileSize(VMXRESTOREHOST, 72);
108	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
109
110	/** @name Host-state MSR lazy-restoration flags.
111	* @{
112	*/
113	/** The host MSRs have been saved. */
114	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
115	/** The guest MSRs are loaded and in effect. */
116	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
117	/** @} */
118
119	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
120	* UFC = Unsupported Feature Combination.
121	* @{
122	*/
123	/** Unsupported pin-based VM-execution controls combo. */
124	#define VMX_UFC_CTRL_PIN_EXEC 1
125	/** Unsupported processor-based VM-execution controls combo. */
126	#define VMX_UFC_CTRL_PROC_EXEC 2
127	/** Unsupported move debug register VM-exit combo. */
128	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
129	/** Unsupported VM-entry controls combo. */
130	#define VMX_UFC_CTRL_ENTRY 4
131	/** Unsupported VM-exit controls combo. */
132	#define VMX_UFC_CTRL_EXIT 5
133	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
134	* for storing host MSRs. */
135	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
136	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
137	* for storing guest MSRs. */
138	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
139	/** Invalid VMCS size. */
140	#define VMX_UFC_INVALID_VMCS_SIZE 8
141	/** Unsupported secondary processor-based VM-execution controls combo. */
142	#define VMX_UFC_CTRL_PROC_EXEC2 9
143	/** Invalid unrestricted-guest execution controls combo. */
144	#define VMX_UFC_INVALID_UX_COMBO 10
145	/** EPT flush type not supported. */
146	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
147	/** EPT paging structure memory type is not write-back. */
148	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
149	/** EPT requires INVEPT instr. support but it's not available. */
150	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
151	/** EPT requires page-walk length of 4. */
152	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
153	/** @} */
154
155	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
156	* VCI = VMCS-field Cache Invalid.
157	* @{
158	*/
159	/** Cache of VM-entry controls invalid. */
160	#define VMX_VCI_CTRL_ENTRY 300
161	/** Cache of VM-exit controls invalid. */
162	#define VMX_VCI_CTRL_EXIT 301
163	/** Cache of pin-based VM-execution controls invalid. */
164	#define VMX_VCI_CTRL_PIN_EXEC 302
165	/** Cache of processor-based VM-execution controls invalid. */
166	#define VMX_VCI_CTRL_PROC_EXEC 303
167	/** Cache of secondary processor-based VM-execution controls invalid. */
168	#define VMX_VCI_CTRL_PROC_EXEC2 304
169	/** Cache of exception bitmap invalid. */
170	#define VMX_VCI_CTRL_XCPT_BITMAP 305
171	/** Cache of TSC offset invalid. */
172	#define VMX_VCI_CTRL_TSC_OFFSET 306
173	/** @} */
174
175	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
176	* IGS = Invalid Guest State.
177	* @{
178	*/
179	/** An error occurred while checking invalid-guest-state. */
180	#define VMX_IGS_ERROR 500
181	/** The invalid guest-state checks did not find any reason why. */
182	#define VMX_IGS_REASON_NOT_FOUND 501
183	/** CR0 fixed1 bits invalid. */
184	#define VMX_IGS_CR0_FIXED1 502
185	/** CR0 fixed0 bits invalid. */
186	#define VMX_IGS_CR0_FIXED0 503
187	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
188	#define VMX_IGS_CR0_PG_PE_COMBO 504
189	/** CR4 fixed1 bits invalid. */
190	#define VMX_IGS_CR4_FIXED1 505
191	/** CR4 fixed0 bits invalid. */
192	#define VMX_IGS_CR4_FIXED0 506
193	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
194	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
195	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
196	/** CR0.PG not set for long-mode when not using unrestricted guest. */
197	#define VMX_IGS_CR0_PG_LONGMODE 508
198	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
199	#define VMX_IGS_CR4_PAE_LONGMODE 509
200	/** CR4.PCIDE set for 32-bit guest. */
201	#define VMX_IGS_CR4_PCIDE 510
202	/** VMCS' DR7 reserved bits not set to 0. */
203	#define VMX_IGS_DR7_RESERVED 511
204	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
205	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
206	/** VMCS' EFER MSR reserved bits not set to 0. */
207	#define VMX_IGS_EFER_MSR_RESERVED 513
208	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
209	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
210	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
211	* without unrestricted guest. */
212	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
213	/** CS.Attr.P bit invalid. */
214	#define VMX_IGS_CS_ATTR_P_INVALID 516
215	/** CS.Attr reserved bits not set to 0. */
216	#define VMX_IGS_CS_ATTR_RESERVED 517
217	/** CS.Attr.G bit invalid. */
218	#define VMX_IGS_CS_ATTR_G_INVALID 518
219	/** CS is unusable. */
220	#define VMX_IGS_CS_ATTR_UNUSABLE 519
221	/** CS and SS DPL unequal. */
222	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
223	/** CS and SS DPL mismatch. */
224	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
225	/** CS Attr.Type invalid. */
226	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
227	/** CS and SS RPL unequal. */
228	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
229	/** SS.Attr.DPL and SS RPL unequal. */
230	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
231	/** SS.Attr.DPL invalid for segment type. */
232	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
233	/** SS.Attr.Type invalid. */
234	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
235	/** SS.Attr.P bit invalid. */
236	#define VMX_IGS_SS_ATTR_P_INVALID 527
237	/** SS.Attr reserved bits not set to 0. */
238	#define VMX_IGS_SS_ATTR_RESERVED 528
239	/** SS.Attr.G bit invalid. */
240	#define VMX_IGS_SS_ATTR_G_INVALID 529
241	/** DS.Attr.A bit invalid. */
242	#define VMX_IGS_DS_ATTR_A_INVALID 530
243	/** DS.Attr.P bit invalid. */
244	#define VMX_IGS_DS_ATTR_P_INVALID 531
245	/** DS.Attr.DPL and DS RPL unequal. */
246	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
247	/** DS.Attr reserved bits not set to 0. */
248	#define VMX_IGS_DS_ATTR_RESERVED 533
249	/** DS.Attr.G bit invalid. */
250	#define VMX_IGS_DS_ATTR_G_INVALID 534
251	/** DS.Attr.Type invalid. */
252	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
253	/** ES.Attr.A bit invalid. */
254	#define VMX_IGS_ES_ATTR_A_INVALID 536
255	/** ES.Attr.P bit invalid. */
256	#define VMX_IGS_ES_ATTR_P_INVALID 537
257	/** ES.Attr.DPL and DS RPL unequal. */
258	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
259	/** ES.Attr reserved bits not set to 0. */
260	#define VMX_IGS_ES_ATTR_RESERVED 539
261	/** ES.Attr.G bit invalid. */
262	#define VMX_IGS_ES_ATTR_G_INVALID 540
263	/** ES.Attr.Type invalid. */
264	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
265	/** FS.Attr.A bit invalid. */
266	#define VMX_IGS_FS_ATTR_A_INVALID 542
267	/** FS.Attr.P bit invalid. */
268	#define VMX_IGS_FS_ATTR_P_INVALID 543
269	/** FS.Attr.DPL and DS RPL unequal. */
270	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
271	/** FS.Attr reserved bits not set to 0. */
272	#define VMX_IGS_FS_ATTR_RESERVED 545
273	/** FS.Attr.G bit invalid. */
274	#define VMX_IGS_FS_ATTR_G_INVALID 546
275	/** FS.Attr.Type invalid. */
276	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
277	/** GS.Attr.A bit invalid. */
278	#define VMX_IGS_GS_ATTR_A_INVALID 548
279	/** GS.Attr.P bit invalid. */
280	#define VMX_IGS_GS_ATTR_P_INVALID 549
281	/** GS.Attr.DPL and DS RPL unequal. */
282	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
283	/** GS.Attr reserved bits not set to 0. */
284	#define VMX_IGS_GS_ATTR_RESERVED 551
285	/** GS.Attr.G bit invalid. */
286	#define VMX_IGS_GS_ATTR_G_INVALID 552
287	/** GS.Attr.Type invalid. */
288	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
289	/** V86 mode CS.Base invalid. */
290	#define VMX_IGS_V86_CS_BASE_INVALID 554
291	/** V86 mode CS.Limit invalid. */
292	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
293	/** V86 mode CS.Attr invalid. */
294	#define VMX_IGS_V86_CS_ATTR_INVALID 556
295	/** V86 mode SS.Base invalid. */
296	#define VMX_IGS_V86_SS_BASE_INVALID 557
297	/** V86 mode SS.Limit invalid. */
298	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
299	/** V86 mode SS.Attr invalid. */
300	#define VMX_IGS_V86_SS_ATTR_INVALID 559
301	/** V86 mode DS.Base invalid. */
302	#define VMX_IGS_V86_DS_BASE_INVALID 560
303	/** V86 mode DS.Limit invalid. */
304	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
305	/** V86 mode DS.Attr invalid. */
306	#define VMX_IGS_V86_DS_ATTR_INVALID 562
307	/** V86 mode ES.Base invalid. */
308	#define VMX_IGS_V86_ES_BASE_INVALID 563
309	/** V86 mode ES.Limit invalid. */
310	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
311	/** V86 mode ES.Attr invalid. */
312	#define VMX_IGS_V86_ES_ATTR_INVALID 565
313	/** V86 mode FS.Base invalid. */
314	#define VMX_IGS_V86_FS_BASE_INVALID 566
315	/** V86 mode FS.Limit invalid. */
316	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
317	/** V86 mode FS.Attr invalid. */
318	#define VMX_IGS_V86_FS_ATTR_INVALID 568
319	/** V86 mode GS.Base invalid. */
320	#define VMX_IGS_V86_GS_BASE_INVALID 569
321	/** V86 mode GS.Limit invalid. */
322	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
323	/** V86 mode GS.Attr invalid. */
324	#define VMX_IGS_V86_GS_ATTR_INVALID 571
325	/** Longmode CS.Base invalid. */
326	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
327	/** Longmode SS.Base invalid. */
328	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
329	/** Longmode DS.Base invalid. */
330	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
331	/** Longmode ES.Base invalid. */
332	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
333	/** SYSENTER ESP is not canonical. */
334	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
335	/** SYSENTER EIP is not canonical. */
336	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
337	/** PAT MSR invalid. */
338	#define VMX_IGS_PAT_MSR_INVALID 578
339	/** PAT MSR reserved bits not set to 0. */
340	#define VMX_IGS_PAT_MSR_RESERVED 579
341	/** GDTR.Base is not canonical. */
342	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
343	/** IDTR.Base is not canonical. */
344	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
345	/** GDTR.Limit invalid. */
346	#define VMX_IGS_GDTR_LIMIT_INVALID 582
347	/** IDTR.Limit invalid. */
348	#define VMX_IGS_IDTR_LIMIT_INVALID 583
349	/** Longmode RIP is invalid. */
350	#define VMX_IGS_LONGMODE_RIP_INVALID 584
351	/** RFLAGS reserved bits not set to 0. */
352	#define VMX_IGS_RFLAGS_RESERVED 585
353	/** RFLAGS RA1 reserved bits not set to 1. */
354	#define VMX_IGS_RFLAGS_RESERVED1 586
355	/** RFLAGS.VM (V86 mode) invalid. */
356	#define VMX_IGS_RFLAGS_VM_INVALID 587
357	/** RFLAGS.IF invalid. */
358	#define VMX_IGS_RFLAGS_IF_INVALID 588
359	/** Activity state invalid. */
360	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
361	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
362	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
363	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
364	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
365	/** Activity state SIPI WAIT invalid. */
366	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
367	/** Interruptibility state reserved bits not set to 0. */
368	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
369	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
370	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
371	/** Interruptibility state block-by-STI invalid for EFLAGS. */
372	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
373	/** Interruptibility state invalid while trying to deliver external
374	* interrupt. */
375	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
376	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
377	* NMI. */
378	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
379	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
380	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
381	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
382	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
383	/** Interruptibility state block-by-STI (maybe) invalid when trying to
384	* deliver an NMI. */
385	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
386	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
387	* active. */
388	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
389	/** Pending debug exceptions reserved bits not set to 0. */
390	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
391	/** Longmode pending debug exceptions reserved bits not set to 0. */
392	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
393	/** Pending debug exceptions.BS bit is not set when it should be. */
394	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
395	/** Pending debug exceptions.BS bit is not clear when it should be. */
396	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
397	/** VMCS link pointer reserved bits not set to 0. */
398	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
399	/** TR cannot index into LDT, TI bit MBZ. */
400	#define VMX_IGS_TR_TI_INVALID 607
401	/** LDTR cannot index into LDT. TI bit MBZ. */
402	#define VMX_IGS_LDTR_TI_INVALID 608
403	/** TR.Base is not canonical. */
404	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
405	/** FS.Base is not canonical. */
406	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
407	/** GS.Base is not canonical. */
408	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
409	/** LDTR.Base is not canonical. */
410	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
411	/** TR is unusable. */
412	#define VMX_IGS_TR_ATTR_UNUSABLE 613
413	/** TR.Attr.S bit invalid. */
414	#define VMX_IGS_TR_ATTR_S_INVALID 614
415	/** TR is not present. */
416	#define VMX_IGS_TR_ATTR_P_INVALID 615
417	/** TR.Attr reserved bits not set to 0. */
418	#define VMX_IGS_TR_ATTR_RESERVED 616
419	/** TR.Attr.G bit invalid. */
420	#define VMX_IGS_TR_ATTR_G_INVALID 617
421	/** Longmode TR.Attr.Type invalid. */
422	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
423	/** TR.Attr.Type invalid. */
424	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
425	/** CS.Attr.S invalid. */
426	#define VMX_IGS_CS_ATTR_S_INVALID 620
427	/** CS.Attr.DPL invalid. */
428	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
429	/** PAE PDPTE reserved bits not set to 0. */
430	#define VMX_IGS_PAE_PDPTE_RESERVED 623
431	/** VMCS link pointer does not point to a shadow VMCS. */
432	#define VMX_IGS_VMCS_LINK_PTR_NOT_SHADOW 624
433	/** VMCS link pointer to a shadow VMCS with invalid VMCS revision identifer. */
434	#define VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID 625
435	/** @} */
436
437	/** @name VMX VMCS-Read cache indices.
438	* @{
439	*/
440	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
441	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
442	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
443	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
444	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
445	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
446	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
447	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
448	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
449	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
450	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
451	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
452	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
453	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
454	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
455	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
456	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
457	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
458	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
459	/** @} */
460
461	/** @name VMX EPT paging structures
462	* @{
463	*/
464
465	/**
466	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
467	*/
468	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
469
470	/**
471	* EPT Page Directory Pointer Entry. Bit view.
472	* In accordance with the VT-x spec.
473	*
474	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
475	* this did cause trouble with one compiler/version).
476	*/
477	typedef struct EPTPML4EBITS
478	{
479	/** Present bit. */
480	RT_GCC_EXTENSION uint64_t u1Present : 1;
481	/** Writable bit. */
482	RT_GCC_EXTENSION uint64_t u1Write : 1;
483	/** Executable bit. */
484	RT_GCC_EXTENSION uint64_t u1Execute : 1;
485	/** Reserved (must be 0). */
486	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
487	/** Available for software. */
488	RT_GCC_EXTENSION uint64_t u4Available : 4;
489	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
490	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
491	/** Available for software. */
492	RT_GCC_EXTENSION uint64_t u12Available : 12;
493	} EPTPML4EBITS;
494	AssertCompileSize(EPTPML4EBITS, 8);
495
496	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
497	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
498	/** The page shift to get the PML4 index. */
499	#define EPT_PML4_SHIFT X86_PML4_SHIFT
500	/** The PML4 index mask (apply to a shifted page address). */
501	#define EPT_PML4_MASK X86_PML4_MASK
502
503	/**
504	* EPT PML4E.
505	* In accordance with the VT-x spec.
506	*/
507	typedef union EPTPML4E
508	{
509	/** Normal view. */
510	EPTPML4EBITS n;
511	/** Unsigned integer view. */
512	X86PGPAEUINT u;
513	/** 64 bit unsigned integer view. */
514	uint64_t au64[1];
515	/** 32 bit unsigned integer view. */
516	uint32_t au32[2];
517	} EPTPML4E;
518	AssertCompileSize(EPTPML4E, 8);
519	/** Pointer to a PML4 table entry. */
520	typedef EPTPML4E *PEPTPML4E;
521	/** Pointer to a const PML4 table entry. */
522	typedef const EPTPML4E *PCEPTPML4E;
523
524	/**
525	* EPT PML4 Table.
526	* In accordance with the VT-x spec.
527	*/
528	typedef struct EPTPML4
529	{
530	EPTPML4E a[EPT_PG_ENTRIES];
531	} EPTPML4;
532	AssertCompileSize(EPTPML4, 0x1000);
533	/** Pointer to an EPT PML4 Table. */
534	typedef EPTPML4 *PEPTPML4;
535	/** Pointer to a const EPT PML4 Table. */
536	typedef const EPTPML4 *PCEPTPML4;
537
538	/**
539	* EPT Page Directory Pointer Entry. Bit view.
540	* In accordance with the VT-x spec.
541	*/
542	typedef struct EPTPDPTEBITS
543	{
544	/** Present bit. */
545	RT_GCC_EXTENSION uint64_t u1Present : 1;
546	/** Writable bit. */
547	RT_GCC_EXTENSION uint64_t u1Write : 1;
548	/** Executable bit. */
549	RT_GCC_EXTENSION uint64_t u1Execute : 1;
550	/** Reserved (must be 0). */
551	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
552	/** Available for software. */
553	RT_GCC_EXTENSION uint64_t u4Available : 4;
554	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
555	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
556	/** Available for software. */
557	RT_GCC_EXTENSION uint64_t u12Available : 12;
558	} EPTPDPTEBITS;
559	AssertCompileSize(EPTPDPTEBITS, 8);
560
561	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
562	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
563	/** The page shift to get the PDPT index. */
564	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
565	/** The PDPT index mask (apply to a shifted page address). */
566	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
567
568	/**
569	* EPT Page Directory Pointer.
570	* In accordance with the VT-x spec.
571	*/
572	typedef union EPTPDPTE
573	{
574	/** Normal view. */
575	EPTPDPTEBITS n;
576	/** Unsigned integer view. */
577	X86PGPAEUINT u;
578	/** 64 bit unsigned integer view. */
579	uint64_t au64[1];
580	/** 32 bit unsigned integer view. */
581	uint32_t au32[2];
582	} EPTPDPTE;
583	AssertCompileSize(EPTPDPTE, 8);
584	/** Pointer to an EPT Page Directory Pointer Entry. */
585	typedef EPTPDPTE *PEPTPDPTE;
586	/** Pointer to a const EPT Page Directory Pointer Entry. */
587	typedef const EPTPDPTE *PCEPTPDPTE;
588
589	/**
590	* EPT Page Directory Pointer Table.
591	* In accordance with the VT-x spec.
592	*/
593	typedef struct EPTPDPT
594	{
595	EPTPDPTE a[EPT_PG_ENTRIES];
596	} EPTPDPT;
597	AssertCompileSize(EPTPDPT, 0x1000);
598	/** Pointer to an EPT Page Directory Pointer Table. */
599	typedef EPTPDPT *PEPTPDPT;
600	/** Pointer to a const EPT Page Directory Pointer Table. */
601	typedef const EPTPDPT *PCEPTPDPT;
602
603	/**
604	* EPT Page Directory Table Entry. Bit view.
605	* In accordance with the VT-x spec.
606	*/
607	typedef struct EPTPDEBITS
608	{
609	/** Present bit. */
610	RT_GCC_EXTENSION uint64_t u1Present : 1;
611	/** Writable bit. */
612	RT_GCC_EXTENSION uint64_t u1Write : 1;
613	/** Executable bit. */
614	RT_GCC_EXTENSION uint64_t u1Execute : 1;
615	/** Reserved (must be 0). */
616	RT_GCC_EXTENSION uint64_t u4Reserved : 4;
617	/** Big page (must be 0 here). */
618	RT_GCC_EXTENSION uint64_t u1Size : 1;
619	/** Available for software. */
620	RT_GCC_EXTENSION uint64_t u4Available : 4;
621	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
622	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
623	/** Available for software. */
624	RT_GCC_EXTENSION uint64_t u12Available : 12;
625	} EPTPDEBITS;
626	AssertCompileSize(EPTPDEBITS, 8);
627
628	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
629	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
630	/** The page shift to get the PD index. */
631	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
632	/** The PD index mask (apply to a shifted page address). */
633	#define EPT_PD_MASK X86_PD_PAE_MASK
634
635	/**
636	* EPT 2MB Page Directory Table Entry. Bit view.
637	* In accordance with the VT-x spec.
638	*/
639	typedef struct EPTPDE2MBITS
640	{
641	/** Present bit. */
642	RT_GCC_EXTENSION uint64_t u1Present : 1;
643	/** Writable bit. */
644	RT_GCC_EXTENSION uint64_t u1Write : 1;
645	/** Executable bit. */
646	RT_GCC_EXTENSION uint64_t u1Execute : 1;
647	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
648	RT_GCC_EXTENSION uint64_t u3EMT : 3;
649	/** Ignore PAT memory type */
650	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
651	/** Big page (must be 1 here). */
652	RT_GCC_EXTENSION uint64_t u1Size : 1;
653	/** Available for software. */
654	RT_GCC_EXTENSION uint64_t u4Available : 4;
655	/** Reserved (must be 0). */
656	RT_GCC_EXTENSION uint64_t u9Reserved : 9;
657	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
658	RT_GCC_EXTENSION uint64_t u31PhysAddr : 31;
659	/** Available for software. */
660	RT_GCC_EXTENSION uint64_t u12Available : 12;
661	} EPTPDE2MBITS;
662	AssertCompileSize(EPTPDE2MBITS, 8);
663
664	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
665	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
666
667	/**
668	* EPT Page Directory Table Entry.
669	* In accordance with the VT-x spec.
670	*/
671	typedef union EPTPDE
672	{
673	/** Normal view. */
674	EPTPDEBITS n;
675	/** 2MB view (big). */
676	EPTPDE2MBITS b;
677	/** Unsigned integer view. */
678	X86PGPAEUINT u;
679	/** 64 bit unsigned integer view. */
680	uint64_t au64[1];
681	/** 32 bit unsigned integer view. */
682	uint32_t au32[2];
683	} EPTPDE;
684	AssertCompileSize(EPTPDE, 8);
685	/** Pointer to an EPT Page Directory Table Entry. */
686	typedef EPTPDE *PEPTPDE;
687	/** Pointer to a const EPT Page Directory Table Entry. */
688	typedef const EPTPDE *PCEPTPDE;
689
690	/**
691	* EPT Page Directory Table.
692	* In accordance with the VT-x spec.
693	*/
694	typedef struct EPTPD
695	{
696	EPTPDE a[EPT_PG_ENTRIES];
697	} EPTPD;
698	AssertCompileSize(EPTPD, 0x1000);
699	/** Pointer to an EPT Page Directory Table. */
700	typedef EPTPD *PEPTPD;
701	/** Pointer to a const EPT Page Directory Table. */
702	typedef const EPTPD *PCEPTPD;
703
704	/**
705	* EPT Page Table Entry. Bit view.
706	* In accordance with the VT-x spec.
707	*/
708	typedef struct EPTPTEBITS
709	{
710	/** 0 - Present bit.
711	* @remarks This is a convenience "misnomer". The bit actually indicates read access
712	* and the CPU will consider an entry with any of the first three bits set
713	* as present. Since all our valid entries will have this bit set, it can
714	* be used as a present indicator and allow some code sharing. */
715	RT_GCC_EXTENSION uint64_t u1Present : 1;
716	/** 1 - Writable bit. */
717	RT_GCC_EXTENSION uint64_t u1Write : 1;
718	/** 2 - Executable bit. */
719	RT_GCC_EXTENSION uint64_t u1Execute : 1;
720	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
721	RT_GCC_EXTENSION uint64_t u3EMT : 3;
722	/** 6 - Ignore PAT memory type */
723	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
724	/** 11:7 - Available for software. */
725	RT_GCC_EXTENSION uint64_t u5Available : 5;
726	/** 51:12 - Physical address of page. Restricted by maximum physical
727	* address width of the cpu. */
728	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
729	/** 63:52 - Available for software. */
730	RT_GCC_EXTENSION uint64_t u12Available : 12;
731	} EPTPTEBITS;
732	AssertCompileSize(EPTPTEBITS, 8);
733
734	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
735	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
736	/** The page shift to get the EPT PTE index. */
737	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
738	/** The EPT PT index mask (apply to a shifted page address). */
739	#define EPT_PT_MASK X86_PT_PAE_MASK
740
741	/**
742	* EPT Page Table Entry.
743	* In accordance with the VT-x spec.
744	*/
745	typedef union EPTPTE
746	{
747	/** Normal view. */
748	EPTPTEBITS n;
749	/** Unsigned integer view. */
750	X86PGPAEUINT u;
751	/** 64 bit unsigned integer view. */
752	uint64_t au64[1];
753	/** 32 bit unsigned integer view. */
754	uint32_t au32[2];
755	} EPTPTE;
756	AssertCompileSize(EPTPTE, 8);
757	/** Pointer to an EPT Page Directory Table Entry. */
758	typedef EPTPTE *PEPTPTE;
759	/** Pointer to a const EPT Page Directory Table Entry. */
760	typedef const EPTPTE *PCEPTPTE;
761
762	/**
763	* EPT Page Table.
764	* In accordance with the VT-x spec.
765	*/
766	typedef struct EPTPT
767	{
768	EPTPTE a[EPT_PG_ENTRIES];
769	} EPTPT;
770	AssertCompileSize(EPTPT, 0x1000);
771	/** Pointer to an extended page table. */
772	typedef EPTPT *PEPTPT;
773	/** Pointer to a const extended table. */
774	typedef const EPTPT *PCEPTPT;
775
776	/** @} */
777
778	/**
779	* VMX VPID flush types.
780	* Valid enum members are in accordance with the VT-x spec.
781	*/
782	typedef enum
783	{
784	/** Invalidate a specific page. */
785	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
786	/** Invalidate one context (specific VPID). */
787	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
788	/** Invalidate all contexts (all VPIDs). */
789	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
790	/** Invalidate a single VPID context retaining global mappings. */
791	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
792	/** Unsupported by VirtualBox. */
793	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
794	/** Unsupported by CPU. */
795	VMXTLBFLUSHVPID_NONE = 0xbad1
796	} VMXTLBFLUSHVPID;
797	AssertCompileSize(VMXTLBFLUSHVPID, 4);
798
799	/**
800	* VMX EPT flush types.
801	* @note Valid enums values are in accordance with the VT-x spec.
802	*/
803	typedef enum
804	{
805	/** Invalidate one context (specific EPT). */
806	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
807	/* Invalidate all contexts (all EPTs) */
808	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
809	/** Unsupported by VirtualBox. */
810	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
811	/** Unsupported by CPU. */
812	VMXTLBFLUSHEPT_NONE = 0xbad1
813	} VMXTLBFLUSHEPT;
814	AssertCompileSize(VMXTLBFLUSHEPT, 4);
815
816	/**
817	* VMX Posted Interrupt Descriptor.
818	* In accordance with the VT-x spec.
819	*/
820	typedef struct VMXPOSTEDINTRDESC
821	{
822	uint32_t aVectorBitmap[8];
823	uint32_t fOutstandingNotification : 1;
824	uint32_t uReserved0 : 31;
825	uint8_t au8Reserved0[28];
826	} VMXPOSTEDINTRDESC;
827	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
828	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
829	/** Pointer to a posted interrupt descriptor. */
830	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
831	/** Pointer to a const posted interrupt descriptor. */
832	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
833
834	/**
835	* VMX VMCS revision identifier.
836	* In accordance with the VT-x spec.
837	*/
838	typedef union
839	{
840	struct
841	{
842	/** Revision identifier. */
843	uint32_t u31RevisionId : 31;
844	/** Whether this is a shadow VMCS. */
845	uint32_t fIsShadowVmcs : 1;
846	} n;
847	/* The unsigned integer view. */
848	uint32_t u;
849	} VMXVMCSREVID;
850	AssertCompileSize(VMXVMCSREVID, 4);
851	/** Pointer to the VMXVMCSREVID union. */
852	typedef VMXVMCSREVID *PVMXVMCSREVID;
853	/** Pointer to a const VMXVMCSREVID union. */
854	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
855
856	/**
857	* VMX VM-exit instruction information.
858	* In accordance with the VT-x spec.
859	*/
860	typedef union
861	{
862	/** Plain unsigned int representation. */
863	uint32_t u;
864
865	/** INS and OUTS information. */
866	struct
867	{
868	uint32_t u7Reserved0 : 7;
869	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
870	uint32_t u3AddrSize : 3;
871	uint32_t u5Reserved1 : 5;
872	/** The segment register (X86_SREG_XXX). */
873	uint32_t iSegReg : 3;
874	uint32_t uReserved2 : 14;
875	} StrIo;
876
877	/** INVEPT, INVPCID, INVVPID information. */
878	struct
879	{
880	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
881	uint32_t u2Scaling : 2;
882	uint32_t u5Undef0 : 5;
883	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
884	uint32_t u3AddrSize : 3;
885	/** Cleared to 0. */
886	uint32_t u1Cleared0 : 1;
887	uint32_t u4Undef0 : 4;
888	/** The segment register (X86_SREG_XXX). */
889	uint32_t iSegReg : 3;
890	/** The index register (X86_GREG_XXX). */
891	uint32_t iIdxReg : 4;
892	/** Set if index register is invalid. */
893	uint32_t fIdxRegInvalid : 1;
894	/** The base register (X86_GREG_XXX). */
895	uint32_t iBaseReg : 4;
896	/** Set if base register is invalid. */
897	uint32_t fBaseRegInvalid : 1;
898	/** Register 2 (X86_GREG_XXX). */
899	uint32_t iReg2 : 4;
900	} Inv;
901
902	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
903	struct
904	{
905	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
906	uint32_t u2Scaling : 2;
907	uint32_t u5Reserved0 : 5;
908	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
909	uint32_t u3AddrSize : 3;
910	/** Cleared to 0. */
911	uint32_t u1Cleared0 : 1;
912	uint32_t u4Reserved0 : 4;
913	/** The segment register (X86_SREG_XXX). */
914	uint32_t iSegReg : 3;
915	/** The index register (X86_GREG_XXX). */
916	uint32_t iIdxReg : 4;
917	/** Set if index register is invalid. */
918	uint32_t fIdxRegInvalid : 1;
919	/** The base register (X86_GREG_XXX). */
920	uint32_t iBaseReg : 4;
921	/** Set if base register is invalid. */
922	uint32_t fBaseRegInvalid : 1;
923	/** Register 2 (X86_GREG_XXX). */
924	uint32_t iReg2 : 4;
925	} VmxXsave;
926
927	/** LIDT, LGDT, SIDT, SGDT information. */
928	struct
929	{
930	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
931	uint32_t u2Scaling : 2;
932	uint32_t u5Undef0 : 5;
933	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
934	uint32_t u3AddrSize : 3;
935	/** Always cleared to 0. */
936	uint32_t u1Cleared0 : 1;
937	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
938	uint32_t uOperandSize : 1;
939	uint32_t u3Undef0 : 3;
940	/** The segment register (X86_SREG_XXX). */
941	uint32_t iSegReg : 3;
942	/** The index register (X86_GREG_XXX). */
943	uint32_t iIdxReg : 4;
944	/** Set if index register is invalid. */
945	uint32_t fIdxRegInvalid : 1;
946	/** The base register (X86_GREG_XXX). */
947	uint32_t iBaseReg : 4;
948	/** Set if base register is invalid. */
949	uint32_t fBaseRegInvalid : 1;
950	/** Instruction identity (VMX_INSTR_ID_XXX). */
951	uint32_t u2InstrId : 2;
952	uint32_t u2Undef0 : 2;
953	} GdtIdt;
954
955	/** LLDT, LTR, SLDT, STR information. */
956	struct
957	{
958	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
959	uint32_t u2Scaling : 2;
960	uint32_t u1Undef0 : 1;
961	/** Register 1 (X86_GREG_XXX). */
962	uint32_t iReg1 : 4;
963	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
964	uint32_t u3AddrSize : 3;
965	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
966	uint32_t fIsRegOperand : 1;
967	uint32_t u4Undef0 : 4;
968	/** The segment register (X86_SREG_XXX). */
969	uint32_t iSegReg : 3;
970	/** The index register (X86_GREG_XXX). */
971	uint32_t iIdxReg : 4;
972	/** Set if index register is invalid. */
973	uint32_t fIdxRegInvalid : 1;
974	/** The base register (X86_GREG_XXX). */
975	uint32_t iBaseReg : 4;
976	/** Set if base register is invalid. */
977	uint32_t fBaseRegInvalid : 1;
978	/** Instruction identity (VMX_INSTR_ID_XXX). */
979	uint32_t u2InstrId : 2;
980	uint32_t u2Undef0 : 2;
981	} LdtTr;
982
983	/** RDRAND, RDSEED information. */
984	struct
985	{
986	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
987	uint32_t u2Undef0 : 2;
988	/** Destination register (X86_GREG_XXX). */
989	uint32_t iReg1 : 4;
990	uint32_t u4Undef0 : 4;
991	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
992	uint32_t u2OperandSize : 2;
993	uint32_t u19Def0 : 20;
994	} RdrandRdseed;
995
996	/** VMREAD, VMWRITE information. */
997	struct
998	{
999	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1000	uint32_t u2Scaling : 2;
1001	uint32_t u1Undef0 : 1;
1002	/** Register 1 (X86_GREG_XXX). */
1003	uint32_t iReg1 : 4;
1004	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1005	uint32_t u3AddrSize : 3;
1006	/** Memory or register operand. */
1007	uint32_t fIsRegOperand : 1;
1008	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1009	uint32_t u4Undef0 : 4;
1010	/** The segment register (X86_SREG_XXX). */
1011	uint32_t iSegReg : 3;
1012	/** The index register (X86_GREG_XXX). */
1013	uint32_t iIdxReg : 4;
1014	/** Set if index register is invalid. */
1015	uint32_t fIdxRegInvalid : 1;
1016	/** The base register (X86_GREG_XXX). */
1017	uint32_t iBaseReg : 4;
1018	/** Set if base register is invalid. */
1019	uint32_t fBaseRegInvalid : 1;
1020	/** Register 2 (X86_GREG_XXX). */
1021	uint32_t iReg2 : 4;
1022	} VmreadVmwrite;
1023
1024	/** This is a combination field of all instruction information. Note! Not all field
1025	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1026	* specialized fields are overwritten by their generic counterparts (e.g. no
1027	* instruction identity field). */
1028	struct
1029	{
1030	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1031	uint32_t u2Scaling : 2;
1032	uint32_t u1Undef0 : 1;
1033	/** Register 1 (X86_GREG_XXX). */
1034	uint32_t iReg1 : 4;
1035	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1036	uint32_t u3AddrSize : 3;
1037	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1038	uint32_t fIsRegOperand : 1;
1039	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1040	uint32_t uOperandSize : 2;
1041	uint32_t u2Undef0 : 2;
1042	/** The segment register (X86_SREG_XXX). */
1043	uint32_t iSegReg : 3;
1044	/** The index register (X86_GREG_XXX). */
1045	uint32_t iIdxReg : 4;
1046	/** Set if index register is invalid. */
1047	uint32_t fIdxRegInvalid : 1;
1048	/** The base register (X86_GREG_XXX). */
1049	uint32_t iBaseReg : 4;
1050	/** Set if base register is invalid. */
1051	uint32_t fBaseRegInvalid : 1;
1052	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1053	uint32_t iReg2 : 4;
1054	} All;
1055	} VMXEXITINSTRINFO;
1056	AssertCompileSize(VMXEXITINSTRINFO, 4);
1057	/** Pointer to a VMX VM-exit instruction info. struct. */
1058	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1059	/** Pointer to a const VMX VM-exit instruction info. struct. */
1060	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1061
1062
1063	/** @name VM-entry failure reported in Exit qualification.
1064	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1065	* @{
1066	*/
1067	/** No errors during VM-entry. */
1068	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1069	/** Not used. */
1070	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1071	/** Error while loading PDPTEs. */
1072	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1073	/** NMI injection when blocking-by-STI is set. */
1074	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1075	/** Invalid VMCS link pointer. */
1076	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1077	/** @} */
1078
1079
1080	/** @name VMXMSRPM_XXX - VMX MSR-bitmap permissions.
1081	* These are -not- specified by Intel but used internally by VirtualBox.
1082	* @{ */
1083	/** Guest software reads of this MSR must not cause a VM-exit. */
1084	#define VMXMSRPM_ALLOW_RD RT_BIT(0)
1085	/** Guest software reads of this MSR must cause a VM-exit. */
1086	#define VMXMSRPM_EXIT_RD RT_BIT(1)
1087	/** Guest software writes to this MSR must not cause a VM-exit. */
1088	#define VMXMSRPM_ALLOW_WR RT_BIT(2)
1089	/** Guest software writes to this MSR must cause a VM-exit. */
1090	#define VMXMSRPM_EXIT_WR RT_BIT(3)
1091	/** Guest software reads or writes of this MSR must not cause a VM-exit. */
1092	#define VMXMSRPM_ALLOW_RD_WR (VMXMSRPM_ALLOW_RD \| VMXMSRPM_ALLOW_WR)
1093	/** Guest software reads or writes of this MSR must cause a VM-exit. */
1094	#define VMXMSRPM_EXIT_RD_WR (VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR)
1095	/** Mask of valid MSR read permissions. */
1096	#define VMXMSRPM_RD_MASK (VMXMSRPM_ALLOW_RD \| VMXMSRPM_EXIT_RD)
1097	/** Mask of valid MSR write permissions. */
1098	#define VMXMSRPM_WR_MASK (VMXMSRPM_ALLOW_WR \| VMXMSRPM_EXIT_WR)
1099	/** Mask of valid MSR permissions. */
1100	#define VMXMSRPM_MASK (VMXMSRPM_RD_MASK \| VMXMSRPM_WR_MASK)
1101	/** */
1102	/** Gets whether the MSR permission is valid or not. */
1103	#define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \
1104	&& ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \
1105	&& ((a_Msrpm) & VMXMSRPM_RD_MASK) != VMXMSRPM_RD_MASK \
1106	&& ((a_Msrpm) & VMXMSRPM_WR_MASK) != VMXMSRPM_WR_MASK)
1107	/** @} */
1108
1109	/**
1110	* VMX MSR autoload/store slot.
1111	* In accordance with the VT-x spec.
1112	*/
1113	typedef struct VMXAUTOMSR
1114	{
1115	/** The MSR Id. */
1116	uint32_t u32Msr;
1117	/** Reserved (MBZ). */
1118	uint32_t u32Reserved;
1119	/** The MSR value. */
1120	uint64_t u64Value;
1121	} VMXAUTOMSR;
1122	AssertCompileSize(VMXAUTOMSR, 16);
1123	/** Pointer to an MSR load/store element. */
1124	typedef VMXAUTOMSR *PVMXAUTOMSR;
1125	/** Pointer to a const MSR load/store element. */
1126	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1127
1128	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1129	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1130
1131	/**
1132	* VMX tagged-TLB flush types.
1133	*/
1134	typedef enum
1135	{
1136	VMXTLBFLUSHTYPE_EPT,
1137	VMXTLBFLUSHTYPE_VPID,
1138	VMXTLBFLUSHTYPE_EPT_VPID,
1139	VMXTLBFLUSHTYPE_NONE
1140	} VMXTLBFLUSHTYPE;
1141	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1142	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1143	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1144	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1145
1146	/**
1147	* VMX controls MSR.
1148	* In accordance with the VT-x spec.
1149	*/
1150	typedef union
1151	{
1152	struct
1153	{
1154	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1155	uint32_t allowed0;
1156	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1157	* controls. */
1158	uint32_t allowed1;
1159	} n;
1160	uint64_t u;
1161	} VMXCTLSMSR;
1162	AssertCompileSize(VMXCTLSMSR, 8);
1163	/** Pointer to a VMXCTLSMSR union. */
1164	typedef VMXCTLSMSR *PVMXCTLSMSR;
1165	/** Pointer to a const VMXCTLSMSR union. */
1166	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1167
1168	/**
1169	* VMX MSRs.
1170	*/
1171	typedef struct VMXMSRS
1172	{
1173	/** VMX/SMX Feature control. */
1174	uint64_t u64FeatCtrl;
1175	/** Basic information. */
1176	uint64_t u64Basic;
1177	/** Pin-based VM-execution controls. */
1178	VMXCTLSMSR PinCtls;
1179	/** Processor-based VM-execution controls. */
1180	VMXCTLSMSR ProcCtls;
1181	/** Secondary processor-based VM-execution controls. */
1182	VMXCTLSMSR ProcCtls2;
1183	/** VM-exit controls. */
1184	VMXCTLSMSR ExitCtls;
1185	/** VM-entry controls. */
1186	VMXCTLSMSR EntryCtls;
1187	/** True pin-based VM-execution controls. */
1188	VMXCTLSMSR TruePinCtls;
1189	/** True processor-based VM-execution controls. */
1190	VMXCTLSMSR TrueProcCtls;
1191	/** True VM-entry controls. */
1192	VMXCTLSMSR TrueEntryCtls;
1193	/** True VM-exit controls. */
1194	VMXCTLSMSR TrueExitCtls;
1195	/** Miscellaneous data. */
1196	uint64_t u64Misc;
1197	/** CR0 fixed-0 - bits set here must be set in VMX operation. */
1198	uint64_t u64Cr0Fixed0;
1199	/** CR0 fixed-1 - bits clear here must be clear in VMX operation. */
1200	uint64_t u64Cr0Fixed1;
1201	/** CR4 fixed-0 - bits set here must be set in VMX operation. */
1202	uint64_t u64Cr4Fixed0;
1203	/** CR4 fixed-1 - bits clear here must be clear in VMX operation. */
1204	uint64_t u64Cr4Fixed1;
1205	/** VMCS enumeration. */
1206	uint64_t u64VmcsEnum;
1207	/** VM Functions. */
1208	uint64_t u64VmFunc;
1209	/** EPT, VPID capabilities. */
1210	uint64_t u64EptVpidCaps;
1211	/** Reserved for future. */
1212	uint64_t a_u64Reserved[9];
1213	} VMXMSRS;
1214	AssertCompileSizeAlignment(VMXMSRS, 8);
1215	AssertCompileSize(VMXMSRS, 224);
1216	/** Pointer to a VMXMSRS struct. */
1217	typedef VMXMSRS *PVMXMSRS;
1218	/** Pointer to a const VMXMSRS struct. */
1219	typedef const VMXMSRS *PCVMXMSRS;
1220
1221
1222	/** @name VMX Basic Exit Reasons.
1223	* @{
1224	*/
1225	/** -1 Invalid exit code */
1226	#define VMX_EXIT_INVALID (-1)
1227	/** 0 Exception or non-maskable interrupt (NMI). */
1228	#define VMX_EXIT_XCPT_OR_NMI 0
1229	/** 1 External interrupt. */
1230	#define VMX_EXIT_EXT_INT 1
1231	/** 2 Triple fault. */
1232	#define VMX_EXIT_TRIPLE_FAULT 2
1233	/** 3 INIT signal. */
1234	#define VMX_EXIT_INIT_SIGNAL 3
1235	/** 4 Start-up IPI (SIPI). */
1236	#define VMX_EXIT_SIPI 4
1237	/** 5 I/O system-management interrupt (SMI). */
1238	#define VMX_EXIT_IO_SMI 5
1239	/** 6 Other SMI. */
1240	#define VMX_EXIT_SMI 6
1241	/** 7 Interrupt window exiting. */
1242	#define VMX_EXIT_INT_WINDOW 7
1243	/** 8 NMI window exiting. */
1244	#define VMX_EXIT_NMI_WINDOW 8
1245	/** 9 Task switch. */
1246	#define VMX_EXIT_TASK_SWITCH 9
1247	/** 10 Guest software attempted to execute CPUID. */
1248	#define VMX_EXIT_CPUID 10
1249	/** 11 Guest software attempted to execute GETSEC. */
1250	#define VMX_EXIT_GETSEC 11
1251	/** 12 Guest software attempted to execute HLT. */
1252	#define VMX_EXIT_HLT 12
1253	/** 13 Guest software attempted to execute INVD. */
1254	#define VMX_EXIT_INVD 13
1255	/** 14 Guest software attempted to execute INVLPG. */
1256	#define VMX_EXIT_INVLPG 14
1257	/** 15 Guest software attempted to execute RDPMC. */
1258	#define VMX_EXIT_RDPMC 15
1259	/** 16 Guest software attempted to execute RDTSC. */
1260	#define VMX_EXIT_RDTSC 16
1261	/** 17 Guest software attempted to execute RSM in SMM. */
1262	#define VMX_EXIT_RSM 17
1263	/** 18 Guest software executed VMCALL. */
1264	#define VMX_EXIT_VMCALL 18
1265	/** 19 Guest software executed VMCLEAR. */
1266	#define VMX_EXIT_VMCLEAR 19
1267	/** 20 Guest software executed VMLAUNCH. */
1268	#define VMX_EXIT_VMLAUNCH 20
1269	/** 21 Guest software executed VMPTRLD. */
1270	#define VMX_EXIT_VMPTRLD 21
1271	/** 22 Guest software executed VMPTRST. */
1272	#define VMX_EXIT_VMPTRST 22
1273	/** 23 Guest software executed VMREAD. */
1274	#define VMX_EXIT_VMREAD 23
1275	/** 24 Guest software executed VMRESUME. */
1276	#define VMX_EXIT_VMRESUME 24
1277	/** 25 Guest software executed VMWRITE. */
1278	#define VMX_EXIT_VMWRITE 25
1279	/** 26 Guest software executed VMXOFF. */
1280	#define VMX_EXIT_VMXOFF 26
1281	/** 27 Guest software executed VMXON. */
1282	#define VMX_EXIT_VMXON 27
1283	/** 28 Control-register accesses. */
1284	#define VMX_EXIT_MOV_CRX 28
1285	/** 29 Debug-register accesses. */
1286	#define VMX_EXIT_MOV_DRX 29
1287	/** 30 I/O instruction. */
1288	#define VMX_EXIT_IO_INSTR 30
1289	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1290	#define VMX_EXIT_RDMSR 31
1291	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1292	#define VMX_EXIT_WRMSR 32
1293	/** 33 VM-entry failure due to invalid guest state. */
1294	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1295	/** 34 VM-entry failure due to MSR loading. */
1296	#define VMX_EXIT_ERR_MSR_LOAD 34
1297	/** 36 Guest software executed MWAIT. */
1298	#define VMX_EXIT_MWAIT 36
1299	/** 37 VM-exit due to monitor trap flag. */
1300	#define VMX_EXIT_MTF 37
1301	/** 39 Guest software attempted to execute MONITOR. */
1302	#define VMX_EXIT_MONITOR 39
1303	/** 40 Guest software attempted to execute PAUSE. */
1304	#define VMX_EXIT_PAUSE 40
1305	/** 41 VM-entry failure due to machine-check. */
1306	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1307	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1308	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1309	/** 44 APIC access. Guest software attempted to access memory at a physical
1310	* address on the APIC-access page. */
1311	#define VMX_EXIT_APIC_ACCESS 44
1312	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1313	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1314	#define VMX_EXIT_VIRTUALIZED_EOI 45
1315	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1316	* SGDT, or SIDT. */
1317	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1318	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1319	* SLDT, or STR. */
1320	#define VMX_EXIT_LDTR_TR_ACCESS 47
1321	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1322	* was disallowed by the configuration of the EPT paging structures. */
1323	#define VMX_EXIT_EPT_VIOLATION 48
1324	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1325	* address encountered a misconfigured EPT paging-structure entry. */
1326	#define VMX_EXIT_EPT_MISCONFIG 49
1327	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1328	#define VMX_EXIT_INVEPT 50
1329	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1330	#define VMX_EXIT_RDTSCP 51
1331	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1332	#define VMX_EXIT_PREEMPT_TIMER 52
1333	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1334	#define VMX_EXIT_INVVPID 53
1335	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1336	#define VMX_EXIT_WBINVD 54
1337	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1338	#define VMX_EXIT_XSETBV 55
1339	/** 56 APIC write. Guest completed write to virtual-APIC. */
1340	#define VMX_EXIT_APIC_WRITE 56
1341	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1342	#define VMX_EXIT_RDRAND 57
1343	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1344	#define VMX_EXIT_INVPCID 58
1345	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1346	#define VMX_EXIT_VMFUNC 59
1347	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1348	#define VMX_EXIT_ENCLS 60
1349	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1350	* enabled. */
1351	#define VMX_EXIT_RDSEED 61
1352	/** 62 - Page-modification log full. */
1353	#define VMX_EXIT_PML_FULL 62
1354	/** 63 - XSAVES. Guest software attempted to execute XSAVES and exiting was
1355	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1356	#define VMX_EXIT_XSAVES 63
1357	/** 64 - XRSTORS. Guest software attempted to execute XRSTORS and exiting
1358	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1359	#define VMX_EXIT_XRSTORS 64
1360	/** 66 - SPP-related event. Attempt to determine an access' sub-page write
1361	* permission encountered an SPP miss or misconfiguration. */
1362	#define VMX_EXIT_SPP_EVENT 66
1363	/* 67 - UMWAIT. Guest software attempted to execute UMWAIT and exiting was enabled. */
1364	#define VMX_EXIT_UMWAIT 67
1365	/** 68 - TPAUSE. Guest software attempted to execute TPAUSE and exiting was
1366	* enabled. */
1367	#define VMX_EXIT_TPAUSE 68
1368	/** The maximum exit value (inclusive). */
1369	#define VMX_EXIT_MAX (VMX_EXIT_TPAUSE)
1370	/** @} */
1371
1372
1373	/** @name VM Instruction Errors.
1374	* In accordance with the VT-x spec.
1375	* See Intel spec. "30.4 VM Instruction Error Numbers"
1376	* @{
1377	*/
1378	typedef enum
1379	{
1380	/** VMCALL executed in VMX root operation. */
1381	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1382	/** VMCLEAR with invalid physical address. */
1383	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1384	/** VMCLEAR with VMXON pointer. */
1385	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1386	/** VMLAUNCH with non-clear VMCS. */
1387	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1388	/** VMRESUME with non-launched VMCS. */
1389	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1390	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1391	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1392	/** VM-entry with invalid control field(s). */
1393	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1394	/** VM-entry with invalid host-state field(s). */
1395	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1396	/** VMPTRLD with invalid physical address. */
1397	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1398	/** VMPTRLD with VMXON pointer. */
1399	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1400	/** VMPTRLD with incorrect VMCS revision identifier. */
1401	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1402	/** VMREAD from unsupported VMCS component. */
1403	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1404	/** VMWRITE to unsupported VMCS component. */
1405	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1406	/** VMWRITE to read-only VMCS component. */
1407	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1408	/** VMXON executed in VMX root operation. */
1409	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1410	/** VM-entry with invalid executive-VMCS pointer. */
1411	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1412	/** VM-entry with non-launched executive VMCS. */
1413	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1414	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1415	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1416	/** VMCALL with non-clear VMCS. */
1417	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1418	/** VMCALL with invalid VM-exit control fields. */
1419	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1420	/** VMCALL with incorrect MSEG revision identifier. */
1421	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1422	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1423	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1424	/** VMCALL with invalid SMM-monitor features. */
1425	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1426	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1427	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1428	/** VM-entry with events blocked by MOV SS. */
1429	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1430	/** Invalid operand to INVEPT/INVVPID. */
1431	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1432	} VMXINSTRERR;
1433	/** @} */
1434
1435
1436	/** @name VMX abort reasons.
1437	* In accordance with the VT-x spec.
1438	* See Intel spec. "27.7 VMX Aborts".
1439	* Update HMGetVmxAbortDesc() if new reasons are added. @{
1440	*/
1441	typedef enum
1442	{
1443	/** None - don't use this / uninitialized value. */
1444	VMXABORT_NONE = 0,
1445	/** VMX abort caused during saving of guest MSRs. */
1446	VMXABORT_SAVE_GUEST_MSRS = 1,
1447	/** VMX abort caused during host PDPTE checks. */
1448	VMXBOART_HOST_PDPTE = 2,
1449	/** VMX abort caused due to current VMCS being corrupted. */
1450	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1451	/** VMX abort caused during loading of host MSRs. */
1452	VMXABORT_LOAD_HOST_MSR = 4,
1453	/** VMX abort caused due to a machine-check exception during VM-exit. */
1454	VMXABORT_MACHINE_CHECK_XCPT = 5,
1455	/** VMX abort caused due to invalid return from long mode. */
1456	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1457	/* Type size hack. */
1458	VMXABORT_32BIT_HACK = 0x7fffffff
1459	} VMXABORT;
1460	AssertCompileSize(VMXABORT, 4);
1461	/** @} */
1462
1463
1464	/** @name VMX MSR - Basic VMX information.
1465	* @{
1466	*/
1467	/** VMCS (and related regions) memory type - Uncacheable. */
1468	#define VMX_BASIC_MEM_TYPE_UC 0
1469	/** VMCS (and related regions) memory type - Write back. */
1470	#define VMX_BASIC_MEM_TYPE_WB 6
1471
1472	/** Bit fields for MSR_IA32_VMX_BASIC. */
1473	/** VMCS revision identifier used by the processor. */
1474	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1475	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1476	/** Bit 31 is reserved and RAZ. */
1477	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1478	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1479	/** VMCS size in bytes. */
1480	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1481	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1482	/** Bits 45:47 are reserved. */
1483	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1484	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1485	/** Width of physical addresses used for the VMCS and associated memory regions
1486	* (always 0 on CPUs that support Intel 64 architecture). */
1487	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1488	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1489	/** Dual-monitor treatment of SMI and SMM supported. */
1490	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1491	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1492	/** Memory type that must be used for the VMCS and associated memory regions. */
1493	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1494	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1495	/** VM-exit instruction information for INS/OUTS. */
1496	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1497	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1498	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1499	* bits in VMX control MSRs. */
1500	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1501	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1502	/** Bits 56:63 are reserved and RAZ. */
1503	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 56
1504	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xff00000000000000)
1505	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1506	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1507	VMCS_INS_OUTS, TRUE_CTLS, RSVD_56_63));
1508	/** @} */
1509
1510
1511	/** @name VMX MSR - Miscellaneous data.
1512	* @{
1513	*/
1514	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1515	#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1516	/** Whether Intel PT is supported in VMX operation. */
1517	#define VMX_MISC_INTEL_PT RT_BIT(14)
1518	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1519	* VMWRITE cannot modify read-only VM-exit information fields. */
1520	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1521	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1522	* instructions. */
1523	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1524	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1525	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1526	/** Maximum CR3-target count supported by the CPU. */
1527	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1528
1529	/** Bit fields for MSR_IA32_VMX_MISC. */
1530	/** Relationship between the preemption timer and tsc. */
1531	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1532	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1533	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1534	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1535	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1536	/** Activity states supported by the implementation. */
1537	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1538	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1539	/** Bits 9:13 is reserved and RAZ. */
1540	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1541	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1542	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1543	#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1544	#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1545	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1546	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1547	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1548	/** Number of CR3 target values supported by the processor. (0-256) */
1549	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1550	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1551	/** Maximum number of MSRs in the VMCS. */
1552	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1553	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1554	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1555	* SMIs. */
1556	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1557	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1558	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1559	* VMWRITE cannot modify read-only VM-exit information fields. */
1560	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1561	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1562	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1563	* instructions. */
1564	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1565	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1566	/** Bit 31 is reserved and RAZ. */
1567	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1568	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1569	/** 32-bit MSEG revision ID used by the processor. */
1570	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1571	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1572	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1573	(PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1574	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1575	/** @} */
1576
1577	/** @name VMX MSR - VMCS enumeration.
1578	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1579	* @{
1580	*/
1581	/** Bit 0 is reserved and RAZ. */
1582	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1583	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1584	/** Highest index value used in VMCS field encoding. */
1585	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1586	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1587	/** Bit 10:63 is reserved and RAZ. */
1588	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1589	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1590	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1591	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1592	/** @} */
1593
1594
1595	/** @name VMX MSR - VM Functions.
1596	* Bit fields for MSR_IA32_VMX_VMFUNC.
1597	* @{
1598	*/
1599	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1600	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1601	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1602	/** Bits 1:63 are reserved and RAZ. */
1603	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1604	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1605	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1606	(EPTP_SWITCHING, RSVD_1_63));
1607	/** @} */
1608
1609
1610	/** @name VMX MSR - EPT/VPID capabilities.
1611	* @{
1612	*/
1613	/** Supports execute-only translations by EPT. */
1614	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1615	/** Supports page-walk length of 4. */
1616	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1617	/** Supports EPT paging-structure memory type to be uncacheable. */
1618	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1619	/** Supports EPT paging structure memory type to be write-back. */
1620	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1621	/** Supports EPT PDE to map a 2 MB page. */
1622	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1623	/** Supports EPT PDPTE to map a 1 GB page. */
1624	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1625	/** Supports INVEPT instruction. */
1626	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1627	/** Supports accessed and dirty flags for EPT. */
1628	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1629	/** Supports single-context INVEPT type. */
1630	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1631	/** Supports all-context INVEPT type. */
1632	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1633	/** Supports INVVPID instruction. */
1634	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1635	/** Supports individual-address INVVPID type. */
1636	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1637	/** Supports single-context INVVPID type. */
1638	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1639	/** Supports all-context INVVPID type. */
1640	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1641	/** Supports singe-context-retaining-globals INVVPID type. */
1642	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1643
1644	/** Bit fields for MSR_IA32_VMX_EPT_VPID_CAP. */
1645	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_SHIFT 0
1646	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_MASK UINT64_C(0x0000000000000001)
1647	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_SHIFT 1
1648	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_MASK UINT64_C(0x000000000000003e)
1649	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_SHIFT 6
1650	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_MASK UINT64_C(0x0000000000000040)
1651	#define VMX_BF_EPT_VPID_CAP_RSVD_7_SHIFT 7
1652	#define VMX_BF_EPT_VPID_CAP_RSVD_7_MASK UINT64_C(0x0000000000000080)
1653	#define VMX_BF_EPT_VPID_CAP_EMT_UC_SHIFT 8
1654	#define VMX_BF_EPT_VPID_CAP_EMT_UC_MASK UINT64_C(0x0000000000000100)
1655	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_SHIFT 9
1656	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1657	#define VMX_BF_EPT_VPID_CAP_EMT_WB_SHIFT 14
1658	#define VMX_BF_EPT_VPID_CAP_EMT_WB_MASK UINT64_C(0x0000000000004000)
1659	#define VMX_BF_EPT_VPID_CAP_RSVD_15_SHIFT 15
1660	#define VMX_BF_EPT_VPID_CAP_RSVD_15_MASK UINT64_C(0x0000000000008000)
1661	#define VMX_BF_EPT_VPID_CAP_PDE_2M_SHIFT 16
1662	#define VMX_BF_EPT_VPID_CAP_PDE_2M_MASK UINT64_C(0x0000000000010000)
1663	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_SHIFT 17
1664	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_MASK UINT64_C(0x0000000000020000)
1665	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_SHIFT 18
1666	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_MASK UINT64_C(0x00000000000c0000)
1667	#define VMX_BF_EPT_VPID_CAP_INVEPT_SHIFT 20
1668	#define VMX_BF_EPT_VPID_CAP_INVEPT_MASK UINT64_C(0x0000000000100000)
1669	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_SHIFT 21
1670	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_MASK UINT64_C(0x0000000000200000)
1671	#define VMX_BF_EPT_VPID_CAP_RSVD_22_24_SHIFT 22
1672	#define VMX_BF_EPT_VPID_CAP_RSVD_22_24_MASK UINT64_C(0x0000000001c00000)
1673	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_SHIFT 25
1674	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_MASK UINT64_C(0x0000000002000000)
1675	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_SHIFT 26
1676	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_MASK UINT64_C(0x0000000004000000)
1677	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_SHIFT 27
1678	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_MASK UINT64_C(0x00000000f8000000)
1679	#define VMX_BF_EPT_VPID_CAP_INVVPID_SHIFT 32
1680	#define VMX_BF_EPT_VPID_CAP_INVVPID_MASK UINT64_C(0x0000000100000000)
1681	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_SHIFT 33
1682	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_MASK UINT64_C(0x000000fe00000000)
1683	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_SHIFT 40
1684	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_MASK UINT64_C(0x0000010000000000)
1685	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_SHIFT 41
1686	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_MASK UINT64_C(0x0000020000000000)
1687	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_SHIFT 42
1688	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_MASK UINT64_C(0x0000040000000000)
1689	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_SHIFT 43
1690	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_MASK UINT64_C(0x0000080000000000)
1691	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_SHIFT 44
1692	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_MASK UINT64_C(0xfffff00000000000)
1693	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_VPID_CAP_, UINT64_C(0), UINT64_MAX,
1694	(RWX_X_ONLY, RSVD_1_5, PAGE_WALK_LENGTH_4, RSVD_7, EMT_UC, RSVD_9_13, EMT_WB, RSVD_15, PDE_2M,
1695	PDPTE_1G, RSVD_18_19, INVEPT, EPT_ACCESS_DIRTY, RSVD_22_24, INVEPT_SINGLE_CTX,
1696	INVEPT_ALL_CTX, RSVD_27_31, INVVPID, RSVD_33_39, INVVPID_INDIV_ADDR, INVVPID_SINGLE_CTX,
1697	INVVPID_ALL_CTX, INVVPID_SINGLE_CTX_RETAIN_GLOBALS, RSVD_44_63));
1698	/** @} */
1699
1700
1701	/** @name Extended Page Table Pointer (EPTP)
1702	* @{
1703	*/
1704	/** Uncachable EPT paging structure memory type. */
1705	#define VMX_EPT_MEMTYPE_UC 0
1706	/** Write-back EPT paging structure memory type. */
1707	#define VMX_EPT_MEMTYPE_WB 6
1708	/** Shift value to get the EPT page walk length (bits 5-3) */
1709	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1710	/** Mask value to get the EPT page walk length (bits 5-3) */
1711	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1712	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1713	* length) */
1714	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1715	/** @} */
1716
1717
1718	/** @name VMCS fields and encoding.
1719	*
1720	* When adding a new field:
1721	* - Always add it to g_aVmcsFields.
1722	* - Consider if it needs to be added to VMXVVMCS.
1723	* @{
1724	*/
1725	/** 16-bit control fields. */
1726	#define VMX_VMCS16_VPID 0x0000
1727	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1728	#define VMX_VMCS16_EPTP_INDEX 0x0004
1729
1730	/** 16-bit guest-state fields. */
1731	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1732	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1733	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1734	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1735	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1736	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1737	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1738	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1739	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1740	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1741
1742	/** 16-bits host-state fields. */
1743	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1744	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1745	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1746	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1747	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1748	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1749	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1750
1751	/** 64-bit control fields. */
1752	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1753	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1754	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1755	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1756	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1757	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1758	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1759	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1760	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1761	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1762	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1763	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1764	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1765	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1766	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1767	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1768	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1769	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1770	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1771	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1772	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1773	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1774	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1775	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1776	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1777	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1778	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1779	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1780	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1781	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1782	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1783	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1784	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1785	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1786	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1787	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1788	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1789	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1790	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1791	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1792	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1793	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1794	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1795	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1796	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1797	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1798	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1799	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1800	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1801	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1802
1803	/** 64-bit read-only data fields. */
1804	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1805	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1806
1807	/** 64-bit guest-state fields. */
1808	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1809	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1810	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1811	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1812	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1813	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1814	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1815	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1816	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1817	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1818	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1819	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1820	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1821	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1822	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1823	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1824	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1825	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1826	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1827	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1828
1829	/** 64-bit host-state fields. */
1830	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1831	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1832	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1833	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1834	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1835	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1836
1837	/** 32-bit control fields. */
1838	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1839	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1840	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1841	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1842	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1843	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1844	#define VMX_VMCS32_CTRL_EXIT 0x400c
1845	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1846	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1847	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1848	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1849	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1850	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1851	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1852	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1853	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1854	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1855	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1856
1857	/** 32-bits read-only fields. */
1858	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1859	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1860	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1861	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1862	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1863	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1864	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1865	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1866
1867	/** 32-bit guest-state fields. */
1868	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1869	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1870	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1871	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1872	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1873	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1874	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1875	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1876	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1877	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1878	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1879	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1880	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1881	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1882	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1883	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1884	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1885	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1886	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1887	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1888	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1889	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
1890	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1891
1892	/** 32-bit host-state fields. */
1893	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1894
1895	/** Natural-width control fields. */
1896	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1897	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1898	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1899	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1900	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1901	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1902	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1903	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
1904
1905	/** Natural-width read-only data fields. */
1906	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1907	#define VMX_VMCS_RO_IO_RCX 0x6402
1908	#define VMX_VMCS_RO_IO_RSI 0x6404
1909	#define VMX_VMCS_RO_IO_RDI 0x6406
1910	#define VMX_VMCS_RO_IO_RIP 0x6408
1911	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
1912
1913	/** Natural-width guest-state fields. */
1914	#define VMX_VMCS_GUEST_CR0 0x6800
1915	#define VMX_VMCS_GUEST_CR3 0x6802
1916	#define VMX_VMCS_GUEST_CR4 0x6804
1917	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1918	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1919	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1920	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1921	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1922	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1923	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1924	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1925	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1926	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1927	#define VMX_VMCS_GUEST_DR7 0x681a
1928	#define VMX_VMCS_GUEST_RSP 0x681c
1929	#define VMX_VMCS_GUEST_RIP 0x681e
1930	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1931	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
1932	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
1933	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
1934
1935	/** Natural-width host-state fields. */
1936	#define VMX_VMCS_HOST_CR0 0x6c00
1937	#define VMX_VMCS_HOST_CR3 0x6c02
1938	#define VMX_VMCS_HOST_CR4 0x6c04
1939	#define VMX_VMCS_HOST_FS_BASE 0x6c06
1940	#define VMX_VMCS_HOST_GS_BASE 0x6c08
1941	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
1942	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
1943	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
1944	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
1945	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
1946	#define VMX_VMCS_HOST_RSP 0x6c14
1947	#define VMX_VMCS_HOST_RIP 0x6c16
1948
1949	/**
1950	* VMCS field.
1951	* In accordance with the VT-x spec.
1952	*/
1953	typedef union
1954	{
1955	struct
1956	{
1957	/** The access type; 0=full, 1=high of 64-bit fields. */
1958	uint32_t fAccessType : 1;
1959	/** The index. */
1960	uint32_t u8Index : 8;
1961	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
1962	uint32_t u2Type : 2;
1963	/** Reserved (MBZ). */
1964	uint32_t u1Reserved0 : 1;
1965	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
1966	uint32_t u2Width : 2;
1967	/** Reserved (MBZ). */
1968	uint32_t u18Reserved0 : 18;
1969	} n;
1970
1971	/* The unsigned integer view. */
1972	uint32_t u;
1973	} VMXVMCSFIELD;
1974	AssertCompileSize(VMXVMCSFIELD, 4);
1975	/** Pointer to a VMCS field. */
1976	typedef VMXVMCSFIELD *PVMXVMCSFIELD;
1977	/** Pointer to a const VMCS field. */
1978	typedef const VMXVMCSFIELD *PCVMXVMCSFIELD;
1979
1980	/** VMCS field: Mask of reserved bits (bits 63:15 MBZ), bit 12 is not included! */
1981	#define VMX_VMCSFIELD_RSVD_MASK UINT64_C(0xffffffffffff8000)
1982
1983	/** Bits fields for a VMCS field. */
1984	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_SHIFT 0
1985	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_MASK UINT32_C(0x00000001)
1986	#define VMX_BF_VMCSFIELD_INDEX_SHIFT 1
1987	#define VMX_BF_VMCSFIELD_INDEX_MASK UINT32_C(0x000003fe)
1988	#define VMX_BF_VMCSFIELD_TYPE_SHIFT 10
1989	#define VMX_BF_VMCSFIELD_TYPE_MASK UINT32_C(0x00000c00)
1990	#define VMX_BF_VMCSFIELD_RSVD_12_SHIFT 12
1991	#define VMX_BF_VMCSFIELD_RSVD_12_MASK UINT32_C(0x00001000)
1992	#define VMX_BF_VMCSFIELD_WIDTH_SHIFT 13
1993	#define VMX_BF_VMCSFIELD_WIDTH_MASK UINT32_C(0x00006000)
1994	#define VMX_BF_VMCSFIELD_RSVD_15_31_SHIFT 15
1995	#define VMX_BF_VMCSFIELD_RSVD_15_31_MASK UINT32_C(0xffff8000)
1996	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCSFIELD_, UINT32_C(0), UINT32_MAX,
1997	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
1998
1999	/**
2000	* VMCS field encoding: Access type.
2001	* In accordance with the VT-x spec.
2002	*/
2003	typedef enum
2004	{
2005	VMXVMCSFIELDACCESS_FULL = 0,
2006	VMXVMCSFIELDACCESS_HIGH
2007	} VMXVMCSFIELDACCESS;
2008	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
2009	/** VMCS field encoding type: Full. */
2010	#define VMX_VMCSFIELD_ACCESS_FULL 0
2011	/** VMCS field encoding type: High. */
2012	#define VMX_VMCSFIELD_ACCESS_HIGH 1
2013
2014	/**
2015	* VMCS field encoding: Type.
2016	* In accordance with the VT-x spec.
2017	*/
2018	typedef enum
2019	{
2020	VMXVMCSFIELDTYPE_CONTROL = 0,
2021	VMXVMCSFIELDTYPE_VMEXIT_INFO,
2022	VMXVMCSFIELDTYPE_GUEST_STATE,
2023	VMXVMCSFIELDTYPE_HOST_STATE
2024	} VMXVMCSFIELDTYPE;
2025	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
2026	/** VMCS field encoding type: Control. */
2027	#define VMX_VMCSFIELD_TYPE_CONTROL 0
2028	/** VMCS field encoding type: VM-exit information / read-only fields. */
2029	#define VMX_VMCSFIELD_TYPE_VMEXIT_INFO 1
2030	/** VMCS field encoding type: Guest-state. */
2031	#define VMX_VMCSFIELD_TYPE_GUEST_STATE 2
2032	/** VMCS field encoding type: Host-state. */
2033	#define VMX_VMCSFIELD_TYPE_HOST_STATE 3
2034
2035	/**
2036	* VMCS field encoding: Width.
2037	* In accordance with the VT-x spec.
2038	*/
2039	typedef enum
2040	{
2041	VMXVMCSFIELDWIDTH_16BIT = 0,
2042	VMXVMCSFIELDWIDTH_64BIT,
2043	VMXVMCSFIELDWIDTH_32BIT,
2044	VMXVMCSFIELDWIDTH_NATURAL
2045	} VMXVMCSFIELDWIDTH;
2046	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
2047	/** VMCS field encoding width: 16-bit. */
2048	#define VMX_VMCSFIELD_WIDTH_16BIT 0
2049	/** VMCS field encoding width: 64-bit. */
2050	#define VMX_VMCSFIELD_WIDTH_64BIT 1
2051	/** VMCS field encoding width: 32-bit. */
2052	#define VMX_VMCSFIELD_WIDTH_32BIT 2
2053	/** VMCS field encoding width: Natural width. */
2054	#define VMX_VMCSFIELD_WIDTH_NATURAL 3
2055	/** @} */
2056
2057
2058	/** @name VM-entry instruction length.
2059	* @{ */
2060	/** The maximum valid value for VM-entry instruction length while injecting a
2061	* software interrupt, software exception or privileged software exception. */
2062	#define VMX_ENTRY_INSTR_LEN_MAX 15
2063	/** @} */
2064
2065
2066	/** @name VM-entry register masks.
2067	* @{ */
2068	/** CR0 bits ignored on VM-entry (ET, NW, CD and reserved bits bits 6:15, bit 17,
2069	* bits 19:28). */
2070	#define VMX_ENTRY_CR0_IGNORE_MASK UINT64_C(0x7ffaffd0)
2071	/** DR7 bits set here are always cleared on VM-entry (bit 12, bits 14:15). */
2072	#define VMX_ENTRY_DR7_MBZ_MASK UINT64_C(0xd000)
2073	/** DR7 bits set here are always set on VM-entry (bit 10). */
2074	#define VMX_ENTRY_DR7_MB1_MASK UINT64_C(0x400)
2075	/** @} */
2076
2077
2078	/** @name Pin-based VM-execution controls.
2079	* @{
2080	*/
2081	/** External interrupt exiting. */
2082	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
2083	/** NMI exiting. */
2084	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
2085	/** Virtual NMIs. */
2086	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
2087	/** Activate VMX preemption timer. */
2088	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
2089	/** Process interrupts with the posted-interrupt notification vector. */
2090	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
2091	/** Default1 class when true capability MSRs are not supported. */
2092	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
2093
2094	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
2095	* controls field in the VMCS. */
2096	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
2097	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
2098	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
2099	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
2100	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
2101	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
2102	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
2103	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
2104	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
2105	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
2106	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
2107	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
2108	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
2109	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
2110	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
2111	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
2112	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
2113	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
2114	/** @} */
2115
2116
2117	/** @name Processor-based VM-execution controls.
2118	* @{
2119	*/
2120	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
2121	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
2122	/** Use timestamp counter offset. */
2123	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
2124	/** VM-exit when executing the HLT instruction. */
2125	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
2126	/** VM-exit when executing the INVLPG instruction. */
2127	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
2128	/** VM-exit when executing the MWAIT instruction. */
2129	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
2130	/** VM-exit when executing the RDPMC instruction. */
2131	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
2132	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
2133	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
2134	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
2135	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2136	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
2137	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
2138	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2139	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
2140	/** VM-exit on CR8 loads. */
2141	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
2142	/** VM-exit on CR8 stores. */
2143	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
2144	/** Use TPR shadow. */
2145	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
2146	/** VM-exit when virtual NMI blocking is disabled. */
2147	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
2148	/** VM-exit when executing a MOV DRx instruction. */
2149	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
2150	/** VM-exit when executing IO instructions. */
2151	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
2152	/** Use IO bitmaps. */
2153	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
2154	/** Monitor trap flag. */
2155	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2156	/** Use MSR bitmaps. */
2157	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2158	/** VM-exit when executing the MONITOR instruction. */
2159	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2160	/** VM-exit when executing the PAUSE instruction. */
2161	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2162	/** Whether the secondary processor based VM-execution controls are used. */
2163	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2164	/** Default1 class when true-capability MSRs are not supported. */
2165	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2166
2167	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2168	* controls field in the VMCS. */
2169	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
2170	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2171	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2172	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2173	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2174	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2175	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
2176	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
2177	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2178	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2179	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
2180	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
2181	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2182	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2183	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2184	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2185	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2186	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2187	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2188	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2189	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
2190	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2191	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2192	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2193	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2194	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2195	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
2196	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
2197	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2198	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2199	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2200	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2201	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2202	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2203	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2204	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2205	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2206	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2207	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2208	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2209	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2210	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2211	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
2212	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
2213	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2214	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2215	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2216	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2217	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2218	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2219	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2220	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2221	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2222	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2223	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2224	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
2225	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
2226	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2227	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2228	USE_SECONDARY_CTLS));
2229	/** @} */
2230
2231
2232	/** @name Secondary Processor-based VM-execution controls.
2233	* @{
2234	*/
2235	/** Virtualize APIC accesses. */
2236	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2237	/** EPT supported/enabled. */
2238	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2239	/** Descriptor table instructions cause VM-exits. */
2240	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2241	/** RDTSCP supported/enabled. */
2242	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2243	/** Virtualize x2APIC mode. */
2244	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2245	/** VPID supported/enabled. */
2246	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2247	/** VM-exit when executing the WBINVD instruction. */
2248	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2249	/** Unrestricted guest execution. */
2250	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2251	/** APIC register virtualization. */
2252	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2253	/** Virtual-interrupt delivery. */
2254	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2255	/** A specified number of pause loops cause a VM-exit. */
2256	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2257	/** VM-exit when executing RDRAND instructions. */
2258	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2259	/** Enables INVPCID instructions. */
2260	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2261	/** Enables VMFUNC instructions. */
2262	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2263	/** Enables VMCS shadowing. */
2264	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2265	/** Enables ENCLS VM-exits. */
2266	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2267	/** VM-exit when executing RDSEED. */
2268	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2269	/** Enables page-modification logging. */
2270	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2271	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2272	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
2273	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2274	#define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19)
2275	/** Enables XSAVES/XRSTORS instructions. */
2276	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2277	/** Enables supervisor/user mode based EPT execute permission for linear
2278	* addresses. */
2279	#define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22)
2280	/** Enables EPT permissions to be specified at granularity of 128 bytes. */
2281	#define VMX_PROC_CTLS2_SPPTP_EPT RT_BIT(23)
2282	/** Intel PT output addresses are treated as guest-physical addresses and
2283	* translated using EPT. */
2284	#define VMX_PROC_CTLS2_PT_EPT RT_BIT(24)
2285	/** Use TSC scaling. */
2286	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2287	/** Enables TPAUSE, UMONITOR and UMWAIT instructions. */
2288	#define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26)
2289	/** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */
2290	#define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28)
2291
2292	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2293	* VM-execution controls field in the VMCS. */
2294	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2295	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2296	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2297	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2298	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2299	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2300	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2301	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2302	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2303	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2304	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2305	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2306	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2307	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2308	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2309	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2310	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2311	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2312	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2313	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2314	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2315	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2316	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2317	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2318	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2319	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2320	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2321	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2322	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2323	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2324	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2325	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2326	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2327	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2328	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2329	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2330	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2331	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2332	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19
2333	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000)
2334	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2335	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2336	#define VMX_BF_PROC_CTLS2_UNDEF_21_SHIFT 21
2337	#define VMX_BF_PROC_CTLS2_UNDEF_21_MASK UINT32_C(0x00200000)
2338	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22
2339	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000)
2340	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_SHIFT 23
2341	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_MASK UINT32_C(0x00800000)
2342	#define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24
2343	#define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000)
2344	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2345	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2346	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26
2347	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000)
2348	#define VMX_BF_PROC_CTLS2_UNDEF_27_SHIFT 27
2349	#define VMX_BF_PROC_CTLS2_UNDEF_27_MASK UINT32_C(0x08000000)
2350	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28
2351	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000)
2352	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_SHIFT 29
2353	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_MASK UINT32_C(0xe0000000)
2354
2355	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2356	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2357	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2358	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, UNDEF_21,
2359	MODE_BASED_EPT_PERM, SPPTP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, UNDEF_27, ENCLV_EXIT,
2360	UNDEF_29_31));
2361	/** @} */
2362
2363
2364	/** @name VM-entry controls.
2365	* @{
2366	*/
2367	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2368	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2369	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2370	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2371	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2372	/** In SMM mode after VM-entry. */
2373	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2374	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2375	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2376	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2377	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2378	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2379	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2380	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2381	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2382	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2383	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2384	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2385	#define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17)
2386	/** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
2387	#define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18)
2388	/** Default1 class when true-capability MSRs are not supported. */
2389	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2390
2391	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2392	* VMCS. */
2393	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2394	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2395	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2396	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2397	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2398	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2399	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2400	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2401	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2402	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2403	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2404	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2405	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2406	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2407	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2408	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2409	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2410	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2411	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2412	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2413	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2414	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2415	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17
2416	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000)
2417	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18
2418	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000)
2419	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_SHIFT 19
2420	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_MASK UINT32_C(0xfff80000)
2421	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2422	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2423	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
2424	LOAD_RTIT_CTL_MSR, UNDEF_19_31));
2425	/** @} */
2426
2427
2428	/** @name VM-exit controls.
2429	* @{
2430	*/
2431	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2432	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2433	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2434	/** Return to long mode after a VM-exit. */
2435	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2436	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2437	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2438	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2439	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2440	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2441	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2442	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2443	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2444	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2445	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2446	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2447	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2448	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2449	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2450	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2451	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2452	/** Whether to conceal VMX from Intel PT. */
2453	#define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24)
2454	/** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
2455	#define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25)
2456	/** Default1 class when true-capability MSRs are not supported. */
2457	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2458
2459	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2460	* VMCS. */
2461	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2462	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2463	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2464	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2465	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2466	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2467	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2468	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2469	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2470	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2471	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2472	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2473	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2474	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2475	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2476	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2477	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2478	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2479	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2480	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2481	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2482	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2483	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2484	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2485	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2486	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2487	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2488	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2489	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23
2490	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000)
2491	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24
2492	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000)
2493	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25
2494	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000)
2495	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_SHIFT 26
2496	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2497	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2498	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2499	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2500	SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, UNDEF_26_31));
2501	/** @} */
2502
2503
2504	/** @name VM-exit reason.
2505	* @{
2506	*/
2507	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2508	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2509	#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2510
2511	/** Bit fields for VM-exit reason. */
2512	/** The exit reason. */
2513	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2514	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2515	/** Bits 16:26 are reseved and MBZ. */
2516	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2517	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2518	/** Whether the VM-exit was incident to enclave mode. */
2519	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2520	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2521	/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2522	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2523	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2524	/** VM-exit from VMX root operation (only possible with SMM). */
2525	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2526	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2527	/** Bit 30 is reserved and MBZ. */
2528	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2529	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2530	/** Whether VM-entry failed (currently only happens during loading guest-state
2531	* or MSRs or machine check exceptions). */
2532	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2533	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2534	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2535	(BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2536	/** @} */
2537
2538
2539	/** @name VM-entry interruption information.
2540	* @{
2541	*/
2542	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2543	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2544	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2545	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2546	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2547	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2548	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2549	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2550	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2551	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2552	/** Construct an VM-entry interruption information field from a VM-exit interruption
2553	* info value (same except that bit 12 is reserved). */
2554	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2555	/** Construct a VM-entry interruption information field from an IDT-vectoring
2556	* information field (same except that bit 12 is reserved). */
2557	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2558
2559	/** Bit fields for VM-entry interruption information. */
2560	/** The VM-entry interruption vector. */
2561	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2562	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2563	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2564	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2565	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2566	/** Whether this event has an error code. */
2567	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2568	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2569	/** Bits 12:30 are reserved and MBZ. */
2570	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2571	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2572	/** Whether this VM-entry interruption info is valid. */
2573	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2574	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2575	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2576	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2577	/** @} */
2578
2579
2580	/** @name VM-entry exception error code.
2581	* @{ */
2582	/** Error code valid mask. */
2583	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2584	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2585	* stack aligned for doubleword pushes, the upper half of the error code is
2586	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2587	* use below. */
2588	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2589	/** @} */
2590
2591	/** @name VM-entry interruption information types.
2592	* @{
2593	*/
2594	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2595	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2596	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2597	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2598	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2599	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2600	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2601	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2602	/** @} */
2603
2604
2605	/** @name VM-entry interruption information vector types for
2606	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2607	* @{ */
2608	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2609	/** @} */
2610
2611
2612	/** @name VM-exit interruption information.
2613	* @{
2614	*/
2615	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2616	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2617	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2618	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2619	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2620	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2621	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2622	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2623	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2624
2625	/** Bit fields for VM-exit interruption infomration. */
2626	/** The VM-exit interruption vector. */
2627	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2628	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2629	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2630	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2631	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2632	/** Whether this event has an error code. */
2633	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2634	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2635	/** Whether NMI-unblocking due to IRET is active. */
2636	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2637	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2638	/** Bits 13:30 is reserved (MBZ). */
2639	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2640	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2641	/** Whether this VM-exit interruption info is valid. */
2642	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2643	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2644	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2645	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2646	/** @} */
2647
2648
2649	/** @name VM-exit interruption information types.
2650	* @{
2651	*/
2652	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2653	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2654	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2655	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2656	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2657	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2658	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2659	/** @} */
2660
2661
2662	/** @name VM-exit instruction identity.
2663	*
2664	* These are found in VM-exit instruction information fields for certain
2665	* instructions.
2666	* @{ */
2667	typedef uint32_t VMXINSTRID;
2668	/** Whether the instruction ID field is valid. */
2669	#define VMXINSTRID_VALID RT_BIT_32(31)
2670	/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
2671	* read or write. */
2672	#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
2673	/** Gets whether the instruction ID is valid or not. */
2674	#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
2675	#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
2676	/** Gets the instruction ID. */
2677	#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W))
2678	/** No instruction ID info. */
2679	#define VMXINSTRID_NONE 0
2680
2681	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2682	#define VMXINSTRID_SGDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2683	#define VMXINSTRID_SIDT (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2684	#define VMXINSTRID_LGDT (0x2 \| VMXINSTRID_VALID)
2685	#define VMXINSTRID_LIDT (0x3 \| VMXINSTRID_VALID)
2686
2687	#define VMXINSTRID_SLDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2688	#define VMXINSTRID_STR (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2689	#define VMXINSTRID_LLDT (0x2 \| VMXINSTRID_VALID)
2690	#define VMXINSTRID_LTR (0x3 \| VMXINSTRID_VALID)
2691
2692	/** The following IDs are used internally (some for logging, others for conveying
2693	* the ModR/M primary operand write bit): */
2694	#define VMXINSTRID_VMLAUNCH (0x10 \| VMXINSTRID_VALID)
2695	#define VMXINSTRID_VMRESUME (0x11 \| VMXINSTRID_VALID)
2696	#define VMXINSTRID_VMREAD (0x12 \| VMXINSTRID_VALID)
2697	#define VMXINSTRID_VMWRITE (0x13 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2698	#define VMXINSTRID_IO_IN (0x14 \| VMXINSTRID_VALID)
2699	#define VMXINSTRID_IO_INS (0x15 \| VMXINSTRID_VALID)
2700	#define VMXINSTRID_IO_OUT (0x16 \| VMXINSTRID_VALID)
2701	#define VMXINSTRID_IO_OUTS (0x17 \| VMXINSTRID_VALID)
2702	#define VMXINSTRID_MOV_TO_DRX (0x18 \| VMXINSTRID_VALID)
2703	#define VMXINSTRID_MOV_FROM_DRX (0x19 \| VMXINSTRID_VALID)
2704	/** @} */
2705
2706
2707	/** @name IDT-vectoring information.
2708	* @{
2709	*/
2710	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2711	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2712	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2713	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2714
2715	/** Construct an IDT-vectoring information field from an VM-entry interruption
2716	* information field (same except that bit 12 is reserved). */
2717	#define VMX_EXIT_IDT_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
2718
2719	/** Bit fields for IDT-vectoring information. */
2720	/** The IDT-vectoring info vector. */
2721	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2722	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2723	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
2724	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2725	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2726	/** Whether the event has an error code. */
2727	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2728	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2729	/** Bit 12 is undefined. */
2730	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2731	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2732	/** Bits 13:30 is reserved (MBZ). */
2733	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2734	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2735	/** Whether this IDT-vectoring info is valid. */
2736	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2737	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2738	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2739	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2740	/** @} */
2741
2742
2743	/** @name IDT-vectoring information vector types.
2744	* @{
2745	*/
2746	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2747	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2748	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2749	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2750	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2751	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2752	#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
2753	/** @} */
2754
2755
2756	/** @name TPR threshold.
2757	* @{ */
2758	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
2759	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
2760
2761	/** Bit fields for TPR threshold. */
2762	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
2763	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
2764	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
2765	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
2766	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
2767	(TPR, RSVD_4_31));
2768	/** @} */
2769
2770
2771	/** @name Guest-activity states.
2772	* @{
2773	*/
2774	/** The logical processor is active. */
2775	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2776	/** The logical processor is inactive, because it executed a HLT instruction. */
2777	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2778	/** The logical processor is inactive, because of a triple fault or other serious error. */
2779	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2780	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2781	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2782	/** @} */
2783
2784
2785	/** @name Guest-interruptibility states.
2786	* @{
2787	*/
2788	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2789	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2790	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2791	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2792	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
2793
2794	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
2795	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
2796	/** @} */
2797
2798
2799	/** @name Exit qualification for debug exceptions.
2800	* @{
2801	*/
2802	/** Hardware breakpoint 0 was met. */
2803	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
2804	/** Hardware breakpoint 1 was met. */
2805	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
2806	/** Hardware breakpoint 2 was met. */
2807	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
2808	/** Hardware breakpoint 3 was met. */
2809	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
2810	/** Debug register access detected. */
2811	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
2812	/** A debug exception would have been triggered by single-step execution mode. */
2813	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
2814	/** Mask of all valid bits. */
2815	#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
2816	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
2817	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
2818	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
2819	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
2820	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
2821
2822	/** Bit fields for Exit qualifications due to debug exceptions. */
2823	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
2824	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
2825	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
2826	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
2827	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
2828	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
2829	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
2830	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
2831	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
2832	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
2833	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
2834	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
2835	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
2836	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
2837	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
2838	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
2839	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
2840	(BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
2841	/** @} */
2842
2843	/** @name Exit qualification for Mov DRx.
2844	* @{
2845	*/
2846	/** 0-2: Debug register number */
2847	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
2848	/** 3: Reserved; cleared to 0. */
2849	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
2850	/** 4: Direction of move (0 = write, 1 = read) */
2851	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
2852	/** 5-7: Reserved; cleared to 0. */
2853	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
2854	/** 8-11: General purpose register number. */
2855	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
2856
2857	/** Bit fields for Exit qualification due to Mov DRx. */
2858	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
2859	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
2860	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
2861	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
2862	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
2863	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
2864	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
2865	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
2866	#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
2867	#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
2868	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
2869	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
2870	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
2871	(REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
2872	/** @} */
2873
2874
2875	/** @name Exit qualification for debug exceptions types.
2876	* @{
2877	*/
2878	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
2879	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
2880	/** @} */
2881
2882
2883	/** @name Exit qualification for control-register accesses.
2884	* @{
2885	*/
2886	/** 0-3: Control register number (0 for CLTS & LMSW) */
2887	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
2888	/** 4-5: Access type. */
2889	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
2890	/** 6: LMSW operand type memory (1 for memory, 0 for register). */
2891	#define VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(a) (((a) >> 6) & 1)
2892	/** 7: Reserved; cleared to 0. */
2893	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
2894	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
2895	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
2896	/** 12-15: Reserved; cleared to 0. */
2897	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
2898	/** 16-31: LMSW source data (else 0). */
2899	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
2900
2901	/** Bit fields for Exit qualification for control-register accesses. */
2902	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
2903	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
2904	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
2905	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
2906	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
2907	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
2908	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
2909	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
2910	#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
2911	#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
2912	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
2913	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
2914	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
2915	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
2916	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
2917	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
2918	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
2919	(REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
2920	/** @} */
2921
2922
2923	/** @name Exit qualification for control-register access types.
2924	* @{
2925	*/
2926	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
2927	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
2928	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
2929	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
2930	/** @} */
2931
2932
2933	/** @name Exit qualification for task switch.
2934	* @{
2935	*/
2936	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
2937	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
2938	/** Task switch caused by a call instruction. */
2939	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
2940	/** Task switch caused by an iret instruction. */
2941	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
2942	/** Task switch caused by a jmp instruction. */
2943	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
2944	/** Task switch caused by an interrupt gate. */
2945	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
2946
2947	/** Bit fields for Exit qualification for task switches. */
2948	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
2949	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
2950	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
2951	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
2952	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
2953	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
2954	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
2955	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
2956	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
2957	(NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
2958	/** @} */
2959
2960
2961	/** @name Exit qualification for EPT violations.
2962	* @{
2963	*/
2964	/** Set if the violation was caused by a data read. */
2965	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
2966	/** Set if the violation was caused by a data write. */
2967	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
2968	/** Set if the violation was caused by an instruction fetch. */
2969	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
2970	/** AND of the present bit of all EPT structures. */
2971	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
2972	/** AND of the write bit of all EPT structures. */
2973	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
2974	/** AND of the execute bit of all EPT structures. */
2975	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
2976	/** Set if the guest linear address field contains the faulting address. */
2977	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
2978	/** If bit 7 is one: (reserved otherwise)
2979	* 1 - violation due to physical address access.
2980	* 0 - violation caused by page walk or access/dirty bit updates
2981	*/
2982	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
2983	/** @} */
2984
2985
2986	/** @name Exit qualification for I/O instructions.
2987	* @{
2988	*/
2989	/** 0-2: IO operation size 0(=1 byte), 1(=2 bytes) and 3(=4 bytes). */
2990	#define VMX_EXIT_QUAL_IO_SIZE(a) ((a) & 7)
2991	/** 3: IO operation direction. */
2992	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
2993	/** 4: String IO operation (INS / OUTS). */
2994	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
2995	/** 5: Repeated IO operation. */
2996	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
2997	/** 6: Operand encoding. */
2998	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
2999	/** 16-31: IO Port (0-0xffff). */
3000	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
3001
3002	/** Bit fields for Exit qualification for I/O instructions. */
3003	#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
3004	#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
3005	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
3006	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
3007	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
3008	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
3009	#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
3010	#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
3011	#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
3012	#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
3013	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
3014	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
3015	#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
3016	#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
3017	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
3018	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3019	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
3020	(WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
3021	/** @} */
3022
3023
3024	/** @name Exit qualification for I/O instruction types.
3025	* @{
3026	*/
3027	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
3028	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
3029	/** @} */
3030
3031
3032	/** @name Exit qualification for I/O instruction encoding.
3033	* @{
3034	*/
3035	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
3036	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
3037	/** @} */
3038
3039
3040	/** @name Exit qualification for APIC-access VM-exits from linear and
3041	* guest-physical accesses.
3042	* @{
3043	*/
3044	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
3045	* access within the APIC page. */
3046	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
3047	/** 12-15: Access type. */
3048	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
3049	/* Rest reserved. */
3050
3051	/** Bit fields for Exit qualification for APIC-access VM-exits. */
3052	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
3053	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
3054	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
3055	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
3056	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
3057	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
3058	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
3059	(OFFSET, TYPE, RSVD_16_63));
3060	/** @} */
3061
3062
3063	/** @name Exit qualification for linear address APIC-access types.
3064	* @{
3065	*/
3066	/** Linear access for a data read during instruction execution. */
3067	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
3068	/** Linear access for a data write during instruction execution. */
3069	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
3070	/** Linear access for an instruction fetch. */
3071	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
3072	/** Linear read/write access during event delivery. */
3073	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
3074	/** Physical read/write access during event delivery. */
3075	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
3076	/** Physical access for an instruction fetch or during instruction execution. */
3077	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
3078
3079	/**
3080	* APIC-access type.
3081	* In accordance with the VT-x spec.
3082	*/
3083	typedef enum
3084	{
3085	VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
3086	VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
3087	VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
3088	VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
3089	VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
3090	VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
3091	} VMXAPICACCESS;
3092	AssertCompileSize(VMXAPICACCESS, 4);
3093	/** @} */
3094
3095
3096	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
3097	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3098	* @{
3099	*/
3100	/** Address calculation scaling field (powers of two). */
3101	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
3102	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3103	/** Bits 2 thru 6 are undefined. */
3104	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
3105	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
3106	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3107	* @remarks anyone's guess why this is a 3 bit field... */
3108	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
3109	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3110	/** Bit 10 is defined as zero. */
3111	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
3112	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
3113	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
3114	* for exits from 64-bit code as the operand size there is fixed. */
3115	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
3116	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
3117	/** Bits 12 thru 14 are undefined. */
3118	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
3119	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
3120	/** Applicable segment register (X86_SREG_XXX values). */
3121	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
3122	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3123	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3124	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
3125	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3126	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3127	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3128	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3129	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3130	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
3131	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3132	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3133	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
3134	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3135	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
3136	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
3137	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3138	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
3139	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
3140	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
3141	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
3142	/** Bits 30 & 31 are undefined. */
3143	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
3144	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3145	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3146	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
3147	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3148	/** @} */
3149
3150
3151	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
3152	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3153	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
3154	* @{
3155	*/
3156	/** Address calculation scaling field (powers of two). */
3157	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
3158	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3159	/** Bit 2 is undefined. */
3160	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
3161	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
3162	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
3163	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
3164	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
3165	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3166	* @remarks anyone's guess why this is a 3 bit field... */
3167	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
3168	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3169	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
3170	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
3171	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
3172	/** Bits 11 thru 14 are undefined. */
3173	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
3174	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
3175	/** Applicable segment register (X86_SREG_XXX values). */
3176	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
3177	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3178	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3179	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
3180	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3181	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3182	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3183	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3184	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3185	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
3186	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3187	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3188	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
3189	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3190	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
3191	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
3192	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3193	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
3194	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
3195	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
3196	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
3197	/** Bits 30 & 31 are undefined. */
3198	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3199	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3200	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3201	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3202	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3203	/** @} */
3204
3205
3206	/** @name Format of Pending-Debug-Exceptions.
3207	* Bits 4-11, 13, 15 and 17-63 are reserved.
3208	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3209	* possibly valid here but not in DR6.
3210	* @{
3211	*/
3212	/** Hardware breakpoint 0 was met. */
3213	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3214	/** Hardware breakpoint 1 was met. */
3215	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3216	/** Hardware breakpoint 2 was met. */
3217	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3218	/** Hardware breakpoint 3 was met. */
3219	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3220	/** At least one data or IO breakpoint was hit. */
3221	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3222	/** A debug exception would have been triggered by single-step execution mode. */
3223	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3224	/** A debug exception occurred inside an RTM region. */
3225	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3226	/** Mask of valid bits. */
3227	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3228	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3229	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3230	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3231	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3232	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3233	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3234	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3235	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3236	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3237	/** Bit fields for Pending debug exceptions. */
3238	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3239	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3240	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3241	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3242	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3243	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3244	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3245	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3246	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3247	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3248	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3249	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3250	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3251	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3252	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3253	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3254	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3255	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3256	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3257	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3258	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3259	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3260	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3261	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3262	/** @} */
3263
3264
3265	/** @defgroup grp_hm_vmx_virt VMX virtualization.
3266	* @{
3267	*/
3268
3269	/** @name Virtual VMX MSR - Miscellaneous data.
3270	* @{ */
3271	/** Number of CR3-target values supported. */
3272	#define VMX_V_CR3_TARGET_COUNT 4
3273	/** Activity states supported. */
3274	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3275	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3276	#define VMX_V_PREEMPT_TIMER_SHIFT 5
3277	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3278	#define VMX_V_AUTOMSR_COUNT_MAX 0
3279	/** SMM MSEG revision ID. */
3280	#define VMX_V_MSEG_REV_ID 0
3281	/** @} */
3282
3283	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS launch state.
3284	* @{ */
3285	/** VMCS launch state clear. */
3286	#define VMX_V_VMCS_LAUNCH_STATE_CLEAR RT_BIT(0)
3287	/** VMCS launch state active. */
3288	#define VMX_V_VMCS_LAUNCH_STATE_ACTIVE RT_BIT(1)
3289	/** VMCS launch state current. */
3290	#define VMX_V_VMCS_LAUNCH_STATE_CURRENT RT_BIT(2)
3291	/** VMCS launch state launched. */
3292	#define VMX_V_VMCS_LAUNCH_STATE_LAUNCHED RT_BIT(3)
3293	/** The mask of valid VMCS launch states. */
3294	#define VMX_V_VMCS_LAUNCH_STATE_MASK ( VMX_V_VMCS_LAUNCH_STATE_CLEAR \
3295	\| VMX_V_VMCS_LAUNCH_STATE_ACTIVE \
3296	\| VMX_V_VMCS_LAUNCH_STATE_CURRENT \
3297	\| VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
3298	/** @} */
3299
3300	/** CR0 bits set here must always be set when in VMX operation. */
3301	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
3302	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
3303	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
3304	/** CR4 bits set here must always be set when in VMX operation. */
3305	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3306
3307	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3308	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3309	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001)
3310	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3311
3312	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3313	* complications when teleporation may be implemented). */
3314	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3315	/** The size of the virtual VMCS region (in pages). */
3316	#define VMX_V_VMCS_PAGES 1
3317
3318	/** The size of the Virtual-APIC page (in bytes). */
3319	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3320	/** The size of the Virtual-APIC page (in pages). */
3321	#define VMX_V_VIRT_APIC_PAGES 1
3322
3323	/** Virtual X2APIC MSR range start. */
3324	#define VMX_V_VIRT_APIC_MSR_START 0x800
3325	/** Virtual X2APIC MSR range end. */
3326	#define VMX_V_VIRT_APIC_MSR_END 0x8ff
3327
3328	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3329	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3330	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3331	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3332
3333	/** The size of the MSR bitmap (in bytes). */
3334	#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3335	/** The size of the MSR bitmap (in pages). */
3336	#define VMX_V_MSR_BITMAP_PAGES 1
3337
3338	/** The size of I/O bitmap A (in bytes). */
3339	#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3340	/** The size of I/O bitmap A (in pages). */
3341	#define VMX_V_IO_BITMAP_A_PAGES 1
3342
3343	/** The size of I/O bitmap B (in bytes). */
3344	#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3345	/** The size of I/O bitmap B (in pages). */
3346	#define VMX_V_IO_BITMAP_B_PAGES 1
3347
3348	/** The size of the auto-load/store MSR area (in bytes). */
3349	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3350	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3351	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3352	/** The size of the auto-load/store MSR area (in pages). */
3353	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3354
3355	/** The highest index value used for supported virtual VMCS field encoding. */
3356	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCSFIELD_INDEX)
3357
3358	/**
3359	* Virtual VM-exit information.
3360	*
3361	* This is a convenience structure that bundles some VM-exit information related
3362	* fields together.
3363	*/
3364	typedef struct
3365	{
3366	/** The VM-exit reason. */
3367	uint32_t uReason;
3368	/** The VM-exit instruction length. */
3369	uint32_t cbInstr;
3370	/** The VM-exit instruction information. */
3371	VMXEXITINSTRINFO InstrInfo;
3372	/** The VM-exit instruction ID. */
3373	VMXINSTRID uInstrId;
3374
3375	/** The Exit qualification field. */
3376	uint64_t u64Qual;
3377	/** The Guest-linear address field. */
3378	uint64_t u64GuestLinearAddr;
3379	/** The Guest-physical address field. */
3380	uint64_t u64GuestPhysAddr;
3381	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3382	* instruction VM-exit. */
3383	RTGCPTR GCPtrEffAddr;
3384	} VMXVEXITINFO;
3385	/** Pointer to the VMXVEXITINFO struct. */
3386	typedef VMXVEXITINFO *PVMXVEXITINFO;
3387	/** Pointer to a const VMXVEXITINFO struct. */
3388	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3389	AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3390
3391	/**
3392	* Virtual VM-exit information for events.
3393	*
3394	* This is a convenience structure that bundles some event-based VM-exit information
3395	* related fields together that are not included in VMXVEXITINFO.
3396	*
3397	* This is kept as a separate structure and not included in VMXVEXITINFO, to make it
3398	* easier to distinguish that IEM VM-exit handlers will set one or more of the
3399	* following fields in the virtual VMCS. Including it in the VMXVEXITINFO will not
3400	* make it ovbious which fields may get set (or cleared).
3401	*/
3402	typedef struct
3403	{
3404	/** VM-exit interruption information. */
3405	uint32_t uExitIntInfo;
3406	/** VM-exit interruption error code. */
3407	uint32_t uExitIntErrCode;
3408	/** IDT-vectoring information. */
3409	uint32_t uIdtVectoringInfo;
3410	/** IDT-vectoring error code. */
3411	uint32_t uIdtVectoringErrCode;
3412	} VMXVEXITEVENTINFO;
3413	/** Pointer to the VMXVEXITINFO2 struct. */
3414	typedef VMXVEXITEVENTINFO *PVMXVEXITEVENTINFO;
3415	/** Pointer to a const VMXVEXITINFO2 struct. */
3416	typedef const VMXVEXITEVENTINFO *PCVMXVEXITEVENTINFO;
3417
3418	/**
3419	* Virtual VMCS.
3420	*
3421	* This is our custom format. Relevant fields from this VMCS will be merged into the
3422	* actual/shadow VMCS when we execute nested-guest code using hardware-assisted
3423	* VMX.
3424	*
3425	* The first 8 bytes must be in accordance with Intel spec. 24.2 "Format of the VMCS
3426	* Region".
3427	*
3428	* The offset and size of the VMCS state field (fVmcsState) is also fixed (not by
3429	* the Intel spec. but for our own requirements) as we use it to offset into guest
3430	* memory.
3431	*
3432	* Although the guest is supposed to access the VMCS only through the execution of
3433	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3434	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
3435	* for teleportation purposes, any newly added fields should be added to the
3436	* appropriate reserved sections or at the end of the structure.
3437	*
3438	* We always treat natural-width fields as 64-bit in our implementation since
3439	* it's easier, allows for teleporation in the future and does not affect guest
3440	* software.
3441	*
3442	* Note! Any fields that are added or modified here, make sure to update the
3443	* corresponding fields in IEM (g_aoffVmcsMap), the corresponding saved
3444	* state structure in CPUM (g_aVmxHwvirtVmcs) and bump the SSM version.
3445	*/
3446	#pragma pack(1)
3447	typedef struct
3448	{
3449	/** 0x0 - VMX VMCS revision identifier. */
3450	VMXVMCSREVID u32VmcsRevId;
3451	/** 0x4 - VMX-abort indicator. */
3452	VMXABORT enmVmxAbort;
3453	/** 0x8 - VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
3454	uint8_t fVmcsState;
3455	/** 0x9 - Reserved for future. */
3456	uint8_t au8Padding0[3];
3457	/** 0xc - Reserved for future. */
3458	uint32_t au32Reserved0[7];
3459
3460	/** @name 16-bit control fields.
3461	* @{ */
3462	/** 0x28 - Virtual processor ID. */
3463	uint16_t u16Vpid;
3464	/** 0x2a - Posted interrupt notify vector. */
3465	uint16_t u16PostIntNotifyVector;
3466	/** 0x2c - EPTP index. */
3467	uint16_t u16EptpIndex;
3468	/** 0x2e - Reserved for future. */
3469	uint16_t au16Reserved0[8];
3470	/** @} */
3471
3472	/** @name 16-bit Guest-state fields.
3473	* Order of [ES..GS] must match [X86_SREG_ES..X86_SREG_GS]!
3474	* @{ */
3475	/** 0x3e - Guest ES selector. */
3476	RTSEL GuestEs;
3477	/** 0x40 - Guest ES selector. */
3478	RTSEL GuestCs;
3479	/** 0x42 - Guest ES selector. */
3480	RTSEL GuestSs;
3481	/** 0x44 - Guest ES selector. */
3482	RTSEL GuestDs;
3483	/** 0x46 - Guest ES selector. */
3484	RTSEL GuestFs;
3485	/** 0x48 - Guest ES selector. */
3486	RTSEL GuestGs;
3487	/** 0x4a - Guest LDTR selector. */
3488	RTSEL GuestLdtr;
3489	/** 0x4c - Guest TR selector. */
3490	RTSEL GuestTr;
3491	/** 0x4e - Guest interrupt status (virtual-interrupt delivery). */
3492	uint16_t u16GuestIntStatus;
3493	/** 0x50 - PML index. */
3494	uint16_t u16PmlIndex;
3495	/** 0x52 - Reserved for future. */
3496	uint16_t au16Reserved1[8];
3497	/** @} */
3498
3499	/** @name 16-bit Host-state fields.
3500	* Order of [ES..GS] must match [X86_SREG_ES..X86_SREG_GS]!
3501	* @{ */
3502	/** 0x62 - Host ES selector. */
3503	RTSEL HostEs;
3504	/** 0x64 - Host CS selector. */
3505	RTSEL HostCs;
3506	/** 0x66 - Host SS selector. */
3507	RTSEL HostSs;
3508	/** 0x68 - Host DS selector. */
3509	RTSEL HostDs;
3510	/** 0x6a - Host FS selector. */
3511	RTSEL HostFs;
3512	/** 0x6c - Host GS selector. */
3513	RTSEL HostGs;
3514	/** 0x6e - Host TR selector. */
3515	RTSEL HostTr;
3516	/** 0x70 - Reserved for future. */
3517	uint16_t au16Reserved2[10];
3518	/** @} */
3519
3520	/** @name 32-bit Control fields.
3521	* @{ */
3522	/** 0x84 - Pin-based VM-execution controls. */
3523	uint32_t u32PinCtls;
3524	/** 0x88 - Processor-based VM-execution controls. */
3525	uint32_t u32ProcCtls;
3526	/** 0x8c - Exception bitmap. */
3527	uint32_t u32XcptBitmap;
3528	/** 0x90 - Page-fault exception error mask. */
3529	uint32_t u32XcptPFMask;
3530	/** 0x94 - Page-fault exception error match. */
3531	uint32_t u32XcptPFMatch;
3532	/** 0x98 - CR3-target count. */
3533	uint32_t u32Cr3TargetCount;
3534	/** 0x9c - VM-exit controls. */
3535	uint32_t u32ExitCtls;
3536	/** 0xa0 - VM-exit MSR store count. */
3537	uint32_t u32ExitMsrStoreCount;
3538	/** 0xa4 - VM-exit MSR load count. */
3539	uint32_t u32ExitMsrLoadCount;
3540	/** 0xa8 - VM-entry controls. */
3541	uint32_t u32EntryCtls;
3542	/** 0xac - VM-entry MSR load count. */
3543	uint32_t u32EntryMsrLoadCount;
3544	/** 0xb0 - VM-entry interruption information. */
3545	uint32_t u32EntryIntInfo;
3546	/** 0xb4 - VM-entry exception error code. */
3547	uint32_t u32EntryXcptErrCode;
3548	/** 0xb8 - VM-entry instruction length. */
3549	uint32_t u32EntryInstrLen;
3550	/** 0xbc - TPR-threshold. */
3551	uint32_t u32TprThreshold;
3552	/** 0xc0 - Secondary-processor based VM-execution controls. */
3553	uint32_t u32ProcCtls2;
3554	/** 0xc4 - Pause-loop exiting Gap. */
3555	uint32_t u32PleGap;
3556	/** 0xc8 - Pause-loop exiting Window. */
3557	uint32_t u32PleWindow;
3558	/** 0xcc - Reserved for future. */
3559	uint32_t au32Reserved1[8];
3560	/** @} */
3561
3562	/** @name 32-bit Read-only Data fields.
3563	* @{ */
3564	/** 0xec - VM-instruction error. */
3565	uint32_t u32RoVmInstrError;
3566	/** 0xf0 - VM-exit reason. */
3567	uint32_t u32RoExitReason;
3568	/** 0xf4 - VM-exit interruption information. */
3569	uint32_t u32RoExitIntInfo;
3570	/** 0xf8 - VM-exit interruption error code. */
3571	uint32_t u32RoExitIntErrCode;
3572	/** 0xfc - IDT-vectoring information. */
3573	uint32_t u32RoIdtVectoringInfo;
3574	/** 0x100 - IDT-vectoring error code. */
3575	uint32_t u32RoIdtVectoringErrCode;
3576	/** 0x104 - VM-exit instruction length. */
3577	uint32_t u32RoExitInstrLen;
3578	/** 0x108 - VM-exit instruction information. */
3579	uint32_t u32RoExitInstrInfo;
3580	/** 0x10c - Reserved for future. */
3581	uint32_t au32RoReserved2[8];
3582	/** @} */
3583
3584	/** @name 32-bit Guest-state fields.
3585	* Order of [ES..GS] limit & attributes must match [X86_SREG_ES..X86_SREG_GS]!
3586	* @{ */
3587	/** 0x12c - Guest ES limit. */
3588	uint32_t u32GuestEsLimit;
3589	/** 0x130 - Guest CS limit. */
3590	uint32_t u32GuestCsLimit;
3591	/** 0x134 - Guest SS limit. */
3592	uint32_t u32GuestSsLimit;
3593	/** 0x138 - Guest DS limit. */
3594	uint32_t u32GuestDsLimit;
3595	/** 0x13c - Guest FS limit. */
3596	uint32_t u32GuestFsLimit;
3597	/** 0x140 - Guest GS limit. */
3598	uint32_t u32GuestGsLimit;
3599	/** 0x144 - Guest LDTR limit. */
3600	uint32_t u32GuestLdtrLimit;
3601	/** 0x148 - Guest TR limit. */
3602	uint32_t u32GuestTrLimit;
3603	/** 0x14c - Guest GDTR limit. */
3604	uint32_t u32GuestGdtrLimit;
3605	/** 0x150 - Guest IDTR limit. */
3606	uint32_t u32GuestIdtrLimit;
3607	/** 0x154 - Guest ES attributes. */
3608	uint32_t u32GuestEsAttr;
3609	/** 0x158 - Guest CS attributes. */
3610	uint32_t u32GuestCsAttr;
3611	/** 0x15c - Guest SS attributes. */
3612	uint32_t u32GuestSsAttr;
3613	/** 0x160 - Guest DS attributes. */
3614	uint32_t u32GuestDsAttr;
3615	/** 0x164 - Guest FS attributes. */
3616	uint32_t u32GuestFsAttr;
3617	/** 0x168 - Guest GS attributes. */
3618	uint32_t u32GuestGsAttr;
3619	/** 0x16c - Guest LDTR attributes. */
3620	uint32_t u32GuestLdtrAttr;
3621	/** 0x170 - Guest TR attributes. */
3622	uint32_t u32GuestTrAttr;
3623	/** 0x174 - Guest interruptibility state. */
3624	uint32_t u32GuestIntrState;
3625	/** 0x178 - Guest activity state. */
3626	uint32_t u32GuestActivityState;
3627	/** 0x17c - Guest SMBASE. */
3628	uint32_t u32GuestSmBase;
3629	/** 0x180 - Guest SYSENTER CS. */
3630	uint32_t u32GuestSysenterCS;
3631	/** 0x184 - Preemption timer value. */
3632	uint32_t u32PreemptTimer;
3633	/** 0x188 - Reserved for future. */
3634	uint32_t au32Reserved3[8];
3635	/** @} */
3636
3637	/** @name 32-bit Host-state fields.
3638	* @{ */
3639	/** 0x1a8 - Host SYSENTER CS. */
3640	uint32_t u32HostSysenterCs;
3641	/** 0x1ac - Reserved for future. */
3642	uint32_t au32Reserved4[11];
3643	/** @} */
3644
3645	/** @name 64-bit Control fields.
3646	* @{ */
3647	/** 0x1d8 - I/O bitmap A address. */
3648	RTUINT64U u64AddrIoBitmapA;
3649	/** 0x1e0 - I/O bitmap B address. */
3650	RTUINT64U u64AddrIoBitmapB;
3651	/** 0x1e8 - MSR bitmap address. */
3652	RTUINT64U u64AddrMsrBitmap;
3653	/** 0x1f0 - VM-exit MSR-store area address. */
3654	RTUINT64U u64AddrExitMsrStore;
3655	/** 0x1f8 - VM-exit MSR-load area address. */
3656	RTUINT64U u64AddrExitMsrLoad;
3657	/** 0x200 - VM-entry MSR-load area address. */
3658	RTUINT64U u64AddrEntryMsrLoad;
3659	/** 0x208 - Executive-VMCS pointer. */
3660	RTUINT64U u64ExecVmcsPtr;
3661	/** 0x210 - PML address. */
3662	RTUINT64U u64AddrPml;
3663	/** 0x218 - TSC offset. */
3664	RTUINT64U u64TscOffset;
3665	/** 0x220 - Virtual-APIC address. */
3666	RTUINT64U u64AddrVirtApic;
3667	/** 0x228 - APIC-access address. */
3668	RTUINT64U u64AddrApicAccess;
3669	/** 0x230 - Posted-interrupt descriptor address. */
3670	RTUINT64U u64AddrPostedIntDesc;
3671	/** 0x238 - VM-functions control. */
3672	RTUINT64U u64VmFuncCtls;
3673	/** 0x240 - EPTP pointer. */
3674	RTUINT64U u64EptpPtr;
3675	/** 0x248 - EOI-exit bitmap 0. */
3676	RTUINT64U u64EoiExitBitmap0;
3677	/** 0x250 - EOI-exit bitmap 1. */
3678	RTUINT64U u64EoiExitBitmap1;
3679	/** 0x258 - EOI-exit bitmap 2. */
3680	RTUINT64U u64EoiExitBitmap2;
3681	/** 0x260 - EOI-exit bitmap 3. */
3682	RTUINT64U u64EoiExitBitmap3;
3683	/** 0x268 - EPTP-list address. */
3684	RTUINT64U u64AddrEptpList;
3685	/** 0x270 - VMREAD-bitmap address. */
3686	RTUINT64U u64AddrVmreadBitmap;
3687	/** 0x278 - VMWRITE-bitmap address. */
3688	RTUINT64U u64AddrVmwriteBitmap;
3689	/** 0x280 - Virtualization-exception information address. */
3690	RTUINT64U u64AddrXcptVeInfo;
3691	/** 0x288 - XSS-exiting bitmap. */
3692	RTUINT64U u64XssBitmap;
3693	/** 0x290 - ENCLS-exiting bitmap address. */
3694	RTUINT64U u64EnclsBitmap;
3695	/** 0x298 - Sub-page-permission-table pointer. */
3696	RTUINT64U u64SpptPtr;
3697	/** 0x2a0 - TSC multiplier. */
3698	RTUINT64U u64TscMultiplier;
3699	/** 0x2a8 - Reserved for future. */
3700	RTUINT64U au64Reserved0[15];
3701	/** @} */
3702
3703	/** @name 64-bit Read-only Data fields.
3704	* @{ */
3705	/** 0x320 - Guest-physical address. */
3706	RTUINT64U u64RoGuestPhysAddr;
3707	/** 0x328 - Reserved for future. */
3708	RTUINT64U au64Reserved1[8];
3709	/** @} */
3710
3711	/** @name 64-bit Guest-state fields.
3712	* @{ */
3713	/** 0x368 - VMCS link pointer. */
3714	RTUINT64U u64VmcsLinkPtr;
3715	/** 0x370 - Guest debug-control MSR. */
3716	RTUINT64U u64GuestDebugCtlMsr;
3717	/** 0x378 - Guest PAT MSR. */
3718	RTUINT64U u64GuestPatMsr;
3719	/** 0x380 - Guest EFER MSR. */
3720	RTUINT64U u64GuestEferMsr;
3721	/** 0x388 - Guest global performance-control MSR. */
3722	RTUINT64U u64GuestPerfGlobalCtlMsr;
3723	/** 0x390 - Guest PDPTE 0. */
3724	RTUINT64U u64GuestPdpte0;
3725	/** 0x398 - Guest PDPTE 0. */
3726	RTUINT64U u64GuestPdpte1;
3727	/** 0x3a0 - Guest PDPTE 1. */
3728	RTUINT64U u64GuestPdpte2;
3729	/** 0x3a8 - Guest PDPTE 2. */
3730	RTUINT64U u64GuestPdpte3;
3731	/** 0x3b0 - Guest Bounds-config MSR (Intel MPX - Memory Protection Extensions). */
3732	RTUINT64U u64GuestBndcfgsMsr;
3733	/** 0x3b8 - Guest RTIT control MSR (Intel Real Time Instruction Trace). */
3734	RTUINT64U u64GuestRtitCtlMsr;
3735	/** 0x3c0 - Reserved for future. */
3736	RTUINT64U au64Reserved2[15];
3737	/** @} */
3738
3739	/** @name 64-bit Host-state Fields.
3740	* @{ */
3741	/** 0x438 - Host PAT MSR. */
3742	RTUINT64U u64HostPatMsr;
3743	/** 0x440 - Host EFER MSR. */
3744	RTUINT64U u64HostEferMsr;
3745	/** 0x448 - Host global performance-control MSR. */
3746	RTUINT64U u64HostPerfGlobalCtlMsr;
3747	/** 0x450 - Reserved for future. */
3748	RTUINT64U au64Reserved3[16];
3749	/** @} */
3750
3751	/** @name Natural-width Control fields.
3752	* @{ */
3753	/** 0x4d0 - CR0 guest/host Mask. */
3754	RTUINT64U u64Cr0Mask;
3755	/** 0x4d8 - CR4 guest/host Mask. */
3756	RTUINT64U u64Cr4Mask;
3757	/** 0x4e0 - CR0 read shadow. */
3758	RTUINT64U u64Cr0ReadShadow;
3759	/** 0x4e8 - CR4 read shadow. */
3760	RTUINT64U u64Cr4ReadShadow;
3761	/** 0x4f0 - CR3-target value 0. */
3762	RTUINT64U u64Cr3Target0;
3763	/** 0x4f8 - CR3-target value 1. */
3764	RTUINT64U u64Cr3Target1;
3765	/** 0x500 - CR3-target value 2. */
3766	RTUINT64U u64Cr3Target2;
3767	/** 0x508 - CR3-target value 3. */
3768	RTUINT64U u64Cr3Target3;
3769	/** 0x510 - Reserved for future. */
3770	RTUINT64U au64Reserved4[32];
3771	/** @} */
3772
3773	/** @name Natural-width Read-only Data fields.
3774	* @{ */
3775	/** 0x610 - Exit qualification. */
3776	RTUINT64U u64RoExitQual;
3777	/** 0x618 - I/O RCX. */
3778	RTUINT64U u64RoIoRcx;
3779	/** 0x620 - I/O RSI. */
3780	RTUINT64U u64RoIoRsi;
3781	/** 0x628 - I/O RDI. */
3782	RTUINT64U u64RoIoRdi;
3783	/** 0x630 - I/O RIP. */
3784	RTUINT64U u64RoIoRip;
3785	/** 0x638 - Guest-linear address. */
3786	RTUINT64U u64RoGuestLinearAddr;
3787	/** 0x640 - Reserved for future. */
3788	RTUINT64U au64Reserved5[16];
3789	/** @} */
3790
3791	/** @name Natural-width Guest-state Fields.
3792	* Order of [ES..GS] base is important, must match X86_SREG_XXX.
3793	* @{ */
3794	/** 0x6c0 - Guest CR0. */
3795	RTUINT64U u64GuestCr0;
3796	/** 0x6c8 - Guest CR3. */
3797	RTUINT64U u64GuestCr3;
3798	/** 0x6d0 - Guest CR4. */
3799	RTUINT64U u64GuestCr4;
3800	/** 0x6d8 - Guest ES base. */
3801	RTUINT64U u64GuestEsBase;
3802	/** 0x6e0 - Guest CS base. */
3803	RTUINT64U u64GuestCsBase;
3804	/** 0x6e8 - Guest SS base. */
3805	RTUINT64U u64GuestSsBase;
3806	/** 0x6f0 - Guest DS base. */
3807	RTUINT64U u64GuestDsBase;
3808	/** 0x6f8 - Guest FS base. */
3809	RTUINT64U u64GuestFsBase;
3810	/** 0x700 - Guest GS base. */
3811	RTUINT64U u64GuestGsBase;
3812	/** 0x708 - Guest LDTR base. */
3813	RTUINT64U u64GuestLdtrBase;
3814	/** 0x710 - Guest TR base. */
3815	RTUINT64U u64GuestTrBase;
3816	/** 0x718 - Guest GDTR base. */
3817	RTUINT64U u64GuestGdtrBase;
3818	/** 0x720 - Guest IDTR base. */
3819	RTUINT64U u64GuestIdtrBase;
3820	/** 0x728 - Guest DR7. */
3821	RTUINT64U u64GuestDr7;
3822	/** 0x730 - Guest RSP. */
3823	RTUINT64U u64GuestRsp;
3824	/** 0x738 - Guest RIP. */
3825	RTUINT64U u64GuestRip;
3826	/** 0x740 - Guest RFLAGS. */
3827	RTUINT64U u64GuestRFlags;
3828	/** 0x748 - Guest pending debug exception. */
3829	RTUINT64U u64GuestPendingDbgXcpt;
3830	/** 0x750 - Guest SYSENTER ESP. */
3831	RTUINT64U u64GuestSysenterEsp;
3832	/** 0x758 - Guest SYSENTER EIP. */
3833	RTUINT64U u64GuestSysenterEip;
3834	/** 0x760 - Reserved for future. */
3835	RTUINT64U au64Reserved6[32];
3836	/** @} */
3837
3838	/** @name Natural-width Host-state fields.
3839	* @{ */
3840	/** 0x860 - Host CR0. */
3841	RTUINT64U u64HostCr0;
3842	/** 0x868 - Host CR3. */
3843	RTUINT64U u64HostCr3;
3844	/** 0x870 - Host CR4. */
3845	RTUINT64U u64HostCr4;
3846	/** 0x878 - Host FS base. */
3847	RTUINT64U u64HostFsBase;
3848	/** 0x880 - Host GS base. */
3849	RTUINT64U u64HostGsBase;
3850	/** 0x888 - Host TR base. */
3851	RTUINT64U u64HostTrBase;
3852	/** 0x890 - Host GDTR base. */
3853	RTUINT64U u64HostGdtrBase;
3854	/** 0x898 - Host IDTR base. */
3855	RTUINT64U u64HostIdtrBase;
3856	/** 0x8a0 - Host SYSENTER ESP base. */
3857	RTUINT64U u64HostSysenterEsp;
3858	/** 0x8a8 - Host SYSENTER ESP base. */
3859	RTUINT64U u64HostSysenterEip;
3860	/** 0x8b0 - Host RSP. */
3861	RTUINT64U u64HostRsp;
3862	/** 0x8b8 - Host RIP. */
3863	RTUINT64U u64HostRip;
3864	/** 0x8c0 - Reserved for future. */
3865	RTUINT64U au64Reserved7[32];
3866	/** @} */
3867
3868	/** 0x9c0 - Padding. */
3869	uint8_t abPadding[X86_PAGE_4K_SIZE - 0x9c0];
3870	} VMXVVMCS;
3871	#pragma pack()
3872	/** Pointer to the VMXVVMCS struct. */
3873	typedef VMXVVMCS *PVMXVVMCS;
3874	/** Pointer to a const VMXVVMCS struct. */
3875	typedef const VMXVVMCS *PCVMXVVMCS;
3876	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
3877	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
3878	AssertCompileMemberOffset(VMXVVMCS, enmVmxAbort, 0x004);
3879	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
3880	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x028);
3881	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x03e);
3882	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x062);
3883	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x084);
3884	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x0ec);
3885	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x12c);
3886	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x1a8);
3887	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x1d8);
3888	AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x320);
3889	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x368);
3890	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x438);
3891	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x4d0);
3892	AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x610);
3893	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x6c0);
3894	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x860);
3895
3896	/**
3897	* Virtual VMX-instruction and VM-exit diagnostics.
3898	*
3899	* These are not the same as VM instruction errors that are enumerated in the Intel
3900	* spec. These are purely internal, fine-grained definitions used for diagnostic
3901	* purposes and are not reported to guest software under the VM-instruction error
3902	* field in its VMCS.
3903	*
3904	* @note Members of this enum are used as array indices, so no gaps are allowed.
3905	* Please update g_apszVmxVDiagDesc when you add new fields to this enum.
3906	*/
3907	typedef enum
3908	{
3909	/* Internal processing errors. */
3910	kVmxVDiag_None = 0,
3911	kVmxVDiag_Ipe_1,
3912	kVmxVDiag_Ipe_2,
3913	kVmxVDiag_Ipe_3,
3914	kVmxVDiag_Ipe_4,
3915	kVmxVDiag_Ipe_5,
3916	kVmxVDiag_Ipe_6,
3917	kVmxVDiag_Ipe_7,
3918	kVmxVDiag_Ipe_8,
3919	kVmxVDiag_Ipe_9,
3920	kVmxVDiag_Ipe_10,
3921	kVmxVDiag_Ipe_11,
3922	kVmxVDiag_Ipe_12,
3923	kVmxVDiag_Ipe_13,
3924	kVmxVDiag_Ipe_14,
3925	kVmxVDiag_Ipe_15,
3926	kVmxVDiag_Ipe_16,
3927	/* VMXON. */
3928	kVmxVDiag_Vmxon_A20M,
3929	kVmxVDiag_Vmxon_Cpl,
3930	kVmxVDiag_Vmxon_Cr0Fixed0,
3931	kVmxVDiag_Vmxon_Cr0Fixed1,
3932	kVmxVDiag_Vmxon_Cr4Fixed0,
3933	kVmxVDiag_Vmxon_Cr4Fixed1,
3934	kVmxVDiag_Vmxon_Intercept,
3935	kVmxVDiag_Vmxon_LongModeCS,
3936	kVmxVDiag_Vmxon_MsrFeatCtl,
3937	kVmxVDiag_Vmxon_PtrAbnormal,
3938	kVmxVDiag_Vmxon_PtrAlign,
3939	kVmxVDiag_Vmxon_PtrMap,
3940	kVmxVDiag_Vmxon_PtrReadPhys,
3941	kVmxVDiag_Vmxon_PtrWidth,
3942	kVmxVDiag_Vmxon_RealOrV86Mode,
3943	kVmxVDiag_Vmxon_ShadowVmcs,
3944	kVmxVDiag_Vmxon_VmxAlreadyRoot,
3945	kVmxVDiag_Vmxon_Vmxe,
3946	kVmxVDiag_Vmxon_VmcsRevId,
3947	kVmxVDiag_Vmxon_VmxRootCpl,
3948	/* VMXOFF. */
3949	kVmxVDiag_Vmxoff_Cpl,
3950	kVmxVDiag_Vmxoff_Intercept,
3951	kVmxVDiag_Vmxoff_LongModeCS,
3952	kVmxVDiag_Vmxoff_RealOrV86Mode,
3953	kVmxVDiag_Vmxoff_Vmxe,
3954	kVmxVDiag_Vmxoff_VmxRoot,
3955	/* VMPTRLD. */
3956	kVmxVDiag_Vmptrld_Cpl,
3957	kVmxVDiag_Vmptrld_LongModeCS,
3958	kVmxVDiag_Vmptrld_PtrAbnormal,
3959	kVmxVDiag_Vmptrld_PtrAlign,
3960	kVmxVDiag_Vmptrld_PtrMap,
3961	kVmxVDiag_Vmptrld_PtrReadPhys,
3962	kVmxVDiag_Vmptrld_PtrVmxon,
3963	kVmxVDiag_Vmptrld_PtrWidth,
3964	kVmxVDiag_Vmptrld_RealOrV86Mode,
3965	kVmxVDiag_Vmptrld_RevPtrReadPhys,
3966	kVmxVDiag_Vmptrld_ShadowVmcs,
3967	kVmxVDiag_Vmptrld_VmcsRevId,
3968	kVmxVDiag_Vmptrld_VmxRoot,
3969	/* VMPTRST. */
3970	kVmxVDiag_Vmptrst_Cpl,
3971	kVmxVDiag_Vmptrst_LongModeCS,
3972	kVmxVDiag_Vmptrst_PtrMap,
3973	kVmxVDiag_Vmptrst_RealOrV86Mode,
3974	kVmxVDiag_Vmptrst_VmxRoot,
3975	/* VMCLEAR. */
3976	kVmxVDiag_Vmclear_Cpl,
3977	kVmxVDiag_Vmclear_LongModeCS,
3978	kVmxVDiag_Vmclear_PtrAbnormal,
3979	kVmxVDiag_Vmclear_PtrAlign,
3980	kVmxVDiag_Vmclear_PtrMap,
3981	kVmxVDiag_Vmclear_PtrReadPhys,
3982	kVmxVDiag_Vmclear_PtrVmxon,
3983	kVmxVDiag_Vmclear_PtrWidth,
3984	kVmxVDiag_Vmclear_RealOrV86Mode,
3985	kVmxVDiag_Vmclear_VmxRoot,
3986	/* VMWRITE. */
3987	kVmxVDiag_Vmwrite_Cpl,
3988	kVmxVDiag_Vmwrite_FieldInvalid,
3989	kVmxVDiag_Vmwrite_FieldRo,
3990	kVmxVDiag_Vmwrite_LinkPtrInvalid,
3991	kVmxVDiag_Vmwrite_LongModeCS,
3992	kVmxVDiag_Vmwrite_PtrInvalid,
3993	kVmxVDiag_Vmwrite_PtrMap,
3994	kVmxVDiag_Vmwrite_RealOrV86Mode,
3995	kVmxVDiag_Vmwrite_VmxRoot,
3996	/* VMREAD. */
3997	kVmxVDiag_Vmread_Cpl,
3998	kVmxVDiag_Vmread_FieldInvalid,
3999	kVmxVDiag_Vmread_LinkPtrInvalid,
4000	kVmxVDiag_Vmread_LongModeCS,
4001	kVmxVDiag_Vmread_PtrInvalid,
4002	kVmxVDiag_Vmread_PtrMap,
4003	kVmxVDiag_Vmread_RealOrV86Mode,
4004	kVmxVDiag_Vmread_VmxRoot,
4005	/* INVVPID. */
4006	kVmxVDiag_Invvpid_Cpl,
4007	kVmxVDiag_Invvpid_DescRsvd,
4008	kVmxVDiag_Invvpid_LongModeCS,
4009	kVmxVDiag_Invvpid_RealOrV86Mode,
4010	kVmxVDiag_Invvpid_TypeInvalid,
4011	kVmxVDiag_Invvpid_Type0InvalidAddr,
4012	kVmxVDiag_Invvpid_Type0InvalidVpid,
4013	kVmxVDiag_Invvpid_Type1InvalidVpid,
4014	kVmxVDiag_Invvpid_Type3InvalidVpid,
4015	kVmxVDiag_Invvpid_VmxRoot,
4016	/* VMLAUNCH/VMRESUME. */
4017	kVmxVDiag_Vmentry_AddrApicAccess,
4018	kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
4019	kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
4020	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
4021	kVmxVDiag_Vmentry_AddrExitMsrLoad,
4022	kVmxVDiag_Vmentry_AddrExitMsrStore,
4023	kVmxVDiag_Vmentry_AddrIoBitmapA,
4024	kVmxVDiag_Vmentry_AddrIoBitmapB,
4025	kVmxVDiag_Vmentry_AddrMsrBitmap,
4026	kVmxVDiag_Vmentry_AddrVirtApicPage,
4027	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
4028	kVmxVDiag_Vmentry_AddrVmreadBitmap,
4029	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
4030	kVmxVDiag_Vmentry_ApicRegVirt,
4031	kVmxVDiag_Vmentry_BlocKMovSS,
4032	kVmxVDiag_Vmentry_Cpl,
4033	kVmxVDiag_Vmentry_Cr3TargetCount,
4034	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
4035	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
4036	kVmxVDiag_Vmentry_EntryInstrLen,
4037	kVmxVDiag_Vmentry_EntryInstrLenZero,
4038	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
4039	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
4040	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
4041	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
4042	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
4043	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
4044	kVmxVDiag_Vmentry_GuestActStateHlt,
4045	kVmxVDiag_Vmentry_GuestActStateRsvd,
4046	kVmxVDiag_Vmentry_GuestActStateShutdown,
4047	kVmxVDiag_Vmentry_GuestActStateSsDpl,
4048	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
4049	kVmxVDiag_Vmentry_GuestCr0Fixed0,
4050	kVmxVDiag_Vmentry_GuestCr0Fixed1,
4051	kVmxVDiag_Vmentry_GuestCr0PgPe,
4052	kVmxVDiag_Vmentry_GuestCr3,
4053	kVmxVDiag_Vmentry_GuestCr4Fixed0,
4054	kVmxVDiag_Vmentry_GuestCr4Fixed1,
4055	kVmxVDiag_Vmentry_GuestDebugCtl,
4056	kVmxVDiag_Vmentry_GuestDr7,
4057	kVmxVDiag_Vmentry_GuestEferMsr,
4058	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
4059	kVmxVDiag_Vmentry_GuestGdtrBase,
4060	kVmxVDiag_Vmentry_GuestGdtrLimit,
4061	kVmxVDiag_Vmentry_GuestIdtrBase,
4062	kVmxVDiag_Vmentry_GuestIdtrLimit,
4063	kVmxVDiag_Vmentry_GuestIntStateEnclave,
4064	kVmxVDiag_Vmentry_GuestIntStateExtInt,
4065	kVmxVDiag_Vmentry_GuestIntStateNmi,
4066	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
4067	kVmxVDiag_Vmentry_GuestIntStateRsvd,
4068	kVmxVDiag_Vmentry_GuestIntStateSmi,
4069	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
4070	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
4071	kVmxVDiag_Vmentry_GuestPae,
4072	kVmxVDiag_Vmentry_GuestPatMsr,
4073	kVmxVDiag_Vmentry_GuestPcide,
4074	kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys,
4075	kVmxVDiag_Vmentry_GuestPdpte0Rsvd,
4076	kVmxVDiag_Vmentry_GuestPdpte1Rsvd,
4077	kVmxVDiag_Vmentry_GuestPdpte2Rsvd,
4078	kVmxVDiag_Vmentry_GuestPdpte3Rsvd,
4079	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
4080	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
4081	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
4082	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
4083	kVmxVDiag_Vmentry_GuestRip,
4084	kVmxVDiag_Vmentry_GuestRipRsvd,
4085	kVmxVDiag_Vmentry_GuestRFlagsIf,
4086	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
4087	kVmxVDiag_Vmentry_GuestRFlagsVm,
4088	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
4089	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
4090	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
4091	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
4092	kVmxVDiag_Vmentry_GuestSegAttrCsType,
4093	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
4094	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
4095	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
4096	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
4097	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
4098	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
4099	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
4100	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
4101	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
4102	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
4103	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
4104	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
4105	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
4106	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
4107	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
4108	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
4109	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
4110	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
4111	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
4112	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
4113	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
4114	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
4115	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
4116	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
4117	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
4118	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
4119	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
4120	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
4121	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
4122	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
4123	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
4124	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
4125	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
4126	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
4127	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
4128	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
4129	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
4130	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
4131	kVmxVDiag_Vmentry_GuestSegAttrSsType,
4132	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
4133	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
4134	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
4135	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
4136	kVmxVDiag_Vmentry_GuestSegAttrTrType,
4137	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
4138	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
4139	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
4140	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
4141	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
4142	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
4143	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
4144	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
4145	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
4146	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
4147	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
4148	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
4149	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
4150	kVmxVDiag_Vmentry_GuestSegBaseCs,
4151	kVmxVDiag_Vmentry_GuestSegBaseDs,
4152	kVmxVDiag_Vmentry_GuestSegBaseEs,
4153	kVmxVDiag_Vmentry_GuestSegBaseFs,
4154	kVmxVDiag_Vmentry_GuestSegBaseGs,
4155	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
4156	kVmxVDiag_Vmentry_GuestSegBaseSs,
4157	kVmxVDiag_Vmentry_GuestSegBaseTr,
4158	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
4159	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
4160	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
4161	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
4162	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
4163	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
4164	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
4165	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
4166	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
4167	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
4168	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
4169	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
4170	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
4171	kVmxVDiag_Vmentry_GuestSegSelLdtr,
4172	kVmxVDiag_Vmentry_GuestSegSelTr,
4173	kVmxVDiag_Vmentry_GuestSysenterEspEip,
4174	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
4175	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
4176	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
4177	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
4178	kVmxVDiag_Vmentry_HostCr0Fixed0,
4179	kVmxVDiag_Vmentry_HostCr0Fixed1,
4180	kVmxVDiag_Vmentry_HostCr3,
4181	kVmxVDiag_Vmentry_HostCr4Fixed0,
4182	kVmxVDiag_Vmentry_HostCr4Fixed1,
4183	kVmxVDiag_Vmentry_HostCr4Pae,
4184	kVmxVDiag_Vmentry_HostCr4Pcide,
4185	kVmxVDiag_Vmentry_HostCsTr,
4186	kVmxVDiag_Vmentry_HostEferMsr,
4187	kVmxVDiag_Vmentry_HostEferMsrRsvd,
4188	kVmxVDiag_Vmentry_HostGuestLongMode,
4189	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4190	kVmxVDiag_Vmentry_HostLongMode,
4191	kVmxVDiag_Vmentry_HostPatMsr,
4192	kVmxVDiag_Vmentry_HostRip,
4193	kVmxVDiag_Vmentry_HostRipRsvd,
4194	kVmxVDiag_Vmentry_HostSel,
4195	kVmxVDiag_Vmentry_HostSegBase,
4196	kVmxVDiag_Vmentry_HostSs,
4197	kVmxVDiag_Vmentry_HostSysenterEspEip,
4198	kVmxVDiag_Vmentry_LongModeCS,
4199	kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4200	kVmxVDiag_Vmentry_MsrLoad,
4201	kVmxVDiag_Vmentry_MsrLoadCount,
4202	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4203	kVmxVDiag_Vmentry_MsrLoadRing3,
4204	kVmxVDiag_Vmentry_MsrLoadRsvd,
4205	kVmxVDiag_Vmentry_NmiWindowExit,
4206	kVmxVDiag_Vmentry_PinCtlsAllowed1,
4207	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4208	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4209	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4210	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4211	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4212	kVmxVDiag_Vmentry_PtrInvalid,
4213	kVmxVDiag_Vmentry_PtrShadowVmcs,
4214	kVmxVDiag_Vmentry_RealOrV86Mode,
4215	kVmxVDiag_Vmentry_SavePreemptTimer,
4216	kVmxVDiag_Vmentry_TprThresholdRsvd,
4217	kVmxVDiag_Vmentry_TprThresholdVTpr,
4218	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4219	kVmxVDiag_Vmentry_VirtIntDelivery,
4220	kVmxVDiag_Vmentry_VirtNmi,
4221	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4222	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4223	kVmxVDiag_Vmentry_VmcsClear,
4224	kVmxVDiag_Vmentry_VmcsLaunch,
4225	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4226	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4227	kVmxVDiag_Vmentry_VmxRoot,
4228	kVmxVDiag_Vmentry_Vpid,
4229	kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys,
4230	kVmxVDiag_Vmexit_HostPdpte0Rsvd,
4231	kVmxVDiag_Vmexit_HostPdpte1Rsvd,
4232	kVmxVDiag_Vmexit_HostPdpte2Rsvd,
4233	kVmxVDiag_Vmexit_HostPdpte3Rsvd,
4234	kVmxVDiag_Vmexit_MsrLoad,
4235	kVmxVDiag_Vmexit_MsrLoadCount,
4236	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4237	kVmxVDiag_Vmexit_MsrLoadRing3,
4238	kVmxVDiag_Vmexit_MsrLoadRsvd,
4239	kVmxVDiag_Vmexit_MsrStore,
4240	kVmxVDiag_Vmexit_MsrStoreCount,
4241	kVmxVDiag_Vmexit_MsrStorePtrReadPhys,
4242	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4243	kVmxVDiag_Vmexit_MsrStoreRing3,
4244	kVmxVDiag_Vmexit_MsrStoreRsvd,
4245	/* Last member for determining array index limit. */
4246	kVmxVDiag_End
4247	} VMXVDIAG;
4248	AssertCompileSize(VMXVDIAG, 4);
4249
4250	/** @} */
4251
4252	/** @} */
4253
4254	#endif /* !VBOX_INCLUDED_vmm_hm_vmx_h */
4255

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 79221

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