hm_vmx.h@ 82573

Last change on this file since 82573 was 82573, checked in by vboxsync, 5 years ago
hm_vmx.h: Important comment to update CPUMIsGuestVmxVmcsFieldValid when adding new VMCS fields to VMXVVMCS.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_hm_vmx_h
27	#define VBOX_INCLUDED_vmm_hm_vmx_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <iprt/x86.h>
34	#include <iprt/assertcompile.h>
35
36
37	/** @defgroup grp_hm_vmx VMX Types and Definitions
38	* @ingroup grp_hm
39	* @{
40	*/
41
42	/** @name Host-state restoration flags.
43	* @note If you change these values don't forget to update the assembly
44	* defines as well!
45	* @{
46	*/
47	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
48	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
49	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
50	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
51	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
52	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
53	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
54	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
55	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
56	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
57	/** @} */
58
59	/**
60	* Host-state restoration structure.
61	* This holds host-state fields that require manual restoration.
62	* Assembly version found in hm_vmx.mac (should be automatically verified).
63	*/
64	typedef struct VMXRESTOREHOST
65	{
66	RTSEL uHostSelDS; /* 0x00 */
67	RTSEL uHostSelES; /* 0x02 */
68	RTSEL uHostSelFS; /* 0x04 */
69	RTSEL uHostSelGS; /* 0x06 */
70	RTSEL uHostSelTR; /* 0x08 */
71	uint8_t abPadding0[4];
72	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
73	uint8_t abPadding1[6];
74	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
75	uint8_t abPadding2[6];
76	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
77	uint64_t uHostFSBase; /* 0x38 */
78	uint64_t uHostGSBase; /* 0x40 */
79	} VMXRESTOREHOST;
80	/** Pointer to VMXRESTOREHOST. */
81	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
82	AssertCompileSize(X86XDTR64, 10);
83	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
84	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
85	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
86	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
87	AssertCompileSize(VMXRESTOREHOST, 72);
88	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
89
90	/** @name Host-state MSR lazy-restoration flags.
91	* @{
92	*/
93	/** The host MSRs have been saved. */
94	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
95	/** The guest MSRs are loaded and in effect. */
96	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
97	/** @} */
98
99	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
100	* UFC = Unsupported Feature Combination.
101	* @{
102	*/
103	/** Unsupported pin-based VM-execution controls combo. */
104	#define VMX_UFC_CTRL_PIN_EXEC 1
105	/** Unsupported processor-based VM-execution controls combo. */
106	#define VMX_UFC_CTRL_PROC_EXEC 2
107	/** Unsupported move debug register VM-exit combo. */
108	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
109	/** Unsupported VM-entry controls combo. */
110	#define VMX_UFC_CTRL_ENTRY 4
111	/** Unsupported VM-exit controls combo. */
112	#define VMX_UFC_CTRL_EXIT 5
113	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
114	* for storing host MSRs. */
115	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
116	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
117	* for storing guest MSRs. */
118	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
119	/** Invalid VMCS size. */
120	#define VMX_UFC_INVALID_VMCS_SIZE 8
121	/** Unsupported secondary processor-based VM-execution controls combo. */
122	#define VMX_UFC_CTRL_PROC_EXEC2 9
123	/** Invalid unrestricted-guest execution controls combo. */
124	#define VMX_UFC_INVALID_UX_COMBO 10
125	/** EPT flush type not supported. */
126	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
127	/** EPT paging structure memory type is not write-back. */
128	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
129	/** EPT requires INVEPT instr. support but it's not available. */
130	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
131	/** EPT requires page-walk length of 4. */
132	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
133	/** VMX VMWRITE all feature exposed to the guest but not supported on host. */
134	#define VMX_UFC_GST_HOST_VMWRITE_ALL 15
135	/** @} */
136
137	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
138	* VCI = VMCS-field Cache Invalid.
139	* @{
140	*/
141	/** Cache of VM-entry controls invalid. */
142	#define VMX_VCI_CTRL_ENTRY 300
143	/** Cache of VM-exit controls invalid. */
144	#define VMX_VCI_CTRL_EXIT 301
145	/** Cache of pin-based VM-execution controls invalid. */
146	#define VMX_VCI_CTRL_PIN_EXEC 302
147	/** Cache of processor-based VM-execution controls invalid. */
148	#define VMX_VCI_CTRL_PROC_EXEC 303
149	/** Cache of secondary processor-based VM-execution controls invalid. */
150	#define VMX_VCI_CTRL_PROC_EXEC2 304
151	/** Cache of exception bitmap invalid. */
152	#define VMX_VCI_CTRL_XCPT_BITMAP 305
153	/** Cache of TSC offset invalid. */
154	#define VMX_VCI_CTRL_TSC_OFFSET 306
155	/** @} */
156
157	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
158	* IGS = Invalid Guest State.
159	* @{
160	*/
161	/** An error occurred while checking invalid-guest-state. */
162	#define VMX_IGS_ERROR 500
163	/** The invalid guest-state checks did not find any reason why. */
164	#define VMX_IGS_REASON_NOT_FOUND 501
165	/** CR0 fixed1 bits invalid. */
166	#define VMX_IGS_CR0_FIXED1 502
167	/** CR0 fixed0 bits invalid. */
168	#define VMX_IGS_CR0_FIXED0 503
169	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
170	#define VMX_IGS_CR0_PG_PE_COMBO 504
171	/** CR4 fixed1 bits invalid. */
172	#define VMX_IGS_CR4_FIXED1 505
173	/** CR4 fixed0 bits invalid. */
174	#define VMX_IGS_CR4_FIXED0 506
175	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
176	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
177	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
178	/** CR0.PG not set for long-mode when not using unrestricted guest. */
179	#define VMX_IGS_CR0_PG_LONGMODE 508
180	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
181	#define VMX_IGS_CR4_PAE_LONGMODE 509
182	/** CR4.PCIDE set for 32-bit guest. */
183	#define VMX_IGS_CR4_PCIDE 510
184	/** VMCS' DR7 reserved bits not set to 0. */
185	#define VMX_IGS_DR7_RESERVED 511
186	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
187	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
188	/** VMCS' EFER MSR reserved bits not set to 0. */
189	#define VMX_IGS_EFER_MSR_RESERVED 513
190	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
191	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
192	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
193	* without unrestricted guest. */
194	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
195	/** CS.Attr.P bit invalid. */
196	#define VMX_IGS_CS_ATTR_P_INVALID 516
197	/** CS.Attr reserved bits not set to 0. */
198	#define VMX_IGS_CS_ATTR_RESERVED 517
199	/** CS.Attr.G bit invalid. */
200	#define VMX_IGS_CS_ATTR_G_INVALID 518
201	/** CS is unusable. */
202	#define VMX_IGS_CS_ATTR_UNUSABLE 519
203	/** CS and SS DPL unequal. */
204	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
205	/** CS and SS DPL mismatch. */
206	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
207	/** CS Attr.Type invalid. */
208	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
209	/** CS and SS RPL unequal. */
210	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
211	/** SS.Attr.DPL and SS RPL unequal. */
212	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
213	/** SS.Attr.DPL invalid for segment type. */
214	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
215	/** SS.Attr.Type invalid. */
216	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
217	/** SS.Attr.P bit invalid. */
218	#define VMX_IGS_SS_ATTR_P_INVALID 527
219	/** SS.Attr reserved bits not set to 0. */
220	#define VMX_IGS_SS_ATTR_RESERVED 528
221	/** SS.Attr.G bit invalid. */
222	#define VMX_IGS_SS_ATTR_G_INVALID 529
223	/** DS.Attr.A bit invalid. */
224	#define VMX_IGS_DS_ATTR_A_INVALID 530
225	/** DS.Attr.P bit invalid. */
226	#define VMX_IGS_DS_ATTR_P_INVALID 531
227	/** DS.Attr.DPL and DS RPL unequal. */
228	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
229	/** DS.Attr reserved bits not set to 0. */
230	#define VMX_IGS_DS_ATTR_RESERVED 533
231	/** DS.Attr.G bit invalid. */
232	#define VMX_IGS_DS_ATTR_G_INVALID 534
233	/** DS.Attr.Type invalid. */
234	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
235	/** ES.Attr.A bit invalid. */
236	#define VMX_IGS_ES_ATTR_A_INVALID 536
237	/** ES.Attr.P bit invalid. */
238	#define VMX_IGS_ES_ATTR_P_INVALID 537
239	/** ES.Attr.DPL and DS RPL unequal. */
240	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
241	/** ES.Attr reserved bits not set to 0. */
242	#define VMX_IGS_ES_ATTR_RESERVED 539
243	/** ES.Attr.G bit invalid. */
244	#define VMX_IGS_ES_ATTR_G_INVALID 540
245	/** ES.Attr.Type invalid. */
246	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
247	/** FS.Attr.A bit invalid. */
248	#define VMX_IGS_FS_ATTR_A_INVALID 542
249	/** FS.Attr.P bit invalid. */
250	#define VMX_IGS_FS_ATTR_P_INVALID 543
251	/** FS.Attr.DPL and DS RPL unequal. */
252	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
253	/** FS.Attr reserved bits not set to 0. */
254	#define VMX_IGS_FS_ATTR_RESERVED 545
255	/** FS.Attr.G bit invalid. */
256	#define VMX_IGS_FS_ATTR_G_INVALID 546
257	/** FS.Attr.Type invalid. */
258	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
259	/** GS.Attr.A bit invalid. */
260	#define VMX_IGS_GS_ATTR_A_INVALID 548
261	/** GS.Attr.P bit invalid. */
262	#define VMX_IGS_GS_ATTR_P_INVALID 549
263	/** GS.Attr.DPL and DS RPL unequal. */
264	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
265	/** GS.Attr reserved bits not set to 0. */
266	#define VMX_IGS_GS_ATTR_RESERVED 551
267	/** GS.Attr.G bit invalid. */
268	#define VMX_IGS_GS_ATTR_G_INVALID 552
269	/** GS.Attr.Type invalid. */
270	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
271	/** V86 mode CS.Base invalid. */
272	#define VMX_IGS_V86_CS_BASE_INVALID 554
273	/** V86 mode CS.Limit invalid. */
274	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
275	/** V86 mode CS.Attr invalid. */
276	#define VMX_IGS_V86_CS_ATTR_INVALID 556
277	/** V86 mode SS.Base invalid. */
278	#define VMX_IGS_V86_SS_BASE_INVALID 557
279	/** V86 mode SS.Limit invalid. */
280	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
281	/** V86 mode SS.Attr invalid. */
282	#define VMX_IGS_V86_SS_ATTR_INVALID 559
283	/** V86 mode DS.Base invalid. */
284	#define VMX_IGS_V86_DS_BASE_INVALID 560
285	/** V86 mode DS.Limit invalid. */
286	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
287	/** V86 mode DS.Attr invalid. */
288	#define VMX_IGS_V86_DS_ATTR_INVALID 562
289	/** V86 mode ES.Base invalid. */
290	#define VMX_IGS_V86_ES_BASE_INVALID 563
291	/** V86 mode ES.Limit invalid. */
292	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
293	/** V86 mode ES.Attr invalid. */
294	#define VMX_IGS_V86_ES_ATTR_INVALID 565
295	/** V86 mode FS.Base invalid. */
296	#define VMX_IGS_V86_FS_BASE_INVALID 566
297	/** V86 mode FS.Limit invalid. */
298	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
299	/** V86 mode FS.Attr invalid. */
300	#define VMX_IGS_V86_FS_ATTR_INVALID 568
301	/** V86 mode GS.Base invalid. */
302	#define VMX_IGS_V86_GS_BASE_INVALID 569
303	/** V86 mode GS.Limit invalid. */
304	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
305	/** V86 mode GS.Attr invalid. */
306	#define VMX_IGS_V86_GS_ATTR_INVALID 571
307	/** Longmode CS.Base invalid. */
308	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
309	/** Longmode SS.Base invalid. */
310	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
311	/** Longmode DS.Base invalid. */
312	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
313	/** Longmode ES.Base invalid. */
314	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
315	/** SYSENTER ESP is not canonical. */
316	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
317	/** SYSENTER EIP is not canonical. */
318	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
319	/** PAT MSR invalid. */
320	#define VMX_IGS_PAT_MSR_INVALID 578
321	/** PAT MSR reserved bits not set to 0. */
322	#define VMX_IGS_PAT_MSR_RESERVED 579
323	/** GDTR.Base is not canonical. */
324	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
325	/** IDTR.Base is not canonical. */
326	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
327	/** GDTR.Limit invalid. */
328	#define VMX_IGS_GDTR_LIMIT_INVALID 582
329	/** IDTR.Limit invalid. */
330	#define VMX_IGS_IDTR_LIMIT_INVALID 583
331	/** Longmode RIP is invalid. */
332	#define VMX_IGS_LONGMODE_RIP_INVALID 584
333	/** RFLAGS reserved bits not set to 0. */
334	#define VMX_IGS_RFLAGS_RESERVED 585
335	/** RFLAGS RA1 reserved bits not set to 1. */
336	#define VMX_IGS_RFLAGS_RESERVED1 586
337	/** RFLAGS.VM (V86 mode) invalid. */
338	#define VMX_IGS_RFLAGS_VM_INVALID 587
339	/** RFLAGS.IF invalid. */
340	#define VMX_IGS_RFLAGS_IF_INVALID 588
341	/** Activity state invalid. */
342	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
343	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
344	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
345	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
346	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
347	/** Activity state SIPI WAIT invalid. */
348	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
349	/** Interruptibility state reserved bits not set to 0. */
350	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
351	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
352	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
353	/** Interruptibility state block-by-STI invalid for EFLAGS. */
354	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
355	/** Interruptibility state invalid while trying to deliver external
356	* interrupt. */
357	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
358	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
359	* NMI. */
360	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
361	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
362	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
363	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
364	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
365	/** Interruptibility state block-by-STI (maybe) invalid when trying to
366	* deliver an NMI. */
367	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
368	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
369	* active. */
370	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
371	/** Pending debug exceptions reserved bits not set to 0. */
372	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
373	/** Longmode pending debug exceptions reserved bits not set to 0. */
374	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
375	/** Pending debug exceptions.BS bit is not set when it should be. */
376	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
377	/** Pending debug exceptions.BS bit is not clear when it should be. */
378	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
379	/** VMCS link pointer reserved bits not set to 0. */
380	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
381	/** TR cannot index into LDT, TI bit MBZ. */
382	#define VMX_IGS_TR_TI_INVALID 607
383	/** LDTR cannot index into LDT. TI bit MBZ. */
384	#define VMX_IGS_LDTR_TI_INVALID 608
385	/** TR.Base is not canonical. */
386	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
387	/** FS.Base is not canonical. */
388	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
389	/** GS.Base is not canonical. */
390	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
391	/** LDTR.Base is not canonical. */
392	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
393	/** TR is unusable. */
394	#define VMX_IGS_TR_ATTR_UNUSABLE 613
395	/** TR.Attr.S bit invalid. */
396	#define VMX_IGS_TR_ATTR_S_INVALID 614
397	/** TR is not present. */
398	#define VMX_IGS_TR_ATTR_P_INVALID 615
399	/** TR.Attr reserved bits not set to 0. */
400	#define VMX_IGS_TR_ATTR_RESERVED 616
401	/** TR.Attr.G bit invalid. */
402	#define VMX_IGS_TR_ATTR_G_INVALID 617
403	/** Longmode TR.Attr.Type invalid. */
404	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
405	/** TR.Attr.Type invalid. */
406	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
407	/** CS.Attr.S invalid. */
408	#define VMX_IGS_CS_ATTR_S_INVALID 620
409	/** CS.Attr.DPL invalid. */
410	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
411	/** PAE PDPTE reserved bits not set to 0. */
412	#define VMX_IGS_PAE_PDPTE_RESERVED 623
413	/** VMCS link pointer does not point to a shadow VMCS. */
414	#define VMX_IGS_VMCS_LINK_PTR_NOT_SHADOW 624
415	/** VMCS link pointer to a shadow VMCS with invalid VMCS revision identifer. */
416	#define VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID 625
417	/** @} */
418
419	/** @name VMX VMCS-Read cache indices.
420	* @{
421	*/
422	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
423	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
424	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
425	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
426	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
427	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
428	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
429	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
430	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
431	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
432	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
433	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
434	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
435	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
436	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
437	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
438	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
439	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
440	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
441	/** @} */
442
443	/** @name VMX EPT paging structures
444	* @{
445	*/
446
447	/**
448	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
449	*/
450	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
451
452	/**
453	* EPT Page Directory Pointer Entry. Bit view.
454	* In accordance with the VT-x spec.
455	*
456	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
457	* this did cause trouble with one compiler/version).
458	*/
459	typedef struct EPTPML4EBITS
460	{
461	/** Present bit. */
462	RT_GCC_EXTENSION uint64_t u1Present : 1;
463	/** Writable bit. */
464	RT_GCC_EXTENSION uint64_t u1Write : 1;
465	/** Executable bit. */
466	RT_GCC_EXTENSION uint64_t u1Execute : 1;
467	/** Reserved (must be 0). */
468	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
469	/** Available for software. */
470	RT_GCC_EXTENSION uint64_t u4Available : 4;
471	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
472	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
473	/** Available for software. */
474	RT_GCC_EXTENSION uint64_t u12Available : 12;
475	} EPTPML4EBITS;
476	AssertCompileSize(EPTPML4EBITS, 8);
477
478	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
479	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
480	/** The page shift to get the PML4 index. */
481	#define EPT_PML4_SHIFT X86_PML4_SHIFT
482	/** The PML4 index mask (apply to a shifted page address). */
483	#define EPT_PML4_MASK X86_PML4_MASK
484
485	/**
486	* EPT PML4E.
487	* In accordance with the VT-x spec.
488	*/
489	typedef union EPTPML4E
490	{
491	/** Normal view. */
492	EPTPML4EBITS n;
493	/** Unsigned integer view. */
494	X86PGPAEUINT u;
495	/** 64 bit unsigned integer view. */
496	uint64_t au64[1];
497	/** 32 bit unsigned integer view. */
498	uint32_t au32[2];
499	} EPTPML4E;
500	AssertCompileSize(EPTPML4E, 8);
501	/** Pointer to a PML4 table entry. */
502	typedef EPTPML4E *PEPTPML4E;
503	/** Pointer to a const PML4 table entry. */
504	typedef const EPTPML4E *PCEPTPML4E;
505
506	/**
507	* EPT PML4 Table.
508	* In accordance with the VT-x spec.
509	*/
510	typedef struct EPTPML4
511	{
512	EPTPML4E a[EPT_PG_ENTRIES];
513	} EPTPML4;
514	AssertCompileSize(EPTPML4, 0x1000);
515	/** Pointer to an EPT PML4 Table. */
516	typedef EPTPML4 *PEPTPML4;
517	/** Pointer to a const EPT PML4 Table. */
518	typedef const EPTPML4 *PCEPTPML4;
519
520	/**
521	* EPT Page Directory Pointer Entry. Bit view.
522	* In accordance with the VT-x spec.
523	*/
524	typedef struct EPTPDPTEBITS
525	{
526	/** Present bit. */
527	RT_GCC_EXTENSION uint64_t u1Present : 1;
528	/** Writable bit. */
529	RT_GCC_EXTENSION uint64_t u1Write : 1;
530	/** Executable bit. */
531	RT_GCC_EXTENSION uint64_t u1Execute : 1;
532	/** Reserved (must be 0). */
533	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
534	/** Available for software. */
535	RT_GCC_EXTENSION uint64_t u4Available : 4;
536	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
537	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
538	/** Available for software. */
539	RT_GCC_EXTENSION uint64_t u12Available : 12;
540	} EPTPDPTEBITS;
541	AssertCompileSize(EPTPDPTEBITS, 8);
542
543	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
544	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
545	/** The page shift to get the PDPT index. */
546	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
547	/** The PDPT index mask (apply to a shifted page address). */
548	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
549
550	/**
551	* EPT Page Directory Pointer.
552	* In accordance with the VT-x spec.
553	*/
554	typedef union EPTPDPTE
555	{
556	/** Normal view. */
557	EPTPDPTEBITS n;
558	/** Unsigned integer view. */
559	X86PGPAEUINT u;
560	/** 64 bit unsigned integer view. */
561	uint64_t au64[1];
562	/** 32 bit unsigned integer view. */
563	uint32_t au32[2];
564	} EPTPDPTE;
565	AssertCompileSize(EPTPDPTE, 8);
566	/** Pointer to an EPT Page Directory Pointer Entry. */
567	typedef EPTPDPTE *PEPTPDPTE;
568	/** Pointer to a const EPT Page Directory Pointer Entry. */
569	typedef const EPTPDPTE *PCEPTPDPTE;
570
571	/**
572	* EPT Page Directory Pointer Table.
573	* In accordance with the VT-x spec.
574	*/
575	typedef struct EPTPDPT
576	{
577	EPTPDPTE a[EPT_PG_ENTRIES];
578	} EPTPDPT;
579	AssertCompileSize(EPTPDPT, 0x1000);
580	/** Pointer to an EPT Page Directory Pointer Table. */
581	typedef EPTPDPT *PEPTPDPT;
582	/** Pointer to a const EPT Page Directory Pointer Table. */
583	typedef const EPTPDPT *PCEPTPDPT;
584
585	/**
586	* EPT Page Directory Table Entry. Bit view.
587	* In accordance with the VT-x spec.
588	*/
589	typedef struct EPTPDEBITS
590	{
591	/** Present bit. */
592	RT_GCC_EXTENSION uint64_t u1Present : 1;
593	/** Writable bit. */
594	RT_GCC_EXTENSION uint64_t u1Write : 1;
595	/** Executable bit. */
596	RT_GCC_EXTENSION uint64_t u1Execute : 1;
597	/** Reserved (must be 0). */
598	RT_GCC_EXTENSION uint64_t u4Reserved : 4;
599	/** Big page (must be 0 here). */
600	RT_GCC_EXTENSION uint64_t u1Size : 1;
601	/** Available for software. */
602	RT_GCC_EXTENSION uint64_t u4Available : 4;
603	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
604	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
605	/** Available for software. */
606	RT_GCC_EXTENSION uint64_t u12Available : 12;
607	} EPTPDEBITS;
608	AssertCompileSize(EPTPDEBITS, 8);
609
610	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
611	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
612	/** The page shift to get the PD index. */
613	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
614	/** The PD index mask (apply to a shifted page address). */
615	#define EPT_PD_MASK X86_PD_PAE_MASK
616
617	/**
618	* EPT 2MB Page Directory Table Entry. Bit view.
619	* In accordance with the VT-x spec.
620	*/
621	typedef struct EPTPDE2MBITS
622	{
623	/** Present bit. */
624	RT_GCC_EXTENSION uint64_t u1Present : 1;
625	/** Writable bit. */
626	RT_GCC_EXTENSION uint64_t u1Write : 1;
627	/** Executable bit. */
628	RT_GCC_EXTENSION uint64_t u1Execute : 1;
629	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
630	RT_GCC_EXTENSION uint64_t u3EMT : 3;
631	/** Ignore PAT memory type */
632	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
633	/** Big page (must be 1 here). */
634	RT_GCC_EXTENSION uint64_t u1Size : 1;
635	/** Available for software. */
636	RT_GCC_EXTENSION uint64_t u4Available : 4;
637	/** Reserved (must be 0). */
638	RT_GCC_EXTENSION uint64_t u9Reserved : 9;
639	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
640	RT_GCC_EXTENSION uint64_t u31PhysAddr : 31;
641	/** Available for software. */
642	RT_GCC_EXTENSION uint64_t u12Available : 12;
643	} EPTPDE2MBITS;
644	AssertCompileSize(EPTPDE2MBITS, 8);
645
646	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
647	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
648
649	/**
650	* EPT Page Directory Table Entry.
651	* In accordance with the VT-x spec.
652	*/
653	typedef union EPTPDE
654	{
655	/** Normal view. */
656	EPTPDEBITS n;
657	/** 2MB view (big). */
658	EPTPDE2MBITS b;
659	/** Unsigned integer view. */
660	X86PGPAEUINT u;
661	/** 64 bit unsigned integer view. */
662	uint64_t au64[1];
663	/** 32 bit unsigned integer view. */
664	uint32_t au32[2];
665	} EPTPDE;
666	AssertCompileSize(EPTPDE, 8);
667	/** Pointer to an EPT Page Directory Table Entry. */
668	typedef EPTPDE *PEPTPDE;
669	/** Pointer to a const EPT Page Directory Table Entry. */
670	typedef const EPTPDE *PCEPTPDE;
671
672	/**
673	* EPT Page Directory Table.
674	* In accordance with the VT-x spec.
675	*/
676	typedef struct EPTPD
677	{
678	EPTPDE a[EPT_PG_ENTRIES];
679	} EPTPD;
680	AssertCompileSize(EPTPD, 0x1000);
681	/** Pointer to an EPT Page Directory Table. */
682	typedef EPTPD *PEPTPD;
683	/** Pointer to a const EPT Page Directory Table. */
684	typedef const EPTPD *PCEPTPD;
685
686	/**
687	* EPT Page Table Entry. Bit view.
688	* In accordance with the VT-x spec.
689	*/
690	typedef struct EPTPTEBITS
691	{
692	/** 0 - Present bit.
693	* @remarks This is a convenience "misnomer". The bit actually indicates read access
694	* and the CPU will consider an entry with any of the first three bits set
695	* as present. Since all our valid entries will have this bit set, it can
696	* be used as a present indicator and allow some code sharing. */
697	RT_GCC_EXTENSION uint64_t u1Present : 1;
698	/** 1 - Writable bit. */
699	RT_GCC_EXTENSION uint64_t u1Write : 1;
700	/** 2 - Executable bit. */
701	RT_GCC_EXTENSION uint64_t u1Execute : 1;
702	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
703	RT_GCC_EXTENSION uint64_t u3EMT : 3;
704	/** 6 - Ignore PAT memory type */
705	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
706	/** 11:7 - Available for software. */
707	RT_GCC_EXTENSION uint64_t u5Available : 5;
708	/** 51:12 - Physical address of page. Restricted by maximum physical
709	* address width of the cpu. */
710	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
711	/** 63:52 - Available for software. */
712	RT_GCC_EXTENSION uint64_t u12Available : 12;
713	} EPTPTEBITS;
714	AssertCompileSize(EPTPTEBITS, 8);
715
716	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
717	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
718	/** The page shift to get the EPT PTE index. */
719	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
720	/** The EPT PT index mask (apply to a shifted page address). */
721	#define EPT_PT_MASK X86_PT_PAE_MASK
722
723	/**
724	* EPT Page Table Entry.
725	* In accordance with the VT-x spec.
726	*/
727	typedef union EPTPTE
728	{
729	/** Normal view. */
730	EPTPTEBITS n;
731	/** Unsigned integer view. */
732	X86PGPAEUINT u;
733	/** 64 bit unsigned integer view. */
734	uint64_t au64[1];
735	/** 32 bit unsigned integer view. */
736	uint32_t au32[2];
737	} EPTPTE;
738	AssertCompileSize(EPTPTE, 8);
739	/** Pointer to an EPT Page Directory Table Entry. */
740	typedef EPTPTE *PEPTPTE;
741	/** Pointer to a const EPT Page Directory Table Entry. */
742	typedef const EPTPTE *PCEPTPTE;
743
744	/**
745	* EPT Page Table.
746	* In accordance with the VT-x spec.
747	*/
748	typedef struct EPTPT
749	{
750	EPTPTE a[EPT_PG_ENTRIES];
751	} EPTPT;
752	AssertCompileSize(EPTPT, 0x1000);
753	/** Pointer to an extended page table. */
754	typedef EPTPT *PEPTPT;
755	/** Pointer to a const extended table. */
756	typedef const EPTPT *PCEPTPT;
757
758	/** @} */
759
760	/**
761	* VMX VPID flush types.
762	* Valid enum members are in accordance with the VT-x spec.
763	*/
764	typedef enum
765	{
766	/** Invalidate a specific page. */
767	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
768	/** Invalidate one context (specific VPID). */
769	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
770	/** Invalidate all contexts (all VPIDs). */
771	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
772	/** Invalidate a single VPID context retaining global mappings. */
773	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
774	/** Unsupported by VirtualBox. */
775	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
776	/** Unsupported by CPU. */
777	VMXTLBFLUSHVPID_NONE = 0xbad1
778	} VMXTLBFLUSHVPID;
779	AssertCompileSize(VMXTLBFLUSHVPID, 4);
780
781	/**
782	* VMX EPT flush types.
783	* @note Valid enums values are in accordance with the VT-x spec.
784	*/
785	typedef enum
786	{
787	/** Invalidate one context (specific EPT). */
788	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
789	/* Invalidate all contexts (all EPTs) */
790	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
791	/** Unsupported by VirtualBox. */
792	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
793	/** Unsupported by CPU. */
794	VMXTLBFLUSHEPT_NONE = 0xbad1
795	} VMXTLBFLUSHEPT;
796	AssertCompileSize(VMXTLBFLUSHEPT, 4);
797
798	/**
799	* VMX Posted Interrupt Descriptor.
800	* In accordance with the VT-x spec.
801	*/
802	typedef struct VMXPOSTEDINTRDESC
803	{
804	uint32_t aVectorBitmap[8];
805	uint32_t fOutstandingNotification : 1;
806	uint32_t uReserved0 : 31;
807	uint8_t au8Reserved0[28];
808	} VMXPOSTEDINTRDESC;
809	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
810	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
811	/** Pointer to a posted interrupt descriptor. */
812	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
813	/** Pointer to a const posted interrupt descriptor. */
814	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
815
816	/**
817	* VMX VMCS revision identifier.
818	* In accordance with the VT-x spec.
819	*/
820	typedef union
821	{
822	struct
823	{
824	/** Revision identifier. */
825	uint32_t u31RevisionId : 31;
826	/** Whether this is a shadow VMCS. */
827	uint32_t fIsShadowVmcs : 1;
828	} n;
829	/* The unsigned integer view. */
830	uint32_t u;
831	} VMXVMCSREVID;
832	AssertCompileSize(VMXVMCSREVID, 4);
833	/** Pointer to the VMXVMCSREVID union. */
834	typedef VMXVMCSREVID *PVMXVMCSREVID;
835	/** Pointer to a const VMXVMCSREVID union. */
836	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
837
838	/**
839	* VMX VM-exit instruction information.
840	* In accordance with the VT-x spec.
841	*/
842	typedef union
843	{
844	/** Plain unsigned int representation. */
845	uint32_t u;
846
847	/** INS and OUTS information. */
848	struct
849	{
850	uint32_t u7Reserved0 : 7;
851	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
852	uint32_t u3AddrSize : 3;
853	uint32_t u5Reserved1 : 5;
854	/** The segment register (X86_SREG_XXX). */
855	uint32_t iSegReg : 3;
856	uint32_t uReserved2 : 14;
857	} StrIo;
858
859	/** INVEPT, INVPCID, INVVPID information. */
860	struct
861	{
862	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
863	uint32_t u2Scaling : 2;
864	uint32_t u5Undef0 : 5;
865	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
866	uint32_t u3AddrSize : 3;
867	/** Cleared to 0. */
868	uint32_t u1Cleared0 : 1;
869	uint32_t u4Undef0 : 4;
870	/** The segment register (X86_SREG_XXX). */
871	uint32_t iSegReg : 3;
872	/** The index register (X86_GREG_XXX). */
873	uint32_t iIdxReg : 4;
874	/** Set if index register is invalid. */
875	uint32_t fIdxRegInvalid : 1;
876	/** The base register (X86_GREG_XXX). */
877	uint32_t iBaseReg : 4;
878	/** Set if base register is invalid. */
879	uint32_t fBaseRegInvalid : 1;
880	/** Register 2 (X86_GREG_XXX). */
881	uint32_t iReg2 : 4;
882	} Inv;
883
884	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
885	struct
886	{
887	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
888	uint32_t u2Scaling : 2;
889	uint32_t u5Reserved0 : 5;
890	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
891	uint32_t u3AddrSize : 3;
892	/** Cleared to 0. */
893	uint32_t u1Cleared0 : 1;
894	uint32_t u4Reserved0 : 4;
895	/** The segment register (X86_SREG_XXX). */
896	uint32_t iSegReg : 3;
897	/** The index register (X86_GREG_XXX). */
898	uint32_t iIdxReg : 4;
899	/** Set if index register is invalid. */
900	uint32_t fIdxRegInvalid : 1;
901	/** The base register (X86_GREG_XXX). */
902	uint32_t iBaseReg : 4;
903	/** Set if base register is invalid. */
904	uint32_t fBaseRegInvalid : 1;
905	/** Register 2 (X86_GREG_XXX). */
906	uint32_t iReg2 : 4;
907	} VmxXsave;
908
909	/** LIDT, LGDT, SIDT, SGDT information. */
910	struct
911	{
912	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
913	uint32_t u2Scaling : 2;
914	uint32_t u5Undef0 : 5;
915	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
916	uint32_t u3AddrSize : 3;
917	/** Always cleared to 0. */
918	uint32_t u1Cleared0 : 1;
919	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
920	uint32_t uOperandSize : 1;
921	uint32_t u3Undef0 : 3;
922	/** The segment register (X86_SREG_XXX). */
923	uint32_t iSegReg : 3;
924	/** The index register (X86_GREG_XXX). */
925	uint32_t iIdxReg : 4;
926	/** Set if index register is invalid. */
927	uint32_t fIdxRegInvalid : 1;
928	/** The base register (X86_GREG_XXX). */
929	uint32_t iBaseReg : 4;
930	/** Set if base register is invalid. */
931	uint32_t fBaseRegInvalid : 1;
932	/** Instruction identity (VMX_INSTR_ID_XXX). */
933	uint32_t u2InstrId : 2;
934	uint32_t u2Undef0 : 2;
935	} GdtIdt;
936
937	/** LLDT, LTR, SLDT, STR information. */
938	struct
939	{
940	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
941	uint32_t u2Scaling : 2;
942	uint32_t u1Undef0 : 1;
943	/** Register 1 (X86_GREG_XXX). */
944	uint32_t iReg1 : 4;
945	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
946	uint32_t u3AddrSize : 3;
947	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
948	uint32_t fIsRegOperand : 1;
949	uint32_t u4Undef0 : 4;
950	/** The segment register (X86_SREG_XXX). */
951	uint32_t iSegReg : 3;
952	/** The index register (X86_GREG_XXX). */
953	uint32_t iIdxReg : 4;
954	/** Set if index register is invalid. */
955	uint32_t fIdxRegInvalid : 1;
956	/** The base register (X86_GREG_XXX). */
957	uint32_t iBaseReg : 4;
958	/** Set if base register is invalid. */
959	uint32_t fBaseRegInvalid : 1;
960	/** Instruction identity (VMX_INSTR_ID_XXX). */
961	uint32_t u2InstrId : 2;
962	uint32_t u2Undef0 : 2;
963	} LdtTr;
964
965	/** RDRAND, RDSEED information. */
966	struct
967	{
968	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
969	uint32_t u2Undef0 : 2;
970	/** Destination register (X86_GREG_XXX). */
971	uint32_t iReg1 : 4;
972	uint32_t u4Undef0 : 4;
973	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
974	uint32_t u2OperandSize : 2;
975	uint32_t u19Def0 : 20;
976	} RdrandRdseed;
977
978	/** VMREAD, VMWRITE information. */
979	struct
980	{
981	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
982	uint32_t u2Scaling : 2;
983	uint32_t u1Undef0 : 1;
984	/** Register 1 (X86_GREG_XXX). */
985	uint32_t iReg1 : 4;
986	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
987	uint32_t u3AddrSize : 3;
988	/** Memory or register operand. */
989	uint32_t fIsRegOperand : 1;
990	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
991	uint32_t u4Undef0 : 4;
992	/** The segment register (X86_SREG_XXX). */
993	uint32_t iSegReg : 3;
994	/** The index register (X86_GREG_XXX). */
995	uint32_t iIdxReg : 4;
996	/** Set if index register is invalid. */
997	uint32_t fIdxRegInvalid : 1;
998	/** The base register (X86_GREG_XXX). */
999	uint32_t iBaseReg : 4;
1000	/** Set if base register is invalid. */
1001	uint32_t fBaseRegInvalid : 1;
1002	/** Register 2 (X86_GREG_XXX). */
1003	uint32_t iReg2 : 4;
1004	} VmreadVmwrite;
1005
1006	/** This is a combination field of all instruction information. Note! Not all field
1007	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1008	* specialized fields are overwritten by their generic counterparts (e.g. no
1009	* instruction identity field). */
1010	struct
1011	{
1012	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1013	uint32_t u2Scaling : 2;
1014	uint32_t u1Undef0 : 1;
1015	/** Register 1 (X86_GREG_XXX). */
1016	uint32_t iReg1 : 4;
1017	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1018	uint32_t u3AddrSize : 3;
1019	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1020	uint32_t fIsRegOperand : 1;
1021	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1022	uint32_t uOperandSize : 2;
1023	uint32_t u2Undef0 : 2;
1024	/** The segment register (X86_SREG_XXX). */
1025	uint32_t iSegReg : 3;
1026	/** The index register (X86_GREG_XXX). */
1027	uint32_t iIdxReg : 4;
1028	/** Set if index register is invalid. */
1029	uint32_t fIdxRegInvalid : 1;
1030	/** The base register (X86_GREG_XXX). */
1031	uint32_t iBaseReg : 4;
1032	/** Set if base register is invalid. */
1033	uint32_t fBaseRegInvalid : 1;
1034	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1035	uint32_t iReg2 : 4;
1036	} All;
1037	} VMXEXITINSTRINFO;
1038	AssertCompileSize(VMXEXITINSTRINFO, 4);
1039	/** Pointer to a VMX VM-exit instruction info. struct. */
1040	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1041	/** Pointer to a const VMX VM-exit instruction info. struct. */
1042	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1043
1044
1045	/** @name VM-entry failure reported in Exit qualification.
1046	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1047	* @{
1048	*/
1049	/** No errors during VM-entry. */
1050	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1051	/** Not used. */
1052	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1053	/** Error while loading PDPTEs. */
1054	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1055	/** NMI injection when blocking-by-STI is set. */
1056	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1057	/** Invalid VMCS link pointer. */
1058	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1059	/** @} */
1060
1061
1062	/** @name VMXMSRPM_XXX - VMX MSR-bitmap permissions.
1063	* These are -not- specified by Intel but used internally by VirtualBox.
1064	* @{ */
1065	/** Guest software reads of this MSR must not cause a VM-exit. */
1066	#define VMXMSRPM_ALLOW_RD RT_BIT(0)
1067	/** Guest software reads of this MSR must cause a VM-exit. */
1068	#define VMXMSRPM_EXIT_RD RT_BIT(1)
1069	/** Guest software writes to this MSR must not cause a VM-exit. */
1070	#define VMXMSRPM_ALLOW_WR RT_BIT(2)
1071	/** Guest software writes to this MSR must cause a VM-exit. */
1072	#define VMXMSRPM_EXIT_WR RT_BIT(3)
1073	/** Guest software reads or writes of this MSR must not cause a VM-exit. */
1074	#define VMXMSRPM_ALLOW_RD_WR (VMXMSRPM_ALLOW_RD \| VMXMSRPM_ALLOW_WR)
1075	/** Guest software reads or writes of this MSR must cause a VM-exit. */
1076	#define VMXMSRPM_EXIT_RD_WR (VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR)
1077	/** Mask of valid MSR read permissions. */
1078	#define VMXMSRPM_RD_MASK (VMXMSRPM_ALLOW_RD \| VMXMSRPM_EXIT_RD)
1079	/** Mask of valid MSR write permissions. */
1080	#define VMXMSRPM_WR_MASK (VMXMSRPM_ALLOW_WR \| VMXMSRPM_EXIT_WR)
1081	/** Mask of valid MSR permissions. */
1082	#define VMXMSRPM_MASK (VMXMSRPM_RD_MASK \| VMXMSRPM_WR_MASK)
1083	/** */
1084	/** Gets whether the MSR permission is valid or not. */
1085	#define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \
1086	&& ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \
1087	&& ((a_Msrpm) & VMXMSRPM_RD_MASK) != VMXMSRPM_RD_MASK \
1088	&& ((a_Msrpm) & VMXMSRPM_WR_MASK) != VMXMSRPM_WR_MASK)
1089	/** @} */
1090
1091	/**
1092	* VMX MSR autoload/store slot.
1093	* In accordance with the VT-x spec.
1094	*/
1095	typedef struct VMXAUTOMSR
1096	{
1097	/** The MSR Id. */
1098	uint32_t u32Msr;
1099	/** Reserved (MBZ). */
1100	uint32_t u32Reserved;
1101	/** The MSR value. */
1102	uint64_t u64Value;
1103	} VMXAUTOMSR;
1104	AssertCompileSize(VMXAUTOMSR, 16);
1105	/** Pointer to an MSR load/store element. */
1106	typedef VMXAUTOMSR *PVMXAUTOMSR;
1107	/** Pointer to a const MSR load/store element. */
1108	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1109
1110	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1111	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1112
1113	/**
1114	* VMX tagged-TLB flush types.
1115	*/
1116	typedef enum
1117	{
1118	VMXTLBFLUSHTYPE_EPT,
1119	VMXTLBFLUSHTYPE_VPID,
1120	VMXTLBFLUSHTYPE_EPT_VPID,
1121	VMXTLBFLUSHTYPE_NONE
1122	} VMXTLBFLUSHTYPE;
1123	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1124	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1125	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1126	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1127
1128	/**
1129	* VMX controls MSR.
1130	* In accordance with the VT-x spec.
1131	*/
1132	typedef union
1133	{
1134	struct
1135	{
1136	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1137	uint32_t allowed0;
1138	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1139	* controls. */
1140	uint32_t allowed1;
1141	} n;
1142	uint64_t u;
1143	} VMXCTLSMSR;
1144	AssertCompileSize(VMXCTLSMSR, 8);
1145	/** Pointer to a VMXCTLSMSR union. */
1146	typedef VMXCTLSMSR *PVMXCTLSMSR;
1147	/** Pointer to a const VMXCTLSMSR union. */
1148	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1149
1150	/**
1151	* VMX MSRs.
1152	*/
1153	typedef struct VMXMSRS
1154	{
1155	/** VMX/SMX Feature control. */
1156	uint64_t u64FeatCtrl;
1157	/** Basic information. */
1158	uint64_t u64Basic;
1159	/** Pin-based VM-execution controls. */
1160	VMXCTLSMSR PinCtls;
1161	/** Processor-based VM-execution controls. */
1162	VMXCTLSMSR ProcCtls;
1163	/** Secondary processor-based VM-execution controls. */
1164	VMXCTLSMSR ProcCtls2;
1165	/** VM-exit controls. */
1166	VMXCTLSMSR ExitCtls;
1167	/** VM-entry controls. */
1168	VMXCTLSMSR EntryCtls;
1169	/** True pin-based VM-execution controls. */
1170	VMXCTLSMSR TruePinCtls;
1171	/** True processor-based VM-execution controls. */
1172	VMXCTLSMSR TrueProcCtls;
1173	/** True VM-entry controls. */
1174	VMXCTLSMSR TrueEntryCtls;
1175	/** True VM-exit controls. */
1176	VMXCTLSMSR TrueExitCtls;
1177	/** Miscellaneous data. */
1178	uint64_t u64Misc;
1179	/** CR0 fixed-0 - bits set here must be set in VMX operation. */
1180	uint64_t u64Cr0Fixed0;
1181	/** CR0 fixed-1 - bits clear here must be clear in VMX operation. */
1182	uint64_t u64Cr0Fixed1;
1183	/** CR4 fixed-0 - bits set here must be set in VMX operation. */
1184	uint64_t u64Cr4Fixed0;
1185	/** CR4 fixed-1 - bits clear here must be clear in VMX operation. */
1186	uint64_t u64Cr4Fixed1;
1187	/** VMCS enumeration. */
1188	uint64_t u64VmcsEnum;
1189	/** VM Functions. */
1190	uint64_t u64VmFunc;
1191	/** EPT, VPID capabilities. */
1192	uint64_t u64EptVpidCaps;
1193	/** Reserved for future. */
1194	uint64_t a_u64Reserved[9];
1195	} VMXMSRS;
1196	AssertCompileSizeAlignment(VMXMSRS, 8);
1197	AssertCompileSize(VMXMSRS, 224);
1198	/** Pointer to a VMXMSRS struct. */
1199	typedef VMXMSRS *PVMXMSRS;
1200	/** Pointer to a const VMXMSRS struct. */
1201	typedef const VMXMSRS *PCVMXMSRS;
1202
1203
1204	/** @name VMX Basic Exit Reasons.
1205	* @{
1206	*/
1207	/** -1 Invalid exit code */
1208	#define VMX_EXIT_INVALID (-1)
1209	/** 0 Exception or non-maskable interrupt (NMI). */
1210	#define VMX_EXIT_XCPT_OR_NMI 0
1211	/** 1 External interrupt. */
1212	#define VMX_EXIT_EXT_INT 1
1213	/** 2 Triple fault. */
1214	#define VMX_EXIT_TRIPLE_FAULT 2
1215	/** 3 INIT signal. */
1216	#define VMX_EXIT_INIT_SIGNAL 3
1217	/** 4 Start-up IPI (SIPI). */
1218	#define VMX_EXIT_SIPI 4
1219	/** 5 I/O system-management interrupt (SMI). */
1220	#define VMX_EXIT_IO_SMI 5
1221	/** 6 Other SMI. */
1222	#define VMX_EXIT_SMI 6
1223	/** 7 Interrupt window exiting. */
1224	#define VMX_EXIT_INT_WINDOW 7
1225	/** 8 NMI window exiting. */
1226	#define VMX_EXIT_NMI_WINDOW 8
1227	/** 9 Task switch. */
1228	#define VMX_EXIT_TASK_SWITCH 9
1229	/** 10 Guest software attempted to execute CPUID. */
1230	#define VMX_EXIT_CPUID 10
1231	/** 11 Guest software attempted to execute GETSEC. */
1232	#define VMX_EXIT_GETSEC 11
1233	/** 12 Guest software attempted to execute HLT. */
1234	#define VMX_EXIT_HLT 12
1235	/** 13 Guest software attempted to execute INVD. */
1236	#define VMX_EXIT_INVD 13
1237	/** 14 Guest software attempted to execute INVLPG. */
1238	#define VMX_EXIT_INVLPG 14
1239	/** 15 Guest software attempted to execute RDPMC. */
1240	#define VMX_EXIT_RDPMC 15
1241	/** 16 Guest software attempted to execute RDTSC. */
1242	#define VMX_EXIT_RDTSC 16
1243	/** 17 Guest software attempted to execute RSM in SMM. */
1244	#define VMX_EXIT_RSM 17
1245	/** 18 Guest software executed VMCALL. */
1246	#define VMX_EXIT_VMCALL 18
1247	/** 19 Guest software executed VMCLEAR. */
1248	#define VMX_EXIT_VMCLEAR 19
1249	/** 20 Guest software executed VMLAUNCH. */
1250	#define VMX_EXIT_VMLAUNCH 20
1251	/** 21 Guest software executed VMPTRLD. */
1252	#define VMX_EXIT_VMPTRLD 21
1253	/** 22 Guest software executed VMPTRST. */
1254	#define VMX_EXIT_VMPTRST 22
1255	/** 23 Guest software executed VMREAD. */
1256	#define VMX_EXIT_VMREAD 23
1257	/** 24 Guest software executed VMRESUME. */
1258	#define VMX_EXIT_VMRESUME 24
1259	/** 25 Guest software executed VMWRITE. */
1260	#define VMX_EXIT_VMWRITE 25
1261	/** 26 Guest software executed VMXOFF. */
1262	#define VMX_EXIT_VMXOFF 26
1263	/** 27 Guest software executed VMXON. */
1264	#define VMX_EXIT_VMXON 27
1265	/** 28 Control-register accesses. */
1266	#define VMX_EXIT_MOV_CRX 28
1267	/** 29 Debug-register accesses. */
1268	#define VMX_EXIT_MOV_DRX 29
1269	/** 30 I/O instruction. */
1270	#define VMX_EXIT_IO_INSTR 30
1271	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1272	#define VMX_EXIT_RDMSR 31
1273	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1274	#define VMX_EXIT_WRMSR 32
1275	/** 33 VM-entry failure due to invalid guest state. */
1276	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1277	/** 34 VM-entry failure due to MSR loading. */
1278	#define VMX_EXIT_ERR_MSR_LOAD 34
1279	/** 36 Guest software executed MWAIT. */
1280	#define VMX_EXIT_MWAIT 36
1281	/** 37 VM-exit due to monitor trap flag. */
1282	#define VMX_EXIT_MTF 37
1283	/** 39 Guest software attempted to execute MONITOR. */
1284	#define VMX_EXIT_MONITOR 39
1285	/** 40 Guest software attempted to execute PAUSE. */
1286	#define VMX_EXIT_PAUSE 40
1287	/** 41 VM-entry failure due to machine-check. */
1288	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1289	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1290	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1291	/** 44 APIC access. Guest software attempted to access memory at a physical
1292	* address on the APIC-access page. */
1293	#define VMX_EXIT_APIC_ACCESS 44
1294	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1295	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1296	#define VMX_EXIT_VIRTUALIZED_EOI 45
1297	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1298	* SGDT, or SIDT. */
1299	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1300	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1301	* SLDT, or STR. */
1302	#define VMX_EXIT_LDTR_TR_ACCESS 47
1303	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1304	* was disallowed by the configuration of the EPT paging structures. */
1305	#define VMX_EXIT_EPT_VIOLATION 48
1306	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1307	* address encountered a misconfigured EPT paging-structure entry. */
1308	#define VMX_EXIT_EPT_MISCONFIG 49
1309	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1310	#define VMX_EXIT_INVEPT 50
1311	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1312	#define VMX_EXIT_RDTSCP 51
1313	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1314	#define VMX_EXIT_PREEMPT_TIMER 52
1315	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1316	#define VMX_EXIT_INVVPID 53
1317	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1318	#define VMX_EXIT_WBINVD 54
1319	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1320	#define VMX_EXIT_XSETBV 55
1321	/** 56 APIC write. Guest completed write to virtual-APIC. */
1322	#define VMX_EXIT_APIC_WRITE 56
1323	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1324	#define VMX_EXIT_RDRAND 57
1325	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1326	#define VMX_EXIT_INVPCID 58
1327	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1328	#define VMX_EXIT_VMFUNC 59
1329	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1330	#define VMX_EXIT_ENCLS 60
1331	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1332	* enabled. */
1333	#define VMX_EXIT_RDSEED 61
1334	/** 62 - Page-modification log full. */
1335	#define VMX_EXIT_PML_FULL 62
1336	/** 63 - XSAVES. Guest software attempted to execute XSAVES and exiting was
1337	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1338	#define VMX_EXIT_XSAVES 63
1339	/** 64 - XRSTORS. Guest software attempted to execute XRSTORS and exiting
1340	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1341	#define VMX_EXIT_XRSTORS 64
1342	/** 66 - SPP-related event. Attempt to determine an access' sub-page write
1343	* permission encountered an SPP miss or misconfiguration. */
1344	#define VMX_EXIT_SPP_EVENT 66
1345	/* 67 - UMWAIT. Guest software attempted to execute UMWAIT and exiting was enabled. */
1346	#define VMX_EXIT_UMWAIT 67
1347	/** 68 - TPAUSE. Guest software attempted to execute TPAUSE and exiting was
1348	* enabled. */
1349	#define VMX_EXIT_TPAUSE 68
1350	/** The maximum exit value (inclusive). */
1351	#define VMX_EXIT_MAX (VMX_EXIT_TPAUSE)
1352	/** @} */
1353
1354
1355	/** @name VM Instruction Errors.
1356	* In accordance with the VT-x spec.
1357	* See Intel spec. "30.4 VM Instruction Error Numbers"
1358	* @{
1359	*/
1360	typedef enum
1361	{
1362	/** VMCALL executed in VMX root operation. */
1363	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1364	/** VMCLEAR with invalid physical address. */
1365	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1366	/** VMCLEAR with VMXON pointer. */
1367	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1368	/** VMLAUNCH with non-clear VMCS. */
1369	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1370	/** VMRESUME with non-launched VMCS. */
1371	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1372	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1373	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1374	/** VM-entry with invalid control field(s). */
1375	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1376	/** VM-entry with invalid host-state field(s). */
1377	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1378	/** VMPTRLD with invalid physical address. */
1379	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1380	/** VMPTRLD with VMXON pointer. */
1381	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1382	/** VMPTRLD with incorrect VMCS revision identifier. */
1383	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1384	/** VMREAD from unsupported VMCS component. */
1385	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1386	/** VMWRITE to unsupported VMCS component. */
1387	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1388	/** VMWRITE to read-only VMCS component. */
1389	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1390	/** VMXON executed in VMX root operation. */
1391	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1392	/** VM-entry with invalid executive-VMCS pointer. */
1393	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1394	/** VM-entry with non-launched executive VMCS. */
1395	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1396	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1397	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1398	/** VMCALL with non-clear VMCS. */
1399	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1400	/** VMCALL with invalid VM-exit control fields. */
1401	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1402	/** VMCALL with incorrect MSEG revision identifier. */
1403	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1404	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1405	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1406	/** VMCALL with invalid SMM-monitor features. */
1407	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1408	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1409	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1410	/** VM-entry with events blocked by MOV SS. */
1411	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1412	/** Invalid operand to INVEPT/INVVPID. */
1413	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1414	} VMXINSTRERR;
1415	/** @} */
1416
1417
1418	/** @name VMX abort reasons.
1419	* In accordance with the VT-x spec.
1420	* See Intel spec. "27.7 VMX Aborts".
1421	* Update HMGetVmxAbortDesc() if new reasons are added.
1422	* @{
1423	*/
1424	typedef enum
1425	{
1426	/** None - don't use this / uninitialized value. */
1427	VMXABORT_NONE = 0,
1428	/** VMX abort caused during saving of guest MSRs. */
1429	VMXABORT_SAVE_GUEST_MSRS = 1,
1430	/** VMX abort caused during host PDPTE checks. */
1431	VMXBOART_HOST_PDPTE = 2,
1432	/** VMX abort caused due to current VMCS being corrupted. */
1433	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1434	/** VMX abort caused during loading of host MSRs. */
1435	VMXABORT_LOAD_HOST_MSR = 4,
1436	/** VMX abort caused due to a machine-check exception during VM-exit. */
1437	VMXABORT_MACHINE_CHECK_XCPT = 5,
1438	/** VMX abort caused due to invalid return from long mode. */
1439	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1440	/* Type size hack. */
1441	VMXABORT_32BIT_HACK = 0x7fffffff
1442	} VMXABORT;
1443	AssertCompileSize(VMXABORT, 4);
1444	/** @} */
1445
1446
1447	/** @name VMX MSR - Basic VMX information.
1448	* @{
1449	*/
1450	/** VMCS (and related regions) memory type - Uncacheable. */
1451	#define VMX_BASIC_MEM_TYPE_UC 0
1452	/** VMCS (and related regions) memory type - Write back. */
1453	#define VMX_BASIC_MEM_TYPE_WB 6
1454	/** Width of physical addresses used for VMCS and associated memory regions
1455	* (1=32-bit, 0=processor's physical address width). */
1456	#define VMX_BASIC_PHYSADDR_WIDTH_32BIT RT_BIT_64(48)
1457
1458	/** Bit fields for MSR_IA32_VMX_BASIC. */
1459	/** VMCS revision identifier used by the processor. */
1460	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1461	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1462	/** Bit 31 is reserved and RAZ. */
1463	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1464	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1465	/** VMCS size in bytes. */
1466	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1467	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1468	/** Bits 45:47 are reserved. */
1469	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1470	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1471	/** Width of physical addresses used for the VMCS and associated memory regions
1472	* (always 0 on CPUs that support Intel 64 architecture). */
1473	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1474	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1475	/** Dual-monitor treatment of SMI and SMM supported. */
1476	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1477	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1478	/** Memory type that must be used for the VMCS and associated memory regions. */
1479	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1480	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1481	/** VM-exit instruction information for INS/OUTS. */
1482	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1483	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1484	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1485	* bits in VMX control MSRs. */
1486	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1487	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1488	/** Whether VM-entry can delivery error code for all hardware exception vectors. */
1489	#define VMX_BF_BASIC_XCPT_ERRCODE_SHIFT 56
1490	#define VMX_BF_BASIC_XCPT_ERRCODE_MASK UINT64_C(0x0100000000000000)
1491	/** Bits 57:63 are reserved and RAZ. */
1492	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 57
1493	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xfe00000000000000)
1494	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1495	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1496	VMCS_INS_OUTS, TRUE_CTLS, XCPT_ERRCODE, RSVD_56_63));
1497	/** @} */
1498
1499
1500	/** @name VMX MSR - Miscellaneous data.
1501	* @{
1502	*/
1503	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1504	#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1505	/** Whether Intel PT is supported in VMX operation. */
1506	#define VMX_MISC_INTEL_PT RT_BIT(14)
1507	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1508	* VMWRITE cannot modify read-only VM-exit information fields. */
1509	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1510	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1511	* instructions. */
1512	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1513	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1514	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1515	/** Maximum CR3-target count supported by the CPU. */
1516	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1517
1518	/** Bit fields for MSR_IA32_VMX_MISC. */
1519	/** Relationship between the preemption timer and tsc. */
1520	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1521	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1522	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1523	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1524	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1525	/** Activity states supported by the implementation. */
1526	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1527	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1528	/** Bits 9:13 is reserved and RAZ. */
1529	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1530	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1531	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1532	#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1533	#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1534	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1535	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1536	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1537	/** Number of CR3 target values supported by the processor. (0-256) */
1538	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1539	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1540	/** Maximum number of MSRs in the VMCS. */
1541	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1542	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1543	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1544	* SMIs. */
1545	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1546	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1547	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1548	* VMWRITE cannot modify read-only VM-exit information fields. */
1549	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1550	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1551	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1552	* instructions. */
1553	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1554	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1555	/** Bit 31 is reserved and RAZ. */
1556	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1557	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1558	/** 32-bit MSEG revision ID used by the processor. */
1559	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1560	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1561	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1562	(PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1563	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1564	/** @} */
1565
1566	/** @name VMX MSR - VMCS enumeration.
1567	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1568	* @{
1569	*/
1570	/** Bit 0 is reserved and RAZ. */
1571	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1572	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1573	/** Highest index value used in VMCS field encoding. */
1574	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1575	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1576	/** Bit 10:63 is reserved and RAZ. */
1577	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1578	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1579	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1580	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1581	/** @} */
1582
1583
1584	/** @name VMX MSR - VM Functions.
1585	* Bit fields for MSR_IA32_VMX_VMFUNC.
1586	* @{
1587	*/
1588	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1589	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1590	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1591	/** Bits 1:63 are reserved and RAZ. */
1592	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1593	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1594	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1595	(EPTP_SWITCHING, RSVD_1_63));
1596	/** @} */
1597
1598
1599	/** @name VMX MSR - EPT/VPID capabilities.
1600	* @{
1601	*/
1602	/** Supports execute-only translations by EPT. */
1603	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1604	/** Supports page-walk length of 4. */
1605	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1606	/** Supports page-walk length of 5. */
1607	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5 RT_BIT_64(7)
1608	/** Supports EPT paging-structure memory type to be uncacheable. */
1609	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1610	/** Supports EPT paging structure memory type to be write-back. */
1611	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1612	/** Supports EPT PDE to map a 2 MB page. */
1613	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1614	/** Supports EPT PDPTE to map a 1 GB page. */
1615	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1616	/** Supports INVEPT instruction. */
1617	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1618	/** Supports accessed and dirty flags for EPT. */
1619	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1620	/** Supports advanced VM-exit info. for EPT violations. */
1621	#define MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT RT_BIT_64(22)
1622	/** Supports supervisor shadow-stack control. */
1623	#define MSR_IA32_VMX_EPT_VPID_CAP_SSS RT_BIT_64(23)
1624	/** Supports single-context INVEPT type. */
1625	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1626	/** Supports all-context INVEPT type. */
1627	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1628	/** Supports INVVPID instruction. */
1629	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1630	/** Supports individual-address INVVPID type. */
1631	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1632	/** Supports single-context INVVPID type. */
1633	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1634	/** Supports all-context INVVPID type. */
1635	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1636	/** Supports singe-context-retaining-globals INVVPID type. */
1637	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1638
1639	/** Bit fields for MSR_IA32_VMX_EPT_VPID_CAP. */
1640	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_SHIFT 0
1641	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_MASK UINT64_C(0x0000000000000001)
1642	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_SHIFT 1
1643	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_MASK UINT64_C(0x000000000000003e)
1644	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_SHIFT 6
1645	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_MASK UINT64_C(0x0000000000000040)
1646	#define VMX_BF_EPT_VPID_CAP_RSVD_7_SHIFT 7
1647	#define VMX_BF_EPT_VPID_CAP_RSVD_7_MASK UINT64_C(0x0000000000000080)
1648	#define VMX_BF_EPT_VPID_CAP_EMT_UC_SHIFT 8
1649	#define VMX_BF_EPT_VPID_CAP_EMT_UC_MASK UINT64_C(0x0000000000000100)
1650	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_SHIFT 9
1651	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1652	#define VMX_BF_EPT_VPID_CAP_EMT_WB_SHIFT 14
1653	#define VMX_BF_EPT_VPID_CAP_EMT_WB_MASK UINT64_C(0x0000000000004000)
1654	#define VMX_BF_EPT_VPID_CAP_RSVD_15_SHIFT 15
1655	#define VMX_BF_EPT_VPID_CAP_RSVD_15_MASK UINT64_C(0x0000000000008000)
1656	#define VMX_BF_EPT_VPID_CAP_PDE_2M_SHIFT 16
1657	#define VMX_BF_EPT_VPID_CAP_PDE_2M_MASK UINT64_C(0x0000000000010000)
1658	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_SHIFT 17
1659	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_MASK UINT64_C(0x0000000000020000)
1660	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_SHIFT 18
1661	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_MASK UINT64_C(0x00000000000c0000)
1662	#define VMX_BF_EPT_VPID_CAP_INVEPT_SHIFT 20
1663	#define VMX_BF_EPT_VPID_CAP_INVEPT_MASK UINT64_C(0x0000000000100000)
1664	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_SHIFT 21
1665	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_MASK UINT64_C(0x0000000000200000)
1666	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_SHIFT 22
1667	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_MASK UINT64_C(0x0000000000400000)
1668	#define VMX_BF_EPT_VPID_CAP_SSS_SHIFT 23
1669	#define VMX_BF_EPT_VPID_CAP_SSS_MASK UINT64_C(0x0000000000800000)
1670	#define VMX_BF_EPT_VPID_CAP_RSVD_24_SHIFT 24
1671	#define VMX_BF_EPT_VPID_CAP_RSVD_24_MASK UINT64_C(0x0000000001000000)
1672	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_SHIFT 25
1673	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_MASK UINT64_C(0x0000000002000000)
1674	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_SHIFT 26
1675	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_MASK UINT64_C(0x0000000004000000)
1676	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_SHIFT 27
1677	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_MASK UINT64_C(0x00000000f8000000)
1678	#define VMX_BF_EPT_VPID_CAP_INVVPID_SHIFT 32
1679	#define VMX_BF_EPT_VPID_CAP_INVVPID_MASK UINT64_C(0x0000000100000000)
1680	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_SHIFT 33
1681	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_MASK UINT64_C(0x000000fe00000000)
1682	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_SHIFT 40
1683	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_MASK UINT64_C(0x0000010000000000)
1684	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_SHIFT 41
1685	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_MASK UINT64_C(0x0000020000000000)
1686	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_SHIFT 42
1687	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_MASK UINT64_C(0x0000040000000000)
1688	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_SHIFT 43
1689	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_MASK UINT64_C(0x0000080000000000)
1690	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_SHIFT 44
1691	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_MASK UINT64_C(0xfffff00000000000)
1692	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_VPID_CAP_, UINT64_C(0), UINT64_MAX,
1693	(RWX_X_ONLY, RSVD_1_5, PAGE_WALK_LENGTH_4, RSVD_7, EMT_UC, RSVD_9_13, EMT_WB, RSVD_15, PDE_2M,
1694	PDPTE_1G, RSVD_18_19, INVEPT, EPT_ACCESS_DIRTY, ADVEXITINFO_EPT, SSS, RSVD_24, INVEPT_SINGLE_CTX,
1695	INVEPT_ALL_CTX, RSVD_27_31, INVVPID, RSVD_33_39, INVVPID_INDIV_ADDR, INVVPID_SINGLE_CTX,
1696	INVVPID_ALL_CTX, INVVPID_SINGLE_CTX_RETAIN_GLOBALS, RSVD_44_63));
1697	/** @} */
1698
1699
1700	/** @name Extended Page Table Pointer (EPTP)
1701	* @{
1702	*/
1703	/** Uncachable EPT paging structure memory type. */
1704	#define VMX_EPT_MEMTYPE_UC 0
1705	/** Write-back EPT paging structure memory type. */
1706	#define VMX_EPT_MEMTYPE_WB 6
1707	/** Shift value to get the EPT page walk length (bits 5-3) */
1708	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1709	/** Mask value to get the EPT page walk length (bits 5-3) */
1710	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1711	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1712	* length) */
1713	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1714	/** @} */
1715
1716
1717	/** @name VMCS fields and encoding.
1718	*
1719	* When adding a new field:
1720	* - Always add it to g_aVmcsFields.
1721	* - Consider if it needs to be added to VMXVVMCS.
1722	* @{
1723	*/
1724	/** 16-bit control fields. */
1725	#define VMX_VMCS16_VPID 0x0000
1726	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1727	#define VMX_VMCS16_EPTP_INDEX 0x0004
1728
1729	/** 16-bit guest-state fields. */
1730	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1731	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1732	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1733	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1734	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1735	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1736	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1737	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1738	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1739	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1740
1741	/** 16-bits host-state fields. */
1742	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1743	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1744	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1745	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1746	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1747	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1748	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1749
1750	/** 64-bit control fields. */
1751	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1752	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1753	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1754	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1755	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1756	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1757	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1758	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1759	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1760	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1761	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1762	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1763	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1764	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1765	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1766	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1767	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1768	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1769	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1770	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1771	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1772	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1773	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1774	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1775	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1776	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1777	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1778	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1779	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1780	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1781	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1782	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1783	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1784	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1785	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1786	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1787	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1788	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1789	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1790	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1791	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1792	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1793	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1794	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1795	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1796	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1797	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1798	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1799	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1800	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1801
1802	/** 64-bit read-only data fields. */
1803	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1804	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1805
1806	/** 64-bit guest-state fields. */
1807	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1808	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1809	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1810	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1811	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1812	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1813	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1814	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1815	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1816	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1817	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1818	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1819	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1820	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1821	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1822	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1823	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1824	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1825	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1826	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1827
1828	/** 64-bit host-state fields. */
1829	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1830	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1831	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1832	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1833	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1834	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1835
1836	/** 32-bit control fields. */
1837	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1838	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1839	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1840	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1841	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1842	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1843	#define VMX_VMCS32_CTRL_EXIT 0x400c
1844	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1845	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1846	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1847	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1848	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1849	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1850	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1851	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1852	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1853	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1854	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1855
1856	/** 32-bits read-only fields. */
1857	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1858	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1859	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1860	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1861	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1862	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1863	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1864	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1865
1866	/** 32-bit guest-state fields. */
1867	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1868	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1869	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1870	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1871	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1872	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1873	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1874	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1875	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1876	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1877	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1878	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1879	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1880	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1881	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1882	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1883	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1884	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1885	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1886	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1887	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1888	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
1889	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1890
1891	/** 32-bit host-state fields. */
1892	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1893
1894	/** Natural-width control fields. */
1895	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1896	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1897	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1898	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1899	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1900	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1901	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1902	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
1903
1904	/** Natural-width read-only data fields. */
1905	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1906	#define VMX_VMCS_RO_IO_RCX 0x6402
1907	#define VMX_VMCS_RO_IO_RSI 0x6404
1908	#define VMX_VMCS_RO_IO_RDI 0x6406
1909	#define VMX_VMCS_RO_IO_RIP 0x6408
1910	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
1911
1912	/** Natural-width guest-state fields. */
1913	#define VMX_VMCS_GUEST_CR0 0x6800
1914	#define VMX_VMCS_GUEST_CR3 0x6802
1915	#define VMX_VMCS_GUEST_CR4 0x6804
1916	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1917	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1918	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1919	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1920	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1921	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1922	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1923	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1924	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1925	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1926	#define VMX_VMCS_GUEST_DR7 0x681a
1927	#define VMX_VMCS_GUEST_RSP 0x681c
1928	#define VMX_VMCS_GUEST_RIP 0x681e
1929	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1930	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
1931	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
1932	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
1933
1934	/** Natural-width host-state fields. */
1935	#define VMX_VMCS_HOST_CR0 0x6c00
1936	#define VMX_VMCS_HOST_CR3 0x6c02
1937	#define VMX_VMCS_HOST_CR4 0x6c04
1938	#define VMX_VMCS_HOST_FS_BASE 0x6c06
1939	#define VMX_VMCS_HOST_GS_BASE 0x6c08
1940	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
1941	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
1942	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
1943	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
1944	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
1945	#define VMX_VMCS_HOST_RSP 0x6c14
1946	#define VMX_VMCS_HOST_RIP 0x6c16
1947
1948	/**
1949	* VMCS field.
1950	* In accordance with the VT-x spec.
1951	*/
1952	typedef union
1953	{
1954	struct
1955	{
1956	/** The access type; 0=full, 1=high of 64-bit fields. */
1957	uint32_t fAccessType : 1;
1958	/** The index. */
1959	uint32_t u8Index : 8;
1960	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
1961	uint32_t u2Type : 2;
1962	/** Reserved (MBZ). */
1963	uint32_t u1Reserved0 : 1;
1964	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
1965	uint32_t u2Width : 2;
1966	/** Reserved (MBZ). */
1967	uint32_t u18Reserved0 : 18;
1968	} n;
1969
1970	/* The unsigned integer view. */
1971	uint32_t u;
1972	} VMXVMCSFIELD;
1973	AssertCompileSize(VMXVMCSFIELD, 4);
1974	/** Pointer to a VMCS field. */
1975	typedef VMXVMCSFIELD *PVMXVMCSFIELD;
1976	/** Pointer to a const VMCS field. */
1977	typedef const VMXVMCSFIELD *PCVMXVMCSFIELD;
1978
1979	/** VMCS field: Mask of reserved bits (bits 63:15 MBZ), bit 12 is not included! */
1980	#define VMX_VMCSFIELD_RSVD_MASK UINT64_C(0xffffffffffff8000)
1981
1982	/** Bits fields for a VMCS field. */
1983	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_SHIFT 0
1984	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_MASK UINT32_C(0x00000001)
1985	#define VMX_BF_VMCSFIELD_INDEX_SHIFT 1
1986	#define VMX_BF_VMCSFIELD_INDEX_MASK UINT32_C(0x000003fe)
1987	#define VMX_BF_VMCSFIELD_TYPE_SHIFT 10
1988	#define VMX_BF_VMCSFIELD_TYPE_MASK UINT32_C(0x00000c00)
1989	#define VMX_BF_VMCSFIELD_RSVD_12_SHIFT 12
1990	#define VMX_BF_VMCSFIELD_RSVD_12_MASK UINT32_C(0x00001000)
1991	#define VMX_BF_VMCSFIELD_WIDTH_SHIFT 13
1992	#define VMX_BF_VMCSFIELD_WIDTH_MASK UINT32_C(0x00006000)
1993	#define VMX_BF_VMCSFIELD_RSVD_15_31_SHIFT 15
1994	#define VMX_BF_VMCSFIELD_RSVD_15_31_MASK UINT32_C(0xffff8000)
1995	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCSFIELD_, UINT32_C(0), UINT32_MAX,
1996	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
1997
1998	/**
1999	* VMCS field encoding: Access type.
2000	* In accordance with the VT-x spec.
2001	*/
2002	typedef enum
2003	{
2004	VMXVMCSFIELDACCESS_FULL = 0,
2005	VMXVMCSFIELDACCESS_HIGH
2006	} VMXVMCSFIELDACCESS;
2007	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
2008	/** VMCS field encoding type: Full. */
2009	#define VMX_VMCSFIELD_ACCESS_FULL 0
2010	/** VMCS field encoding type: High. */
2011	#define VMX_VMCSFIELD_ACCESS_HIGH 1
2012
2013	/**
2014	* VMCS field encoding: Type.
2015	* In accordance with the VT-x spec.
2016	*/
2017	typedef enum
2018	{
2019	VMXVMCSFIELDTYPE_CONTROL = 0,
2020	VMXVMCSFIELDTYPE_VMEXIT_INFO,
2021	VMXVMCSFIELDTYPE_GUEST_STATE,
2022	VMXVMCSFIELDTYPE_HOST_STATE
2023	} VMXVMCSFIELDTYPE;
2024	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
2025	/** VMCS field encoding type: Control. */
2026	#define VMX_VMCSFIELD_TYPE_CONTROL 0
2027	/** VMCS field encoding type: VM-exit information / read-only fields. */
2028	#define VMX_VMCSFIELD_TYPE_VMEXIT_INFO 1
2029	/** VMCS field encoding type: Guest-state. */
2030	#define VMX_VMCSFIELD_TYPE_GUEST_STATE 2
2031	/** VMCS field encoding type: Host-state. */
2032	#define VMX_VMCSFIELD_TYPE_HOST_STATE 3
2033
2034	/**
2035	* VMCS field encoding: Width.
2036	* In accordance with the VT-x spec.
2037	*/
2038	typedef enum
2039	{
2040	VMXVMCSFIELDWIDTH_16BIT = 0,
2041	VMXVMCSFIELDWIDTH_64BIT,
2042	VMXVMCSFIELDWIDTH_32BIT,
2043	VMXVMCSFIELDWIDTH_NATURAL
2044	} VMXVMCSFIELDWIDTH;
2045	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
2046	/** VMCS field encoding width: 16-bit. */
2047	#define VMX_VMCSFIELD_WIDTH_16BIT 0
2048	/** VMCS field encoding width: 64-bit. */
2049	#define VMX_VMCSFIELD_WIDTH_64BIT 1
2050	/** VMCS field encoding width: 32-bit. */
2051	#define VMX_VMCSFIELD_WIDTH_32BIT 2
2052	/** VMCS field encoding width: Natural width. */
2053	#define VMX_VMCSFIELD_WIDTH_NATURAL 3
2054	/** @} */
2055
2056
2057	/** @name VM-entry instruction length.
2058	* @{ */
2059	/** The maximum valid value for VM-entry instruction length while injecting a
2060	* software interrupt, software exception or privileged software exception. */
2061	#define VMX_ENTRY_INSTR_LEN_MAX 15
2062	/** @} */
2063
2064
2065	/** @name VM-entry register masks.
2066	* @{ */
2067	/** CR0 bits ignored on VM-entry while loading guest CR0 (ET, CD, NW, bits 6:15,
2068	* bit 17 and bits 19:28). */
2069	#define VMX_ENTRY_GUEST_CR0_IGNORE_MASK UINT64_C(0x7ffaffd0)
2070	/** DR7 bits set here are always cleared on VM-entry while loading guest DR7 (bit
2071	* 12, bits 14:15). */
2072	#define VMX_ENTRY_GUEST_DR7_MBZ_MASK UINT64_C(0xd000)
2073	/** DR7 bits set here are always set on VM-entry while loading guest DR7 (bit
2074	* 10). */
2075	#define VMX_ENTRY_GUEST_DR7_MB1_MASK UINT64_C(0x400)
2076	/** @} */
2077
2078
2079	/** @name VM-exit register masks.
2080	* @{ */
2081	/** CR0 bits ignored on VM-exit while loading host CR0 (ET, CD, NW, bits 6:15,
2082	* bit 17, bits 19:28 and bits 32:63). */
2083	#define VMX_EXIT_HOST_CR0_IGNORE_MASK UINT64_C(0xffffffff7ffaffd0)
2084	/** @} */
2085
2086
2087	/** @name Pin-based VM-execution controls.
2088	* @{
2089	*/
2090	/** External interrupt exiting. */
2091	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
2092	/** NMI exiting. */
2093	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
2094	/** Virtual NMIs. */
2095	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
2096	/** Activate VMX preemption timer. */
2097	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
2098	/** Process interrupts with the posted-interrupt notification vector. */
2099	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
2100	/** Default1 class when true capability MSRs are not supported. */
2101	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
2102
2103	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
2104	* controls field in the VMCS. */
2105	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
2106	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
2107	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
2108	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
2109	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
2110	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
2111	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
2112	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
2113	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
2114	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
2115	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
2116	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
2117	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
2118	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
2119	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
2120	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
2121	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
2122	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
2123	/** @} */
2124
2125
2126	/** @name Processor-based VM-execution controls.
2127	* @{
2128	*/
2129	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
2130	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
2131	/** Use timestamp counter offset. */
2132	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
2133	/** VM-exit when executing the HLT instruction. */
2134	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
2135	/** VM-exit when executing the INVLPG instruction. */
2136	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
2137	/** VM-exit when executing the MWAIT instruction. */
2138	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
2139	/** VM-exit when executing the RDPMC instruction. */
2140	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
2141	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
2142	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
2143	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
2144	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2145	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
2146	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
2147	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2148	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
2149	/** VM-exit on CR8 loads. */
2150	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
2151	/** VM-exit on CR8 stores. */
2152	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
2153	/** Use TPR shadow. */
2154	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
2155	/** VM-exit when virtual NMI blocking is disabled. */
2156	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
2157	/** VM-exit when executing a MOV DRx instruction. */
2158	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
2159	/** VM-exit when executing IO instructions. */
2160	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
2161	/** Use IO bitmaps. */
2162	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
2163	/** Monitor trap flag. */
2164	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2165	/** Use MSR bitmaps. */
2166	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2167	/** VM-exit when executing the MONITOR instruction. */
2168	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2169	/** VM-exit when executing the PAUSE instruction. */
2170	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2171	/** Whether the secondary processor based VM-execution controls are used. */
2172	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2173	/** Default1 class when true-capability MSRs are not supported. */
2174	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2175
2176	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2177	* controls field in the VMCS. */
2178	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
2179	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2180	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2181	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2182	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2183	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2184	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
2185	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
2186	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2187	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2188	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
2189	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
2190	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2191	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2192	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2193	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2194	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2195	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2196	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2197	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2198	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
2199	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2200	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2201	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2202	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2203	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2204	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
2205	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
2206	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2207	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2208	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2209	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2210	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2211	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2212	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2213	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2214	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2215	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2216	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2217	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2218	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2219	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2220	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
2221	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
2222	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2223	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2224	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2225	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2226	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2227	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2228	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2229	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2230	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2231	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2232	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2233	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
2234	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
2235	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2236	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2237	USE_SECONDARY_CTLS));
2238	/** @} */
2239
2240
2241	/** @name Secondary Processor-based VM-execution controls.
2242	* @{
2243	*/
2244	/** Virtualize APIC accesses. */
2245	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2246	/** EPT supported/enabled. */
2247	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2248	/** Descriptor table instructions cause VM-exits. */
2249	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2250	/** RDTSCP supported/enabled. */
2251	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2252	/** Virtualize x2APIC mode. */
2253	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2254	/** VPID supported/enabled. */
2255	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2256	/** VM-exit when executing the WBINVD instruction. */
2257	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2258	/** Unrestricted guest execution. */
2259	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2260	/** APIC register virtualization. */
2261	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2262	/** Virtual-interrupt delivery. */
2263	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2264	/** A specified number of pause loops cause a VM-exit. */
2265	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2266	/** VM-exit when executing RDRAND instructions. */
2267	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2268	/** Enables INVPCID instructions. */
2269	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2270	/** Enables VMFUNC instructions. */
2271	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2272	/** Enables VMCS shadowing. */
2273	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2274	/** Enables ENCLS VM-exits. */
2275	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2276	/** VM-exit when executing RDSEED. */
2277	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2278	/** Enables page-modification logging. */
2279	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2280	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2281	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
2282	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2283	#define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19)
2284	/** Enables XSAVES/XRSTORS instructions. */
2285	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2286	/** Enables supervisor/user mode based EPT execute permission for linear
2287	* addresses. */
2288	#define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22)
2289	/** Enables EPT permissions to be specified at granularity of 128 bytes. */
2290	#define VMX_PROC_CTLS2_SPPTP_EPT RT_BIT(23)
2291	/** Intel PT output addresses are treated as guest-physical addresses and
2292	* translated using EPT. */
2293	#define VMX_PROC_CTLS2_PT_EPT RT_BIT(24)
2294	/** Use TSC scaling. */
2295	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2296	/** Enables TPAUSE, UMONITOR and UMWAIT instructions. */
2297	#define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26)
2298	/** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */
2299	#define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28)
2300
2301	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2302	* VM-execution controls field in the VMCS. */
2303	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2304	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2305	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2306	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2307	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2308	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2309	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2310	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2311	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2312	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2313	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2314	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2315	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2316	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2317	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2318	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2319	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2320	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2321	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2322	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2323	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2324	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2325	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2326	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2327	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2328	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2329	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2330	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2331	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2332	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2333	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2334	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2335	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2336	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2337	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2338	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2339	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2340	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2341	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19
2342	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000)
2343	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2344	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2345	#define VMX_BF_PROC_CTLS2_UNDEF_21_SHIFT 21
2346	#define VMX_BF_PROC_CTLS2_UNDEF_21_MASK UINT32_C(0x00200000)
2347	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22
2348	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000)
2349	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_SHIFT 23
2350	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_MASK UINT32_C(0x00800000)
2351	#define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24
2352	#define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000)
2353	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2354	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2355	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26
2356	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000)
2357	#define VMX_BF_PROC_CTLS2_UNDEF_27_SHIFT 27
2358	#define VMX_BF_PROC_CTLS2_UNDEF_27_MASK UINT32_C(0x08000000)
2359	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28
2360	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000)
2361	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_SHIFT 29
2362	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_MASK UINT32_C(0xe0000000)
2363
2364	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2365	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2366	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2367	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, UNDEF_21,
2368	MODE_BASED_EPT_PERM, SPPTP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, UNDEF_27, ENCLV_EXIT,
2369	UNDEF_29_31));
2370	/** @} */
2371
2372
2373	/** @name VM-entry controls.
2374	* @{
2375	*/
2376	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2377	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2378	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2379	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2380	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2381	/** In SMM mode after VM-entry. */
2382	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2383	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2384	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2385	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2386	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2387	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2388	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2389	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2390	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2391	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2392	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2393	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2394	#define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17)
2395	/** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
2396	#define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18)
2397	/** Whether the guest CET-related MSRs and SPP are loaded on VM-entry. */
2398	#define VMX_ENTRY_CTLS_LOAD_CET_STATE RT_BIT(20)
2399	/** Default1 class when true-capability MSRs are not supported. */
2400	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2401
2402	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2403	* VMCS. */
2404	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2405	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2406	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2407	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2408	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2409	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2410	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2411	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2412	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2413	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2414	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2415	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2416	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2417	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2418	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2419	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2420	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2421	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2422	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2423	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2424	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2425	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2426	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17
2427	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000)
2428	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18
2429	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000)
2430	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_SHIFT 19
2431	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_MASK UINT32_C(0xfff80000)
2432	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2433	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2434	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
2435	LOAD_RTIT_CTL_MSR, UNDEF_19_31));
2436	/** @} */
2437
2438
2439	/** @name VM-exit controls.
2440	* @{
2441	*/
2442	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2443	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2444	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2445	/** Return to long mode after a VM-exit. */
2446	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2447	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2448	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2449	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2450	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2451	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2452	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2453	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2454	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2455	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2456	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2457	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2458	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2459	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2460	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2461	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2462	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2463	/** Whether to conceal VMX from Intel PT. */
2464	#define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24)
2465	/** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
2466	#define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25)
2467	/** Whether CET-related MSRs and SPP are loaded on VM-exit. */
2468	#define VMX_EXIT_CTLS_LOAD_CET_STATE RT_BIT(28)
2469	/** Default1 class when true-capability MSRs are not supported. */
2470	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2471
2472	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2473	* VMCS. */
2474	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2475	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2476	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2477	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2478	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2479	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2480	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2481	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2482	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2483	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2484	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2485	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2486	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2487	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2488	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2489	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2490	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2491	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2492	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2493	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2494	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2495	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2496	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2497	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2498	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2499	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2500	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2501	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2502	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23
2503	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000)
2504	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24
2505	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000)
2506	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25
2507	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000)
2508	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_SHIFT 26
2509	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2510	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2511	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2512	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2513	SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, UNDEF_26_31));
2514	/** @} */
2515
2516
2517	/** @name VM-exit reason.
2518	* @{
2519	*/
2520	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2521	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2522	#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2523
2524	/** Bit fields for VM-exit reason. */
2525	/** The exit reason. */
2526	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2527	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2528	/** Bits 16:26 are reseved and MBZ. */
2529	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2530	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2531	/** Whether the VM-exit was incident to enclave mode. */
2532	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2533	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2534	/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2535	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2536	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2537	/** VM-exit from VMX root operation (only possible with SMM). */
2538	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2539	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2540	/** Bit 30 is reserved and MBZ. */
2541	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2542	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2543	/** Whether VM-entry failed (currently only happens during loading guest-state
2544	* or MSRs or machine check exceptions). */
2545	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2546	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2547	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2548	(BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2549	/** @} */
2550
2551
2552	/** @name VM-entry interruption information.
2553	* @{
2554	*/
2555	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2556	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2557	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2558	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2559	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2560	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2561	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2562	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2563	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2564	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2565	/** Construct an VM-entry interruption information field from a VM-exit interruption
2566	* info value (same except that bit 12 is reserved). */
2567	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2568	/** Construct a VM-entry interruption information field from an IDT-vectoring
2569	* information field (same except that bit 12 is reserved). */
2570	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2571	/** If the VM-entry interruption information field indicates a page-fault. */
2572	#define VMX_ENTRY_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2573	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2574	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2575	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2576	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT) \
2577	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_PF)))
2578	/** If the VM-entry interruption information field indicates an external
2579	* interrupt. */
2580	#define VMX_ENTRY_INT_INFO_IS_EXT_INT(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2581	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK)) \
2582	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2583	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_EXT_INT)))
2584	/** If the VM-entry interruption information field indicates an NMI. */
2585	#define VMX_ENTRY_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2586	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2587	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2588	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2589	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_NMI) \
2590	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_NMI)))
2591
2592	/** Bit fields for VM-entry interruption information. */
2593	/** The VM-entry interruption vector. */
2594	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2595	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2596	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2597	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2598	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2599	/** Whether this event has an error code. */
2600	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2601	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2602	/** Bits 12:30 are reserved and MBZ. */
2603	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2604	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2605	/** Whether this VM-entry interruption info is valid. */
2606	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2607	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2608	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2609	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2610	/** @} */
2611
2612
2613	/** @name VM-entry exception error code.
2614	* @{ */
2615	/** Error code valid mask. */
2616	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2617	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2618	* stack aligned for doubleword pushes, the upper half of the error code is
2619	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2620	* use below. */
2621	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2622	/** @} */
2623
2624	/** @name VM-entry interruption information types.
2625	* @{
2626	*/
2627	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2628	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2629	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2630	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2631	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2632	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2633	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2634	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2635	/** @} */
2636
2637
2638	/** @name VM-entry interruption information vector types for
2639	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2640	* @{ */
2641	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2642	/** @} */
2643
2644
2645	/** @name VM-exit interruption information.
2646	* @{
2647	*/
2648	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2649	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2650	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2651	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2652	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2653	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2654	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2655	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2656	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2657
2658	/** If the VM-exit interruption information field indicates an page-fault. */
2659	#define VMX_EXIT_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2660	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2661	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2662	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2663	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2664	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_PF)))
2665	/** If the VM-exit interruption information field indicates an double-fault. */
2666	#define VMX_EXIT_INT_INFO_IS_XCPT_DF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2667	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2668	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2669	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2670	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2671	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)))
2672	/** If the VM-exit interruption information field indicates an NMI. */
2673	#define VMX_EXIT_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2674	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2675	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2676	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2677	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI) \
2678	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI)))
2679
2680
2681	/** Bit fields for VM-exit interruption infomration. */
2682	/** The VM-exit interruption vector. */
2683	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2684	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2685	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2686	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2687	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2688	/** Whether this event has an error code. */
2689	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2690	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2691	/** Whether NMI-unblocking due to IRET is active. */
2692	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2693	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2694	/** Bits 13:30 is reserved (MBZ). */
2695	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2696	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2697	/** Whether this VM-exit interruption info is valid. */
2698	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2699	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2700	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2701	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2702	/** @} */
2703
2704
2705	/** @name VM-exit interruption information types.
2706	* @{
2707	*/
2708	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2709	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2710	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2711	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2712	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2713	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2714	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2715	/** @} */
2716
2717
2718	/** @name VM-exit instruction identity.
2719	*
2720	* These are found in VM-exit instruction information fields for certain
2721	* instructions.
2722	* @{ */
2723	typedef uint32_t VMXINSTRID;
2724	/** Whether the instruction ID field is valid. */
2725	#define VMXINSTRID_VALID RT_BIT_32(31)
2726	/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
2727	* read or write. */
2728	#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
2729	/** Gets whether the instruction ID is valid or not. */
2730	#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
2731	#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
2732	/** Gets the instruction ID. */
2733	#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W))
2734	/** No instruction ID info. */
2735	#define VMXINSTRID_NONE 0
2736
2737	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2738	#define VMXINSTRID_SGDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2739	#define VMXINSTRID_SIDT (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2740	#define VMXINSTRID_LGDT (0x2 \| VMXINSTRID_VALID)
2741	#define VMXINSTRID_LIDT (0x3 \| VMXINSTRID_VALID)
2742
2743	#define VMXINSTRID_SLDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2744	#define VMXINSTRID_STR (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2745	#define VMXINSTRID_LLDT (0x2 \| VMXINSTRID_VALID)
2746	#define VMXINSTRID_LTR (0x3 \| VMXINSTRID_VALID)
2747
2748	/** The following IDs are used internally (some for logging, others for conveying
2749	* the ModR/M primary operand write bit): */
2750	#define VMXINSTRID_VMLAUNCH (0x10 \| VMXINSTRID_VALID)
2751	#define VMXINSTRID_VMRESUME (0x11 \| VMXINSTRID_VALID)
2752	#define VMXINSTRID_VMREAD (0x12 \| VMXINSTRID_VALID)
2753	#define VMXINSTRID_VMWRITE (0x13 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2754	#define VMXINSTRID_IO_IN (0x14 \| VMXINSTRID_VALID)
2755	#define VMXINSTRID_IO_INS (0x15 \| VMXINSTRID_VALID)
2756	#define VMXINSTRID_IO_OUT (0x16 \| VMXINSTRID_VALID)
2757	#define VMXINSTRID_IO_OUTS (0x17 \| VMXINSTRID_VALID)
2758	#define VMXINSTRID_MOV_TO_DRX (0x18 \| VMXINSTRID_VALID)
2759	#define VMXINSTRID_MOV_FROM_DRX (0x19 \| VMXINSTRID_VALID)
2760	/** @} */
2761
2762
2763	/** @name IDT-vectoring information.
2764	* @{
2765	*/
2766	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2767	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
2768	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2769	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
2770	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2771	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2772	#define VMX_IDT_VECTORING_INFO_VALID RT_BIT(31)
2773
2774	/** Construct an IDT-vectoring information field from an VM-entry interruption
2775	* information field (same except that bit 12 is reserved). */
2776	#define VMX_IDT_VECTORING_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
2777	/** If the IDT-vectoring information field indicates a page-fault. */
2778	#define VMX_IDT_VECTORING_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
2779	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
2780	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
2781	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
2782	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT) \
2783	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_PF)))
2784	/** If the IDT-vectoring information field indicates an NMI. */
2785	#define VMX_IDT_VECTORING_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
2786	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
2787	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
2788	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
2789	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_NMI) \
2790	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_NMI)))
2791
2792
2793	/** Bit fields for IDT-vectoring information. */
2794	/** The IDT-vectoring info vector. */
2795	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2796	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2797	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
2798	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2799	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2800	/** Whether the event has an error code. */
2801	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2802	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2803	/** Bit 12 is undefined. */
2804	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2805	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2806	/** Bits 13:30 is reserved (MBZ). */
2807	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2808	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2809	/** Whether this IDT-vectoring info is valid. */
2810	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2811	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2812	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2813	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2814	/** @} */
2815
2816
2817	/** @name IDT-vectoring information vector types.
2818	* @{
2819	*/
2820	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2821	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2822	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2823	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2824	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2825	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2826	#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
2827	/** @} */
2828
2829
2830	/** @name TPR threshold.
2831	* @{ */
2832	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
2833	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
2834
2835	/** Bit fields for TPR threshold. */
2836	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
2837	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
2838	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
2839	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
2840	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
2841	(TPR, RSVD_4_31));
2842	/** @} */
2843
2844
2845	/** @name Guest-activity states.
2846	* @{
2847	*/
2848	/** The logical processor is active. */
2849	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2850	/** The logical processor is inactive, because it executed a HLT instruction. */
2851	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2852	/** The logical processor is inactive, because of a triple fault or other serious error. */
2853	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2854	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2855	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2856	/** @} */
2857
2858
2859	/** @name Guest-interruptibility states.
2860	* @{
2861	*/
2862	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2863	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2864	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2865	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2866	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
2867
2868	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
2869	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
2870	/** @} */
2871
2872
2873	/** @name Exit qualification for debug exceptions.
2874	* @{
2875	*/
2876	/** Hardware breakpoint 0 was met. */
2877	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
2878	/** Hardware breakpoint 1 was met. */
2879	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
2880	/** Hardware breakpoint 2 was met. */
2881	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
2882	/** Hardware breakpoint 3 was met. */
2883	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
2884	/** Debug register access detected. */
2885	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
2886	/** A debug exception would have been triggered by single-step execution mode. */
2887	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
2888	/** Mask of all valid bits. */
2889	#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
2890	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
2891	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
2892	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
2893	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
2894	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
2895
2896	/** Bit fields for Exit qualifications due to debug exceptions. */
2897	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
2898	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
2899	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
2900	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
2901	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
2902	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
2903	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
2904	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
2905	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
2906	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
2907	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
2908	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
2909	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
2910	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
2911	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
2912	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
2913	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
2914	(BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
2915	/** @} */
2916
2917	/** @name Exit qualification for Mov DRx.
2918	* @{
2919	*/
2920	/** 0-2: Debug register number */
2921	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
2922	/** 3: Reserved; cleared to 0. */
2923	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
2924	/** 4: Direction of move (0 = write, 1 = read) */
2925	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
2926	/** 5-7: Reserved; cleared to 0. */
2927	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
2928	/** 8-11: General purpose register number. */
2929	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
2930
2931	/** Bit fields for Exit qualification due to Mov DRx. */
2932	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
2933	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
2934	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
2935	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
2936	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
2937	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
2938	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
2939	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
2940	#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
2941	#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
2942	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
2943	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
2944	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
2945	(REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
2946	/** @} */
2947
2948
2949	/** @name Exit qualification for debug exceptions types.
2950	* @{
2951	*/
2952	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
2953	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
2954	/** @} */
2955
2956
2957	/** @name Exit qualification for control-register accesses.
2958	* @{
2959	*/
2960	/** 0-3: Control register number (0 for CLTS & LMSW) */
2961	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
2962	/** 4-5: Access type. */
2963	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
2964	/** 6: LMSW operand type memory (1 for memory, 0 for register). */
2965	#define VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(a) (((a) >> 6) & 1)
2966	/** 7: Reserved; cleared to 0. */
2967	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
2968	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
2969	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
2970	/** 12-15: Reserved; cleared to 0. */
2971	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
2972	/** 16-31: LMSW source data (else 0). */
2973	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
2974
2975	/** Bit fields for Exit qualification for control-register accesses. */
2976	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
2977	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
2978	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
2979	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
2980	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
2981	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
2982	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
2983	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
2984	#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
2985	#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
2986	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
2987	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
2988	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
2989	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
2990	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
2991	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
2992	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
2993	(REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
2994	/** @} */
2995
2996
2997	/** @name Exit qualification for control-register access types.
2998	* @{
2999	*/
3000	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
3001	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
3002	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
3003	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
3004	/** @} */
3005
3006
3007	/** @name Exit qualification for task switch.
3008	* @{
3009	*/
3010	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
3011	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
3012	/** Task switch caused by a call instruction. */
3013	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
3014	/** Task switch caused by an iret instruction. */
3015	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
3016	/** Task switch caused by a jmp instruction. */
3017	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
3018	/** Task switch caused by an interrupt gate. */
3019	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
3020
3021	/** Bit fields for Exit qualification for task switches. */
3022	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
3023	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
3024	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
3025	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
3026	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
3027	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
3028	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
3029	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3030	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
3031	(NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
3032	/** @} */
3033
3034
3035	/** @name Exit qualification for EPT violations.
3036	* @{
3037	*/
3038	/** Set if the violation was caused by a data read. */
3039	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
3040	/** Set if the violation was caused by a data write. */
3041	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
3042	/** Set if the violation was caused by an instruction fetch. */
3043	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
3044	/** AND of the present bit of all EPT structures. */
3045	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
3046	/** AND of the write bit of all EPT structures. */
3047	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
3048	/** AND of the execute bit of all EPT structures. */
3049	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
3050	/** Set if the guest linear address field contains the faulting address. */
3051	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
3052	/** If bit 7 is one: (reserved otherwise)
3053	* 1 - violation due to physical address access.
3054	* 0 - violation caused by page walk or access/dirty bit updates
3055	*/
3056	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
3057	/** NMI unblocking due to IRET. */
3058	#define VMX_EXIT_QUAL_EPT_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
3059	/** @} */
3060
3061
3062	/** @name Exit qualification for I/O instructions.
3063	* @{
3064	*/
3065	/** 0-2: IO operation size 0(=1 byte), 1(=2 bytes) and 3(=4 bytes). */
3066	#define VMX_EXIT_QUAL_IO_SIZE(a) ((a) & 7)
3067	/** 3: IO operation direction. */
3068	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
3069	/** 4: String IO operation (INS / OUTS). */
3070	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
3071	/** 5: Repeated IO operation. */
3072	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
3073	/** 6: Operand encoding. */
3074	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
3075	/** 16-31: IO Port (0-0xffff). */
3076	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
3077
3078	/** Bit fields for Exit qualification for I/O instructions. */
3079	#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
3080	#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
3081	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
3082	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
3083	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
3084	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
3085	#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
3086	#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
3087	#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
3088	#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
3089	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
3090	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
3091	#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
3092	#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
3093	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
3094	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3095	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
3096	(WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
3097	/** @} */
3098
3099
3100	/** @name Exit qualification for I/O instruction types.
3101	* @{
3102	*/
3103	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
3104	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
3105	/** @} */
3106
3107
3108	/** @name Exit qualification for I/O instruction encoding.
3109	* @{
3110	*/
3111	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
3112	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
3113	/** @} */
3114
3115
3116	/** @name Exit qualification for APIC-access VM-exits from linear and
3117	* guest-physical accesses.
3118	* @{
3119	*/
3120	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
3121	* access within the APIC page. */
3122	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
3123	/** 12-15: Access type. */
3124	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
3125	/* Rest reserved. */
3126
3127	/** Bit fields for Exit qualification for APIC-access VM-exits. */
3128	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
3129	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
3130	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
3131	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
3132	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
3133	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
3134	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
3135	(OFFSET, TYPE, RSVD_16_63));
3136	/** @} */
3137
3138
3139	/** @name Exit qualification for linear address APIC-access types.
3140	* @{
3141	*/
3142	/** Linear access for a data read during instruction execution. */
3143	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
3144	/** Linear access for a data write during instruction execution. */
3145	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
3146	/** Linear access for an instruction fetch. */
3147	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
3148	/** Linear read/write access during event delivery. */
3149	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
3150	/** Physical read/write access during event delivery. */
3151	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
3152	/** Physical access for an instruction fetch or during instruction execution. */
3153	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
3154
3155	/**
3156	* APIC-access type.
3157	* In accordance with the VT-x spec.
3158	*/
3159	typedef enum
3160	{
3161	VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
3162	VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
3163	VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
3164	VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
3165	VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
3166	VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
3167	} VMXAPICACCESS;
3168	AssertCompileSize(VMXAPICACCESS, 4);
3169	/** @} */
3170
3171
3172	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
3173	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3174	* @{
3175	*/
3176	/** Address calculation scaling field (powers of two). */
3177	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
3178	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3179	/** Bits 2 thru 6 are undefined. */
3180	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
3181	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
3182	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3183	* @remarks anyone's guess why this is a 3 bit field... */
3184	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
3185	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3186	/** Bit 10 is defined as zero. */
3187	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
3188	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
3189	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
3190	* for exits from 64-bit code as the operand size there is fixed. */
3191	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
3192	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
3193	/** Bits 12 thru 14 are undefined. */
3194	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
3195	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
3196	/** Applicable segment register (X86_SREG_XXX values). */
3197	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
3198	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3199	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3200	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
3201	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3202	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3203	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3204	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3205	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3206	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
3207	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3208	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3209	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
3210	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3211	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
3212	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
3213	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3214	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
3215	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
3216	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
3217	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
3218	/** Bits 30 & 31 are undefined. */
3219	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
3220	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3221	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3222	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
3223	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3224	/** @} */
3225
3226
3227	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
3228	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3229	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
3230	* @{
3231	*/
3232	/** Address calculation scaling field (powers of two). */
3233	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
3234	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3235	/** Bit 2 is undefined. */
3236	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
3237	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
3238	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
3239	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
3240	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
3241	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3242	* @remarks anyone's guess why this is a 3 bit field... */
3243	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
3244	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3245	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
3246	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
3247	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
3248	/** Bits 11 thru 14 are undefined. */
3249	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
3250	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
3251	/** Applicable segment register (X86_SREG_XXX values). */
3252	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
3253	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3254	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3255	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
3256	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3257	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3258	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3259	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3260	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3261	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
3262	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3263	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3264	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
3265	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3266	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
3267	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
3268	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3269	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
3270	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
3271	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
3272	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
3273	/** Bits 30 & 31 are undefined. */
3274	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3275	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3276	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3277	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3278	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3279	/** @} */
3280
3281
3282	/** @name Format of Pending-Debug-Exceptions.
3283	* Bits 4-11, 13, 15 and 17-63 are reserved.
3284	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3285	* possibly valid here but not in DR6.
3286	* @{
3287	*/
3288	/** Hardware breakpoint 0 was met. */
3289	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3290	/** Hardware breakpoint 1 was met. */
3291	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3292	/** Hardware breakpoint 2 was met. */
3293	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3294	/** Hardware breakpoint 3 was met. */
3295	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3296	/** At least one data or IO breakpoint was hit. */
3297	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3298	/** A debug exception would have been triggered by single-step execution mode. */
3299	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3300	/** A debug exception occurred inside an RTM region. */
3301	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3302	/** Mask of valid bits. */
3303	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3304	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3305	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3306	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3307	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3308	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3309	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3310	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3311	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3312	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3313	/** Bit fields for Pending debug exceptions. */
3314	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3315	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3316	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3317	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3318	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3319	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3320	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3321	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3322	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3323	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3324	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3325	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3326	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3327	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3328	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3329	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3330	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3331	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3332	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3333	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3334	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3335	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3336	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3337	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3338	/** @} */
3339
3340
3341	/** @defgroup grp_hm_vmx_virt VMX virtualization.
3342	* @{
3343	*/
3344
3345	/** @name Virtual VMX MSR - Miscellaneous data.
3346	* @{ */
3347	/** Number of CR3-target values supported. */
3348	#define VMX_V_CR3_TARGET_COUNT 4
3349	/** Activity states supported. */
3350	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3351	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3352	#define VMX_V_PREEMPT_TIMER_SHIFT 5
3353	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3354	#define VMX_V_AUTOMSR_COUNT_MAX 0
3355	/** SMM MSEG revision ID. */
3356	#define VMX_V_MSEG_REV_ID 0
3357	/** @} */
3358
3359	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS launch state.
3360	* @{ */
3361	/** VMCS launch state clear. */
3362	#define VMX_V_VMCS_LAUNCH_STATE_CLEAR RT_BIT(0)
3363	/** VMCS launch state active. */
3364	#define VMX_V_VMCS_LAUNCH_STATE_ACTIVE RT_BIT(1)
3365	/** VMCS launch state current. */
3366	#define VMX_V_VMCS_LAUNCH_STATE_CURRENT RT_BIT(2)
3367	/** VMCS launch state launched. */
3368	#define VMX_V_VMCS_LAUNCH_STATE_LAUNCHED RT_BIT(3)
3369	/** The mask of valid VMCS launch states. */
3370	#define VMX_V_VMCS_LAUNCH_STATE_MASK ( VMX_V_VMCS_LAUNCH_STATE_CLEAR \
3371	\| VMX_V_VMCS_LAUNCH_STATE_ACTIVE \
3372	\| VMX_V_VMCS_LAUNCH_STATE_CURRENT \
3373	\| VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
3374	/** @} */
3375
3376	/** CR0 bits set here must always be set when in VMX operation. */
3377	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
3378	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
3379	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
3380	/** CR4 bits set here must always be set when in VMX operation. */
3381	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3382
3383	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3384	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3385	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001)
3386	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3387
3388	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3389	* complications when teleporation may be implemented). */
3390	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3391	/** The size of the virtual VMCS region (in pages). */
3392	#define VMX_V_VMCS_PAGES 1
3393
3394	/** The size of the virtual shadow VMCS region. */
3395	#define VMX_V_SHADOW_VMCS_SIZE VMX_V_VMCS_SIZE
3396	/** The size of the virtual shadow VMCS region (in pages). */
3397	#define VMX_V_SHADOW_VMCS_PAGES VMX_V_VMCS_PAGES
3398
3399	/** The size of the Virtual-APIC page (in bytes). */
3400	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3401	/** The size of the Virtual-APIC page (in pages). */
3402	#define VMX_V_VIRT_APIC_PAGES 1
3403
3404	/** Virtual X2APIC MSR range start. */
3405	#define VMX_V_VIRT_APIC_MSR_START 0x800
3406	/** Virtual X2APIC MSR range end. */
3407	#define VMX_V_VIRT_APIC_MSR_END 0x8ff
3408
3409	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3410	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3411	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3412	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3413
3414	/** The size of the MSR bitmap (in bytes). */
3415	#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3416	/** The size of the MSR bitmap (in pages). */
3417	#define VMX_V_MSR_BITMAP_PAGES 1
3418
3419	/** The size of I/O bitmap A (in bytes). */
3420	#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3421	/** The size of I/O bitmap A (in pages). */
3422	#define VMX_V_IO_BITMAP_A_PAGES 1
3423
3424	/** The size of I/O bitmap B (in bytes). */
3425	#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3426	/** The size of I/O bitmap B (in pages). */
3427	#define VMX_V_IO_BITMAP_B_PAGES 1
3428
3429	/** The size of the auto-load/store MSR area (in bytes). */
3430	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3431	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3432	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3433	/** The size of the auto-load/store MSR area (in pages). */
3434	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3435
3436	/** The highest index value used for supported virtual VMCS field encoding. */
3437	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCSFIELD_INDEX)
3438
3439	/**
3440	* Virtual VM-exit information.
3441	*
3442	* This is a convenience structure that bundles some VM-exit information related
3443	* fields together.
3444	*/
3445	typedef struct
3446	{
3447	/** The VM-exit reason. */
3448	uint32_t uReason;
3449	/** The VM-exit instruction length. */
3450	uint32_t cbInstr;
3451	/** The VM-exit instruction information. */
3452	VMXEXITINSTRINFO InstrInfo;
3453	/** The VM-exit instruction ID. */
3454	VMXINSTRID uInstrId;
3455
3456	/** The Exit qualification field. */
3457	uint64_t u64Qual;
3458	/** The Guest-linear address field. */
3459	uint64_t u64GuestLinearAddr;
3460	/** The Guest-physical address field. */
3461	uint64_t u64GuestPhysAddr;
3462	/** The guest pending-debug exceptions. */
3463	uint64_t u64GuestPendingDbgXcpts;
3464	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3465	* instruction VM-exit. */
3466	RTGCPTR GCPtrEffAddr;
3467	} VMXVEXITINFO;
3468	/** Pointer to the VMXVEXITINFO struct. */
3469	typedef VMXVEXITINFO *PVMXVEXITINFO;
3470	/** Pointer to a const VMXVEXITINFO struct. */
3471	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3472	AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3473
3474	/**
3475	* Virtual VM-exit information for events.
3476	*
3477	* This is a convenience structure that bundles some event-based VM-exit information
3478	* related fields together that are not included in VMXVEXITINFO.
3479	*
3480	* This is kept as a separate structure and not included in VMXVEXITINFO, to make it
3481	* easier to distinguish that IEM VM-exit handlers will set one or more of the
3482	* following fields in the virtual VMCS. Including it in the VMXVEXITINFO will not
3483	* make it ovbious which fields may get set (or cleared).
3484	*/
3485	typedef struct
3486	{
3487	/** VM-exit interruption information. */
3488	uint32_t uExitIntInfo;
3489	/** VM-exit interruption error code. */
3490	uint32_t uExitIntErrCode;
3491	/** IDT-vectoring information. */
3492	uint32_t uIdtVectoringInfo;
3493	/** IDT-vectoring error code. */
3494	uint32_t uIdtVectoringErrCode;
3495	} VMXVEXITEVENTINFO;
3496	/** Pointer to the VMXVEXITINFO2 struct. */
3497	typedef VMXVEXITEVENTINFO *PVMXVEXITEVENTINFO;
3498	/** Pointer to a const VMXVEXITINFO2 struct. */
3499	typedef const VMXVEXITEVENTINFO *PCVMXVEXITEVENTINFO;
3500
3501	/**
3502	* Virtual VMCS.
3503	*
3504	* This is our custom format. Relevant fields from this VMCS will be merged into the
3505	* actual/shadow VMCS when we execute nested-guest code using hardware-assisted
3506	* VMX.
3507	*
3508	* The first 8 bytes must be in accordance with the Intel VT-x spec.
3509	* See Intel spec. 24.2 "Format of the VMCS Region".
3510	*
3511	* The offset and size of the VMCS state field (@a fVmcsState) is also fixed (not by
3512	* the Intel spec. but for our own requirements) as we use it to offset into guest
3513	* memory.
3514	*
3515	* Although the guest is supposed to access the VMCS only through the execution of
3516	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3517	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
3518	* for teleportation purposes, any newly added fields should be added to the
3519	* appropriate reserved sections or at the end of the structure.
3520	*
3521	* We always treat natural-width fields as 64-bit in our implementation since
3522	* it's easier, allows for teleporation in the future and does not affect guest
3523	* software.
3524	*
3525	* Note! Any fields that are added or modified here, make sure to update the
3526	* corresponding fields in IEM (g_aoffVmcsMap), the corresponding saved
3527	* state structure in CPUM (g_aVmxHwvirtVmcs) and bump the SSM version.
3528	* Also consider updating CPUMIsGuestVmxVmcsFieldValid.
3529	*/
3530	#pragma pack(1)
3531	typedef struct
3532	{
3533	/** @name Header.
3534	* @{
3535	*/
3536	VMXVMCSREVID u32VmcsRevId; /*< 0x000 - VMX VMCS revision identifier. /
3537	VMXABORT enmVmxAbort; /*< 0x004 - VMX-abort indicator. /
3538	uint8_t fVmcsState; /*< 0x008 - VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. /
3539	uint8_t au8Padding0[3]; /*< 0x009 - Reserved for future. /
3540	uint32_t au32Reserved0[12]; /*< 0x00c - Reserved for future. /
3541	/** @} */
3542
3543	/** @name Read-only fields.
3544	* @{ */
3545	/** 16-bit fields. */
3546	uint16_t u16Reserved0[14]; /*< 0x03c - Reserved for future. /
3547
3548	/** 32-bit fields. */
3549	uint32_t u32RoVmInstrError; /*< 0x058 - VM-instruction error. /
3550	uint32_t u32RoExitReason; /*< 0x05c - VM-exit reason. /
3551	uint32_t u32RoExitIntInfo; /*< 0x060 - VM-exit interruption information. /
3552	uint32_t u32RoExitIntErrCode; /*< 0x064 - VM-exit interruption error code. /
3553	uint32_t u32RoIdtVectoringInfo; /*< 0x068 - IDT-vectoring information. /
3554	uint32_t u32RoIdtVectoringErrCode; /*< 0x06c - IDT-vectoring error code. /
3555	uint32_t u32RoExitInstrLen; /*< 0x070 - VM-exit instruction length. /
3556	uint32_t u32RoExitInstrInfo; /*< 0x074 - VM-exit instruction information. /
3557	uint32_t au32RoReserved2[16]; /*< 0x078 - Reserved for future. /
3558
3559	/** 64-bit fields. */
3560	RTUINT64U u64RoGuestPhysAddr; /*< 0x0b8 - Guest-physical address. /
3561	RTUINT64U au64Reserved1[8]; /*< 0x0c0 - Reserved for future. /
3562
3563	/** Natural-width fields. */
3564	RTUINT64U u64RoExitQual; /*< 0x100 - Exit qualification. /
3565	RTUINT64U u64RoIoRcx; /*< 0x108 - I/O RCX. /
3566	RTUINT64U u64RoIoRsi; /*< 0x110 - I/O RSI. /
3567	RTUINT64U u64RoIoRdi; /*< 0x118 - I/O RDI. /
3568	RTUINT64U u64RoIoRip; /*< 0x120 - I/O RIP. /
3569	RTUINT64U u64RoGuestLinearAddr; /*< 0x128 - Guest-linear address. /
3570	RTUINT64U au64Reserved5[16]; /*< 0x130 - Reserved for future. /
3571	/** @} */
3572
3573	/** @name Control fields.
3574	* @{ */
3575	/** 16-bit fields. */
3576	uint16_t u16Vpid; /*< 0x1b0 - Virtual processor ID. /
3577	uint16_t u16PostIntNotifyVector; /*< 0x1b2 - Posted interrupt notify vector. /
3578	uint16_t u16EptpIndex; /*< 0x1b4 - EPTP index. /
3579	uint16_t au16Reserved0[13]; /*< 0x1b6 - Reserved for future. /
3580
3581	/** 32-bit fields. */
3582	uint32_t u32PinCtls; /*< 0x1d0 - Pin-based VM-execution controls. /
3583	uint32_t u32ProcCtls; /*< 0x1d4 - Processor-based VM-execution controls. /
3584	uint32_t u32XcptBitmap; /*< 0x1d8 - Exception bitmap. /
3585	uint32_t u32XcptPFMask; /*< 0x1dc - Page-fault exception error mask. /
3586	uint32_t u32XcptPFMatch; /*< 0x1e0 - Page-fault exception error match. /
3587	uint32_t u32Cr3TargetCount; /*< 0x1e4 - CR3-target count. /
3588	uint32_t u32ExitCtls; /*< 0x1e8 - VM-exit controls. /
3589	uint32_t u32ExitMsrStoreCount; /*< 0x1ec - VM-exit MSR store count. /
3590	uint32_t u32ExitMsrLoadCount; /*< 0x1f0 - VM-exit MSR load count. /
3591	uint32_t u32EntryCtls; /*< 0x1f4 - VM-entry controls. /
3592	uint32_t u32EntryMsrLoadCount; /*< 0x1f8 - VM-entry MSR load count. /
3593	uint32_t u32EntryIntInfo; /*< 0x1fc - VM-entry interruption information. /
3594	uint32_t u32EntryXcptErrCode; /*< 0x200 - VM-entry exception error code. /
3595	uint32_t u32EntryInstrLen; /*< 0x204 - VM-entry instruction length. /
3596	uint32_t u32TprThreshold; /*< 0x208 - TPR-threshold. /
3597	uint32_t u32ProcCtls2; /*< 0x20c - Secondary-processor based VM-execution controls. /
3598	uint32_t u32PleGap; /*< 0x210 - Pause-loop exiting Gap. /
3599	uint32_t u32PleWindow; /*< 0x214 - Pause-loop exiting Window. /
3600	uint32_t au32Reserved1[16]; /*< 0x218 - Reserved for future. /
3601
3602	/** 64-bit fields. */
3603	RTUINT64U u64AddrIoBitmapA; /*< 0x258 - I/O bitmap A address. /
3604	RTUINT64U u64AddrIoBitmapB; /*< 0x260 - I/O bitmap B address. /
3605	RTUINT64U u64AddrMsrBitmap; /*< 0x268 - MSR bitmap address. /
3606	RTUINT64U u64AddrExitMsrStore; /*< 0x270 - VM-exit MSR-store area address. /
3607	RTUINT64U u64AddrExitMsrLoad; /*< 0x278 - VM-exit MSR-load area address. /
3608	RTUINT64U u64AddrEntryMsrLoad; /*< 0x280 - VM-entry MSR-load area address. /
3609	RTUINT64U u64ExecVmcsPtr; /*< 0x288 - Executive-VMCS pointer. /
3610	RTUINT64U u64AddrPml; /*< 0x290 - PML address. /
3611	RTUINT64U u64TscOffset; /*< 0x298 - TSC offset. /
3612	RTUINT64U u64AddrVirtApic; /*< 0x2a0 - Virtual-APIC address. /
3613	RTUINT64U u64AddrApicAccess; /*< 0x2a8 - APIC-access address. /
3614	RTUINT64U u64AddrPostedIntDesc; /*< 0x2b0 - Posted-interrupt descriptor address. /
3615	RTUINT64U u64VmFuncCtls; /*< 0x2b8 - VM-functions control. /
3616	RTUINT64U u64EptpPtr; /*< 0x2c0 - EPTP pointer. /
3617	RTUINT64U u64EoiExitBitmap0; /*< 0x2c8 - EOI-exit bitmap 0. /
3618	RTUINT64U u64EoiExitBitmap1; /*< 0x2d0 - EOI-exit bitmap 1. /
3619	RTUINT64U u64EoiExitBitmap2; /*< 0x2d8 - EOI-exit bitmap 2. /
3620	RTUINT64U u64EoiExitBitmap3; /*< 0x2e0 - EOI-exit bitmap 3. /
3621	RTUINT64U u64AddrEptpList; /*< 0x2e8 - EPTP-list address. /
3622	RTUINT64U u64AddrVmreadBitmap; /*< 0x2f0 - VMREAD-bitmap address. /
3623	RTUINT64U u64AddrVmwriteBitmap; /*< 0x2f8 - VMWRITE-bitmap address. /
3624	RTUINT64U u64AddrXcptVeInfo; /*< 0x300 - Virtualization-exception information address. /
3625	RTUINT64U u64XssBitmap; /*< 0x308 - XSS-exiting bitmap. /
3626	RTUINT64U u64EnclsBitmap; /*< 0x310 - ENCLS-exiting bitmap address. /
3627	RTUINT64U u64SpptPtr; /*< 0x318 - Sub-page-permission-table pointer. /
3628	RTUINT64U u64TscMultiplier; /*< 0x320 - TSC multiplier. /
3629	RTUINT64U au64Reserved0[15]; /*< 0x328 - Reserved for future. /
3630
3631	/** Natural-width fields. */
3632	RTUINT64U u64Cr0Mask; /*< 0x3a0 - CR0 guest/host Mask. /
3633	RTUINT64U u64Cr4Mask; /*< 0x3a8 - CR4 guest/host Mask. /
3634	RTUINT64U u64Cr0ReadShadow; /*< 0x3b0 - CR0 read shadow. /
3635	RTUINT64U u64Cr4ReadShadow; /*< 0x3b8 - CR4 read shadow. /
3636	RTUINT64U u64Cr3Target0; /*< 0x3c0 - CR3-target value 0. /
3637	RTUINT64U u64Cr3Target1; /*< 0x3c8 - CR3-target value 1. /
3638	RTUINT64U u64Cr3Target2; /*< 0x3d0 - CR3-target value 2. /
3639	RTUINT64U u64Cr3Target3; /*< 0x3d8 - CR3-target value 3. /
3640	RTUINT64U au64Reserved4[32]; /*< 0x3e0 - Reserved for future. /
3641	/** @} */
3642
3643	/** @name Host-state fields.
3644	* @{ */
3645	/** 16-bit fields. */
3646	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3647	RTSEL HostEs; /*< 0x4e0 - Host ES selector. /
3648	RTSEL HostCs; /*< 0x4e2 - Host CS selector. /
3649	RTSEL HostSs; /*< 0x4e4 - Host SS selector. /
3650	RTSEL HostDs; /*< 0x4e6 - Host DS selector. /
3651	RTSEL HostFs; /*< 0x4e8 - Host FS selector. /
3652	RTSEL HostGs; /*< 0x4ea - Host GS selector. /
3653	RTSEL HostTr; /*< 0x4ec - Host TR selector. /
3654	uint16_t au16Reserved2[13]; /*< 0x4ee - Reserved for future. /
3655
3656	/** 32-bit fields. */
3657	uint32_t u32HostSysenterCs; /*< 0x508 - Host SYSENTER CS. /
3658	uint32_t au32Reserved4[11]; /*< 0x50c - Reserved for future. /
3659
3660	/** 64-bit fields. */
3661	RTUINT64U u64HostPatMsr; /*< 0x538 - Host PAT MSR. /
3662	RTUINT64U u64HostEferMsr; /*< 0x540 - Host EFER MSR. /
3663	RTUINT64U u64HostPerfGlobalCtlMsr; /*< 0x548 - Host global performance-control MSR. /
3664	RTUINT64U au64Reserved3[16]; /*< 0x550 - Reserved for future. /
3665
3666	/** Natural-width fields. */
3667	RTUINT64U u64HostCr0; /*< 0x5d0 - Host CR0. /
3668	RTUINT64U u64HostCr3; /*< 0x5d8 - Host CR3. /
3669	RTUINT64U u64HostCr4; /*< 0x5e0 - Host CR4. /
3670	RTUINT64U u64HostFsBase; /*< 0x5e8 - Host FS base. /
3671	RTUINT64U u64HostGsBase; /*< 0x5f0 - Host GS base. /
3672	RTUINT64U u64HostTrBase; /*< 0x5f8 - Host TR base. /
3673	RTUINT64U u64HostGdtrBase; /*< 0x600 - Host GDTR base. /
3674	RTUINT64U u64HostIdtrBase; /*< 0x608 - Host IDTR base. /
3675	RTUINT64U u64HostSysenterEsp; /*< 0x610 - Host SYSENTER ESP base. /
3676	RTUINT64U u64HostSysenterEip; /*< 0x618 - Host SYSENTER ESP base. /
3677	RTUINT64U u64HostRsp; /*< 0x620 - Host RSP. /
3678	RTUINT64U u64HostRip; /*< 0x628 - Host RIP. /
3679	RTUINT64U au64Reserved7[32]; /*< 0x630 - Reserved for future. /
3680	/** @} */
3681
3682	/** @name Guest-state fields.
3683	* @{ */
3684	/** 16-bit fields. */
3685	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3686	RTSEL GuestEs; /*< 0x730 - Guest ES selector. /
3687	RTSEL GuestCs; /*< 0x732 - Guest ES selector. /
3688	RTSEL GuestSs; /*< 0x734 - Guest ES selector. /
3689	RTSEL GuestDs; /*< 0x736 - Guest ES selector. /
3690	RTSEL GuestFs; /*< 0x738 - Guest ES selector. /
3691	RTSEL GuestGs; /*< 0x73a - Guest ES selector. /
3692	RTSEL GuestLdtr; /*< 0x73c - Guest LDTR selector. /
3693	RTSEL GuestTr; /*< 0x73e - Guest TR selector. /
3694	uint16_t u16GuestIntStatus; /*< 0x740 - Guest interrupt status (virtual-interrupt delivery). /
3695	uint16_t u16PmlIndex; /*< 0x742 - PML index. /
3696	uint16_t au16Reserved1[14]; /*< 0x744 - Reserved for future. /
3697
3698	/** 32-bit fields. */
3699	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3700	uint32_t u32GuestEsLimit; /*< 0x760 - Guest ES limit. /
3701	uint32_t u32GuestCsLimit; /*< 0x764 - Guest CS limit. /
3702	uint32_t u32GuestSsLimit; /*< 0x768 - Guest SS limit. /
3703	uint32_t u32GuestDsLimit; /*< 0x76c - Guest DS limit. /
3704	uint32_t u32GuestFsLimit; /*< 0x770 - Guest FS limit. /
3705	uint32_t u32GuestGsLimit; /*< 0x774 - Guest GS limit. /
3706	uint32_t u32GuestLdtrLimit; /*< 0x778 - Guest LDTR limit. /
3707	uint32_t u32GuestTrLimit; /*< 0x77c - Guest TR limit. /
3708	uint32_t u32GuestGdtrLimit; /*< 0x780 - Guest GDTR limit. /
3709	uint32_t u32GuestIdtrLimit; /*< 0x784 - Guest IDTR limit. /
3710	uint32_t u32GuestEsAttr; /*< 0x788 - Guest ES attributes. /
3711	uint32_t u32GuestCsAttr; /*< 0x78c - Guest CS attributes. /
3712	uint32_t u32GuestSsAttr; /*< 0x790 - Guest SS attributes. /
3713	uint32_t u32GuestDsAttr; /*< 0x794 - Guest DS attributes. /
3714	uint32_t u32GuestFsAttr; /*< 0x798 - Guest FS attributes. /
3715	uint32_t u32GuestGsAttr; /*< 0x79c - Guest GS attributes. /
3716	uint32_t u32GuestLdtrAttr; /*< 0x7a0 - Guest LDTR attributes. /
3717	uint32_t u32GuestTrAttr; /*< 0x7a4 - Guest TR attributes. /
3718	uint32_t u32GuestIntrState; /*< 0x7a8 - Guest interruptibility state. /
3719	uint32_t u32GuestActivityState; /*< 0x7ac - Guest activity state. /
3720	uint32_t u32GuestSmBase; /*< 0x7b0 - Guest SMBASE. /
3721	uint32_t u32GuestSysenterCS; /*< 0x7b4 - Guest SYSENTER CS. /
3722	uint32_t u32PreemptTimer; /*< 0x7b8 - Preemption timer value. /
3723	uint32_t au32Reserved3[11]; /*< 0x7bc - Reserved for future. /
3724
3725	/** 64-bit fields. */
3726	RTUINT64U u64VmcsLinkPtr; /*< 0x7e8 - VMCS link pointer. /
3727	RTUINT64U u64GuestDebugCtlMsr; /*< 0x7f0 - Guest debug-control MSR. /
3728	RTUINT64U u64GuestPatMsr; /*< 0x7f8 - Guest PAT MSR. /
3729	RTUINT64U u64GuestEferMsr; /*< 0x800 - Guest EFER MSR. /
3730	RTUINT64U u64GuestPerfGlobalCtlMsr; /*< 0x808 - Guest global performance-control MSR. /
3731	RTUINT64U u64GuestPdpte0; /*< 0x810 - Guest PDPTE 0. /
3732	RTUINT64U u64GuestPdpte1; /*< 0x818 - Guest PDPTE 0. /
3733	RTUINT64U u64GuestPdpte2; /*< 0x820 - Guest PDPTE 1. /
3734	RTUINT64U u64GuestPdpte3; /*< 0x828 - Guest PDPTE 2. /
3735	RTUINT64U u64GuestBndcfgsMsr; /*< 0x830 - Guest Bounds config MPX MSR (Intel Memory Protection Extensions). /
3736	RTUINT64U u64GuestRtitCtlMsr; /*< 0x838 - Guest RTIT control MSR (Intel Real Time Instruction Trace). /
3737	RTUINT64U au64Reserved2[32]; /*< 0x840 - Reserved for future. /
3738
3739	/** Natural-width fields. */
3740	RTUINT64U u64GuestCr0; /*< 0x940 - Guest CR0. /
3741	RTUINT64U u64GuestCr3; /*< 0x948 - Guest CR3. /
3742	RTUINT64U u64GuestCr4; /*< 0x950 - Guest CR4. /
3743	RTUINT64U u64GuestEsBase; /*< 0x958 - Guest ES base. /
3744	RTUINT64U u64GuestCsBase; /*< 0x960 - Guest CS base. /
3745	RTUINT64U u64GuestSsBase; /*< 0x968 - Guest SS base. /
3746	RTUINT64U u64GuestDsBase; /*< 0x970 - Guest DS base. /
3747	RTUINT64U u64GuestFsBase; /*< 0x978 - Guest FS base. /
3748	RTUINT64U u64GuestGsBase; /*< 0x980 - Guest GS base. /
3749	RTUINT64U u64GuestLdtrBase; /*< 0x988 - Guest LDTR base. /
3750	RTUINT64U u64GuestTrBase; /*< 0x990 - Guest TR base. /
3751	RTUINT64U u64GuestGdtrBase; /*< 0x998 - Guest GDTR base. /
3752	RTUINT64U u64GuestIdtrBase; /*< 0x9a0 - Guest IDTR base. /
3753	RTUINT64U u64GuestDr7; /*< 0x9a8 - Guest DR7. /
3754	RTUINT64U u64GuestRsp; /*< 0x9b0 - Guest RSP. /
3755	RTUINT64U u64GuestRip; /*< 0x9b8 - Guest RIP. /
3756	RTUINT64U u64GuestRFlags; /*< 0x9c0 - Guest RFLAGS. /
3757	RTUINT64U u64GuestPendingDbgXcpts; /*< 0x9c8 - Guest pending debug exceptions. /
3758	RTUINT64U u64GuestSysenterEsp; /*< 0x9d0 - Guest SYSENTER ESP. /
3759	RTUINT64U u64GuestSysenterEip; /*< 0x9d8 - Guest SYSENTER EIP. /
3760	RTUINT64U au64Reserved6[32]; /*< 0x9e0 - Reserved for future. /
3761	/** @} */
3762
3763	/** 0xae0 - Padding / reserved for future use. */
3764	uint8_t abPadding[X86_PAGE_4K_SIZE - 0xae0];
3765	} VMXVVMCS;
3766	#pragma pack()
3767	/** Pointer to the VMXVVMCS struct. */
3768	typedef VMXVVMCS *PVMXVVMCS;
3769	/** Pointer to a const VMXVVMCS struct. */
3770	typedef const VMXVVMCS *PCVMXVVMCS;
3771	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
3772	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
3773	AssertCompileMemberOffset(VMXVVMCS, enmVmxAbort, 0x004);
3774	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
3775	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x058);
3776	AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x0b8);
3777	AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x100);
3778	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x1b0);
3779	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x1d0);
3780	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x258);
3781	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x3a0);
3782	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x4e0);
3783	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x508);
3784	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x538);
3785	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x5d0);
3786	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x730);
3787	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x760);
3788	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x7e8);
3789	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x940);
3790
3791	/**
3792	* Virtual VMX-instruction and VM-exit diagnostics.
3793	*
3794	* These are not the same as VM instruction errors that are enumerated in the Intel
3795	* spec. These are purely internal, fine-grained definitions used for diagnostic
3796	* purposes and are not reported to guest software under the VM-instruction error
3797	* field in its VMCS.
3798	*
3799	* @note Members of this enum are used as array indices, so no gaps are allowed.
3800	* Please update g_apszVmxVDiagDesc when you add new fields to this enum.
3801	*/
3802	typedef enum
3803	{
3804	/* Internal processing errors. */
3805	kVmxVDiag_None = 0,
3806	kVmxVDiag_Ipe_1,
3807	kVmxVDiag_Ipe_2,
3808	kVmxVDiag_Ipe_3,
3809	kVmxVDiag_Ipe_4,
3810	kVmxVDiag_Ipe_5,
3811	kVmxVDiag_Ipe_6,
3812	kVmxVDiag_Ipe_7,
3813	kVmxVDiag_Ipe_8,
3814	kVmxVDiag_Ipe_9,
3815	kVmxVDiag_Ipe_10,
3816	kVmxVDiag_Ipe_11,
3817	kVmxVDiag_Ipe_12,
3818	kVmxVDiag_Ipe_13,
3819	kVmxVDiag_Ipe_14,
3820	kVmxVDiag_Ipe_15,
3821	kVmxVDiag_Ipe_16,
3822	/* VMXON. */
3823	kVmxVDiag_Vmxon_A20M,
3824	kVmxVDiag_Vmxon_Cpl,
3825	kVmxVDiag_Vmxon_Cr0Fixed0,
3826	kVmxVDiag_Vmxon_Cr0Fixed1,
3827	kVmxVDiag_Vmxon_Cr4Fixed0,
3828	kVmxVDiag_Vmxon_Cr4Fixed1,
3829	kVmxVDiag_Vmxon_Intercept,
3830	kVmxVDiag_Vmxon_LongModeCS,
3831	kVmxVDiag_Vmxon_MsrFeatCtl,
3832	kVmxVDiag_Vmxon_PtrAbnormal,
3833	kVmxVDiag_Vmxon_PtrAlign,
3834	kVmxVDiag_Vmxon_PtrMap,
3835	kVmxVDiag_Vmxon_PtrReadPhys,
3836	kVmxVDiag_Vmxon_PtrWidth,
3837	kVmxVDiag_Vmxon_RealOrV86Mode,
3838	kVmxVDiag_Vmxon_ShadowVmcs,
3839	kVmxVDiag_Vmxon_VmxAlreadyRoot,
3840	kVmxVDiag_Vmxon_Vmxe,
3841	kVmxVDiag_Vmxon_VmcsRevId,
3842	kVmxVDiag_Vmxon_VmxRootCpl,
3843	/* VMXOFF. */
3844	kVmxVDiag_Vmxoff_Cpl,
3845	kVmxVDiag_Vmxoff_Intercept,
3846	kVmxVDiag_Vmxoff_LongModeCS,
3847	kVmxVDiag_Vmxoff_RealOrV86Mode,
3848	kVmxVDiag_Vmxoff_Vmxe,
3849	kVmxVDiag_Vmxoff_VmxRoot,
3850	/* VMPTRLD. */
3851	kVmxVDiag_Vmptrld_Cpl,
3852	kVmxVDiag_Vmptrld_LongModeCS,
3853	kVmxVDiag_Vmptrld_PtrAbnormal,
3854	kVmxVDiag_Vmptrld_PtrAlign,
3855	kVmxVDiag_Vmptrld_PtrMap,
3856	kVmxVDiag_Vmptrld_PtrReadPhys,
3857	kVmxVDiag_Vmptrld_PtrVmxon,
3858	kVmxVDiag_Vmptrld_PtrWidth,
3859	kVmxVDiag_Vmptrld_RealOrV86Mode,
3860	kVmxVDiag_Vmptrld_RevPtrReadPhys,
3861	kVmxVDiag_Vmptrld_ShadowVmcs,
3862	kVmxVDiag_Vmptrld_VmcsRevId,
3863	kVmxVDiag_Vmptrld_VmxRoot,
3864	/* VMPTRST. */
3865	kVmxVDiag_Vmptrst_Cpl,
3866	kVmxVDiag_Vmptrst_LongModeCS,
3867	kVmxVDiag_Vmptrst_PtrMap,
3868	kVmxVDiag_Vmptrst_RealOrV86Mode,
3869	kVmxVDiag_Vmptrst_VmxRoot,
3870	/* VMCLEAR. */
3871	kVmxVDiag_Vmclear_Cpl,
3872	kVmxVDiag_Vmclear_LongModeCS,
3873	kVmxVDiag_Vmclear_PtrAbnormal,
3874	kVmxVDiag_Vmclear_PtrAlign,
3875	kVmxVDiag_Vmclear_PtrMap,
3876	kVmxVDiag_Vmclear_PtrReadPhys,
3877	kVmxVDiag_Vmclear_PtrVmxon,
3878	kVmxVDiag_Vmclear_PtrWidth,
3879	kVmxVDiag_Vmclear_RealOrV86Mode,
3880	kVmxVDiag_Vmclear_VmxRoot,
3881	/* VMWRITE. */
3882	kVmxVDiag_Vmwrite_Cpl,
3883	kVmxVDiag_Vmwrite_FieldInvalid,
3884	kVmxVDiag_Vmwrite_FieldRo,
3885	kVmxVDiag_Vmwrite_LinkPtrInvalid,
3886	kVmxVDiag_Vmwrite_LongModeCS,
3887	kVmxVDiag_Vmwrite_PtrInvalid,
3888	kVmxVDiag_Vmwrite_PtrMap,
3889	kVmxVDiag_Vmwrite_RealOrV86Mode,
3890	kVmxVDiag_Vmwrite_VmxRoot,
3891	/* VMREAD. */
3892	kVmxVDiag_Vmread_Cpl,
3893	kVmxVDiag_Vmread_FieldInvalid,
3894	kVmxVDiag_Vmread_LinkPtrInvalid,
3895	kVmxVDiag_Vmread_LongModeCS,
3896	kVmxVDiag_Vmread_PtrInvalid,
3897	kVmxVDiag_Vmread_PtrMap,
3898	kVmxVDiag_Vmread_RealOrV86Mode,
3899	kVmxVDiag_Vmread_VmxRoot,
3900	/* INVVPID. */
3901	kVmxVDiag_Invvpid_Cpl,
3902	kVmxVDiag_Invvpid_DescRsvd,
3903	kVmxVDiag_Invvpid_LongModeCS,
3904	kVmxVDiag_Invvpid_RealOrV86Mode,
3905	kVmxVDiag_Invvpid_TypeInvalid,
3906	kVmxVDiag_Invvpid_Type0InvalidAddr,
3907	kVmxVDiag_Invvpid_Type0InvalidVpid,
3908	kVmxVDiag_Invvpid_Type1InvalidVpid,
3909	kVmxVDiag_Invvpid_Type3InvalidVpid,
3910	kVmxVDiag_Invvpid_VmxRoot,
3911	/* VMLAUNCH/VMRESUME. */
3912	kVmxVDiag_Vmentry_AddrApicAccess,
3913	kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
3914	kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
3915	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
3916	kVmxVDiag_Vmentry_AddrExitMsrLoad,
3917	kVmxVDiag_Vmentry_AddrExitMsrStore,
3918	kVmxVDiag_Vmentry_AddrIoBitmapA,
3919	kVmxVDiag_Vmentry_AddrIoBitmapB,
3920	kVmxVDiag_Vmentry_AddrMsrBitmap,
3921	kVmxVDiag_Vmentry_AddrVirtApicPage,
3922	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
3923	kVmxVDiag_Vmentry_AddrVmreadBitmap,
3924	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
3925	kVmxVDiag_Vmentry_ApicRegVirt,
3926	kVmxVDiag_Vmentry_BlocKMovSS,
3927	kVmxVDiag_Vmentry_Cpl,
3928	kVmxVDiag_Vmentry_Cr3TargetCount,
3929	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
3930	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
3931	kVmxVDiag_Vmentry_EntryInstrLen,
3932	kVmxVDiag_Vmentry_EntryInstrLenZero,
3933	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
3934	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
3935	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
3936	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
3937	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
3938	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
3939	kVmxVDiag_Vmentry_GuestActStateHlt,
3940	kVmxVDiag_Vmentry_GuestActStateRsvd,
3941	kVmxVDiag_Vmentry_GuestActStateShutdown,
3942	kVmxVDiag_Vmentry_GuestActStateSsDpl,
3943	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
3944	kVmxVDiag_Vmentry_GuestCr0Fixed0,
3945	kVmxVDiag_Vmentry_GuestCr0Fixed1,
3946	kVmxVDiag_Vmentry_GuestCr0PgPe,
3947	kVmxVDiag_Vmentry_GuestCr3,
3948	kVmxVDiag_Vmentry_GuestCr4Fixed0,
3949	kVmxVDiag_Vmentry_GuestCr4Fixed1,
3950	kVmxVDiag_Vmentry_GuestDebugCtl,
3951	kVmxVDiag_Vmentry_GuestDr7,
3952	kVmxVDiag_Vmentry_GuestEferMsr,
3953	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
3954	kVmxVDiag_Vmentry_GuestGdtrBase,
3955	kVmxVDiag_Vmentry_GuestGdtrLimit,
3956	kVmxVDiag_Vmentry_GuestIdtrBase,
3957	kVmxVDiag_Vmentry_GuestIdtrLimit,
3958	kVmxVDiag_Vmentry_GuestIntStateEnclave,
3959	kVmxVDiag_Vmentry_GuestIntStateExtInt,
3960	kVmxVDiag_Vmentry_GuestIntStateNmi,
3961	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
3962	kVmxVDiag_Vmentry_GuestIntStateRsvd,
3963	kVmxVDiag_Vmentry_GuestIntStateSmi,
3964	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
3965	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
3966	kVmxVDiag_Vmentry_GuestPae,
3967	kVmxVDiag_Vmentry_GuestPatMsr,
3968	kVmxVDiag_Vmentry_GuestPcide,
3969	kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys,
3970	kVmxVDiag_Vmentry_GuestPdpte0Rsvd,
3971	kVmxVDiag_Vmentry_GuestPdpte1Rsvd,
3972	kVmxVDiag_Vmentry_GuestPdpte2Rsvd,
3973	kVmxVDiag_Vmentry_GuestPdpte3Rsvd,
3974	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
3975	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
3976	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
3977	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
3978	kVmxVDiag_Vmentry_GuestRip,
3979	kVmxVDiag_Vmentry_GuestRipRsvd,
3980	kVmxVDiag_Vmentry_GuestRFlagsIf,
3981	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
3982	kVmxVDiag_Vmentry_GuestRFlagsVm,
3983	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
3984	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
3985	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
3986	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
3987	kVmxVDiag_Vmentry_GuestSegAttrCsType,
3988	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
3989	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
3990	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
3991	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
3992	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
3993	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
3994	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
3995	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
3996	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
3997	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
3998	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
3999	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
4000	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
4001	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
4002	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
4003	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
4004	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
4005	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
4006	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
4007	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
4008	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
4009	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
4010	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
4011	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
4012	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
4013	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
4014	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
4015	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
4016	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
4017	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
4018	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
4019	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
4020	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
4021	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
4022	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
4023	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
4024	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
4025	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
4026	kVmxVDiag_Vmentry_GuestSegAttrSsType,
4027	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
4028	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
4029	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
4030	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
4031	kVmxVDiag_Vmentry_GuestSegAttrTrType,
4032	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
4033	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
4034	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
4035	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
4036	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
4037	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
4038	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
4039	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
4040	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
4041	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
4042	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
4043	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
4044	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
4045	kVmxVDiag_Vmentry_GuestSegBaseCs,
4046	kVmxVDiag_Vmentry_GuestSegBaseDs,
4047	kVmxVDiag_Vmentry_GuestSegBaseEs,
4048	kVmxVDiag_Vmentry_GuestSegBaseFs,
4049	kVmxVDiag_Vmentry_GuestSegBaseGs,
4050	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
4051	kVmxVDiag_Vmentry_GuestSegBaseSs,
4052	kVmxVDiag_Vmentry_GuestSegBaseTr,
4053	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
4054	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
4055	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
4056	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
4057	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
4058	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
4059	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
4060	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
4061	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
4062	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
4063	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
4064	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
4065	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
4066	kVmxVDiag_Vmentry_GuestSegSelLdtr,
4067	kVmxVDiag_Vmentry_GuestSegSelTr,
4068	kVmxVDiag_Vmentry_GuestSysenterEspEip,
4069	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
4070	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
4071	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
4072	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
4073	kVmxVDiag_Vmentry_HostCr0Fixed0,
4074	kVmxVDiag_Vmentry_HostCr0Fixed1,
4075	kVmxVDiag_Vmentry_HostCr3,
4076	kVmxVDiag_Vmentry_HostCr4Fixed0,
4077	kVmxVDiag_Vmentry_HostCr4Fixed1,
4078	kVmxVDiag_Vmentry_HostCr4Pae,
4079	kVmxVDiag_Vmentry_HostCr4Pcide,
4080	kVmxVDiag_Vmentry_HostCsTr,
4081	kVmxVDiag_Vmentry_HostEferMsr,
4082	kVmxVDiag_Vmentry_HostEferMsrRsvd,
4083	kVmxVDiag_Vmentry_HostGuestLongMode,
4084	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4085	kVmxVDiag_Vmentry_HostLongMode,
4086	kVmxVDiag_Vmentry_HostPatMsr,
4087	kVmxVDiag_Vmentry_HostRip,
4088	kVmxVDiag_Vmentry_HostRipRsvd,
4089	kVmxVDiag_Vmentry_HostSel,
4090	kVmxVDiag_Vmentry_HostSegBase,
4091	kVmxVDiag_Vmentry_HostSs,
4092	kVmxVDiag_Vmentry_HostSysenterEspEip,
4093	kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys,
4094	kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys,
4095	kVmxVDiag_Vmentry_LongModeCS,
4096	kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4097	kVmxVDiag_Vmentry_MsrLoad,
4098	kVmxVDiag_Vmentry_MsrLoadCount,
4099	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4100	kVmxVDiag_Vmentry_MsrLoadRing3,
4101	kVmxVDiag_Vmentry_MsrLoadRsvd,
4102	kVmxVDiag_Vmentry_NmiWindowExit,
4103	kVmxVDiag_Vmentry_PinCtlsAllowed1,
4104	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4105	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4106	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4107	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4108	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4109	kVmxVDiag_Vmentry_PtrInvalid,
4110	kVmxVDiag_Vmentry_PtrShadowVmcs,
4111	kVmxVDiag_Vmentry_RealOrV86Mode,
4112	kVmxVDiag_Vmentry_SavePreemptTimer,
4113	kVmxVDiag_Vmentry_TprThresholdRsvd,
4114	kVmxVDiag_Vmentry_TprThresholdVTpr,
4115	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4116	kVmxVDiag_Vmentry_VirtIntDelivery,
4117	kVmxVDiag_Vmentry_VirtNmi,
4118	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4119	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4120	kVmxVDiag_Vmentry_VmcsClear,
4121	kVmxVDiag_Vmentry_VmcsLaunch,
4122	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4123	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4124	kVmxVDiag_Vmentry_VmxRoot,
4125	kVmxVDiag_Vmentry_Vpid,
4126	kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys,
4127	kVmxVDiag_Vmexit_HostPdpte0Rsvd,
4128	kVmxVDiag_Vmexit_HostPdpte1Rsvd,
4129	kVmxVDiag_Vmexit_HostPdpte2Rsvd,
4130	kVmxVDiag_Vmexit_HostPdpte3Rsvd,
4131	kVmxVDiag_Vmexit_MsrLoad,
4132	kVmxVDiag_Vmexit_MsrLoadCount,
4133	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4134	kVmxVDiag_Vmexit_MsrLoadRing3,
4135	kVmxVDiag_Vmexit_MsrLoadRsvd,
4136	kVmxVDiag_Vmexit_MsrStore,
4137	kVmxVDiag_Vmexit_MsrStoreCount,
4138	kVmxVDiag_Vmexit_MsrStorePtrReadPhys,
4139	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4140	kVmxVDiag_Vmexit_MsrStoreRing3,
4141	kVmxVDiag_Vmexit_MsrStoreRsvd,
4142	kVmxVDiag_Vmexit_VirtApicPagePtrWritePhys,
4143	/* Last member for determining array index limit. */
4144	kVmxVDiag_End
4145	} VMXVDIAG;
4146	AssertCompileSize(VMXVDIAG, 4);
4147
4148	/** @} */
4149
4150	/** @} */
4151
4152	#endif /* !VBOX_INCLUDED_vmm_hm_vmx_h */
4153

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 82573

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