hm_vmx.h@ 82817

Last change on this file since 82817 was 82817, checked in by vboxsync, 5 years ago
VMM/IEM: Nested VMX: bugref:9180 Use x2APIC range defines from x86.h now that it's no longer different from what was specified in the VT-x spec prior to Jan 2019.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_hm_vmx_h
27	#define VBOX_INCLUDED_vmm_hm_vmx_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <iprt/x86.h>
34	#include <iprt/assertcompile.h>
35
36
37	/** @defgroup grp_hm_vmx VMX Types and Definitions
38	* @ingroup grp_hm
39	* @{
40	*/
41
42	/** @name Host-state restoration flags.
43	* @note If you change these values don't forget to update the assembly
44	* defines as well!
45	* @{
46	*/
47	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
48	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
49	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
50	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
51	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
52	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
53	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
54	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
55	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
56	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
57	/** @} */
58
59	/**
60	* Host-state restoration structure.
61	* This holds host-state fields that require manual restoration.
62	* Assembly version found in hm_vmx.mac (should be automatically verified).
63	*/
64	typedef struct VMXRESTOREHOST
65	{
66	RTSEL uHostSelDS; /* 0x00 */
67	RTSEL uHostSelES; /* 0x02 */
68	RTSEL uHostSelFS; /* 0x04 */
69	RTSEL uHostSelGS; /* 0x06 */
70	RTSEL uHostSelTR; /* 0x08 */
71	uint8_t abPadding0[4];
72	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
73	uint8_t abPadding1[6];
74	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
75	uint8_t abPadding2[6];
76	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
77	uint64_t uHostFSBase; /* 0x38 */
78	uint64_t uHostGSBase; /* 0x40 */
79	} VMXRESTOREHOST;
80	/** Pointer to VMXRESTOREHOST. */
81	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
82	AssertCompileSize(X86XDTR64, 10);
83	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
84	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
85	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
86	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
87	AssertCompileSize(VMXRESTOREHOST, 72);
88	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
89
90	/** @name Host-state MSR lazy-restoration flags.
91	* @{
92	*/
93	/** The host MSRs have been saved. */
94	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
95	/** The guest MSRs are loaded and in effect. */
96	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
97	/** @} */
98
99	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
100	* UFC = Unsupported Feature Combination.
101	* @{
102	*/
103	/** Unsupported pin-based VM-execution controls combo. */
104	#define VMX_UFC_CTRL_PIN_EXEC 1
105	/** Unsupported processor-based VM-execution controls combo. */
106	#define VMX_UFC_CTRL_PROC_EXEC 2
107	/** Unsupported move debug register VM-exit combo. */
108	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
109	/** Unsupported VM-entry controls combo. */
110	#define VMX_UFC_CTRL_ENTRY 4
111	/** Unsupported VM-exit controls combo. */
112	#define VMX_UFC_CTRL_EXIT 5
113	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
114	* for storing host MSRs. */
115	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
116	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
117	* for storing guest MSRs. */
118	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
119	/** Invalid VMCS size. */
120	#define VMX_UFC_INVALID_VMCS_SIZE 8
121	/** Unsupported secondary processor-based VM-execution controls combo. */
122	#define VMX_UFC_CTRL_PROC_EXEC2 9
123	/** Invalid unrestricted-guest execution controls combo. */
124	#define VMX_UFC_INVALID_UX_COMBO 10
125	/** EPT flush type not supported. */
126	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
127	/** EPT paging structure memory type is not write-back. */
128	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
129	/** EPT requires INVEPT instr. support but it's not available. */
130	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
131	/** EPT requires page-walk length of 4. */
132	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
133	/** VMX VMWRITE all feature exposed to the guest but not supported on host. */
134	#define VMX_UFC_GST_HOST_VMWRITE_ALL 15
135	/** LBR stack size cannot be determined for the current CPU. */
136	#define VMX_UFC_LBR_STACK_SIZE_UNKNOWN 16
137	/** LBR stack size of the CPU exceeds our buffer size. */
138	#define VMX_UFC_LBR_STACK_SIZE_OVERFLOW 17
139	/** @} */
140
141	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
142	* VCI = VMCS-field Cache Invalid.
143	* @{
144	*/
145	/** Cache of VM-entry controls invalid. */
146	#define VMX_VCI_CTRL_ENTRY 300
147	/** Cache of VM-exit controls invalid. */
148	#define VMX_VCI_CTRL_EXIT 301
149	/** Cache of pin-based VM-execution controls invalid. */
150	#define VMX_VCI_CTRL_PIN_EXEC 302
151	/** Cache of processor-based VM-execution controls invalid. */
152	#define VMX_VCI_CTRL_PROC_EXEC 303
153	/** Cache of secondary processor-based VM-execution controls invalid. */
154	#define VMX_VCI_CTRL_PROC_EXEC2 304
155	/** Cache of exception bitmap invalid. */
156	#define VMX_VCI_CTRL_XCPT_BITMAP 305
157	/** Cache of TSC offset invalid. */
158	#define VMX_VCI_CTRL_TSC_OFFSET 306
159	/** @} */
160
161	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
162	* IGS = Invalid Guest State.
163	* @{
164	*/
165	/** An error occurred while checking invalid-guest-state. */
166	#define VMX_IGS_ERROR 500
167	/** The invalid guest-state checks did not find any reason why. */
168	#define VMX_IGS_REASON_NOT_FOUND 501
169	/** CR0 fixed1 bits invalid. */
170	#define VMX_IGS_CR0_FIXED1 502
171	/** CR0 fixed0 bits invalid. */
172	#define VMX_IGS_CR0_FIXED0 503
173	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
174	#define VMX_IGS_CR0_PG_PE_COMBO 504
175	/** CR4 fixed1 bits invalid. */
176	#define VMX_IGS_CR4_FIXED1 505
177	/** CR4 fixed0 bits invalid. */
178	#define VMX_IGS_CR4_FIXED0 506
179	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
180	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
181	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
182	/** CR0.PG not set for long-mode when not using unrestricted guest. */
183	#define VMX_IGS_CR0_PG_LONGMODE 508
184	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
185	#define VMX_IGS_CR4_PAE_LONGMODE 509
186	/** CR4.PCIDE set for 32-bit guest. */
187	#define VMX_IGS_CR4_PCIDE 510
188	/** VMCS' DR7 reserved bits not set to 0. */
189	#define VMX_IGS_DR7_RESERVED 511
190	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
191	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
192	/** VMCS' EFER MSR reserved bits not set to 0. */
193	#define VMX_IGS_EFER_MSR_RESERVED 513
194	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
195	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
196	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
197	* without unrestricted guest. */
198	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
199	/** CS.Attr.P bit invalid. */
200	#define VMX_IGS_CS_ATTR_P_INVALID 516
201	/** CS.Attr reserved bits not set to 0. */
202	#define VMX_IGS_CS_ATTR_RESERVED 517
203	/** CS.Attr.G bit invalid. */
204	#define VMX_IGS_CS_ATTR_G_INVALID 518
205	/** CS is unusable. */
206	#define VMX_IGS_CS_ATTR_UNUSABLE 519
207	/** CS and SS DPL unequal. */
208	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
209	/** CS and SS DPL mismatch. */
210	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
211	/** CS Attr.Type invalid. */
212	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
213	/** CS and SS RPL unequal. */
214	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
215	/** SS.Attr.DPL and SS RPL unequal. */
216	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
217	/** SS.Attr.DPL invalid for segment type. */
218	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
219	/** SS.Attr.Type invalid. */
220	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
221	/** SS.Attr.P bit invalid. */
222	#define VMX_IGS_SS_ATTR_P_INVALID 527
223	/** SS.Attr reserved bits not set to 0. */
224	#define VMX_IGS_SS_ATTR_RESERVED 528
225	/** SS.Attr.G bit invalid. */
226	#define VMX_IGS_SS_ATTR_G_INVALID 529
227	/** DS.Attr.A bit invalid. */
228	#define VMX_IGS_DS_ATTR_A_INVALID 530
229	/** DS.Attr.P bit invalid. */
230	#define VMX_IGS_DS_ATTR_P_INVALID 531
231	/** DS.Attr.DPL and DS RPL unequal. */
232	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
233	/** DS.Attr reserved bits not set to 0. */
234	#define VMX_IGS_DS_ATTR_RESERVED 533
235	/** DS.Attr.G bit invalid. */
236	#define VMX_IGS_DS_ATTR_G_INVALID 534
237	/** DS.Attr.Type invalid. */
238	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
239	/** ES.Attr.A bit invalid. */
240	#define VMX_IGS_ES_ATTR_A_INVALID 536
241	/** ES.Attr.P bit invalid. */
242	#define VMX_IGS_ES_ATTR_P_INVALID 537
243	/** ES.Attr.DPL and DS RPL unequal. */
244	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
245	/** ES.Attr reserved bits not set to 0. */
246	#define VMX_IGS_ES_ATTR_RESERVED 539
247	/** ES.Attr.G bit invalid. */
248	#define VMX_IGS_ES_ATTR_G_INVALID 540
249	/** ES.Attr.Type invalid. */
250	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
251	/** FS.Attr.A bit invalid. */
252	#define VMX_IGS_FS_ATTR_A_INVALID 542
253	/** FS.Attr.P bit invalid. */
254	#define VMX_IGS_FS_ATTR_P_INVALID 543
255	/** FS.Attr.DPL and DS RPL unequal. */
256	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
257	/** FS.Attr reserved bits not set to 0. */
258	#define VMX_IGS_FS_ATTR_RESERVED 545
259	/** FS.Attr.G bit invalid. */
260	#define VMX_IGS_FS_ATTR_G_INVALID 546
261	/** FS.Attr.Type invalid. */
262	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
263	/** GS.Attr.A bit invalid. */
264	#define VMX_IGS_GS_ATTR_A_INVALID 548
265	/** GS.Attr.P bit invalid. */
266	#define VMX_IGS_GS_ATTR_P_INVALID 549
267	/** GS.Attr.DPL and DS RPL unequal. */
268	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
269	/** GS.Attr reserved bits not set to 0. */
270	#define VMX_IGS_GS_ATTR_RESERVED 551
271	/** GS.Attr.G bit invalid. */
272	#define VMX_IGS_GS_ATTR_G_INVALID 552
273	/** GS.Attr.Type invalid. */
274	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
275	/** V86 mode CS.Base invalid. */
276	#define VMX_IGS_V86_CS_BASE_INVALID 554
277	/** V86 mode CS.Limit invalid. */
278	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
279	/** V86 mode CS.Attr invalid. */
280	#define VMX_IGS_V86_CS_ATTR_INVALID 556
281	/** V86 mode SS.Base invalid. */
282	#define VMX_IGS_V86_SS_BASE_INVALID 557
283	/** V86 mode SS.Limit invalid. */
284	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
285	/** V86 mode SS.Attr invalid. */
286	#define VMX_IGS_V86_SS_ATTR_INVALID 559
287	/** V86 mode DS.Base invalid. */
288	#define VMX_IGS_V86_DS_BASE_INVALID 560
289	/** V86 mode DS.Limit invalid. */
290	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
291	/** V86 mode DS.Attr invalid. */
292	#define VMX_IGS_V86_DS_ATTR_INVALID 562
293	/** V86 mode ES.Base invalid. */
294	#define VMX_IGS_V86_ES_BASE_INVALID 563
295	/** V86 mode ES.Limit invalid. */
296	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
297	/** V86 mode ES.Attr invalid. */
298	#define VMX_IGS_V86_ES_ATTR_INVALID 565
299	/** V86 mode FS.Base invalid. */
300	#define VMX_IGS_V86_FS_BASE_INVALID 566
301	/** V86 mode FS.Limit invalid. */
302	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
303	/** V86 mode FS.Attr invalid. */
304	#define VMX_IGS_V86_FS_ATTR_INVALID 568
305	/** V86 mode GS.Base invalid. */
306	#define VMX_IGS_V86_GS_BASE_INVALID 569
307	/** V86 mode GS.Limit invalid. */
308	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
309	/** V86 mode GS.Attr invalid. */
310	#define VMX_IGS_V86_GS_ATTR_INVALID 571
311	/** Longmode CS.Base invalid. */
312	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
313	/** Longmode SS.Base invalid. */
314	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
315	/** Longmode DS.Base invalid. */
316	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
317	/** Longmode ES.Base invalid. */
318	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
319	/** SYSENTER ESP is not canonical. */
320	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
321	/** SYSENTER EIP is not canonical. */
322	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
323	/** PAT MSR invalid. */
324	#define VMX_IGS_PAT_MSR_INVALID 578
325	/** PAT MSR reserved bits not set to 0. */
326	#define VMX_IGS_PAT_MSR_RESERVED 579
327	/** GDTR.Base is not canonical. */
328	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
329	/** IDTR.Base is not canonical. */
330	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
331	/** GDTR.Limit invalid. */
332	#define VMX_IGS_GDTR_LIMIT_INVALID 582
333	/** IDTR.Limit invalid. */
334	#define VMX_IGS_IDTR_LIMIT_INVALID 583
335	/** Longmode RIP is invalid. */
336	#define VMX_IGS_LONGMODE_RIP_INVALID 584
337	/** RFLAGS reserved bits not set to 0. */
338	#define VMX_IGS_RFLAGS_RESERVED 585
339	/** RFLAGS RA1 reserved bits not set to 1. */
340	#define VMX_IGS_RFLAGS_RESERVED1 586
341	/** RFLAGS.VM (V86 mode) invalid. */
342	#define VMX_IGS_RFLAGS_VM_INVALID 587
343	/** RFLAGS.IF invalid. */
344	#define VMX_IGS_RFLAGS_IF_INVALID 588
345	/** Activity state invalid. */
346	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
347	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
348	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
349	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
350	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
351	/** Activity state SIPI WAIT invalid. */
352	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
353	/** Interruptibility state reserved bits not set to 0. */
354	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
355	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
356	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
357	/** Interruptibility state block-by-STI invalid for EFLAGS. */
358	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
359	/** Interruptibility state invalid while trying to deliver external
360	* interrupt. */
361	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
362	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
363	* NMI. */
364	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
365	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
366	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
367	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
368	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
369	/** Interruptibility state block-by-STI (maybe) invalid when trying to
370	* deliver an NMI. */
371	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
372	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
373	* active. */
374	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
375	/** Pending debug exceptions reserved bits not set to 0. */
376	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
377	/** Longmode pending debug exceptions reserved bits not set to 0. */
378	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
379	/** Pending debug exceptions.BS bit is not set when it should be. */
380	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
381	/** Pending debug exceptions.BS bit is not clear when it should be. */
382	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
383	/** VMCS link pointer reserved bits not set to 0. */
384	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
385	/** TR cannot index into LDT, TI bit MBZ. */
386	#define VMX_IGS_TR_TI_INVALID 607
387	/** LDTR cannot index into LDT. TI bit MBZ. */
388	#define VMX_IGS_LDTR_TI_INVALID 608
389	/** TR.Base is not canonical. */
390	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
391	/** FS.Base is not canonical. */
392	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
393	/** GS.Base is not canonical. */
394	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
395	/** LDTR.Base is not canonical. */
396	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
397	/** TR is unusable. */
398	#define VMX_IGS_TR_ATTR_UNUSABLE 613
399	/** TR.Attr.S bit invalid. */
400	#define VMX_IGS_TR_ATTR_S_INVALID 614
401	/** TR is not present. */
402	#define VMX_IGS_TR_ATTR_P_INVALID 615
403	/** TR.Attr reserved bits not set to 0. */
404	#define VMX_IGS_TR_ATTR_RESERVED 616
405	/** TR.Attr.G bit invalid. */
406	#define VMX_IGS_TR_ATTR_G_INVALID 617
407	/** Longmode TR.Attr.Type invalid. */
408	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
409	/** TR.Attr.Type invalid. */
410	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
411	/** CS.Attr.S invalid. */
412	#define VMX_IGS_CS_ATTR_S_INVALID 620
413	/** CS.Attr.DPL invalid. */
414	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
415	/** PAE PDPTE reserved bits not set to 0. */
416	#define VMX_IGS_PAE_PDPTE_RESERVED 623
417	/** VMCS link pointer does not point to a shadow VMCS. */
418	#define VMX_IGS_VMCS_LINK_PTR_NOT_SHADOW 624
419	/** VMCS link pointer to a shadow VMCS with invalid VMCS revision identifer. */
420	#define VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID 625
421	/** @} */
422
423	/** @name VMX VMCS-Read cache indices.
424	* @{
425	*/
426	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
427	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
428	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
429	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
430	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
431	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
432	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
433	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
434	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
435	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
436	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
437	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
438	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
439	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
440	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
441	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
442	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
443	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
444	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
445	/** @} */
446
447	/** @name VMX EPT paging structures
448	* @{
449	*/
450
451	/**
452	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
453	*/
454	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
455
456	/**
457	* EPT Page Directory Pointer Entry. Bit view.
458	* In accordance with the VT-x spec.
459	*
460	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
461	* this did cause trouble with one compiler/version).
462	*/
463	typedef struct EPTPML4EBITS
464	{
465	/** Present bit. */
466	RT_GCC_EXTENSION uint64_t u1Present : 1;
467	/** Writable bit. */
468	RT_GCC_EXTENSION uint64_t u1Write : 1;
469	/** Executable bit. */
470	RT_GCC_EXTENSION uint64_t u1Execute : 1;
471	/** Reserved (must be 0). */
472	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
473	/** Available for software. */
474	RT_GCC_EXTENSION uint64_t u4Available : 4;
475	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
476	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
477	/** Available for software. */
478	RT_GCC_EXTENSION uint64_t u12Available : 12;
479	} EPTPML4EBITS;
480	AssertCompileSize(EPTPML4EBITS, 8);
481
482	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
483	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
484	/** The page shift to get the PML4 index. */
485	#define EPT_PML4_SHIFT X86_PML4_SHIFT
486	/** The PML4 index mask (apply to a shifted page address). */
487	#define EPT_PML4_MASK X86_PML4_MASK
488
489	/**
490	* EPT PML4E.
491	* In accordance with the VT-x spec.
492	*/
493	typedef union EPTPML4E
494	{
495	/** Normal view. */
496	EPTPML4EBITS n;
497	/** Unsigned integer view. */
498	X86PGPAEUINT u;
499	/** 64 bit unsigned integer view. */
500	uint64_t au64[1];
501	/** 32 bit unsigned integer view. */
502	uint32_t au32[2];
503	} EPTPML4E;
504	AssertCompileSize(EPTPML4E, 8);
505	/** Pointer to a PML4 table entry. */
506	typedef EPTPML4E *PEPTPML4E;
507	/** Pointer to a const PML4 table entry. */
508	typedef const EPTPML4E *PCEPTPML4E;
509
510	/**
511	* EPT PML4 Table.
512	* In accordance with the VT-x spec.
513	*/
514	typedef struct EPTPML4
515	{
516	EPTPML4E a[EPT_PG_ENTRIES];
517	} EPTPML4;
518	AssertCompileSize(EPTPML4, 0x1000);
519	/** Pointer to an EPT PML4 Table. */
520	typedef EPTPML4 *PEPTPML4;
521	/** Pointer to a const EPT PML4 Table. */
522	typedef const EPTPML4 *PCEPTPML4;
523
524	/**
525	* EPT Page Directory Pointer Entry. Bit view.
526	* In accordance with the VT-x spec.
527	*/
528	typedef struct EPTPDPTEBITS
529	{
530	/** Present bit. */
531	RT_GCC_EXTENSION uint64_t u1Present : 1;
532	/** Writable bit. */
533	RT_GCC_EXTENSION uint64_t u1Write : 1;
534	/** Executable bit. */
535	RT_GCC_EXTENSION uint64_t u1Execute : 1;
536	/** Reserved (must be 0). */
537	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
538	/** Available for software. */
539	RT_GCC_EXTENSION uint64_t u4Available : 4;
540	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
541	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
542	/** Available for software. */
543	RT_GCC_EXTENSION uint64_t u12Available : 12;
544	} EPTPDPTEBITS;
545	AssertCompileSize(EPTPDPTEBITS, 8);
546
547	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
548	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
549	/** The page shift to get the PDPT index. */
550	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
551	/** The PDPT index mask (apply to a shifted page address). */
552	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
553
554	/**
555	* EPT Page Directory Pointer.
556	* In accordance with the VT-x spec.
557	*/
558	typedef union EPTPDPTE
559	{
560	/** Normal view. */
561	EPTPDPTEBITS n;
562	/** Unsigned integer view. */
563	X86PGPAEUINT u;
564	/** 64 bit unsigned integer view. */
565	uint64_t au64[1];
566	/** 32 bit unsigned integer view. */
567	uint32_t au32[2];
568	} EPTPDPTE;
569	AssertCompileSize(EPTPDPTE, 8);
570	/** Pointer to an EPT Page Directory Pointer Entry. */
571	typedef EPTPDPTE *PEPTPDPTE;
572	/** Pointer to a const EPT Page Directory Pointer Entry. */
573	typedef const EPTPDPTE *PCEPTPDPTE;
574
575	/**
576	* EPT Page Directory Pointer Table.
577	* In accordance with the VT-x spec.
578	*/
579	typedef struct EPTPDPT
580	{
581	EPTPDPTE a[EPT_PG_ENTRIES];
582	} EPTPDPT;
583	AssertCompileSize(EPTPDPT, 0x1000);
584	/** Pointer to an EPT Page Directory Pointer Table. */
585	typedef EPTPDPT *PEPTPDPT;
586	/** Pointer to a const EPT Page Directory Pointer Table. */
587	typedef const EPTPDPT *PCEPTPDPT;
588
589	/**
590	* EPT Page Directory Table Entry. Bit view.
591	* In accordance with the VT-x spec.
592	*/
593	typedef struct EPTPDEBITS
594	{
595	/** Present bit. */
596	RT_GCC_EXTENSION uint64_t u1Present : 1;
597	/** Writable bit. */
598	RT_GCC_EXTENSION uint64_t u1Write : 1;
599	/** Executable bit. */
600	RT_GCC_EXTENSION uint64_t u1Execute : 1;
601	/** Reserved (must be 0). */
602	RT_GCC_EXTENSION uint64_t u4Reserved : 4;
603	/** Big page (must be 0 here). */
604	RT_GCC_EXTENSION uint64_t u1Size : 1;
605	/** Available for software. */
606	RT_GCC_EXTENSION uint64_t u4Available : 4;
607	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
608	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
609	/** Available for software. */
610	RT_GCC_EXTENSION uint64_t u12Available : 12;
611	} EPTPDEBITS;
612	AssertCompileSize(EPTPDEBITS, 8);
613
614	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
615	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
616	/** The page shift to get the PD index. */
617	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
618	/** The PD index mask (apply to a shifted page address). */
619	#define EPT_PD_MASK X86_PD_PAE_MASK
620
621	/**
622	* EPT 2MB Page Directory Table Entry. Bit view.
623	* In accordance with the VT-x spec.
624	*/
625	typedef struct EPTPDE2MBITS
626	{
627	/** Present bit. */
628	RT_GCC_EXTENSION uint64_t u1Present : 1;
629	/** Writable bit. */
630	RT_GCC_EXTENSION uint64_t u1Write : 1;
631	/** Executable bit. */
632	RT_GCC_EXTENSION uint64_t u1Execute : 1;
633	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
634	RT_GCC_EXTENSION uint64_t u3EMT : 3;
635	/** Ignore PAT memory type */
636	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
637	/** Big page (must be 1 here). */
638	RT_GCC_EXTENSION uint64_t u1Size : 1;
639	/** Available for software. */
640	RT_GCC_EXTENSION uint64_t u4Available : 4;
641	/** Reserved (must be 0). */
642	RT_GCC_EXTENSION uint64_t u9Reserved : 9;
643	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
644	RT_GCC_EXTENSION uint64_t u31PhysAddr : 31;
645	/** Available for software. */
646	RT_GCC_EXTENSION uint64_t u12Available : 12;
647	} EPTPDE2MBITS;
648	AssertCompileSize(EPTPDE2MBITS, 8);
649
650	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
651	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
652
653	/**
654	* EPT Page Directory Table Entry.
655	* In accordance with the VT-x spec.
656	*/
657	typedef union EPTPDE
658	{
659	/** Normal view. */
660	EPTPDEBITS n;
661	/** 2MB view (big). */
662	EPTPDE2MBITS b;
663	/** Unsigned integer view. */
664	X86PGPAEUINT u;
665	/** 64 bit unsigned integer view. */
666	uint64_t au64[1];
667	/** 32 bit unsigned integer view. */
668	uint32_t au32[2];
669	} EPTPDE;
670	AssertCompileSize(EPTPDE, 8);
671	/** Pointer to an EPT Page Directory Table Entry. */
672	typedef EPTPDE *PEPTPDE;
673	/** Pointer to a const EPT Page Directory Table Entry. */
674	typedef const EPTPDE *PCEPTPDE;
675
676	/**
677	* EPT Page Directory Table.
678	* In accordance with the VT-x spec.
679	*/
680	typedef struct EPTPD
681	{
682	EPTPDE a[EPT_PG_ENTRIES];
683	} EPTPD;
684	AssertCompileSize(EPTPD, 0x1000);
685	/** Pointer to an EPT Page Directory Table. */
686	typedef EPTPD *PEPTPD;
687	/** Pointer to a const EPT Page Directory Table. */
688	typedef const EPTPD *PCEPTPD;
689
690	/**
691	* EPT Page Table Entry. Bit view.
692	* In accordance with the VT-x spec.
693	*/
694	typedef struct EPTPTEBITS
695	{
696	/** 0 - Present bit.
697	* @remarks This is a convenience "misnomer". The bit actually indicates read access
698	* and the CPU will consider an entry with any of the first three bits set
699	* as present. Since all our valid entries will have this bit set, it can
700	* be used as a present indicator and allow some code sharing. */
701	RT_GCC_EXTENSION uint64_t u1Present : 1;
702	/** 1 - Writable bit. */
703	RT_GCC_EXTENSION uint64_t u1Write : 1;
704	/** 2 - Executable bit. */
705	RT_GCC_EXTENSION uint64_t u1Execute : 1;
706	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
707	RT_GCC_EXTENSION uint64_t u3EMT : 3;
708	/** 6 - Ignore PAT memory type */
709	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
710	/** 11:7 - Available for software. */
711	RT_GCC_EXTENSION uint64_t u5Available : 5;
712	/** 51:12 - Physical address of page. Restricted by maximum physical
713	* address width of the cpu. */
714	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
715	/** 63:52 - Available for software. */
716	RT_GCC_EXTENSION uint64_t u12Available : 12;
717	} EPTPTEBITS;
718	AssertCompileSize(EPTPTEBITS, 8);
719
720	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
721	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
722	/** The page shift to get the EPT PTE index. */
723	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
724	/** The EPT PT index mask (apply to a shifted page address). */
725	#define EPT_PT_MASK X86_PT_PAE_MASK
726
727	/**
728	* EPT Page Table Entry.
729	* In accordance with the VT-x spec.
730	*/
731	typedef union EPTPTE
732	{
733	/** Normal view. */
734	EPTPTEBITS n;
735	/** Unsigned integer view. */
736	X86PGPAEUINT u;
737	/** 64 bit unsigned integer view. */
738	uint64_t au64[1];
739	/** 32 bit unsigned integer view. */
740	uint32_t au32[2];
741	} EPTPTE;
742	AssertCompileSize(EPTPTE, 8);
743	/** Pointer to an EPT Page Directory Table Entry. */
744	typedef EPTPTE *PEPTPTE;
745	/** Pointer to a const EPT Page Directory Table Entry. */
746	typedef const EPTPTE *PCEPTPTE;
747
748	/**
749	* EPT Page Table.
750	* In accordance with the VT-x spec.
751	*/
752	typedef struct EPTPT
753	{
754	EPTPTE a[EPT_PG_ENTRIES];
755	} EPTPT;
756	AssertCompileSize(EPTPT, 0x1000);
757	/** Pointer to an extended page table. */
758	typedef EPTPT *PEPTPT;
759	/** Pointer to a const extended table. */
760	typedef const EPTPT *PCEPTPT;
761
762	/** @} */
763
764	/**
765	* VMX VPID flush types.
766	* Valid enum members are in accordance with the VT-x spec.
767	*/
768	typedef enum
769	{
770	/** Invalidate a specific page. */
771	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
772	/** Invalidate one context (specific VPID). */
773	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
774	/** Invalidate all contexts (all VPIDs). */
775	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
776	/** Invalidate a single VPID context retaining global mappings. */
777	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
778	/** Unsupported by VirtualBox. */
779	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
780	/** Unsupported by CPU. */
781	VMXTLBFLUSHVPID_NONE = 0xbad1
782	} VMXTLBFLUSHVPID;
783	AssertCompileSize(VMXTLBFLUSHVPID, 4);
784
785	/**
786	* VMX EPT flush types.
787	* @note Valid enums values are in accordance with the VT-x spec.
788	*/
789	typedef enum
790	{
791	/** Invalidate one context (specific EPT). */
792	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
793	/* Invalidate all contexts (all EPTs) */
794	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
795	/** Unsupported by VirtualBox. */
796	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
797	/** Unsupported by CPU. */
798	VMXTLBFLUSHEPT_NONE = 0xbad1
799	} VMXTLBFLUSHEPT;
800	AssertCompileSize(VMXTLBFLUSHEPT, 4);
801
802	/**
803	* VMX Posted Interrupt Descriptor.
804	* In accordance with the VT-x spec.
805	*/
806	typedef struct VMXPOSTEDINTRDESC
807	{
808	uint32_t aVectorBitmap[8];
809	uint32_t fOutstandingNotification : 1;
810	uint32_t uReserved0 : 31;
811	uint8_t au8Reserved0[28];
812	} VMXPOSTEDINTRDESC;
813	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
814	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
815	/** Pointer to a posted interrupt descriptor. */
816	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
817	/** Pointer to a const posted interrupt descriptor. */
818	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
819
820	/**
821	* VMX VMCS revision identifier.
822	* In accordance with the VT-x spec.
823	*/
824	typedef union
825	{
826	struct
827	{
828	/** Revision identifier. */
829	uint32_t u31RevisionId : 31;
830	/** Whether this is a shadow VMCS. */
831	uint32_t fIsShadowVmcs : 1;
832	} n;
833	/* The unsigned integer view. */
834	uint32_t u;
835	} VMXVMCSREVID;
836	AssertCompileSize(VMXVMCSREVID, 4);
837	/** Pointer to the VMXVMCSREVID union. */
838	typedef VMXVMCSREVID *PVMXVMCSREVID;
839	/** Pointer to a const VMXVMCSREVID union. */
840	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
841
842	/**
843	* VMX VM-exit instruction information.
844	* In accordance with the VT-x spec.
845	*/
846	typedef union
847	{
848	/** Plain unsigned int representation. */
849	uint32_t u;
850
851	/** INS and OUTS information. */
852	struct
853	{
854	uint32_t u7Reserved0 : 7;
855	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
856	uint32_t u3AddrSize : 3;
857	uint32_t u5Reserved1 : 5;
858	/** The segment register (X86_SREG_XXX). */
859	uint32_t iSegReg : 3;
860	uint32_t uReserved2 : 14;
861	} StrIo;
862
863	/** INVEPT, INVPCID, INVVPID information. */
864	struct
865	{
866	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
867	uint32_t u2Scaling : 2;
868	uint32_t u5Undef0 : 5;
869	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
870	uint32_t u3AddrSize : 3;
871	/** Cleared to 0. */
872	uint32_t u1Cleared0 : 1;
873	uint32_t u4Undef0 : 4;
874	/** The segment register (X86_SREG_XXX). */
875	uint32_t iSegReg : 3;
876	/** The index register (X86_GREG_XXX). */
877	uint32_t iIdxReg : 4;
878	/** Set if index register is invalid. */
879	uint32_t fIdxRegInvalid : 1;
880	/** The base register (X86_GREG_XXX). */
881	uint32_t iBaseReg : 4;
882	/** Set if base register is invalid. */
883	uint32_t fBaseRegInvalid : 1;
884	/** Register 2 (X86_GREG_XXX). */
885	uint32_t iReg2 : 4;
886	} Inv;
887
888	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
889	struct
890	{
891	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
892	uint32_t u2Scaling : 2;
893	uint32_t u5Reserved0 : 5;
894	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
895	uint32_t u3AddrSize : 3;
896	/** Cleared to 0. */
897	uint32_t u1Cleared0 : 1;
898	uint32_t u4Reserved0 : 4;
899	/** The segment register (X86_SREG_XXX). */
900	uint32_t iSegReg : 3;
901	/** The index register (X86_GREG_XXX). */
902	uint32_t iIdxReg : 4;
903	/** Set if index register is invalid. */
904	uint32_t fIdxRegInvalid : 1;
905	/** The base register (X86_GREG_XXX). */
906	uint32_t iBaseReg : 4;
907	/** Set if base register is invalid. */
908	uint32_t fBaseRegInvalid : 1;
909	/** Register 2 (X86_GREG_XXX). */
910	uint32_t iReg2 : 4;
911	} VmxXsave;
912
913	/** LIDT, LGDT, SIDT, SGDT information. */
914	struct
915	{
916	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
917	uint32_t u2Scaling : 2;
918	uint32_t u5Undef0 : 5;
919	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
920	uint32_t u3AddrSize : 3;
921	/** Always cleared to 0. */
922	uint32_t u1Cleared0 : 1;
923	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
924	uint32_t uOperandSize : 1;
925	uint32_t u3Undef0 : 3;
926	/** The segment register (X86_SREG_XXX). */
927	uint32_t iSegReg : 3;
928	/** The index register (X86_GREG_XXX). */
929	uint32_t iIdxReg : 4;
930	/** Set if index register is invalid. */
931	uint32_t fIdxRegInvalid : 1;
932	/** The base register (X86_GREG_XXX). */
933	uint32_t iBaseReg : 4;
934	/** Set if base register is invalid. */
935	uint32_t fBaseRegInvalid : 1;
936	/** Instruction identity (VMX_INSTR_ID_XXX). */
937	uint32_t u2InstrId : 2;
938	uint32_t u2Undef0 : 2;
939	} GdtIdt;
940
941	/** LLDT, LTR, SLDT, STR information. */
942	struct
943	{
944	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
945	uint32_t u2Scaling : 2;
946	uint32_t u1Undef0 : 1;
947	/** Register 1 (X86_GREG_XXX). */
948	uint32_t iReg1 : 4;
949	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
950	uint32_t u3AddrSize : 3;
951	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
952	uint32_t fIsRegOperand : 1;
953	uint32_t u4Undef0 : 4;
954	/** The segment register (X86_SREG_XXX). */
955	uint32_t iSegReg : 3;
956	/** The index register (X86_GREG_XXX). */
957	uint32_t iIdxReg : 4;
958	/** Set if index register is invalid. */
959	uint32_t fIdxRegInvalid : 1;
960	/** The base register (X86_GREG_XXX). */
961	uint32_t iBaseReg : 4;
962	/** Set if base register is invalid. */
963	uint32_t fBaseRegInvalid : 1;
964	/** Instruction identity (VMX_INSTR_ID_XXX). */
965	uint32_t u2InstrId : 2;
966	uint32_t u2Undef0 : 2;
967	} LdtTr;
968
969	/** RDRAND, RDSEED information. */
970	struct
971	{
972	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
973	uint32_t u2Undef0 : 2;
974	/** Destination register (X86_GREG_XXX). */
975	uint32_t iReg1 : 4;
976	uint32_t u4Undef0 : 4;
977	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
978	uint32_t u2OperandSize : 2;
979	uint32_t u19Def0 : 20;
980	} RdrandRdseed;
981
982	/** VMREAD, VMWRITE information. */
983	struct
984	{
985	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
986	uint32_t u2Scaling : 2;
987	uint32_t u1Undef0 : 1;
988	/** Register 1 (X86_GREG_XXX). */
989	uint32_t iReg1 : 4;
990	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
991	uint32_t u3AddrSize : 3;
992	/** Memory or register operand. */
993	uint32_t fIsRegOperand : 1;
994	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
995	uint32_t u4Undef0 : 4;
996	/** The segment register (X86_SREG_XXX). */
997	uint32_t iSegReg : 3;
998	/** The index register (X86_GREG_XXX). */
999	uint32_t iIdxReg : 4;
1000	/** Set if index register is invalid. */
1001	uint32_t fIdxRegInvalid : 1;
1002	/** The base register (X86_GREG_XXX). */
1003	uint32_t iBaseReg : 4;
1004	/** Set if base register is invalid. */
1005	uint32_t fBaseRegInvalid : 1;
1006	/** Register 2 (X86_GREG_XXX). */
1007	uint32_t iReg2 : 4;
1008	} VmreadVmwrite;
1009
1010	/** This is a combination field of all instruction information. Note! Not all field
1011	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1012	* specialized fields are overwritten by their generic counterparts (e.g. no
1013	* instruction identity field). */
1014	struct
1015	{
1016	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1017	uint32_t u2Scaling : 2;
1018	uint32_t u1Undef0 : 1;
1019	/** Register 1 (X86_GREG_XXX). */
1020	uint32_t iReg1 : 4;
1021	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1022	uint32_t u3AddrSize : 3;
1023	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1024	uint32_t fIsRegOperand : 1;
1025	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1026	uint32_t uOperandSize : 2;
1027	uint32_t u2Undef0 : 2;
1028	/** The segment register (X86_SREG_XXX). */
1029	uint32_t iSegReg : 3;
1030	/** The index register (X86_GREG_XXX). */
1031	uint32_t iIdxReg : 4;
1032	/** Set if index register is invalid. */
1033	uint32_t fIdxRegInvalid : 1;
1034	/** The base register (X86_GREG_XXX). */
1035	uint32_t iBaseReg : 4;
1036	/** Set if base register is invalid. */
1037	uint32_t fBaseRegInvalid : 1;
1038	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1039	uint32_t iReg2 : 4;
1040	} All;
1041	} VMXEXITINSTRINFO;
1042	AssertCompileSize(VMXEXITINSTRINFO, 4);
1043	/** Pointer to a VMX VM-exit instruction info. struct. */
1044	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1045	/** Pointer to a const VMX VM-exit instruction info. struct. */
1046	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1047
1048
1049	/** @name VM-entry failure reported in Exit qualification.
1050	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1051	* @{
1052	*/
1053	/** No errors during VM-entry. */
1054	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1055	/** Not used. */
1056	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1057	/** Error while loading PDPTEs. */
1058	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1059	/** NMI injection when blocking-by-STI is set. */
1060	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1061	/** Invalid VMCS link pointer. */
1062	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1063	/** @} */
1064
1065
1066	/** @name VMXMSRPM_XXX - VMX MSR-bitmap permissions.
1067	* These are -not- specified by Intel but used internally by VirtualBox.
1068	* @{ */
1069	/** Guest software reads of this MSR must not cause a VM-exit. */
1070	#define VMXMSRPM_ALLOW_RD RT_BIT(0)
1071	/** Guest software reads of this MSR must cause a VM-exit. */
1072	#define VMXMSRPM_EXIT_RD RT_BIT(1)
1073	/** Guest software writes to this MSR must not cause a VM-exit. */
1074	#define VMXMSRPM_ALLOW_WR RT_BIT(2)
1075	/** Guest software writes to this MSR must cause a VM-exit. */
1076	#define VMXMSRPM_EXIT_WR RT_BIT(3)
1077	/** Guest software reads or writes of this MSR must not cause a VM-exit. */
1078	#define VMXMSRPM_ALLOW_RD_WR (VMXMSRPM_ALLOW_RD \| VMXMSRPM_ALLOW_WR)
1079	/** Guest software reads or writes of this MSR must cause a VM-exit. */
1080	#define VMXMSRPM_EXIT_RD_WR (VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR)
1081	/** Mask of valid MSR read permissions. */
1082	#define VMXMSRPM_RD_MASK (VMXMSRPM_ALLOW_RD \| VMXMSRPM_EXIT_RD)
1083	/** Mask of valid MSR write permissions. */
1084	#define VMXMSRPM_WR_MASK (VMXMSRPM_ALLOW_WR \| VMXMSRPM_EXIT_WR)
1085	/** Mask of valid MSR permissions. */
1086	#define VMXMSRPM_MASK (VMXMSRPM_RD_MASK \| VMXMSRPM_WR_MASK)
1087	/** */
1088	/** Gets whether the MSR permission is valid or not. */
1089	#define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \
1090	&& ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \
1091	&& ((a_Msrpm) & VMXMSRPM_RD_MASK) != VMXMSRPM_RD_MASK \
1092	&& ((a_Msrpm) & VMXMSRPM_WR_MASK) != VMXMSRPM_WR_MASK)
1093	/** @} */
1094
1095	/**
1096	* VMX MSR autoload/store slot.
1097	* In accordance with the VT-x spec.
1098	*/
1099	typedef struct VMXAUTOMSR
1100	{
1101	/** The MSR Id. */
1102	uint32_t u32Msr;
1103	/** Reserved (MBZ). */
1104	uint32_t u32Reserved;
1105	/** The MSR value. */
1106	uint64_t u64Value;
1107	} VMXAUTOMSR;
1108	AssertCompileSize(VMXAUTOMSR, 16);
1109	/** Pointer to an MSR load/store element. */
1110	typedef VMXAUTOMSR *PVMXAUTOMSR;
1111	/** Pointer to a const MSR load/store element. */
1112	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1113
1114	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1115	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1116
1117	/**
1118	* VMX tagged-TLB flush types.
1119	*/
1120	typedef enum
1121	{
1122	VMXTLBFLUSHTYPE_EPT,
1123	VMXTLBFLUSHTYPE_VPID,
1124	VMXTLBFLUSHTYPE_EPT_VPID,
1125	VMXTLBFLUSHTYPE_NONE
1126	} VMXTLBFLUSHTYPE;
1127	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1128	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1129	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1130	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1131
1132	/**
1133	* VMX controls MSR.
1134	* In accordance with the VT-x spec.
1135	*/
1136	typedef union
1137	{
1138	struct
1139	{
1140	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1141	uint32_t allowed0;
1142	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1143	* controls. */
1144	uint32_t allowed1;
1145	} n;
1146	uint64_t u;
1147	} VMXCTLSMSR;
1148	AssertCompileSize(VMXCTLSMSR, 8);
1149	/** Pointer to a VMXCTLSMSR union. */
1150	typedef VMXCTLSMSR *PVMXCTLSMSR;
1151	/** Pointer to a const VMXCTLSMSR union. */
1152	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1153
1154	/**
1155	* VMX MSRs.
1156	*/
1157	typedef struct VMXMSRS
1158	{
1159	/** VMX/SMX Feature control. */
1160	uint64_t u64FeatCtrl;
1161	/** Basic information. */
1162	uint64_t u64Basic;
1163	/** Pin-based VM-execution controls. */
1164	VMXCTLSMSR PinCtls;
1165	/** Processor-based VM-execution controls. */
1166	VMXCTLSMSR ProcCtls;
1167	/** Secondary processor-based VM-execution controls. */
1168	VMXCTLSMSR ProcCtls2;
1169	/** VM-exit controls. */
1170	VMXCTLSMSR ExitCtls;
1171	/** VM-entry controls. */
1172	VMXCTLSMSR EntryCtls;
1173	/** True pin-based VM-execution controls. */
1174	VMXCTLSMSR TruePinCtls;
1175	/** True processor-based VM-execution controls. */
1176	VMXCTLSMSR TrueProcCtls;
1177	/** True VM-entry controls. */
1178	VMXCTLSMSR TrueEntryCtls;
1179	/** True VM-exit controls. */
1180	VMXCTLSMSR TrueExitCtls;
1181	/** Miscellaneous data. */
1182	uint64_t u64Misc;
1183	/** CR0 fixed-0 - bits set here must be set in VMX operation. */
1184	uint64_t u64Cr0Fixed0;
1185	/** CR0 fixed-1 - bits clear here must be clear in VMX operation. */
1186	uint64_t u64Cr0Fixed1;
1187	/** CR4 fixed-0 - bits set here must be set in VMX operation. */
1188	uint64_t u64Cr4Fixed0;
1189	/** CR4 fixed-1 - bits clear here must be clear in VMX operation. */
1190	uint64_t u64Cr4Fixed1;
1191	/** VMCS enumeration. */
1192	uint64_t u64VmcsEnum;
1193	/** VM Functions. */
1194	uint64_t u64VmFunc;
1195	/** EPT, VPID capabilities. */
1196	uint64_t u64EptVpidCaps;
1197	/** Reserved for future. */
1198	uint64_t a_u64Reserved[9];
1199	} VMXMSRS;
1200	AssertCompileSizeAlignment(VMXMSRS, 8);
1201	AssertCompileSize(VMXMSRS, 224);
1202	/** Pointer to a VMXMSRS struct. */
1203	typedef VMXMSRS *PVMXMSRS;
1204	/** Pointer to a const VMXMSRS struct. */
1205	typedef const VMXMSRS *PCVMXMSRS;
1206
1207
1208	/**
1209	* LBR MSRs.
1210	*/
1211	typedef struct LBRMSRS
1212	{
1213	/** List of LastBranch-From-IP MSRs. */
1214	uint64_t au64BranchFromIpMsr[32];
1215	/** List of LastBranch-To-IP MSRs. */
1216	uint64_t au64BranchToIpMsr[32];
1217	/** The MSR containing the index to the most recent branch record. */
1218	uint64_t uBranchTosMsr;
1219	} LBRMSRS;
1220	AssertCompileSizeAlignment(LBRMSRS, 8);
1221	/** Pointer to a VMXMSRS struct. */
1222	typedef LBRMSRS *PLBRMSRS;
1223	/** Pointer to a const VMXMSRS struct. */
1224	typedef const LBRMSRS *PCLBRMSRS;
1225
1226
1227	/** @name VMX Basic Exit Reasons.
1228	* @{
1229	*/
1230	/** -1 Invalid exit code */
1231	#define VMX_EXIT_INVALID (-1)
1232	/** 0 Exception or non-maskable interrupt (NMI). */
1233	#define VMX_EXIT_XCPT_OR_NMI 0
1234	/** 1 External interrupt. */
1235	#define VMX_EXIT_EXT_INT 1
1236	/** 2 Triple fault. */
1237	#define VMX_EXIT_TRIPLE_FAULT 2
1238	/** 3 INIT signal. */
1239	#define VMX_EXIT_INIT_SIGNAL 3
1240	/** 4 Start-up IPI (SIPI). */
1241	#define VMX_EXIT_SIPI 4
1242	/** 5 I/O system-management interrupt (SMI). */
1243	#define VMX_EXIT_IO_SMI 5
1244	/** 6 Other SMI. */
1245	#define VMX_EXIT_SMI 6
1246	/** 7 Interrupt window exiting. */
1247	#define VMX_EXIT_INT_WINDOW 7
1248	/** 8 NMI window exiting. */
1249	#define VMX_EXIT_NMI_WINDOW 8
1250	/** 9 Task switch. */
1251	#define VMX_EXIT_TASK_SWITCH 9
1252	/** 10 Guest software attempted to execute CPUID. */
1253	#define VMX_EXIT_CPUID 10
1254	/** 11 Guest software attempted to execute GETSEC. */
1255	#define VMX_EXIT_GETSEC 11
1256	/** 12 Guest software attempted to execute HLT. */
1257	#define VMX_EXIT_HLT 12
1258	/** 13 Guest software attempted to execute INVD. */
1259	#define VMX_EXIT_INVD 13
1260	/** 14 Guest software attempted to execute INVLPG. */
1261	#define VMX_EXIT_INVLPG 14
1262	/** 15 Guest software attempted to execute RDPMC. */
1263	#define VMX_EXIT_RDPMC 15
1264	/** 16 Guest software attempted to execute RDTSC. */
1265	#define VMX_EXIT_RDTSC 16
1266	/** 17 Guest software attempted to execute RSM in SMM. */
1267	#define VMX_EXIT_RSM 17
1268	/** 18 Guest software executed VMCALL. */
1269	#define VMX_EXIT_VMCALL 18
1270	/** 19 Guest software executed VMCLEAR. */
1271	#define VMX_EXIT_VMCLEAR 19
1272	/** 20 Guest software executed VMLAUNCH. */
1273	#define VMX_EXIT_VMLAUNCH 20
1274	/** 21 Guest software executed VMPTRLD. */
1275	#define VMX_EXIT_VMPTRLD 21
1276	/** 22 Guest software executed VMPTRST. */
1277	#define VMX_EXIT_VMPTRST 22
1278	/** 23 Guest software executed VMREAD. */
1279	#define VMX_EXIT_VMREAD 23
1280	/** 24 Guest software executed VMRESUME. */
1281	#define VMX_EXIT_VMRESUME 24
1282	/** 25 Guest software executed VMWRITE. */
1283	#define VMX_EXIT_VMWRITE 25
1284	/** 26 Guest software executed VMXOFF. */
1285	#define VMX_EXIT_VMXOFF 26
1286	/** 27 Guest software executed VMXON. */
1287	#define VMX_EXIT_VMXON 27
1288	/** 28 Control-register accesses. */
1289	#define VMX_EXIT_MOV_CRX 28
1290	/** 29 Debug-register accesses. */
1291	#define VMX_EXIT_MOV_DRX 29
1292	/** 30 I/O instruction. */
1293	#define VMX_EXIT_IO_INSTR 30
1294	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1295	#define VMX_EXIT_RDMSR 31
1296	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1297	#define VMX_EXIT_WRMSR 32
1298	/** 33 VM-entry failure due to invalid guest state. */
1299	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1300	/** 34 VM-entry failure due to MSR loading. */
1301	#define VMX_EXIT_ERR_MSR_LOAD 34
1302	/** 36 Guest software executed MWAIT. */
1303	#define VMX_EXIT_MWAIT 36
1304	/** 37 VM-exit due to monitor trap flag. */
1305	#define VMX_EXIT_MTF 37
1306	/** 39 Guest software attempted to execute MONITOR. */
1307	#define VMX_EXIT_MONITOR 39
1308	/** 40 Guest software attempted to execute PAUSE. */
1309	#define VMX_EXIT_PAUSE 40
1310	/** 41 VM-entry failure due to machine-check. */
1311	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1312	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1313	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1314	/** 44 APIC access. Guest software attempted to access memory at a physical
1315	* address on the APIC-access page. */
1316	#define VMX_EXIT_APIC_ACCESS 44
1317	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1318	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1319	#define VMX_EXIT_VIRTUALIZED_EOI 45
1320	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1321	* SGDT, or SIDT. */
1322	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1323	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1324	* SLDT, or STR. */
1325	#define VMX_EXIT_LDTR_TR_ACCESS 47
1326	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1327	* was disallowed by the configuration of the EPT paging structures. */
1328	#define VMX_EXIT_EPT_VIOLATION 48
1329	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1330	* address encountered a misconfigured EPT paging-structure entry. */
1331	#define VMX_EXIT_EPT_MISCONFIG 49
1332	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1333	#define VMX_EXIT_INVEPT 50
1334	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1335	#define VMX_EXIT_RDTSCP 51
1336	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1337	#define VMX_EXIT_PREEMPT_TIMER 52
1338	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1339	#define VMX_EXIT_INVVPID 53
1340	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1341	#define VMX_EXIT_WBINVD 54
1342	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1343	#define VMX_EXIT_XSETBV 55
1344	/** 56 APIC write. Guest completed write to virtual-APIC. */
1345	#define VMX_EXIT_APIC_WRITE 56
1346	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1347	#define VMX_EXIT_RDRAND 57
1348	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1349	#define VMX_EXIT_INVPCID 58
1350	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1351	#define VMX_EXIT_VMFUNC 59
1352	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1353	#define VMX_EXIT_ENCLS 60
1354	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1355	* enabled. */
1356	#define VMX_EXIT_RDSEED 61
1357	/** 62 - Page-modification log full. */
1358	#define VMX_EXIT_PML_FULL 62
1359	/** 63 - XSAVES. Guest software attempted to execute XSAVES and exiting was
1360	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1361	#define VMX_EXIT_XSAVES 63
1362	/** 64 - XRSTORS. Guest software attempted to execute XRSTORS and exiting
1363	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1364	#define VMX_EXIT_XRSTORS 64
1365	/** 66 - SPP-related event. Attempt to determine an access' sub-page write
1366	* permission encountered an SPP miss or misconfiguration. */
1367	#define VMX_EXIT_SPP_EVENT 66
1368	/* 67 - UMWAIT. Guest software attempted to execute UMWAIT and exiting was enabled. */
1369	#define VMX_EXIT_UMWAIT 67
1370	/** 68 - TPAUSE. Guest software attempted to execute TPAUSE and exiting was
1371	* enabled. */
1372	#define VMX_EXIT_TPAUSE 68
1373	/** The maximum exit value (inclusive). */
1374	#define VMX_EXIT_MAX (VMX_EXIT_TPAUSE)
1375	/** @} */
1376
1377
1378	/** @name VM Instruction Errors.
1379	* In accordance with the VT-x spec.
1380	* See Intel spec. "30.4 VM Instruction Error Numbers"
1381	* @{
1382	*/
1383	typedef enum
1384	{
1385	/** VMCALL executed in VMX root operation. */
1386	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1387	/** VMCLEAR with invalid physical address. */
1388	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1389	/** VMCLEAR with VMXON pointer. */
1390	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1391	/** VMLAUNCH with non-clear VMCS. */
1392	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1393	/** VMRESUME with non-launched VMCS. */
1394	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1395	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1396	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1397	/** VM-entry with invalid control field(s). */
1398	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1399	/** VM-entry with invalid host-state field(s). */
1400	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1401	/** VMPTRLD with invalid physical address. */
1402	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1403	/** VMPTRLD with VMXON pointer. */
1404	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1405	/** VMPTRLD with incorrect VMCS revision identifier. */
1406	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1407	/** VMREAD from unsupported VMCS component. */
1408	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1409	/** VMWRITE to unsupported VMCS component. */
1410	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1411	/** VMWRITE to read-only VMCS component. */
1412	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1413	/** VMXON executed in VMX root operation. */
1414	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1415	/** VM-entry with invalid executive-VMCS pointer. */
1416	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1417	/** VM-entry with non-launched executive VMCS. */
1418	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1419	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1420	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1421	/** VMCALL with non-clear VMCS. */
1422	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1423	/** VMCALL with invalid VM-exit control fields. */
1424	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1425	/** VMCALL with incorrect MSEG revision identifier. */
1426	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1427	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1428	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1429	/** VMCALL with invalid SMM-monitor features. */
1430	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1431	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1432	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1433	/** VM-entry with events blocked by MOV SS. */
1434	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1435	/** Invalid operand to INVEPT/INVVPID. */
1436	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1437	} VMXINSTRERR;
1438	/** @} */
1439
1440
1441	/** @name VMX abort reasons.
1442	* In accordance with the VT-x spec.
1443	* See Intel spec. "27.7 VMX Aborts".
1444	* Update HMGetVmxAbortDesc() if new reasons are added.
1445	* @{
1446	*/
1447	typedef enum
1448	{
1449	/** None - don't use this / uninitialized value. */
1450	VMXABORT_NONE = 0,
1451	/** VMX abort caused during saving of guest MSRs. */
1452	VMXABORT_SAVE_GUEST_MSRS = 1,
1453	/** VMX abort caused during host PDPTE checks. */
1454	VMXBOART_HOST_PDPTE = 2,
1455	/** VMX abort caused due to current VMCS being corrupted. */
1456	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1457	/** VMX abort caused during loading of host MSRs. */
1458	VMXABORT_LOAD_HOST_MSR = 4,
1459	/** VMX abort caused due to a machine-check exception during VM-exit. */
1460	VMXABORT_MACHINE_CHECK_XCPT = 5,
1461	/** VMX abort caused due to invalid return from long mode. */
1462	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1463	/* Type size hack. */
1464	VMXABORT_32BIT_HACK = 0x7fffffff
1465	} VMXABORT;
1466	AssertCompileSize(VMXABORT, 4);
1467	/** @} */
1468
1469
1470	/** @name VMX MSR - Basic VMX information.
1471	* @{
1472	*/
1473	/** VMCS (and related regions) memory type - Uncacheable. */
1474	#define VMX_BASIC_MEM_TYPE_UC 0
1475	/** VMCS (and related regions) memory type - Write back. */
1476	#define VMX_BASIC_MEM_TYPE_WB 6
1477	/** Width of physical addresses used for VMCS and associated memory regions
1478	* (1=32-bit, 0=processor's physical address width). */
1479	#define VMX_BASIC_PHYSADDR_WIDTH_32BIT RT_BIT_64(48)
1480
1481	/** Bit fields for MSR_IA32_VMX_BASIC. */
1482	/** VMCS revision identifier used by the processor. */
1483	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1484	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1485	/** Bit 31 is reserved and RAZ. */
1486	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1487	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1488	/** VMCS size in bytes. */
1489	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1490	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1491	/** Bits 45:47 are reserved. */
1492	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1493	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1494	/** Width of physical addresses used for the VMCS and associated memory regions
1495	* (always 0 on CPUs that support Intel 64 architecture). */
1496	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1497	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1498	/** Dual-monitor treatment of SMI and SMM supported. */
1499	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1500	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1501	/** Memory type that must be used for the VMCS and associated memory regions. */
1502	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1503	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1504	/** VM-exit instruction information for INS/OUTS. */
1505	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1506	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1507	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1508	* bits in VMX control MSRs. */
1509	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1510	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1511	/** Whether VM-entry can delivery error code for all hardware exception vectors. */
1512	#define VMX_BF_BASIC_XCPT_ERRCODE_SHIFT 56
1513	#define VMX_BF_BASIC_XCPT_ERRCODE_MASK UINT64_C(0x0100000000000000)
1514	/** Bits 57:63 are reserved and RAZ. */
1515	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 57
1516	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xfe00000000000000)
1517	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1518	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1519	VMCS_INS_OUTS, TRUE_CTLS, XCPT_ERRCODE, RSVD_56_63));
1520	/** @} */
1521
1522
1523	/** @name VMX MSR - Miscellaneous data.
1524	* @{
1525	*/
1526	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1527	#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1528	/** Whether Intel PT is supported in VMX operation. */
1529	#define VMX_MISC_INTEL_PT RT_BIT(14)
1530	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1531	* VMWRITE cannot modify read-only VM-exit information fields. */
1532	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1533	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1534	* instructions. */
1535	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1536	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1537	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1538	/** Maximum CR3-target count supported by the CPU. */
1539	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1540
1541	/** Bit fields for MSR_IA32_VMX_MISC. */
1542	/** Relationship between the preemption timer and tsc. */
1543	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1544	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1545	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1546	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1547	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1548	/** Activity states supported by the implementation. */
1549	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1550	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1551	/** Bits 9:13 is reserved and RAZ. */
1552	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1553	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1554	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1555	#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1556	#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1557	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1558	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1559	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1560	/** Number of CR3 target values supported by the processor. (0-256) */
1561	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1562	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1563	/** Maximum number of MSRs in the VMCS. */
1564	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1565	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1566	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1567	* SMIs. */
1568	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1569	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1570	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1571	* VMWRITE cannot modify read-only VM-exit information fields. */
1572	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1573	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1574	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1575	* instructions. */
1576	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1577	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1578	/** Bit 31 is reserved and RAZ. */
1579	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1580	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1581	/** 32-bit MSEG revision ID used by the processor. */
1582	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1583	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1584	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1585	(PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1586	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1587	/** @} */
1588
1589	/** @name VMX MSR - VMCS enumeration.
1590	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1591	* @{
1592	*/
1593	/** Bit 0 is reserved and RAZ. */
1594	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1595	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1596	/** Highest index value used in VMCS field encoding. */
1597	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1598	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1599	/** Bit 10:63 is reserved and RAZ. */
1600	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1601	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1602	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1603	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1604	/** @} */
1605
1606
1607	/** @name VMX MSR - VM Functions.
1608	* Bit fields for MSR_IA32_VMX_VMFUNC.
1609	* @{
1610	*/
1611	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1612	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1613	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1614	/** Bits 1:63 are reserved and RAZ. */
1615	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1616	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1617	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1618	(EPTP_SWITCHING, RSVD_1_63));
1619	/** @} */
1620
1621
1622	/** @name VMX MSR - EPT/VPID capabilities.
1623	* @{
1624	*/
1625	/** Supports execute-only translations by EPT. */
1626	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1627	/** Supports page-walk length of 4. */
1628	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1629	/** Supports page-walk length of 5. */
1630	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5 RT_BIT_64(7)
1631	/** Supports EPT paging-structure memory type to be uncacheable. */
1632	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1633	/** Supports EPT paging structure memory type to be write-back. */
1634	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1635	/** Supports EPT PDE to map a 2 MB page. */
1636	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1637	/** Supports EPT PDPTE to map a 1 GB page. */
1638	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1639	/** Supports INVEPT instruction. */
1640	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1641	/** Supports accessed and dirty flags for EPT. */
1642	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1643	/** Supports advanced VM-exit info. for EPT violations. */
1644	#define MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT RT_BIT_64(22)
1645	/** Supports supervisor shadow-stack control. */
1646	#define MSR_IA32_VMX_EPT_VPID_CAP_SSS RT_BIT_64(23)
1647	/** Supports single-context INVEPT type. */
1648	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1649	/** Supports all-context INVEPT type. */
1650	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1651	/** Supports INVVPID instruction. */
1652	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1653	/** Supports individual-address INVVPID type. */
1654	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1655	/** Supports single-context INVVPID type. */
1656	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1657	/** Supports all-context INVVPID type. */
1658	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1659	/** Supports singe-context-retaining-globals INVVPID type. */
1660	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1661
1662	/** Bit fields for MSR_IA32_VMX_EPT_VPID_CAP. */
1663	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_SHIFT 0
1664	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_MASK UINT64_C(0x0000000000000001)
1665	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_SHIFT 1
1666	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_MASK UINT64_C(0x000000000000003e)
1667	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_SHIFT 6
1668	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_MASK UINT64_C(0x0000000000000040)
1669	#define VMX_BF_EPT_VPID_CAP_RSVD_7_SHIFT 7
1670	#define VMX_BF_EPT_VPID_CAP_RSVD_7_MASK UINT64_C(0x0000000000000080)
1671	#define VMX_BF_EPT_VPID_CAP_EMT_UC_SHIFT 8
1672	#define VMX_BF_EPT_VPID_CAP_EMT_UC_MASK UINT64_C(0x0000000000000100)
1673	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_SHIFT 9
1674	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1675	#define VMX_BF_EPT_VPID_CAP_EMT_WB_SHIFT 14
1676	#define VMX_BF_EPT_VPID_CAP_EMT_WB_MASK UINT64_C(0x0000000000004000)
1677	#define VMX_BF_EPT_VPID_CAP_RSVD_15_SHIFT 15
1678	#define VMX_BF_EPT_VPID_CAP_RSVD_15_MASK UINT64_C(0x0000000000008000)
1679	#define VMX_BF_EPT_VPID_CAP_PDE_2M_SHIFT 16
1680	#define VMX_BF_EPT_VPID_CAP_PDE_2M_MASK UINT64_C(0x0000000000010000)
1681	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_SHIFT 17
1682	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_MASK UINT64_C(0x0000000000020000)
1683	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_SHIFT 18
1684	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_MASK UINT64_C(0x00000000000c0000)
1685	#define VMX_BF_EPT_VPID_CAP_INVEPT_SHIFT 20
1686	#define VMX_BF_EPT_VPID_CAP_INVEPT_MASK UINT64_C(0x0000000000100000)
1687	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_SHIFT 21
1688	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_MASK UINT64_C(0x0000000000200000)
1689	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_SHIFT 22
1690	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_MASK UINT64_C(0x0000000000400000)
1691	#define VMX_BF_EPT_VPID_CAP_SSS_SHIFT 23
1692	#define VMX_BF_EPT_VPID_CAP_SSS_MASK UINT64_C(0x0000000000800000)
1693	#define VMX_BF_EPT_VPID_CAP_RSVD_24_SHIFT 24
1694	#define VMX_BF_EPT_VPID_CAP_RSVD_24_MASK UINT64_C(0x0000000001000000)
1695	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_SHIFT 25
1696	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_MASK UINT64_C(0x0000000002000000)
1697	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_SHIFT 26
1698	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_MASK UINT64_C(0x0000000004000000)
1699	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_SHIFT 27
1700	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_MASK UINT64_C(0x00000000f8000000)
1701	#define VMX_BF_EPT_VPID_CAP_INVVPID_SHIFT 32
1702	#define VMX_BF_EPT_VPID_CAP_INVVPID_MASK UINT64_C(0x0000000100000000)
1703	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_SHIFT 33
1704	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_MASK UINT64_C(0x000000fe00000000)
1705	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_SHIFT 40
1706	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_MASK UINT64_C(0x0000010000000000)
1707	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_SHIFT 41
1708	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_MASK UINT64_C(0x0000020000000000)
1709	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_SHIFT 42
1710	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_MASK UINT64_C(0x0000040000000000)
1711	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_SHIFT 43
1712	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_MASK UINT64_C(0x0000080000000000)
1713	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_SHIFT 44
1714	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_MASK UINT64_C(0xfffff00000000000)
1715	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_VPID_CAP_, UINT64_C(0), UINT64_MAX,
1716	(RWX_X_ONLY, RSVD_1_5, PAGE_WALK_LENGTH_4, RSVD_7, EMT_UC, RSVD_9_13, EMT_WB, RSVD_15, PDE_2M,
1717	PDPTE_1G, RSVD_18_19, INVEPT, EPT_ACCESS_DIRTY, ADVEXITINFO_EPT, SSS, RSVD_24, INVEPT_SINGLE_CTX,
1718	INVEPT_ALL_CTX, RSVD_27_31, INVVPID, RSVD_33_39, INVVPID_INDIV_ADDR, INVVPID_SINGLE_CTX,
1719	INVVPID_ALL_CTX, INVVPID_SINGLE_CTX_RETAIN_GLOBALS, RSVD_44_63));
1720	/** @} */
1721
1722
1723	/** @name Extended Page Table Pointer (EPTP)
1724	* @{
1725	*/
1726	/** Uncachable EPT paging structure memory type. */
1727	#define VMX_EPT_MEMTYPE_UC 0
1728	/** Write-back EPT paging structure memory type. */
1729	#define VMX_EPT_MEMTYPE_WB 6
1730	/** Shift value to get the EPT page walk length (bits 5-3) */
1731	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1732	/** Mask value to get the EPT page walk length (bits 5-3) */
1733	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1734	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1735	* length) */
1736	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1737	/** @} */
1738
1739
1740	/** @name VMCS fields and encoding.
1741	*
1742	* When adding a new field:
1743	* - Always add it to g_aVmcsFields.
1744	* - Consider if it needs to be added to VMXVVMCS.
1745	* @{
1746	*/
1747	/** 16-bit control fields. */
1748	#define VMX_VMCS16_VPID 0x0000
1749	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1750	#define VMX_VMCS16_EPTP_INDEX 0x0004
1751
1752	/** 16-bit guest-state fields. */
1753	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1754	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1755	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1756	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1757	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1758	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1759	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1760	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1761	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1762	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1763
1764	/** 16-bits host-state fields. */
1765	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1766	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1767	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1768	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1769	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1770	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1771	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1772
1773	/** 64-bit control fields. */
1774	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1775	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1776	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1777	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1778	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1779	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1780	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1781	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1782	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1783	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1784	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1785	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1786	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1787	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1788	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1789	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1790	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1791	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1792	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1793	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1794	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1795	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1796	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1797	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1798	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1799	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1800	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1801	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1802	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1803	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1804	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1805	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1806	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1807	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1808	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1809	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1810	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1811	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1812	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1813	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1814	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1815	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1816	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1817	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1818	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1819	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1820	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1821	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1822	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1823	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1824
1825	/** 64-bit read-only data fields. */
1826	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1827	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1828
1829	/** 64-bit guest-state fields. */
1830	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1831	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1832	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1833	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1834	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1835	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1836	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1837	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1838	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1839	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1840	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1841	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1842	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1843	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1844	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1845	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1846	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1847	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1848	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1849	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1850
1851	/** 64-bit host-state fields. */
1852	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1853	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1854	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1855	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1856	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1857	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1858
1859	/** 32-bit control fields. */
1860	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1861	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1862	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1863	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1864	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1865	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1866	#define VMX_VMCS32_CTRL_EXIT 0x400c
1867	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1868	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1869	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1870	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1871	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1872	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1873	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1874	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1875	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1876	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1877	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1878
1879	/** 32-bits read-only fields. */
1880	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1881	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1882	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1883	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1884	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1885	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1886	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1887	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1888
1889	/** 32-bit guest-state fields. */
1890	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1891	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1892	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1893	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1894	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1895	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1896	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1897	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1898	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1899	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1900	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1901	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1902	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1903	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1904	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1905	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1906	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1907	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1908	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1909	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1910	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1911	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
1912	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1913
1914	/** 32-bit host-state fields. */
1915	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1916
1917	/** Natural-width control fields. */
1918	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1919	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1920	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1921	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1922	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1923	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1924	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1925	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
1926
1927	/** Natural-width read-only data fields. */
1928	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1929	#define VMX_VMCS_RO_IO_RCX 0x6402
1930	#define VMX_VMCS_RO_IO_RSI 0x6404
1931	#define VMX_VMCS_RO_IO_RDI 0x6406
1932	#define VMX_VMCS_RO_IO_RIP 0x6408
1933	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
1934
1935	/** Natural-width guest-state fields. */
1936	#define VMX_VMCS_GUEST_CR0 0x6800
1937	#define VMX_VMCS_GUEST_CR3 0x6802
1938	#define VMX_VMCS_GUEST_CR4 0x6804
1939	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1940	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1941	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1942	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1943	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1944	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1945	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1946	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1947	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1948	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1949	#define VMX_VMCS_GUEST_DR7 0x681a
1950	#define VMX_VMCS_GUEST_RSP 0x681c
1951	#define VMX_VMCS_GUEST_RIP 0x681e
1952	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1953	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
1954	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
1955	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
1956
1957	/** Natural-width host-state fields. */
1958	#define VMX_VMCS_HOST_CR0 0x6c00
1959	#define VMX_VMCS_HOST_CR3 0x6c02
1960	#define VMX_VMCS_HOST_CR4 0x6c04
1961	#define VMX_VMCS_HOST_FS_BASE 0x6c06
1962	#define VMX_VMCS_HOST_GS_BASE 0x6c08
1963	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
1964	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
1965	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
1966	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
1967	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
1968	#define VMX_VMCS_HOST_RSP 0x6c14
1969	#define VMX_VMCS_HOST_RIP 0x6c16
1970
1971	/**
1972	* VMCS field.
1973	* In accordance with the VT-x spec.
1974	*/
1975	typedef union
1976	{
1977	struct
1978	{
1979	/** The access type; 0=full, 1=high of 64-bit fields. */
1980	uint32_t fAccessType : 1;
1981	/** The index. */
1982	uint32_t u8Index : 8;
1983	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
1984	uint32_t u2Type : 2;
1985	/** Reserved (MBZ). */
1986	uint32_t u1Reserved0 : 1;
1987	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
1988	uint32_t u2Width : 2;
1989	/** Reserved (MBZ). */
1990	uint32_t u18Reserved0 : 18;
1991	} n;
1992
1993	/* The unsigned integer view. */
1994	uint32_t u;
1995	} VMXVMCSFIELD;
1996	AssertCompileSize(VMXVMCSFIELD, 4);
1997	/** Pointer to a VMCS field. */
1998	typedef VMXVMCSFIELD *PVMXVMCSFIELD;
1999	/** Pointer to a const VMCS field. */
2000	typedef const VMXVMCSFIELD *PCVMXVMCSFIELD;
2001
2002	/** VMCS field: Mask of reserved bits (bits 63:15 MBZ), bit 12 is not included! */
2003	#define VMX_VMCSFIELD_RSVD_MASK UINT64_C(0xffffffffffff8000)
2004
2005	/** Bits fields for a VMCS field. */
2006	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_SHIFT 0
2007	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2008	#define VMX_BF_VMCSFIELD_INDEX_SHIFT 1
2009	#define VMX_BF_VMCSFIELD_INDEX_MASK UINT32_C(0x000003fe)
2010	#define VMX_BF_VMCSFIELD_TYPE_SHIFT 10
2011	#define VMX_BF_VMCSFIELD_TYPE_MASK UINT32_C(0x00000c00)
2012	#define VMX_BF_VMCSFIELD_RSVD_12_SHIFT 12
2013	#define VMX_BF_VMCSFIELD_RSVD_12_MASK UINT32_C(0x00001000)
2014	#define VMX_BF_VMCSFIELD_WIDTH_SHIFT 13
2015	#define VMX_BF_VMCSFIELD_WIDTH_MASK UINT32_C(0x00006000)
2016	#define VMX_BF_VMCSFIELD_RSVD_15_31_SHIFT 15
2017	#define VMX_BF_VMCSFIELD_RSVD_15_31_MASK UINT32_C(0xffff8000)
2018	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCSFIELD_, UINT32_C(0), UINT32_MAX,
2019	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2020
2021	/**
2022	* VMCS field encoding: Access type.
2023	* In accordance with the VT-x spec.
2024	*/
2025	typedef enum
2026	{
2027	VMXVMCSFIELDACCESS_FULL = 0,
2028	VMXVMCSFIELDACCESS_HIGH
2029	} VMXVMCSFIELDACCESS;
2030	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
2031	/** VMCS field encoding type: Full. */
2032	#define VMX_VMCSFIELD_ACCESS_FULL 0
2033	/** VMCS field encoding type: High. */
2034	#define VMX_VMCSFIELD_ACCESS_HIGH 1
2035
2036	/**
2037	* VMCS field encoding: Type.
2038	* In accordance with the VT-x spec.
2039	*/
2040	typedef enum
2041	{
2042	VMXVMCSFIELDTYPE_CONTROL = 0,
2043	VMXVMCSFIELDTYPE_VMEXIT_INFO,
2044	VMXVMCSFIELDTYPE_GUEST_STATE,
2045	VMXVMCSFIELDTYPE_HOST_STATE
2046	} VMXVMCSFIELDTYPE;
2047	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
2048	/** VMCS field encoding type: Control. */
2049	#define VMX_VMCSFIELD_TYPE_CONTROL 0
2050	/** VMCS field encoding type: VM-exit information / read-only fields. */
2051	#define VMX_VMCSFIELD_TYPE_VMEXIT_INFO 1
2052	/** VMCS field encoding type: Guest-state. */
2053	#define VMX_VMCSFIELD_TYPE_GUEST_STATE 2
2054	/** VMCS field encoding type: Host-state. */
2055	#define VMX_VMCSFIELD_TYPE_HOST_STATE 3
2056
2057	/**
2058	* VMCS field encoding: Width.
2059	* In accordance with the VT-x spec.
2060	*/
2061	typedef enum
2062	{
2063	VMXVMCSFIELDWIDTH_16BIT = 0,
2064	VMXVMCSFIELDWIDTH_64BIT,
2065	VMXVMCSFIELDWIDTH_32BIT,
2066	VMXVMCSFIELDWIDTH_NATURAL
2067	} VMXVMCSFIELDWIDTH;
2068	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
2069	/** VMCS field encoding width: 16-bit. */
2070	#define VMX_VMCSFIELD_WIDTH_16BIT 0
2071	/** VMCS field encoding width: 64-bit. */
2072	#define VMX_VMCSFIELD_WIDTH_64BIT 1
2073	/** VMCS field encoding width: 32-bit. */
2074	#define VMX_VMCSFIELD_WIDTH_32BIT 2
2075	/** VMCS field encoding width: Natural width. */
2076	#define VMX_VMCSFIELD_WIDTH_NATURAL 3
2077	/** @} */
2078
2079
2080	/** @name VM-entry instruction length.
2081	* @{ */
2082	/** The maximum valid value for VM-entry instruction length while injecting a
2083	* software interrupt, software exception or privileged software exception. */
2084	#define VMX_ENTRY_INSTR_LEN_MAX 15
2085	/** @} */
2086
2087
2088	/** @name VM-entry register masks.
2089	* @{ */
2090	/** CR0 bits ignored on VM-entry while loading guest CR0 (ET, CD, NW, bits 6:15,
2091	* bit 17 and bits 19:28). */
2092	#define VMX_ENTRY_GUEST_CR0_IGNORE_MASK UINT64_C(0x7ffaffd0)
2093	/** DR7 bits set here are always cleared on VM-entry while loading guest DR7 (bit
2094	* 12, bits 14:15). */
2095	#define VMX_ENTRY_GUEST_DR7_MBZ_MASK UINT64_C(0xd000)
2096	/** DR7 bits set here are always set on VM-entry while loading guest DR7 (bit
2097	* 10). */
2098	#define VMX_ENTRY_GUEST_DR7_MB1_MASK UINT64_C(0x400)
2099	/** @} */
2100
2101
2102	/** @name VM-exit register masks.
2103	* @{ */
2104	/** CR0 bits ignored on VM-exit while loading host CR0 (ET, CD, NW, bits 6:15,
2105	* bit 17, bits 19:28 and bits 32:63). */
2106	#define VMX_EXIT_HOST_CR0_IGNORE_MASK UINT64_C(0xffffffff7ffaffd0)
2107	/** @} */
2108
2109
2110	/** @name Pin-based VM-execution controls.
2111	* @{
2112	*/
2113	/** External interrupt exiting. */
2114	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
2115	/** NMI exiting. */
2116	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
2117	/** Virtual NMIs. */
2118	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
2119	/** Activate VMX preemption timer. */
2120	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
2121	/** Process interrupts with the posted-interrupt notification vector. */
2122	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
2123	/** Default1 class when true capability MSRs are not supported. */
2124	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
2125
2126	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
2127	* controls field in the VMCS. */
2128	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
2129	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
2130	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
2131	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
2132	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
2133	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
2134	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
2135	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
2136	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
2137	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
2138	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
2139	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
2140	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
2141	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
2142	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
2143	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
2144	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
2145	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
2146	/** @} */
2147
2148
2149	/** @name Processor-based VM-execution controls.
2150	* @{
2151	*/
2152	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
2153	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
2154	/** Use timestamp counter offset. */
2155	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
2156	/** VM-exit when executing the HLT instruction. */
2157	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
2158	/** VM-exit when executing the INVLPG instruction. */
2159	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
2160	/** VM-exit when executing the MWAIT instruction. */
2161	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
2162	/** VM-exit when executing the RDPMC instruction. */
2163	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
2164	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
2165	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
2166	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
2167	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2168	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
2169	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
2170	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2171	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
2172	/** VM-exit on CR8 loads. */
2173	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
2174	/** VM-exit on CR8 stores. */
2175	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
2176	/** Use TPR shadow. */
2177	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
2178	/** VM-exit when virtual NMI blocking is disabled. */
2179	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
2180	/** VM-exit when executing a MOV DRx instruction. */
2181	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
2182	/** VM-exit when executing IO instructions. */
2183	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
2184	/** Use IO bitmaps. */
2185	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
2186	/** Monitor trap flag. */
2187	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2188	/** Use MSR bitmaps. */
2189	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2190	/** VM-exit when executing the MONITOR instruction. */
2191	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2192	/** VM-exit when executing the PAUSE instruction. */
2193	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2194	/** Whether the secondary processor based VM-execution controls are used. */
2195	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2196	/** Default1 class when true-capability MSRs are not supported. */
2197	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2198
2199	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2200	* controls field in the VMCS. */
2201	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
2202	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2203	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2204	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2205	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2206	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2207	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
2208	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
2209	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2210	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2211	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
2212	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
2213	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2214	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2215	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2216	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2217	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2218	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2219	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2220	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2221	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
2222	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2223	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2224	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2225	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2226	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2227	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
2228	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
2229	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2230	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2231	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2232	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2233	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2234	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2235	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2236	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2237	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2238	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2239	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2240	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2241	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2242	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2243	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
2244	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
2245	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2246	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2247	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2248	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2249	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2250	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2251	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2252	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2253	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2254	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2255	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2256	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
2257	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
2258	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2259	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2260	USE_SECONDARY_CTLS));
2261	/** @} */
2262
2263
2264	/** @name Secondary Processor-based VM-execution controls.
2265	* @{
2266	*/
2267	/** Virtualize APIC accesses. */
2268	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2269	/** EPT supported/enabled. */
2270	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2271	/** Descriptor table instructions cause VM-exits. */
2272	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2273	/** RDTSCP supported/enabled. */
2274	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2275	/** Virtualize x2APIC mode. */
2276	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2277	/** VPID supported/enabled. */
2278	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2279	/** VM-exit when executing the WBINVD instruction. */
2280	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2281	/** Unrestricted guest execution. */
2282	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2283	/** APIC register virtualization. */
2284	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2285	/** Virtual-interrupt delivery. */
2286	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2287	/** A specified number of pause loops cause a VM-exit. */
2288	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2289	/** VM-exit when executing RDRAND instructions. */
2290	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2291	/** Enables INVPCID instructions. */
2292	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2293	/** Enables VMFUNC instructions. */
2294	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2295	/** Enables VMCS shadowing. */
2296	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2297	/** Enables ENCLS VM-exits. */
2298	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2299	/** VM-exit when executing RDSEED. */
2300	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2301	/** Enables page-modification logging. */
2302	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2303	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2304	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
2305	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2306	#define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19)
2307	/** Enables XSAVES/XRSTORS instructions. */
2308	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2309	/** Enables supervisor/user mode based EPT execute permission for linear
2310	* addresses. */
2311	#define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22)
2312	/** Enables EPT permissions to be specified at granularity of 128 bytes. */
2313	#define VMX_PROC_CTLS2_SPPTP_EPT RT_BIT(23)
2314	/** Intel PT output addresses are treated as guest-physical addresses and
2315	* translated using EPT. */
2316	#define VMX_PROC_CTLS2_PT_EPT RT_BIT(24)
2317	/** Use TSC scaling. */
2318	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2319	/** Enables TPAUSE, UMONITOR and UMWAIT instructions. */
2320	#define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26)
2321	/** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */
2322	#define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28)
2323
2324	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2325	* VM-execution controls field in the VMCS. */
2326	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2327	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2328	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2329	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2330	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2331	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2332	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2333	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2334	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2335	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2336	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2337	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2338	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2339	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2340	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2341	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2342	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2343	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2344	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2345	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2346	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2347	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2348	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2349	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2350	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2351	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2352	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2353	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2354	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2355	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2356	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2357	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2358	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2359	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2360	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2361	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2362	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2363	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2364	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19
2365	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000)
2366	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2367	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2368	#define VMX_BF_PROC_CTLS2_UNDEF_21_SHIFT 21
2369	#define VMX_BF_PROC_CTLS2_UNDEF_21_MASK UINT32_C(0x00200000)
2370	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22
2371	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000)
2372	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_SHIFT 23
2373	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_MASK UINT32_C(0x00800000)
2374	#define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24
2375	#define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000)
2376	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2377	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2378	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26
2379	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000)
2380	#define VMX_BF_PROC_CTLS2_UNDEF_27_SHIFT 27
2381	#define VMX_BF_PROC_CTLS2_UNDEF_27_MASK UINT32_C(0x08000000)
2382	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28
2383	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000)
2384	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_SHIFT 29
2385	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_MASK UINT32_C(0xe0000000)
2386
2387	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2388	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2389	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2390	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, UNDEF_21,
2391	MODE_BASED_EPT_PERM, SPPTP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, UNDEF_27, ENCLV_EXIT,
2392	UNDEF_29_31));
2393	/** @} */
2394
2395
2396	/** @name VM-entry controls.
2397	* @{
2398	*/
2399	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2400	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2401	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2402	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2403	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2404	/** In SMM mode after VM-entry. */
2405	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2406	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2407	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2408	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2409	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2410	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2411	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2412	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2413	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2414	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2415	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2416	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2417	#define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17)
2418	/** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
2419	#define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18)
2420	/** Whether the guest CET-related MSRs and SPP are loaded on VM-entry. */
2421	#define VMX_ENTRY_CTLS_LOAD_CET_STATE RT_BIT(20)
2422	/** Default1 class when true-capability MSRs are not supported. */
2423	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2424
2425	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2426	* VMCS. */
2427	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2428	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2429	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2430	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2431	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2432	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2433	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2434	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2435	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2436	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2437	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2438	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2439	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2440	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2441	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2442	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2443	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2444	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2445	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2446	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2447	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2448	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2449	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17
2450	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000)
2451	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18
2452	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000)
2453	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_SHIFT 19
2454	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_MASK UINT32_C(0xfff80000)
2455	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2456	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2457	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
2458	LOAD_RTIT_CTL_MSR, UNDEF_19_31));
2459	/** @} */
2460
2461
2462	/** @name VM-exit controls.
2463	* @{
2464	*/
2465	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2466	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2467	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2468	/** Return to long mode after a VM-exit. */
2469	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2470	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2471	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2472	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2473	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2474	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2475	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2476	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2477	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2478	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2479	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2480	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2481	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2482	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2483	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2484	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2485	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2486	/** Whether to conceal VMX from Intel PT. */
2487	#define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24)
2488	/** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
2489	#define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25)
2490	/** Whether CET-related MSRs and SPP are loaded on VM-exit. */
2491	#define VMX_EXIT_CTLS_LOAD_CET_STATE RT_BIT(28)
2492	/** Default1 class when true-capability MSRs are not supported. */
2493	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2494
2495	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2496	* VMCS. */
2497	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2498	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2499	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2500	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2501	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2502	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2503	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2504	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2505	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2506	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2507	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2508	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2509	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2510	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2511	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2512	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2513	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2514	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2515	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2516	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2517	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2518	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2519	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2520	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2521	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2522	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2523	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2524	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2525	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23
2526	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000)
2527	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24
2528	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000)
2529	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25
2530	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000)
2531	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_SHIFT 26
2532	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2533	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2534	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2535	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2536	SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, UNDEF_26_31));
2537	/** @} */
2538
2539
2540	/** @name VM-exit reason.
2541	* @{
2542	*/
2543	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2544	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2545	#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2546
2547	/** Bit fields for VM-exit reason. */
2548	/** The exit reason. */
2549	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2550	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2551	/** Bits 16:26 are reseved and MBZ. */
2552	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2553	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2554	/** Whether the VM-exit was incident to enclave mode. */
2555	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2556	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2557	/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2558	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2559	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2560	/** VM-exit from VMX root operation (only possible with SMM). */
2561	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2562	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2563	/** Bit 30 is reserved and MBZ. */
2564	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2565	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2566	/** Whether VM-entry failed (currently only happens during loading guest-state
2567	* or MSRs or machine check exceptions). */
2568	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2569	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2570	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2571	(BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2572	/** @} */
2573
2574
2575	/** @name VM-entry interruption information.
2576	* @{
2577	*/
2578	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2579	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2580	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2581	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2582	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2583	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2584	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2585	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2586	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2587	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2588	/** Construct an VM-entry interruption information field from a VM-exit interruption
2589	* info value (same except that bit 12 is reserved). */
2590	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2591	/** Construct a VM-entry interruption information field from an IDT-vectoring
2592	* information field (same except that bit 12 is reserved). */
2593	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2594	/** If the VM-entry interruption information field indicates a page-fault. */
2595	#define VMX_ENTRY_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2596	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2597	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2598	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2599	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT) \
2600	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_PF)))
2601	/** If the VM-entry interruption information field indicates an external
2602	* interrupt. */
2603	#define VMX_ENTRY_INT_INFO_IS_EXT_INT(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2604	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK)) \
2605	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2606	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_EXT_INT)))
2607	/** If the VM-entry interruption information field indicates an NMI. */
2608	#define VMX_ENTRY_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2609	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2610	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2611	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2612	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_NMI) \
2613	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_NMI)))
2614
2615	/** Bit fields for VM-entry interruption information. */
2616	/** The VM-entry interruption vector. */
2617	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2618	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2619	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2620	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2621	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2622	/** Whether this event has an error code. */
2623	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2624	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2625	/** Bits 12:30 are reserved and MBZ. */
2626	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2627	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2628	/** Whether this VM-entry interruption info is valid. */
2629	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2630	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2631	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2632	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2633	/** @} */
2634
2635
2636	/** @name VM-entry exception error code.
2637	* @{ */
2638	/** Error code valid mask. */
2639	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2640	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2641	* stack aligned for doubleword pushes, the upper half of the error code is
2642	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2643	* use below. */
2644	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2645	/** @} */
2646
2647	/** @name VM-entry interruption information types.
2648	* @{
2649	*/
2650	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2651	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2652	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2653	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2654	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2655	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2656	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2657	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2658	/** @} */
2659
2660
2661	/** @name VM-entry interruption information vector types for
2662	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2663	* @{ */
2664	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2665	/** @} */
2666
2667
2668	/** @name VM-exit interruption information.
2669	* @{
2670	*/
2671	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2672	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2673	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2674	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2675	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2676	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2677	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2678	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2679	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2680
2681	/** If the VM-exit interruption information field indicates an page-fault. */
2682	#define VMX_EXIT_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2683	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2684	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2685	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2686	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2687	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_PF)))
2688	/** If the VM-exit interruption information field indicates an double-fault. */
2689	#define VMX_EXIT_INT_INFO_IS_XCPT_DF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2690	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2691	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2692	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2693	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2694	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)))
2695	/** If the VM-exit interruption information field indicates an NMI. */
2696	#define VMX_EXIT_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2697	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2698	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2699	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2700	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI) \
2701	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI)))
2702
2703
2704	/** Bit fields for VM-exit interruption infomration. */
2705	/** The VM-exit interruption vector. */
2706	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2707	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2708	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2709	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2710	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2711	/** Whether this event has an error code. */
2712	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2713	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2714	/** Whether NMI-unblocking due to IRET is active. */
2715	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2716	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2717	/** Bits 13:30 is reserved (MBZ). */
2718	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2719	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2720	/** Whether this VM-exit interruption info is valid. */
2721	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2722	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2723	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2724	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2725	/** @} */
2726
2727
2728	/** @name VM-exit interruption information types.
2729	* @{
2730	*/
2731	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2732	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2733	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2734	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2735	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2736	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2737	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2738	/** @} */
2739
2740
2741	/** @name VM-exit instruction identity.
2742	*
2743	* These are found in VM-exit instruction information fields for certain
2744	* instructions.
2745	* @{ */
2746	typedef uint32_t VMXINSTRID;
2747	/** Whether the instruction ID field is valid. */
2748	#define VMXINSTRID_VALID RT_BIT_32(31)
2749	/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
2750	* read or write. */
2751	#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
2752	/** Gets whether the instruction ID is valid or not. */
2753	#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
2754	#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
2755	/** Gets the instruction ID. */
2756	#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W))
2757	/** No instruction ID info. */
2758	#define VMXINSTRID_NONE 0
2759
2760	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2761	#define VMXINSTRID_SGDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2762	#define VMXINSTRID_SIDT (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2763	#define VMXINSTRID_LGDT (0x2 \| VMXINSTRID_VALID)
2764	#define VMXINSTRID_LIDT (0x3 \| VMXINSTRID_VALID)
2765
2766	#define VMXINSTRID_SLDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2767	#define VMXINSTRID_STR (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2768	#define VMXINSTRID_LLDT (0x2 \| VMXINSTRID_VALID)
2769	#define VMXINSTRID_LTR (0x3 \| VMXINSTRID_VALID)
2770
2771	/** The following IDs are used internally (some for logging, others for conveying
2772	* the ModR/M primary operand write bit): */
2773	#define VMXINSTRID_VMLAUNCH (0x10 \| VMXINSTRID_VALID)
2774	#define VMXINSTRID_VMRESUME (0x11 \| VMXINSTRID_VALID)
2775	#define VMXINSTRID_VMREAD (0x12 \| VMXINSTRID_VALID)
2776	#define VMXINSTRID_VMWRITE (0x13 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2777	#define VMXINSTRID_IO_IN (0x14 \| VMXINSTRID_VALID)
2778	#define VMXINSTRID_IO_INS (0x15 \| VMXINSTRID_VALID)
2779	#define VMXINSTRID_IO_OUT (0x16 \| VMXINSTRID_VALID)
2780	#define VMXINSTRID_IO_OUTS (0x17 \| VMXINSTRID_VALID)
2781	#define VMXINSTRID_MOV_TO_DRX (0x18 \| VMXINSTRID_VALID)
2782	#define VMXINSTRID_MOV_FROM_DRX (0x19 \| VMXINSTRID_VALID)
2783	/** @} */
2784
2785
2786	/** @name IDT-vectoring information.
2787	* @{
2788	*/
2789	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2790	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
2791	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2792	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
2793	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2794	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2795	#define VMX_IDT_VECTORING_INFO_VALID RT_BIT(31)
2796
2797	/** Construct an IDT-vectoring information field from an VM-entry interruption
2798	* information field (same except that bit 12 is reserved). */
2799	#define VMX_IDT_VECTORING_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
2800	/** If the IDT-vectoring information field indicates a page-fault. */
2801	#define VMX_IDT_VECTORING_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
2802	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
2803	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
2804	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
2805	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT) \
2806	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_PF)))
2807	/** If the IDT-vectoring information field indicates an NMI. */
2808	#define VMX_IDT_VECTORING_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
2809	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
2810	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
2811	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
2812	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_NMI) \
2813	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_NMI)))
2814
2815
2816	/** Bit fields for IDT-vectoring information. */
2817	/** The IDT-vectoring info vector. */
2818	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2819	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2820	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
2821	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2822	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2823	/** Whether the event has an error code. */
2824	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2825	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2826	/** Bit 12 is undefined. */
2827	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2828	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2829	/** Bits 13:30 is reserved (MBZ). */
2830	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2831	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2832	/** Whether this IDT-vectoring info is valid. */
2833	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2834	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2835	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2836	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2837	/** @} */
2838
2839
2840	/** @name IDT-vectoring information vector types.
2841	* @{
2842	*/
2843	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2844	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2845	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2846	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2847	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2848	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2849	#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
2850	/** @} */
2851
2852
2853	/** @name TPR threshold.
2854	* @{ */
2855	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
2856	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
2857
2858	/** Bit fields for TPR threshold. */
2859	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
2860	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
2861	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
2862	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
2863	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
2864	(TPR, RSVD_4_31));
2865	/** @} */
2866
2867
2868	/** @name Guest-activity states.
2869	* @{
2870	*/
2871	/** The logical processor is active. */
2872	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2873	/** The logical processor is inactive, because it executed a HLT instruction. */
2874	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2875	/** The logical processor is inactive, because of a triple fault or other serious error. */
2876	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2877	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2878	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2879	/** @} */
2880
2881
2882	/** @name Guest-interruptibility states.
2883	* @{
2884	*/
2885	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2886	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2887	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2888	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2889	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
2890
2891	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
2892	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
2893	/** @} */
2894
2895
2896	/** @name Exit qualification for debug exceptions.
2897	* @{
2898	*/
2899	/** Hardware breakpoint 0 was met. */
2900	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
2901	/** Hardware breakpoint 1 was met. */
2902	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
2903	/** Hardware breakpoint 2 was met. */
2904	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
2905	/** Hardware breakpoint 3 was met. */
2906	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
2907	/** Debug register access detected. */
2908	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
2909	/** A debug exception would have been triggered by single-step execution mode. */
2910	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
2911	/** Mask of all valid bits. */
2912	#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
2913	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
2914	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
2915	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
2916	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
2917	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
2918
2919	/** Bit fields for Exit qualifications due to debug exceptions. */
2920	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
2921	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
2922	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
2923	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
2924	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
2925	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
2926	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
2927	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
2928	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
2929	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
2930	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
2931	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
2932	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
2933	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
2934	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
2935	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
2936	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
2937	(BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
2938	/** @} */
2939
2940	/** @name Exit qualification for Mov DRx.
2941	* @{
2942	*/
2943	/** 0-2: Debug register number */
2944	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
2945	/** 3: Reserved; cleared to 0. */
2946	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
2947	/** 4: Direction of move (0 = write, 1 = read) */
2948	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
2949	/** 5-7: Reserved; cleared to 0. */
2950	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
2951	/** 8-11: General purpose register number. */
2952	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
2953
2954	/** Bit fields for Exit qualification due to Mov DRx. */
2955	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
2956	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
2957	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
2958	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
2959	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
2960	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
2961	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
2962	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
2963	#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
2964	#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
2965	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
2966	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
2967	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
2968	(REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
2969	/** @} */
2970
2971
2972	/** @name Exit qualification for debug exceptions types.
2973	* @{
2974	*/
2975	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
2976	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
2977	/** @} */
2978
2979
2980	/** @name Exit qualification for control-register accesses.
2981	* @{
2982	*/
2983	/** 0-3: Control register number (0 for CLTS & LMSW) */
2984	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
2985	/** 4-5: Access type. */
2986	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
2987	/** 6: LMSW operand type memory (1 for memory, 0 for register). */
2988	#define VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(a) (((a) >> 6) & 1)
2989	/** 7: Reserved; cleared to 0. */
2990	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
2991	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
2992	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
2993	/** 12-15: Reserved; cleared to 0. */
2994	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
2995	/** 16-31: LMSW source data (else 0). */
2996	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
2997
2998	/** Bit fields for Exit qualification for control-register accesses. */
2999	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
3000	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
3001	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
3002	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
3003	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
3004	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
3005	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
3006	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
3007	#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
3008	#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3009	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
3010	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
3011	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
3012	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
3013	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
3014	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3015	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
3016	(REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
3017	/** @} */
3018
3019
3020	/** @name Exit qualification for control-register access types.
3021	* @{
3022	*/
3023	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
3024	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
3025	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
3026	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
3027	/** @} */
3028
3029
3030	/** @name Exit qualification for task switch.
3031	* @{
3032	*/
3033	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
3034	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
3035	/** Task switch caused by a call instruction. */
3036	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
3037	/** Task switch caused by an iret instruction. */
3038	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
3039	/** Task switch caused by a jmp instruction. */
3040	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
3041	/** Task switch caused by an interrupt gate. */
3042	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
3043
3044	/** Bit fields for Exit qualification for task switches. */
3045	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
3046	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
3047	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
3048	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
3049	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
3050	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
3051	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
3052	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3053	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
3054	(NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
3055	/** @} */
3056
3057
3058	/** @name Exit qualification for EPT violations.
3059	* @{
3060	*/
3061	/** Set if the violation was caused by a data read. */
3062	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
3063	/** Set if the violation was caused by a data write. */
3064	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
3065	/** Set if the violation was caused by an instruction fetch. */
3066	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
3067	/** AND of the present bit of all EPT structures. */
3068	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
3069	/** AND of the write bit of all EPT structures. */
3070	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
3071	/** AND of the execute bit of all EPT structures. */
3072	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
3073	/** Set if the guest linear address field contains the faulting address. */
3074	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
3075	/** If bit 7 is one: (reserved otherwise)
3076	* 1 - violation due to physical address access.
3077	* 0 - violation caused by page walk or access/dirty bit updates
3078	*/
3079	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
3080	/** NMI unblocking due to IRET. */
3081	#define VMX_EXIT_QUAL_EPT_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
3082	/** @} */
3083
3084
3085	/** @name Exit qualification for I/O instructions.
3086	* @{
3087	*/
3088	/** 0-2: IO operation size 0(=1 byte), 1(=2 bytes) and 3(=4 bytes). */
3089	#define VMX_EXIT_QUAL_IO_SIZE(a) ((a) & 7)
3090	/** 3: IO operation direction. */
3091	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
3092	/** 4: String IO operation (INS / OUTS). */
3093	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
3094	/** 5: Repeated IO operation. */
3095	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
3096	/** 6: Operand encoding. */
3097	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
3098	/** 16-31: IO Port (0-0xffff). */
3099	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
3100
3101	/** Bit fields for Exit qualification for I/O instructions. */
3102	#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
3103	#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
3104	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
3105	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
3106	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
3107	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
3108	#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
3109	#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
3110	#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
3111	#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
3112	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
3113	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
3114	#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
3115	#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
3116	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
3117	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3118	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
3119	(WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
3120	/** @} */
3121
3122
3123	/** @name Exit qualification for I/O instruction types.
3124	* @{
3125	*/
3126	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
3127	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
3128	/** @} */
3129
3130
3131	/** @name Exit qualification for I/O instruction encoding.
3132	* @{
3133	*/
3134	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
3135	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
3136	/** @} */
3137
3138
3139	/** @name Exit qualification for APIC-access VM-exits from linear and
3140	* guest-physical accesses.
3141	* @{
3142	*/
3143	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
3144	* access within the APIC page. */
3145	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
3146	/** 12-15: Access type. */
3147	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
3148	/* Rest reserved. */
3149
3150	/** Bit fields for Exit qualification for APIC-access VM-exits. */
3151	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
3152	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
3153	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
3154	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
3155	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
3156	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
3157	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
3158	(OFFSET, TYPE, RSVD_16_63));
3159	/** @} */
3160
3161
3162	/** @name Exit qualification for linear address APIC-access types.
3163	* @{
3164	*/
3165	/** Linear access for a data read during instruction execution. */
3166	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
3167	/** Linear access for a data write during instruction execution. */
3168	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
3169	/** Linear access for an instruction fetch. */
3170	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
3171	/** Linear read/write access during event delivery. */
3172	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
3173	/** Physical read/write access during event delivery. */
3174	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
3175	/** Physical access for an instruction fetch or during instruction execution. */
3176	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
3177
3178	/**
3179	* APIC-access type.
3180	* In accordance with the VT-x spec.
3181	*/
3182	typedef enum
3183	{
3184	VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
3185	VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
3186	VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
3187	VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
3188	VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
3189	VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
3190	} VMXAPICACCESS;
3191	AssertCompileSize(VMXAPICACCESS, 4);
3192	/** @} */
3193
3194
3195	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
3196	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3197	* @{
3198	*/
3199	/** Address calculation scaling field (powers of two). */
3200	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
3201	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3202	/** Bits 2 thru 6 are undefined. */
3203	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
3204	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
3205	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3206	* @remarks anyone's guess why this is a 3 bit field... */
3207	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
3208	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3209	/** Bit 10 is defined as zero. */
3210	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
3211	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
3212	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
3213	* for exits from 64-bit code as the operand size there is fixed. */
3214	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
3215	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
3216	/** Bits 12 thru 14 are undefined. */
3217	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
3218	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
3219	/** Applicable segment register (X86_SREG_XXX values). */
3220	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
3221	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3222	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3223	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
3224	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3225	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3226	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3227	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3228	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3229	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
3230	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3231	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3232	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
3233	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3234	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
3235	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
3236	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3237	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
3238	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
3239	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
3240	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
3241	/** Bits 30 & 31 are undefined. */
3242	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
3243	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3244	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3245	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
3246	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3247	/** @} */
3248
3249
3250	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
3251	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3252	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
3253	* @{
3254	*/
3255	/** Address calculation scaling field (powers of two). */
3256	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
3257	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3258	/** Bit 2 is undefined. */
3259	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
3260	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
3261	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
3262	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
3263	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
3264	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3265	* @remarks anyone's guess why this is a 3 bit field... */
3266	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
3267	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3268	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
3269	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
3270	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
3271	/** Bits 11 thru 14 are undefined. */
3272	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
3273	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
3274	/** Applicable segment register (X86_SREG_XXX values). */
3275	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
3276	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3277	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3278	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
3279	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3280	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3281	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3282	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3283	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3284	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
3285	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3286	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3287	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
3288	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3289	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
3290	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
3291	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3292	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
3293	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
3294	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
3295	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
3296	/** Bits 30 & 31 are undefined. */
3297	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3298	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3299	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3300	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3301	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3302	/** @} */
3303
3304
3305	/** @name Format of Pending-Debug-Exceptions.
3306	* Bits 4-11, 13, 15 and 17-63 are reserved.
3307	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3308	* possibly valid here but not in DR6.
3309	* @{
3310	*/
3311	/** Hardware breakpoint 0 was met. */
3312	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3313	/** Hardware breakpoint 1 was met. */
3314	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3315	/** Hardware breakpoint 2 was met. */
3316	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3317	/** Hardware breakpoint 3 was met. */
3318	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3319	/** At least one data or IO breakpoint was hit. */
3320	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3321	/** A debug exception would have been triggered by single-step execution mode. */
3322	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3323	/** A debug exception occurred inside an RTM region. */
3324	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3325	/** Mask of valid bits. */
3326	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3327	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3328	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3329	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3330	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3331	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3332	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3333	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3334	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3335	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3336	/** Bit fields for Pending debug exceptions. */
3337	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3338	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3339	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3340	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3341	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3342	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3343	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3344	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3345	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3346	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3347	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3348	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3349	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3350	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3351	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3352	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3353	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3354	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3355	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3356	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3357	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3358	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3359	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3360	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3361	/** @} */
3362
3363
3364	/** @defgroup grp_hm_vmx_virt VMX virtualization.
3365	* @{
3366	*/
3367
3368	/** @name Virtual VMX MSR - Miscellaneous data.
3369	* @{ */
3370	/** Number of CR3-target values supported. */
3371	#define VMX_V_CR3_TARGET_COUNT 4
3372	/** Activity states supported. */
3373	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3374	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3375	#define VMX_V_PREEMPT_TIMER_SHIFT 5
3376	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3377	#define VMX_V_AUTOMSR_COUNT_MAX 0
3378	/** SMM MSEG revision ID. */
3379	#define VMX_V_MSEG_REV_ID 0
3380	/** @} */
3381
3382	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS launch state.
3383	* @{ */
3384	/** VMCS launch state clear. */
3385	#define VMX_V_VMCS_LAUNCH_STATE_CLEAR RT_BIT(0)
3386	/** VMCS launch state active. */
3387	#define VMX_V_VMCS_LAUNCH_STATE_ACTIVE RT_BIT(1)
3388	/** VMCS launch state current. */
3389	#define VMX_V_VMCS_LAUNCH_STATE_CURRENT RT_BIT(2)
3390	/** VMCS launch state launched. */
3391	#define VMX_V_VMCS_LAUNCH_STATE_LAUNCHED RT_BIT(3)
3392	/** The mask of valid VMCS launch states. */
3393	#define VMX_V_VMCS_LAUNCH_STATE_MASK ( VMX_V_VMCS_LAUNCH_STATE_CLEAR \
3394	\| VMX_V_VMCS_LAUNCH_STATE_ACTIVE \
3395	\| VMX_V_VMCS_LAUNCH_STATE_CURRENT \
3396	\| VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
3397	/** @} */
3398
3399	/** CR0 bits set here must always be set when in VMX operation. */
3400	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
3401	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
3402	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
3403	/** CR4 bits set here must always be set when in VMX operation. */
3404	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3405
3406	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3407	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3408	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001)
3409	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3410
3411	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3412	* complications when teleporation may be implemented). */
3413	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3414	/** The size of the virtual VMCS region (in pages). */
3415	#define VMX_V_VMCS_PAGES 1
3416
3417	/** The size of the virtual shadow VMCS region. */
3418	#define VMX_V_SHADOW_VMCS_SIZE VMX_V_VMCS_SIZE
3419	/** The size of the virtual shadow VMCS region (in pages). */
3420	#define VMX_V_SHADOW_VMCS_PAGES VMX_V_VMCS_PAGES
3421
3422	/** The size of the Virtual-APIC page (in bytes). */
3423	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3424	/** The size of the Virtual-APIC page (in pages). */
3425	#define VMX_V_VIRT_APIC_PAGES 1
3426
3427	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3428	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3429	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3430	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3431
3432	/** The size of the MSR bitmap (in bytes). */
3433	#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3434	/** The size of the MSR bitmap (in pages). */
3435	#define VMX_V_MSR_BITMAP_PAGES 1
3436
3437	/** The size of I/O bitmap A (in bytes). */
3438	#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3439	/** The size of I/O bitmap A (in pages). */
3440	#define VMX_V_IO_BITMAP_A_PAGES 1
3441
3442	/** The size of I/O bitmap B (in bytes). */
3443	#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3444	/** The size of I/O bitmap B (in pages). */
3445	#define VMX_V_IO_BITMAP_B_PAGES 1
3446
3447	/** The size of the auto-load/store MSR area (in bytes). */
3448	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3449	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3450	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3451	/** The size of the auto-load/store MSR area (in pages). */
3452	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3453
3454	/** The highest index value used for supported virtual VMCS field encoding. */
3455	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCSFIELD_INDEX)
3456
3457	/**
3458	* Virtual VM-exit information.
3459	*
3460	* This is a convenience structure that bundles some VM-exit information related
3461	* fields together.
3462	*/
3463	typedef struct
3464	{
3465	/** The VM-exit reason. */
3466	uint32_t uReason;
3467	/** The VM-exit instruction length. */
3468	uint32_t cbInstr;
3469	/** The VM-exit instruction information. */
3470	VMXEXITINSTRINFO InstrInfo;
3471	/** The VM-exit instruction ID. */
3472	VMXINSTRID uInstrId;
3473
3474	/** The Exit qualification field. */
3475	uint64_t u64Qual;
3476	/** The Guest-linear address field. */
3477	uint64_t u64GuestLinearAddr;
3478	/** The Guest-physical address field. */
3479	uint64_t u64GuestPhysAddr;
3480	/** The guest pending-debug exceptions. */
3481	uint64_t u64GuestPendingDbgXcpts;
3482	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3483	* instruction VM-exit. */
3484	RTGCPTR GCPtrEffAddr;
3485	} VMXVEXITINFO;
3486	/** Pointer to the VMXVEXITINFO struct. */
3487	typedef VMXVEXITINFO *PVMXVEXITINFO;
3488	/** Pointer to a const VMXVEXITINFO struct. */
3489	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3490	AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3491
3492	/**
3493	* Virtual VM-exit information for events.
3494	*
3495	* This is a convenience structure that bundles some event-based VM-exit information
3496	* related fields together that are not included in VMXVEXITINFO.
3497	*
3498	* This is kept as a separate structure and not included in VMXVEXITINFO, to make it
3499	* easier to distinguish that IEM VM-exit handlers will set one or more of the
3500	* following fields in the virtual VMCS. Including it in the VMXVEXITINFO will not
3501	* make it ovbious which fields may get set (or cleared).
3502	*/
3503	typedef struct
3504	{
3505	/** VM-exit interruption information. */
3506	uint32_t uExitIntInfo;
3507	/** VM-exit interruption error code. */
3508	uint32_t uExitIntErrCode;
3509	/** IDT-vectoring information. */
3510	uint32_t uIdtVectoringInfo;
3511	/** IDT-vectoring error code. */
3512	uint32_t uIdtVectoringErrCode;
3513	} VMXVEXITEVENTINFO;
3514	/** Pointer to the VMXVEXITINFO2 struct. */
3515	typedef VMXVEXITEVENTINFO *PVMXVEXITEVENTINFO;
3516	/** Pointer to a const VMXVEXITINFO2 struct. */
3517	typedef const VMXVEXITEVENTINFO *PCVMXVEXITEVENTINFO;
3518
3519	/**
3520	* Virtual VMCS.
3521	*
3522	* This is our custom format. Relevant fields from this VMCS will be merged into the
3523	* actual/shadow VMCS when we execute nested-guest code using hardware-assisted
3524	* VMX.
3525	*
3526	* The first 8 bytes must be in accordance with the Intel VT-x spec.
3527	* See Intel spec. 24.2 "Format of the VMCS Region".
3528	*
3529	* The offset and size of the VMCS state field (@a fVmcsState) is also fixed (not by
3530	* the Intel spec. but for our own requirements) as we use it to offset into guest
3531	* memory.
3532	*
3533	* Although the guest is supposed to access the VMCS only through the execution of
3534	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3535	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
3536	* for teleportation purposes, any newly added fields should be added to the
3537	* appropriate reserved sections or at the end of the structure.
3538	*
3539	* We always treat natural-width fields as 64-bit in our implementation since
3540	* it's easier, allows for teleporation in the future and does not affect guest
3541	* software.
3542	*
3543	* Note! Any fields that are added or modified here, make sure to update the
3544	* corresponding fields in IEM (g_aoffVmcsMap), the corresponding saved
3545	* state structure in CPUM (g_aVmxHwvirtVmcs) and bump the SSM version.
3546	* Also consider updating CPUMIsGuestVmxVmcsFieldValid.
3547	*/
3548	#pragma pack(1)
3549	typedef struct
3550	{
3551	/** @name Header.
3552	* @{
3553	*/
3554	VMXVMCSREVID u32VmcsRevId; /*< 0x000 - VMX VMCS revision identifier. /
3555	VMXABORT enmVmxAbort; /*< 0x004 - VMX-abort indicator. /
3556	uint8_t fVmcsState; /*< 0x008 - VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. /
3557	uint8_t au8Padding0[3]; /*< 0x009 - Reserved for future. /
3558	uint32_t au32Reserved0[12]; /*< 0x00c - Reserved for future. /
3559	/** @} */
3560
3561	/** @name Read-only fields.
3562	* @{ */
3563	/** 16-bit fields. */
3564	uint16_t u16Reserved0[14]; /*< 0x03c - Reserved for future. /
3565
3566	/** 32-bit fields. */
3567	uint32_t u32RoVmInstrError; /*< 0x058 - VM-instruction error. /
3568	uint32_t u32RoExitReason; /*< 0x05c - VM-exit reason. /
3569	uint32_t u32RoExitIntInfo; /*< 0x060 - VM-exit interruption information. /
3570	uint32_t u32RoExitIntErrCode; /*< 0x064 - VM-exit interruption error code. /
3571	uint32_t u32RoIdtVectoringInfo; /*< 0x068 - IDT-vectoring information. /
3572	uint32_t u32RoIdtVectoringErrCode; /*< 0x06c - IDT-vectoring error code. /
3573	uint32_t u32RoExitInstrLen; /*< 0x070 - VM-exit instruction length. /
3574	uint32_t u32RoExitInstrInfo; /*< 0x074 - VM-exit instruction information. /
3575	uint32_t au32RoReserved2[16]; /*< 0x078 - Reserved for future. /
3576
3577	/** 64-bit fields. */
3578	RTUINT64U u64RoGuestPhysAddr; /*< 0x0b8 - Guest-physical address. /
3579	RTUINT64U au64Reserved1[8]; /*< 0x0c0 - Reserved for future. /
3580
3581	/** Natural-width fields. */
3582	RTUINT64U u64RoExitQual; /*< 0x100 - Exit qualification. /
3583	RTUINT64U u64RoIoRcx; /*< 0x108 - I/O RCX. /
3584	RTUINT64U u64RoIoRsi; /*< 0x110 - I/O RSI. /
3585	RTUINT64U u64RoIoRdi; /*< 0x118 - I/O RDI. /
3586	RTUINT64U u64RoIoRip; /*< 0x120 - I/O RIP. /
3587	RTUINT64U u64RoGuestLinearAddr; /*< 0x128 - Guest-linear address. /
3588	RTUINT64U au64Reserved5[16]; /*< 0x130 - Reserved for future. /
3589	/** @} */
3590
3591	/** @name Control fields.
3592	* @{ */
3593	/** 16-bit fields. */
3594	uint16_t u16Vpid; /*< 0x1b0 - Virtual processor ID. /
3595	uint16_t u16PostIntNotifyVector; /*< 0x1b2 - Posted interrupt notify vector. /
3596	uint16_t u16EptpIndex; /*< 0x1b4 - EPTP index. /
3597	uint16_t au16Reserved0[13]; /*< 0x1b6 - Reserved for future. /
3598
3599	/** 32-bit fields. */
3600	uint32_t u32PinCtls; /*< 0x1d0 - Pin-based VM-execution controls. /
3601	uint32_t u32ProcCtls; /*< 0x1d4 - Processor-based VM-execution controls. /
3602	uint32_t u32XcptBitmap; /*< 0x1d8 - Exception bitmap. /
3603	uint32_t u32XcptPFMask; /*< 0x1dc - Page-fault exception error mask. /
3604	uint32_t u32XcptPFMatch; /*< 0x1e0 - Page-fault exception error match. /
3605	uint32_t u32Cr3TargetCount; /*< 0x1e4 - CR3-target count. /
3606	uint32_t u32ExitCtls; /*< 0x1e8 - VM-exit controls. /
3607	uint32_t u32ExitMsrStoreCount; /*< 0x1ec - VM-exit MSR store count. /
3608	uint32_t u32ExitMsrLoadCount; /*< 0x1f0 - VM-exit MSR load count. /
3609	uint32_t u32EntryCtls; /*< 0x1f4 - VM-entry controls. /
3610	uint32_t u32EntryMsrLoadCount; /*< 0x1f8 - VM-entry MSR load count. /
3611	uint32_t u32EntryIntInfo; /*< 0x1fc - VM-entry interruption information. /
3612	uint32_t u32EntryXcptErrCode; /*< 0x200 - VM-entry exception error code. /
3613	uint32_t u32EntryInstrLen; /*< 0x204 - VM-entry instruction length. /
3614	uint32_t u32TprThreshold; /*< 0x208 - TPR-threshold. /
3615	uint32_t u32ProcCtls2; /*< 0x20c - Secondary-processor based VM-execution controls. /
3616	uint32_t u32PleGap; /*< 0x210 - Pause-loop exiting Gap. /
3617	uint32_t u32PleWindow; /*< 0x214 - Pause-loop exiting Window. /
3618	uint32_t au32Reserved1[16]; /*< 0x218 - Reserved for future. /
3619
3620	/** 64-bit fields. */
3621	RTUINT64U u64AddrIoBitmapA; /*< 0x258 - I/O bitmap A address. /
3622	RTUINT64U u64AddrIoBitmapB; /*< 0x260 - I/O bitmap B address. /
3623	RTUINT64U u64AddrMsrBitmap; /*< 0x268 - MSR bitmap address. /
3624	RTUINT64U u64AddrExitMsrStore; /*< 0x270 - VM-exit MSR-store area address. /
3625	RTUINT64U u64AddrExitMsrLoad; /*< 0x278 - VM-exit MSR-load area address. /
3626	RTUINT64U u64AddrEntryMsrLoad; /*< 0x280 - VM-entry MSR-load area address. /
3627	RTUINT64U u64ExecVmcsPtr; /*< 0x288 - Executive-VMCS pointer. /
3628	RTUINT64U u64AddrPml; /*< 0x290 - PML address. /
3629	RTUINT64U u64TscOffset; /*< 0x298 - TSC offset. /
3630	RTUINT64U u64AddrVirtApic; /*< 0x2a0 - Virtual-APIC address. /
3631	RTUINT64U u64AddrApicAccess; /*< 0x2a8 - APIC-access address. /
3632	RTUINT64U u64AddrPostedIntDesc; /*< 0x2b0 - Posted-interrupt descriptor address. /
3633	RTUINT64U u64VmFuncCtls; /*< 0x2b8 - VM-functions control. /
3634	RTUINT64U u64EptpPtr; /*< 0x2c0 - EPTP pointer. /
3635	RTUINT64U u64EoiExitBitmap0; /*< 0x2c8 - EOI-exit bitmap 0. /
3636	RTUINT64U u64EoiExitBitmap1; /*< 0x2d0 - EOI-exit bitmap 1. /
3637	RTUINT64U u64EoiExitBitmap2; /*< 0x2d8 - EOI-exit bitmap 2. /
3638	RTUINT64U u64EoiExitBitmap3; /*< 0x2e0 - EOI-exit bitmap 3. /
3639	RTUINT64U u64AddrEptpList; /*< 0x2e8 - EPTP-list address. /
3640	RTUINT64U u64AddrVmreadBitmap; /*< 0x2f0 - VMREAD-bitmap address. /
3641	RTUINT64U u64AddrVmwriteBitmap; /*< 0x2f8 - VMWRITE-bitmap address. /
3642	RTUINT64U u64AddrXcptVeInfo; /*< 0x300 - Virtualization-exception information address. /
3643	RTUINT64U u64XssBitmap; /*< 0x308 - XSS-exiting bitmap. /
3644	RTUINT64U u64EnclsBitmap; /*< 0x310 - ENCLS-exiting bitmap address. /
3645	RTUINT64U u64SpptPtr; /*< 0x318 - Sub-page-permission-table pointer. /
3646	RTUINT64U u64TscMultiplier; /*< 0x320 - TSC multiplier. /
3647	RTUINT64U au64Reserved0[15]; /*< 0x328 - Reserved for future. /
3648
3649	/** Natural-width fields. */
3650	RTUINT64U u64Cr0Mask; /*< 0x3a0 - CR0 guest/host Mask. /
3651	RTUINT64U u64Cr4Mask; /*< 0x3a8 - CR4 guest/host Mask. /
3652	RTUINT64U u64Cr0ReadShadow; /*< 0x3b0 - CR0 read shadow. /
3653	RTUINT64U u64Cr4ReadShadow; /*< 0x3b8 - CR4 read shadow. /
3654	RTUINT64U u64Cr3Target0; /*< 0x3c0 - CR3-target value 0. /
3655	RTUINT64U u64Cr3Target1; /*< 0x3c8 - CR3-target value 1. /
3656	RTUINT64U u64Cr3Target2; /*< 0x3d0 - CR3-target value 2. /
3657	RTUINT64U u64Cr3Target3; /*< 0x3d8 - CR3-target value 3. /
3658	RTUINT64U au64Reserved4[32]; /*< 0x3e0 - Reserved for future. /
3659	/** @} */
3660
3661	/** @name Host-state fields.
3662	* @{ */
3663	/** 16-bit fields. */
3664	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3665	RTSEL HostEs; /*< 0x4e0 - Host ES selector. /
3666	RTSEL HostCs; /*< 0x4e2 - Host CS selector. /
3667	RTSEL HostSs; /*< 0x4e4 - Host SS selector. /
3668	RTSEL HostDs; /*< 0x4e6 - Host DS selector. /
3669	RTSEL HostFs; /*< 0x4e8 - Host FS selector. /
3670	RTSEL HostGs; /*< 0x4ea - Host GS selector. /
3671	RTSEL HostTr; /*< 0x4ec - Host TR selector. /
3672	uint16_t au16Reserved2[13]; /*< 0x4ee - Reserved for future. /
3673
3674	/** 32-bit fields. */
3675	uint32_t u32HostSysenterCs; /*< 0x508 - Host SYSENTER CS. /
3676	uint32_t au32Reserved4[11]; /*< 0x50c - Reserved for future. /
3677
3678	/** 64-bit fields. */
3679	RTUINT64U u64HostPatMsr; /*< 0x538 - Host PAT MSR. /
3680	RTUINT64U u64HostEferMsr; /*< 0x540 - Host EFER MSR. /
3681	RTUINT64U u64HostPerfGlobalCtlMsr; /*< 0x548 - Host global performance-control MSR. /
3682	RTUINT64U au64Reserved3[16]; /*< 0x550 - Reserved for future. /
3683
3684	/** Natural-width fields. */
3685	RTUINT64U u64HostCr0; /*< 0x5d0 - Host CR0. /
3686	RTUINT64U u64HostCr3; /*< 0x5d8 - Host CR3. /
3687	RTUINT64U u64HostCr4; /*< 0x5e0 - Host CR4. /
3688	RTUINT64U u64HostFsBase; /*< 0x5e8 - Host FS base. /
3689	RTUINT64U u64HostGsBase; /*< 0x5f0 - Host GS base. /
3690	RTUINT64U u64HostTrBase; /*< 0x5f8 - Host TR base. /
3691	RTUINT64U u64HostGdtrBase; /*< 0x600 - Host GDTR base. /
3692	RTUINT64U u64HostIdtrBase; /*< 0x608 - Host IDTR base. /
3693	RTUINT64U u64HostSysenterEsp; /*< 0x610 - Host SYSENTER ESP base. /
3694	RTUINT64U u64HostSysenterEip; /*< 0x618 - Host SYSENTER ESP base. /
3695	RTUINT64U u64HostRsp; /*< 0x620 - Host RSP. /
3696	RTUINT64U u64HostRip; /*< 0x628 - Host RIP. /
3697	RTUINT64U au64Reserved7[32]; /*< 0x630 - Reserved for future. /
3698	/** @} */
3699
3700	/** @name Guest-state fields.
3701	* @{ */
3702	/** 16-bit fields. */
3703	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3704	RTSEL GuestEs; /*< 0x730 - Guest ES selector. /
3705	RTSEL GuestCs; /*< 0x732 - Guest ES selector. /
3706	RTSEL GuestSs; /*< 0x734 - Guest ES selector. /
3707	RTSEL GuestDs; /*< 0x736 - Guest ES selector. /
3708	RTSEL GuestFs; /*< 0x738 - Guest ES selector. /
3709	RTSEL GuestGs; /*< 0x73a - Guest ES selector. /
3710	RTSEL GuestLdtr; /*< 0x73c - Guest LDTR selector. /
3711	RTSEL GuestTr; /*< 0x73e - Guest TR selector. /
3712	uint16_t u16GuestIntStatus; /*< 0x740 - Guest interrupt status (virtual-interrupt delivery). /
3713	uint16_t u16PmlIndex; /*< 0x742 - PML index. /
3714	uint16_t au16Reserved1[14]; /*< 0x744 - Reserved for future. /
3715
3716	/** 32-bit fields. */
3717	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3718	uint32_t u32GuestEsLimit; /*< 0x760 - Guest ES limit. /
3719	uint32_t u32GuestCsLimit; /*< 0x764 - Guest CS limit. /
3720	uint32_t u32GuestSsLimit; /*< 0x768 - Guest SS limit. /
3721	uint32_t u32GuestDsLimit; /*< 0x76c - Guest DS limit. /
3722	uint32_t u32GuestFsLimit; /*< 0x770 - Guest FS limit. /
3723	uint32_t u32GuestGsLimit; /*< 0x774 - Guest GS limit. /
3724	uint32_t u32GuestLdtrLimit; /*< 0x778 - Guest LDTR limit. /
3725	uint32_t u32GuestTrLimit; /*< 0x77c - Guest TR limit. /
3726	uint32_t u32GuestGdtrLimit; /*< 0x780 - Guest GDTR limit. /
3727	uint32_t u32GuestIdtrLimit; /*< 0x784 - Guest IDTR limit. /
3728	uint32_t u32GuestEsAttr; /*< 0x788 - Guest ES attributes. /
3729	uint32_t u32GuestCsAttr; /*< 0x78c - Guest CS attributes. /
3730	uint32_t u32GuestSsAttr; /*< 0x790 - Guest SS attributes. /
3731	uint32_t u32GuestDsAttr; /*< 0x794 - Guest DS attributes. /
3732	uint32_t u32GuestFsAttr; /*< 0x798 - Guest FS attributes. /
3733	uint32_t u32GuestGsAttr; /*< 0x79c - Guest GS attributes. /
3734	uint32_t u32GuestLdtrAttr; /*< 0x7a0 - Guest LDTR attributes. /
3735	uint32_t u32GuestTrAttr; /*< 0x7a4 - Guest TR attributes. /
3736	uint32_t u32GuestIntrState; /*< 0x7a8 - Guest interruptibility state. /
3737	uint32_t u32GuestActivityState; /*< 0x7ac - Guest activity state. /
3738	uint32_t u32GuestSmBase; /*< 0x7b0 - Guest SMBASE. /
3739	uint32_t u32GuestSysenterCS; /*< 0x7b4 - Guest SYSENTER CS. /
3740	uint32_t u32PreemptTimer; /*< 0x7b8 - Preemption timer value. /
3741	uint32_t au32Reserved3[11]; /*< 0x7bc - Reserved for future. /
3742
3743	/** 64-bit fields. */
3744	RTUINT64U u64VmcsLinkPtr; /*< 0x7e8 - VMCS link pointer. /
3745	RTUINT64U u64GuestDebugCtlMsr; /*< 0x7f0 - Guest debug-control MSR. /
3746	RTUINT64U u64GuestPatMsr; /*< 0x7f8 - Guest PAT MSR. /
3747	RTUINT64U u64GuestEferMsr; /*< 0x800 - Guest EFER MSR. /
3748	RTUINT64U u64GuestPerfGlobalCtlMsr; /*< 0x808 - Guest global performance-control MSR. /
3749	RTUINT64U u64GuestPdpte0; /*< 0x810 - Guest PDPTE 0. /
3750	RTUINT64U u64GuestPdpte1; /*< 0x818 - Guest PDPTE 0. /
3751	RTUINT64U u64GuestPdpte2; /*< 0x820 - Guest PDPTE 1. /
3752	RTUINT64U u64GuestPdpte3; /*< 0x828 - Guest PDPTE 2. /
3753	RTUINT64U u64GuestBndcfgsMsr; /*< 0x830 - Guest Bounds config MPX MSR (Intel Memory Protection Extensions). /
3754	RTUINT64U u64GuestRtitCtlMsr; /*< 0x838 - Guest RTIT control MSR (Intel Real Time Instruction Trace). /
3755	RTUINT64U au64Reserved2[32]; /*< 0x840 - Reserved for future. /
3756
3757	/** Natural-width fields. */
3758	RTUINT64U u64GuestCr0; /*< 0x940 - Guest CR0. /
3759	RTUINT64U u64GuestCr3; /*< 0x948 - Guest CR3. /
3760	RTUINT64U u64GuestCr4; /*< 0x950 - Guest CR4. /
3761	RTUINT64U u64GuestEsBase; /*< 0x958 - Guest ES base. /
3762	RTUINT64U u64GuestCsBase; /*< 0x960 - Guest CS base. /
3763	RTUINT64U u64GuestSsBase; /*< 0x968 - Guest SS base. /
3764	RTUINT64U u64GuestDsBase; /*< 0x970 - Guest DS base. /
3765	RTUINT64U u64GuestFsBase; /*< 0x978 - Guest FS base. /
3766	RTUINT64U u64GuestGsBase; /*< 0x980 - Guest GS base. /
3767	RTUINT64U u64GuestLdtrBase; /*< 0x988 - Guest LDTR base. /
3768	RTUINT64U u64GuestTrBase; /*< 0x990 - Guest TR base. /
3769	RTUINT64U u64GuestGdtrBase; /*< 0x998 - Guest GDTR base. /
3770	RTUINT64U u64GuestIdtrBase; /*< 0x9a0 - Guest IDTR base. /
3771	RTUINT64U u64GuestDr7; /*< 0x9a8 - Guest DR7. /
3772	RTUINT64U u64GuestRsp; /*< 0x9b0 - Guest RSP. /
3773	RTUINT64U u64GuestRip; /*< 0x9b8 - Guest RIP. /
3774	RTUINT64U u64GuestRFlags; /*< 0x9c0 - Guest RFLAGS. /
3775	RTUINT64U u64GuestPendingDbgXcpts; /*< 0x9c8 - Guest pending debug exceptions. /
3776	RTUINT64U u64GuestSysenterEsp; /*< 0x9d0 - Guest SYSENTER ESP. /
3777	RTUINT64U u64GuestSysenterEip; /*< 0x9d8 - Guest SYSENTER EIP. /
3778	RTUINT64U au64Reserved6[32]; /*< 0x9e0 - Reserved for future. /
3779	/** @} */
3780
3781	/** 0xae0 - Padding / reserved for future use. */
3782	uint8_t abPadding[X86_PAGE_4K_SIZE - 0xae0];
3783	} VMXVVMCS;
3784	#pragma pack()
3785	/** Pointer to the VMXVVMCS struct. */
3786	typedef VMXVVMCS *PVMXVVMCS;
3787	/** Pointer to a const VMXVVMCS struct. */
3788	typedef const VMXVVMCS *PCVMXVVMCS;
3789	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
3790	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
3791	AssertCompileMemberOffset(VMXVVMCS, enmVmxAbort, 0x004);
3792	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
3793	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x058);
3794	AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x0b8);
3795	AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x100);
3796	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x1b0);
3797	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x1d0);
3798	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x258);
3799	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x3a0);
3800	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x4e0);
3801	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x508);
3802	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x538);
3803	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x5d0);
3804	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x730);
3805	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x760);
3806	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x7e8);
3807	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x940);
3808
3809	/**
3810	* Virtual VMX-instruction and VM-exit diagnostics.
3811	*
3812	* These are not the same as VM instruction errors that are enumerated in the Intel
3813	* spec. These are purely internal, fine-grained definitions used for diagnostic
3814	* purposes and are not reported to guest software under the VM-instruction error
3815	* field in its VMCS.
3816	*
3817	* @note Members of this enum are used as array indices, so no gaps are allowed.
3818	* Please update g_apszVmxVDiagDesc when you add new fields to this enum.
3819	*/
3820	typedef enum
3821	{
3822	/* Internal processing errors. */
3823	kVmxVDiag_None = 0,
3824	kVmxVDiag_Ipe_1,
3825	kVmxVDiag_Ipe_2,
3826	kVmxVDiag_Ipe_3,
3827	kVmxVDiag_Ipe_4,
3828	kVmxVDiag_Ipe_5,
3829	kVmxVDiag_Ipe_6,
3830	kVmxVDiag_Ipe_7,
3831	kVmxVDiag_Ipe_8,
3832	kVmxVDiag_Ipe_9,
3833	kVmxVDiag_Ipe_10,
3834	kVmxVDiag_Ipe_11,
3835	kVmxVDiag_Ipe_12,
3836	kVmxVDiag_Ipe_13,
3837	kVmxVDiag_Ipe_14,
3838	kVmxVDiag_Ipe_15,
3839	kVmxVDiag_Ipe_16,
3840	/* VMXON. */
3841	kVmxVDiag_Vmxon_A20M,
3842	kVmxVDiag_Vmxon_Cpl,
3843	kVmxVDiag_Vmxon_Cr0Fixed0,
3844	kVmxVDiag_Vmxon_Cr0Fixed1,
3845	kVmxVDiag_Vmxon_Cr4Fixed0,
3846	kVmxVDiag_Vmxon_Cr4Fixed1,
3847	kVmxVDiag_Vmxon_Intercept,
3848	kVmxVDiag_Vmxon_LongModeCS,
3849	kVmxVDiag_Vmxon_MsrFeatCtl,
3850	kVmxVDiag_Vmxon_PtrAbnormal,
3851	kVmxVDiag_Vmxon_PtrAlign,
3852	kVmxVDiag_Vmxon_PtrMap,
3853	kVmxVDiag_Vmxon_PtrReadPhys,
3854	kVmxVDiag_Vmxon_PtrWidth,
3855	kVmxVDiag_Vmxon_RealOrV86Mode,
3856	kVmxVDiag_Vmxon_ShadowVmcs,
3857	kVmxVDiag_Vmxon_VmxAlreadyRoot,
3858	kVmxVDiag_Vmxon_Vmxe,
3859	kVmxVDiag_Vmxon_VmcsRevId,
3860	kVmxVDiag_Vmxon_VmxRootCpl,
3861	/* VMXOFF. */
3862	kVmxVDiag_Vmxoff_Cpl,
3863	kVmxVDiag_Vmxoff_Intercept,
3864	kVmxVDiag_Vmxoff_LongModeCS,
3865	kVmxVDiag_Vmxoff_RealOrV86Mode,
3866	kVmxVDiag_Vmxoff_Vmxe,
3867	kVmxVDiag_Vmxoff_VmxRoot,
3868	/* VMPTRLD. */
3869	kVmxVDiag_Vmptrld_Cpl,
3870	kVmxVDiag_Vmptrld_LongModeCS,
3871	kVmxVDiag_Vmptrld_PtrAbnormal,
3872	kVmxVDiag_Vmptrld_PtrAlign,
3873	kVmxVDiag_Vmptrld_PtrMap,
3874	kVmxVDiag_Vmptrld_PtrReadPhys,
3875	kVmxVDiag_Vmptrld_PtrVmxon,
3876	kVmxVDiag_Vmptrld_PtrWidth,
3877	kVmxVDiag_Vmptrld_RealOrV86Mode,
3878	kVmxVDiag_Vmptrld_RevPtrReadPhys,
3879	kVmxVDiag_Vmptrld_ShadowVmcs,
3880	kVmxVDiag_Vmptrld_VmcsRevId,
3881	kVmxVDiag_Vmptrld_VmxRoot,
3882	/* VMPTRST. */
3883	kVmxVDiag_Vmptrst_Cpl,
3884	kVmxVDiag_Vmptrst_LongModeCS,
3885	kVmxVDiag_Vmptrst_PtrMap,
3886	kVmxVDiag_Vmptrst_RealOrV86Mode,
3887	kVmxVDiag_Vmptrst_VmxRoot,
3888	/* VMCLEAR. */
3889	kVmxVDiag_Vmclear_Cpl,
3890	kVmxVDiag_Vmclear_LongModeCS,
3891	kVmxVDiag_Vmclear_PtrAbnormal,
3892	kVmxVDiag_Vmclear_PtrAlign,
3893	kVmxVDiag_Vmclear_PtrMap,
3894	kVmxVDiag_Vmclear_PtrReadPhys,
3895	kVmxVDiag_Vmclear_PtrVmxon,
3896	kVmxVDiag_Vmclear_PtrWidth,
3897	kVmxVDiag_Vmclear_RealOrV86Mode,
3898	kVmxVDiag_Vmclear_VmxRoot,
3899	/* VMWRITE. */
3900	kVmxVDiag_Vmwrite_Cpl,
3901	kVmxVDiag_Vmwrite_FieldInvalid,
3902	kVmxVDiag_Vmwrite_FieldRo,
3903	kVmxVDiag_Vmwrite_LinkPtrInvalid,
3904	kVmxVDiag_Vmwrite_LongModeCS,
3905	kVmxVDiag_Vmwrite_PtrInvalid,
3906	kVmxVDiag_Vmwrite_PtrMap,
3907	kVmxVDiag_Vmwrite_RealOrV86Mode,
3908	kVmxVDiag_Vmwrite_VmxRoot,
3909	/* VMREAD. */
3910	kVmxVDiag_Vmread_Cpl,
3911	kVmxVDiag_Vmread_FieldInvalid,
3912	kVmxVDiag_Vmread_LinkPtrInvalid,
3913	kVmxVDiag_Vmread_LongModeCS,
3914	kVmxVDiag_Vmread_PtrInvalid,
3915	kVmxVDiag_Vmread_PtrMap,
3916	kVmxVDiag_Vmread_RealOrV86Mode,
3917	kVmxVDiag_Vmread_VmxRoot,
3918	/* INVVPID. */
3919	kVmxVDiag_Invvpid_Cpl,
3920	kVmxVDiag_Invvpid_DescRsvd,
3921	kVmxVDiag_Invvpid_LongModeCS,
3922	kVmxVDiag_Invvpid_RealOrV86Mode,
3923	kVmxVDiag_Invvpid_TypeInvalid,
3924	kVmxVDiag_Invvpid_Type0InvalidAddr,
3925	kVmxVDiag_Invvpid_Type0InvalidVpid,
3926	kVmxVDiag_Invvpid_Type1InvalidVpid,
3927	kVmxVDiag_Invvpid_Type3InvalidVpid,
3928	kVmxVDiag_Invvpid_VmxRoot,
3929	/* VMLAUNCH/VMRESUME. */
3930	kVmxVDiag_Vmentry_AddrApicAccess,
3931	kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
3932	kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
3933	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
3934	kVmxVDiag_Vmentry_AddrExitMsrLoad,
3935	kVmxVDiag_Vmentry_AddrExitMsrStore,
3936	kVmxVDiag_Vmentry_AddrIoBitmapA,
3937	kVmxVDiag_Vmentry_AddrIoBitmapB,
3938	kVmxVDiag_Vmentry_AddrMsrBitmap,
3939	kVmxVDiag_Vmentry_AddrVirtApicPage,
3940	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
3941	kVmxVDiag_Vmentry_AddrVmreadBitmap,
3942	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
3943	kVmxVDiag_Vmentry_ApicRegVirt,
3944	kVmxVDiag_Vmentry_BlocKMovSS,
3945	kVmxVDiag_Vmentry_Cpl,
3946	kVmxVDiag_Vmentry_Cr3TargetCount,
3947	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
3948	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
3949	kVmxVDiag_Vmentry_EntryInstrLen,
3950	kVmxVDiag_Vmentry_EntryInstrLenZero,
3951	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
3952	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
3953	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
3954	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
3955	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
3956	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
3957	kVmxVDiag_Vmentry_GuestActStateHlt,
3958	kVmxVDiag_Vmentry_GuestActStateRsvd,
3959	kVmxVDiag_Vmentry_GuestActStateShutdown,
3960	kVmxVDiag_Vmentry_GuestActStateSsDpl,
3961	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
3962	kVmxVDiag_Vmentry_GuestCr0Fixed0,
3963	kVmxVDiag_Vmentry_GuestCr0Fixed1,
3964	kVmxVDiag_Vmentry_GuestCr0PgPe,
3965	kVmxVDiag_Vmentry_GuestCr3,
3966	kVmxVDiag_Vmentry_GuestCr4Fixed0,
3967	kVmxVDiag_Vmentry_GuestCr4Fixed1,
3968	kVmxVDiag_Vmentry_GuestDebugCtl,
3969	kVmxVDiag_Vmentry_GuestDr7,
3970	kVmxVDiag_Vmentry_GuestEferMsr,
3971	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
3972	kVmxVDiag_Vmentry_GuestGdtrBase,
3973	kVmxVDiag_Vmentry_GuestGdtrLimit,
3974	kVmxVDiag_Vmentry_GuestIdtrBase,
3975	kVmxVDiag_Vmentry_GuestIdtrLimit,
3976	kVmxVDiag_Vmentry_GuestIntStateEnclave,
3977	kVmxVDiag_Vmentry_GuestIntStateExtInt,
3978	kVmxVDiag_Vmentry_GuestIntStateNmi,
3979	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
3980	kVmxVDiag_Vmentry_GuestIntStateRsvd,
3981	kVmxVDiag_Vmentry_GuestIntStateSmi,
3982	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
3983	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
3984	kVmxVDiag_Vmentry_GuestPae,
3985	kVmxVDiag_Vmentry_GuestPatMsr,
3986	kVmxVDiag_Vmentry_GuestPcide,
3987	kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys,
3988	kVmxVDiag_Vmentry_GuestPdpte0Rsvd,
3989	kVmxVDiag_Vmentry_GuestPdpte1Rsvd,
3990	kVmxVDiag_Vmentry_GuestPdpte2Rsvd,
3991	kVmxVDiag_Vmentry_GuestPdpte3Rsvd,
3992	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
3993	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
3994	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
3995	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
3996	kVmxVDiag_Vmentry_GuestRip,
3997	kVmxVDiag_Vmentry_GuestRipRsvd,
3998	kVmxVDiag_Vmentry_GuestRFlagsIf,
3999	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
4000	kVmxVDiag_Vmentry_GuestRFlagsVm,
4001	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
4002	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
4003	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
4004	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
4005	kVmxVDiag_Vmentry_GuestSegAttrCsType,
4006	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
4007	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
4008	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
4009	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
4010	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
4011	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
4012	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
4013	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
4014	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
4015	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
4016	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
4017	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
4018	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
4019	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
4020	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
4021	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
4022	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
4023	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
4024	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
4025	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
4026	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
4027	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
4028	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
4029	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
4030	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
4031	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
4032	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
4033	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
4034	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
4035	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
4036	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
4037	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
4038	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
4039	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
4040	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
4041	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
4042	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
4043	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
4044	kVmxVDiag_Vmentry_GuestSegAttrSsType,
4045	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
4046	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
4047	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
4048	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
4049	kVmxVDiag_Vmentry_GuestSegAttrTrType,
4050	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
4051	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
4052	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
4053	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
4054	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
4055	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
4056	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
4057	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
4058	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
4059	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
4060	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
4061	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
4062	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
4063	kVmxVDiag_Vmentry_GuestSegBaseCs,
4064	kVmxVDiag_Vmentry_GuestSegBaseDs,
4065	kVmxVDiag_Vmentry_GuestSegBaseEs,
4066	kVmxVDiag_Vmentry_GuestSegBaseFs,
4067	kVmxVDiag_Vmentry_GuestSegBaseGs,
4068	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
4069	kVmxVDiag_Vmentry_GuestSegBaseSs,
4070	kVmxVDiag_Vmentry_GuestSegBaseTr,
4071	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
4072	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
4073	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
4074	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
4075	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
4076	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
4077	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
4078	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
4079	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
4080	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
4081	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
4082	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
4083	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
4084	kVmxVDiag_Vmentry_GuestSegSelLdtr,
4085	kVmxVDiag_Vmentry_GuestSegSelTr,
4086	kVmxVDiag_Vmentry_GuestSysenterEspEip,
4087	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
4088	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
4089	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
4090	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
4091	kVmxVDiag_Vmentry_HostCr0Fixed0,
4092	kVmxVDiag_Vmentry_HostCr0Fixed1,
4093	kVmxVDiag_Vmentry_HostCr3,
4094	kVmxVDiag_Vmentry_HostCr4Fixed0,
4095	kVmxVDiag_Vmentry_HostCr4Fixed1,
4096	kVmxVDiag_Vmentry_HostCr4Pae,
4097	kVmxVDiag_Vmentry_HostCr4Pcide,
4098	kVmxVDiag_Vmentry_HostCsTr,
4099	kVmxVDiag_Vmentry_HostEferMsr,
4100	kVmxVDiag_Vmentry_HostEferMsrRsvd,
4101	kVmxVDiag_Vmentry_HostGuestLongMode,
4102	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4103	kVmxVDiag_Vmentry_HostLongMode,
4104	kVmxVDiag_Vmentry_HostPatMsr,
4105	kVmxVDiag_Vmentry_HostRip,
4106	kVmxVDiag_Vmentry_HostRipRsvd,
4107	kVmxVDiag_Vmentry_HostSel,
4108	kVmxVDiag_Vmentry_HostSegBase,
4109	kVmxVDiag_Vmentry_HostSs,
4110	kVmxVDiag_Vmentry_HostSysenterEspEip,
4111	kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys,
4112	kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys,
4113	kVmxVDiag_Vmentry_LongModeCS,
4114	kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4115	kVmxVDiag_Vmentry_MsrLoad,
4116	kVmxVDiag_Vmentry_MsrLoadCount,
4117	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4118	kVmxVDiag_Vmentry_MsrLoadRing3,
4119	kVmxVDiag_Vmentry_MsrLoadRsvd,
4120	kVmxVDiag_Vmentry_NmiWindowExit,
4121	kVmxVDiag_Vmentry_PinCtlsAllowed1,
4122	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4123	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4124	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4125	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4126	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4127	kVmxVDiag_Vmentry_PtrInvalid,
4128	kVmxVDiag_Vmentry_PtrShadowVmcs,
4129	kVmxVDiag_Vmentry_RealOrV86Mode,
4130	kVmxVDiag_Vmentry_SavePreemptTimer,
4131	kVmxVDiag_Vmentry_TprThresholdRsvd,
4132	kVmxVDiag_Vmentry_TprThresholdVTpr,
4133	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4134	kVmxVDiag_Vmentry_VirtIntDelivery,
4135	kVmxVDiag_Vmentry_VirtNmi,
4136	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4137	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4138	kVmxVDiag_Vmentry_VmcsClear,
4139	kVmxVDiag_Vmentry_VmcsLaunch,
4140	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4141	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4142	kVmxVDiag_Vmentry_VmxRoot,
4143	kVmxVDiag_Vmentry_Vpid,
4144	kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys,
4145	kVmxVDiag_Vmexit_HostPdpte0Rsvd,
4146	kVmxVDiag_Vmexit_HostPdpte1Rsvd,
4147	kVmxVDiag_Vmexit_HostPdpte2Rsvd,
4148	kVmxVDiag_Vmexit_HostPdpte3Rsvd,
4149	kVmxVDiag_Vmexit_MsrLoad,
4150	kVmxVDiag_Vmexit_MsrLoadCount,
4151	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4152	kVmxVDiag_Vmexit_MsrLoadRing3,
4153	kVmxVDiag_Vmexit_MsrLoadRsvd,
4154	kVmxVDiag_Vmexit_MsrStore,
4155	kVmxVDiag_Vmexit_MsrStoreCount,
4156	kVmxVDiag_Vmexit_MsrStorePtrReadPhys,
4157	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4158	kVmxVDiag_Vmexit_MsrStoreRing3,
4159	kVmxVDiag_Vmexit_MsrStoreRsvd,
4160	kVmxVDiag_Vmexit_VirtApicPagePtrWritePhys,
4161	/* Last member for determining array index limit. */
4162	kVmxVDiag_End
4163	} VMXVDIAG;
4164	AssertCompileSize(VMXVDIAG, 4);
4165
4166	/** @} */
4167
4168	/** @} */
4169
4170	#endif /* !VBOX_INCLUDED_vmm_hm_vmx_h */
4171

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 82817

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