hm_vmx.h@ 90932

Last change on this file since 90932 was 90932, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Renamed VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_XXX to VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_XXX and fixed comment typo. No functional change.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 216.5 KB

Line
1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_hm_vmx_h
27	#define VBOX_INCLUDED_vmm_hm_vmx_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <iprt/x86.h>
34	#include <iprt/assertcompile.h>
35
36
37	/** @defgroup grp_hm_vmx VMX Types and Definitions
38	* @ingroup grp_hm
39	* @{
40	*/
41
42	/** @name Host-state MSR lazy-restoration flags.
43	* @{
44	*/
45	/** The host MSRs have been saved. */
46	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
47	/** The guest MSRs are loaded and in effect. */
48	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
49	/** @} */
50
51	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
52	* UFC = Unsupported Feature Combination.
53	* @{
54	*/
55	/** Unsupported pin-based VM-execution controls combo. */
56	#define VMX_UFC_CTRL_PIN_EXEC 1
57	/** Unsupported processor-based VM-execution controls combo. */
58	#define VMX_UFC_CTRL_PROC_EXEC 2
59	/** Unsupported move debug register VM-exit combo. */
60	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
61	/** Unsupported VM-entry controls combo. */
62	#define VMX_UFC_CTRL_ENTRY 4
63	/** Unsupported VM-exit controls combo. */
64	#define VMX_UFC_CTRL_EXIT 5
65	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
66	* for storing host MSRs. */
67	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
68	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
69	* for storing guest MSRs. */
70	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
71	/** Invalid VMCS size. */
72	#define VMX_UFC_INVALID_VMCS_SIZE 8
73	/** Unsupported secondary processor-based VM-execution controls combo. */
74	#define VMX_UFC_CTRL_PROC_EXEC2 9
75	/** Invalid unrestricted-guest execution controls combo. */
76	#define VMX_UFC_INVALID_UX_COMBO 10
77	/** EPT flush type not supported. */
78	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
79	/** EPT paging structure memory type is not write-back. */
80	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
81	/** EPT requires INVEPT instr. support but it's not available. */
82	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
83	/** EPT requires page-walk length of 4. */
84	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
85	/** VMX VMWRITE all feature exposed to the guest but not supported on host. */
86	#define VMX_UFC_GST_HOST_VMWRITE_ALL 15
87	/** LBR stack size cannot be determined for the current CPU. */
88	#define VMX_UFC_LBR_STACK_SIZE_UNKNOWN 16
89	/** LBR stack size of the CPU exceeds our buffer size. */
90	#define VMX_UFC_LBR_STACK_SIZE_OVERFLOW 17
91	/** @} */
92
93	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
94	* VCI = VMCS-field Cache Invalid.
95	* @{
96	*/
97	/** Cache of VM-entry controls invalid. */
98	#define VMX_VCI_CTRL_ENTRY 300
99	/** Cache of VM-exit controls invalid. */
100	#define VMX_VCI_CTRL_EXIT 301
101	/** Cache of pin-based VM-execution controls invalid. */
102	#define VMX_VCI_CTRL_PIN_EXEC 302
103	/** Cache of processor-based VM-execution controls invalid. */
104	#define VMX_VCI_CTRL_PROC_EXEC 303
105	/** Cache of secondary processor-based VM-execution controls invalid. */
106	#define VMX_VCI_CTRL_PROC_EXEC2 304
107	/** Cache of exception bitmap invalid. */
108	#define VMX_VCI_CTRL_XCPT_BITMAP 305
109	/** Cache of TSC offset invalid. */
110	#define VMX_VCI_CTRL_TSC_OFFSET 306
111	/** @} */
112
113	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
114	* IGS = Invalid Guest State.
115	* @{
116	*/
117	/** An error occurred while checking invalid-guest-state. */
118	#define VMX_IGS_ERROR 500
119	/** The invalid guest-state checks did not find any reason why. */
120	#define VMX_IGS_REASON_NOT_FOUND 501
121	/** CR0 fixed1 bits invalid. */
122	#define VMX_IGS_CR0_FIXED1 502
123	/** CR0 fixed0 bits invalid. */
124	#define VMX_IGS_CR0_FIXED0 503
125	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
126	#define VMX_IGS_CR0_PG_PE_COMBO 504
127	/** CR4 fixed1 bits invalid. */
128	#define VMX_IGS_CR4_FIXED1 505
129	/** CR4 fixed0 bits invalid. */
130	#define VMX_IGS_CR4_FIXED0 506
131	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
132	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
133	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
134	/** CR0.PG not set for long-mode when not using unrestricted guest. */
135	#define VMX_IGS_CR0_PG_LONGMODE 508
136	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
137	#define VMX_IGS_CR4_PAE_LONGMODE 509
138	/** CR4.PCIDE set for 32-bit guest. */
139	#define VMX_IGS_CR4_PCIDE 510
140	/** VMCS' DR7 reserved bits not set to 0. */
141	#define VMX_IGS_DR7_RESERVED 511
142	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
143	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
144	/** VMCS' EFER MSR reserved bits not set to 0. */
145	#define VMX_IGS_EFER_MSR_RESERVED 513
146	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
147	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
148	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
149	* without unrestricted guest. */
150	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
151	/** CS.Attr.P bit invalid. */
152	#define VMX_IGS_CS_ATTR_P_INVALID 516
153	/** CS.Attr reserved bits not set to 0. */
154	#define VMX_IGS_CS_ATTR_RESERVED 517
155	/** CS.Attr.G bit invalid. */
156	#define VMX_IGS_CS_ATTR_G_INVALID 518
157	/** CS is unusable. */
158	#define VMX_IGS_CS_ATTR_UNUSABLE 519
159	/** CS and SS DPL unequal. */
160	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
161	/** CS and SS DPL mismatch. */
162	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
163	/** CS Attr.Type invalid. */
164	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
165	/** CS and SS RPL unequal. */
166	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
167	/** SS.Attr.DPL and SS RPL unequal. */
168	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
169	/** SS.Attr.DPL invalid for segment type. */
170	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
171	/** SS.Attr.Type invalid. */
172	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
173	/** SS.Attr.P bit invalid. */
174	#define VMX_IGS_SS_ATTR_P_INVALID 527
175	/** SS.Attr reserved bits not set to 0. */
176	#define VMX_IGS_SS_ATTR_RESERVED 528
177	/** SS.Attr.G bit invalid. */
178	#define VMX_IGS_SS_ATTR_G_INVALID 529
179	/** DS.Attr.A bit invalid. */
180	#define VMX_IGS_DS_ATTR_A_INVALID 530
181	/** DS.Attr.P bit invalid. */
182	#define VMX_IGS_DS_ATTR_P_INVALID 531
183	/** DS.Attr.DPL and DS RPL unequal. */
184	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
185	/** DS.Attr reserved bits not set to 0. */
186	#define VMX_IGS_DS_ATTR_RESERVED 533
187	/** DS.Attr.G bit invalid. */
188	#define VMX_IGS_DS_ATTR_G_INVALID 534
189	/** DS.Attr.Type invalid. */
190	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
191	/** ES.Attr.A bit invalid. */
192	#define VMX_IGS_ES_ATTR_A_INVALID 536
193	/** ES.Attr.P bit invalid. */
194	#define VMX_IGS_ES_ATTR_P_INVALID 537
195	/** ES.Attr.DPL and DS RPL unequal. */
196	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
197	/** ES.Attr reserved bits not set to 0. */
198	#define VMX_IGS_ES_ATTR_RESERVED 539
199	/** ES.Attr.G bit invalid. */
200	#define VMX_IGS_ES_ATTR_G_INVALID 540
201	/** ES.Attr.Type invalid. */
202	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
203	/** FS.Attr.A bit invalid. */
204	#define VMX_IGS_FS_ATTR_A_INVALID 542
205	/** FS.Attr.P bit invalid. */
206	#define VMX_IGS_FS_ATTR_P_INVALID 543
207	/** FS.Attr.DPL and DS RPL unequal. */
208	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
209	/** FS.Attr reserved bits not set to 0. */
210	#define VMX_IGS_FS_ATTR_RESERVED 545
211	/** FS.Attr.G bit invalid. */
212	#define VMX_IGS_FS_ATTR_G_INVALID 546
213	/** FS.Attr.Type invalid. */
214	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
215	/** GS.Attr.A bit invalid. */
216	#define VMX_IGS_GS_ATTR_A_INVALID 548
217	/** GS.Attr.P bit invalid. */
218	#define VMX_IGS_GS_ATTR_P_INVALID 549
219	/** GS.Attr.DPL and DS RPL unequal. */
220	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
221	/** GS.Attr reserved bits not set to 0. */
222	#define VMX_IGS_GS_ATTR_RESERVED 551
223	/** GS.Attr.G bit invalid. */
224	#define VMX_IGS_GS_ATTR_G_INVALID 552
225	/** GS.Attr.Type invalid. */
226	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
227	/** V86 mode CS.Base invalid. */
228	#define VMX_IGS_V86_CS_BASE_INVALID 554
229	/** V86 mode CS.Limit invalid. */
230	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
231	/** V86 mode CS.Attr invalid. */
232	#define VMX_IGS_V86_CS_ATTR_INVALID 556
233	/** V86 mode SS.Base invalid. */
234	#define VMX_IGS_V86_SS_BASE_INVALID 557
235	/** V86 mode SS.Limit invalid. */
236	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
237	/** V86 mode SS.Attr invalid. */
238	#define VMX_IGS_V86_SS_ATTR_INVALID 559
239	/** V86 mode DS.Base invalid. */
240	#define VMX_IGS_V86_DS_BASE_INVALID 560
241	/** V86 mode DS.Limit invalid. */
242	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
243	/** V86 mode DS.Attr invalid. */
244	#define VMX_IGS_V86_DS_ATTR_INVALID 562
245	/** V86 mode ES.Base invalid. */
246	#define VMX_IGS_V86_ES_BASE_INVALID 563
247	/** V86 mode ES.Limit invalid. */
248	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
249	/** V86 mode ES.Attr invalid. */
250	#define VMX_IGS_V86_ES_ATTR_INVALID 565
251	/** V86 mode FS.Base invalid. */
252	#define VMX_IGS_V86_FS_BASE_INVALID 566
253	/** V86 mode FS.Limit invalid. */
254	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
255	/** V86 mode FS.Attr invalid. */
256	#define VMX_IGS_V86_FS_ATTR_INVALID 568
257	/** V86 mode GS.Base invalid. */
258	#define VMX_IGS_V86_GS_BASE_INVALID 569
259	/** V86 mode GS.Limit invalid. */
260	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
261	/** V86 mode GS.Attr invalid. */
262	#define VMX_IGS_V86_GS_ATTR_INVALID 571
263	/** Longmode CS.Base invalid. */
264	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
265	/** Longmode SS.Base invalid. */
266	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
267	/** Longmode DS.Base invalid. */
268	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
269	/** Longmode ES.Base invalid. */
270	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
271	/** SYSENTER ESP is not canonical. */
272	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
273	/** SYSENTER EIP is not canonical. */
274	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
275	/** PAT MSR invalid. */
276	#define VMX_IGS_PAT_MSR_INVALID 578
277	/** PAT MSR reserved bits not set to 0. */
278	#define VMX_IGS_PAT_MSR_RESERVED 579
279	/** GDTR.Base is not canonical. */
280	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
281	/** IDTR.Base is not canonical. */
282	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
283	/** GDTR.Limit invalid. */
284	#define VMX_IGS_GDTR_LIMIT_INVALID 582
285	/** IDTR.Limit invalid. */
286	#define VMX_IGS_IDTR_LIMIT_INVALID 583
287	/** Longmode RIP is invalid. */
288	#define VMX_IGS_LONGMODE_RIP_INVALID 584
289	/** RFLAGS reserved bits not set to 0. */
290	#define VMX_IGS_RFLAGS_RESERVED 585
291	/** RFLAGS RA1 reserved bits not set to 1. */
292	#define VMX_IGS_RFLAGS_RESERVED1 586
293	/** RFLAGS.VM (V86 mode) invalid. */
294	#define VMX_IGS_RFLAGS_VM_INVALID 587
295	/** RFLAGS.IF invalid. */
296	#define VMX_IGS_RFLAGS_IF_INVALID 588
297	/** Activity state invalid. */
298	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
299	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
300	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
301	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
302	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
303	/** Activity state SIPI WAIT invalid. */
304	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
305	/** Interruptibility state reserved bits not set to 0. */
306	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
307	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
308	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
309	/** Interruptibility state block-by-STI invalid for EFLAGS. */
310	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
311	/** Interruptibility state invalid while trying to deliver external
312	* interrupt. */
313	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
314	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
315	* NMI. */
316	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
317	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
318	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
319	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
320	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
321	/** Interruptibility state block-by-STI (maybe) invalid when trying to
322	* deliver an NMI. */
323	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
324	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
325	* active. */
326	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
327	/** Pending debug exceptions reserved bits not set to 0. */
328	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
329	/** Longmode pending debug exceptions reserved bits not set to 0. */
330	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
331	/** Pending debug exceptions.BS bit is not set when it should be. */
332	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
333	/** Pending debug exceptions.BS bit is not clear when it should be. */
334	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
335	/** VMCS link pointer reserved bits not set to 0. */
336	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
337	/** TR cannot index into LDT, TI bit MBZ. */
338	#define VMX_IGS_TR_TI_INVALID 607
339	/** LDTR cannot index into LDT. TI bit MBZ. */
340	#define VMX_IGS_LDTR_TI_INVALID 608
341	/** TR.Base is not canonical. */
342	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
343	/** FS.Base is not canonical. */
344	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
345	/** GS.Base is not canonical. */
346	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
347	/** LDTR.Base is not canonical. */
348	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
349	/** TR is unusable. */
350	#define VMX_IGS_TR_ATTR_UNUSABLE 613
351	/** TR.Attr.S bit invalid. */
352	#define VMX_IGS_TR_ATTR_S_INVALID 614
353	/** TR is not present. */
354	#define VMX_IGS_TR_ATTR_P_INVALID 615
355	/** TR.Attr reserved bits not set to 0. */
356	#define VMX_IGS_TR_ATTR_RESERVED 616
357	/** TR.Attr.G bit invalid. */
358	#define VMX_IGS_TR_ATTR_G_INVALID 617
359	/** Longmode TR.Attr.Type invalid. */
360	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
361	/** TR.Attr.Type invalid. */
362	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
363	/** CS.Attr.S invalid. */
364	#define VMX_IGS_CS_ATTR_S_INVALID 620
365	/** CS.Attr.DPL invalid. */
366	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
367	/** PAE PDPTE reserved bits not set to 0. */
368	#define VMX_IGS_PAE_PDPTE_RESERVED 623
369	/** VMCS link pointer does not point to a shadow VMCS. */
370	#define VMX_IGS_VMCS_LINK_PTR_NOT_SHADOW 624
371	/** VMCS link pointer to a shadow VMCS with invalid VMCS revision identifer. */
372	#define VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID 625
373	/** @} */
374
375	/** @name VMX VMCS-Read cache indices.
376	* @{
377	*/
378	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
379	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
380	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
381	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
382	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
383	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
384	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
385	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
386	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
387	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
388	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
389	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
390	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
391	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
392	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
393	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
394	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
395	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
396	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
397	/** @} */
398
399	/** @name VMX Extended Page Tables (EPT) Common Bits
400	* @{ */
401	/** Bit 0 - Readable (we often think of it as present). */
402	#define EPT_E_BIT_READ 0
403	#define EPT_E_READ RT_BIT_64(EPT_E_BIT_READ) /*< @see EPT_E_BIT_READ /
404	/** Bit 1 - Writable. */
405	#define EPT_E_BIT_WRITE 1
406	#define EPT_E_WRITE RT_BIT_64(EPT_E_BIT_WRITE) /*< @see EPT_E_BIT_WRITE /
407	/** Bit 2 - Executable.
408	* @note This controls supervisor instruction fetching if mode-based
409	* execution control is enabled. */
410	#define EPT_E_BIT_EXECUTE 2
411	#define EPT_E_EXECUTE RT_BIT_64(EPT_E_BIT_EXECUTE) /*< @see EPT_E_BIT_EXECUTE /
412	/** Bits 3-5 - Memory type mask (leaf only, MBZ).
413	* The memory type is only applicable for leaf entries and MBZ for
414	* non-leaf (causes miconfiguration exit). */
415	#define EPT_E_TYPE_MASK UINT64_C(0x0038)
416	/** Bits 3-5 - Memory type shifted mask. */
417	#define EPT_E_TYPE_SMASK UINT64_C(0x0007)
418	/** Bits 3-5 - Memory type shift count. */
419	#define EPT_E_TYPE_SHIFT 3
420	/** Bits 3-5 - Memory type: UC. */
421	#define EPT_E_TYPE_UC (UINT64_C(0) << EPT_E_TYPE_SHIFT)
422	/** Bits 3-5 - Memory type: WC. */
423	#define EPT_E_TYPE_WC (UINT64_C(1) << EPT_E_TYPE_SHIFT)
424	/** Bits 3-5 - Memory type: Invalid (2). */
425	#define EPT_E_TYPE_INVALID_2 (UINT64_C(2) << EPT_E_TYPE_SHIFT)
426	/** Bits 3-5 - Memory type: Invalid (3). */
427	#define EPT_E_TYPE_INVALID_3 (UINT64_C(3) << EPT_E_TYPE_SHIFT)
428	/** Bits 3-5 - Memory type: WT. */
429	#define EPT_E_TYPE_WT (UINT64_C(4) << EPT_E_TYPE_SHIFT)
430	/** Bits 3-5 - Memory type: WP. */
431	#define EPT_E_TYPE_WP (UINT64_C(5) << EPT_E_TYPE_SHIFT)
432	/** Bits 3-5 - Memory type: WB. */
433	#define EPT_E_TYPE_WB (UINT64_C(6) << EPT_E_TYPE_SHIFT)
434	/** Bits 3-5 - Memory type: Invalid (7). */
435	#define EPT_E_TYPE_INVALID_7 (UINT64_C(7) << EPT_E_TYPE_SHIFT)
436
437	/** Bit 6 - Ignore page attribute table (leaf, MBZ). */
438	#define EPT_E_BIT_IGNORE_PAT 6
439	#define EPT_E_IGNORE_PAT RT_BIT_64(EPT_E_BIT_IGNORE_PAT) /*< @see EPT_E_BIT_IGNORE_PAT /
440	/** Bit 7 - Leaf entry (MBZ in PML4, ignored in PT). */
441	#define EPT_E_BIT_LEAF 7
442	#define EPT_E_LEAF RT_BIT_64(EPT_E_BIT_LEAF) /*< @see EPT_E_BIT_LEAF /
443	/** Bit 8 - Accessed (all levels).
444	* @note Ignored and not written when EPTP bit 6 is 0. */
445	#define EPT_E_BIT_ACCESSED 8
446	#define EPT_E_ACCESSED RT_BIT_64(EPT_E_BIT_ACCESSED) /*< @see EPT_E_BIT_ACCESSED /
447	/** Bit 9 - Dirty (leaf only).
448	* @note Ignored and not written when EPTP bit 6 is 0. */
449	#define EPT_E_BIT_DIRTY 9
450	#define EPT_E_DIRTY RT_BIT_64(EPT_E_BIT_DIRTY) /*< @see EPT_E_BIT_DIRTY /
451	/** Bit 10 - Executable for usermode.
452	* @note This ignored if mode-based execution control is disabled. */
453	#define EPT_E_BIT_USER_EXECUTE 10
454	#define EPT_E_USER_EXECUTE RT_BIT_64(EPT_E_BIT_USER_EXECUTE) /*< @see EPT_E_BIT_USER_EXECUTE /
455
456	/* 11 is always ignored (at time of writing) */
457
458	/** Bits 12-51 - Physical Page number of the next level. */
459	#define EPT_E_PG_MASK UINT64_C(0x000ffffffffff000)
460
461	/** Bit 60 - Supervisor shadow stack (leaf only, ignored).
462	* @note Ignored if EPT bit 7 is 0. */
463	#define EPT_E_BIT_SHADOW_STACK 60
464	#define EPT_E_SHADOW_STACK RT_BIT_64(EPT_E_BIT_SHADOW_STACK) /*< @see EPT_E_BIT_SHADOW_STACK/
465	/** Bit 61 - Sub-page write permissions (PT only, ignored).
466	* @note Ignored if sub-page write permissions for EPT is disabled. */
467	#define EPT_E_BIT_SHADOW_STACK 60
468	#define EPT_E_SHADOW_STACK RT_BIT_64(EPT_E_BIT_SHADOW_STACK) /*< @see EPT_E_BIT_SHADOW_STACK/
469
470	/* Bit 62 is always ignored at time of writing. */
471
472	/** Bit 63 - Supress \#VE (leaf only, ignored).
473	* @note Ignored if EPT violation to \#VE conversion is disabled. */
474	#define EPT_E_BIT_IGNORE_VE 63
475	#define EPT_E_IGNORE_VE RT_BIT_64(EPT_E_BIT_IGNORE_VE) /*< @see EPT_E_BIT_IGNORE_VE/
476	/** @} */
477
478
479	/** @name VMX Extended Page Tables (EPT) Structures
480	* @{
481	*/
482
483	/**
484	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
485	*/
486	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
487
488	/**
489	* EPT Page Directory Pointer Entry. Bit view.
490	* In accordance with the VT-x spec.
491	*
492	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
493	* this did cause trouble with one compiler/version).
494	*/
495	typedef struct EPTPML4EBITS
496	{
497	/** Present bit. */
498	RT_GCC_EXTENSION uint64_t u1Present : 1;
499	/** Writable bit. */
500	RT_GCC_EXTENSION uint64_t u1Write : 1;
501	/** Executable bit. */
502	RT_GCC_EXTENSION uint64_t u1Execute : 1;
503	/** Reserved (must be 0). */
504	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
505	/** Available for software. */
506	RT_GCC_EXTENSION uint64_t u4Available : 4;
507	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
508	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
509	/** Available for software. */
510	RT_GCC_EXTENSION uint64_t u12Available : 12;
511	} EPTPML4EBITS;
512	AssertCompileSize(EPTPML4EBITS, 8);
513
514	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
515	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
516	/** The page shift to get the PML4 index. */
517	#define EPT_PML4_SHIFT X86_PML4_SHIFT
518	/** The PML4 index mask (apply to a shifted page address). */
519	#define EPT_PML4_MASK X86_PML4_MASK
520
521	/**
522	* EPT PML4E.
523	* In accordance with the VT-x spec.
524	*/
525	typedef union EPTPML4E
526	{
527	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
528	/** Normal view. */
529	EPTPML4EBITS n;
530	#endif
531	/** Unsigned integer view. */
532	X86PGPAEUINT u;
533	/** 64 bit unsigned integer view. */
534	uint64_t au64[1];
535	/** 32 bit unsigned integer view. */
536	uint32_t au32[2];
537	} EPTPML4E;
538	AssertCompileSize(EPTPML4E, 8);
539	/** Pointer to a PML4 table entry. */
540	typedef EPTPML4E *PEPTPML4E;
541	/** Pointer to a const PML4 table entry. */
542	typedef const EPTPML4E *PCEPTPML4E;
543
544	/**
545	* EPT PML4 Table.
546	* In accordance with the VT-x spec.
547	*/
548	typedef struct EPTPML4
549	{
550	EPTPML4E a[EPT_PG_ENTRIES];
551	} EPTPML4;
552	AssertCompileSize(EPTPML4, 0x1000);
553	/** Pointer to an EPT PML4 Table. */
554	typedef EPTPML4 *PEPTPML4;
555	/** Pointer to a const EPT PML4 Table. */
556	typedef const EPTPML4 *PCEPTPML4;
557
558	/**
559	* EPT Page Directory Pointer Entry. Bit view.
560	* In accordance with the VT-x spec.
561	*/
562	typedef struct EPTPDPTEBITS
563	{
564	/** Present bit. */
565	RT_GCC_EXTENSION uint64_t u1Present : 1;
566	/** Writable bit. */
567	RT_GCC_EXTENSION uint64_t u1Write : 1;
568	/** Executable bit. */
569	RT_GCC_EXTENSION uint64_t u1Execute : 1;
570	/** Reserved (must be 0). */
571	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
572	/** Available for software. */
573	RT_GCC_EXTENSION uint64_t u4Available : 4;
574	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
575	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
576	/** Available for software. */
577	RT_GCC_EXTENSION uint64_t u12Available : 12;
578	} EPTPDPTEBITS;
579	AssertCompileSize(EPTPDPTEBITS, 8);
580
581	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
582	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
583	/** The page shift to get the PDPT index. */
584	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
585	/** The PDPT index mask (apply to a shifted page address). */
586	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
587
588	/**
589	* EPT Page Directory Pointer.
590	* In accordance with the VT-x spec.
591	*/
592	typedef union EPTPDPTE
593	{
594	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
595	/** Normal view. */
596	EPTPDPTEBITS n;
597	#endif
598	/** Unsigned integer view. */
599	X86PGPAEUINT u;
600	/** 64 bit unsigned integer view. */
601	uint64_t au64[1];
602	/** 32 bit unsigned integer view. */
603	uint32_t au32[2];
604	} EPTPDPTE;
605	AssertCompileSize(EPTPDPTE, 8);
606	/** Pointer to an EPT Page Directory Pointer Entry. */
607	typedef EPTPDPTE *PEPTPDPTE;
608	/** Pointer to a const EPT Page Directory Pointer Entry. */
609	typedef const EPTPDPTE *PCEPTPDPTE;
610
611	/**
612	* EPT Page Directory Pointer Table.
613	* In accordance with the VT-x spec.
614	*/
615	typedef struct EPTPDPT
616	{
617	EPTPDPTE a[EPT_PG_ENTRIES];
618	} EPTPDPT;
619	AssertCompileSize(EPTPDPT, 0x1000);
620	/** Pointer to an EPT Page Directory Pointer Table. */
621	typedef EPTPDPT *PEPTPDPT;
622	/** Pointer to a const EPT Page Directory Pointer Table. */
623	typedef const EPTPDPT *PCEPTPDPT;
624
625	/**
626	* EPT Page Directory Table Entry. Bit view.
627	* In accordance with the VT-x spec.
628	*/
629	typedef struct EPTPDEBITS
630	{
631	/** Present bit. */
632	RT_GCC_EXTENSION uint64_t u1Present : 1;
633	/** Writable bit. */
634	RT_GCC_EXTENSION uint64_t u1Write : 1;
635	/** Executable bit. */
636	RT_GCC_EXTENSION uint64_t u1Execute : 1;
637	/** Reserved (must be 0). */
638	RT_GCC_EXTENSION uint64_t u4Reserved : 4;
639	/** Big page (must be 0 here). */
640	RT_GCC_EXTENSION uint64_t u1Size : 1;
641	/** Available for software. */
642	RT_GCC_EXTENSION uint64_t u4Available : 4;
643	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
644	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
645	/** Available for software. */
646	RT_GCC_EXTENSION uint64_t u12Available : 12;
647	} EPTPDEBITS;
648	AssertCompileSize(EPTPDEBITS, 8);
649
650	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
651	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
652	/** The page shift to get the PD index. */
653	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
654	/** The PD index mask (apply to a shifted page address). */
655	#define EPT_PD_MASK X86_PD_PAE_MASK
656
657	/**
658	* EPT 2MB Page Directory Table Entry. Bit view.
659	* In accordance with the VT-x spec.
660	*/
661	typedef struct EPTPDE2MBITS
662	{
663	/** Present bit. */
664	RT_GCC_EXTENSION uint64_t u1Present : 1;
665	/** Writable bit. */
666	RT_GCC_EXTENSION uint64_t u1Write : 1;
667	/** Executable bit. */
668	RT_GCC_EXTENSION uint64_t u1Execute : 1;
669	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
670	RT_GCC_EXTENSION uint64_t u3EMT : 3;
671	/** Ignore PAT memory type */
672	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
673	/** Big page (must be 1 here). */
674	RT_GCC_EXTENSION uint64_t u1Size : 1;
675	/** Available for software. */
676	RT_GCC_EXTENSION uint64_t u4Available : 4;
677	/** Reserved (must be 0). */
678	RT_GCC_EXTENSION uint64_t u9Reserved : 9;
679	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
680	RT_GCC_EXTENSION uint64_t u31PhysAddr : 31;
681	/** Available for software. */
682	RT_GCC_EXTENSION uint64_t u12Available : 12;
683	} EPTPDE2MBITS;
684	AssertCompileSize(EPTPDE2MBITS, 8);
685
686	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
687	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
688
689	/**
690	* EPT Page Directory Table Entry.
691	* In accordance with the VT-x spec.
692	*/
693	typedef union EPTPDE
694	{
695	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
696	/** Normal view. */
697	EPTPDEBITS n;
698	/** 2MB view (big). */
699	EPTPDE2MBITS b;
700	#endif
701	/** Unsigned integer view. */
702	X86PGPAEUINT u;
703	/** 64 bit unsigned integer view. */
704	uint64_t au64[1];
705	/** 32 bit unsigned integer view. */
706	uint32_t au32[2];
707	} EPTPDE;
708	AssertCompileSize(EPTPDE, 8);
709	/** Pointer to an EPT Page Directory Table Entry. */
710	typedef EPTPDE *PEPTPDE;
711	/** Pointer to a const EPT Page Directory Table Entry. */
712	typedef const EPTPDE *PCEPTPDE;
713
714	/**
715	* EPT Page Directory Table.
716	* In accordance with the VT-x spec.
717	*/
718	typedef struct EPTPD
719	{
720	EPTPDE a[EPT_PG_ENTRIES];
721	} EPTPD;
722	AssertCompileSize(EPTPD, 0x1000);
723	/** Pointer to an EPT Page Directory Table. */
724	typedef EPTPD *PEPTPD;
725	/** Pointer to a const EPT Page Directory Table. */
726	typedef const EPTPD *PCEPTPD;
727
728	/**
729	* EPT Page Table Entry. Bit view.
730	* In accordance with the VT-x spec.
731	*/
732	typedef struct EPTPTEBITS
733	{
734	/** 0 - Present bit.
735	* @remarks This is a convenience "misnomer". The bit actually indicates read access
736	* and the CPU will consider an entry with any of the first three bits set
737	* as present. Since all our valid entries will have this bit set, it can
738	* be used as a present indicator and allow some code sharing. */
739	RT_GCC_EXTENSION uint64_t u1Present : 1;
740	/** 1 - Writable bit. */
741	RT_GCC_EXTENSION uint64_t u1Write : 1;
742	/** 2 - Executable bit. */
743	RT_GCC_EXTENSION uint64_t u1Execute : 1;
744	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
745	RT_GCC_EXTENSION uint64_t u3EMT : 3;
746	/** 6 - Ignore PAT memory type */
747	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
748	/** 11:7 - Available for software. */
749	RT_GCC_EXTENSION uint64_t u5Available : 5;
750	/** 51:12 - Physical address of page. Restricted by maximum physical
751	* address width of the cpu. */
752	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
753	/** 63:52 - Available for software. */
754	RT_GCC_EXTENSION uint64_t u12Available : 12;
755	} EPTPTEBITS;
756	AssertCompileSize(EPTPTEBITS, 8);
757
758	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
759	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
760	/** The page shift to get the EPT PTE index. */
761	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
762	/** The EPT PT index mask (apply to a shifted page address). */
763	#define EPT_PT_MASK X86_PT_PAE_MASK
764
765	/**
766	* EPT Page Table Entry.
767	* In accordance with the VT-x spec.
768	*/
769	typedef union EPTPTE
770	{
771	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
772	/** Normal view. */
773	EPTPTEBITS n;
774	#endif
775	/** Unsigned integer view. */
776	X86PGPAEUINT u;
777	/** 64 bit unsigned integer view. */
778	uint64_t au64[1];
779	/** 32 bit unsigned integer view. */
780	uint32_t au32[2];
781	} EPTPTE;
782	AssertCompileSize(EPTPTE, 8);
783	/** Pointer to an EPT Page Directory Table Entry. */
784	typedef EPTPTE *PEPTPTE;
785	/** Pointer to a const EPT Page Directory Table Entry. */
786	typedef const EPTPTE *PCEPTPTE;
787
788	/**
789	* EPT Page Table.
790	* In accordance with the VT-x spec.
791	*/
792	typedef struct EPTPT
793	{
794	EPTPTE a[EPT_PG_ENTRIES];
795	} EPTPT;
796	AssertCompileSize(EPTPT, 0x1000);
797	/** Pointer to an extended page table. */
798	typedef EPTPT *PEPTPT;
799	/** Pointer to a const extended table. */
800	typedef const EPTPT *PCEPTPT;
801
802	/** @} */
803
804	/**
805	* VMX VPID flush types.
806	* Valid enum members are in accordance with the VT-x spec.
807	*/
808	typedef enum
809	{
810	/** Invalidate a specific page. */
811	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
812	/** Invalidate one context (specific VPID). */
813	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
814	/** Invalidate all contexts (all VPIDs). */
815	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
816	/** Invalidate a single VPID context retaining global mappings. */
817	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
818	/** Unsupported by VirtualBox. */
819	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
820	/** Unsupported by CPU. */
821	VMXTLBFLUSHVPID_NONE = 0xbad1
822	} VMXTLBFLUSHVPID;
823	AssertCompileSize(VMXTLBFLUSHVPID, 4);
824
825	/**
826	* VMX EPT flush types.
827	* @note Valid enums values are in accordance with the VT-x spec.
828	*/
829	typedef enum
830	{
831	/** Invalidate one context (specific EPT). */
832	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
833	/* Invalidate all contexts (all EPTs) */
834	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
835	/** Unsupported by VirtualBox. */
836	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
837	/** Unsupported by CPU. */
838	VMXTLBFLUSHEPT_NONE = 0xbad1
839	} VMXTLBFLUSHEPT;
840	AssertCompileSize(VMXTLBFLUSHEPT, 4);
841
842	/**
843	* VMX Posted Interrupt Descriptor.
844	* In accordance with the VT-x spec.
845	*/
846	typedef struct VMXPOSTEDINTRDESC
847	{
848	uint32_t aVectorBitmap[8];
849	uint32_t fOutstandingNotification : 1;
850	uint32_t uReserved0 : 31;
851	uint8_t au8Reserved0[28];
852	} VMXPOSTEDINTRDESC;
853	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
854	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
855	/** Pointer to a posted interrupt descriptor. */
856	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
857	/** Pointer to a const posted interrupt descriptor. */
858	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
859
860	/**
861	* VMX VMCS revision identifier.
862	* In accordance with the VT-x spec.
863	*/
864	typedef union
865	{
866	struct
867	{
868	/** Revision identifier. */
869	uint32_t u31RevisionId : 31;
870	/** Whether this is a shadow VMCS. */
871	uint32_t fIsShadowVmcs : 1;
872	} n;
873	/* The unsigned integer view. */
874	uint32_t u;
875	} VMXVMCSREVID;
876	AssertCompileSize(VMXVMCSREVID, 4);
877	/** Pointer to the VMXVMCSREVID union. */
878	typedef VMXVMCSREVID *PVMXVMCSREVID;
879	/** Pointer to a const VMXVMCSREVID union. */
880	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
881
882	/**
883	* VMX VM-exit instruction information.
884	* In accordance with the VT-x spec.
885	*/
886	typedef union
887	{
888	/** Plain unsigned int representation. */
889	uint32_t u;
890
891	/** INS and OUTS information. */
892	struct
893	{
894	uint32_t u7Reserved0 : 7;
895	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
896	uint32_t u3AddrSize : 3;
897	uint32_t u5Reserved1 : 5;
898	/** The segment register (X86_SREG_XXX). */
899	uint32_t iSegReg : 3;
900	uint32_t uReserved2 : 14;
901	} StrIo;
902
903	/** INVEPT, INVPCID, INVVPID information. */
904	struct
905	{
906	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
907	uint32_t u2Scaling : 2;
908	uint32_t u5Undef0 : 5;
909	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
910	uint32_t u3AddrSize : 3;
911	/** Cleared to 0. */
912	uint32_t u1Cleared0 : 1;
913	uint32_t u4Undef0 : 4;
914	/** The segment register (X86_SREG_XXX). */
915	uint32_t iSegReg : 3;
916	/** The index register (X86_GREG_XXX). */
917	uint32_t iIdxReg : 4;
918	/** Set if index register is invalid. */
919	uint32_t fIdxRegInvalid : 1;
920	/** The base register (X86_GREG_XXX). */
921	uint32_t iBaseReg : 4;
922	/** Set if base register is invalid. */
923	uint32_t fBaseRegInvalid : 1;
924	/** Register 2 (X86_GREG_XXX). */
925	uint32_t iReg2 : 4;
926	} Inv;
927
928	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
929	struct
930	{
931	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
932	uint32_t u2Scaling : 2;
933	uint32_t u5Reserved0 : 5;
934	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
935	uint32_t u3AddrSize : 3;
936	/** Cleared to 0. */
937	uint32_t u1Cleared0 : 1;
938	uint32_t u4Reserved0 : 4;
939	/** The segment register (X86_SREG_XXX). */
940	uint32_t iSegReg : 3;
941	/** The index register (X86_GREG_XXX). */
942	uint32_t iIdxReg : 4;
943	/** Set if index register is invalid. */
944	uint32_t fIdxRegInvalid : 1;
945	/** The base register (X86_GREG_XXX). */
946	uint32_t iBaseReg : 4;
947	/** Set if base register is invalid. */
948	uint32_t fBaseRegInvalid : 1;
949	/** Register 2 (X86_GREG_XXX). */
950	uint32_t iReg2 : 4;
951	} VmxXsave;
952
953	/** LIDT, LGDT, SIDT, SGDT information. */
954	struct
955	{
956	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
957	uint32_t u2Scaling : 2;
958	uint32_t u5Undef0 : 5;
959	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
960	uint32_t u3AddrSize : 3;
961	/** Always cleared to 0. */
962	uint32_t u1Cleared0 : 1;
963	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
964	uint32_t uOperandSize : 1;
965	uint32_t u3Undef0 : 3;
966	/** The segment register (X86_SREG_XXX). */
967	uint32_t iSegReg : 3;
968	/** The index register (X86_GREG_XXX). */
969	uint32_t iIdxReg : 4;
970	/** Set if index register is invalid. */
971	uint32_t fIdxRegInvalid : 1;
972	/** The base register (X86_GREG_XXX). */
973	uint32_t iBaseReg : 4;
974	/** Set if base register is invalid. */
975	uint32_t fBaseRegInvalid : 1;
976	/** Instruction identity (VMX_INSTR_ID_XXX). */
977	uint32_t u2InstrId : 2;
978	uint32_t u2Undef0 : 2;
979	} GdtIdt;
980
981	/** LLDT, LTR, SLDT, STR information. */
982	struct
983	{
984	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
985	uint32_t u2Scaling : 2;
986	uint32_t u1Undef0 : 1;
987	/** Register 1 (X86_GREG_XXX). */
988	uint32_t iReg1 : 4;
989	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
990	uint32_t u3AddrSize : 3;
991	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
992	uint32_t fIsRegOperand : 1;
993	uint32_t u4Undef0 : 4;
994	/** The segment register (X86_SREG_XXX). */
995	uint32_t iSegReg : 3;
996	/** The index register (X86_GREG_XXX). */
997	uint32_t iIdxReg : 4;
998	/** Set if index register is invalid. */
999	uint32_t fIdxRegInvalid : 1;
1000	/** The base register (X86_GREG_XXX). */
1001	uint32_t iBaseReg : 4;
1002	/** Set if base register is invalid. */
1003	uint32_t fBaseRegInvalid : 1;
1004	/** Instruction identity (VMX_INSTR_ID_XXX). */
1005	uint32_t u2InstrId : 2;
1006	uint32_t u2Undef0 : 2;
1007	} LdtTr;
1008
1009	/** RDRAND, RDSEED information. */
1010	struct
1011	{
1012	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1013	uint32_t u2Undef0 : 2;
1014	/** Destination register (X86_GREG_XXX). */
1015	uint32_t iReg1 : 4;
1016	uint32_t u4Undef0 : 4;
1017	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1018	uint32_t u2OperandSize : 2;
1019	uint32_t u19Def0 : 20;
1020	} RdrandRdseed;
1021
1022	/** VMREAD, VMWRITE information. */
1023	struct
1024	{
1025	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1026	uint32_t u2Scaling : 2;
1027	uint32_t u1Undef0 : 1;
1028	/** Register 1 (X86_GREG_XXX). */
1029	uint32_t iReg1 : 4;
1030	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1031	uint32_t u3AddrSize : 3;
1032	/** Memory or register operand. */
1033	uint32_t fIsRegOperand : 1;
1034	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1035	uint32_t u4Undef0 : 4;
1036	/** The segment register (X86_SREG_XXX). */
1037	uint32_t iSegReg : 3;
1038	/** The index register (X86_GREG_XXX). */
1039	uint32_t iIdxReg : 4;
1040	/** Set if index register is invalid. */
1041	uint32_t fIdxRegInvalid : 1;
1042	/** The base register (X86_GREG_XXX). */
1043	uint32_t iBaseReg : 4;
1044	/** Set if base register is invalid. */
1045	uint32_t fBaseRegInvalid : 1;
1046	/** Register 2 (X86_GREG_XXX). */
1047	uint32_t iReg2 : 4;
1048	} VmreadVmwrite;
1049
1050	/** This is a combination field of all instruction information. Note! Not all field
1051	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1052	* specialized fields are overwritten by their generic counterparts (e.g. no
1053	* instruction identity field). */
1054	struct
1055	{
1056	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1057	uint32_t u2Scaling : 2;
1058	uint32_t u1Undef0 : 1;
1059	/** Register 1 (X86_GREG_XXX). */
1060	uint32_t iReg1 : 4;
1061	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1062	uint32_t u3AddrSize : 3;
1063	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1064	uint32_t fIsRegOperand : 1;
1065	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1066	uint32_t uOperandSize : 2;
1067	uint32_t u2Undef0 : 2;
1068	/** The segment register (X86_SREG_XXX). */
1069	uint32_t iSegReg : 3;
1070	/** The index register (X86_GREG_XXX). */
1071	uint32_t iIdxReg : 4;
1072	/** Set if index register is invalid. */
1073	uint32_t fIdxRegInvalid : 1;
1074	/** The base register (X86_GREG_XXX). */
1075	uint32_t iBaseReg : 4;
1076	/** Set if base register is invalid. */
1077	uint32_t fBaseRegInvalid : 1;
1078	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1079	uint32_t iReg2 : 4;
1080	} All;
1081	} VMXEXITINSTRINFO;
1082	AssertCompileSize(VMXEXITINSTRINFO, 4);
1083	/** Pointer to a VMX VM-exit instruction info. struct. */
1084	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1085	/** Pointer to a const VMX VM-exit instruction info. struct. */
1086	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1087
1088
1089	/** @name VM-entry failure reported in Exit qualification.
1090	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1091	* @{
1092	*/
1093	/** No errors during VM-entry. */
1094	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1095	/** Not used. */
1096	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1097	/** Error while loading PDPTEs. */
1098	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1099	/** NMI injection when blocking-by-STI is set. */
1100	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1101	/** Invalid VMCS link pointer. */
1102	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1103	/** @} */
1104
1105
1106	/** @name VMXMSRPM_XXX - VMX MSR-bitmap permissions.
1107	* These are -not- specified by Intel but used internally by VirtualBox.
1108	* @{ */
1109	/** Guest software reads of this MSR must not cause a VM-exit. */
1110	#define VMXMSRPM_ALLOW_RD RT_BIT(0)
1111	/** Guest software reads of this MSR must cause a VM-exit. */
1112	#define VMXMSRPM_EXIT_RD RT_BIT(1)
1113	/** Guest software writes to this MSR must not cause a VM-exit. */
1114	#define VMXMSRPM_ALLOW_WR RT_BIT(2)
1115	/** Guest software writes to this MSR must cause a VM-exit. */
1116	#define VMXMSRPM_EXIT_WR RT_BIT(3)
1117	/** Guest software reads or writes of this MSR must not cause a VM-exit. */
1118	#define VMXMSRPM_ALLOW_RD_WR (VMXMSRPM_ALLOW_RD \| VMXMSRPM_ALLOW_WR)
1119	/** Guest software reads or writes of this MSR must cause a VM-exit. */
1120	#define VMXMSRPM_EXIT_RD_WR (VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR)
1121	/** Mask of valid MSR read permissions. */
1122	#define VMXMSRPM_RD_MASK (VMXMSRPM_ALLOW_RD \| VMXMSRPM_EXIT_RD)
1123	/** Mask of valid MSR write permissions. */
1124	#define VMXMSRPM_WR_MASK (VMXMSRPM_ALLOW_WR \| VMXMSRPM_EXIT_WR)
1125	/** Mask of valid MSR permissions. */
1126	#define VMXMSRPM_MASK (VMXMSRPM_RD_MASK \| VMXMSRPM_WR_MASK)
1127	/** */
1128	/** Gets whether the MSR permission is valid or not. */
1129	#define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \
1130	&& ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \
1131	&& ((a_Msrpm) & VMXMSRPM_RD_MASK) != VMXMSRPM_RD_MASK \
1132	&& ((a_Msrpm) & VMXMSRPM_WR_MASK) != VMXMSRPM_WR_MASK)
1133	/** @} */
1134
1135	/**
1136	* VMX MSR autoload/store slot.
1137	* In accordance with the VT-x spec.
1138	*/
1139	typedef struct VMXAUTOMSR
1140	{
1141	/** The MSR Id. */
1142	uint32_t u32Msr;
1143	/** Reserved (MBZ). */
1144	uint32_t u32Reserved;
1145	/** The MSR value. */
1146	uint64_t u64Value;
1147	} VMXAUTOMSR;
1148	AssertCompileSize(VMXAUTOMSR, 16);
1149	/** Pointer to an MSR load/store element. */
1150	typedef VMXAUTOMSR *PVMXAUTOMSR;
1151	/** Pointer to a const MSR load/store element. */
1152	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1153
1154	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1155	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1156
1157	/**
1158	* VMX tagged-TLB flush types.
1159	*/
1160	typedef enum
1161	{
1162	VMXTLBFLUSHTYPE_EPT,
1163	VMXTLBFLUSHTYPE_VPID,
1164	VMXTLBFLUSHTYPE_EPT_VPID,
1165	VMXTLBFLUSHTYPE_NONE
1166	} VMXTLBFLUSHTYPE;
1167	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1168	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1169	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1170	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1171
1172	/**
1173	* VMX controls MSR.
1174	* In accordance with the VT-x spec.
1175	*/
1176	typedef union
1177	{
1178	struct
1179	{
1180	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1181	uint32_t allowed0;
1182	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1183	* controls. */
1184	uint32_t allowed1;
1185	} n;
1186	uint64_t u;
1187	} VMXCTLSMSR;
1188	AssertCompileSize(VMXCTLSMSR, 8);
1189	/** Pointer to a VMXCTLSMSR union. */
1190	typedef VMXCTLSMSR *PVMXCTLSMSR;
1191	/** Pointer to a const VMXCTLSMSR union. */
1192	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1193
1194	/**
1195	* VMX MSRs.
1196	*/
1197	typedef struct VMXMSRS
1198	{
1199	/** VMX/SMX Feature control. */
1200	uint64_t u64FeatCtrl;
1201	/** Basic information. */
1202	uint64_t u64Basic;
1203	/** Pin-based VM-execution controls. */
1204	VMXCTLSMSR PinCtls;
1205	/** Processor-based VM-execution controls. */
1206	VMXCTLSMSR ProcCtls;
1207	/** Secondary processor-based VM-execution controls. */
1208	VMXCTLSMSR ProcCtls2;
1209	/** VM-exit controls. */
1210	VMXCTLSMSR ExitCtls;
1211	/** VM-entry controls. */
1212	VMXCTLSMSR EntryCtls;
1213	/** True pin-based VM-execution controls. */
1214	VMXCTLSMSR TruePinCtls;
1215	/** True processor-based VM-execution controls. */
1216	VMXCTLSMSR TrueProcCtls;
1217	/** True VM-entry controls. */
1218	VMXCTLSMSR TrueEntryCtls;
1219	/** True VM-exit controls. */
1220	VMXCTLSMSR TrueExitCtls;
1221	/** Miscellaneous data. */
1222	uint64_t u64Misc;
1223	/** CR0 fixed-0 - bits set here must be set in VMX operation. */
1224	uint64_t u64Cr0Fixed0;
1225	/** CR0 fixed-1 - bits clear here must be clear in VMX operation. */
1226	uint64_t u64Cr0Fixed1;
1227	/** CR4 fixed-0 - bits set here must be set in VMX operation. */
1228	uint64_t u64Cr4Fixed0;
1229	/** CR4 fixed-1 - bits clear here must be clear in VMX operation. */
1230	uint64_t u64Cr4Fixed1;
1231	/** VMCS enumeration. */
1232	uint64_t u64VmcsEnum;
1233	/** VM Functions. */
1234	uint64_t u64VmFunc;
1235	/** EPT, VPID capabilities. */
1236	uint64_t u64EptVpidCaps;
1237	/** Reserved for future. */
1238	uint64_t a_u64Reserved[9];
1239	} VMXMSRS;
1240	AssertCompileSizeAlignment(VMXMSRS, 8);
1241	AssertCompileSize(VMXMSRS, 224);
1242	/** Pointer to a VMXMSRS struct. */
1243	typedef VMXMSRS *PVMXMSRS;
1244	/** Pointer to a const VMXMSRS struct. */
1245	typedef const VMXMSRS *PCVMXMSRS;
1246
1247
1248	/**
1249	* LBR MSRs.
1250	*/
1251	typedef struct LBRMSRS
1252	{
1253	/** List of LastBranch-From-IP MSRs. */
1254	uint64_t au64BranchFromIpMsr[32];
1255	/** List of LastBranch-To-IP MSRs. */
1256	uint64_t au64BranchToIpMsr[32];
1257	/** The MSR containing the index to the most recent branch record. */
1258	uint64_t uBranchTosMsr;
1259	} LBRMSRS;
1260	AssertCompileSizeAlignment(LBRMSRS, 8);
1261	/** Pointer to a VMXMSRS struct. */
1262	typedef LBRMSRS *PLBRMSRS;
1263	/** Pointer to a const VMXMSRS struct. */
1264	typedef const LBRMSRS *PCLBRMSRS;
1265
1266
1267	/** @name VMX Basic Exit Reasons.
1268	* @{
1269	*/
1270	/** -1 Invalid exit code */
1271	#define VMX_EXIT_INVALID (-1)
1272	/** 0 Exception or non-maskable interrupt (NMI). */
1273	#define VMX_EXIT_XCPT_OR_NMI 0
1274	/** 1 External interrupt. */
1275	#define VMX_EXIT_EXT_INT 1
1276	/** 2 Triple fault. */
1277	#define VMX_EXIT_TRIPLE_FAULT 2
1278	/** 3 INIT signal. */
1279	#define VMX_EXIT_INIT_SIGNAL 3
1280	/** 4 Start-up IPI (SIPI). */
1281	#define VMX_EXIT_SIPI 4
1282	/** 5 I/O system-management interrupt (SMI). */
1283	#define VMX_EXIT_IO_SMI 5
1284	/** 6 Other SMI. */
1285	#define VMX_EXIT_SMI 6
1286	/** 7 Interrupt window exiting. */
1287	#define VMX_EXIT_INT_WINDOW 7
1288	/** 8 NMI window exiting. */
1289	#define VMX_EXIT_NMI_WINDOW 8
1290	/** 9 Task switch. */
1291	#define VMX_EXIT_TASK_SWITCH 9
1292	/** 10 Guest software attempted to execute CPUID. */
1293	#define VMX_EXIT_CPUID 10
1294	/** 11 Guest software attempted to execute GETSEC. */
1295	#define VMX_EXIT_GETSEC 11
1296	/** 12 Guest software attempted to execute HLT. */
1297	#define VMX_EXIT_HLT 12
1298	/** 13 Guest software attempted to execute INVD. */
1299	#define VMX_EXIT_INVD 13
1300	/** 14 Guest software attempted to execute INVLPG. */
1301	#define VMX_EXIT_INVLPG 14
1302	/** 15 Guest software attempted to execute RDPMC. */
1303	#define VMX_EXIT_RDPMC 15
1304	/** 16 Guest software attempted to execute RDTSC. */
1305	#define VMX_EXIT_RDTSC 16
1306	/** 17 Guest software attempted to execute RSM in SMM. */
1307	#define VMX_EXIT_RSM 17
1308	/** 18 Guest software executed VMCALL. */
1309	#define VMX_EXIT_VMCALL 18
1310	/** 19 Guest software executed VMCLEAR. */
1311	#define VMX_EXIT_VMCLEAR 19
1312	/** 20 Guest software executed VMLAUNCH. */
1313	#define VMX_EXIT_VMLAUNCH 20
1314	/** 21 Guest software executed VMPTRLD. */
1315	#define VMX_EXIT_VMPTRLD 21
1316	/** 22 Guest software executed VMPTRST. */
1317	#define VMX_EXIT_VMPTRST 22
1318	/** 23 Guest software executed VMREAD. */
1319	#define VMX_EXIT_VMREAD 23
1320	/** 24 Guest software executed VMRESUME. */
1321	#define VMX_EXIT_VMRESUME 24
1322	/** 25 Guest software executed VMWRITE. */
1323	#define VMX_EXIT_VMWRITE 25
1324	/** 26 Guest software executed VMXOFF. */
1325	#define VMX_EXIT_VMXOFF 26
1326	/** 27 Guest software executed VMXON. */
1327	#define VMX_EXIT_VMXON 27
1328	/** 28 Control-register accesses. */
1329	#define VMX_EXIT_MOV_CRX 28
1330	/** 29 Debug-register accesses. */
1331	#define VMX_EXIT_MOV_DRX 29
1332	/** 30 I/O instruction. */
1333	#define VMX_EXIT_IO_INSTR 30
1334	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1335	#define VMX_EXIT_RDMSR 31
1336	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1337	#define VMX_EXIT_WRMSR 32
1338	/** 33 VM-entry failure due to invalid guest state. */
1339	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1340	/** 34 VM-entry failure due to MSR loading. */
1341	#define VMX_EXIT_ERR_MSR_LOAD 34
1342	/** 36 Guest software executed MWAIT. */
1343	#define VMX_EXIT_MWAIT 36
1344	/** 37 VM-exit due to monitor trap flag. */
1345	#define VMX_EXIT_MTF 37
1346	/** 39 Guest software attempted to execute MONITOR. */
1347	#define VMX_EXIT_MONITOR 39
1348	/** 40 Guest software attempted to execute PAUSE. */
1349	#define VMX_EXIT_PAUSE 40
1350	/** 41 VM-entry failure due to machine-check. */
1351	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1352	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1353	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1354	/** 44 APIC access. Guest software attempted to access memory at a physical
1355	* address on the APIC-access page. */
1356	#define VMX_EXIT_APIC_ACCESS 44
1357	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1358	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1359	#define VMX_EXIT_VIRTUALIZED_EOI 45
1360	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1361	* SGDT, or SIDT. */
1362	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1363	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1364	* SLDT, or STR. */
1365	#define VMX_EXIT_LDTR_TR_ACCESS 47
1366	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1367	* was disallowed by the configuration of the EPT paging structures. */
1368	#define VMX_EXIT_EPT_VIOLATION 48
1369	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1370	* address encountered a misconfigured EPT paging-structure entry. */
1371	#define VMX_EXIT_EPT_MISCONFIG 49
1372	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1373	#define VMX_EXIT_INVEPT 50
1374	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1375	#define VMX_EXIT_RDTSCP 51
1376	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1377	#define VMX_EXIT_PREEMPT_TIMER 52
1378	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1379	#define VMX_EXIT_INVVPID 53
1380	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1381	#define VMX_EXIT_WBINVD 54
1382	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1383	#define VMX_EXIT_XSETBV 55
1384	/** 56 APIC write. Guest completed write to virtual-APIC. */
1385	#define VMX_EXIT_APIC_WRITE 56
1386	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1387	#define VMX_EXIT_RDRAND 57
1388	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1389	#define VMX_EXIT_INVPCID 58
1390	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1391	#define VMX_EXIT_VMFUNC 59
1392	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1393	#define VMX_EXIT_ENCLS 60
1394	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1395	* enabled. */
1396	#define VMX_EXIT_RDSEED 61
1397	/** 62 - Page-modification log full. */
1398	#define VMX_EXIT_PML_FULL 62
1399	/** 63 - XSAVES. Guest software attempted to execute XSAVES and exiting was
1400	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1401	#define VMX_EXIT_XSAVES 63
1402	/** 64 - XRSTORS. Guest software attempted to execute XRSTORS and exiting
1403	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1404	#define VMX_EXIT_XRSTORS 64
1405	/** 66 - SPP-related event. Attempt to determine an access' sub-page write
1406	* permission encountered an SPP miss or misconfiguration. */
1407	#define VMX_EXIT_SPP_EVENT 66
1408	/* 67 - UMWAIT. Guest software attempted to execute UMWAIT and exiting was enabled. */
1409	#define VMX_EXIT_UMWAIT 67
1410	/** 68 - TPAUSE. Guest software attempted to execute TPAUSE and exiting was
1411	* enabled. */
1412	#define VMX_EXIT_TPAUSE 68
1413	/** The maximum exit value (inclusive). */
1414	#define VMX_EXIT_MAX (VMX_EXIT_TPAUSE)
1415	/** @} */
1416
1417
1418	/** @name VM Instruction Errors.
1419	* In accordance with the VT-x spec.
1420	* See Intel spec. "30.4 VM Instruction Error Numbers"
1421	* @{
1422	*/
1423	typedef enum
1424	{
1425	/** VMCALL executed in VMX root operation. */
1426	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1427	/** VMCLEAR with invalid physical address. */
1428	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1429	/** VMCLEAR with VMXON pointer. */
1430	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1431	/** VMLAUNCH with non-clear VMCS. */
1432	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1433	/** VMRESUME with non-launched VMCS. */
1434	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1435	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1436	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1437	/** VM-entry with invalid control field(s). */
1438	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1439	/** VM-entry with invalid host-state field(s). */
1440	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1441	/** VMPTRLD with invalid physical address. */
1442	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1443	/** VMPTRLD with VMXON pointer. */
1444	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1445	/** VMPTRLD with incorrect VMCS revision identifier. */
1446	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1447	/** VMREAD from unsupported VMCS component. */
1448	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1449	/** VMWRITE to unsupported VMCS component. */
1450	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1451	/** VMWRITE to read-only VMCS component. */
1452	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1453	/** VMXON executed in VMX root operation. */
1454	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1455	/** VM-entry with invalid executive-VMCS pointer. */
1456	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1457	/** VM-entry with non-launched executive VMCS. */
1458	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1459	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1460	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1461	/** VMCALL with non-clear VMCS. */
1462	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1463	/** VMCALL with invalid VM-exit control fields. */
1464	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1465	/** VMCALL with incorrect MSEG revision identifier. */
1466	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1467	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1468	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1469	/** VMCALL with invalid SMM-monitor features. */
1470	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1471	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1472	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1473	/** VM-entry with events blocked by MOV SS. */
1474	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1475	/** Invalid operand to INVEPT/INVVPID. */
1476	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1477	} VMXINSTRERR;
1478	/** @} */
1479
1480
1481	/** @name VMX abort reasons.
1482	* In accordance with the VT-x spec.
1483	* See Intel spec. "27.7 VMX Aborts".
1484	* Update HMGetVmxAbortDesc() if new reasons are added.
1485	* @{
1486	*/
1487	typedef enum
1488	{
1489	/** None - don't use this / uninitialized value. */
1490	VMXABORT_NONE = 0,
1491	/** VMX abort caused during saving of guest MSRs. */
1492	VMXABORT_SAVE_GUEST_MSRS = 1,
1493	/** VMX abort caused during host PDPTE checks. */
1494	VMXBOART_HOST_PDPTE = 2,
1495	/** VMX abort caused due to current VMCS being corrupted. */
1496	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1497	/** VMX abort caused during loading of host MSRs. */
1498	VMXABORT_LOAD_HOST_MSR = 4,
1499	/** VMX abort caused due to a machine-check exception during VM-exit. */
1500	VMXABORT_MACHINE_CHECK_XCPT = 5,
1501	/** VMX abort caused due to invalid return from long mode. */
1502	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1503	/* Type size hack. */
1504	VMXABORT_32BIT_HACK = 0x7fffffff
1505	} VMXABORT;
1506	AssertCompileSize(VMXABORT, 4);
1507	/** @} */
1508
1509
1510	/** @name VMX MSR - Basic VMX information.
1511	* @{
1512	*/
1513	/** VMCS (and related regions) memory type - Uncacheable. */
1514	#define VMX_BASIC_MEM_TYPE_UC 0
1515	/** VMCS (and related regions) memory type - Write back. */
1516	#define VMX_BASIC_MEM_TYPE_WB 6
1517	/** Width of physical addresses used for VMCS and associated memory regions
1518	* (1=32-bit, 0=processor's physical address width). */
1519	#define VMX_BASIC_PHYSADDR_WIDTH_32BIT RT_BIT_64(48)
1520
1521	/** Bit fields for MSR_IA32_VMX_BASIC. */
1522	/** VMCS revision identifier used by the processor. */
1523	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1524	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1525	/** Bit 31 is reserved and RAZ. */
1526	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1527	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1528	/** VMCS size in bytes. */
1529	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1530	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1531	/** Bits 45:47 are reserved. */
1532	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1533	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1534	/** Width of physical addresses used for the VMCS and associated memory regions
1535	* (always 0 on CPUs that support Intel 64 architecture). */
1536	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1537	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1538	/** Dual-monitor treatment of SMI and SMM supported. */
1539	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1540	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1541	/** Memory type that must be used for the VMCS and associated memory regions. */
1542	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1543	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1544	/** VM-exit instruction information for INS/OUTS. */
1545	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1546	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1547	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1548	* bits in VMX control MSRs. */
1549	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1550	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1551	/** Whether VM-entry can delivery error code for all hardware exception vectors. */
1552	#define VMX_BF_BASIC_XCPT_ERRCODE_SHIFT 56
1553	#define VMX_BF_BASIC_XCPT_ERRCODE_MASK UINT64_C(0x0100000000000000)
1554	/** Bits 57:63 are reserved and RAZ. */
1555	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 57
1556	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xfe00000000000000)
1557	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1558	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1559	VMCS_INS_OUTS, TRUE_CTLS, XCPT_ERRCODE, RSVD_56_63));
1560	/** @} */
1561
1562
1563	/** @name VMX MSR - Miscellaneous data.
1564	* @{
1565	*/
1566	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1567	#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1568	/** Whether Intel PT is supported in VMX operation. */
1569	#define VMX_MISC_INTEL_PT RT_BIT(14)
1570	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1571	* VMWRITE cannot modify read-only VM-exit information fields. */
1572	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1573	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1574	* instructions. */
1575	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1576	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1577	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1578	/** Maximum CR3-target count supported by the CPU. */
1579	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1580
1581	/** Bit fields for MSR_IA32_VMX_MISC. */
1582	/** Relationship between the preemption timer and tsc. */
1583	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1584	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1585	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1586	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1587	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1588	/** Activity states supported by the implementation. */
1589	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1590	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1591	/** Bits 9:13 is reserved and RAZ. */
1592	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1593	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1594	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1595	#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1596	#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1597	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1598	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1599	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1600	/** Number of CR3 target values supported by the processor. (0-256) */
1601	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1602	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1603	/** Maximum number of MSRs in the VMCS. */
1604	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1605	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1606	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1607	* SMIs. */
1608	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1609	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1610	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1611	* VMWRITE cannot modify read-only VM-exit information fields. */
1612	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1613	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1614	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1615	* instructions. */
1616	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1617	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1618	/** Bit 31 is reserved and RAZ. */
1619	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1620	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1621	/** 32-bit MSEG revision ID used by the processor. */
1622	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1623	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1624	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1625	(PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1626	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1627	/** @} */
1628
1629	/** @name VMX MSR - VMCS enumeration.
1630	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1631	* @{
1632	*/
1633	/** Bit 0 is reserved and RAZ. */
1634	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1635	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1636	/** Highest index value used in VMCS field encoding. */
1637	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1638	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1639	/** Bit 10:63 is reserved and RAZ. */
1640	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1641	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1642	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1643	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1644	/** @} */
1645
1646
1647	/** @name VMX MSR - VM Functions.
1648	* Bit fields for MSR_IA32_VMX_VMFUNC.
1649	* @{
1650	*/
1651	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1652	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1653	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1654	/** Bits 1:63 are reserved and RAZ. */
1655	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1656	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1657	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1658	(EPTP_SWITCHING, RSVD_1_63));
1659	/** @} */
1660
1661
1662	/** @name VMX MSR - EPT/VPID capabilities.
1663	* @{
1664	*/
1665	/** Supports execute-only translations by EPT. */
1666	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1667	/** Supports page-walk length of 4. */
1668	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1669	/** Supports page-walk length of 5. */
1670	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5 RT_BIT_64(7)
1671	/** Supports EPT paging-structure memory type to be uncacheable. */
1672	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1673	/** Supports EPT paging structure memory type to be write-back. */
1674	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1675	/** Supports EPT PDE to map a 2 MB page. */
1676	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1677	/** Supports EPT PDPTE to map a 1 GB page. */
1678	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1679	/** Supports INVEPT instruction. */
1680	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1681	/** Supports accessed and dirty flags for EPT. */
1682	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1683	/** Supports advanced VM-exit info. for EPT violations. */
1684	#define MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT RT_BIT_64(22)
1685	/** Supports supervisor shadow-stack control. */
1686	#define MSR_IA32_VMX_EPT_VPID_CAP_SSS RT_BIT_64(23)
1687	/** Supports single-context INVEPT type. */
1688	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1689	/** Supports all-context INVEPT type. */
1690	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1691	/** Supports INVVPID instruction. */
1692	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1693	/** Supports individual-address INVVPID type. */
1694	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1695	/** Supports single-context INVVPID type. */
1696	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1697	/** Supports all-context INVVPID type. */
1698	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1699	/** Supports singe-context-retaining-globals INVVPID type. */
1700	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1701
1702	/** Bit fields for MSR_IA32_VMX_EPT_VPID_CAP. */
1703	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_SHIFT 0
1704	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_MASK UINT64_C(0x0000000000000001)
1705	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_SHIFT 1
1706	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_MASK UINT64_C(0x000000000000003e)
1707	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_SHIFT 6
1708	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_MASK UINT64_C(0x0000000000000040)
1709	#define VMX_BF_EPT_VPID_CAP_RSVD_7_SHIFT 7
1710	#define VMX_BF_EPT_VPID_CAP_RSVD_7_MASK UINT64_C(0x0000000000000080)
1711	#define VMX_BF_EPT_VPID_CAP_EMT_UC_SHIFT 8
1712	#define VMX_BF_EPT_VPID_CAP_EMT_UC_MASK UINT64_C(0x0000000000000100)
1713	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_SHIFT 9
1714	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1715	#define VMX_BF_EPT_VPID_CAP_EMT_WB_SHIFT 14
1716	#define VMX_BF_EPT_VPID_CAP_EMT_WB_MASK UINT64_C(0x0000000000004000)
1717	#define VMX_BF_EPT_VPID_CAP_RSVD_15_SHIFT 15
1718	#define VMX_BF_EPT_VPID_CAP_RSVD_15_MASK UINT64_C(0x0000000000008000)
1719	#define VMX_BF_EPT_VPID_CAP_PDE_2M_SHIFT 16
1720	#define VMX_BF_EPT_VPID_CAP_PDE_2M_MASK UINT64_C(0x0000000000010000)
1721	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_SHIFT 17
1722	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_MASK UINT64_C(0x0000000000020000)
1723	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_SHIFT 18
1724	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_MASK UINT64_C(0x00000000000c0000)
1725	#define VMX_BF_EPT_VPID_CAP_INVEPT_SHIFT 20
1726	#define VMX_BF_EPT_VPID_CAP_INVEPT_MASK UINT64_C(0x0000000000100000)
1727	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_SHIFT 21
1728	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_MASK UINT64_C(0x0000000000200000)
1729	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_SHIFT 22
1730	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_MASK UINT64_C(0x0000000000400000)
1731	#define VMX_BF_EPT_VPID_CAP_SSS_SHIFT 23
1732	#define VMX_BF_EPT_VPID_CAP_SSS_MASK UINT64_C(0x0000000000800000)
1733	#define VMX_BF_EPT_VPID_CAP_RSVD_24_SHIFT 24
1734	#define VMX_BF_EPT_VPID_CAP_RSVD_24_MASK UINT64_C(0x0000000001000000)
1735	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_SHIFT 25
1736	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_MASK UINT64_C(0x0000000002000000)
1737	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_SHIFT 26
1738	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_MASK UINT64_C(0x0000000004000000)
1739	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_SHIFT 27
1740	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_MASK UINT64_C(0x00000000f8000000)
1741	#define VMX_BF_EPT_VPID_CAP_INVVPID_SHIFT 32
1742	#define VMX_BF_EPT_VPID_CAP_INVVPID_MASK UINT64_C(0x0000000100000000)
1743	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_SHIFT 33
1744	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_MASK UINT64_C(0x000000fe00000000)
1745	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_SHIFT 40
1746	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_MASK UINT64_C(0x0000010000000000)
1747	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_SHIFT 41
1748	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_MASK UINT64_C(0x0000020000000000)
1749	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_SHIFT 42
1750	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_MASK UINT64_C(0x0000040000000000)
1751	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_SHIFT 43
1752	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_MASK UINT64_C(0x0000080000000000)
1753	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_SHIFT 44
1754	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_MASK UINT64_C(0xfffff00000000000)
1755	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_VPID_CAP_, UINT64_C(0), UINT64_MAX,
1756	(RWX_X_ONLY, RSVD_1_5, PAGE_WALK_LENGTH_4, RSVD_7, EMT_UC, RSVD_9_13, EMT_WB, RSVD_15, PDE_2M,
1757	PDPTE_1G, RSVD_18_19, INVEPT, EPT_ACCESS_DIRTY, ADVEXITINFO_EPT, SSS, RSVD_24, INVEPT_SINGLE_CTX,
1758	INVEPT_ALL_CTX, RSVD_27_31, INVVPID, RSVD_33_39, INVVPID_INDIV_ADDR, INVVPID_SINGLE_CTX,
1759	INVVPID_ALL_CTX, INVVPID_SINGLE_CTX_RETAIN_GLOBALS, RSVD_44_63));
1760	/** @} */
1761
1762
1763	/** @name Extended Page Table Pointer (EPTP)
1764	* @{
1765	*/
1766	/** Uncachable EPT paging structure memory type. */
1767	#define VMX_EPT_MEMTYPE_UC 0
1768	/** Write-back EPT paging structure memory type. */
1769	#define VMX_EPT_MEMTYPE_WB 6
1770	/** Shift value to get the EPT page walk length (bits 5-3) */
1771	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1772	/** Mask value to get the EPT page walk length (bits 5-3) */
1773	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1774	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1775	* length) */
1776	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1777	/** @} */
1778
1779
1780	/** @name VMCS fields and encoding.
1781	*
1782	* When adding a new field:
1783	* - Always add it to g_aVmcsFields.
1784	* - Consider if it needs to be added to VMXVVMCS.
1785	* @{
1786	*/
1787	/** 16-bit control fields. */
1788	#define VMX_VMCS16_VPID 0x0000
1789	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1790	#define VMX_VMCS16_EPTP_INDEX 0x0004
1791
1792	/** 16-bit guest-state fields. */
1793	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1794	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1795	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1796	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1797	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1798	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1799	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1800	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1801	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1802	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1803
1804	/** 16-bits host-state fields. */
1805	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1806	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1807	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1808	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1809	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1810	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1811	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1812
1813	/** 64-bit control fields. */
1814	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1815	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1816	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1817	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1818	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1819	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1820	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1821	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1822	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1823	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1824	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1825	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1826	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1827	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1828	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1829	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1830	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1831	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1832	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1833	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1834	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1835	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1836	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1837	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1838	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1839	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1840	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1841	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1842	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1843	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1844	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1845	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1846	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1847	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1848	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1849	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1850	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1851	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1852	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1853	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1854	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1855	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1856	#define VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_FULL 0x202a
1857	#define VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_HIGH 0x202b
1858	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1859	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1860	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1861	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1862	#define VMX_VMCS64_CTRL_SPPTP_FULL 0x2030
1863	#define VMX_VMCS64_CTRL_SPPTP_HIGH 0x2031
1864	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1865	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1866	#define VMX_VMCS64_CTRL_PROC_EXEC3_FULL 0x2034
1867	#define VMX_VMCS64_CTRL_PROC_EXEC3_HIGH 0x2035
1868	#define VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_FULL 0x2036
1869	#define VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_HIGH 0x2037
1870
1871	/** 64-bit read-only data fields. */
1872	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1873	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1874
1875	/** 64-bit guest-state fields. */
1876	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1877	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1878	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1879	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1880	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1881	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1882	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1883	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1884	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1885	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1886	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1887	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1888	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1889	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1890	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1891	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1892	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1893	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1894	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1895	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1896	#define VMX_VMCS64_GUEST_RTIT_CTL_FULL 0x2814
1897	#define VMX_VMCS64_GUEST_RTIT_CTL_HIGH 0x2815
1898	#define VMX_VMCS64_GUEST_PKRS_FULL 0x2818
1899	#define VMX_VMCS64_GUEST_PKRS_HIGH 0x2819
1900
1901	/** 64-bit host-state fields. */
1902	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1903	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1904	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1905	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1906	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1907	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1908	#define VMX_VMCS64_HOST_PKRS_FULL 0x2c06
1909	#define VMX_VMCS64_HOST_PKRS_HIGH 0x2c07
1910
1911	/** 32-bit control fields. */
1912	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1913	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1914	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1915	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1916	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1917	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1918	#define VMX_VMCS32_CTRL_EXIT 0x400c
1919	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1920	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1921	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1922	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1923	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1924	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1925	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1926	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1927	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1928	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1929	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1930
1931	/** 32-bits read-only fields. */
1932	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1933	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1934	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1935	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1936	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1937	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1938	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1939	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1940
1941	/** 32-bit guest-state fields. */
1942	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1943	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1944	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1945	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1946	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1947	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1948	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1949	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1950	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1951	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1952	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1953	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1954	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1955	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1956	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1957	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1958	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1959	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1960	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1961	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1962	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1963	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
1964	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1965
1966	/** 32-bit host-state fields. */
1967	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1968
1969	/** Natural-width control fields. */
1970	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1971	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1972	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1973	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1974	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1975	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1976	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1977	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
1978
1979	/** Natural-width read-only data fields. */
1980	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1981	#define VMX_VMCS_RO_IO_RCX 0x6402
1982	#define VMX_VMCS_RO_IO_RSI 0x6404
1983	#define VMX_VMCS_RO_IO_RDI 0x6406
1984	#define VMX_VMCS_RO_IO_RIP 0x6408
1985	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
1986
1987	/** Natural-width guest-state fields. */
1988	#define VMX_VMCS_GUEST_CR0 0x6800
1989	#define VMX_VMCS_GUEST_CR3 0x6802
1990	#define VMX_VMCS_GUEST_CR4 0x6804
1991	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1992	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1993	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1994	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1995	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1996	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1997	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1998	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1999	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
2000	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
2001	#define VMX_VMCS_GUEST_DR7 0x681a
2002	#define VMX_VMCS_GUEST_RSP 0x681c
2003	#define VMX_VMCS_GUEST_RIP 0x681e
2004	#define VMX_VMCS_GUEST_RFLAGS 0x6820
2005	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
2006	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
2007	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
2008	#define VMX_VMCS_GUEST_S_CET 0x6828
2009	#define VMX_VMCS_GUEST_SSP 0x682a
2010	#define VMX_VMCS_GUEST_INTR_SSP_TABLE_ADDR 0x682c
2011
2012	/** Natural-width host-state fields. */
2013	#define VMX_VMCS_HOST_CR0 0x6c00
2014	#define VMX_VMCS_HOST_CR3 0x6c02
2015	#define VMX_VMCS_HOST_CR4 0x6c04
2016	#define VMX_VMCS_HOST_FS_BASE 0x6c06
2017	#define VMX_VMCS_HOST_GS_BASE 0x6c08
2018	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
2019	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
2020	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
2021	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
2022	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
2023	#define VMX_VMCS_HOST_RSP 0x6c14
2024	#define VMX_VMCS_HOST_RIP 0x6c16
2025	#define VMX_VMCS_HOST_S_CET 0x6c18
2026	#define VMX_VMCS_HOST_SSP 0x6c1a
2027	#define VMX_VMCS_HOST_INTR_SSP_TABLE_ADDR 0x6c1c
2028
2029	#define VMX_VMCS16_GUEST_SEG_SEL(a_iSegReg) (VMX_VMCS16_GUEST_ES_SEL + (a_iSegReg) * 2)
2030	#define VMX_VMCS_GUEST_SEG_BASE(a_iSegReg) (VMX_VMCS_GUEST_ES_BASE + (a_iSegReg) * 2)
2031	#define VMX_VMCS32_GUEST_SEG_LIMIT(a_iSegReg) (VMX_VMCS32_GUEST_ES_LIMIT + (a_iSegReg) * 2)
2032	#define VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(a_iSegReg) (VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS + (a_iSegReg) * 2)
2033
2034	/**
2035	* VMCS field.
2036	* In accordance with the VT-x spec.
2037	*/
2038	typedef union
2039	{
2040	struct
2041	{
2042	/** The access type; 0=full, 1=high of 64-bit fields. */
2043	uint32_t fAccessType : 1;
2044	/** The index. */
2045	uint32_t u8Index : 8;
2046	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
2047	uint32_t u2Type : 2;
2048	/** Reserved (MBZ). */
2049	uint32_t u1Reserved0 : 1;
2050	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
2051	uint32_t u2Width : 2;
2052	/** Reserved (MBZ). */
2053	uint32_t u18Reserved0 : 18;
2054	} n;
2055
2056	/* The unsigned integer view. */
2057	uint32_t u;
2058	} VMXVMCSFIELD;
2059	AssertCompileSize(VMXVMCSFIELD, 4);
2060	/** Pointer to a VMCS field. */
2061	typedef VMXVMCSFIELD *PVMXVMCSFIELD;
2062	/** Pointer to a const VMCS field. */
2063	typedef const VMXVMCSFIELD *PCVMXVMCSFIELD;
2064
2065	/** VMCS field: Mask of reserved bits (bits 63:15 MBZ), bit 12 is not included! */
2066	#define VMX_VMCSFIELD_RSVD_MASK UINT64_C(0xffffffffffff8000)
2067
2068	/** Bits fields for a VMCS field. */
2069	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_SHIFT 0
2070	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2071	#define VMX_BF_VMCSFIELD_INDEX_SHIFT 1
2072	#define VMX_BF_VMCSFIELD_INDEX_MASK UINT32_C(0x000003fe)
2073	#define VMX_BF_VMCSFIELD_TYPE_SHIFT 10
2074	#define VMX_BF_VMCSFIELD_TYPE_MASK UINT32_C(0x00000c00)
2075	#define VMX_BF_VMCSFIELD_RSVD_12_SHIFT 12
2076	#define VMX_BF_VMCSFIELD_RSVD_12_MASK UINT32_C(0x00001000)
2077	#define VMX_BF_VMCSFIELD_WIDTH_SHIFT 13
2078	#define VMX_BF_VMCSFIELD_WIDTH_MASK UINT32_C(0x00006000)
2079	#define VMX_BF_VMCSFIELD_RSVD_15_31_SHIFT 15
2080	#define VMX_BF_VMCSFIELD_RSVD_15_31_MASK UINT32_C(0xffff8000)
2081	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCSFIELD_, UINT32_C(0), UINT32_MAX,
2082	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2083
2084	/**
2085	* VMCS field encoding: Access type.
2086	* In accordance with the VT-x spec.
2087	*/
2088	typedef enum
2089	{
2090	VMXVMCSFIELDACCESS_FULL = 0,
2091	VMXVMCSFIELDACCESS_HIGH
2092	} VMXVMCSFIELDACCESS;
2093	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
2094	/** VMCS field encoding type: Full. */
2095	#define VMX_VMCSFIELD_ACCESS_FULL 0
2096	/** VMCS field encoding type: High. */
2097	#define VMX_VMCSFIELD_ACCESS_HIGH 1
2098
2099	/**
2100	* VMCS field encoding: Type.
2101	* In accordance with the VT-x spec.
2102	*/
2103	typedef enum
2104	{
2105	VMXVMCSFIELDTYPE_CONTROL = 0,
2106	VMXVMCSFIELDTYPE_VMEXIT_INFO,
2107	VMXVMCSFIELDTYPE_GUEST_STATE,
2108	VMXVMCSFIELDTYPE_HOST_STATE
2109	} VMXVMCSFIELDTYPE;
2110	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
2111	/** VMCS field encoding type: Control. */
2112	#define VMX_VMCSFIELD_TYPE_CONTROL 0
2113	/** VMCS field encoding type: VM-exit information / read-only fields. */
2114	#define VMX_VMCSFIELD_TYPE_VMEXIT_INFO 1
2115	/** VMCS field encoding type: Guest-state. */
2116	#define VMX_VMCSFIELD_TYPE_GUEST_STATE 2
2117	/** VMCS field encoding type: Host-state. */
2118	#define VMX_VMCSFIELD_TYPE_HOST_STATE 3
2119
2120	/**
2121	* VMCS field encoding: Width.
2122	* In accordance with the VT-x spec.
2123	*/
2124	typedef enum
2125	{
2126	VMXVMCSFIELDWIDTH_16BIT = 0,
2127	VMXVMCSFIELDWIDTH_64BIT,
2128	VMXVMCSFIELDWIDTH_32BIT,
2129	VMXVMCSFIELDWIDTH_NATURAL
2130	} VMXVMCSFIELDWIDTH;
2131	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
2132	/** VMCS field encoding width: 16-bit. */
2133	#define VMX_VMCSFIELD_WIDTH_16BIT 0
2134	/** VMCS field encoding width: 64-bit. */
2135	#define VMX_VMCSFIELD_WIDTH_64BIT 1
2136	/** VMCS field encoding width: 32-bit. */
2137	#define VMX_VMCSFIELD_WIDTH_32BIT 2
2138	/** VMCS field encoding width: Natural width. */
2139	#define VMX_VMCSFIELD_WIDTH_NATURAL 3
2140	/** @} */
2141
2142
2143	/** @name VM-entry instruction length.
2144	* @{ */
2145	/** The maximum valid value for VM-entry instruction length while injecting a
2146	* software interrupt, software exception or privileged software exception. */
2147	#define VMX_ENTRY_INSTR_LEN_MAX 15
2148	/** @} */
2149
2150
2151	/** @name VM-entry register masks.
2152	* @{ */
2153	/** CR0 bits ignored on VM-entry while loading guest CR0 (ET, CD, NW, bits 6:15,
2154	* bit 17 and bits 19:28). */
2155	#define VMX_ENTRY_GUEST_CR0_IGNORE_MASK UINT64_C(0x7ffaffd0)
2156	/** DR7 bits set here are always cleared on VM-entry while loading guest DR7 (bit
2157	* 12, bits 14:15). */
2158	#define VMX_ENTRY_GUEST_DR7_MBZ_MASK UINT64_C(0xd000)
2159	/** DR7 bits set here are always set on VM-entry while loading guest DR7 (bit
2160	* 10). */
2161	#define VMX_ENTRY_GUEST_DR7_MB1_MASK UINT64_C(0x400)
2162	/** @} */
2163
2164
2165	/** @name VM-exit register masks.
2166	* @{ */
2167	/** CR0 bits ignored on VM-exit while loading host CR0 (ET, CD, NW, bits 6:15,
2168	* bit 17, bits 19:28 and bits 32:63). */
2169	#define VMX_EXIT_HOST_CR0_IGNORE_MASK UINT64_C(0xffffffff7ffaffd0)
2170	/** @} */
2171
2172
2173	/** @name Pin-based VM-execution controls.
2174	* @{
2175	*/
2176	/** External interrupt exiting. */
2177	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
2178	/** NMI exiting. */
2179	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
2180	/** Virtual NMIs. */
2181	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
2182	/** Activate VMX preemption timer. */
2183	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
2184	/** Process interrupts with the posted-interrupt notification vector. */
2185	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
2186	/** Default1 class when true capability MSRs are not supported. */
2187	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
2188
2189	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
2190	* controls field in the VMCS. */
2191	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
2192	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
2193	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
2194	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
2195	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
2196	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
2197	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
2198	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
2199	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
2200	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
2201	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
2202	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
2203	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
2204	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
2205	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
2206	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
2207	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
2208	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
2209	/** @} */
2210
2211
2212	/** @name Processor-based VM-execution controls.
2213	* @{
2214	*/
2215	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
2216	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
2217	/** Use timestamp counter offset. */
2218	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
2219	/** VM-exit when executing the HLT instruction. */
2220	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
2221	/** VM-exit when executing the INVLPG instruction. */
2222	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
2223	/** VM-exit when executing the MWAIT instruction. */
2224	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
2225	/** VM-exit when executing the RDPMC instruction. */
2226	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
2227	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
2228	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
2229	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
2230	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2231	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
2232	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
2233	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2234	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
2235	/** VM-exit on CR8 loads. */
2236	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
2237	/** VM-exit on CR8 stores. */
2238	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
2239	/** Use TPR shadow. */
2240	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
2241	/** VM-exit when virtual NMI blocking is disabled. */
2242	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
2243	/** VM-exit when executing a MOV DRx instruction. */
2244	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
2245	/** VM-exit when executing IO instructions. */
2246	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
2247	/** Use IO bitmaps. */
2248	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
2249	/** Monitor trap flag. */
2250	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2251	/** Use MSR bitmaps. */
2252	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2253	/** VM-exit when executing the MONITOR instruction. */
2254	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2255	/** VM-exit when executing the PAUSE instruction. */
2256	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2257	/** Whether the secondary processor based VM-execution controls are used. */
2258	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2259	/** Default1 class when true-capability MSRs are not supported. */
2260	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2261
2262	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2263	* controls field in the VMCS. */
2264	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
2265	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2266	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2267	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2268	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2269	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2270	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
2271	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
2272	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2273	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2274	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
2275	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
2276	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2277	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2278	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2279	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2280	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2281	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2282	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2283	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2284	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
2285	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2286	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2287	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2288	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2289	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2290	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
2291	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
2292	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2293	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2294	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2295	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2296	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2297	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2298	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2299	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2300	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2301	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2302	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2303	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2304	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2305	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2306	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
2307	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
2308	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2309	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2310	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2311	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2312	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2313	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2314	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2315	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2316	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2317	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2318	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2319	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
2320	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
2321	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2322	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2323	USE_SECONDARY_CTLS));
2324	/** @} */
2325
2326
2327	/** @name Secondary Processor-based VM-execution controls.
2328	* @{
2329	*/
2330	/** Virtualize APIC accesses. */
2331	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2332	/** EPT supported/enabled. */
2333	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2334	/** Descriptor table instructions cause VM-exits. */
2335	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2336	/** RDTSCP supported/enabled. */
2337	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2338	/** Virtualize x2APIC mode. */
2339	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2340	/** VPID supported/enabled. */
2341	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2342	/** VM-exit when executing the WBINVD instruction. */
2343	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2344	/** Unrestricted guest execution. */
2345	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2346	/** APIC register virtualization. */
2347	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2348	/** Virtual-interrupt delivery. */
2349	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2350	/** A specified number of pause loops cause a VM-exit. */
2351	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2352	/** VM-exit when executing RDRAND instructions. */
2353	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2354	/** Enables INVPCID instructions. */
2355	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2356	/** Enables VMFUNC instructions. */
2357	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2358	/** Enables VMCS shadowing. */
2359	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2360	/** Enables ENCLS VM-exits. */
2361	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2362	/** VM-exit when executing RDSEED. */
2363	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2364	/** Enables page-modification logging. */
2365	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2366	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2367	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
2368	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2369	#define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19)
2370	/** Enables XSAVES/XRSTORS instructions. */
2371	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2372	/** Enables supervisor/user mode based EPT execute permission for linear
2373	* addresses. */
2374	#define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22)
2375	/** Enables EPT permissions to be specified at granularity of 128 bytes. */
2376	#define VMX_PROC_CTLS2_SPPTP_EPT RT_BIT(23)
2377	/** Intel PT output addresses are treated as guest-physical addresses and
2378	* translated using EPT. */
2379	#define VMX_PROC_CTLS2_PT_EPT RT_BIT(24)
2380	/** Use TSC scaling. */
2381	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2382	/** Enables TPAUSE, UMONITOR and UMWAIT instructions. */
2383	#define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26)
2384	/** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */
2385	#define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28)
2386
2387	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2388	* VM-execution controls field in the VMCS. */
2389	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2390	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2391	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2392	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2393	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2394	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2395	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2396	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2397	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2398	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2399	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2400	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2401	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2402	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2403	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2404	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2405	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2406	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2407	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2408	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2409	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2410	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2411	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2412	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2413	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2414	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2415	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2416	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2417	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2418	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2419	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2420	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2421	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2422	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2423	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2424	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2425	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2426	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2427	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19
2428	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000)
2429	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2430	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2431	#define VMX_BF_PROC_CTLS2_UNDEF_21_SHIFT 21
2432	#define VMX_BF_PROC_CTLS2_UNDEF_21_MASK UINT32_C(0x00200000)
2433	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22
2434	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000)
2435	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_SHIFT 23
2436	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_MASK UINT32_C(0x00800000)
2437	#define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24
2438	#define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000)
2439	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2440	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2441	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26
2442	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000)
2443	#define VMX_BF_PROC_CTLS2_UNDEF_27_SHIFT 27
2444	#define VMX_BF_PROC_CTLS2_UNDEF_27_MASK UINT32_C(0x08000000)
2445	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28
2446	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000)
2447	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_SHIFT 29
2448	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_MASK UINT32_C(0xe0000000)
2449
2450	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2451	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2452	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2453	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, UNDEF_21,
2454	MODE_BASED_EPT_PERM, SPPTP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, UNDEF_27, ENCLV_EXIT,
2455	UNDEF_29_31));
2456	/** @} */
2457
2458
2459	/** @name VM-entry controls.
2460	* @{
2461	*/
2462	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2463	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2464	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2465	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2466	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2467	/** In SMM mode after VM-entry. */
2468	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2469	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2470	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2471	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2472	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2473	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2474	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2475	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2476	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2477	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2478	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2479	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2480	#define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17)
2481	/** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
2482	#define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18)
2483	/** Whether the guest CET-related MSRs and SPP are loaded on VM-entry. */
2484	#define VMX_ENTRY_CTLS_LOAD_CET_STATE RT_BIT(20)
2485	/** Default1 class when true-capability MSRs are not supported. */
2486	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2487
2488	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2489	* VMCS. */
2490	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2491	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2492	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2493	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2494	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2495	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2496	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2497	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2498	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2499	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2500	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2501	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2502	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2503	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2504	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2505	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2506	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2507	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2508	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2509	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2510	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2511	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2512	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17
2513	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000)
2514	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18
2515	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000)
2516	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_SHIFT 19
2517	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_MASK UINT32_C(0xfff80000)
2518	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2519	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2520	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
2521	LOAD_RTIT_CTL_MSR, UNDEF_19_31));
2522	/** @} */
2523
2524
2525	/** @name VM-exit controls.
2526	* @{
2527	*/
2528	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2529	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2530	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2531	/** Return to long mode after a VM-exit. */
2532	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2533	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2534	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2535	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2536	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2537	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2538	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2539	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2540	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2541	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2542	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2543	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2544	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2545	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2546	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2547	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2548	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2549	/** Whether to conceal VMX from Intel PT. */
2550	#define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24)
2551	/** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
2552	#define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25)
2553	/** Whether CET-related MSRs and SPP are loaded on VM-exit. */
2554	#define VMX_EXIT_CTLS_LOAD_CET_STATE RT_BIT(28)
2555	/** Default1 class when true-capability MSRs are not supported. */
2556	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2557
2558	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2559	* VMCS. */
2560	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2561	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2562	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2563	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2564	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2565	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2566	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2567	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2568	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2569	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2570	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2571	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2572	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2573	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2574	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2575	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2576	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2577	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2578	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2579	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2580	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2581	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2582	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2583	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2584	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2585	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2586	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2587	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2588	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23
2589	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000)
2590	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24
2591	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000)
2592	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25
2593	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000)
2594	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_SHIFT 26
2595	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2596	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2597	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2598	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2599	SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, UNDEF_26_31));
2600	/** @} */
2601
2602
2603	/** @name VM-exit reason.
2604	* @{
2605	*/
2606	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2607	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2608	#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2609
2610	/** Bit fields for VM-exit reason. */
2611	/** The exit reason. */
2612	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2613	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2614	/** Bits 16:26 are reseved and MBZ. */
2615	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2616	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2617	/** Whether the VM-exit was incident to enclave mode. */
2618	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2619	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2620	/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2621	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2622	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2623	/** VM-exit from VMX root operation (only possible with SMM). */
2624	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2625	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2626	/** Bit 30 is reserved and MBZ. */
2627	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2628	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2629	/** Whether VM-entry failed (currently only happens during loading guest-state
2630	* or MSRs or machine check exceptions). */
2631	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2632	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2633	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2634	(BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2635	/** @} */
2636
2637
2638	/** @name VM-entry interruption information.
2639	* @{
2640	*/
2641	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2642	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2643	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2644	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2645	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2646	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2647	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2648	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2649	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2650	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2651	/** Construct an VM-entry interruption information field from a VM-exit interruption
2652	* info value (same except that bit 12 is reserved). */
2653	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2654	/** Construct a VM-entry interruption information field from an IDT-vectoring
2655	* information field (same except that bit 12 is reserved). */
2656	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2657	/** If the VM-entry interruption information field indicates a page-fault. */
2658	#define VMX_ENTRY_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2659	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2660	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2661	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2662	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT) \
2663	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_PF)))
2664	/** If the VM-entry interruption information field indicates an external
2665	* interrupt. */
2666	#define VMX_ENTRY_INT_INFO_IS_EXT_INT(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2667	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK)) \
2668	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2669	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_EXT_INT)))
2670	/** If the VM-entry interruption information field indicates an NMI. */
2671	#define VMX_ENTRY_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2672	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2673	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2674	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2675	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_NMI) \
2676	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_NMI)))
2677
2678	/** Bit fields for VM-entry interruption information. */
2679	/** The VM-entry interruption vector. */
2680	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2681	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2682	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2683	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2684	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2685	/** Whether this event has an error code. */
2686	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2687	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2688	/** Bits 12:30 are reserved and MBZ. */
2689	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2690	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2691	/** Whether this VM-entry interruption info is valid. */
2692	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2693	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2694	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2695	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2696	/** @} */
2697
2698
2699	/** @name VM-entry exception error code.
2700	* @{ */
2701	/** Error code valid mask. */
2702	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2703	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2704	* stack aligned for doubleword pushes, the upper half of the error code is
2705	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2706	* use below. */
2707	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2708	/** @} */
2709
2710	/** @name VM-entry interruption information types.
2711	* @{
2712	*/
2713	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2714	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2715	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2716	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2717	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2718	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2719	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2720	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2721	/** @} */
2722
2723
2724	/** @name VM-entry interruption information vector types for
2725	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2726	* @{ */
2727	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2728	/** @} */
2729
2730
2731	/** @name VM-exit interruption information.
2732	* @{
2733	*/
2734	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2735	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2736	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2737	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2738	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2739	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2740	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2741	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2742	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2743
2744	/** If the VM-exit interruption information field indicates an page-fault. */
2745	#define VMX_EXIT_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2746	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2747	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2748	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2749	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2750	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_PF)))
2751	/** If the VM-exit interruption information field indicates an double-fault. */
2752	#define VMX_EXIT_INT_INFO_IS_XCPT_DF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2753	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2754	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2755	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2756	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2757	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)))
2758	/** If the VM-exit interruption information field indicates an NMI. */
2759	#define VMX_EXIT_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2760	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2761	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2762	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2763	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI) \
2764	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI)))
2765
2766
2767	/** Bit fields for VM-exit interruption infomration. */
2768	/** The VM-exit interruption vector. */
2769	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2770	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2771	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2772	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2773	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2774	/** Whether this event has an error code. */
2775	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2776	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2777	/** Whether NMI-unblocking due to IRET is active. */
2778	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2779	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2780	/** Bits 13:30 is reserved (MBZ). */
2781	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2782	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2783	/** Whether this VM-exit interruption info is valid. */
2784	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2785	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2786	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2787	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2788	/** @} */
2789
2790
2791	/** @name VM-exit interruption information types.
2792	* @{
2793	*/
2794	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2795	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2796	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2797	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2798	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2799	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2800	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2801	/** @} */
2802
2803
2804	/** @name VM-exit instruction identity.
2805	*
2806	* These are found in VM-exit instruction information fields for certain
2807	* instructions.
2808	* @{ */
2809	typedef uint32_t VMXINSTRID;
2810	/** Whether the instruction ID field is valid. */
2811	#define VMXINSTRID_VALID RT_BIT_32(31)
2812	/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
2813	* read or write. */
2814	#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
2815	/** Gets whether the instruction ID is valid or not. */
2816	#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
2817	#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
2818	/** Gets the instruction ID. */
2819	#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W))
2820	/** No instruction ID info. */
2821	#define VMXINSTRID_NONE 0
2822
2823	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2824	#define VMXINSTRID_SGDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2825	#define VMXINSTRID_SIDT (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2826	#define VMXINSTRID_LGDT (0x2 \| VMXINSTRID_VALID)
2827	#define VMXINSTRID_LIDT (0x3 \| VMXINSTRID_VALID)
2828
2829	#define VMXINSTRID_SLDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2830	#define VMXINSTRID_STR (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2831	#define VMXINSTRID_LLDT (0x2 \| VMXINSTRID_VALID)
2832	#define VMXINSTRID_LTR (0x3 \| VMXINSTRID_VALID)
2833
2834	/** The following IDs are used internally (some for logging, others for conveying
2835	* the ModR/M primary operand write bit): */
2836	#define VMXINSTRID_VMLAUNCH (0x10 \| VMXINSTRID_VALID)
2837	#define VMXINSTRID_VMRESUME (0x11 \| VMXINSTRID_VALID)
2838	#define VMXINSTRID_VMREAD (0x12 \| VMXINSTRID_VALID)
2839	#define VMXINSTRID_VMWRITE (0x13 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2840	#define VMXINSTRID_IO_IN (0x14 \| VMXINSTRID_VALID)
2841	#define VMXINSTRID_IO_INS (0x15 \| VMXINSTRID_VALID)
2842	#define VMXINSTRID_IO_OUT (0x16 \| VMXINSTRID_VALID)
2843	#define VMXINSTRID_IO_OUTS (0x17 \| VMXINSTRID_VALID)
2844	#define VMXINSTRID_MOV_TO_DRX (0x18 \| VMXINSTRID_VALID)
2845	#define VMXINSTRID_MOV_FROM_DRX (0x19 \| VMXINSTRID_VALID)
2846	/** @} */
2847
2848
2849	/** @name IDT-vectoring information.
2850	* @{
2851	*/
2852	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2853	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
2854	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2855	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
2856	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2857	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2858	#define VMX_IDT_VECTORING_INFO_VALID RT_BIT(31)
2859
2860	/** Construct an IDT-vectoring information field from an VM-entry interruption
2861	* information field (same except that bit 12 is reserved). */
2862	#define VMX_IDT_VECTORING_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
2863	/** If the IDT-vectoring information field indicates a page-fault. */
2864	#define VMX_IDT_VECTORING_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
2865	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
2866	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
2867	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
2868	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT) \
2869	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_PF)))
2870	/** If the IDT-vectoring information field indicates an NMI. */
2871	#define VMX_IDT_VECTORING_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
2872	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
2873	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
2874	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
2875	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_NMI) \
2876	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_NMI)))
2877
2878
2879	/** Bit fields for IDT-vectoring information. */
2880	/** The IDT-vectoring info vector. */
2881	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2882	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2883	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
2884	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2885	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2886	/** Whether the event has an error code. */
2887	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2888	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2889	/** Bit 12 is undefined. */
2890	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2891	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2892	/** Bits 13:30 is reserved (MBZ). */
2893	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2894	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2895	/** Whether this IDT-vectoring info is valid. */
2896	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2897	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2898	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2899	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2900	/** @} */
2901
2902
2903	/** @name IDT-vectoring information vector types.
2904	* @{
2905	*/
2906	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2907	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2908	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2909	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2910	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2911	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2912	#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
2913	/** @} */
2914
2915
2916	/** @name TPR threshold.
2917	* @{ */
2918	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
2919	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
2920
2921	/** Bit fields for TPR threshold. */
2922	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
2923	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
2924	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
2925	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
2926	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
2927	(TPR, RSVD_4_31));
2928	/** @} */
2929
2930
2931	/** @name Guest-activity states.
2932	* @{
2933	*/
2934	/** The logical processor is active. */
2935	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2936	/** The logical processor is inactive, because it executed a HLT instruction. */
2937	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2938	/** The logical processor is inactive, because of a triple fault or other serious error. */
2939	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2940	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2941	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2942	/** @} */
2943
2944
2945	/** @name Guest-interruptibility states.
2946	* @{
2947	*/
2948	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2949	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2950	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2951	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2952	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
2953
2954	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
2955	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
2956	/** @} */
2957
2958
2959	/** @name Exit qualification for debug exceptions.
2960	* @{
2961	*/
2962	/** Hardware breakpoint 0 was met. */
2963	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
2964	/** Hardware breakpoint 1 was met. */
2965	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
2966	/** Hardware breakpoint 2 was met. */
2967	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
2968	/** Hardware breakpoint 3 was met. */
2969	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
2970	/** Debug register access detected. */
2971	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
2972	/** A debug exception would have been triggered by single-step execution mode. */
2973	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
2974	/** Mask of all valid bits. */
2975	#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
2976	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
2977	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
2978	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
2979	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
2980	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
2981
2982	/** Bit fields for Exit qualifications due to debug exceptions. */
2983	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
2984	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
2985	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
2986	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
2987	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
2988	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
2989	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
2990	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
2991	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
2992	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
2993	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
2994	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
2995	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
2996	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
2997	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
2998	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
2999	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
3000	(BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
3001	/** @} */
3002
3003	/** @name Exit qualification for Mov DRx.
3004	* @{
3005	*/
3006	/** 0-2: Debug register number */
3007	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
3008	/** 3: Reserved; cleared to 0. */
3009	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
3010	/** 4: Direction of move (0 = write, 1 = read) */
3011	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
3012	/** 5-7: Reserved; cleared to 0. */
3013	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
3014	/** 8-11: General purpose register number. */
3015	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
3016
3017	/** Bit fields for Exit qualification due to Mov DRx. */
3018	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
3019	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
3020	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
3021	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
3022	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
3023	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
3024	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
3025	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
3026	#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
3027	#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3028	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
3029	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
3030	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
3031	(REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
3032	/** @} */
3033
3034
3035	/** @name Exit qualification for debug exceptions types.
3036	* @{
3037	*/
3038	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
3039	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
3040	/** @} */
3041
3042
3043	/** @name Exit qualification for control-register accesses.
3044	* @{
3045	*/
3046	/** 0-3: Control register number (0 for CLTS & LMSW) */
3047	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
3048	/** 4-5: Access type. */
3049	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
3050	/** 6: LMSW operand type memory (1 for memory, 0 for register). */
3051	#define VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(a) (((a) >> 6) & 1)
3052	/** 7: Reserved; cleared to 0. */
3053	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
3054	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
3055	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
3056	/** 12-15: Reserved; cleared to 0. */
3057	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
3058	/** 16-31: LMSW source data (else 0). */
3059	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
3060
3061	/** Bit fields for Exit qualification for control-register accesses. */
3062	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
3063	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
3064	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
3065	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
3066	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
3067	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
3068	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
3069	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
3070	#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
3071	#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3072	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
3073	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
3074	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
3075	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
3076	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
3077	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3078	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
3079	(REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
3080	/** @} */
3081
3082
3083	/** @name Exit qualification for control-register access types.
3084	* @{
3085	*/
3086	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
3087	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
3088	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
3089	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
3090	/** @} */
3091
3092
3093	/** @name Exit qualification for task switch.
3094	* @{
3095	*/
3096	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
3097	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
3098	/** Task switch caused by a call instruction. */
3099	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
3100	/** Task switch caused by an iret instruction. */
3101	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
3102	/** Task switch caused by a jmp instruction. */
3103	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
3104	/** Task switch caused by an interrupt gate. */
3105	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
3106
3107	/** Bit fields for Exit qualification for task switches. */
3108	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
3109	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
3110	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
3111	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
3112	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
3113	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
3114	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
3115	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3116	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
3117	(NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
3118	/** @} */
3119
3120
3121	/** @name Exit qualification for EPT violations.
3122	* @{
3123	*/
3124	/** Set if the violation was caused by a data read. */
3125	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
3126	/** Set if the violation was caused by a data write. */
3127	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
3128	/** Set if the violation was caused by an instruction fetch. */
3129	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
3130	/** AND of the present bit of all EPT structures. */
3131	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
3132	/** AND of the write bit of all EPT structures. */
3133	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
3134	/** AND of the execute bit of all EPT structures. */
3135	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
3136	/** Set if the guest linear address field contains the faulting address. */
3137	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
3138	/** If bit 7 is one: (reserved otherwise)
3139	* 1 - violation due to physical address access.
3140	* 0 - violation caused by page walk or access/dirty bit updates
3141	*/
3142	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
3143	/** NMI unblocking due to IRET. */
3144	#define VMX_EXIT_QUAL_EPT_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
3145	/** @} */
3146
3147
3148	/** @name Exit qualification for I/O instructions.
3149	* @{
3150	*/
3151	/** 0-2: IO operation size 0(=1 byte), 1(=2 bytes) and 3(=4 bytes). */
3152	#define VMX_EXIT_QUAL_IO_SIZE(a) ((a) & 7)
3153	/** 3: IO operation direction. */
3154	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
3155	/** 4: String IO operation (INS / OUTS). */
3156	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
3157	/** 5: Repeated IO operation. */
3158	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
3159	/** 6: Operand encoding. */
3160	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
3161	/** 16-31: IO Port (0-0xffff). */
3162	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
3163
3164	/** Bit fields for Exit qualification for I/O instructions. */
3165	#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
3166	#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
3167	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
3168	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
3169	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
3170	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
3171	#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
3172	#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
3173	#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
3174	#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
3175	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
3176	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
3177	#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
3178	#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
3179	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
3180	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3181	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
3182	(WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
3183	/** @} */
3184
3185
3186	/** @name Exit qualification for I/O instruction types.
3187	* @{
3188	*/
3189	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
3190	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
3191	/** @} */
3192
3193
3194	/** @name Exit qualification for I/O instruction encoding.
3195	* @{
3196	*/
3197	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
3198	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
3199	/** @} */
3200
3201
3202	/** @name Exit qualification for APIC-access VM-exits from linear and
3203	* guest-physical accesses.
3204	* @{
3205	*/
3206	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
3207	* access within the APIC page. */
3208	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
3209	/** 12-15: Access type. */
3210	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
3211	/* Rest reserved. */
3212
3213	/** Bit fields for Exit qualification for APIC-access VM-exits. */
3214	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
3215	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
3216	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
3217	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
3218	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
3219	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
3220	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
3221	(OFFSET, TYPE, RSVD_16_63));
3222	/** @} */
3223
3224
3225	/** @name Exit qualification for linear address APIC-access types.
3226	* @{
3227	*/
3228	/** Linear access for a data read during instruction execution. */
3229	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
3230	/** Linear access for a data write during instruction execution. */
3231	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
3232	/** Linear access for an instruction fetch. */
3233	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
3234	/** Linear read/write access during event delivery. */
3235	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
3236	/** Physical read/write access during event delivery. */
3237	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
3238	/** Physical access for an instruction fetch or during instruction execution. */
3239	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
3240
3241	/**
3242	* APIC-access type.
3243	* In accordance with the VT-x spec.
3244	*/
3245	typedef enum
3246	{
3247	VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
3248	VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
3249	VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
3250	VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
3251	VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
3252	VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
3253	} VMXAPICACCESS;
3254	AssertCompileSize(VMXAPICACCESS, 4);
3255	/** @} */
3256
3257
3258	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
3259	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3260	* @{
3261	*/
3262	/** Address calculation scaling field (powers of two). */
3263	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
3264	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3265	/** Bits 2 thru 6 are undefined. */
3266	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
3267	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
3268	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3269	* @remarks anyone's guess why this is a 3 bit field... */
3270	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
3271	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3272	/** Bit 10 is defined as zero. */
3273	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
3274	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
3275	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
3276	* for exits from 64-bit code as the operand size there is fixed. */
3277	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
3278	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
3279	/** Bits 12 thru 14 are undefined. */
3280	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
3281	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
3282	/** Applicable segment register (X86_SREG_XXX values). */
3283	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
3284	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3285	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3286	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
3287	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3288	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3289	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3290	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3291	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3292	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
3293	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3294	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3295	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
3296	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3297	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
3298	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
3299	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3300	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
3301	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
3302	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
3303	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
3304	/** Bits 30 & 31 are undefined. */
3305	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
3306	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3307	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3308	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
3309	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3310	/** @} */
3311
3312
3313	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
3314	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3315	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
3316	* @{
3317	*/
3318	/** Address calculation scaling field (powers of two). */
3319	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
3320	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3321	/** Bit 2 is undefined. */
3322	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
3323	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
3324	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
3325	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
3326	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
3327	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3328	* @remarks anyone's guess why this is a 3 bit field... */
3329	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
3330	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3331	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
3332	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
3333	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
3334	/** Bits 11 thru 14 are undefined. */
3335	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
3336	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
3337	/** Applicable segment register (X86_SREG_XXX values). */
3338	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
3339	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3340	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3341	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
3342	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3343	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3344	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3345	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3346	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3347	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
3348	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3349	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3350	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
3351	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3352	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
3353	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
3354	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3355	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
3356	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
3357	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
3358	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
3359	/** Bits 30 & 31 are undefined. */
3360	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3361	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3362	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3363	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3364	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3365	/** @} */
3366
3367
3368	/** @name Format of Pending-Debug-Exceptions.
3369	* Bits 4-11, 13, 15 and 17-63 are reserved.
3370	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3371	* possibly valid here but not in DR6.
3372	* @{
3373	*/
3374	/** Hardware breakpoint 0 was met. */
3375	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3376	/** Hardware breakpoint 1 was met. */
3377	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3378	/** Hardware breakpoint 2 was met. */
3379	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3380	/** Hardware breakpoint 3 was met. */
3381	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3382	/** At least one data or IO breakpoint was hit. */
3383	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3384	/** A debug exception would have been triggered by single-step execution mode. */
3385	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3386	/** A debug exception occurred inside an RTM region. */
3387	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3388	/** Mask of valid bits. */
3389	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3390	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3391	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3392	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3393	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3394	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3395	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3396	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3397	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3398	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3399	/** Bit fields for Pending debug exceptions. */
3400	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3401	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3402	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3403	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3404	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3405	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3406	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3407	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3408	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3409	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3410	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3411	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3412	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3413	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3414	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3415	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3416	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3417	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3418	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3419	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3420	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3421	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3422	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3423	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3424	/** @} */
3425
3426
3427	/** @defgroup grp_hm_vmx_virt VMX virtualization.
3428	* @{
3429	*/
3430
3431	/** @name Virtual VMX MSR - Miscellaneous data.
3432	* @{ */
3433	/** Number of CR3-target values supported. */
3434	#define VMX_V_CR3_TARGET_COUNT 4
3435	/** Activity states supported. */
3436	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3437	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3438	#define VMX_V_PREEMPT_TIMER_SHIFT 5
3439	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3440	#define VMX_V_AUTOMSR_COUNT_MAX 0
3441	/** SMM MSEG revision ID. */
3442	#define VMX_V_MSEG_REV_ID 0
3443	/** @} */
3444
3445	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS launch state.
3446	* @{ */
3447	/** VMCS launch state clear. */
3448	#define VMX_V_VMCS_LAUNCH_STATE_CLEAR RT_BIT(0)
3449	/** VMCS launch state active. */
3450	#define VMX_V_VMCS_LAUNCH_STATE_ACTIVE RT_BIT(1)
3451	/** VMCS launch state current. */
3452	#define VMX_V_VMCS_LAUNCH_STATE_CURRENT RT_BIT(2)
3453	/** VMCS launch state launched. */
3454	#define VMX_V_VMCS_LAUNCH_STATE_LAUNCHED RT_BIT(3)
3455	/** The mask of valid VMCS launch states. */
3456	#define VMX_V_VMCS_LAUNCH_STATE_MASK ( VMX_V_VMCS_LAUNCH_STATE_CLEAR \
3457	\| VMX_V_VMCS_LAUNCH_STATE_ACTIVE \
3458	\| VMX_V_VMCS_LAUNCH_STATE_CURRENT \
3459	\| VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
3460	/** @} */
3461
3462	/** CR0 bits set here must always be set when in VMX operation. */
3463	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
3464	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
3465	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
3466	/** CR4 bits set here must always be set when in VMX operation. */
3467	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3468
3469	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3470	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3471	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001)
3472	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3473
3474	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3475	* complications when teleporation may be implemented). */
3476	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3477	/** The size of the virtual VMCS region (in pages). */
3478	#define VMX_V_VMCS_PAGES 1
3479
3480	/** The size of the virtual shadow VMCS region. */
3481	#define VMX_V_SHADOW_VMCS_SIZE VMX_V_VMCS_SIZE
3482	/** The size of the virtual shadow VMCS region (in pages). */
3483	#define VMX_V_SHADOW_VMCS_PAGES VMX_V_VMCS_PAGES
3484
3485	/** The size of the Virtual-APIC page (in bytes). */
3486	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3487	/** The size of the Virtual-APIC page (in pages). */
3488	#define VMX_V_VIRT_APIC_PAGES 1
3489
3490	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3491	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3492	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3493	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3494
3495	/** The size of the MSR bitmap (in bytes). */
3496	#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3497	/** The size of the MSR bitmap (in pages). */
3498	#define VMX_V_MSR_BITMAP_PAGES 1
3499
3500	/** The size of I/O bitmap A (in bytes). */
3501	#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3502	/** The size of I/O bitmap A (in pages). */
3503	#define VMX_V_IO_BITMAP_A_PAGES 1
3504
3505	/** The size of I/O bitmap B (in bytes). */
3506	#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3507	/** The size of I/O bitmap B (in pages). */
3508	#define VMX_V_IO_BITMAP_B_PAGES 1
3509
3510	/** The size of the auto-load/store MSR area (in bytes). */
3511	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3512	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3513	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3514	/** The size of the auto-load/store MSR area (in pages). */
3515	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3516
3517	/** The highest index value used for supported virtual VMCS field encoding. */
3518	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCSFIELD_INDEX)
3519
3520	/**
3521	* Virtual VM-exit information.
3522	*
3523	* This is a convenience structure that bundles some VM-exit information related
3524	* fields together.
3525	*/
3526	typedef struct
3527	{
3528	/** The VM-exit reason. */
3529	uint32_t uReason;
3530	/** The VM-exit instruction length. */
3531	uint32_t cbInstr;
3532	/** The VM-exit instruction information. */
3533	VMXEXITINSTRINFO InstrInfo;
3534	/** The VM-exit instruction ID. */
3535	VMXINSTRID uInstrId;
3536
3537	/** The Exit qualification field. */
3538	uint64_t u64Qual;
3539	/** The Guest-linear address field. */
3540	uint64_t u64GuestLinearAddr;
3541	/** The Guest-physical address field. */
3542	uint64_t u64GuestPhysAddr;
3543	/** The guest pending-debug exceptions. */
3544	uint64_t u64GuestPendingDbgXcpts;
3545	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3546	* instruction VM-exit. */
3547	RTGCPTR GCPtrEffAddr;
3548	} VMXVEXITINFO;
3549	/** Pointer to the VMXVEXITINFO struct. */
3550	typedef VMXVEXITINFO *PVMXVEXITINFO;
3551	/** Pointer to a const VMXVEXITINFO struct. */
3552	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3553	AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3554
3555	/**
3556	* Virtual VM-exit information for events.
3557	*
3558	* This is a convenience structure that bundles some event-based VM-exit information
3559	* related fields together that are not included in VMXVEXITINFO.
3560	*
3561	* This is kept as a separate structure and not included in VMXVEXITINFO, to make it
3562	* easier to distinguish that IEM VM-exit handlers will set one or more of the
3563	* following fields in the virtual VMCS. Including it in the VMXVEXITINFO will not
3564	* make it ovbious which fields may get set (or cleared).
3565	*/
3566	typedef struct
3567	{
3568	/** VM-exit interruption information. */
3569	uint32_t uExitIntInfo;
3570	/** VM-exit interruption error code. */
3571	uint32_t uExitIntErrCode;
3572	/** IDT-vectoring information. */
3573	uint32_t uIdtVectoringInfo;
3574	/** IDT-vectoring error code. */
3575	uint32_t uIdtVectoringErrCode;
3576	} VMXVEXITEVENTINFO;
3577	/** Pointer to the VMXVEXITINFO2 struct. */
3578	typedef VMXVEXITEVENTINFO *PVMXVEXITEVENTINFO;
3579	/** Pointer to a const VMXVEXITINFO2 struct. */
3580	typedef const VMXVEXITEVENTINFO *PCVMXVEXITEVENTINFO;
3581
3582	/**
3583	* Virtual VMCS.
3584	*
3585	* This is our custom format. Relevant fields from this VMCS will be merged into the
3586	* actual/shadow VMCS when we execute nested-guest code using hardware-assisted
3587	* VMX.
3588	*
3589	* The first 8 bytes must be in accordance with the Intel VT-x spec.
3590	* See Intel spec. 24.2 "Format of the VMCS Region".
3591	*
3592	* The offset and size of the VMCS state field (@a fVmcsState) is also fixed (not by
3593	* the Intel spec. but for our own requirements) as we use it to offset into guest
3594	* memory.
3595	*
3596	* Although the guest is supposed to access the VMCS only through the execution of
3597	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3598	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
3599	* for teleportation purposes, any newly added fields should be added to the
3600	* appropriate reserved sections or at the end of the structure.
3601	*
3602	* We always treat natural-width fields as 64-bit in our implementation since
3603	* it's easier, allows for teleporation in the future and does not affect guest
3604	* software.
3605	*
3606	* @note Any fields that are added or modified here, make sure to update the
3607	* corresponding fields in IEM (g_aoffVmcsMap), the corresponding saved
3608	* state structure in CPUM (g_aVmxHwvirtVmcs) and bump the SSM version.
3609	* Also consider updating CPUMIsGuestVmxVmcsFieldValid.
3610	*/
3611	#pragma pack(1)
3612	typedef struct
3613	{
3614	/** @name Header.
3615	* @{
3616	*/
3617	VMXVMCSREVID u32VmcsRevId; /*< 0x000 - VMX VMCS revision identifier. /
3618	VMXABORT enmVmxAbort; /*< 0x004 - VMX-abort indicator. /
3619	uint8_t fVmcsState; /*< 0x008 - VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. /
3620	uint8_t au8Padding0[3]; /*< 0x009 - Reserved for future. /
3621	uint32_t au32Reserved0[12]; /*< 0x00c - Reserved for future. /
3622	/** @} */
3623
3624	/** @name Read-only fields.
3625	* @{ */
3626	/** 16-bit fields. */
3627	uint16_t u16Reserved0[14]; /*< 0x03c - Reserved for future. /
3628
3629	/** 32-bit fields. */
3630	uint32_t u32RoVmInstrError; /*< 0x058 - VM-instruction error. /
3631	uint32_t u32RoExitReason; /*< 0x05c - VM-exit reason. /
3632	uint32_t u32RoExitIntInfo; /*< 0x060 - VM-exit interruption information. /
3633	uint32_t u32RoExitIntErrCode; /*< 0x064 - VM-exit interruption error code. /
3634	uint32_t u32RoIdtVectoringInfo; /*< 0x068 - IDT-vectoring information. /
3635	uint32_t u32RoIdtVectoringErrCode; /*< 0x06c - IDT-vectoring error code. /
3636	uint32_t u32RoExitInstrLen; /*< 0x070 - VM-exit instruction length. /
3637	uint32_t u32RoExitInstrInfo; /*< 0x074 - VM-exit instruction information. /
3638	uint32_t au32RoReserved2[16]; /*< 0x078 - Reserved for future. /
3639
3640	/** 64-bit fields. */
3641	RTUINT64U u64RoGuestPhysAddr; /*< 0x0b8 - Guest-physical address. /
3642	RTUINT64U au64Reserved1[8]; /*< 0x0c0 - Reserved for future. /
3643
3644	/** Natural-width fields. */
3645	RTUINT64U u64RoExitQual; /*< 0x100 - Exit qualification. /
3646	RTUINT64U u64RoIoRcx; /*< 0x108 - I/O RCX. /
3647	RTUINT64U u64RoIoRsi; /*< 0x110 - I/O RSI. /
3648	RTUINT64U u64RoIoRdi; /*< 0x118 - I/O RDI. /
3649	RTUINT64U u64RoIoRip; /*< 0x120 - I/O RIP. /
3650	RTUINT64U u64RoGuestLinearAddr; /*< 0x128 - Guest-linear address. /
3651	RTUINT64U au64Reserved5[16]; /*< 0x130 - Reserved for future. /
3652	/** @} */
3653
3654	/** @name Control fields.
3655	* @{ */
3656	/** 16-bit fields. */
3657	uint16_t u16Vpid; /*< 0x1b0 - Virtual processor ID. /
3658	uint16_t u16PostIntNotifyVector; /*< 0x1b2 - Posted interrupt notify vector. /
3659	uint16_t u16EptpIndex; /*< 0x1b4 - EPTP index. /
3660	uint16_t au16Reserved0[13]; /*< 0x1b6 - Reserved for future. /
3661
3662	/** 32-bit fields. */
3663	uint32_t u32PinCtls; /*< 0x1d0 - Pin-based VM-execution controls. /
3664	uint32_t u32ProcCtls; /*< 0x1d4 - Processor-based VM-execution controls. /
3665	uint32_t u32XcptBitmap; /*< 0x1d8 - Exception bitmap. /
3666	uint32_t u32XcptPFMask; /*< 0x1dc - Page-fault exception error mask. /
3667	uint32_t u32XcptPFMatch; /*< 0x1e0 - Page-fault exception error match. /
3668	uint32_t u32Cr3TargetCount; /*< 0x1e4 - CR3-target count. /
3669	uint32_t u32ExitCtls; /*< 0x1e8 - VM-exit controls. /
3670	uint32_t u32ExitMsrStoreCount; /*< 0x1ec - VM-exit MSR store count. /
3671	uint32_t u32ExitMsrLoadCount; /*< 0x1f0 - VM-exit MSR load count. /
3672	uint32_t u32EntryCtls; /*< 0x1f4 - VM-entry controls. /
3673	uint32_t u32EntryMsrLoadCount; /*< 0x1f8 - VM-entry MSR load count. /
3674	uint32_t u32EntryIntInfo; /*< 0x1fc - VM-entry interruption information. /
3675	uint32_t u32EntryXcptErrCode; /*< 0x200 - VM-entry exception error code. /
3676	uint32_t u32EntryInstrLen; /*< 0x204 - VM-entry instruction length. /
3677	uint32_t u32TprThreshold; /*< 0x208 - TPR-threshold. /
3678	uint32_t u32ProcCtls2; /*< 0x20c - Secondary-processor based VM-execution controls. /
3679	uint32_t u32PleGap; /*< 0x210 - Pause-loop exiting Gap. /
3680	uint32_t u32PleWindow; /*< 0x214 - Pause-loop exiting Window. /
3681	uint32_t au32Reserved1[16]; /*< 0x218 - Reserved for future. /
3682
3683	/** 64-bit fields. */
3684	RTUINT64U u64AddrIoBitmapA; /*< 0x258 - I/O bitmap A address. /
3685	RTUINT64U u64AddrIoBitmapB; /*< 0x260 - I/O bitmap B address. /
3686	RTUINT64U u64AddrMsrBitmap; /*< 0x268 - MSR bitmap address. /
3687	RTUINT64U u64AddrExitMsrStore; /*< 0x270 - VM-exit MSR-store area address. /
3688	RTUINT64U u64AddrExitMsrLoad; /*< 0x278 - VM-exit MSR-load area address. /
3689	RTUINT64U u64AddrEntryMsrLoad; /*< 0x280 - VM-entry MSR-load area address. /
3690	RTUINT64U u64ExecVmcsPtr; /*< 0x288 - Executive-VMCS pointer. /
3691	RTUINT64U u64AddrPml; /*< 0x290 - PML address. /
3692	RTUINT64U u64TscOffset; /*< 0x298 - TSC offset. /
3693	RTUINT64U u64AddrVirtApic; /*< 0x2a0 - Virtual-APIC address. /
3694	RTUINT64U u64AddrApicAccess; /*< 0x2a8 - APIC-access address. /
3695	RTUINT64U u64AddrPostedIntDesc; /*< 0x2b0 - Posted-interrupt descriptor address. /
3696	RTUINT64U u64VmFuncCtls; /*< 0x2b8 - VM-functions control. /
3697	RTUINT64U u64EptpPtr; /*< 0x2c0 - EPTP pointer. /
3698	RTUINT64U u64EoiExitBitmap0; /*< 0x2c8 - EOI-exit bitmap 0. /
3699	RTUINT64U u64EoiExitBitmap1; /*< 0x2d0 - EOI-exit bitmap 1. /
3700	RTUINT64U u64EoiExitBitmap2; /*< 0x2d8 - EOI-exit bitmap 2. /
3701	RTUINT64U u64EoiExitBitmap3; /*< 0x2e0 - EOI-exit bitmap 3. /
3702	RTUINT64U u64AddrEptpList; /*< 0x2e8 - EPTP-list address. /
3703	RTUINT64U u64AddrVmreadBitmap; /*< 0x2f0 - VMREAD-bitmap address. /
3704	RTUINT64U u64AddrVmwriteBitmap; /*< 0x2f8 - VMWRITE-bitmap address. /
3705	RTUINT64U u64AddrXcptVeInfo; /*< 0x300 - Virtualization-exception information address. /
3706	RTUINT64U u64XssBitmap; /*< 0x308 - XSS-exiting bitmap. /
3707	RTUINT64U u64EnclsBitmap; /*< 0x310 - ENCLS-exiting bitmap address. /
3708	RTUINT64U u64SpptPtr; /*< 0x318 - Sub-page-permission-table pointer. /
3709	RTUINT64U u64TscMultiplier; /*< 0x320 - TSC multiplier. /
3710	RTUINT64U au64Reserved0[15]; /*< 0x328 - Reserved for future. /
3711
3712	/** Natural-width fields. */
3713	RTUINT64U u64Cr0Mask; /*< 0x3a0 - CR0 guest/host Mask. /
3714	RTUINT64U u64Cr4Mask; /*< 0x3a8 - CR4 guest/host Mask. /
3715	RTUINT64U u64Cr0ReadShadow; /*< 0x3b0 - CR0 read shadow. /
3716	RTUINT64U u64Cr4ReadShadow; /*< 0x3b8 - CR4 read shadow. /
3717	RTUINT64U u64Cr3Target0; /*< 0x3c0 - CR3-target value 0. /
3718	RTUINT64U u64Cr3Target1; /*< 0x3c8 - CR3-target value 1. /
3719	RTUINT64U u64Cr3Target2; /*< 0x3d0 - CR3-target value 2. /
3720	RTUINT64U u64Cr3Target3; /*< 0x3d8 - CR3-target value 3. /
3721	RTUINT64U au64Reserved4[32]; /*< 0x3e0 - Reserved for future. /
3722	/** @} */
3723
3724	/** @name Host-state fields.
3725	* @{ */
3726	/** 16-bit fields. */
3727	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3728	RTSEL HostEs; /*< 0x4e0 - Host ES selector. /
3729	RTSEL HostCs; /*< 0x4e2 - Host CS selector. /
3730	RTSEL HostSs; /*< 0x4e4 - Host SS selector. /
3731	RTSEL HostDs; /*< 0x4e6 - Host DS selector. /
3732	RTSEL HostFs; /*< 0x4e8 - Host FS selector. /
3733	RTSEL HostGs; /*< 0x4ea - Host GS selector. /
3734	RTSEL HostTr; /*< 0x4ec - Host TR selector. /
3735	uint16_t au16Reserved2[13]; /*< 0x4ee - Reserved for future. /
3736
3737	/** 32-bit fields. */
3738	uint32_t u32HostSysenterCs; /*< 0x508 - Host SYSENTER CS. /
3739	uint32_t au32Reserved4[11]; /*< 0x50c - Reserved for future. /
3740
3741	/** 64-bit fields. */
3742	RTUINT64U u64HostPatMsr; /*< 0x538 - Host PAT MSR. /
3743	RTUINT64U u64HostEferMsr; /*< 0x540 - Host EFER MSR. /
3744	RTUINT64U u64HostPerfGlobalCtlMsr; /*< 0x548 - Host global performance-control MSR. /
3745	RTUINT64U au64Reserved3[16]; /*< 0x550 - Reserved for future. /
3746
3747	/** Natural-width fields. */
3748	RTUINT64U u64HostCr0; /*< 0x5d0 - Host CR0. /
3749	RTUINT64U u64HostCr3; /*< 0x5d8 - Host CR3. /
3750	RTUINT64U u64HostCr4; /*< 0x5e0 - Host CR4. /
3751	RTUINT64U u64HostFsBase; /*< 0x5e8 - Host FS base. /
3752	RTUINT64U u64HostGsBase; /*< 0x5f0 - Host GS base. /
3753	RTUINT64U u64HostTrBase; /*< 0x5f8 - Host TR base. /
3754	RTUINT64U u64HostGdtrBase; /*< 0x600 - Host GDTR base. /
3755	RTUINT64U u64HostIdtrBase; /*< 0x608 - Host IDTR base. /
3756	RTUINT64U u64HostSysenterEsp; /*< 0x610 - Host SYSENTER ESP base. /
3757	RTUINT64U u64HostSysenterEip; /*< 0x618 - Host SYSENTER ESP base. /
3758	RTUINT64U u64HostRsp; /*< 0x620 - Host RSP. /
3759	RTUINT64U u64HostRip; /*< 0x628 - Host RIP. /
3760	RTUINT64U au64Reserved7[32]; /*< 0x630 - Reserved for future. /
3761	/** @} */
3762
3763	/** @name Guest-state fields.
3764	* @{ */
3765	/** 16-bit fields. */
3766	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3767	RTSEL GuestEs; /*< 0x730 - Guest ES selector. /
3768	RTSEL GuestCs; /*< 0x732 - Guest ES selector. /
3769	RTSEL GuestSs; /*< 0x734 - Guest ES selector. /
3770	RTSEL GuestDs; /*< 0x736 - Guest ES selector. /
3771	RTSEL GuestFs; /*< 0x738 - Guest ES selector. /
3772	RTSEL GuestGs; /*< 0x73a - Guest ES selector. /
3773	RTSEL GuestLdtr; /*< 0x73c - Guest LDTR selector. /
3774	RTSEL GuestTr; /*< 0x73e - Guest TR selector. /
3775	uint16_t u16GuestIntStatus; /*< 0x740 - Guest interrupt status (virtual-interrupt delivery). /
3776	uint16_t u16PmlIndex; /*< 0x742 - PML index. /
3777	uint16_t au16Reserved1[14]; /*< 0x744 - Reserved for future. /
3778
3779	/** 32-bit fields. */
3780	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3781	uint32_t u32GuestEsLimit; /*< 0x760 - Guest ES limit. /
3782	uint32_t u32GuestCsLimit; /*< 0x764 - Guest CS limit. /
3783	uint32_t u32GuestSsLimit; /*< 0x768 - Guest SS limit. /
3784	uint32_t u32GuestDsLimit; /*< 0x76c - Guest DS limit. /
3785	uint32_t u32GuestFsLimit; /*< 0x770 - Guest FS limit. /
3786	uint32_t u32GuestGsLimit; /*< 0x774 - Guest GS limit. /
3787	uint32_t u32GuestLdtrLimit; /*< 0x778 - Guest LDTR limit. /
3788	uint32_t u32GuestTrLimit; /*< 0x77c - Guest TR limit. /
3789	uint32_t u32GuestGdtrLimit; /*< 0x780 - Guest GDTR limit. /
3790	uint32_t u32GuestIdtrLimit; /*< 0x784 - Guest IDTR limit. /
3791	uint32_t u32GuestEsAttr; /*< 0x788 - Guest ES attributes. /
3792	uint32_t u32GuestCsAttr; /*< 0x78c - Guest CS attributes. /
3793	uint32_t u32GuestSsAttr; /*< 0x790 - Guest SS attributes. /
3794	uint32_t u32GuestDsAttr; /*< 0x794 - Guest DS attributes. /
3795	uint32_t u32GuestFsAttr; /*< 0x798 - Guest FS attributes. /
3796	uint32_t u32GuestGsAttr; /*< 0x79c - Guest GS attributes. /
3797	uint32_t u32GuestLdtrAttr; /*< 0x7a0 - Guest LDTR attributes. /
3798	uint32_t u32GuestTrAttr; /*< 0x7a4 - Guest TR attributes. /
3799	uint32_t u32GuestIntrState; /*< 0x7a8 - Guest interruptibility state. /
3800	uint32_t u32GuestActivityState; /*< 0x7ac - Guest activity state. /
3801	uint32_t u32GuestSmBase; /*< 0x7b0 - Guest SMBASE. /
3802	uint32_t u32GuestSysenterCS; /*< 0x7b4 - Guest SYSENTER CS. /
3803	uint32_t u32PreemptTimer; /*< 0x7b8 - Preemption timer value. /
3804	uint32_t au32Reserved3[11]; /*< 0x7bc - Reserved for future. /
3805
3806	/** 64-bit fields. */
3807	RTUINT64U u64VmcsLinkPtr; /*< 0x7e8 - VMCS link pointer. /
3808	RTUINT64U u64GuestDebugCtlMsr; /*< 0x7f0 - Guest debug-control MSR. /
3809	RTUINT64U u64GuestPatMsr; /*< 0x7f8 - Guest PAT MSR. /
3810	RTUINT64U u64GuestEferMsr; /*< 0x800 - Guest EFER MSR. /
3811	RTUINT64U u64GuestPerfGlobalCtlMsr; /*< 0x808 - Guest global performance-control MSR. /
3812	RTUINT64U u64GuestPdpte0; /*< 0x810 - Guest PDPTE 0. /
3813	RTUINT64U u64GuestPdpte1; /*< 0x818 - Guest PDPTE 0. /
3814	RTUINT64U u64GuestPdpte2; /*< 0x820 - Guest PDPTE 1. /
3815	RTUINT64U u64GuestPdpte3; /*< 0x828 - Guest PDPTE 2. /
3816	RTUINT64U u64GuestBndcfgsMsr; /*< 0x830 - Guest Bounds config MPX MSR (Intel Memory Protection Extensions). /
3817	RTUINT64U u64GuestRtitCtlMsr; /*< 0x838 - Guest RTIT control MSR (Intel Real Time Instruction Trace). /
3818	RTUINT64U au64Reserved2[32]; /*< 0x840 - Reserved for future. /
3819
3820	/** Natural-width fields. */
3821	RTUINT64U u64GuestCr0; /*< 0x940 - Guest CR0. /
3822	RTUINT64U u64GuestCr3; /*< 0x948 - Guest CR3. /
3823	RTUINT64U u64GuestCr4; /*< 0x950 - Guest CR4. /
3824	RTUINT64U u64GuestEsBase; /*< 0x958 - Guest ES base. /
3825	RTUINT64U u64GuestCsBase; /*< 0x960 - Guest CS base. /
3826	RTUINT64U u64GuestSsBase; /*< 0x968 - Guest SS base. /
3827	RTUINT64U u64GuestDsBase; /*< 0x970 - Guest DS base. /
3828	RTUINT64U u64GuestFsBase; /*< 0x978 - Guest FS base. /
3829	RTUINT64U u64GuestGsBase; /*< 0x980 - Guest GS base. /
3830	RTUINT64U u64GuestLdtrBase; /*< 0x988 - Guest LDTR base. /
3831	RTUINT64U u64GuestTrBase; /*< 0x990 - Guest TR base. /
3832	RTUINT64U u64GuestGdtrBase; /*< 0x998 - Guest GDTR base. /
3833	RTUINT64U u64GuestIdtrBase; /*< 0x9a0 - Guest IDTR base. /
3834	RTUINT64U u64GuestDr7; /*< 0x9a8 - Guest DR7. /
3835	RTUINT64U u64GuestRsp; /*< 0x9b0 - Guest RSP. /
3836	RTUINT64U u64GuestRip; /*< 0x9b8 - Guest RIP. /
3837	RTUINT64U u64GuestRFlags; /*< 0x9c0 - Guest RFLAGS. /
3838	RTUINT64U u64GuestPendingDbgXcpts; /*< 0x9c8 - Guest pending debug exceptions. /
3839	RTUINT64U u64GuestSysenterEsp; /*< 0x9d0 - Guest SYSENTER ESP. /
3840	RTUINT64U u64GuestSysenterEip; /*< 0x9d8 - Guest SYSENTER EIP. /
3841	RTUINT64U au64Reserved6[32]; /*< 0x9e0 - Reserved for future. /
3842	/** @} */
3843
3844	/** 0xae0 - Padding / reserved for future use. */
3845	uint8_t abPadding[X86_PAGE_4K_SIZE - 0xae0];
3846	} VMXVVMCS;
3847	#pragma pack()
3848	/** Pointer to the VMXVVMCS struct. */
3849	typedef VMXVVMCS *PVMXVVMCS;
3850	/** Pointer to a const VMXVVMCS struct. */
3851	typedef const VMXVVMCS *PCVMXVVMCS;
3852	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
3853	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
3854	AssertCompileMemberOffset(VMXVVMCS, enmVmxAbort, 0x004);
3855	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
3856	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x058);
3857	AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x0b8);
3858	AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x100);
3859	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x1b0);
3860	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x1d0);
3861	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x258);
3862	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x3a0);
3863	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x4e0);
3864	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x508);
3865	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x538);
3866	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x5d0);
3867	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x730);
3868	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x760);
3869	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x7e8);
3870	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x940);
3871
3872	/**
3873	* Virtual VMX-instruction and VM-exit diagnostics.
3874	*
3875	* These are not the same as VM instruction errors that are enumerated in the Intel
3876	* spec. These are purely internal, fine-grained definitions used for diagnostic
3877	* purposes and are not reported to guest software under the VM-instruction error
3878	* field in its VMCS.
3879	*
3880	* @note Members of this enum are used as array indices, so no gaps are allowed.
3881	* Please update g_apszVmxVDiagDesc when you add new fields to this enum.
3882	*/
3883	typedef enum
3884	{
3885	/* Internal processing errors. */
3886	kVmxVDiag_None = 0,
3887	kVmxVDiag_Ipe_1,
3888	kVmxVDiag_Ipe_2,
3889	kVmxVDiag_Ipe_3,
3890	kVmxVDiag_Ipe_4,
3891	kVmxVDiag_Ipe_5,
3892	kVmxVDiag_Ipe_6,
3893	kVmxVDiag_Ipe_7,
3894	kVmxVDiag_Ipe_8,
3895	kVmxVDiag_Ipe_9,
3896	kVmxVDiag_Ipe_10,
3897	kVmxVDiag_Ipe_11,
3898	kVmxVDiag_Ipe_12,
3899	kVmxVDiag_Ipe_13,
3900	kVmxVDiag_Ipe_14,
3901	kVmxVDiag_Ipe_15,
3902	kVmxVDiag_Ipe_16,
3903	/* VMXON. */
3904	kVmxVDiag_Vmxon_A20M,
3905	kVmxVDiag_Vmxon_Cpl,
3906	kVmxVDiag_Vmxon_Cr0Fixed0,
3907	kVmxVDiag_Vmxon_Cr0Fixed1,
3908	kVmxVDiag_Vmxon_Cr4Fixed0,
3909	kVmxVDiag_Vmxon_Cr4Fixed1,
3910	kVmxVDiag_Vmxon_Intercept,
3911	kVmxVDiag_Vmxon_LongModeCS,
3912	kVmxVDiag_Vmxon_MsrFeatCtl,
3913	kVmxVDiag_Vmxon_PtrAbnormal,
3914	kVmxVDiag_Vmxon_PtrAlign,
3915	kVmxVDiag_Vmxon_PtrMap,
3916	kVmxVDiag_Vmxon_PtrReadPhys,
3917	kVmxVDiag_Vmxon_PtrWidth,
3918	kVmxVDiag_Vmxon_RealOrV86Mode,
3919	kVmxVDiag_Vmxon_ShadowVmcs,
3920	kVmxVDiag_Vmxon_VmxAlreadyRoot,
3921	kVmxVDiag_Vmxon_Vmxe,
3922	kVmxVDiag_Vmxon_VmcsRevId,
3923	kVmxVDiag_Vmxon_VmxRootCpl,
3924	/* VMXOFF. */
3925	kVmxVDiag_Vmxoff_Cpl,
3926	kVmxVDiag_Vmxoff_Intercept,
3927	kVmxVDiag_Vmxoff_LongModeCS,
3928	kVmxVDiag_Vmxoff_RealOrV86Mode,
3929	kVmxVDiag_Vmxoff_Vmxe,
3930	kVmxVDiag_Vmxoff_VmxRoot,
3931	/* VMPTRLD. */
3932	kVmxVDiag_Vmptrld_Cpl,
3933	kVmxVDiag_Vmptrld_LongModeCS,
3934	kVmxVDiag_Vmptrld_PtrAbnormal,
3935	kVmxVDiag_Vmptrld_PtrAlign,
3936	kVmxVDiag_Vmptrld_PtrMap,
3937	kVmxVDiag_Vmptrld_PtrReadPhys,
3938	kVmxVDiag_Vmptrld_PtrVmxon,
3939	kVmxVDiag_Vmptrld_PtrWidth,
3940	kVmxVDiag_Vmptrld_RealOrV86Mode,
3941	kVmxVDiag_Vmptrld_RevPtrReadPhys,
3942	kVmxVDiag_Vmptrld_ShadowVmcs,
3943	kVmxVDiag_Vmptrld_VmcsRevId,
3944	kVmxVDiag_Vmptrld_VmxRoot,
3945	/* VMPTRST. */
3946	kVmxVDiag_Vmptrst_Cpl,
3947	kVmxVDiag_Vmptrst_LongModeCS,
3948	kVmxVDiag_Vmptrst_PtrMap,
3949	kVmxVDiag_Vmptrst_RealOrV86Mode,
3950	kVmxVDiag_Vmptrst_VmxRoot,
3951	/* VMCLEAR. */
3952	kVmxVDiag_Vmclear_Cpl,
3953	kVmxVDiag_Vmclear_LongModeCS,
3954	kVmxVDiag_Vmclear_PtrAbnormal,
3955	kVmxVDiag_Vmclear_PtrAlign,
3956	kVmxVDiag_Vmclear_PtrMap,
3957	kVmxVDiag_Vmclear_PtrReadPhys,
3958	kVmxVDiag_Vmclear_PtrVmxon,
3959	kVmxVDiag_Vmclear_PtrWidth,
3960	kVmxVDiag_Vmclear_RealOrV86Mode,
3961	kVmxVDiag_Vmclear_VmxRoot,
3962	/* VMWRITE. */
3963	kVmxVDiag_Vmwrite_Cpl,
3964	kVmxVDiag_Vmwrite_FieldInvalid,
3965	kVmxVDiag_Vmwrite_FieldRo,
3966	kVmxVDiag_Vmwrite_LinkPtrInvalid,
3967	kVmxVDiag_Vmwrite_LongModeCS,
3968	kVmxVDiag_Vmwrite_PtrInvalid,
3969	kVmxVDiag_Vmwrite_PtrMap,
3970	kVmxVDiag_Vmwrite_RealOrV86Mode,
3971	kVmxVDiag_Vmwrite_VmxRoot,
3972	/* VMREAD. */
3973	kVmxVDiag_Vmread_Cpl,
3974	kVmxVDiag_Vmread_FieldInvalid,
3975	kVmxVDiag_Vmread_LinkPtrInvalid,
3976	kVmxVDiag_Vmread_LongModeCS,
3977	kVmxVDiag_Vmread_PtrInvalid,
3978	kVmxVDiag_Vmread_PtrMap,
3979	kVmxVDiag_Vmread_RealOrV86Mode,
3980	kVmxVDiag_Vmread_VmxRoot,
3981	/* INVVPID. */
3982	kVmxVDiag_Invvpid_Cpl,
3983	kVmxVDiag_Invvpid_DescRsvd,
3984	kVmxVDiag_Invvpid_LongModeCS,
3985	kVmxVDiag_Invvpid_RealOrV86Mode,
3986	kVmxVDiag_Invvpid_TypeInvalid,
3987	kVmxVDiag_Invvpid_Type0InvalidAddr,
3988	kVmxVDiag_Invvpid_Type0InvalidVpid,
3989	kVmxVDiag_Invvpid_Type1InvalidVpid,
3990	kVmxVDiag_Invvpid_Type3InvalidVpid,
3991	kVmxVDiag_Invvpid_VmxRoot,
3992	/* VMLAUNCH/VMRESUME. */
3993	kVmxVDiag_Vmentry_AddrApicAccess,
3994	kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
3995	kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
3996	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
3997	kVmxVDiag_Vmentry_AddrExitMsrLoad,
3998	kVmxVDiag_Vmentry_AddrExitMsrStore,
3999	kVmxVDiag_Vmentry_AddrIoBitmapA,
4000	kVmxVDiag_Vmentry_AddrIoBitmapB,
4001	kVmxVDiag_Vmentry_AddrMsrBitmap,
4002	kVmxVDiag_Vmentry_AddrVirtApicPage,
4003	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
4004	kVmxVDiag_Vmentry_AddrVmreadBitmap,
4005	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
4006	kVmxVDiag_Vmentry_ApicRegVirt,
4007	kVmxVDiag_Vmentry_BlocKMovSS,
4008	kVmxVDiag_Vmentry_Cpl,
4009	kVmxVDiag_Vmentry_Cr3TargetCount,
4010	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
4011	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
4012	kVmxVDiag_Vmentry_EntryInstrLen,
4013	kVmxVDiag_Vmentry_EntryInstrLenZero,
4014	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
4015	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
4016	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
4017	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
4018	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
4019	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
4020	kVmxVDiag_Vmentry_GuestActStateHlt,
4021	kVmxVDiag_Vmentry_GuestActStateRsvd,
4022	kVmxVDiag_Vmentry_GuestActStateShutdown,
4023	kVmxVDiag_Vmentry_GuestActStateSsDpl,
4024	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
4025	kVmxVDiag_Vmentry_GuestCr0Fixed0,
4026	kVmxVDiag_Vmentry_GuestCr0Fixed1,
4027	kVmxVDiag_Vmentry_GuestCr0PgPe,
4028	kVmxVDiag_Vmentry_GuestCr3,
4029	kVmxVDiag_Vmentry_GuestCr4Fixed0,
4030	kVmxVDiag_Vmentry_GuestCr4Fixed1,
4031	kVmxVDiag_Vmentry_GuestDebugCtl,
4032	kVmxVDiag_Vmentry_GuestDr7,
4033	kVmxVDiag_Vmentry_GuestEferMsr,
4034	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
4035	kVmxVDiag_Vmentry_GuestGdtrBase,
4036	kVmxVDiag_Vmentry_GuestGdtrLimit,
4037	kVmxVDiag_Vmentry_GuestIdtrBase,
4038	kVmxVDiag_Vmentry_GuestIdtrLimit,
4039	kVmxVDiag_Vmentry_GuestIntStateEnclave,
4040	kVmxVDiag_Vmentry_GuestIntStateExtInt,
4041	kVmxVDiag_Vmentry_GuestIntStateNmi,
4042	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
4043	kVmxVDiag_Vmentry_GuestIntStateRsvd,
4044	kVmxVDiag_Vmentry_GuestIntStateSmi,
4045	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
4046	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
4047	kVmxVDiag_Vmentry_GuestPae,
4048	kVmxVDiag_Vmentry_GuestPatMsr,
4049	kVmxVDiag_Vmentry_GuestPcide,
4050	kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys,
4051	kVmxVDiag_Vmentry_GuestPdpte0Rsvd,
4052	kVmxVDiag_Vmentry_GuestPdpte1Rsvd,
4053	kVmxVDiag_Vmentry_GuestPdpte2Rsvd,
4054	kVmxVDiag_Vmentry_GuestPdpte3Rsvd,
4055	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
4056	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
4057	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
4058	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
4059	kVmxVDiag_Vmentry_GuestRip,
4060	kVmxVDiag_Vmentry_GuestRipRsvd,
4061	kVmxVDiag_Vmentry_GuestRFlagsIf,
4062	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
4063	kVmxVDiag_Vmentry_GuestRFlagsVm,
4064	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
4065	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
4066	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
4067	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
4068	kVmxVDiag_Vmentry_GuestSegAttrCsType,
4069	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
4070	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
4071	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
4072	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
4073	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
4074	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
4075	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
4076	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
4077	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
4078	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
4079	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
4080	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
4081	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
4082	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
4083	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
4084	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
4085	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
4086	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
4087	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
4088	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
4089	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
4090	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
4091	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
4092	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
4093	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
4094	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
4095	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
4096	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
4097	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
4098	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
4099	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
4100	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
4101	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
4102	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
4103	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
4104	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
4105	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
4106	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
4107	kVmxVDiag_Vmentry_GuestSegAttrSsType,
4108	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
4109	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
4110	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
4111	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
4112	kVmxVDiag_Vmentry_GuestSegAttrTrType,
4113	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
4114	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
4115	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
4116	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
4117	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
4118	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
4119	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
4120	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
4121	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
4122	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
4123	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
4124	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
4125	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
4126	kVmxVDiag_Vmentry_GuestSegBaseCs,
4127	kVmxVDiag_Vmentry_GuestSegBaseDs,
4128	kVmxVDiag_Vmentry_GuestSegBaseEs,
4129	kVmxVDiag_Vmentry_GuestSegBaseFs,
4130	kVmxVDiag_Vmentry_GuestSegBaseGs,
4131	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
4132	kVmxVDiag_Vmentry_GuestSegBaseSs,
4133	kVmxVDiag_Vmentry_GuestSegBaseTr,
4134	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
4135	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
4136	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
4137	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
4138	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
4139	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
4140	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
4141	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
4142	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
4143	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
4144	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
4145	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
4146	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
4147	kVmxVDiag_Vmentry_GuestSegSelLdtr,
4148	kVmxVDiag_Vmentry_GuestSegSelTr,
4149	kVmxVDiag_Vmentry_GuestSysenterEspEip,
4150	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
4151	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
4152	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
4153	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
4154	kVmxVDiag_Vmentry_HostCr0Fixed0,
4155	kVmxVDiag_Vmentry_HostCr0Fixed1,
4156	kVmxVDiag_Vmentry_HostCr3,
4157	kVmxVDiag_Vmentry_HostCr4Fixed0,
4158	kVmxVDiag_Vmentry_HostCr4Fixed1,
4159	kVmxVDiag_Vmentry_HostCr4Pae,
4160	kVmxVDiag_Vmentry_HostCr4Pcide,
4161	kVmxVDiag_Vmentry_HostCsTr,
4162	kVmxVDiag_Vmentry_HostEferMsr,
4163	kVmxVDiag_Vmentry_HostEferMsrRsvd,
4164	kVmxVDiag_Vmentry_HostGuestLongMode,
4165	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4166	kVmxVDiag_Vmentry_HostLongMode,
4167	kVmxVDiag_Vmentry_HostPatMsr,
4168	kVmxVDiag_Vmentry_HostRip,
4169	kVmxVDiag_Vmentry_HostRipRsvd,
4170	kVmxVDiag_Vmentry_HostSel,
4171	kVmxVDiag_Vmentry_HostSegBase,
4172	kVmxVDiag_Vmentry_HostSs,
4173	kVmxVDiag_Vmentry_HostSysenterEspEip,
4174	kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys,
4175	kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys,
4176	kVmxVDiag_Vmentry_LongModeCS,
4177	kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4178	kVmxVDiag_Vmentry_MsrLoad,
4179	kVmxVDiag_Vmentry_MsrLoadCount,
4180	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4181	kVmxVDiag_Vmentry_MsrLoadRing3,
4182	kVmxVDiag_Vmentry_MsrLoadRsvd,
4183	kVmxVDiag_Vmentry_NmiWindowExit,
4184	kVmxVDiag_Vmentry_PinCtlsAllowed1,
4185	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4186	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4187	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4188	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4189	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4190	kVmxVDiag_Vmentry_PtrInvalid,
4191	kVmxVDiag_Vmentry_PtrShadowVmcs,
4192	kVmxVDiag_Vmentry_RealOrV86Mode,
4193	kVmxVDiag_Vmentry_SavePreemptTimer,
4194	kVmxVDiag_Vmentry_TprThresholdRsvd,
4195	kVmxVDiag_Vmentry_TprThresholdVTpr,
4196	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4197	kVmxVDiag_Vmentry_VirtIntDelivery,
4198	kVmxVDiag_Vmentry_VirtNmi,
4199	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4200	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4201	kVmxVDiag_Vmentry_VmcsClear,
4202	kVmxVDiag_Vmentry_VmcsLaunch,
4203	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4204	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4205	kVmxVDiag_Vmentry_VmxRoot,
4206	kVmxVDiag_Vmentry_Vpid,
4207	kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys,
4208	kVmxVDiag_Vmexit_HostPdpte0Rsvd,
4209	kVmxVDiag_Vmexit_HostPdpte1Rsvd,
4210	kVmxVDiag_Vmexit_HostPdpte2Rsvd,
4211	kVmxVDiag_Vmexit_HostPdpte3Rsvd,
4212	kVmxVDiag_Vmexit_MsrLoad,
4213	kVmxVDiag_Vmexit_MsrLoadCount,
4214	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4215	kVmxVDiag_Vmexit_MsrLoadRing3,
4216	kVmxVDiag_Vmexit_MsrLoadRsvd,
4217	kVmxVDiag_Vmexit_MsrStore,
4218	kVmxVDiag_Vmexit_MsrStoreCount,
4219	kVmxVDiag_Vmexit_MsrStorePtrReadPhys,
4220	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4221	kVmxVDiag_Vmexit_MsrStoreRing3,
4222	kVmxVDiag_Vmexit_MsrStoreRsvd,
4223	kVmxVDiag_Vmexit_VirtApicPagePtrWritePhys,
4224	/* Last member for determining array index limit. */
4225	kVmxVDiag_End
4226	} VMXVDIAG;
4227	AssertCompileSize(VMXVDIAG, 4);
4228
4229	/** @} */
4230
4231	/** @} */
4232
4233	#endif /* !VBOX_INCLUDED_vmm_hm_vmx_h */
4234

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 90932

Download in other formats: