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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 91971

Last change on this file since 91971 was 91971, checked in by vboxsync, 3 years ago

VMM: Nested VMX: bugref:10092 Renamed typo in VMCS field.
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1/** @file
2 * HM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_hm_vmx_h
27#define VBOX_INCLUDED_vmm_hm_vmx_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/types.h>
33#include <iprt/x86.h>
34#include <iprt/assertcompile.h>
35
36
37/** @defgroup grp_hm_vmx VMX Types and Definitions
38 * @ingroup grp_hm
39 * @{
40 */
41
42/** @name Host-state MSR lazy-restoration flags.
43 * @{
44 */
45/** The host MSRs have been saved. */
46#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
47/** The guest MSRs are loaded and in effect. */
48#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
49/** @} */
50
51/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
52 * UFC = Unsupported Feature Combination.
53 * @{
54 */
55/** Unsupported pin-based VM-execution controls combo. */
56#define VMX_UFC_CTRL_PIN_EXEC 1
57/** Unsupported processor-based VM-execution controls combo. */
58#define VMX_UFC_CTRL_PROC_EXEC 2
59/** Unsupported move debug register VM-exit combo. */
60#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
61/** Unsupported VM-entry controls combo. */
62#define VMX_UFC_CTRL_ENTRY 4
63/** Unsupported VM-exit controls combo. */
64#define VMX_UFC_CTRL_EXIT 5
65/** MSR storage capacity of the VMCS autoload/store area is not sufficient
66 * for storing host MSRs. */
67#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
68/** MSR storage capacity of the VMCS autoload/store area is not sufficient
69 * for storing guest MSRs. */
70#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
71/** Invalid VMCS size. */
72#define VMX_UFC_INVALID_VMCS_SIZE 8
73/** Unsupported secondary processor-based VM-execution controls combo. */
74#define VMX_UFC_CTRL_PROC_EXEC2 9
75/** Invalid unrestricted-guest execution controls combo. */
76#define VMX_UFC_INVALID_UX_COMBO 10
77/** EPT flush type not supported. */
78#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
79/** EPT paging structure memory type is not write-back. */
80#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
81/** EPT requires INVEPT instr. support but it's not available. */
82#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
83/** EPT requires page-walk length of 4. */
84#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
85/** VMX VMWRITE all feature exposed to the guest but not supported on host. */
86#define VMX_UFC_GST_HOST_VMWRITE_ALL 15
87/** LBR stack size cannot be determined for the current CPU. */
88#define VMX_UFC_LBR_STACK_SIZE_UNKNOWN 16
89/** LBR stack size of the CPU exceeds our buffer size. */
90#define VMX_UFC_LBR_STACK_SIZE_OVERFLOW 17
91/** @} */
92
93/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
94 * VCI = VMCS-field Cache Invalid.
95 * @{
96 */
97/** Cache of VM-entry controls invalid. */
98#define VMX_VCI_CTRL_ENTRY 300
99/** Cache of VM-exit controls invalid. */
100#define VMX_VCI_CTRL_EXIT 301
101/** Cache of pin-based VM-execution controls invalid. */
102#define VMX_VCI_CTRL_PIN_EXEC 302
103/** Cache of processor-based VM-execution controls invalid. */
104#define VMX_VCI_CTRL_PROC_EXEC 303
105/** Cache of secondary processor-based VM-execution controls invalid. */
106#define VMX_VCI_CTRL_PROC_EXEC2 304
107/** Cache of exception bitmap invalid. */
108#define VMX_VCI_CTRL_XCPT_BITMAP 305
109/** Cache of TSC offset invalid. */
110#define VMX_VCI_CTRL_TSC_OFFSET 306
111/** Cache of tertiary processor-based VM-execution controls invalid. */
112#define VMX_VCI_CTRL_PROC_EXEC3 307
113/** @} */
114
115/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
116 * IGS = Invalid Guest State.
117 * @{
118 */
119/** An error occurred while checking invalid-guest-state. */
120#define VMX_IGS_ERROR 500
121/** The invalid guest-state checks did not find any reason why. */
122#define VMX_IGS_REASON_NOT_FOUND 501
123/** CR0 fixed1 bits invalid. */
124#define VMX_IGS_CR0_FIXED1 502
125/** CR0 fixed0 bits invalid. */
126#define VMX_IGS_CR0_FIXED0 503
127/** CR0.PE and CR0.PE invalid VT-x/host combination. */
128#define VMX_IGS_CR0_PG_PE_COMBO 504
129/** CR4 fixed1 bits invalid. */
130#define VMX_IGS_CR4_FIXED1 505
131/** CR4 fixed0 bits invalid. */
132#define VMX_IGS_CR4_FIXED0 506
133/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
134 * VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
135#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
136/** CR0.PG not set for long-mode when not using unrestricted guest. */
137#define VMX_IGS_CR0_PG_LONGMODE 508
138/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
139#define VMX_IGS_CR4_PAE_LONGMODE 509
140/** CR4.PCIDE set for 32-bit guest. */
141#define VMX_IGS_CR4_PCIDE 510
142/** VMCS' DR7 reserved bits not set to 0. */
143#define VMX_IGS_DR7_RESERVED 511
144/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
145#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
146/** VMCS' EFER MSR reserved bits not set to 0. */
147#define VMX_IGS_EFER_MSR_RESERVED 513
148/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
149#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
150/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
151 * without unrestricted guest. */
152#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
153/** CS.Attr.P bit invalid. */
154#define VMX_IGS_CS_ATTR_P_INVALID 516
155/** CS.Attr reserved bits not set to 0. */
156#define VMX_IGS_CS_ATTR_RESERVED 517
157/** CS.Attr.G bit invalid. */
158#define VMX_IGS_CS_ATTR_G_INVALID 518
159/** CS is unusable. */
160#define VMX_IGS_CS_ATTR_UNUSABLE 519
161/** CS and SS DPL unequal. */
162#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
163/** CS and SS DPL mismatch. */
164#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
165/** CS Attr.Type invalid. */
166#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
167/** CS and SS RPL unequal. */
168#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
169/** SS.Attr.DPL and SS RPL unequal. */
170#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
171/** SS.Attr.DPL invalid for segment type. */
172#define VMX_IGS_SS_ATTR_DPL_INVALID 525
173/** SS.Attr.Type invalid. */
174#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
175/** SS.Attr.P bit invalid. */
176#define VMX_IGS_SS_ATTR_P_INVALID 527
177/** SS.Attr reserved bits not set to 0. */
178#define VMX_IGS_SS_ATTR_RESERVED 528
179/** SS.Attr.G bit invalid. */
180#define VMX_IGS_SS_ATTR_G_INVALID 529
181/** DS.Attr.A bit invalid. */
182#define VMX_IGS_DS_ATTR_A_INVALID 530
183/** DS.Attr.P bit invalid. */
184#define VMX_IGS_DS_ATTR_P_INVALID 531
185/** DS.Attr.DPL and DS RPL unequal. */
186#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
187/** DS.Attr reserved bits not set to 0. */
188#define VMX_IGS_DS_ATTR_RESERVED 533
189/** DS.Attr.G bit invalid. */
190#define VMX_IGS_DS_ATTR_G_INVALID 534
191/** DS.Attr.Type invalid. */
192#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
193/** ES.Attr.A bit invalid. */
194#define VMX_IGS_ES_ATTR_A_INVALID 536
195/** ES.Attr.P bit invalid. */
196#define VMX_IGS_ES_ATTR_P_INVALID 537
197/** ES.Attr.DPL and DS RPL unequal. */
198#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
199/** ES.Attr reserved bits not set to 0. */
200#define VMX_IGS_ES_ATTR_RESERVED 539
201/** ES.Attr.G bit invalid. */
202#define VMX_IGS_ES_ATTR_G_INVALID 540
203/** ES.Attr.Type invalid. */
204#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
205/** FS.Attr.A bit invalid. */
206#define VMX_IGS_FS_ATTR_A_INVALID 542
207/** FS.Attr.P bit invalid. */
208#define VMX_IGS_FS_ATTR_P_INVALID 543
209/** FS.Attr.DPL and DS RPL unequal. */
210#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
211/** FS.Attr reserved bits not set to 0. */
212#define VMX_IGS_FS_ATTR_RESERVED 545
213/** FS.Attr.G bit invalid. */
214#define VMX_IGS_FS_ATTR_G_INVALID 546
215/** FS.Attr.Type invalid. */
216#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
217/** GS.Attr.A bit invalid. */
218#define VMX_IGS_GS_ATTR_A_INVALID 548
219/** GS.Attr.P bit invalid. */
220#define VMX_IGS_GS_ATTR_P_INVALID 549
221/** GS.Attr.DPL and DS RPL unequal. */
222#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
223/** GS.Attr reserved bits not set to 0. */
224#define VMX_IGS_GS_ATTR_RESERVED 551
225/** GS.Attr.G bit invalid. */
226#define VMX_IGS_GS_ATTR_G_INVALID 552
227/** GS.Attr.Type invalid. */
228#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
229/** V86 mode CS.Base invalid. */
230#define VMX_IGS_V86_CS_BASE_INVALID 554
231/** V86 mode CS.Limit invalid. */
232#define VMX_IGS_V86_CS_LIMIT_INVALID 555
233/** V86 mode CS.Attr invalid. */
234#define VMX_IGS_V86_CS_ATTR_INVALID 556
235/** V86 mode SS.Base invalid. */
236#define VMX_IGS_V86_SS_BASE_INVALID 557
237/** V86 mode SS.Limit invalid. */
238#define VMX_IGS_V86_SS_LIMIT_INVALID 558
239/** V86 mode SS.Attr invalid. */
240#define VMX_IGS_V86_SS_ATTR_INVALID 559
241/** V86 mode DS.Base invalid. */
242#define VMX_IGS_V86_DS_BASE_INVALID 560
243/** V86 mode DS.Limit invalid. */
244#define VMX_IGS_V86_DS_LIMIT_INVALID 561
245/** V86 mode DS.Attr invalid. */
246#define VMX_IGS_V86_DS_ATTR_INVALID 562
247/** V86 mode ES.Base invalid. */
248#define VMX_IGS_V86_ES_BASE_INVALID 563
249/** V86 mode ES.Limit invalid. */
250#define VMX_IGS_V86_ES_LIMIT_INVALID 564
251/** V86 mode ES.Attr invalid. */
252#define VMX_IGS_V86_ES_ATTR_INVALID 565
253/** V86 mode FS.Base invalid. */
254#define VMX_IGS_V86_FS_BASE_INVALID 566
255/** V86 mode FS.Limit invalid. */
256#define VMX_IGS_V86_FS_LIMIT_INVALID 567
257/** V86 mode FS.Attr invalid. */
258#define VMX_IGS_V86_FS_ATTR_INVALID 568
259/** V86 mode GS.Base invalid. */
260#define VMX_IGS_V86_GS_BASE_INVALID 569
261/** V86 mode GS.Limit invalid. */
262#define VMX_IGS_V86_GS_LIMIT_INVALID 570
263/** V86 mode GS.Attr invalid. */
264#define VMX_IGS_V86_GS_ATTR_INVALID 571
265/** Longmode CS.Base invalid. */
266#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
267/** Longmode SS.Base invalid. */
268#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
269/** Longmode DS.Base invalid. */
270#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
271/** Longmode ES.Base invalid. */
272#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
273/** SYSENTER ESP is not canonical. */
274#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
275/** SYSENTER EIP is not canonical. */
276#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
277/** PAT MSR invalid. */
278#define VMX_IGS_PAT_MSR_INVALID 578
279/** PAT MSR reserved bits not set to 0. */
280#define VMX_IGS_PAT_MSR_RESERVED 579
281/** GDTR.Base is not canonical. */
282#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
283/** IDTR.Base is not canonical. */
284#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
285/** GDTR.Limit invalid. */
286#define VMX_IGS_GDTR_LIMIT_INVALID 582
287/** IDTR.Limit invalid. */
288#define VMX_IGS_IDTR_LIMIT_INVALID 583
289/** Longmode RIP is invalid. */
290#define VMX_IGS_LONGMODE_RIP_INVALID 584
291/** RFLAGS reserved bits not set to 0. */
292#define VMX_IGS_RFLAGS_RESERVED 585
293/** RFLAGS RA1 reserved bits not set to 1. */
294#define VMX_IGS_RFLAGS_RESERVED1 586
295/** RFLAGS.VM (V86 mode) invalid. */
296#define VMX_IGS_RFLAGS_VM_INVALID 587
297/** RFLAGS.IF invalid. */
298#define VMX_IGS_RFLAGS_IF_INVALID 588
299/** Activity state invalid. */
300#define VMX_IGS_ACTIVITY_STATE_INVALID 589
301/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
302#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
303/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
304#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
305/** Activity state SIPI WAIT invalid. */
306#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
307/** Interruptibility state reserved bits not set to 0. */
308#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
309/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
310#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
311/** Interruptibility state block-by-STI invalid for EFLAGS. */
312#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
313/** Interruptibility state invalid while trying to deliver external
314 * interrupt. */
315#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
316/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
317 * NMI. */
318#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
319/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
320#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
321/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
322#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
323/** Interruptibility state block-by-STI (maybe) invalid when trying to
324 * deliver an NMI. */
325#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
326/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
327 * active. */
328#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
329/** Pending debug exceptions reserved bits not set to 0. */
330#define VMX_IGS_PENDING_DEBUG_RESERVED 602
331/** Longmode pending debug exceptions reserved bits not set to 0. */
332#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
333/** Pending debug exceptions.BS bit is not set when it should be. */
334#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
335/** Pending debug exceptions.BS bit is not clear when it should be. */
336#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
337/** VMCS link pointer reserved bits not set to 0. */
338#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
339/** TR cannot index into LDT, TI bit MBZ. */
340#define VMX_IGS_TR_TI_INVALID 607
341/** LDTR cannot index into LDT. TI bit MBZ. */
342#define VMX_IGS_LDTR_TI_INVALID 608
343/** TR.Base is not canonical. */
344#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
345/** FS.Base is not canonical. */
346#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
347/** GS.Base is not canonical. */
348#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
349/** LDTR.Base is not canonical. */
350#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
351/** TR is unusable. */
352#define VMX_IGS_TR_ATTR_UNUSABLE 613
353/** TR.Attr.S bit invalid. */
354#define VMX_IGS_TR_ATTR_S_INVALID 614
355/** TR is not present. */
356#define VMX_IGS_TR_ATTR_P_INVALID 615
357/** TR.Attr reserved bits not set to 0. */
358#define VMX_IGS_TR_ATTR_RESERVED 616
359/** TR.Attr.G bit invalid. */
360#define VMX_IGS_TR_ATTR_G_INVALID 617
361/** Longmode TR.Attr.Type invalid. */
362#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
363/** TR.Attr.Type invalid. */
364#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
365/** CS.Attr.S invalid. */
366#define VMX_IGS_CS_ATTR_S_INVALID 620
367/** CS.Attr.DPL invalid. */
368#define VMX_IGS_CS_ATTR_DPL_INVALID 621
369/** PAE PDPTE reserved bits not set to 0. */
370#define VMX_IGS_PAE_PDPTE_RESERVED 623
371/** VMCS link pointer does not point to a shadow VMCS. */
372#define VMX_IGS_VMCS_LINK_PTR_NOT_SHADOW 624
373/** VMCS link pointer to a shadow VMCS with invalid VMCS revision identifer. */
374#define VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID 625
375/** @} */
376
377/** @name VMX VMCS-Read cache indices.
378 * @{
379 */
380#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
381#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
382#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
383#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
384#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
385#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
386#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
387#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
388#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
389#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
390#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
391#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
392#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
393#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
394#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
395#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
396#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
397#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
398#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
399/** @} */
400
401/** @name VMX Extended Page Tables (EPT) Common Bits
402 * @{ */
403/** Bit 0 - Readable (we often think of it as present). */
404#define EPT_E_BIT_READ 0
405#define EPT_E_READ RT_BIT_64(EPT_E_BIT_READ) /**< @see EPT_E_BIT_READ */
406/** Bit 1 - Writable. */
407#define EPT_E_BIT_WRITE 1
408#define EPT_E_WRITE RT_BIT_64(EPT_E_BIT_WRITE) /**< @see EPT_E_BIT_WRITE */
409/** Bit 2 - Executable.
410 * @note This controls supervisor instruction fetching if mode-based
411 * execution control is enabled. */
412#define EPT_E_BIT_EXECUTE 2
413#define EPT_E_EXECUTE RT_BIT_64(EPT_E_BIT_EXECUTE) /**< @see EPT_E_BIT_EXECUTE */
414/** Bits 3-5 - Memory type mask (leaf only, MBZ).
415 * The memory type is only applicable for leaf entries and MBZ for
416 * non-leaf (causes miconfiguration exit). */
417#define EPT_E_TYPE_MASK UINT64_C(0x0038)
418/** Bits 3-5 - Memory type shifted mask. */
419#define EPT_E_TYPE_SMASK UINT64_C(0x0007)
420/** Bits 3-5 - Memory type shift count. */
421#define EPT_E_TYPE_SHIFT 3
422/** Bits 3-5 - Memory type: UC. */
423#define EPT_E_TYPE_UC (UINT64_C(0) << EPT_E_TYPE_SHIFT)
424/** Bits 3-5 - Memory type: WC. */
425#define EPT_E_TYPE_WC (UINT64_C(1) << EPT_E_TYPE_SHIFT)
426/** Bits 3-5 - Memory type: Invalid (2). */
427#define EPT_E_TYPE_INVALID_2 (UINT64_C(2) << EPT_E_TYPE_SHIFT)
428/** Bits 3-5 - Memory type: Invalid (3). */
429#define EPT_E_TYPE_INVALID_3 (UINT64_C(3) << EPT_E_TYPE_SHIFT)
430/** Bits 3-5 - Memory type: WT. */
431#define EPT_E_TYPE_WT (UINT64_C(4) << EPT_E_TYPE_SHIFT)
432/** Bits 3-5 - Memory type: WP. */
433#define EPT_E_TYPE_WP (UINT64_C(5) << EPT_E_TYPE_SHIFT)
434/** Bits 3-5 - Memory type: WB. */
435#define EPT_E_TYPE_WB (UINT64_C(6) << EPT_E_TYPE_SHIFT)
436/** Bits 3-5 - Memory type: Invalid (7). */
437#define EPT_E_TYPE_INVALID_7 (UINT64_C(7) << EPT_E_TYPE_SHIFT)
438
439/** Bit 6 - Ignore page attribute table (leaf, MBZ). */
440#define EPT_E_BIT_IGNORE_PAT 6
441#define EPT_E_IGNORE_PAT RT_BIT_64(EPT_E_BIT_IGNORE_PAT) /**< @see EPT_E_BIT_IGNORE_PAT */
442/** Bit 7 - Leaf entry (MBZ in PML4, ignored in PT). */
443#define EPT_E_BIT_LEAF 7
444#define EPT_E_LEAF RT_BIT_64(EPT_E_BIT_LEAF) /**< @see EPT_E_BIT_LEAF */
445/** Bit 8 - Accessed (all levels).
446 * @note Ignored and not written when EPTP bit 6 is 0. */
447#define EPT_E_BIT_ACCESSED 8
448#define EPT_E_ACCESSED RT_BIT_64(EPT_E_BIT_ACCESSED) /**< @see EPT_E_BIT_ACCESSED */
449/** Bit 9 - Dirty (leaf only).
450 * @note Ignored and not written when EPTP bit 6 is 0. */
451#define EPT_E_BIT_DIRTY 9
452#define EPT_E_DIRTY RT_BIT_64(EPT_E_BIT_DIRTY) /**< @see EPT_E_BIT_DIRTY */
453/** Bit 10 - Executable for usermode.
454 * @note This ignored if mode-based execution control is disabled. */
455#define EPT_E_BIT_USER_EXECUTE 10
456#define EPT_E_USER_EXECUTE RT_BIT_64(EPT_E_BIT_USER_EXECUTE) /**< @see EPT_E_BIT_USER_EXECUTE */
457
458/* 11 is always ignored (at time of writing) */
459
460/** Bits 12-51 - Physical Page number of the next level. */
461#define EPT_E_PG_MASK UINT64_C(0x000ffffffffff000)
462
463/** Bit 60 - Supervisor shadow stack (leaf only, ignored).
464 * @note Ignored if EPT bit 7 is 0. */
465#define EPT_E_BIT_SHADOW_STACK 60
466#define EPT_E_SHADOW_STACK RT_BIT_64(EPT_E_BIT_SHADOW_STACK) /**< @see EPT_E_BIT_SHADOW_STACK*/
467
468/* Bit 61, 62 are always ignored at time of writing. */
469
470/** Bit 63 - Supress \#VE (leaf only, ignored).
471 * @note Ignored if EPT violation to \#VE conversion is disabled. */
472#define EPT_E_BIT_IGNORE_VE 63
473#define EPT_E_IGNORE_VE RT_BIT_64(EPT_E_BIT_IGNORE_VE) /**< @see EPT_E_BIT_IGNORE_VE*/
474/** @} */
475
476
477/** @name VMX Extended Page Tables (EPT) Structures
478 * @{
479 */
480
481/**
482 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
483 */
484#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
485
486/**
487 * EPT Page Directory Pointer Entry. Bit view.
488 * In accordance with the VT-x spec.
489 *
490 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
491 * this did cause trouble with one compiler/version).
492 */
493typedef struct EPTPML4EBITS
494{
495 /** Present bit. */
496 RT_GCC_EXTENSION uint64_t u1Present : 1;
497 /** Writable bit. */
498 RT_GCC_EXTENSION uint64_t u1Write : 1;
499 /** Executable bit. */
500 RT_GCC_EXTENSION uint64_t u1Execute : 1;
501 /** Reserved (must be 0). */
502 RT_GCC_EXTENSION uint64_t u5Reserved : 5;
503 /** Available for software. */
504 RT_GCC_EXTENSION uint64_t u4Available : 4;
505 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
506 RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
507 /** Available for software. */
508 RT_GCC_EXTENSION uint64_t u12Available : 12;
509} EPTPML4EBITS;
510AssertCompileSize(EPTPML4EBITS, 8);
511
512/** Bits 12-51 - - EPT - Physical Page number of the next level. */
513#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
514/** The page shift to get the PML4 index. */
515#define EPT_PML4_SHIFT X86_PML4_SHIFT
516/** The PML4 index mask (apply to a shifted page address). */
517#define EPT_PML4_MASK X86_PML4_MASK
518/** Bits - - EPT - PML4 MBZ mask. */
519#define EPT_PML4E_MBZ_MASK UINT64_C(0x00000000000000f8)
520/** Mask of all possible EPT PML4E attribute bits. */
521#define EPT_PML4E_ATTR_MASK (EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE | EPT_E_ACCESSED | EPT_E_USER_EXECUTE)
522
523/**
524 * EPT PML4E.
525 * In accordance with the VT-x spec.
526 */
527typedef union EPTPML4E
528{
529#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
530 /** Normal view. */
531 EPTPML4EBITS n;
532#endif
533 /** Unsigned integer view. */
534 X86PGPAEUINT u;
535 /** 64 bit unsigned integer view. */
536 uint64_t au64[1];
537 /** 32 bit unsigned integer view. */
538 uint32_t au32[2];
539} EPTPML4E;
540AssertCompileSize(EPTPML4E, 8);
541/** Pointer to a PML4 table entry. */
542typedef EPTPML4E *PEPTPML4E;
543/** Pointer to a const PML4 table entry. */
544typedef const EPTPML4E *PCEPTPML4E;
545
546/**
547 * EPT PML4 Table.
548 * In accordance with the VT-x spec.
549 */
550typedef struct EPTPML4
551{
552 EPTPML4E a[EPT_PG_ENTRIES];
553} EPTPML4;
554AssertCompileSize(EPTPML4, 0x1000);
555/** Pointer to an EPT PML4 Table. */
556typedef EPTPML4 *PEPTPML4;
557/** Pointer to a const EPT PML4 Table. */
558typedef const EPTPML4 *PCEPTPML4;
559
560
561/**
562 * EPT Page Directory Pointer Entry. Bit view.
563 * In accordance with the VT-x spec.
564 */
565typedef struct EPTPDPTEBITS
566{
567 /** Present bit. */
568 RT_GCC_EXTENSION uint64_t u1Present : 1;
569 /** Writable bit. */
570 RT_GCC_EXTENSION uint64_t u1Write : 1;
571 /** Executable bit. */
572 RT_GCC_EXTENSION uint64_t u1Execute : 1;
573 /** Reserved (must be 0). */
574 RT_GCC_EXTENSION uint64_t u5Reserved : 5;
575 /** Available for software. */
576 RT_GCC_EXTENSION uint64_t u4Available : 4;
577 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
578 RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
579 /** Available for software. */
580 RT_GCC_EXTENSION uint64_t u12Available : 12;
581} EPTPDPTEBITS;
582AssertCompileSize(EPTPDPTEBITS, 8);
583
584/** Bits 12-51 - - EPT - Physical Page number of the next level. */
585#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
586/** The page shift to get the PDPT index. */
587#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
588/** The PDPT index mask (apply to a shifted page address). */
589#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
590/** Bits 3-7 - - EPT - PDPTE MBZ Mask. */
591#define EPT_PDPTE_MBZ_MASK UINT64_C(0x00000000000000f8)
592/** Bits 12-29 - - EPT - 1GB PDPTE MBZ Mask. */
593#define EPT_PDPTE1G_MBZ_MASK UINT64_C(0x000000003ffff000)
594/** */
595
596/**
597 * EPT Page Directory Pointer.
598 * In accordance with the VT-x spec.
599 */
600typedef union EPTPDPTE
601{
602#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
603 /** Normal view. */
604 EPTPDPTEBITS n;
605#endif
606 /** Unsigned integer view. */
607 X86PGPAEUINT u;
608 /** 64 bit unsigned integer view. */
609 uint64_t au64[1];
610 /** 32 bit unsigned integer view. */
611 uint32_t au32[2];
612} EPTPDPTE;
613AssertCompileSize(EPTPDPTE, 8);
614/** Pointer to an EPT Page Directory Pointer Entry. */
615typedef EPTPDPTE *PEPTPDPTE;
616/** Pointer to a const EPT Page Directory Pointer Entry. */
617typedef const EPTPDPTE *PCEPTPDPTE;
618
619/**
620 * EPT Page Directory Pointer Table.
621 * In accordance with the VT-x spec.
622 */
623typedef struct EPTPDPT
624{
625 EPTPDPTE a[EPT_PG_ENTRIES];
626} EPTPDPT;
627AssertCompileSize(EPTPDPT, 0x1000);
628/** Pointer to an EPT Page Directory Pointer Table. */
629typedef EPTPDPT *PEPTPDPT;
630/** Pointer to a const EPT Page Directory Pointer Table. */
631typedef const EPTPDPT *PCEPTPDPT;
632
633
634/**
635 * EPT Page Directory Table Entry. Bit view.
636 * In accordance with the VT-x spec.
637 */
638typedef struct EPTPDEBITS
639{
640 /** Present bit. */
641 RT_GCC_EXTENSION uint64_t u1Present : 1;
642 /** Writable bit. */
643 RT_GCC_EXTENSION uint64_t u1Write : 1;
644 /** Executable bit. */
645 RT_GCC_EXTENSION uint64_t u1Execute : 1;
646 /** Reserved (must be 0). */
647 RT_GCC_EXTENSION uint64_t u4Reserved : 4;
648 /** Big page (must be 0 here). */
649 RT_GCC_EXTENSION uint64_t u1Size : 1;
650 /** Available for software. */
651 RT_GCC_EXTENSION uint64_t u4Available : 4;
652 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
653 RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
654 /** Available for software. */
655 RT_GCC_EXTENSION uint64_t u12Available : 12;
656} EPTPDEBITS;
657AssertCompileSize(EPTPDEBITS, 8);
658
659/** Bits 12-51 - - EPT - Physical Page number of the next level. */
660#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
661/** The page shift to get the PD index. */
662#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
663/** The PD index mask (apply to a shifted page address). */
664#define EPT_PD_MASK X86_PD_PAE_MASK
665/** Bits 3-7 - EPT - PDE MBZ Mask. */
666#define EPT_PDE_MBZ_MASK UINT64_C(0x00000000000000f8)
667
668
669
670/**
671 * EPT 2MB Page Directory Table Entry. Bit view.
672 * In accordance with the VT-x spec.
673 */
674typedef struct EPTPDE2MBITS
675{
676 /** Present bit. */
677 RT_GCC_EXTENSION uint64_t u1Present : 1;
678 /** Writable bit. */
679 RT_GCC_EXTENSION uint64_t u1Write : 1;
680 /** Executable bit. */
681 RT_GCC_EXTENSION uint64_t u1Execute : 1;
682 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
683 RT_GCC_EXTENSION uint64_t u3EMT : 3;
684 /** Ignore PAT memory type */
685 RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
686 /** Big page (must be 1 here). */
687 RT_GCC_EXTENSION uint64_t u1Size : 1;
688 /** Available for software. */
689 RT_GCC_EXTENSION uint64_t u4Available : 4;
690 /** Reserved (must be 0). */
691 RT_GCC_EXTENSION uint64_t u9Reserved : 9;
692 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
693 RT_GCC_EXTENSION uint64_t u31PhysAddr : 31;
694 /** Available for software. */
695 RT_GCC_EXTENSION uint64_t u12Available : 12;
696} EPTPDE2MBITS;
697AssertCompileSize(EPTPDE2MBITS, 8);
698
699/** Bits 21-51 - - EPT - Physical Page number of the next level. */
700#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
701/** Bits 20-12 - - EPT - PDE 2M MBZ Mask. */
702#define EPT_PDE2M_MBZ_MASK UINT64_C(0x00000000001ff000)
703
704
705/**
706 * EPT Page Directory Table Entry.
707 * In accordance with the VT-x spec.
708 */
709typedef union EPTPDE
710{
711#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
712 /** Normal view. */
713 EPTPDEBITS n;
714 /** 2MB view (big). */
715 EPTPDE2MBITS b;
716#endif
717 /** Unsigned integer view. */
718 X86PGPAEUINT u;
719 /** 64 bit unsigned integer view. */
720 uint64_t au64[1];
721 /** 32 bit unsigned integer view. */
722 uint32_t au32[2];
723} EPTPDE;
724AssertCompileSize(EPTPDE, 8);
725/** Pointer to an EPT Page Directory Table Entry. */
726typedef EPTPDE *PEPTPDE;
727/** Pointer to a const EPT Page Directory Table Entry. */
728typedef const EPTPDE *PCEPTPDE;
729
730/**
731 * EPT Page Directory Table.
732 * In accordance with the VT-x spec.
733 */
734typedef struct EPTPD
735{
736 EPTPDE a[EPT_PG_ENTRIES];
737} EPTPD;
738AssertCompileSize(EPTPD, 0x1000);
739/** Pointer to an EPT Page Directory Table. */
740typedef EPTPD *PEPTPD;
741/** Pointer to a const EPT Page Directory Table. */
742typedef const EPTPD *PCEPTPD;
743
744/**
745 * EPT Page Table Entry. Bit view.
746 * In accordance with the VT-x spec.
747 */
748typedef struct EPTPTEBITS
749{
750 /** 0 - Present bit.
751 * @remarks This is a convenience "misnomer". The bit actually indicates read access
752 * and the CPU will consider an entry with any of the first three bits set
753 * as present. Since all our valid entries will have this bit set, it can
754 * be used as a present indicator and allow some code sharing. */
755 RT_GCC_EXTENSION uint64_t u1Present : 1;
756 /** 1 - Writable bit. */
757 RT_GCC_EXTENSION uint64_t u1Write : 1;
758 /** 2 - Executable bit. */
759 RT_GCC_EXTENSION uint64_t u1Execute : 1;
760 /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
761 RT_GCC_EXTENSION uint64_t u3EMT : 3;
762 /** 6 - Ignore PAT memory type */
763 RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
764 /** 11:7 - Available for software. */
765 RT_GCC_EXTENSION uint64_t u5Available : 5;
766 /** 51:12 - Physical address of page. Restricted by maximum physical
767 * address width of the cpu. */
768 RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
769 /** 63:52 - Available for software. */
770 RT_GCC_EXTENSION uint64_t u12Available : 12;
771} EPTPTEBITS;
772AssertCompileSize(EPTPTEBITS, 8);
773
774/** Bits 12-51 - - EPT - Physical Page number of the next level. */
775#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
776/** The page shift to get the EPT PTE index. */
777#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
778/** The EPT PT index mask (apply to a shifted page address). */
779#define EPT_PT_MASK X86_PT_PAE_MASK
780/** No bits - - EPT - PTE MBZ bits. */
781#define EPT_PTE_MBZ_MASK UINT64_C(0x0000000000000000)
782
783
784/**
785 * EPT Page Table Entry.
786 * In accordance with the VT-x spec.
787 */
788typedef union EPTPTE
789{
790#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
791 /** Normal view. */
792 EPTPTEBITS n;
793#endif
794 /** Unsigned integer view. */
795 X86PGPAEUINT u;
796 /** 64 bit unsigned integer view. */
797 uint64_t au64[1];
798 /** 32 bit unsigned integer view. */
799 uint32_t au32[2];
800} EPTPTE;
801AssertCompileSize(EPTPTE, 8);
802/** Pointer to an EPT Page Directory Table Entry. */
803typedef EPTPTE *PEPTPTE;
804/** Pointer to a const EPT Page Directory Table Entry. */
805typedef const EPTPTE *PCEPTPTE;
806
807/**
808 * EPT Page Table.
809 * In accordance with the VT-x spec.
810 */
811typedef struct EPTPT
812{
813 EPTPTE a[EPT_PG_ENTRIES];
814} EPTPT;
815AssertCompileSize(EPTPT, 0x1000);
816/** Pointer to an extended page table. */
817typedef EPTPT *PEPTPT;
818/** Pointer to a const extended table. */
819typedef const EPTPT *PCEPTPT;
820
821/** @} */
822
823/**
824 * VMX VPID flush types.
825 * Valid enum members are in accordance with the VT-x spec.
826 */
827typedef enum
828{
829 /** Invalidate a specific page. */
830 VMXTLBFLUSHVPID_INDIV_ADDR = 0,
831 /** Invalidate one context (specific VPID). */
832 VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
833 /** Invalidate all contexts (all VPIDs). */
834 VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
835 /** Invalidate a single VPID context retaining global mappings. */
836 VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
837 /** Unsupported by VirtualBox. */
838 VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
839 /** Unsupported by CPU. */
840 VMXTLBFLUSHVPID_NONE = 0xbad1
841} VMXTLBFLUSHVPID;
842AssertCompileSize(VMXTLBFLUSHVPID, 4);
843
844/**
845 * VMX EPT flush types.
846 * @note Valid enums values are in accordance with the VT-x spec.
847 */
848typedef enum
849{
850 /** Invalidate one context (specific EPT). */
851 VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
852 /* Invalidate all contexts (all EPTs) */
853 VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
854 /** Unsupported by VirtualBox. */
855 VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
856 /** Unsupported by CPU. */
857 VMXTLBFLUSHEPT_NONE = 0xbad1
858} VMXTLBFLUSHEPT;
859AssertCompileSize(VMXTLBFLUSHEPT, 4);
860
861/**
862 * VMX Posted Interrupt Descriptor.
863 * In accordance with the VT-x spec.
864 */
865typedef struct VMXPOSTEDINTRDESC
866{
867 uint32_t aVectorBitmap[8];
868 uint32_t fOutstandingNotification : 1;
869 uint32_t uReserved0 : 31;
870 uint8_t au8Reserved0[28];
871} VMXPOSTEDINTRDESC;
872AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
873AssertCompileSize(VMXPOSTEDINTRDESC, 64);
874/** Pointer to a posted interrupt descriptor. */
875typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
876/** Pointer to a const posted interrupt descriptor. */
877typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
878
879/**
880 * VMX VMCS revision identifier.
881 * In accordance with the VT-x spec.
882 */
883typedef union
884{
885 struct
886 {
887 /** Revision identifier. */
888 uint32_t u31RevisionId : 31;
889 /** Whether this is a shadow VMCS. */
890 uint32_t fIsShadowVmcs : 1;
891 } n;
892 /* The unsigned integer view. */
893 uint32_t u;
894} VMXVMCSREVID;
895AssertCompileSize(VMXVMCSREVID, 4);
896/** Pointer to the VMXVMCSREVID union. */
897typedef VMXVMCSREVID *PVMXVMCSREVID;
898/** Pointer to a const VMXVMCSREVID union. */
899typedef const VMXVMCSREVID *PCVMXVMCSREVID;
900
901/**
902 * VMX VM-exit instruction information.
903 * In accordance with the VT-x spec.
904 */
905typedef union
906{
907 /** Plain unsigned int representation. */
908 uint32_t u;
909
910 /** INS and OUTS information. */
911 struct
912 {
913 uint32_t u7Reserved0 : 7;
914 /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
915 uint32_t u3AddrSize : 3;
916 uint32_t u5Reserved1 : 5;
917 /** The segment register (X86_SREG_XXX). */
918 uint32_t iSegReg : 3;
919 uint32_t uReserved2 : 14;
920 } StrIo;
921
922 /** INVEPT, INVPCID, INVVPID information. */
923 struct
924 {
925 /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
926 uint32_t u2Scaling : 2;
927 uint32_t u5Undef0 : 5;
928 /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
929 uint32_t u3AddrSize : 3;
930 /** Cleared to 0. */
931 uint32_t u1Cleared0 : 1;
932 uint32_t u4Undef0 : 4;
933 /** The segment register (X86_SREG_XXX). */
934 uint32_t iSegReg : 3;
935 /** The index register (X86_GREG_XXX). */
936 uint32_t iIdxReg : 4;
937 /** Set if index register is invalid. */
938 uint32_t fIdxRegInvalid : 1;
939 /** The base register (X86_GREG_XXX). */
940 uint32_t iBaseReg : 4;
941 /** Set if base register is invalid. */
942 uint32_t fBaseRegInvalid : 1;
943 /** Register 2 (X86_GREG_XXX). */
944 uint32_t iReg2 : 4;
945 } Inv;
946
947 /** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
948 struct
949 {
950 /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
951 uint32_t u2Scaling : 2;
952 uint32_t u5Reserved0 : 5;
953 /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
954 uint32_t u3AddrSize : 3;
955 /** Cleared to 0. */
956 uint32_t u1Cleared0 : 1;
957 uint32_t u4Reserved0 : 4;
958 /** The segment register (X86_SREG_XXX). */
959 uint32_t iSegReg : 3;
960 /** The index register (X86_GREG_XXX). */
961 uint32_t iIdxReg : 4;
962 /** Set if index register is invalid. */
963 uint32_t fIdxRegInvalid : 1;
964 /** The base register (X86_GREG_XXX). */
965 uint32_t iBaseReg : 4;
966 /** Set if base register is invalid. */
967 uint32_t fBaseRegInvalid : 1;
968 /** Register 2 (X86_GREG_XXX). */
969 uint32_t iReg2 : 4;
970 } VmxXsave;
971
972 /** LIDT, LGDT, SIDT, SGDT information. */
973 struct
974 {
975 /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
976 uint32_t u2Scaling : 2;
977 uint32_t u5Undef0 : 5;
978 /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
979 uint32_t u3AddrSize : 3;
980 /** Always cleared to 0. */
981 uint32_t u1Cleared0 : 1;
982 /** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
983 uint32_t uOperandSize : 1;
984 uint32_t u3Undef0 : 3;
985 /** The segment register (X86_SREG_XXX). */
986 uint32_t iSegReg : 3;
987 /** The index register (X86_GREG_XXX). */
988 uint32_t iIdxReg : 4;
989 /** Set if index register is invalid. */
990 uint32_t fIdxRegInvalid : 1;
991 /** The base register (X86_GREG_XXX). */
992 uint32_t iBaseReg : 4;
993 /** Set if base register is invalid. */
994 uint32_t fBaseRegInvalid : 1;
995 /** Instruction identity (VMX_INSTR_ID_XXX). */
996 uint32_t u2InstrId : 2;
997 uint32_t u2Undef0 : 2;
998 } GdtIdt;
999
1000 /** LLDT, LTR, SLDT, STR information. */
1001 struct
1002 {
1003 /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1004 uint32_t u2Scaling : 2;
1005 uint32_t u1Undef0 : 1;
1006 /** Register 1 (X86_GREG_XXX). */
1007 uint32_t iReg1 : 4;
1008 /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1009 uint32_t u3AddrSize : 3;
1010 /** Memory/Register - Always cleared to 0 to indicate memory operand. */
1011 uint32_t fIsRegOperand : 1;
1012 uint32_t u4Undef0 : 4;
1013 /** The segment register (X86_SREG_XXX). */
1014 uint32_t iSegReg : 3;
1015 /** The index register (X86_GREG_XXX). */
1016 uint32_t iIdxReg : 4;
1017 /** Set if index register is invalid. */
1018 uint32_t fIdxRegInvalid : 1;
1019 /** The base register (X86_GREG_XXX). */
1020 uint32_t iBaseReg : 4;
1021 /** Set if base register is invalid. */
1022 uint32_t fBaseRegInvalid : 1;
1023 /** Instruction identity (VMX_INSTR_ID_XXX). */
1024 uint32_t u2InstrId : 2;
1025 uint32_t u2Undef0 : 2;
1026 } LdtTr;
1027
1028 /** RDRAND, RDSEED information. */
1029 struct
1030 {
1031 /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1032 uint32_t u2Undef0 : 2;
1033 /** Destination register (X86_GREG_XXX). */
1034 uint32_t iReg1 : 4;
1035 uint32_t u4Undef0 : 4;
1036 /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1037 uint32_t u2OperandSize : 2;
1038 uint32_t u19Def0 : 20;
1039 } RdrandRdseed;
1040
1041 /** VMREAD, VMWRITE information. */
1042 struct
1043 {
1044 /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1045 uint32_t u2Scaling : 2;
1046 uint32_t u1Undef0 : 1;
1047 /** Register 1 (X86_GREG_XXX). */
1048 uint32_t iReg1 : 4;
1049 /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1050 uint32_t u3AddrSize : 3;
1051 /** Memory or register operand. */
1052 uint32_t fIsRegOperand : 1;
1053 /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1054 uint32_t u4Undef0 : 4;
1055 /** The segment register (X86_SREG_XXX). */
1056 uint32_t iSegReg : 3;
1057 /** The index register (X86_GREG_XXX). */
1058 uint32_t iIdxReg : 4;
1059 /** Set if index register is invalid. */
1060 uint32_t fIdxRegInvalid : 1;
1061 /** The base register (X86_GREG_XXX). */
1062 uint32_t iBaseReg : 4;
1063 /** Set if base register is invalid. */
1064 uint32_t fBaseRegInvalid : 1;
1065 /** Register 2 (X86_GREG_XXX). */
1066 uint32_t iReg2 : 4;
1067 } VmreadVmwrite;
1068
1069 struct
1070 {
1071 uint32_t u2Undef0 : 3;
1072 /** First XMM register operand. */
1073 uint32_t u4XmmReg1 : 4;
1074 uint32_t u23Undef1 : 21;
1075 /** Second XMM register operand. */
1076 uint32_t u4XmmReg2 : 4;
1077 } LoadIwkey;
1078
1079 /** This is a combination field of all instruction information. Note! Not all field
1080 * combinations are valid (e.g., iReg1 is undefined for memory operands) and
1081 * specialized fields are overwritten by their generic counterparts (e.g. no
1082 * instruction identity field). */
1083 struct
1084 {
1085 /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1086 uint32_t u2Scaling : 2;
1087 uint32_t u1Undef0 : 1;
1088 /** Register 1 (X86_GREG_XXX). */
1089 uint32_t iReg1 : 4;
1090 /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1091 uint32_t u3AddrSize : 3;
1092 /** Memory/Register - Always cleared to 0 to indicate memory operand. */
1093 uint32_t fIsRegOperand : 1;
1094 /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1095 uint32_t uOperandSize : 2;
1096 uint32_t u2Undef0 : 2;
1097 /** The segment register (X86_SREG_XXX). */
1098 uint32_t iSegReg : 3;
1099 /** The index register (X86_GREG_XXX). */
1100 uint32_t iIdxReg : 4;
1101 /** Set if index register is invalid. */
1102 uint32_t fIdxRegInvalid : 1;
1103 /** The base register (X86_GREG_XXX). */
1104 uint32_t iBaseReg : 4;
1105 /** Set if base register is invalid. */
1106 uint32_t fBaseRegInvalid : 1;
1107 /** Register 2 (X86_GREG_XXX) or instruction identity. */
1108 uint32_t iReg2 : 4;
1109 } All;
1110} VMXEXITINSTRINFO;
1111AssertCompileSize(VMXEXITINSTRINFO, 4);
1112/** Pointer to a VMX VM-exit instruction info. struct. */
1113typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1114/** Pointer to a const VMX VM-exit instruction info. struct. */
1115typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1116
1117
1118/** @name VM-entry failure reported in Exit qualification.
1119 * See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1120 * @{
1121 */
1122/** No errors during VM-entry. */
1123#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1124/** Not used. */
1125#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1126/** Error while loading PDPTEs. */
1127#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1128/** NMI injection when blocking-by-STI is set. */
1129#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1130/** Invalid VMCS link pointer. */
1131#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1132/** @} */
1133
1134
1135/** @name VMXMSRPM_XXX - VMX MSR-bitmap permissions.
1136 * These are -not- specified by Intel but used internally by VirtualBox.
1137 * @{ */
1138/** Guest software reads of this MSR must not cause a VM-exit. */
1139#define VMXMSRPM_ALLOW_RD RT_BIT(0)
1140/** Guest software reads of this MSR must cause a VM-exit. */
1141#define VMXMSRPM_EXIT_RD RT_BIT(1)
1142/** Guest software writes to this MSR must not cause a VM-exit. */
1143#define VMXMSRPM_ALLOW_WR RT_BIT(2)
1144/** Guest software writes to this MSR must cause a VM-exit. */
1145#define VMXMSRPM_EXIT_WR RT_BIT(3)
1146/** Guest software reads or writes of this MSR must not cause a VM-exit. */
1147#define VMXMSRPM_ALLOW_RD_WR (VMXMSRPM_ALLOW_RD | VMXMSRPM_ALLOW_WR)
1148/** Guest software reads or writes of this MSR must cause a VM-exit. */
1149#define VMXMSRPM_EXIT_RD_WR (VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR)
1150/** Mask of valid MSR read permissions. */
1151#define VMXMSRPM_RD_MASK (VMXMSRPM_ALLOW_RD | VMXMSRPM_EXIT_RD)
1152/** Mask of valid MSR write permissions. */
1153#define VMXMSRPM_WR_MASK (VMXMSRPM_ALLOW_WR | VMXMSRPM_EXIT_WR)
1154/** Mask of valid MSR permissions. */
1155#define VMXMSRPM_MASK (VMXMSRPM_RD_MASK | VMXMSRPM_WR_MASK)
1156/** */
1157/** Gets whether the MSR permission is valid or not. */
1158#define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \
1159 && ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \
1160 && ((a_Msrpm) & VMXMSRPM_RD_MASK) != VMXMSRPM_RD_MASK \
1161 && ((a_Msrpm) & VMXMSRPM_WR_MASK) != VMXMSRPM_WR_MASK)
1162/** @} */
1163
1164/**
1165 * VMX MSR autoload/store slot.
1166 * In accordance with the VT-x spec.
1167 */
1168typedef struct VMXAUTOMSR
1169{
1170 /** The MSR Id. */
1171 uint32_t u32Msr;
1172 /** Reserved (MBZ). */
1173 uint32_t u32Reserved;
1174 /** The MSR value. */
1175 uint64_t u64Value;
1176} VMXAUTOMSR;
1177AssertCompileSize(VMXAUTOMSR, 16);
1178/** Pointer to an MSR load/store element. */
1179typedef VMXAUTOMSR *PVMXAUTOMSR;
1180/** Pointer to a const MSR load/store element. */
1181typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1182
1183/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1184#define VMX_AUTOMSR_OFFSET_MASK 0xf
1185
1186/**
1187 * VMX tagged-TLB flush types.
1188 */
1189typedef enum
1190{
1191 VMXTLBFLUSHTYPE_EPT,
1192 VMXTLBFLUSHTYPE_VPID,
1193 VMXTLBFLUSHTYPE_EPT_VPID,
1194 VMXTLBFLUSHTYPE_NONE
1195} VMXTLBFLUSHTYPE;
1196/** Pointer to a VMXTLBFLUSHTYPE enum. */
1197typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1198/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1199typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1200
1201/**
1202 * VMX controls MSR.
1203 * In accordance with the VT-x spec.
1204 */
1205typedef union
1206{
1207 struct
1208 {
1209 /** Bits set here -must- be set in the corresponding VM-execution controls. */
1210 uint32_t allowed0;
1211 /** Bits cleared here -must- be cleared in the corresponding VM-execution
1212 * controls. */
1213 uint32_t allowed1;
1214 } n;
1215 uint64_t u;
1216} VMXCTLSMSR;
1217AssertCompileSize(VMXCTLSMSR, 8);
1218/** Pointer to a VMXCTLSMSR union. */
1219typedef VMXCTLSMSR *PVMXCTLSMSR;
1220/** Pointer to a const VMXCTLSMSR union. */
1221typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1222
1223/**
1224 * VMX MSRs.
1225 */
1226typedef struct VMXMSRS
1227{
1228 /** Basic information. */
1229 uint64_t u64Basic;
1230 /** Pin-based VM-execution controls. */
1231 VMXCTLSMSR PinCtls;
1232 /** Processor-based VM-execution controls. */
1233 VMXCTLSMSR ProcCtls;
1234 /** Secondary processor-based VM-execution controls. */
1235 VMXCTLSMSR ProcCtls2;
1236 /** VM-exit controls. */
1237 VMXCTLSMSR ExitCtls;
1238 /** VM-entry controls. */
1239 VMXCTLSMSR EntryCtls;
1240 /** True pin-based VM-execution controls. */
1241 VMXCTLSMSR TruePinCtls;
1242 /** True processor-based VM-execution controls. */
1243 VMXCTLSMSR TrueProcCtls;
1244 /** True VM-entry controls. */
1245 VMXCTLSMSR TrueEntryCtls;
1246 /** True VM-exit controls. */
1247 VMXCTLSMSR TrueExitCtls;
1248 /** Miscellaneous data. */
1249 uint64_t u64Misc;
1250 /** CR0 fixed-0 - bits set here must be set in VMX operation. */
1251 uint64_t u64Cr0Fixed0;
1252 /** CR0 fixed-1 - bits clear here must be clear in VMX operation. */
1253 uint64_t u64Cr0Fixed1;
1254 /** CR4 fixed-0 - bits set here must be set in VMX operation. */
1255 uint64_t u64Cr4Fixed0;
1256 /** CR4 fixed-1 - bits clear here must be clear in VMX operation. */
1257 uint64_t u64Cr4Fixed1;
1258 /** VMCS enumeration. */
1259 uint64_t u64VmcsEnum;
1260 /** VM Functions. */
1261 uint64_t u64VmFunc;
1262 /** EPT, VPID capabilities. */
1263 uint64_t u64EptVpidCaps;
1264 /** Tertiary processor-based VM-execution controls. */
1265 uint64_t u64ProcCtls3;
1266 /** Reserved for future. */
1267 uint64_t a_u64Reserved[9];
1268} VMXMSRS;
1269AssertCompileSizeAlignment(VMXMSRS, 8);
1270AssertCompileSize(VMXMSRS, 224);
1271/** Pointer to a VMXMSRS struct. */
1272typedef VMXMSRS *PVMXMSRS;
1273/** Pointer to a const VMXMSRS struct. */
1274typedef const VMXMSRS *PCVMXMSRS;
1275
1276
1277/**
1278 * LBR MSRs.
1279 */
1280typedef struct LBRMSRS
1281{
1282 /** List of LastBranch-From-IP MSRs. */
1283 uint64_t au64BranchFromIpMsr[32];
1284 /** List of LastBranch-To-IP MSRs. */
1285 uint64_t au64BranchToIpMsr[32];
1286 /** The MSR containing the index to the most recent branch record. */
1287 uint64_t uBranchTosMsr;
1288} LBRMSRS;
1289AssertCompileSizeAlignment(LBRMSRS, 8);
1290/** Pointer to a VMXMSRS struct. */
1291typedef LBRMSRS *PLBRMSRS;
1292/** Pointer to a const VMXMSRS struct. */
1293typedef const LBRMSRS *PCLBRMSRS;
1294
1295
1296/** @name VMX Basic Exit Reasons.
1297 * In accordance with the VT-x spec.
1298 * Update g_aVMExitHandlers if new VM-exit reasons are added.
1299 * @{
1300 */
1301/** Invalid exit code */
1302#define VMX_EXIT_INVALID (-1)
1303/** Exception or non-maskable interrupt (NMI). */
1304#define VMX_EXIT_XCPT_OR_NMI 0
1305/** External interrupt. */
1306#define VMX_EXIT_EXT_INT 1
1307/** Triple fault. */
1308#define VMX_EXIT_TRIPLE_FAULT 2
1309/** INIT signal. */
1310#define VMX_EXIT_INIT_SIGNAL 3
1311/** Start-up IPI (SIPI). */
1312#define VMX_EXIT_SIPI 4
1313/** I/O system-management interrupt (SMI). */
1314#define VMX_EXIT_IO_SMI 5
1315/** Other SMI. */
1316#define VMX_EXIT_SMI 6
1317/** Interrupt window exiting. */
1318#define VMX_EXIT_INT_WINDOW 7
1319/** NMI window exiting. */
1320#define VMX_EXIT_NMI_WINDOW 8
1321/** Task switch. */
1322#define VMX_EXIT_TASK_SWITCH 9
1323/** CPUID. */
1324#define VMX_EXIT_CPUID 10
1325/** GETSEC. */
1326#define VMX_EXIT_GETSEC 11
1327/** HLT. */
1328#define VMX_EXIT_HLT 12
1329/** INVD. */
1330#define VMX_EXIT_INVD 13
1331/** INVLPG. */
1332#define VMX_EXIT_INVLPG 14
1333/** RDPMC. */
1334#define VMX_EXIT_RDPMC 15
1335/** RDTSC. */
1336#define VMX_EXIT_RDTSC 16
1337/** RSM in SMM. */
1338#define VMX_EXIT_RSM 17
1339/** VMCALL. */
1340#define VMX_EXIT_VMCALL 18
1341/** VMCLEAR. */
1342#define VMX_EXIT_VMCLEAR 19
1343/** VMLAUNCH. */
1344#define VMX_EXIT_VMLAUNCH 20
1345/** VMPTRLD. */
1346#define VMX_EXIT_VMPTRLD 21
1347/** VMPTRST. */
1348#define VMX_EXIT_VMPTRST 22
1349/** VMREAD. */
1350#define VMX_EXIT_VMREAD 23
1351/** VMRESUME. */
1352#define VMX_EXIT_VMRESUME 24
1353/** VMWRITE. */
1354#define VMX_EXIT_VMWRITE 25
1355/** VMXOFF. */
1356#define VMX_EXIT_VMXOFF 26
1357/** VMXON. */
1358#define VMX_EXIT_VMXON 27
1359/** Control-register accesses. */
1360#define VMX_EXIT_MOV_CRX 28
1361/** Debug-register accesses. */
1362#define VMX_EXIT_MOV_DRX 29
1363/** I/O instruction. */
1364#define VMX_EXIT_IO_INSTR 30
1365/** RDMSR. */
1366#define VMX_EXIT_RDMSR 31
1367/** WRMSR. */
1368#define VMX_EXIT_WRMSR 32
1369/** VM-entry failure due to invalid guest state. */
1370#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1371/** VM-entry failure due to MSR loading. */
1372#define VMX_EXIT_ERR_MSR_LOAD 34
1373/** MWAIT. */
1374#define VMX_EXIT_MWAIT 36
1375/** VM-exit due to monitor trap flag. */
1376#define VMX_EXIT_MTF 37
1377/** MONITOR. */
1378#define VMX_EXIT_MONITOR 39
1379/** PAUSE. */
1380#define VMX_EXIT_PAUSE 40
1381/** VM-entry failure due to machine-check. */
1382#define VMX_EXIT_ERR_MACHINE_CHECK 41
1383/** TPR below threshold. Guest software executed MOV to CR8. */
1384#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1385/** VM-exit due to guest accessing physical address in the APIC-access page. */
1386#define VMX_EXIT_APIC_ACCESS 44
1387/** VM-exit due to EOI virtualization. */
1388#define VMX_EXIT_VIRTUALIZED_EOI 45
1389/** Access to GDTR/IDTR using LGDT, LIDT, SGDT or SIDT. */
1390#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1391/** Access to LDTR/TR due to LLDT, LTR, SLDT, or STR. */
1392#define VMX_EXIT_LDTR_TR_ACCESS 47
1393/** EPT violation. */
1394#define VMX_EXIT_EPT_VIOLATION 48
1395/** EPT misconfiguration. */
1396#define VMX_EXIT_EPT_MISCONFIG 49
1397/** INVEPT. */
1398#define VMX_EXIT_INVEPT 50
1399/** RDTSCP. */
1400#define VMX_EXIT_RDTSCP 51
1401/** VMX-preemption timer expired. */
1402#define VMX_EXIT_PREEMPT_TIMER 52
1403/** INVVPID. */
1404#define VMX_EXIT_INVVPID 53
1405/** WBINVD. */
1406#define VMX_EXIT_WBINVD 54
1407/** XSETBV. */
1408#define VMX_EXIT_XSETBV 55
1409/** Guest completed write to virtual-APIC. */
1410#define VMX_EXIT_APIC_WRITE 56
1411/** RDRAND. */
1412#define VMX_EXIT_RDRAND 57
1413/** INVPCID. */
1414#define VMX_EXIT_INVPCID 58
1415/** VMFUNC. */
1416#define VMX_EXIT_VMFUNC 59
1417/** ENCLS. */
1418#define VMX_EXIT_ENCLS 60
1419/** RDSEED. */
1420#define VMX_EXIT_RDSEED 61
1421/** Page-modification log full. */
1422#define VMX_EXIT_PML_FULL 62
1423/** XSAVES. */
1424#define VMX_EXIT_XSAVES 63
1425/** XRSTORS. */
1426#define VMX_EXIT_XRSTORS 64
1427/** SPP-related event (SPP miss or misconfiguration). */
1428#define VMX_EXIT_SPP_EVENT 66
1429/* UMWAIT. */
1430#define VMX_EXIT_UMWAIT 67
1431/** TPAUSE. */
1432#define VMX_EXIT_TPAUSE 68
1433/** LOADIWKEY. */
1434#define VMX_EXIT_LOADIWKEY 69
1435/** The maximum VM-exit value (inclusive). */
1436#define VMX_EXIT_MAX (VMX_EXIT_LOADIWKEY)
1437/** @} */
1438
1439
1440/** @name VM Instruction Errors.
1441 * In accordance with the VT-x spec.
1442 * See Intel spec. "30.4 VM Instruction Error Numbers"
1443 * @{
1444 */
1445typedef enum
1446{
1447 /** VMCALL executed in VMX root operation. */
1448 VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1449 /** VMCLEAR with invalid physical address. */
1450 VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1451 /** VMCLEAR with VMXON pointer. */
1452 VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1453 /** VMLAUNCH with non-clear VMCS. */
1454 VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1455 /** VMRESUME with non-launched VMCS. */
1456 VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1457 /** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1458 VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1459 /** VM-entry with invalid control field(s). */
1460 VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1461 /** VM-entry with invalid host-state field(s). */
1462 VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1463 /** VMPTRLD with invalid physical address. */
1464 VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1465 /** VMPTRLD with VMXON pointer. */
1466 VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1467 /** VMPTRLD with incorrect VMCS revision identifier. */
1468 VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1469 /** VMREAD from unsupported VMCS component. */
1470 VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1471 /** VMWRITE to unsupported VMCS component. */
1472 VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1473 /** VMWRITE to read-only VMCS component. */
1474 VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1475 /** VMXON executed in VMX root operation. */
1476 VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1477 /** VM-entry with invalid executive-VMCS pointer. */
1478 VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1479 /** VM-entry with non-launched executive VMCS. */
1480 VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1481 /** VM-entry with executive-VMCS pointer not VMXON pointer. */
1482 VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1483 /** VMCALL with non-clear VMCS. */
1484 VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1485 /** VMCALL with invalid VM-exit control fields. */
1486 VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1487 /** VMCALL with incorrect MSEG revision identifier. */
1488 VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1489 /** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1490 VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1491 /** VMCALL with invalid SMM-monitor features. */
1492 VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1493 /** VM-entry with invalid VM-execution control fields in executive VMCS. */
1494 VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1495 /** VM-entry with events blocked by MOV SS. */
1496 VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1497 /** Invalid operand to INVEPT/INVVPID. */
1498 VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1499} VMXINSTRERR;
1500/** @} */
1501
1502
1503/** @name VMX abort reasons.
1504 * In accordance with the VT-x spec.
1505 * See Intel spec. "27.7 VMX Aborts".
1506 * Update HMGetVmxAbortDesc() if new reasons are added.
1507 * @{
1508 */
1509typedef enum
1510{
1511 /** None - don't use this / uninitialized value. */
1512 VMXABORT_NONE = 0,
1513 /** VMX abort caused during saving of guest MSRs. */
1514 VMXABORT_SAVE_GUEST_MSRS = 1,
1515 /** VMX abort caused during host PDPTE checks. */
1516 VMXBOART_HOST_PDPTE = 2,
1517 /** VMX abort caused due to current VMCS being corrupted. */
1518 VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1519 /** VMX abort caused during loading of host MSRs. */
1520 VMXABORT_LOAD_HOST_MSR = 4,
1521 /** VMX abort caused due to a machine-check exception during VM-exit. */
1522 VMXABORT_MACHINE_CHECK_XCPT = 5,
1523 /** VMX abort caused due to invalid return from long mode. */
1524 VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1525 /* Type size hack. */
1526 VMXABORT_32BIT_HACK = 0x7fffffff
1527} VMXABORT;
1528AssertCompileSize(VMXABORT, 4);
1529/** @} */
1530
1531
1532/** @name VMX MSR - Basic VMX information.
1533 * @{
1534 */
1535/** VMCS (and related regions) memory type - Uncacheable. */
1536#define VMX_BASIC_MEM_TYPE_UC 0
1537/** VMCS (and related regions) memory type - Write back. */
1538#define VMX_BASIC_MEM_TYPE_WB 6
1539/** Width of physical addresses used for VMCS and associated memory regions
1540 * (1=32-bit, 0=processor's physical address width). */
1541#define VMX_BASIC_PHYSADDR_WIDTH_32BIT RT_BIT_64(48)
1542
1543/** Bit fields for MSR_IA32_VMX_BASIC. */
1544/** VMCS revision identifier used by the processor. */
1545#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1546#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1547/** Bit 31 is reserved and RAZ. */
1548#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1549#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1550/** VMCS size in bytes. */
1551#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1552#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1553/** Bits 45:47 are reserved. */
1554#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1555#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1556/** Width of physical addresses used for the VMCS and associated memory regions
1557 * (always 0 on CPUs that support Intel 64 architecture). */
1558#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1559#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1560/** Dual-monitor treatment of SMI and SMM supported. */
1561#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1562#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1563/** Memory type that must be used for the VMCS and associated memory regions. */
1564#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1565#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1566/** VM-exit instruction information for INS/OUTS. */
1567#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1568#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1569/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1570 * bits in VMX control MSRs. */
1571#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1572#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1573/** Whether VM-entry can delivery error code for all hardware exception vectors. */
1574#define VMX_BF_BASIC_XCPT_ERRCODE_SHIFT 56
1575#define VMX_BF_BASIC_XCPT_ERRCODE_MASK UINT64_C(0x0100000000000000)
1576/** Bits 57:63 are reserved and RAZ. */
1577#define VMX_BF_BASIC_RSVD_56_63_SHIFT 57
1578#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xfe00000000000000)
1579RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1580 (VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1581 VMCS_INS_OUTS, TRUE_CTLS, XCPT_ERRCODE, RSVD_56_63));
1582/** @} */
1583
1584
1585/** @name VMX MSR - Miscellaneous data.
1586 * @{
1587 */
1588/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1589#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1590/** Whether Intel PT is supported in VMX operation. */
1591#define VMX_MISC_INTEL_PT RT_BIT(14)
1592/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1593 * VMWRITE cannot modify read-only VM-exit information fields. */
1594#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1595/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1596 * instructions. */
1597#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1598/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1599#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1600/** Maximum CR3-target count supported by the CPU. */
1601#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1602
1603/** Bit fields for MSR_IA32_VMX_MISC. */
1604/** Relationship between the preemption timer and tsc. */
1605#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1606#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1607/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1608#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1609#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1610/** Activity states supported by the implementation. */
1611#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1612#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1613/** Bits 9:13 is reserved and RAZ. */
1614#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1615#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1616/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1617#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1618#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1619/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1620#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1621#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1622/** Number of CR3 target values supported by the processor. (0-256) */
1623#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1624#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1625/** Maximum number of MSRs in the VMCS. */
1626#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1627#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1628/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1629 * SMIs. */
1630#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1631#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1632/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1633 * VMWRITE cannot modify read-only VM-exit information fields. */
1634#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1635#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1636/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1637 * instructions. */
1638#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1639#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1640/** Bit 31 is reserved and RAZ. */
1641#define VMX_BF_MISC_RSVD_31_SHIFT 31
1642#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1643/** 32-bit MSEG revision ID used by the processor. */
1644#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1645#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1646RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1647 (PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1648 CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1649/** @} */
1650
1651/** @name VMX MSR - VMCS enumeration.
1652 * Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1653 * @{
1654 */
1655/** Bit 0 is reserved and RAZ. */
1656#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1657#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1658/** Highest index value used in VMCS field encoding. */
1659#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1660#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1661/** Bit 10:63 is reserved and RAZ. */
1662#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1663#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1664RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1665 (RSVD_0, HIGHEST_IDX, RSVD_10_63));
1666/** @} */
1667
1668
1669/** @name VMX MSR - VM Functions.
1670 * Bit fields for MSR_IA32_VMX_VMFUNC.
1671 * @{
1672 */
1673/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1674#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1675#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1676/** Bits 1:63 are reserved and RAZ. */
1677#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1678#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1679RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1680 (EPTP_SWITCHING, RSVD_1_63));
1681/** @} */
1682
1683
1684/** @name VMX MSR - EPT/VPID capabilities.
1685 * @{
1686 */
1687/** Supports execute-only translations by EPT. */
1688#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1689/** Supports page-walk length of 4. */
1690#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1691/** Supports page-walk length of 5. */
1692#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5 RT_BIT_64(7)
1693/** Supports EPT paging-structure memory type to be uncacheable. */
1694#define MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC RT_BIT_64(8)
1695/** Supports EPT paging structure memory type to be write-back. */
1696#define MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB RT_BIT_64(14)
1697/** Supports EPT PDE to map a 2 MB page. */
1698#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1699/** Supports EPT PDPTE to map a 1 GB page. */
1700#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1701/** Supports INVEPT instruction. */
1702#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1703/** Supports accessed and dirty flags for EPT. */
1704#define MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY RT_BIT_64(21)
1705/** Supports advanced VM-exit info. for EPT violations. */
1706#define MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION RT_BIT_64(22)
1707/** Supports supervisor shadow-stack control. */
1708#define MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK RT_BIT_64(23)
1709/** Supports single-context INVEPT type. */
1710#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1711/** Supports all-context INVEPT type. */
1712#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1713/** Supports INVVPID instruction. */
1714#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1715/** Supports individual-address INVVPID type. */
1716#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1717/** Supports single-context INVVPID type. */
1718#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1719/** Supports all-context INVVPID type. */
1720#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1721/** Supports singe-context-retaining-globals INVVPID type. */
1722#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1723
1724/** Bit fields for MSR_IA32_VMX_EPT_VPID_CAP. */
1725#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_SHIFT 0
1726#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_MASK UINT64_C(0x0000000000000001)
1727#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_SHIFT 1
1728#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_MASK UINT64_C(0x000000000000003e)
1729#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_SHIFT 6
1730#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_MASK UINT64_C(0x0000000000000040)
1731#define VMX_BF_EPT_VPID_CAP_RSVD_7_SHIFT 7
1732#define VMX_BF_EPT_VPID_CAP_RSVD_7_MASK UINT64_C(0x0000000000000080)
1733#define VMX_BF_EPT_VPID_CAP_MEMTYPE_UC_SHIFT 8
1734#define VMX_BF_EPT_VPID_CAP_MEMTYPE_UC_MASK UINT64_C(0x0000000000000100)
1735#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_SHIFT 9
1736#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1737#define VMX_BF_EPT_VPID_CAP_MEMTYPE_WB_SHIFT 14
1738#define VMX_BF_EPT_VPID_CAP_MEMTYPE_WB_MASK UINT64_C(0x0000000000004000)
1739#define VMX_BF_EPT_VPID_CAP_RSVD_15_SHIFT 15
1740#define VMX_BF_EPT_VPID_CAP_RSVD_15_MASK UINT64_C(0x0000000000008000)
1741#define VMX_BF_EPT_VPID_CAP_PDE_2M_SHIFT 16
1742#define VMX_BF_EPT_VPID_CAP_PDE_2M_MASK UINT64_C(0x0000000000010000)
1743#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_SHIFT 17
1744#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_MASK UINT64_C(0x0000000000020000)
1745#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_SHIFT 18
1746#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_MASK UINT64_C(0x00000000000c0000)
1747#define VMX_BF_EPT_VPID_CAP_INVEPT_SHIFT 20
1748#define VMX_BF_EPT_VPID_CAP_INVEPT_MASK UINT64_C(0x0000000000100000)
1749#define VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY_SHIFT 21
1750#define VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY_MASK UINT64_C(0x0000000000200000)
1751#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION_SHIFT 22
1752#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION_MASK UINT64_C(0x0000000000400000)
1753#define VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK_SHIFT 23
1754#define VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK_MASK UINT64_C(0x0000000000800000)
1755#define VMX_BF_EPT_VPID_CAP_RSVD_24_SHIFT 24
1756#define VMX_BF_EPT_VPID_CAP_RSVD_24_MASK UINT64_C(0x0000000001000000)
1757#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_SHIFT 25
1758#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_MASK UINT64_C(0x0000000002000000)
1759#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_SHIFT 26
1760#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_MASK UINT64_C(0x0000000004000000)
1761#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_SHIFT 27
1762#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_MASK UINT64_C(0x00000000f8000000)
1763#define VMX_BF_EPT_VPID_CAP_INVVPID_SHIFT 32
1764#define VMX_BF_EPT_VPID_CAP_INVVPID_MASK UINT64_C(0x0000000100000000)
1765#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_SHIFT 33
1766#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_MASK UINT64_C(0x000000fe00000000)
1767#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_SHIFT 40
1768#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_MASK UINT64_C(0x0000010000000000)
1769#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_SHIFT 41
1770#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_MASK UINT64_C(0x0000020000000000)
1771#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_SHIFT 42
1772#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_MASK UINT64_C(0x0000040000000000)
1773#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_SHIFT 43
1774#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_MASK UINT64_C(0x0000080000000000)
1775#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_SHIFT 44
1776#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_MASK UINT64_C(0xfffff00000000000)
1777RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_VPID_CAP_, UINT64_C(0), UINT64_MAX,
1778 (RWX_X_ONLY, RSVD_1_5, PAGE_WALK_LENGTH_4, RSVD_7, MEMTYPE_UC, RSVD_9_13, MEMTYPE_WB, RSVD_15, PDE_2M,
1779 PDPTE_1G, RSVD_18_19, INVEPT, ACCESS_DIRTY, ADVEXITINFO_EPT_VIOLATION, SUPER_SHW_STACK, RSVD_24,
1780 INVEPT_SINGLE_CTX, INVEPT_ALL_CTX, RSVD_27_31, INVVPID, RSVD_33_39, INVVPID_INDIV_ADDR,
1781 INVVPID_SINGLE_CTX, INVVPID_ALL_CTX, INVVPID_SINGLE_CTX_RETAIN_GLOBALS, RSVD_44_63));
1782/** @} */
1783
1784
1785/** @name Extended Page Table Pointer (EPTP)
1786 * In accordance with the VT-x spec.
1787 * See Intel spec. 23.6.11 "Extended-Page-Table Pointer (EPTP)".
1788 * @{
1789 */
1790/** EPTP memory type: Uncachable. */
1791#define VMX_EPTP_MEMTYPE_UC 0
1792/** EPTP memory type: Write Back. */
1793#define VMX_EPTP_MEMTYPE_WB 6
1794/** Page-walk length for PML4 (4-level paging). */
1795#define VMX_EPTP_PAGE_WALK_LENGTH_4 3
1796
1797/** Bit fields for EPTP. */
1798#define VMX_BF_EPTP_MEMTYPE_SHIFT 0
1799#define VMX_BF_EPTP_MEMTYPE_MASK UINT64_C(0x0000000000000007)
1800#define VMX_BF_EPTP_PAGE_WALK_LENGTH_SHIFT 3
1801#define VMX_BF_EPTP_PAGE_WALK_LENGTH_MASK UINT64_C(0x0000000000000038)
1802#define VMX_BF_EPTP_ACCESS_DIRTY_SHIFT 6
1803#define VMX_BF_EPTP_ACCESS_DIRTY_MASK UINT64_C(0x0000000000000040)
1804#define VMX_BF_EPTP_SUPER_SHW_STACK_SHIFT 7
1805#define VMX_BF_EPTP_SUPER_SHW_STACK_MASK UINT64_C(0x0000000000000080)
1806#define VMX_BF_EPTP_RSVD_8_11_SHIFT 8
1807#define VMX_BF_EPTP_RSVD_8_11_MASK UINT64_C(0x0000000000000f00)
1808#define VMX_BF_EPTP_PML4_TABLE_ADDR_SHIFT 12
1809#define VMX_BF_EPTP_PML4_TABLE_ADDR_MASK UINT64_C(0xfffffffffffff000)
1810RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPTP_, UINT64_C(0), UINT64_MAX,
1811 (MEMTYPE, PAGE_WALK_LENGTH, ACCESS_DIRTY, SUPER_SHW_STACK, RSVD_8_11, PML4_TABLE_ADDR));
1812
1813/* Mask of valid EPTP bits sans physically non-addressable bits. */
1814#define VMX_EPTP_VALID_MASK ( VMX_BF_EPTP_MEMTYPE_MASK \
1815 | VMX_BF_EPTP_PAGE_WALK_LENGTH_MASK \
1816 | VMX_BF_EPTP_ACCESS_DIRTY_MASK \
1817 | VMX_BF_EPTP_SUPER_SHW_STACK_MASK \
1818 | VMX_BF_EPTP_PML4_TABLE_ADDR_MASK)
1819/** @} */
1820
1821
1822/** @name VMCS fields and encoding.
1823 *
1824 * When adding a new field:
1825 * - Always add it to g_aVmcsFields.
1826 * - Consider if it needs to be added to VMXVVMCS.
1827 * @{
1828 */
1829/** 16-bit control fields. */
1830#define VMX_VMCS16_VPID 0x0000
1831#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1832#define VMX_VMCS16_EPTP_INDEX 0x0004
1833
1834/** 16-bit guest-state fields. */
1835#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1836#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1837#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1838#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1839#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1840#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1841#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1842#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1843#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1844#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1845
1846/** 16-bits host-state fields. */
1847#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1848#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1849#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1850#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1851#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1852#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1853#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1854
1855/** 64-bit control fields. */
1856#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1857#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1858#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1859#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1860#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1861#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1862#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1863#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1864#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1865#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1866#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1867#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1868#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1869#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1870#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1871#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1872#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1873#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1874#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1875#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1876#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1877#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1878#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1879#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1880#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1881#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1882#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1883#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1884#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1885#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1886#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1887#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1888#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1889#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1890#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1891#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1892#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1893#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1894#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1895#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1896#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1897#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1898#define VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_FULL 0x202a
1899#define VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_HIGH 0x202b
1900#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1901#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1902#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1903#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1904#define VMX_VMCS64_CTRL_SPPTP_FULL 0x2030
1905#define VMX_VMCS64_CTRL_SPPTP_HIGH 0x2031
1906#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1907#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1908#define VMX_VMCS64_CTRL_PROC_EXEC3_FULL 0x2034
1909#define VMX_VMCS64_CTRL_PROC_EXEC3_HIGH 0x2035
1910#define VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_FULL 0x2036
1911#define VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_HIGH 0x2037
1912
1913/** 64-bit read-only data fields. */
1914#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1915#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1916
1917/** 64-bit guest-state fields. */
1918#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1919#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1920#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1921#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1922#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1923#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1924#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1925#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1926#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1927#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1928#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1929#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1930#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1931#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1932#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1933#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1934#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1935#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1936#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1937#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1938#define VMX_VMCS64_GUEST_RTIT_CTL_FULL 0x2814
1939#define VMX_VMCS64_GUEST_RTIT_CTL_HIGH 0x2815
1940#define VMX_VMCS64_GUEST_PKRS_FULL 0x2818
1941#define VMX_VMCS64_GUEST_PKRS_HIGH 0x2819
1942
1943/** 64-bit host-state fields. */
1944#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1945#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1946#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1947#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1948#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1949#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1950#define VMX_VMCS64_HOST_PKRS_FULL 0x2c06
1951#define VMX_VMCS64_HOST_PKRS_HIGH 0x2c07
1952
1953/** 32-bit control fields. */
1954#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1955#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1956#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1957#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1958#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1959#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1960#define VMX_VMCS32_CTRL_EXIT 0x400c
1961#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1962#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1963#define VMX_VMCS32_CTRL_ENTRY 0x4012
1964#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1965#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1966#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1967#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1968#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1969#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1970#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1971#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1972
1973/** 32-bits read-only fields. */
1974#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1975#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1976#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1977#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1978#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1979#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1980#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1981#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1982
1983/** 32-bit guest-state fields. */
1984#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1985#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1986#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1987#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1988#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1989#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1990#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1991#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1992#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1993#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1994#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1995#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1996#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1997#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1998#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1999#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
2000#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
2001#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
2002#define VMX_VMCS32_GUEST_INT_STATE 0x4824
2003#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
2004#define VMX_VMCS32_GUEST_SMBASE 0x4828
2005#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
2006#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
2007
2008/** 32-bit host-state fields. */
2009#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
2010
2011/** Natural-width control fields. */
2012#define VMX_VMCS_CTRL_CR0_MASK 0x6000
2013#define VMX_VMCS_CTRL_CR4_MASK 0x6002
2014#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
2015#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
2016#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
2017#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
2018#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
2019#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
2020
2021/** Natural-width read-only data fields. */
2022#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
2023#define VMX_VMCS_RO_IO_RCX 0x6402
2024#define VMX_VMCS_RO_IO_RSI 0x6404
2025#define VMX_VMCS_RO_IO_RDI 0x6406
2026#define VMX_VMCS_RO_IO_RIP 0x6408
2027#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
2028
2029/** Natural-width guest-state fields. */
2030#define VMX_VMCS_GUEST_CR0 0x6800
2031#define VMX_VMCS_GUEST_CR3 0x6802
2032#define VMX_VMCS_GUEST_CR4 0x6804
2033#define VMX_VMCS_GUEST_ES_BASE 0x6806
2034#define VMX_VMCS_GUEST_CS_BASE 0x6808
2035#define VMX_VMCS_GUEST_SS_BASE 0x680a
2036#define VMX_VMCS_GUEST_DS_BASE 0x680c
2037#define VMX_VMCS_GUEST_FS_BASE 0x680e
2038#define VMX_VMCS_GUEST_GS_BASE 0x6810
2039#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
2040#define VMX_VMCS_GUEST_TR_BASE 0x6814
2041#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
2042#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
2043#define VMX_VMCS_GUEST_DR7 0x681a
2044#define VMX_VMCS_GUEST_RSP 0x681c
2045#define VMX_VMCS_GUEST_RIP 0x681e
2046#define VMX_VMCS_GUEST_RFLAGS 0x6820
2047#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
2048#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
2049#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
2050#define VMX_VMCS_GUEST_S_CET 0x6828
2051#define VMX_VMCS_GUEST_SSP 0x682a
2052#define VMX_VMCS_GUEST_INTR_SSP_TABLE_ADDR 0x682c
2053
2054/** Natural-width host-state fields. */
2055#define VMX_VMCS_HOST_CR0 0x6c00
2056#define VMX_VMCS_HOST_CR3 0x6c02
2057#define VMX_VMCS_HOST_CR4 0x6c04
2058#define VMX_VMCS_HOST_FS_BASE 0x6c06
2059#define VMX_VMCS_HOST_GS_BASE 0x6c08
2060#define VMX_VMCS_HOST_TR_BASE 0x6c0a
2061#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
2062#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
2063#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
2064#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
2065#define VMX_VMCS_HOST_RSP 0x6c14
2066#define VMX_VMCS_HOST_RIP 0x6c16
2067#define VMX_VMCS_HOST_S_CET 0x6c18
2068#define VMX_VMCS_HOST_SSP 0x6c1a
2069#define VMX_VMCS_HOST_INTR_SSP_TABLE_ADDR 0x6c1c
2070
2071#define VMX_VMCS16_GUEST_SEG_SEL(a_iSegReg) (VMX_VMCS16_GUEST_ES_SEL + (a_iSegReg) * 2)
2072#define VMX_VMCS_GUEST_SEG_BASE(a_iSegReg) (VMX_VMCS_GUEST_ES_BASE + (a_iSegReg) * 2)
2073#define VMX_VMCS32_GUEST_SEG_LIMIT(a_iSegReg) (VMX_VMCS32_GUEST_ES_LIMIT + (a_iSegReg) * 2)
2074#define VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(a_iSegReg) (VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS + (a_iSegReg) * 2)
2075
2076/**
2077 * VMCS field.
2078 * In accordance with the VT-x spec.
2079 */
2080typedef union
2081{
2082 struct
2083 {
2084 /** The access type; 0=full, 1=high of 64-bit fields. */
2085 uint32_t fAccessType : 1;
2086 /** The index. */
2087 uint32_t u8Index : 8;
2088 /** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
2089 uint32_t u2Type : 2;
2090 /** Reserved (MBZ). */
2091 uint32_t u1Reserved0 : 1;
2092 /** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
2093 uint32_t u2Width : 2;
2094 /** Reserved (MBZ). */
2095 uint32_t u18Reserved0 : 18;
2096 } n;
2097
2098 /* The unsigned integer view. */
2099 uint32_t u;
2100} VMXVMCSFIELD;
2101AssertCompileSize(VMXVMCSFIELD, 4);
2102/** Pointer to a VMCS field. */
2103typedef VMXVMCSFIELD *PVMXVMCSFIELD;
2104/** Pointer to a const VMCS field. */
2105typedef const VMXVMCSFIELD *PCVMXVMCSFIELD;
2106
2107/** VMCS field: Mask of reserved bits (bits 63:15 MBZ), bit 12 is not included! */
2108#define VMX_VMCSFIELD_RSVD_MASK UINT64_C(0xffffffffffff8000)
2109
2110/** Bits fields for a VMCS field. */
2111#define VMX_BF_VMCSFIELD_ACCESS_TYPE_SHIFT 0
2112#define VMX_BF_VMCSFIELD_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2113#define VMX_BF_VMCSFIELD_INDEX_SHIFT 1
2114#define VMX_BF_VMCSFIELD_INDEX_MASK UINT32_C(0x000003fe)
2115#define VMX_BF_VMCSFIELD_TYPE_SHIFT 10
2116#define VMX_BF_VMCSFIELD_TYPE_MASK UINT32_C(0x00000c00)
2117#define VMX_BF_VMCSFIELD_RSVD_12_SHIFT 12
2118#define VMX_BF_VMCSFIELD_RSVD_12_MASK UINT32_C(0x00001000)
2119#define VMX_BF_VMCSFIELD_WIDTH_SHIFT 13
2120#define VMX_BF_VMCSFIELD_WIDTH_MASK UINT32_C(0x00006000)
2121#define VMX_BF_VMCSFIELD_RSVD_15_31_SHIFT 15
2122#define VMX_BF_VMCSFIELD_RSVD_15_31_MASK UINT32_C(0xffff8000)
2123RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCSFIELD_, UINT32_C(0), UINT32_MAX,
2124 (ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2125
2126/**
2127 * VMCS field encoding: Access type.
2128 * In accordance with the VT-x spec.
2129 */
2130typedef enum
2131{
2132 VMXVMCSFIELDACCESS_FULL = 0,
2133 VMXVMCSFIELDACCESS_HIGH
2134} VMXVMCSFIELDACCESS;
2135AssertCompileSize(VMXVMCSFIELDACCESS, 4);
2136/** VMCS field encoding type: Full. */
2137#define VMX_VMCSFIELD_ACCESS_FULL 0
2138/** VMCS field encoding type: High. */
2139#define VMX_VMCSFIELD_ACCESS_HIGH 1
2140
2141/**
2142 * VMCS field encoding: Type.
2143 * In accordance with the VT-x spec.
2144 */
2145typedef enum
2146{
2147 VMXVMCSFIELDTYPE_CONTROL = 0,
2148 VMXVMCSFIELDTYPE_VMEXIT_INFO,
2149 VMXVMCSFIELDTYPE_GUEST_STATE,
2150 VMXVMCSFIELDTYPE_HOST_STATE
2151} VMXVMCSFIELDTYPE;
2152AssertCompileSize(VMXVMCSFIELDTYPE, 4);
2153/** VMCS field encoding type: Control. */
2154#define VMX_VMCSFIELD_TYPE_CONTROL 0
2155/** VMCS field encoding type: VM-exit information / read-only fields. */
2156#define VMX_VMCSFIELD_TYPE_VMEXIT_INFO 1
2157/** VMCS field encoding type: Guest-state. */
2158#define VMX_VMCSFIELD_TYPE_GUEST_STATE 2
2159/** VMCS field encoding type: Host-state. */
2160#define VMX_VMCSFIELD_TYPE_HOST_STATE 3
2161
2162/**
2163 * VMCS field encoding: Width.
2164 * In accordance with the VT-x spec.
2165 */
2166typedef enum
2167{
2168 VMXVMCSFIELDWIDTH_16BIT = 0,
2169 VMXVMCSFIELDWIDTH_64BIT,
2170 VMXVMCSFIELDWIDTH_32BIT,
2171 VMXVMCSFIELDWIDTH_NATURAL
2172} VMXVMCSFIELDWIDTH;
2173AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
2174/** VMCS field encoding width: 16-bit. */
2175#define VMX_VMCSFIELD_WIDTH_16BIT 0
2176/** VMCS field encoding width: 64-bit. */
2177#define VMX_VMCSFIELD_WIDTH_64BIT 1
2178/** VMCS field encoding width: 32-bit. */
2179#define VMX_VMCSFIELD_WIDTH_32BIT 2
2180/** VMCS field encoding width: Natural width. */
2181#define VMX_VMCSFIELD_WIDTH_NATURAL 3
2182/** @} */
2183
2184
2185/** @name VM-entry instruction length.
2186 * @{ */
2187/** The maximum valid value for VM-entry instruction length while injecting a
2188 * software interrupt, software exception or privileged software exception. */
2189#define VMX_ENTRY_INSTR_LEN_MAX 15
2190/** @} */
2191
2192
2193/** @name VM-entry register masks.
2194 * @{ */
2195/** CR0 bits ignored on VM-entry while loading guest CR0 (ET, CD, NW, bits 6:15,
2196 * bit 17 and bits 19:28). */
2197#define VMX_ENTRY_GUEST_CR0_IGNORE_MASK UINT64_C(0x7ffaffd0)
2198/** DR7 bits set here are always cleared on VM-entry while loading guest DR7 (bit
2199 * 12, bits 14:15). */
2200#define VMX_ENTRY_GUEST_DR7_MBZ_MASK UINT64_C(0xd000)
2201/** DR7 bits set here are always set on VM-entry while loading guest DR7 (bit
2202 * 10). */
2203#define VMX_ENTRY_GUEST_DR7_MB1_MASK UINT64_C(0x400)
2204/** @} */
2205
2206
2207/** @name VM-exit register masks.
2208 * @{ */
2209/** CR0 bits ignored on VM-exit while loading host CR0 (ET, CD, NW, bits 6:15,
2210 * bit 17, bits 19:28 and bits 32:63). */
2211#define VMX_EXIT_HOST_CR0_IGNORE_MASK UINT64_C(0xffffffff7ffaffd0)
2212/** @} */
2213
2214
2215/** @name Pin-based VM-execution controls.
2216 * @{
2217 */
2218/** External interrupt exiting. */
2219#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
2220/** NMI exiting. */
2221#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
2222/** Virtual NMIs. */
2223#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
2224/** Activate VMX preemption timer. */
2225#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
2226/** Process interrupts with the posted-interrupt notification vector. */
2227#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
2228/** Default1 class when true capability MSRs are not supported. */
2229#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
2230
2231/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
2232 * controls field in the VMCS. */
2233#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
2234#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
2235#define VMX_BF_PIN_CTLS_RSVD_1_2_SHIFT 1
2236#define VMX_BF_PIN_CTLS_RSVD_1_2_MASK UINT32_C(0x00000006)
2237#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
2238#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
2239#define VMX_BF_PIN_CTLS_RSVD_4_SHIFT 4
2240#define VMX_BF_PIN_CTLS_RSVD_4_MASK UINT32_C(0x00000010)
2241#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
2242#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
2243#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
2244#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
2245#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
2246#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
2247#define VMX_BF_PIN_CTLS_RSVD_8_31_SHIFT 8
2248#define VMX_BF_PIN_CTLS_RSVD_8_31_MASK UINT32_C(0xffffff00)
2249RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
2250 (EXT_INT_EXIT, RSVD_1_2, NMI_EXIT, RSVD_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, RSVD_8_31));
2251/** @} */
2252
2253
2254/** @name Processor-based VM-execution controls.
2255 * @{
2256 */
2257/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
2258#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
2259/** Use timestamp counter offset. */
2260#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
2261/** VM-exit when executing the HLT instruction. */
2262#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
2263/** VM-exit when executing the INVLPG instruction. */
2264#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
2265/** VM-exit when executing the MWAIT instruction. */
2266#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
2267/** VM-exit when executing the RDPMC instruction. */
2268#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
2269/** VM-exit when executing the RDTSC/RDTSCP instruction. */
2270#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
2271/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
2272 * 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2273#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
2274/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
2275 * 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2276#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
2277/** Whether the secondary processor based VM-execution controls are used. */
2278#define VMX_PROC_CTLS_USE_TERTIARY_CTLS RT_BIT(17)
2279/** VM-exit on CR8 loads. */
2280#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
2281/** VM-exit on CR8 stores. */
2282#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
2283/** Use TPR shadow. */
2284#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
2285/** VM-exit when virtual NMI blocking is disabled. */
2286#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
2287/** VM-exit when executing a MOV DRx instruction. */
2288#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
2289/** VM-exit when executing IO instructions. */
2290#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
2291/** Use IO bitmaps. */
2292#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
2293/** Monitor trap flag. */
2294#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2295/** Use MSR bitmaps. */
2296#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2297/** VM-exit when executing the MONITOR instruction. */
2298#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2299/** VM-exit when executing the PAUSE instruction. */
2300#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2301/** Whether the secondary processor based VM-execution controls are used. */
2302#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2303/** Default1 class when true-capability MSRs are not supported. */
2304#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2305
2306/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2307 * controls field in the VMCS. */
2308#define VMX_BF_PROC_CTLS_RSVD_0_1_SHIFT 0
2309#define VMX_BF_PROC_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2310#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2311#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2312#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2313#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2314#define VMX_BF_PROC_CTLS_RSVD_4_6_SHIFT 4
2315#define VMX_BF_PROC_CTLS_RSVD_4_6_MASK UINT32_C(0x00000070)
2316#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2317#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2318#define VMX_BF_PROC_CTLS_RSVD_8_SHIFT 8
2319#define VMX_BF_PROC_CTLS_RSVD_8_MASK UINT32_C(0x00000100)
2320#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2321#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2322#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2323#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2324#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2325#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2326#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2327#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2328#define VMX_BF_PROC_CTLS_RSVD_13_14_SHIFT 13
2329#define VMX_BF_PROC_CTLS_RSVD_13_14_MASK UINT32_C(0x00006000)
2330#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2331#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2332#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2333#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2334#define VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT 17
2335#define VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_MASK UINT32_C(0x00020000)
2336#define VMX_BF_PROC_CTLS_RSVD_18_SHIFT 18
2337#define VMX_BF_PROC_CTLS_RSVD_18_MASK UINT32_C(0x00040000)
2338#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2339#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2340#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2341#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2342#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2343#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2344#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2345#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2346#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2347#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2348#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2349#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2350#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2351#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2352#define VMX_BF_PROC_CTLS_RSVD_26_SHIFT 26
2353#define VMX_BF_PROC_CTLS_RSVD_26_MASK UINT32_C(0x4000000)
2354#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2355#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2356#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2357#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2358#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2359#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2360#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2361#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2362#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2363#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2364RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2365 (RSVD_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, RSVD_4_6, HLT_EXIT, RSVD_8, INVLPG_EXIT,
2366 MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, RSVD_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, USE_TERTIARY_CTLS,
2367 RSVD_18, CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2368 USE_IO_BITMAPS, RSVD_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2369 USE_SECONDARY_CTLS));
2370/** @} */
2371
2372
2373/** @name Secondary Processor-based VM-execution controls.
2374 * @{
2375 */
2376/** Virtualize APIC accesses. */
2377#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2378/** EPT supported/enabled. */
2379#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2380/** Descriptor table instructions cause VM-exits. */
2381#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2382/** RDTSCP supported/enabled. */
2383#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2384/** Virtualize x2APIC mode. */
2385#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2386/** VPID supported/enabled. */
2387#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2388/** VM-exit when executing the WBINVD instruction. */
2389#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2390/** Unrestricted guest execution. */
2391#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2392/** APIC register virtualization. */
2393#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2394/** Virtual-interrupt delivery. */
2395#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2396/** A specified number of pause loops cause a VM-exit. */
2397#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2398/** VM-exit when executing RDRAND instructions. */
2399#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2400/** Enables INVPCID instructions. */
2401#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2402/** Enables VMFUNC instructions. */
2403#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2404/** Enables VMCS shadowing. */
2405#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2406/** Enables ENCLS VM-exits. */
2407#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2408/** VM-exit when executing RDSEED. */
2409#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2410/** Enables page-modification logging. */
2411#define VMX_PROC_CTLS2_PML RT_BIT(17)
2412/** Controls whether EPT-violations may cause \#VE instead of exits. */
2413#define VMX_PROC_CTLS2_EPT_XCPT_VE RT_BIT(18)
2414/** Conceal VMX non-root operation from Intel processor trace (PT). */
2415#define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19)
2416/** Enables XSAVES/XRSTORS instructions. */
2417#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2418/** Enables supervisor/user mode based EPT execute permission for linear
2419 * addresses. */
2420#define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22)
2421/** Enables EPT write permissions to be specified at granularity of 128 bytes. */
2422#define VMX_PROC_CTLS2_SPP_EPT RT_BIT(23)
2423/** Intel PT output addresses are treated as guest-physical addresses and
2424 * translated using EPT. */
2425#define VMX_PROC_CTLS2_PT_EPT RT_BIT(24)
2426/** Use TSC scaling. */
2427#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2428/** Enables TPAUSE, UMONITOR and UMWAIT instructions. */
2429#define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26)
2430/** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */
2431#define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28)
2432
2433/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2434 * VM-execution controls field in the VMCS. */
2435#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2436#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2437#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2438#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2439#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2440#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2441#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2442#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2443#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2444#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2445#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2446#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2447#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2448#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2449#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2450#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2451#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2452#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2453#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2454#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2455#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2456#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2457#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2458#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2459#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2460#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2461#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2462#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2463#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2464#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2465#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2466#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2467#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2468#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2469#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2470#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2471#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2472#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2473#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19
2474#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000)
2475#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2476#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2477#define VMX_BF_PROC_CTLS2_RSVD_21_SHIFT 21
2478#define VMX_BF_PROC_CTLS2_RSVD_21_MASK UINT32_C(0x00200000)
2479#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22
2480#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000)
2481#define VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT 23
2482#define VMX_BF_PROC_CTLS2_SPP_EPT_MASK UINT32_C(0x00800000)
2483#define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24
2484#define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000)
2485#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2486#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2487#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26
2488#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000)
2489#define VMX_BF_PROC_CTLS2_RSVD_27_SHIFT 27
2490#define VMX_BF_PROC_CTLS2_RSVD_27_MASK UINT32_C(0x08000000)
2491#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28
2492#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000)
2493#define VMX_BF_PROC_CTLS2_RSVD_29_31_SHIFT 29
2494#define VMX_BF_PROC_CTLS2_RSVD_29_31_MASK UINT32_C(0xe0000000)
2495
2496RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2497 (VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2498 UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2499 VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, RSVD_21,
2500 MODE_BASED_EPT_PERM, SPP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, RSVD_27, ENCLV_EXIT,
2501 RSVD_29_31));
2502/** @} */
2503
2504
2505/** @name Tertiary Processor-based VM-execution controls.
2506 * @{
2507 */
2508/** VM-exit when executing LOADIWKEY. */
2509#define VMX_PROC_CTLS3_LOADIWKEY_EXIT RT_BIT_64(0)
2510
2511/** Bit fields for Tertiary processor-based VM-execution controls field in the VMCS. */
2512#define VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT 0
2513#define VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_MASK UINT64_C(0x0000000000000001)
2514#define VMX_BF_PROC_CTLS3_RSVD_1_63_SHIFT 1
2515#define VMX_BF_PROC_CTLS3_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
2516
2517RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS3_, UINT64_C(0), UINT64_MAX,
2518 (LOADIWKEY_EXIT, RSVD_1_63));
2519/** @} */
2520
2521
2522/** @name VM-entry controls.
2523 * @{
2524 */
2525/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2526 * 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2527#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2528/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2529#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2530/** In SMM mode after VM-entry. */
2531#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2532/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2533#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2534/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2535#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2536/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2537#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2538/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2539#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2540/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2541#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2542/** Whether to conceal VMX from Intel PT (Processor Trace). */
2543#define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17)
2544/** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
2545#define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18)
2546/** Whether the guest CET-related MSRs and SPP are loaded on VM-entry. */
2547#define VMX_ENTRY_CTLS_LOAD_CET_STATE RT_BIT(20)
2548/** Whether the guest IA32_PKRS MSR is loaded on VM-entry. */
2549#define VMX_ENTRY_CTLS_LOAD_PKRS_MSR RT_BIT(22)
2550/** Default1 class when true-capability MSRs are not supported. */
2551#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2552
2553/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2554 * VMCS. */
2555#define VMX_BF_ENTRY_CTLS_RSVD_0_1_SHIFT 0
2556#define VMX_BF_ENTRY_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2557#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2558#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2559#define VMX_BF_ENTRY_CTLS_RSVD_3_8_SHIFT 3
2560#define VMX_BF_ENTRY_CTLS_RSVD_3_8_MASK UINT32_C(0x000001f8)
2561#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2562#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2563#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2564#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2565#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2566#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2567#define VMX_BF_ENTRY_CTLS_RSVD_12_SHIFT 12
2568#define VMX_BF_ENTRY_CTLS_RSVD_12_MASK UINT32_C(0x00001000)
2569#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2570#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2571#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2572#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2573#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2574#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2575#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2576#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2577#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17
2578#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000)
2579#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18
2580#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000)
2581#define VMX_BF_ENTRY_CTLS_RSVD_19_SHIFT 19
2582#define VMX_BF_ENTRY_CTLS_RSVD_19_MASK UINT32_C(0x00080000)
2583#define VMX_BF_ENTRY_CTLS_LOAD_CET_SHIFT 20
2584#define VMX_BF_ENTRY_CTLS_LOAD_CET_MASK UINT32_C(0x00100000)
2585#define VMX_BF_ENTRY_CTLS_RSVD_21_SHIFT 21
2586#define VMX_BF_ENTRY_CTLS_RSVD_21_MASK UINT32_C(0x00200000)
2587#define VMX_BF_ENTRY_CTLS_LOAD_PKRS_MSR_SHIFT 22
2588#define VMX_BF_ENTRY_CTLS_LOAD_PKRS_MSR_MASK UINT32_C(0x00400000)
2589#define VMX_BF_ENTRY_CTLS_RSVD_23_31_SHIFT 23
2590#define VMX_BF_ENTRY_CTLS_RSVD_23_31_MASK UINT32_C(0xff800000)
2591
2592RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2593 (RSVD_0_1, LOAD_DEBUG, RSVD_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, RSVD_12,
2594 LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
2595 LOAD_RTIT_CTL_MSR, RSVD_19, LOAD_CET, RSVD_21, LOAD_PKRS_MSR, RSVD_23_31));
2596/** @} */
2597
2598
2599/** @name VM-exit controls.
2600 * @{
2601 */
2602/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2603 * 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2604#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2605/** Return to long mode after a VM-exit. */
2606#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2607/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2608#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2609/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2610#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2611/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2612#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2613/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2614#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2615/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2616#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2617/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2618#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2619/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2620#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2621/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2622#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2623/** Whether to conceal VMX from Intel PT. */
2624#define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24)
2625/** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
2626#define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25)
2627/** Whether CET-related MSRs and SPP are loaded on VM-exit. */
2628#define VMX_EXIT_CTLS_LOAD_CET_STATE RT_BIT(28)
2629/** Whether the host IA32_PKRS MSR is loaded on VM-exit. */
2630#define VMX_EXIT_CTLS_LOAD_PKRS_MSR RT_BIT(29)
2631/** Default1 class when true-capability MSRs are not supported. */
2632#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2633
2634/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2635 * VMCS. */
2636#define VMX_BF_EXIT_CTLS_RSVD_0_1_SHIFT 0
2637#define VMX_BF_EXIT_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2638#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2639#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2640#define VMX_BF_EXIT_CTLS_RSVD_3_8_SHIFT 3
2641#define VMX_BF_EXIT_CTLS_RSVD_3_8_MASK UINT32_C(0x000001f8)
2642#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2643#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2644#define VMX_BF_EXIT_CTLS_RSVD_10_11_SHIFT 10
2645#define VMX_BF_EXIT_CTLS_RSVD_10_11_MASK UINT32_C(0x00000c00)
2646#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2647#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2648#define VMX_BF_EXIT_CTLS_RSVD_13_14_SHIFT 13
2649#define VMX_BF_EXIT_CTLS_RSVD_13_14_MASK UINT32_C(0x00006000)
2650#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2651#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2652#define VMX_BF_EXIT_CTLS_RSVD_16_17_SHIFT 16
2653#define VMX_BF_EXIT_CTLS_RSVD_16_17_MASK UINT32_C(0x00030000)
2654#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2655#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2656#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2657#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2658#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2659#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2660#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2661#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2662#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2663#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2664#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23
2665#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000)
2666#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24
2667#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000)
2668#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25
2669#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000)
2670#define VMX_BF_EXIT_CTLS_RSVD_26_27_SHIFT 26
2671#define VMX_BF_EXIT_CTLS_RSVD_26_27_MASK UINT32_C(0x0c000000)
2672#define VMX_BF_EXIT_CTLS_LOAD_CET_SHIFT 28
2673#define VMX_BF_EXIT_CTLS_LOAD_CET_MASK UINT32_C(0x10000000)
2674#define VMX_BF_EXIT_CTLS_LOAD_PKRS_MSR_SHIFT 29
2675#define VMX_BF_EXIT_CTLS_LOAD_PKRS_MSR_MASK UINT32_C(0x20000000)
2676#define VMX_BF_EXIT_CTLS_RSVD_30_31_SHIFT 30
2677#define VMX_BF_EXIT_CTLS_RSVD_30_31_MASK UINT32_C(0xc0000000)
2678RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2679 (RSVD_0_1, SAVE_DEBUG, RSVD_3_8, HOST_ADDR_SPACE_SIZE, RSVD_10_11, LOAD_PERF_MSR, RSVD_13_14,
2680 ACK_EXT_INT, RSVD_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2681 SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, RSVD_26_27,
2682 LOAD_CET, LOAD_PKRS_MSR, RSVD_30_31));
2683/** @} */
2684
2685
2686/** @name VM-exit reason.
2687 * @{
2688 */
2689#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2690#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2691#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2692
2693/** Bit fields for VM-exit reason. */
2694/** The exit reason. */
2695#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2696#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2697/** Bits 16:26 are reseved and MBZ. */
2698#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2699#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2700/** Whether the VM-exit was incident to enclave mode. */
2701#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2702#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2703/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2704#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2705#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2706/** VM-exit from VMX root operation (only possible with SMM). */
2707#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2708#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2709/** Bit 30 is reserved and MBZ. */
2710#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2711#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2712/** Whether VM-entry failed (currently only happens during loading guest-state
2713 * or MSRs or machine check exceptions). */
2714#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2715#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2716RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2717 (BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2718/** @} */
2719
2720
2721/** @name VM-entry interruption information.
2722 * @{
2723 */
2724#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2725#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2726#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2727#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2728#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2729#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2730#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2731#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2732#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2733#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2734/** Construct an VM-entry interruption information field from a VM-exit interruption
2735 * info value (same except that bit 12 is reserved). */
2736#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2737/** Construct a VM-entry interruption information field from an IDT-vectoring
2738 * information field (same except that bit 12 is reserved). */
2739#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2740/** If the VM-entry interruption information field indicates a page-fault. */
2741#define VMX_ENTRY_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2742 | VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2743 | VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2744 == ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2745 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT) \
2746 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_PF)))
2747/** If the VM-entry interruption information field indicates an external
2748 * interrupt. */
2749#define VMX_ENTRY_INT_INFO_IS_EXT_INT(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2750 | VMX_BF_ENTRY_INT_INFO_TYPE_MASK)) \
2751 == ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2752 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_EXT_INT)))
2753/** If the VM-entry interruption information field indicates an NMI. */
2754#define VMX_ENTRY_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2755 | VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2756 | VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2757 == ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2758 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_NMI) \
2759 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_NMI)))
2760
2761/** Bit fields for VM-entry interruption information. */
2762/** The VM-entry interruption vector. */
2763#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2764#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2765/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2766#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2767#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2768/** Whether this event has an error code. */
2769#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2770#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2771/** Bits 12:30 are reserved and MBZ. */
2772#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2773#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2774/** Whether this VM-entry interruption info is valid. */
2775#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2776#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2777RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2778 (VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2779/** @} */
2780
2781
2782/** @name VM-entry exception error code.
2783 * @{ */
2784/** Error code valid mask. */
2785/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2786 * bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2787 * stack aligned for doubleword pushes, the upper half of the error code is
2788 * reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2789 * use below. */
2790#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2791/** @} */
2792
2793/** @name VM-entry interruption information types.
2794 * @{
2795 */
2796#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2797#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2798#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2799#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2800#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2801#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2802#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2803#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2804/** @} */
2805
2806
2807/** @name VM-entry interruption information vector types for
2808 * VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2809 * @{ */
2810#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2811/** @} */
2812
2813
2814/** @name VM-exit interruption information.
2815 * @{
2816 */
2817#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2818#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2819#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2820#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2821#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2822#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2823#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2824#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2825#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2826
2827/** If the VM-exit interruption information field indicates an page-fault. */
2828#define VMX_EXIT_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2829 | VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2830 | VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2831 == ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2832 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2833 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_PF)))
2834/** If the VM-exit interruption information field indicates an double-fault. */
2835#define VMX_EXIT_INT_INFO_IS_XCPT_DF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2836 | VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2837 | VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2838 == ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2839 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2840 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)))
2841/** If the VM-exit interruption information field indicates an NMI. */
2842#define VMX_EXIT_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2843 | VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2844 | VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2845 == ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2846 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI) \
2847 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI)))
2848
2849
2850/** Bit fields for VM-exit interruption infomration. */
2851/** The VM-exit interruption vector. */
2852#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2853#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2854/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2855#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2856#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2857/** Whether this event has an error code. */
2858#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2859#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2860/** Whether NMI-unblocking due to IRET is active. */
2861#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2862#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2863/** Bits 13:30 is reserved (MBZ). */
2864#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2865#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2866/** Whether this VM-exit interruption info is valid. */
2867#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2868#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2869RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2870 (VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2871/** @} */
2872
2873
2874/** @name VM-exit interruption information types.
2875 * @{
2876 */
2877#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2878#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2879#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2880#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2881#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2882#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2883#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2884/** @} */
2885
2886
2887/** @name VM-exit instruction identity.
2888 *
2889 * These are found in VM-exit instruction information fields for certain
2890 * instructions.
2891 * @{ */
2892typedef uint32_t VMXINSTRID;
2893/** Whether the instruction ID field is valid. */
2894#define VMXINSTRID_VALID RT_BIT_32(31)
2895/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
2896 * read or write. */
2897#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
2898/** Gets whether the instruction ID is valid or not. */
2899#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
2900#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
2901/** Gets the instruction ID. */
2902#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W))
2903/** No instruction ID info. */
2904#define VMXINSTRID_NONE 0
2905
2906/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2907#define VMXINSTRID_SGDT (0x0 | VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)
2908#define VMXINSTRID_SIDT (0x1 | VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)
2909#define VMXINSTRID_LGDT (0x2 | VMXINSTRID_VALID)
2910#define VMXINSTRID_LIDT (0x3 | VMXINSTRID_VALID)
2911
2912#define VMXINSTRID_SLDT (0x0 | VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)
2913#define VMXINSTRID_STR (0x1 | VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)
2914#define VMXINSTRID_LLDT (0x2 | VMXINSTRID_VALID)
2915#define VMXINSTRID_LTR (0x3 | VMXINSTRID_VALID)
2916
2917/** The following IDs are used internally (some for logging, others for conveying
2918 * the ModR/M primary operand write bit): */
2919#define VMXINSTRID_VMLAUNCH (0x10 | VMXINSTRID_VALID)
2920#define VMXINSTRID_VMRESUME (0x11 | VMXINSTRID_VALID)
2921#define VMXINSTRID_VMREAD (0x12 | VMXINSTRID_VALID)
2922#define VMXINSTRID_VMWRITE (0x13 | VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)
2923#define VMXINSTRID_IO_IN (0x14 | VMXINSTRID_VALID)
2924#define VMXINSTRID_IO_INS (0x15 | VMXINSTRID_VALID)
2925#define VMXINSTRID_IO_OUT (0x16 | VMXINSTRID_VALID)
2926#define VMXINSTRID_IO_OUTS (0x17 | VMXINSTRID_VALID)
2927#define VMXINSTRID_MOV_TO_DRX (0x18 | VMXINSTRID_VALID)
2928#define VMXINSTRID_MOV_FROM_DRX (0x19 | VMXINSTRID_VALID)
2929/** @} */
2930
2931
2932/** @name IDT-vectoring information.
2933 * @{
2934 */
2935#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2936#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
2937#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2938#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
2939#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2940#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2941#define VMX_IDT_VECTORING_INFO_VALID RT_BIT(31)
2942
2943/** Construct an IDT-vectoring information field from an VM-entry interruption
2944 * information field (same except that bit 12 is reserved). */
2945#define VMX_IDT_VECTORING_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
2946/** If the IDT-vectoring information field indicates a page-fault. */
2947#define VMX_IDT_VECTORING_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
2948 | VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
2949 | VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
2950 == ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
2951 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT) \
2952 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_PF)))
2953/** If the IDT-vectoring information field indicates an NMI. */
2954#define VMX_IDT_VECTORING_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
2955 | VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
2956 | VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
2957 == ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
2958 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_NMI) \
2959 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_NMI)))
2960
2961
2962/** Bit fields for IDT-vectoring information. */
2963/** The IDT-vectoring info vector. */
2964#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2965#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2966/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
2967#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2968#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2969/** Whether the event has an error code. */
2970#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2971#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2972/** Bit 12 is undefined. */
2973#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2974#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2975/** Bits 13:30 is reserved (MBZ). */
2976#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2977#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2978/** Whether this IDT-vectoring info is valid. */
2979#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2980#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2981RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2982 (VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2983/** @} */
2984
2985
2986/** @name IDT-vectoring information vector types.
2987 * @{
2988 */
2989#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2990#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2991#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2992#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2993#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2994#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2995#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
2996/** @} */
2997
2998
2999/** @name TPR threshold.
3000 * @{ */
3001/** Mask of the TPR threshold field (bits 31:4 MBZ). */
3002#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
3003
3004/** Bit fields for TPR threshold. */
3005#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
3006#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
3007#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
3008#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
3009RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
3010 (TPR, RSVD_4_31));
3011/** @} */
3012
3013
3014/** @name Guest-activity states.
3015 * @{
3016 */
3017/** The logical processor is active. */
3018#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
3019/** The logical processor is inactive, because it executed a HLT instruction. */
3020#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
3021/** The logical processor is inactive, because of a triple fault or other serious error. */
3022#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
3023/** The logical processor is inactive, because it's waiting for a startup-IPI */
3024#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
3025/** @} */
3026
3027
3028/** @name Guest-interruptibility states.
3029 * @{
3030 */
3031#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
3032#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
3033#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
3034#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
3035#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
3036
3037/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
3038#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
3039/** @} */
3040
3041
3042/** @name Exit qualification for debug exceptions.
3043 * @{
3044 */
3045/** Hardware breakpoint 0 was met. */
3046#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
3047/** Hardware breakpoint 1 was met. */
3048#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
3049/** Hardware breakpoint 2 was met. */
3050#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
3051/** Hardware breakpoint 3 was met. */
3052#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
3053/** Debug register access detected. */
3054#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
3055/** A debug exception would have been triggered by single-step execution mode. */
3056#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
3057/** Mask of all valid bits. */
3058#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
3059 | VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
3060 | VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
3061 | VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
3062 | VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
3063 | VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
3064
3065/** Bit fields for Exit qualifications due to debug exceptions. */
3066#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
3067#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3068#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
3069#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3070#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
3071#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3072#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
3073#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3074#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
3075#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
3076#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
3077#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
3078#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
3079#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3080#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
3081#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
3082RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
3083 (BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
3084/** @} */
3085
3086/** @name Exit qualification for Mov DRx.
3087 * @{
3088 */
3089/** 0-2: Debug register number */
3090#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
3091/** 3: Reserved; cleared to 0. */
3092#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
3093/** 4: Direction of move (0 = write, 1 = read) */
3094#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
3095/** 5-7: Reserved; cleared to 0. */
3096#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
3097/** 8-11: General purpose register number. */
3098#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
3099
3100/** Bit fields for Exit qualification due to Mov DRx. */
3101#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
3102#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
3103#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
3104#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
3105#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
3106#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
3107#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
3108#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
3109#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
3110#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3111#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
3112#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
3113RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
3114 (REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
3115/** @} */
3116
3117
3118/** @name Exit qualification for debug exceptions types.
3119 * @{
3120 */
3121#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
3122#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
3123/** @} */
3124
3125
3126/** @name Exit qualification for control-register accesses.
3127 * @{
3128 */
3129/** 0-3: Control register number (0 for CLTS & LMSW) */
3130#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
3131/** 4-5: Access type. */
3132#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
3133/** 6: LMSW operand type memory (1 for memory, 0 for register). */
3134#define VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(a) (((a) >> 6) & 1)
3135/** 7: Reserved; cleared to 0. */
3136#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
3137/** 8-11: General purpose register number (0 for CLTS & LMSW). */
3138#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
3139/** 12-15: Reserved; cleared to 0. */
3140#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
3141/** 16-31: LMSW source data (else 0). */
3142#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
3143
3144/** Bit fields for Exit qualification for control-register accesses. */
3145#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
3146#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
3147#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
3148#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
3149#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
3150#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
3151#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
3152#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
3153#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
3154#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3155#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
3156#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
3157#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
3158#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
3159#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
3160#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3161RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
3162 (REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
3163/** @} */
3164
3165
3166/** @name Exit qualification for control-register access types.
3167 * @{
3168 */
3169#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
3170#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
3171#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
3172#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
3173/** @} */
3174
3175
3176/** @name Exit qualification for task switch.
3177 * @{
3178 */
3179#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
3180#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
3181/** Task switch caused by a call instruction. */
3182#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
3183/** Task switch caused by an iret instruction. */
3184#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
3185/** Task switch caused by a jmp instruction. */
3186#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
3187/** Task switch caused by an interrupt gate. */
3188#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
3189
3190/** Bit fields for Exit qualification for task switches. */
3191#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
3192#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
3193#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
3194#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
3195#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
3196#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
3197#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
3198#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3199RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
3200 (NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
3201/** @} */
3202
3203
3204/** @name Exit qualification for EPT violations.
3205 * @{
3206 */
3207/** Set if acess causing the violation was a data read. */
3208#define VMX_EXIT_QUAL_EPT_ACCESS_READ RT_BIT_64(0)
3209/** Set if acess causing the violation was a data write. */
3210#define VMX_EXIT_QUAL_EPT_ACCESS_WRITE RT_BIT_64(1)
3211/** Set if the violation was caused by an instruction fetch. */
3212#define VMX_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH RT_BIT_64(2)
3213/** AND of the present bit of all EPT structures. */
3214#define VMX_EXIT_QUAL_EPT_ENTRY_READ RT_BIT_64(3)
3215/** AND of the write bit of all EPT structures. */
3216#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT_64(4)
3217/** AND of the execute bit of all EPT structures. */
3218#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT_64(5)
3219/** And of the execute bit of all EPT structures for user-mode addresses
3220 * (requires mode-based execute control). */
3221#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER RT_BIT_64(6)
3222/** Set if the guest linear address field is valid. */
3223#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID RT_BIT_64(7)
3224/** If bit 7 is one: (reserved otherwise)
3225 * 1 - violation due to physical address access.
3226 * 0 - violation caused by page walk or access/dirty bit updates
3227 */
3228#define VMX_EXIT_QUAL_EPT_ACCESS_TRANSLATE RT_BIT_64(8)
3229/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3230 * 1 - linear address is user-mode address.
3231 * 0 - linear address is supervisor-mode address.
3232 */
3233#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_USER RT_BIT_64(9)
3234/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3235 * 1 - linear address translates to read-only page.
3236 * 0 - linear address translates to read-write page.
3237 */
3238#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_RO RT_BIT_64(10)
3239/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3240 * 1 - linear address translates to executable-disabled page.
3241 * 0 - linear address translates to executable page.
3242 */
3243#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_XD RT_BIT_64(11)
3244/** NMI unblocking due to IRET. */
3245#define VMX_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET RT_BIT_64(12)
3246/** Set if acess causing the violation was a shadow-stack access. */
3247#define VMX_EXIT_QUAL_EPT_ACCESS_SHW_STACK RT_BIT_64(13)
3248/** If supervisor-shadow stack is enabled: (reserved otherwise)
3249 * 1 - supervisor shadow-stack access allowed.
3250 * 0 - supervisor shadow-stack access disallowed.
3251 */
3252#define VMX_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER RT_BIT_64(14)
3253/** Set if access is related to trace output by Intel PT (reserved otherwise). */
3254#define VMX_EXIT_QUAL_EPT_ACCESS_PT_TRACE RT_BIT_64(16)
3255
3256/** Checks whether NMI unblocking due to IRET. */
3257#define VMX_EXIT_QUAL_EPT_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
3258
3259/** Bit fields for Exit qualification for EPT violations. */
3260#define VMX_BF_EXIT_QUAL_EPT_ACCESS_READ_SHIFT 0
3261#define VMX_BF_EXIT_QUAL_EPT_ACCESS_READ_MASK UINT64_C(0x0000000000000001)
3262#define VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE_SHIFT 1
3263#define VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE_MASK UINT64_C(0x0000000000000002)
3264#define VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH_SHIFT 2
3265#define VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH_MASK UINT64_C(0x0000000000000004)
3266#define VMX_BF_EXIT_QUAL_EPT_ENTRY_READ_SHIFT 3
3267#define VMX_BF_EXIT_QUAL_EPT_ENTRY_READ_MASK UINT64_C(0x0000000000000008)
3268#define VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE_SHIFT 4
3269#define VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE_MASK UINT64_C(0x0000000000000010)
3270#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_SHIFT 5
3271#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_MASK UINT64_C(0x0000000000000020)
3272#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER_SHIFT 6
3273#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER_MASK UINT64_C(0x0000000000000040)
3274#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_SHIFT 7
3275#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK UINT64_C(0x0000000000000080)
3276#define VMX_BF_EXIT_QUAL_EPT_ACCESS_TRANSLATE_SHIFT 8
3277#define VMX_BF_EXIT_QUAL_EPT_ACCESS_TRANSLATE_MASK UINT64_C(0x0000000000000100)
3278#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_USER_SHIFT 9
3279#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_USER_MASK UINT64_C(0x0000000000000200)
3280#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_RO_SHIFT 10
3281#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_RO_MASK UINT64_C(0x0000000000000400)
3282#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_XD_SHIFT 11
3283#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_XD_MASK UINT64_C(0x0000000000000800)
3284#define VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET_SHIFT 12
3285#define VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET_MASK UINT64_C(0x0000000000001000)
3286#define VMX_BF_EXIT_QUAL_EPT_ACCESS_SHW_STACK_SHIFT 13
3287#define VMX_BF_EXIT_QUAL_EPT_ACCESS_SHW_STACK_MASK UINT64_C(0x0000000000002000)
3288#define VMX_BF_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER_SHIFT 14
3289#define VMX_BF_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER_MASK UINT64_C(0x0000000000004000)
3290#define VMX_BF_EXIT_QUAL_EPT_RSVD_15_SHIFT 15
3291#define VMX_BF_EXIT_QUAL_EPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3292#define VMX_BF_EXIT_QUAL_EPT_ACCESS_PT_TRACE_SHIFT 16
3293#define VMX_BF_EXIT_QUAL_EPT_ACCESS_PT_TRACE_MASK UINT64_C(0x0000000000010000)
3294#define VMX_BF_EXIT_QUAL_EPT_RSVD_17_63_SHIFT 17
3295#define VMX_BF_EXIT_QUAL_EPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3296RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_EPT_, UINT64_C(0), UINT64_MAX,
3297 (ACCESS_READ, ACCESS_WRITE, ACCESS_INSTR_FETCH, ENTRY_READ, ENTRY_WRITE, ENTRY_EXECUTE,
3298 ENTRY_EXECUTE_USER, LINEAR_ADDR_VALID, ACCESS_TRANSLATE, LINEAR_ADDR_USER, LINEAR_ADDR_RO,
3299 LINEAR_ADDR_XD, NMI_UNBLOCK_IRET, ACCESS_SHW_STACK, ENTRY_SHW_STACK_SUPER, RSVD_15,
3300 ACCESS_PT_TRACE, RSVD_17_63));
3301/** @} */
3302
3303
3304/** @name Exit qualification for I/O instructions.
3305 * @{
3306 */
3307/** 0-2: IO operation size 0(=1 byte), 1(=2 bytes) and 3(=4 bytes). */
3308#define VMX_EXIT_QUAL_IO_SIZE(a) ((a) & 7)
3309/** 3: IO operation direction. */
3310#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
3311/** 4: String IO operation (INS / OUTS). */
3312#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
3313/** 5: Repeated IO operation. */
3314#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
3315/** 6: Operand encoding. */
3316#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
3317/** 16-31: IO Port (0-0xffff). */
3318#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
3319
3320/** Bit fields for Exit qualification for I/O instructions. */
3321#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
3322#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
3323#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
3324#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
3325#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
3326#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
3327#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
3328#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
3329#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
3330#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
3331#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
3332#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
3333#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
3334#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
3335#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
3336#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3337RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
3338 (WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
3339/** @} */
3340
3341
3342/** @name Exit qualification for I/O instruction types.
3343 * @{
3344 */
3345#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
3346#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
3347/** @} */
3348
3349
3350/** @name Exit qualification for I/O instruction encoding.
3351 * @{
3352 */
3353#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
3354#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
3355/** @} */
3356
3357
3358/** @name Exit qualification for APIC-access VM-exits from linear and
3359 * guest-physical accesses.
3360 * @{
3361 */
3362/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
3363 * access within the APIC page. */
3364#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
3365/** 12-15: Access type. */
3366#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
3367/* Rest reserved. */
3368
3369/** Bit fields for Exit qualification for APIC-access VM-exits. */
3370#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
3371#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
3372#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
3373#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
3374#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
3375#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
3376RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
3377 (OFFSET, TYPE, RSVD_16_63));
3378/** @} */
3379
3380
3381/** @name Exit qualification for linear address APIC-access types.
3382 * @{
3383 */
3384/** Linear access for a data read during instruction execution. */
3385#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
3386/** Linear access for a data write during instruction execution. */
3387#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
3388/** Linear access for an instruction fetch. */
3389#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
3390/** Linear read/write access during event delivery. */
3391#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
3392/** Physical read/write access during event delivery. */
3393#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
3394/** Physical access for an instruction fetch or during instruction execution. */
3395#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
3396
3397/**
3398 * APIC-access type.
3399 * In accordance with the VT-x spec.
3400 */
3401typedef enum
3402{
3403 VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
3404 VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
3405 VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
3406 VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
3407 VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
3408 VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
3409} VMXAPICACCESS;
3410AssertCompileSize(VMXAPICACCESS, 4);
3411/** @} */
3412
3413
3414/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
3415 * Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3416 * @{
3417 */
3418/** Address calculation scaling field (powers of two). */
3419#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
3420#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3421/** Bits 2 thru 6 are undefined. */
3422#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
3423#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
3424/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3425 * @remarks anyone's guess why this is a 3 bit field... */
3426#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
3427#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3428/** Bit 10 is defined as zero. */
3429#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
3430#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
3431/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
3432 * for exits from 64-bit code as the operand size there is fixed. */
3433#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
3434#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
3435/** Bits 12 thru 14 are undefined. */
3436#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
3437#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
3438/** Applicable segment register (X86_SREG_XXX values). */
3439#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
3440#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3441/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3442#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
3443#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3444/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3445#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3446#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3447/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3448#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
3449#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3450/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3451#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
3452#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3453/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
3454#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
3455#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3456#define VMX_XDTR_INSINFO_II_SGDT 0 /**< Instruction ID: SGDT */
3457#define VMX_XDTR_INSINFO_II_SIDT 1 /**< Instruction ID: SIDT */
3458#define VMX_XDTR_INSINFO_II_LGDT 2 /**< Instruction ID: LGDT */
3459#define VMX_XDTR_INSINFO_II_LIDT 3 /**< Instruction ID: LIDT */
3460/** Bits 30 & 31 are undefined. */
3461#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
3462#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3463RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3464 (SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
3465 BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3466/** @} */
3467
3468
3469/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
3470 * Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3471 * This is similar to VMX_BF_XDTR_INSINFO_XXX.
3472 * @{
3473 */
3474/** Address calculation scaling field (powers of two). */
3475#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
3476#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3477/** Bit 2 is undefined. */
3478#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
3479#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
3480/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
3481#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
3482#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
3483/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3484 * @remarks anyone's guess why this is a 3 bit field... */
3485#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
3486#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3487/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
3488#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
3489#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
3490/** Bits 11 thru 14 are undefined. */
3491#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
3492#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
3493/** Applicable segment register (X86_SREG_XXX values). */
3494#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
3495#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3496/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3497#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
3498#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3499/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3500#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3501#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3502/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3503#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
3504#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3505/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3506#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
3507#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3508/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
3509#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
3510#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3511#define VMX_YYTR_INSINFO_II_SLDT 0 /**< Instruction ID: SLDT */
3512#define VMX_YYTR_INSINFO_II_STR 1 /**< Instruction ID: STR */
3513#define VMX_YYTR_INSINFO_II_LLDT 2 /**< Instruction ID: LLDT */
3514#define VMX_YYTR_INSINFO_II_LTR 3 /**< Instruction ID: LTR */
3515/** Bits 30 & 31 are undefined. */
3516#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3517#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3518RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3519 (SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3520 BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3521/** @} */
3522
3523
3524/** @name Format of Pending-Debug-Exceptions.
3525 * Bits 4-11, 13, 15 and 17-63 are reserved.
3526 * Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3527 * possibly valid here but not in DR6.
3528 * @{
3529 */
3530/** Hardware breakpoint 0 was met. */
3531#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3532/** Hardware breakpoint 1 was met. */
3533#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3534/** Hardware breakpoint 2 was met. */
3535#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3536/** Hardware breakpoint 3 was met. */
3537#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3538/** At least one data or IO breakpoint was hit. */
3539#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3540/** A debug exception would have been triggered by single-step execution mode. */
3541#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3542/** A debug exception occurred inside an RTM region. */
3543#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3544/** Mask of valid bits. */
3545#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3546 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3547 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3548 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3549 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3550 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3551 | VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3552#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3553 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3554 | VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3555/** Bit fields for Pending debug exceptions. */
3556#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3557#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3558#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3559#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3560#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3561#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3562#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3563#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3564#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3565#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3566#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3567#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3568#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3569#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3570#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3571#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3572#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3573#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3574#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3575#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3576#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3577#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3578RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3579 (BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3580/** @} */
3581
3582
3583/** @defgroup grp_hm_vmx_virt VMX virtualization.
3584 * @{
3585 */
3586
3587/** @name Virtual VMX MSR - Miscellaneous data.
3588 * @{ */
3589/** Number of CR3-target values supported. */
3590#define VMX_V_CR3_TARGET_COUNT 4
3591/** Activity states supported. */
3592#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3593/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3594#define VMX_V_PREEMPT_TIMER_SHIFT 5
3595/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3596#define VMX_V_AUTOMSR_COUNT_MAX 0
3597/** SMM MSEG revision ID. */
3598#define VMX_V_MSEG_REV_ID 0
3599/** @} */
3600
3601/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS launch state.
3602 * @{ */
3603/** VMCS launch state clear. */
3604#define VMX_V_VMCS_LAUNCH_STATE_CLEAR RT_BIT(0)
3605/** VMCS launch state active. */
3606#define VMX_V_VMCS_LAUNCH_STATE_ACTIVE RT_BIT(1)
3607/** VMCS launch state current. */
3608#define VMX_V_VMCS_LAUNCH_STATE_CURRENT RT_BIT(2)
3609/** VMCS launch state launched. */
3610#define VMX_V_VMCS_LAUNCH_STATE_LAUNCHED RT_BIT(3)
3611/** The mask of valid VMCS launch states. */
3612#define VMX_V_VMCS_LAUNCH_STATE_MASK ( VMX_V_VMCS_LAUNCH_STATE_CLEAR \
3613 | VMX_V_VMCS_LAUNCH_STATE_ACTIVE \
3614 | VMX_V_VMCS_LAUNCH_STATE_CURRENT \
3615 | VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
3616/** @} */
3617
3618/** CR0 bits set here must always be set when in VMX operation. */
3619#define VMX_V_CR0_FIXED0 (X86_CR0_PE | X86_CR0_NE | X86_CR0_PG)
3620/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
3621#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE | X86_CR0_PG))
3622/** CR4 bits set here must always be set when in VMX operation. */
3623#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3624
3625/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3626 * changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3627#define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001)
3628AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3629
3630/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3631 * complications when teleporation may be implemented). */
3632#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3633/** The size of the virtual VMCS region (in pages). */
3634#define VMX_V_VMCS_PAGES 1
3635
3636/** The size of the virtual shadow VMCS region. */
3637#define VMX_V_SHADOW_VMCS_SIZE VMX_V_VMCS_SIZE
3638/** The size of the virtual shadow VMCS region (in pages). */
3639#define VMX_V_SHADOW_VMCS_PAGES VMX_V_VMCS_PAGES
3640
3641/** The size of the Virtual-APIC page (in bytes). */
3642#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3643/** The size of the Virtual-APIC page (in pages). */
3644#define VMX_V_VIRT_APIC_PAGES 1
3645
3646/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3647#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3648/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3649#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3650
3651/** The size of the MSR bitmap (in bytes). */
3652#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3653/** The size of the MSR bitmap (in pages). */
3654#define VMX_V_MSR_BITMAP_PAGES 1
3655
3656/** The size of I/O bitmap A (in bytes). */
3657#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3658/** The size of I/O bitmap A (in pages). */
3659#define VMX_V_IO_BITMAP_A_PAGES 1
3660
3661/** The size of I/O bitmap B (in bytes). */
3662#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3663/** The size of I/O bitmap B (in pages). */
3664#define VMX_V_IO_BITMAP_B_PAGES 1
3665
3666/** The size of the auto-load/store MSR area (in bytes). */
3667#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3668/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3669AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3670/** The size of the auto-load/store MSR area (in pages). */
3671#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3672
3673/** The highest index value used for supported virtual VMCS field encoding. */
3674#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_HIGH, VMX_BF_VMCSFIELD_INDEX)
3675
3676/**
3677 * Virtual VM-exit information.
3678 *
3679 * This is a convenience structure that bundles some VM-exit information related
3680 * fields together.
3681 */
3682typedef struct
3683{
3684 /** The VM-exit reason. */
3685 uint32_t uReason;
3686 /** The VM-exit instruction length. */
3687 uint32_t cbInstr;
3688 /** The VM-exit instruction information. */
3689 VMXEXITINSTRINFO InstrInfo;
3690 /** The VM-exit instruction ID. */
3691 VMXINSTRID uInstrId;
3692
3693 /** The Exit qualification field. */
3694 uint64_t u64Qual;
3695 /** The Guest-linear address field. */
3696 uint64_t u64GuestLinearAddr;
3697 /** The Guest-physical address field. */
3698 uint64_t u64GuestPhysAddr;
3699 /** The guest pending-debug exceptions. */
3700 uint64_t u64GuestPendingDbgXcpts;
3701 /** The effective guest-linear address if @a InstrInfo indicates a memory-based
3702 * instruction VM-exit. */
3703 RTGCPTR GCPtrEffAddr;
3704} VMXVEXITINFO;
3705/** Pointer to the VMXVEXITINFO struct. */
3706typedef VMXVEXITINFO *PVMXVEXITINFO;
3707/** Pointer to a const VMXVEXITINFO struct. */
3708typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3709AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3710
3711/**
3712 * Virtual VM-exit information for events.
3713 *
3714 * This is a convenience structure that bundles some event-based VM-exit information
3715 * related fields together that are not included in VMXVEXITINFO.
3716 *
3717 * This is kept as a separate structure and not included in VMXVEXITINFO, to make it
3718 * easier to distinguish that IEM VM-exit handlers will set one or more of the
3719 * following fields in the virtual VMCS. Including it in the VMXVEXITINFO will not
3720 * make it ovbious which fields may get set (or cleared).
3721 */
3722typedef struct
3723{
3724 /** VM-exit interruption information. */
3725 uint32_t uExitIntInfo;
3726 /** VM-exit interruption error code. */
3727 uint32_t uExitIntErrCode;
3728 /** IDT-vectoring information. */
3729 uint32_t uIdtVectoringInfo;
3730 /** IDT-vectoring error code. */
3731 uint32_t uIdtVectoringErrCode;
3732} VMXVEXITEVENTINFO;
3733/** Pointer to the VMXVEXITINFO2 struct. */
3734typedef VMXVEXITEVENTINFO *PVMXVEXITEVENTINFO;
3735/** Pointer to a const VMXVEXITINFO2 struct. */
3736typedef const VMXVEXITEVENTINFO *PCVMXVEXITEVENTINFO;
3737
3738/**
3739 * Virtual VMCS.
3740 *
3741 * This is our custom format. Relevant fields from this VMCS will be merged into the
3742 * actual/shadow VMCS when we execute nested-guest code using hardware-assisted
3743 * VMX.
3744 *
3745 * The first 8 bytes must be in accordance with the Intel VT-x spec.
3746 * See Intel spec. 24.2 "Format of the VMCS Region".
3747 *
3748 * The offset and size of the VMCS state field (@a fVmcsState) is also fixed (not by
3749 * the Intel spec. but for our own requirements) as we use it to offset into guest
3750 * memory.
3751 *
3752 * Although the guest is supposed to access the VMCS only through the execution of
3753 * VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3754 * memory (e.g, active but not current VMCS), for saved-states compatibility, and
3755 * for teleportation purposes, any newly added fields should be added to the
3756 * appropriate reserved sections or at the end of the structure.
3757 *
3758 * We always treat natural-width fields as 64-bit in our implementation since
3759 * it's easier, allows for teleporation in the future and does not affect guest
3760 * software.
3761 *
3762 * @note Any fields that are added or modified here, make sure to update the
3763 * corresponding fields in IEM (g_aoffVmcsMap), the corresponding saved
3764 * state structure in CPUM (g_aVmxHwvirtVmcs) and bump the SSM version.
3765 * Also consider updating CPUMIsGuestVmxVmcsFieldValid and cpumR3InfoVmxVmcs.
3766 */
3767#pragma pack(1)
3768typedef struct
3769{
3770 /** @name Header.
3771 * @{
3772 */
3773 VMXVMCSREVID u32VmcsRevId; /**< 0x000 - VMX VMCS revision identifier. */
3774 VMXABORT enmVmxAbort; /**< 0x004 - VMX-abort indicator. */
3775 uint8_t fVmcsState; /**< 0x008 - VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
3776 uint8_t au8Padding0[3]; /**< 0x009 - Reserved for future. */
3777 uint32_t au32Reserved0[12]; /**< 0x00c - Reserved for future. */
3778 /** @} */
3779
3780 /** @name Read-only fields.
3781 * @{ */
3782 /** 16-bit fields. */
3783 uint16_t u16Reserved0[14]; /**< 0x03c - Reserved for future. */
3784
3785 /** 32-bit fields. */
3786 uint32_t u32RoVmInstrError; /**< 0x058 - VM-instruction error. */
3787 uint32_t u32RoExitReason; /**< 0x05c - VM-exit reason. */
3788 uint32_t u32RoExitIntInfo; /**< 0x060 - VM-exit interruption information. */
3789 uint32_t u32RoExitIntErrCode; /**< 0x064 - VM-exit interruption error code. */
3790 uint32_t u32RoIdtVectoringInfo; /**< 0x068 - IDT-vectoring information. */
3791 uint32_t u32RoIdtVectoringErrCode; /**< 0x06c - IDT-vectoring error code. */
3792 uint32_t u32RoExitInstrLen; /**< 0x070 - VM-exit instruction length. */
3793 uint32_t u32RoExitInstrInfo; /**< 0x074 - VM-exit instruction information. */
3794 uint32_t au32RoReserved2[16]; /**< 0x078 - Reserved for future. */
3795
3796 /** 64-bit fields. */
3797 RTUINT64U u64RoGuestPhysAddr; /**< 0x0b8 - Guest-physical address. */
3798 RTUINT64U au64Reserved1[8]; /**< 0x0c0 - Reserved for future. */
3799
3800 /** Natural-width fields. */
3801 RTUINT64U u64RoExitQual; /**< 0x100 - Exit qualification. */
3802 RTUINT64U u64RoIoRcx; /**< 0x108 - I/O RCX. */
3803 RTUINT64U u64RoIoRsi; /**< 0x110 - I/O RSI. */
3804 RTUINT64U u64RoIoRdi; /**< 0x118 - I/O RDI. */
3805 RTUINT64U u64RoIoRip; /**< 0x120 - I/O RIP. */
3806 RTUINT64U u64RoGuestLinearAddr; /**< 0x128 - Guest-linear address. */
3807 RTUINT64U au64Reserved5[16]; /**< 0x130 - Reserved for future. */
3808 /** @} */
3809
3810 /** @name Control fields.
3811 * @{ */
3812 /** 16-bit fields. */
3813 uint16_t u16Vpid; /**< 0x1b0 - Virtual processor ID. */
3814 uint16_t u16PostIntNotifyVector; /**< 0x1b2 - Posted interrupt notify vector. */
3815 uint16_t u16EptpIndex; /**< 0x1b4 - EPTP index. */
3816 uint16_t au16Reserved0[13]; /**< 0x1b6 - Reserved for future. */
3817
3818 /** 32-bit fields. */
3819 uint32_t u32PinCtls; /**< 0x1d0 - Pin-based VM-execution controls. */
3820 uint32_t u32ProcCtls; /**< 0x1d4 - Processor-based VM-execution controls. */
3821 uint32_t u32XcptBitmap; /**< 0x1d8 - Exception bitmap. */
3822 uint32_t u32XcptPFMask; /**< 0x1dc - Page-fault exception error mask. */
3823 uint32_t u32XcptPFMatch; /**< 0x1e0 - Page-fault exception error match. */
3824 uint32_t u32Cr3TargetCount; /**< 0x1e4 - CR3-target count. */
3825 uint32_t u32ExitCtls; /**< 0x1e8 - VM-exit controls. */
3826 uint32_t u32ExitMsrStoreCount; /**< 0x1ec - VM-exit MSR store count. */
3827 uint32_t u32ExitMsrLoadCount; /**< 0x1f0 - VM-exit MSR load count. */
3828 uint32_t u32EntryCtls; /**< 0x1f4 - VM-entry controls. */
3829 uint32_t u32EntryMsrLoadCount; /**< 0x1f8 - VM-entry MSR load count. */
3830 uint32_t u32EntryIntInfo; /**< 0x1fc - VM-entry interruption information. */
3831 uint32_t u32EntryXcptErrCode; /**< 0x200 - VM-entry exception error code. */
3832 uint32_t u32EntryInstrLen; /**< 0x204 - VM-entry instruction length. */
3833 uint32_t u32TprThreshold; /**< 0x208 - TPR-threshold. */
3834 uint32_t u32ProcCtls2; /**< 0x20c - Secondary-processor based VM-execution controls. */
3835 uint32_t u32PleGap; /**< 0x210 - Pause-loop exiting Gap. */
3836 uint32_t u32PleWindow; /**< 0x214 - Pause-loop exiting Window. */
3837 uint32_t au32Reserved1[16]; /**< 0x218 - Reserved for future. */
3838
3839 /** 64-bit fields. */
3840 RTUINT64U u64AddrIoBitmapA; /**< 0x258 - I/O bitmap A address. */
3841 RTUINT64U u64AddrIoBitmapB; /**< 0x260 - I/O bitmap B address. */
3842 RTUINT64U u64AddrMsrBitmap; /**< 0x268 - MSR bitmap address. */
3843 RTUINT64U u64AddrExitMsrStore; /**< 0x270 - VM-exit MSR-store area address. */
3844 RTUINT64U u64AddrExitMsrLoad; /**< 0x278 - VM-exit MSR-load area address. */
3845 RTUINT64U u64AddrEntryMsrLoad; /**< 0x280 - VM-entry MSR-load area address. */
3846 RTUINT64U u64ExecVmcsPtr; /**< 0x288 - Executive-VMCS pointer. */
3847 RTUINT64U u64AddrPml; /**< 0x290 - Page-modification log address (PML). */
3848 RTUINT64U u64TscOffset; /**< 0x298 - TSC offset. */
3849 RTUINT64U u64AddrVirtApic; /**< 0x2a0 - Virtual-APIC address. */
3850 RTUINT64U u64AddrApicAccess; /**< 0x2a8 - APIC-access address. */
3851 RTUINT64U u64AddrPostedIntDesc; /**< 0x2b0 - Posted-interrupt descriptor address. */
3852 RTUINT64U u64VmFuncCtls; /**< 0x2b8 - VM-functions control. */
3853 RTUINT64U u64EptPtr; /**< 0x2c0 - EPT pointer. */
3854 RTUINT64U u64EoiExitBitmap0; /**< 0x2c8 - EOI-exit bitmap 0. */
3855 RTUINT64U u64EoiExitBitmap1; /**< 0x2d0 - EOI-exit bitmap 1. */
3856 RTUINT64U u64EoiExitBitmap2; /**< 0x2d8 - EOI-exit bitmap 2. */
3857 RTUINT64U u64EoiExitBitmap3; /**< 0x2e0 - EOI-exit bitmap 3. */
3858 RTUINT64U u64AddrEptpList; /**< 0x2e8 - EPTP-list address. */
3859 RTUINT64U u64AddrVmreadBitmap; /**< 0x2f0 - VMREAD-bitmap address. */
3860 RTUINT64U u64AddrVmwriteBitmap; /**< 0x2f8 - VMWRITE-bitmap address. */
3861 RTUINT64U u64AddrXcptVeInfo; /**< 0x300 - Virtualization-exception information address. */
3862 RTUINT64U u64XssExitBitmap; /**< 0x308 - XSS-exiting bitmap. */
3863 RTUINT64U u64EnclsExitBitmap; /**< 0x310 - ENCLS-exiting bitmap address. */
3864 RTUINT64U u64SppTablePtr; /**< 0x318 - Sub-page-permission-table pointer (SPPTP). */
3865 RTUINT64U u64TscMultiplier; /**< 0x320 - TSC multiplier. */
3866 RTUINT64U u64ProcCtls3; /**< 0x328 - Tertiary-Processor based VM-execution controls. */
3867 RTUINT64U u64EnclvExitBitmap; /**< 0x330 - ENCLV-exiting bitmap. */
3868 RTUINT64U au64Reserved0[13]; /**< 0x338 - Reserved for future. */
3869
3870 /** Natural-width fields. */
3871 RTUINT64U u64Cr0Mask; /**< 0x3a0 - CR0 guest/host Mask. */
3872 RTUINT64U u64Cr4Mask; /**< 0x3a8 - CR4 guest/host Mask. */
3873 RTUINT64U u64Cr0ReadShadow; /**< 0x3b0 - CR0 read shadow. */
3874 RTUINT64U u64Cr4ReadShadow; /**< 0x3b8 - CR4 read shadow. */
3875 RTUINT64U u64Cr3Target0; /**< 0x3c0 - CR3-target value 0. */
3876 RTUINT64U u64Cr3Target1; /**< 0x3c8 - CR3-target value 1. */
3877 RTUINT64U u64Cr3Target2; /**< 0x3d0 - CR3-target value 2. */
3878 RTUINT64U u64Cr3Target3; /**< 0x3d8 - CR3-target value 3. */
3879 RTUINT64U au64Reserved4[32]; /**< 0x3e0 - Reserved for future. */
3880 /** @} */
3881
3882 /** @name Host-state fields.
3883 * @{ */
3884 /** 16-bit fields. */
3885 /* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3886 RTSEL HostEs; /**< 0x4e0 - Host ES selector. */
3887 RTSEL HostCs; /**< 0x4e2 - Host CS selector. */
3888 RTSEL HostSs; /**< 0x4e4 - Host SS selector. */
3889 RTSEL HostDs; /**< 0x4e6 - Host DS selector. */
3890 RTSEL HostFs; /**< 0x4e8 - Host FS selector. */
3891 RTSEL HostGs; /**< 0x4ea - Host GS selector. */
3892 RTSEL HostTr; /**< 0x4ec - Host TR selector. */
3893 uint16_t au16Reserved2[13]; /**< 0x4ee - Reserved for future. */
3894
3895 /** 32-bit fields. */
3896 uint32_t u32HostSysenterCs; /**< 0x508 - Host SYSENTER CS. */
3897 uint32_t au32Reserved4[11]; /**< 0x50c - Reserved for future. */
3898
3899 /** 64-bit fields. */
3900 RTUINT64U u64HostPatMsr; /**< 0x538 - Host PAT MSR. */
3901 RTUINT64U u64HostEferMsr; /**< 0x540 - Host EFER MSR. */
3902 RTUINT64U u64HostPerfGlobalCtlMsr; /**< 0x548 - Host global performance-control MSR. */
3903 RTUINT64U u64HostPkrsMsr; /**< 0x550 - Host PKRS MSR. */
3904 RTUINT64U au64Reserved3[15]; /**< 0x558 - Reserved for future. */
3905
3906 /** Natural-width fields. */
3907 RTUINT64U u64HostCr0; /**< 0x5d0 - Host CR0. */
3908 RTUINT64U u64HostCr3; /**< 0x5d8 - Host CR3. */
3909 RTUINT64U u64HostCr4; /**< 0x5e0 - Host CR4. */
3910 RTUINT64U u64HostFsBase; /**< 0x5e8 - Host FS base. */
3911 RTUINT64U u64HostGsBase; /**< 0x5f0 - Host GS base. */
3912 RTUINT64U u64HostTrBase; /**< 0x5f8 - Host TR base. */
3913 RTUINT64U u64HostGdtrBase; /**< 0x600 - Host GDTR base. */
3914 RTUINT64U u64HostIdtrBase; /**< 0x608 - Host IDTR base. */
3915 RTUINT64U u64HostSysenterEsp; /**< 0x610 - Host SYSENTER ESP base. */
3916 RTUINT64U u64HostSysenterEip; /**< 0x618 - Host SYSENTER ESP base. */
3917 RTUINT64U u64HostRsp; /**< 0x620 - Host RSP. */
3918 RTUINT64U u64HostRip; /**< 0x628 - Host RIP. */
3919 RTUINT64U u64HostSCetMsr; /**< 0x630 - Host S_CET MSR. */
3920 RTUINT64U u64HostSsp; /**< 0x638 - Host SSP. */
3921 RTUINT64U u64HostIntrSspTableAddrMsr; /**< 0x640 - Host Interrupt SSP table address MSR. */
3922 RTUINT64U au64Reserved7[29]; /**< 0x648 - Reserved for future. */
3923 /** @} */
3924
3925 /** @name Guest-state fields.
3926 * @{ */
3927 /** 16-bit fields. */
3928 /* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3929 RTSEL GuestEs; /**< 0x730 - Guest ES selector. */
3930 RTSEL GuestCs; /**< 0x732 - Guest ES selector. */
3931 RTSEL GuestSs; /**< 0x734 - Guest ES selector. */
3932 RTSEL GuestDs; /**< 0x736 - Guest ES selector. */
3933 RTSEL GuestFs; /**< 0x738 - Guest ES selector. */
3934 RTSEL GuestGs; /**< 0x73a - Guest ES selector. */
3935 RTSEL GuestLdtr; /**< 0x73c - Guest LDTR selector. */
3936 RTSEL GuestTr; /**< 0x73e - Guest TR selector. */
3937 uint16_t u16GuestIntStatus; /**< 0x740 - Guest interrupt status (virtual-interrupt delivery). */
3938 uint16_t u16PmlIndex; /**< 0x742 - PML index. */
3939 uint16_t au16Reserved1[14]; /**< 0x744 - Reserved for future. */
3940
3941 /** 32-bit fields. */
3942 /* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3943 uint32_t u32GuestEsLimit; /**< 0x760 - Guest ES limit. */
3944 uint32_t u32GuestCsLimit; /**< 0x764 - Guest CS limit. */
3945 uint32_t u32GuestSsLimit; /**< 0x768 - Guest SS limit. */
3946 uint32_t u32GuestDsLimit; /**< 0x76c - Guest DS limit. */
3947 uint32_t u32GuestFsLimit; /**< 0x770 - Guest FS limit. */
3948 uint32_t u32GuestGsLimit; /**< 0x774 - Guest GS limit. */
3949 uint32_t u32GuestLdtrLimit; /**< 0x778 - Guest LDTR limit. */
3950 uint32_t u32GuestTrLimit; /**< 0x77c - Guest TR limit. */
3951 uint32_t u32GuestGdtrLimit; /**< 0x780 - Guest GDTR limit. */
3952 uint32_t u32GuestIdtrLimit; /**< 0x784 - Guest IDTR limit. */
3953 uint32_t u32GuestEsAttr; /**< 0x788 - Guest ES attributes. */
3954 uint32_t u32GuestCsAttr; /**< 0x78c - Guest CS attributes. */
3955 uint32_t u32GuestSsAttr; /**< 0x790 - Guest SS attributes. */
3956 uint32_t u32GuestDsAttr; /**< 0x794 - Guest DS attributes. */
3957 uint32_t u32GuestFsAttr; /**< 0x798 - Guest FS attributes. */
3958 uint32_t u32GuestGsAttr; /**< 0x79c - Guest GS attributes. */
3959 uint32_t u32GuestLdtrAttr; /**< 0x7a0 - Guest LDTR attributes. */
3960 uint32_t u32GuestTrAttr; /**< 0x7a4 - Guest TR attributes. */
3961 uint32_t u32GuestIntrState; /**< 0x7a8 - Guest interruptibility state. */
3962 uint32_t u32GuestActivityState; /**< 0x7ac - Guest activity state. */
3963 uint32_t u32GuestSmBase; /**< 0x7b0 - Guest SMBASE. */
3964 uint32_t u32GuestSysenterCS; /**< 0x7b4 - Guest SYSENTER CS. */
3965 uint32_t u32PreemptTimer; /**< 0x7b8 - Preemption timer value. */
3966 uint32_t au32Reserved3[11]; /**< 0x7bc - Reserved for future. */
3967
3968 /** 64-bit fields. */
3969 RTUINT64U u64VmcsLinkPtr; /**< 0x7e8 - VMCS link pointer. */
3970 RTUINT64U u64GuestDebugCtlMsr; /**< 0x7f0 - Guest debug-control MSR. */
3971 RTUINT64U u64GuestPatMsr; /**< 0x7f8 - Guest PAT MSR. */
3972 RTUINT64U u64GuestEferMsr; /**< 0x800 - Guest EFER MSR. */
3973 RTUINT64U u64GuestPerfGlobalCtlMsr; /**< 0x808 - Guest global performance-control MSR. */
3974 RTUINT64U u64GuestPdpte0; /**< 0x810 - Guest PDPTE 0. */
3975 RTUINT64U u64GuestPdpte1; /**< 0x818 - Guest PDPTE 0. */
3976 RTUINT64U u64GuestPdpte2; /**< 0x820 - Guest PDPTE 1. */
3977 RTUINT64U u64GuestPdpte3; /**< 0x828 - Guest PDPTE 2. */
3978 RTUINT64U u64GuestBndcfgsMsr; /**< 0x830 - Guest Bounds config MPX MSR (Intel Memory Protection Extensions). */
3979 RTUINT64U u64GuestRtitCtlMsr; /**< 0x838 - Guest RTIT control MSR (Intel Real Time Instruction Trace). */
3980 RTUINT64U u64GuestPkrsMsr; /**< 0x840 - Guest PKRS MSR. */
3981 RTUINT64U au64Reserved2[31]; /**< 0x848 - Reserved for future. */
3982
3983 /** Natural-width fields. */
3984 RTUINT64U u64GuestCr0; /**< 0x940 - Guest CR0. */
3985 RTUINT64U u64GuestCr3; /**< 0x948 - Guest CR3. */
3986 RTUINT64U u64GuestCr4; /**< 0x950 - Guest CR4. */
3987 RTUINT64U u64GuestEsBase; /**< 0x958 - Guest ES base. */
3988 RTUINT64U u64GuestCsBase; /**< 0x960 - Guest CS base. */
3989 RTUINT64U u64GuestSsBase; /**< 0x968 - Guest SS base. */
3990 RTUINT64U u64GuestDsBase; /**< 0x970 - Guest DS base. */
3991 RTUINT64U u64GuestFsBase; /**< 0x978 - Guest FS base. */
3992 RTUINT64U u64GuestGsBase; /**< 0x980 - Guest GS base. */
3993 RTUINT64U u64GuestLdtrBase; /**< 0x988 - Guest LDTR base. */
3994 RTUINT64U u64GuestTrBase; /**< 0x990 - Guest TR base. */
3995 RTUINT64U u64GuestGdtrBase; /**< 0x998 - Guest GDTR base. */
3996 RTUINT64U u64GuestIdtrBase; /**< 0x9a0 - Guest IDTR base. */
3997 RTUINT64U u64GuestDr7; /**< 0x9a8 - Guest DR7. */
3998 RTUINT64U u64GuestRsp; /**< 0x9b0 - Guest RSP. */
3999 RTUINT64U u64GuestRip; /**< 0x9b8 - Guest RIP. */
4000 RTUINT64U u64GuestRFlags; /**< 0x9c0 - Guest RFLAGS. */
4001 RTUINT64U u64GuestPendingDbgXcpts; /**< 0x9c8 - Guest pending debug exceptions. */
4002 RTUINT64U u64GuestSysenterEsp; /**< 0x9d0 - Guest SYSENTER ESP. */
4003 RTUINT64U u64GuestSysenterEip; /**< 0x9d8 - Guest SYSENTER EIP. */
4004 RTUINT64U u64GuestSCetMsr; /**< 0x9e0 - Guest S_CET MSR. */
4005 RTUINT64U u64GuestSsp; /**< 0x9e8 - Guest SSP. */
4006 RTUINT64U u64GuestIntrSspTableAddrMsr; /**< 0x9f0 - Guest Interrupt SSP table address MSR. */
4007 RTUINT64U au64Reserved6[29]; /**< 0x9f8 - Reserved for future. */
4008 /** @} */
4009
4010 /** 0xae0 - Padding / reserved for future use. */
4011 uint8_t abPadding[X86_PAGE_4K_SIZE - 0xae0];
4012} VMXVVMCS;
4013#pragma pack()
4014/** Pointer to the VMXVVMCS struct. */
4015typedef VMXVVMCS *PVMXVVMCS;
4016/** Pointer to a const VMXVVMCS struct. */
4017typedef const VMXVVMCS *PCVMXVVMCS;
4018AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
4019AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
4020AssertCompileMemberOffset(VMXVVMCS, enmVmxAbort, 0x004);
4021AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
4022AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x058);
4023AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x0b8);
4024AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x100);
4025AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x1b0);
4026AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x1d0);
4027AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x258);
4028AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x3a0);
4029AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x4e0);
4030AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x508);
4031AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x538);
4032AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x5d0);
4033AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x730);
4034AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x760);
4035AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x7e8);
4036AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x940);
4037
4038/**
4039 * Virtual VMX-instruction and VM-exit diagnostics.
4040 *
4041 * These are not the same as VM instruction errors that are enumerated in the Intel
4042 * spec. These are purely internal, fine-grained definitions used for diagnostic
4043 * purposes and are not reported to guest software under the VM-instruction error
4044 * field in its VMCS.
4045 *
4046 * @note Members of this enum are used as array indices, so no gaps are allowed.
4047 * Please update g_apszVmxVDiagDesc when you add new fields to this enum.
4048 */
4049typedef enum
4050{
4051 /* Internal processing errors. */
4052 kVmxVDiag_None = 0,
4053 kVmxVDiag_Ipe_1,
4054 kVmxVDiag_Ipe_2,
4055 kVmxVDiag_Ipe_3,
4056 kVmxVDiag_Ipe_4,
4057 kVmxVDiag_Ipe_5,
4058 kVmxVDiag_Ipe_6,
4059 kVmxVDiag_Ipe_7,
4060 kVmxVDiag_Ipe_8,
4061 kVmxVDiag_Ipe_9,
4062 kVmxVDiag_Ipe_10,
4063 kVmxVDiag_Ipe_11,
4064 kVmxVDiag_Ipe_12,
4065 kVmxVDiag_Ipe_13,
4066 kVmxVDiag_Ipe_14,
4067 kVmxVDiag_Ipe_15,
4068 kVmxVDiag_Ipe_16,
4069 /* VMXON. */
4070 kVmxVDiag_Vmxon_A20M,
4071 kVmxVDiag_Vmxon_Cpl,
4072 kVmxVDiag_Vmxon_Cr0Fixed0,
4073 kVmxVDiag_Vmxon_Cr0Fixed1,
4074 kVmxVDiag_Vmxon_Cr4Fixed0,
4075 kVmxVDiag_Vmxon_Cr4Fixed1,
4076 kVmxVDiag_Vmxon_Intercept,
4077 kVmxVDiag_Vmxon_LongModeCS,
4078 kVmxVDiag_Vmxon_MsrFeatCtl,
4079 kVmxVDiag_Vmxon_PtrAbnormal,
4080 kVmxVDiag_Vmxon_PtrAlign,
4081 kVmxVDiag_Vmxon_PtrMap,
4082 kVmxVDiag_Vmxon_PtrReadPhys,
4083 kVmxVDiag_Vmxon_PtrWidth,
4084 kVmxVDiag_Vmxon_RealOrV86Mode,
4085 kVmxVDiag_Vmxon_ShadowVmcs,
4086 kVmxVDiag_Vmxon_VmxAlreadyRoot,
4087 kVmxVDiag_Vmxon_Vmxe,
4088 kVmxVDiag_Vmxon_VmcsRevId,
4089 kVmxVDiag_Vmxon_VmxRootCpl,
4090 /* VMXOFF. */
4091 kVmxVDiag_Vmxoff_Cpl,
4092 kVmxVDiag_Vmxoff_Intercept,
4093 kVmxVDiag_Vmxoff_LongModeCS,
4094 kVmxVDiag_Vmxoff_RealOrV86Mode,
4095 kVmxVDiag_Vmxoff_Vmxe,
4096 kVmxVDiag_Vmxoff_VmxRoot,
4097 /* VMPTRLD. */
4098 kVmxVDiag_Vmptrld_Cpl,
4099 kVmxVDiag_Vmptrld_LongModeCS,
4100 kVmxVDiag_Vmptrld_PtrAbnormal,
4101 kVmxVDiag_Vmptrld_PtrAlign,
4102 kVmxVDiag_Vmptrld_PtrMap,
4103 kVmxVDiag_Vmptrld_PtrReadPhys,
4104 kVmxVDiag_Vmptrld_PtrVmxon,
4105 kVmxVDiag_Vmptrld_PtrWidth,
4106 kVmxVDiag_Vmptrld_RealOrV86Mode,
4107 kVmxVDiag_Vmptrld_RevPtrReadPhys,
4108 kVmxVDiag_Vmptrld_ShadowVmcs,
4109 kVmxVDiag_Vmptrld_VmcsRevId,
4110 kVmxVDiag_Vmptrld_VmxRoot,
4111 /* VMPTRST. */
4112 kVmxVDiag_Vmptrst_Cpl,
4113 kVmxVDiag_Vmptrst_LongModeCS,
4114 kVmxVDiag_Vmptrst_PtrMap,
4115 kVmxVDiag_Vmptrst_RealOrV86Mode,
4116 kVmxVDiag_Vmptrst_VmxRoot,
4117 /* VMCLEAR. */
4118 kVmxVDiag_Vmclear_Cpl,
4119 kVmxVDiag_Vmclear_LongModeCS,
4120 kVmxVDiag_Vmclear_PtrAbnormal,
4121 kVmxVDiag_Vmclear_PtrAlign,
4122 kVmxVDiag_Vmclear_PtrMap,
4123 kVmxVDiag_Vmclear_PtrReadPhys,
4124 kVmxVDiag_Vmclear_PtrVmxon,
4125 kVmxVDiag_Vmclear_PtrWidth,
4126 kVmxVDiag_Vmclear_RealOrV86Mode,
4127 kVmxVDiag_Vmclear_VmxRoot,
4128 /* VMWRITE. */
4129 kVmxVDiag_Vmwrite_Cpl,
4130 kVmxVDiag_Vmwrite_FieldInvalid,
4131 kVmxVDiag_Vmwrite_FieldRo,
4132 kVmxVDiag_Vmwrite_LinkPtrInvalid,
4133 kVmxVDiag_Vmwrite_LongModeCS,
4134 kVmxVDiag_Vmwrite_PtrInvalid,
4135 kVmxVDiag_Vmwrite_PtrMap,
4136 kVmxVDiag_Vmwrite_RealOrV86Mode,
4137 kVmxVDiag_Vmwrite_VmxRoot,
4138 /* VMREAD. */
4139 kVmxVDiag_Vmread_Cpl,
4140 kVmxVDiag_Vmread_FieldInvalid,
4141 kVmxVDiag_Vmread_LinkPtrInvalid,
4142 kVmxVDiag_Vmread_LongModeCS,
4143 kVmxVDiag_Vmread_PtrInvalid,
4144 kVmxVDiag_Vmread_PtrMap,
4145 kVmxVDiag_Vmread_RealOrV86Mode,
4146 kVmxVDiag_Vmread_VmxRoot,
4147 /* INVVPID. */
4148 kVmxVDiag_Invvpid_Cpl,
4149 kVmxVDiag_Invvpid_DescRsvd,
4150 kVmxVDiag_Invvpid_LongModeCS,
4151 kVmxVDiag_Invvpid_RealOrV86Mode,
4152 kVmxVDiag_Invvpid_TypeInvalid,
4153 kVmxVDiag_Invvpid_Type0InvalidAddr,
4154 kVmxVDiag_Invvpid_Type0InvalidVpid,
4155 kVmxVDiag_Invvpid_Type1InvalidVpid,
4156 kVmxVDiag_Invvpid_Type3InvalidVpid,
4157 kVmxVDiag_Invvpid_VmxRoot,
4158 /* VMLAUNCH/VMRESUME. */
4159 kVmxVDiag_Vmentry_AddrApicAccess,
4160 kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
4161 kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
4162 kVmxVDiag_Vmentry_AddrEntryMsrLoad,
4163 kVmxVDiag_Vmentry_AddrExitMsrLoad,
4164 kVmxVDiag_Vmentry_AddrExitMsrStore,
4165 kVmxVDiag_Vmentry_AddrIoBitmapA,
4166 kVmxVDiag_Vmentry_AddrIoBitmapB,
4167 kVmxVDiag_Vmentry_AddrMsrBitmap,
4168 kVmxVDiag_Vmentry_AddrVirtApicPage,
4169 kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
4170 kVmxVDiag_Vmentry_AddrVmreadBitmap,
4171 kVmxVDiag_Vmentry_AddrVmwriteBitmap,
4172 kVmxVDiag_Vmentry_ApicRegVirt,
4173 kVmxVDiag_Vmentry_BlocKMovSS,
4174 kVmxVDiag_Vmentry_Cpl,
4175 kVmxVDiag_Vmentry_Cr3TargetCount,
4176 kVmxVDiag_Vmentry_EntryCtlsAllowed1,
4177 kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
4178 kVmxVDiag_Vmentry_EntryInstrLen,
4179 kVmxVDiag_Vmentry_EntryInstrLenZero,
4180 kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
4181 kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
4182 kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
4183 kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
4184 kVmxVDiag_Vmentry_EptpAccessDirty,
4185 kVmxVDiag_Vmentry_EptpPageWalkLength,
4186 kVmxVDiag_Vmentry_EptpMemType,
4187 kVmxVDiag_Vmentry_EptpRsvd,
4188 kVmxVDiag_Vmentry_ExitCtlsAllowed1,
4189 kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
4190 kVmxVDiag_Vmentry_GuestActStateHlt,
4191 kVmxVDiag_Vmentry_GuestActStateRsvd,
4192 kVmxVDiag_Vmentry_GuestActStateShutdown,
4193 kVmxVDiag_Vmentry_GuestActStateSsDpl,
4194 kVmxVDiag_Vmentry_GuestActStateStiMovSs,
4195 kVmxVDiag_Vmentry_GuestCr0Fixed0,
4196 kVmxVDiag_Vmentry_GuestCr0Fixed1,
4197 kVmxVDiag_Vmentry_GuestCr0PgPe,
4198 kVmxVDiag_Vmentry_GuestCr3,
4199 kVmxVDiag_Vmentry_GuestCr4Fixed0,
4200 kVmxVDiag_Vmentry_GuestCr4Fixed1,
4201 kVmxVDiag_Vmentry_GuestDebugCtl,
4202 kVmxVDiag_Vmentry_GuestDr7,
4203 kVmxVDiag_Vmentry_GuestEferMsr,
4204 kVmxVDiag_Vmentry_GuestEferMsrRsvd,
4205 kVmxVDiag_Vmentry_GuestGdtrBase,
4206 kVmxVDiag_Vmentry_GuestGdtrLimit,
4207 kVmxVDiag_Vmentry_GuestIdtrBase,
4208 kVmxVDiag_Vmentry_GuestIdtrLimit,
4209 kVmxVDiag_Vmentry_GuestIntStateEnclave,
4210 kVmxVDiag_Vmentry_GuestIntStateExtInt,
4211 kVmxVDiag_Vmentry_GuestIntStateNmi,
4212 kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
4213 kVmxVDiag_Vmentry_GuestIntStateRsvd,
4214 kVmxVDiag_Vmentry_GuestIntStateSmi,
4215 kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
4216 kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
4217 kVmxVDiag_Vmentry_GuestPae,
4218 kVmxVDiag_Vmentry_GuestPatMsr,
4219 kVmxVDiag_Vmentry_GuestPcide,
4220 kVmxVDiag_Vmentry_GuestPdpte,
4221 kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
4222 kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
4223 kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
4224 kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
4225 kVmxVDiag_Vmentry_GuestRip,
4226 kVmxVDiag_Vmentry_GuestRipRsvd,
4227 kVmxVDiag_Vmentry_GuestRFlagsIf,
4228 kVmxVDiag_Vmentry_GuestRFlagsRsvd,
4229 kVmxVDiag_Vmentry_GuestRFlagsVm,
4230 kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
4231 kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
4232 kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
4233 kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
4234 kVmxVDiag_Vmentry_GuestSegAttrCsType,
4235 kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
4236 kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
4237 kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
4238 kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
4239 kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
4240 kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
4241 kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
4242 kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
4243 kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
4244 kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
4245 kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
4246 kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
4247 kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
4248 kVmxVDiag_Vmentry_GuestSegAttrGranCs,
4249 kVmxVDiag_Vmentry_GuestSegAttrGranDs,
4250 kVmxVDiag_Vmentry_GuestSegAttrGranEs,
4251 kVmxVDiag_Vmentry_GuestSegAttrGranFs,
4252 kVmxVDiag_Vmentry_GuestSegAttrGranGs,
4253 kVmxVDiag_Vmentry_GuestSegAttrGranSs,
4254 kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
4255 kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
4256 kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
4257 kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
4258 kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
4259 kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
4260 kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
4261 kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
4262 kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
4263 kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
4264 kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
4265 kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
4266 kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
4267 kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
4268 kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
4269 kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
4270 kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
4271 kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
4272 kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
4273 kVmxVDiag_Vmentry_GuestSegAttrSsType,
4274 kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
4275 kVmxVDiag_Vmentry_GuestSegAttrTrGran,
4276 kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
4277 kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
4278 kVmxVDiag_Vmentry_GuestSegAttrTrType,
4279 kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
4280 kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
4281 kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
4282 kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
4283 kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
4284 kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
4285 kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
4286 kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
4287 kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
4288 kVmxVDiag_Vmentry_GuestSegAttrV86Es,
4289 kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
4290 kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
4291 kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
4292 kVmxVDiag_Vmentry_GuestSegBaseCs,
4293 kVmxVDiag_Vmentry_GuestSegBaseDs,
4294 kVmxVDiag_Vmentry_GuestSegBaseEs,
4295 kVmxVDiag_Vmentry_GuestSegBaseFs,
4296 kVmxVDiag_Vmentry_GuestSegBaseGs,
4297 kVmxVDiag_Vmentry_GuestSegBaseLdtr,
4298 kVmxVDiag_Vmentry_GuestSegBaseSs,
4299 kVmxVDiag_Vmentry_GuestSegBaseTr,
4300 kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
4301 kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
4302 kVmxVDiag_Vmentry_GuestSegBaseV86Es,
4303 kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
4304 kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
4305 kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
4306 kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
4307 kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
4308 kVmxVDiag_Vmentry_GuestSegLimitV86Es,
4309 kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
4310 kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
4311 kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
4312 kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
4313 kVmxVDiag_Vmentry_GuestSegSelLdtr,
4314 kVmxVDiag_Vmentry_GuestSegSelTr,
4315 kVmxVDiag_Vmentry_GuestSysenterEspEip,
4316 kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
4317 kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
4318 kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
4319 kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
4320 kVmxVDiag_Vmentry_HostCr0Fixed0,
4321 kVmxVDiag_Vmentry_HostCr0Fixed1,
4322 kVmxVDiag_Vmentry_HostCr3,
4323 kVmxVDiag_Vmentry_HostCr4Fixed0,
4324 kVmxVDiag_Vmentry_HostCr4Fixed1,
4325 kVmxVDiag_Vmentry_HostCr4Pae,
4326 kVmxVDiag_Vmentry_HostCr4Pcide,
4327 kVmxVDiag_Vmentry_HostCsTr,
4328 kVmxVDiag_Vmentry_HostEferMsr,
4329 kVmxVDiag_Vmentry_HostEferMsrRsvd,
4330 kVmxVDiag_Vmentry_HostGuestLongMode,
4331 kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4332 kVmxVDiag_Vmentry_HostLongMode,
4333 kVmxVDiag_Vmentry_HostPatMsr,
4334 kVmxVDiag_Vmentry_HostRip,
4335 kVmxVDiag_Vmentry_HostRipRsvd,
4336 kVmxVDiag_Vmentry_HostSel,
4337 kVmxVDiag_Vmentry_HostSegBase,
4338 kVmxVDiag_Vmentry_HostSs,
4339 kVmxVDiag_Vmentry_HostSysenterEspEip,
4340 kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys,
4341 kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys,
4342 kVmxVDiag_Vmentry_LongModeCS,
4343 kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4344 kVmxVDiag_Vmentry_MsrLoad,
4345 kVmxVDiag_Vmentry_MsrLoadCount,
4346 kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4347 kVmxVDiag_Vmentry_MsrLoadRing3,
4348 kVmxVDiag_Vmentry_MsrLoadRsvd,
4349 kVmxVDiag_Vmentry_NmiWindowExit,
4350 kVmxVDiag_Vmentry_PinCtlsAllowed1,
4351 kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4352 kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4353 kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4354 kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4355 kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4356 kVmxVDiag_Vmentry_PtrInvalid,
4357 kVmxVDiag_Vmentry_PtrShadowVmcs,
4358 kVmxVDiag_Vmentry_RealOrV86Mode,
4359 kVmxVDiag_Vmentry_SavePreemptTimer,
4360 kVmxVDiag_Vmentry_TprThresholdRsvd,
4361 kVmxVDiag_Vmentry_TprThresholdVTpr,
4362 kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4363 kVmxVDiag_Vmentry_VirtIntDelivery,
4364 kVmxVDiag_Vmentry_VirtNmi,
4365 kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4366 kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4367 kVmxVDiag_Vmentry_VmcsClear,
4368 kVmxVDiag_Vmentry_VmcsLaunch,
4369 kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4370 kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4371 kVmxVDiag_Vmentry_VmxRoot,
4372 kVmxVDiag_Vmentry_Vpid,
4373 kVmxVDiag_Vmexit_HostPdpte,
4374 kVmxVDiag_Vmexit_MsrLoad,
4375 kVmxVDiag_Vmexit_MsrLoadCount,
4376 kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4377 kVmxVDiag_Vmexit_MsrLoadRing3,
4378 kVmxVDiag_Vmexit_MsrLoadRsvd,
4379 kVmxVDiag_Vmexit_MsrStore,
4380 kVmxVDiag_Vmexit_MsrStoreCount,
4381 kVmxVDiag_Vmexit_MsrStorePtrReadPhys,
4382 kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4383 kVmxVDiag_Vmexit_MsrStoreRing3,
4384 kVmxVDiag_Vmexit_MsrStoreRsvd,
4385 kVmxVDiag_Vmexit_VirtApicPagePtrWritePhys,
4386 /* Last member for determining array index limit. */
4387 kVmxVDiag_End
4388} VMXVDIAG;
4389AssertCompileSize(VMXVDIAG, 4);
4390
4391/** @} */
4392
4393/** @} */
4394
4395#endif /* !VBOX_INCLUDED_vmm_hm_vmx_h */
4396
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