hm_vmx.h@ 92585

Last change on this file since 92585 was 92479, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Renamed EPT bitfield macro to be more consistent.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_hm_vmx_h
27	#define VBOX_INCLUDED_vmm_hm_vmx_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <iprt/x86.h>
34	#include <iprt/assertcompile.h>
35
36
37	/** @defgroup grp_hm_vmx VMX Types and Definitions
38	* @ingroup grp_hm
39	* @{
40	*/
41
42	/** @name Host-state MSR lazy-restoration flags.
43	* @{
44	*/
45	/** The host MSRs have been saved. */
46	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
47	/** The guest MSRs are loaded and in effect. */
48	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
49	/** @} */
50
51	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
52	* UFC = Unsupported Feature Combination.
53	* @{
54	*/
55	/** Unsupported pin-based VM-execution controls combo. */
56	#define VMX_UFC_CTRL_PIN_EXEC 1
57	/** Unsupported processor-based VM-execution controls combo. */
58	#define VMX_UFC_CTRL_PROC_EXEC 2
59	/** Unsupported move debug register VM-exit combo. */
60	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
61	/** Unsupported VM-entry controls combo. */
62	#define VMX_UFC_CTRL_ENTRY 4
63	/** Unsupported VM-exit controls combo. */
64	#define VMX_UFC_CTRL_EXIT 5
65	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
66	* for storing host MSRs. */
67	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
68	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
69	* for storing guest MSRs. */
70	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
71	/** Invalid VMCS size. */
72	#define VMX_UFC_INVALID_VMCS_SIZE 8
73	/** Unsupported secondary processor-based VM-execution controls combo. */
74	#define VMX_UFC_CTRL_PROC_EXEC2 9
75	/** Invalid unrestricted-guest execution controls combo. */
76	#define VMX_UFC_INVALID_UX_COMBO 10
77	/** EPT flush type not supported. */
78	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
79	/** EPT paging structure memory type is not write-back. */
80	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
81	/** EPT requires INVEPT instr. support but it's not available. */
82	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
83	/** EPT requires page-walk length of 4. */
84	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
85	/** VMX VMWRITE all feature exposed to the guest but not supported on host. */
86	#define VMX_UFC_GST_HOST_VMWRITE_ALL 15
87	/** LBR stack size cannot be determined for the current CPU. */
88	#define VMX_UFC_LBR_STACK_SIZE_UNKNOWN 16
89	/** LBR stack size of the CPU exceeds our buffer size. */
90	#define VMX_UFC_LBR_STACK_SIZE_OVERFLOW 17
91	/** @} */
92
93	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
94	* VCI = VMCS-field Cache Invalid.
95	* @{
96	*/
97	/** Cache of VM-entry controls invalid. */
98	#define VMX_VCI_CTRL_ENTRY 300
99	/** Cache of VM-exit controls invalid. */
100	#define VMX_VCI_CTRL_EXIT 301
101	/** Cache of pin-based VM-execution controls invalid. */
102	#define VMX_VCI_CTRL_PIN_EXEC 302
103	/** Cache of processor-based VM-execution controls invalid. */
104	#define VMX_VCI_CTRL_PROC_EXEC 303
105	/** Cache of secondary processor-based VM-execution controls invalid. */
106	#define VMX_VCI_CTRL_PROC_EXEC2 304
107	/** Cache of exception bitmap invalid. */
108	#define VMX_VCI_CTRL_XCPT_BITMAP 305
109	/** Cache of TSC offset invalid. */
110	#define VMX_VCI_CTRL_TSC_OFFSET 306
111	/** Cache of tertiary processor-based VM-execution controls invalid. */
112	#define VMX_VCI_CTRL_PROC_EXEC3 307
113	/** @} */
114
115	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
116	* IGS = Invalid Guest State.
117	* @{
118	*/
119	/** An error occurred while checking invalid-guest-state. */
120	#define VMX_IGS_ERROR 500
121	/** The invalid guest-state checks did not find any reason why. */
122	#define VMX_IGS_REASON_NOT_FOUND 501
123	/** CR0 fixed1 bits invalid. */
124	#define VMX_IGS_CR0_FIXED1 502
125	/** CR0 fixed0 bits invalid. */
126	#define VMX_IGS_CR0_FIXED0 503
127	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
128	#define VMX_IGS_CR0_PG_PE_COMBO 504
129	/** CR4 fixed1 bits invalid. */
130	#define VMX_IGS_CR4_FIXED1 505
131	/** CR4 fixed0 bits invalid. */
132	#define VMX_IGS_CR4_FIXED0 506
133	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
134	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
135	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
136	/** CR0.PG not set for long-mode when not using unrestricted guest. */
137	#define VMX_IGS_CR0_PG_LONGMODE 508
138	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
139	#define VMX_IGS_CR4_PAE_LONGMODE 509
140	/** CR4.PCIDE set for 32-bit guest. */
141	#define VMX_IGS_CR4_PCIDE 510
142	/** VMCS' DR7 reserved bits not set to 0. */
143	#define VMX_IGS_DR7_RESERVED 511
144	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
145	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
146	/** VMCS' EFER MSR reserved bits not set to 0. */
147	#define VMX_IGS_EFER_MSR_RESERVED 513
148	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
149	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
150	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
151	* without unrestricted guest. */
152	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
153	/** CS.Attr.P bit invalid. */
154	#define VMX_IGS_CS_ATTR_P_INVALID 516
155	/** CS.Attr reserved bits not set to 0. */
156	#define VMX_IGS_CS_ATTR_RESERVED 517
157	/** CS.Attr.G bit invalid. */
158	#define VMX_IGS_CS_ATTR_G_INVALID 518
159	/** CS is unusable. */
160	#define VMX_IGS_CS_ATTR_UNUSABLE 519
161	/** CS and SS DPL unequal. */
162	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
163	/** CS and SS DPL mismatch. */
164	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
165	/** CS Attr.Type invalid. */
166	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
167	/** CS and SS RPL unequal. */
168	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
169	/** SS.Attr.DPL and SS RPL unequal. */
170	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
171	/** SS.Attr.DPL invalid for segment type. */
172	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
173	/** SS.Attr.Type invalid. */
174	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
175	/** SS.Attr.P bit invalid. */
176	#define VMX_IGS_SS_ATTR_P_INVALID 527
177	/** SS.Attr reserved bits not set to 0. */
178	#define VMX_IGS_SS_ATTR_RESERVED 528
179	/** SS.Attr.G bit invalid. */
180	#define VMX_IGS_SS_ATTR_G_INVALID 529
181	/** DS.Attr.A bit invalid. */
182	#define VMX_IGS_DS_ATTR_A_INVALID 530
183	/** DS.Attr.P bit invalid. */
184	#define VMX_IGS_DS_ATTR_P_INVALID 531
185	/** DS.Attr.DPL and DS RPL unequal. */
186	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
187	/** DS.Attr reserved bits not set to 0. */
188	#define VMX_IGS_DS_ATTR_RESERVED 533
189	/** DS.Attr.G bit invalid. */
190	#define VMX_IGS_DS_ATTR_G_INVALID 534
191	/** DS.Attr.Type invalid. */
192	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
193	/** ES.Attr.A bit invalid. */
194	#define VMX_IGS_ES_ATTR_A_INVALID 536
195	/** ES.Attr.P bit invalid. */
196	#define VMX_IGS_ES_ATTR_P_INVALID 537
197	/** ES.Attr.DPL and DS RPL unequal. */
198	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
199	/** ES.Attr reserved bits not set to 0. */
200	#define VMX_IGS_ES_ATTR_RESERVED 539
201	/** ES.Attr.G bit invalid. */
202	#define VMX_IGS_ES_ATTR_G_INVALID 540
203	/** ES.Attr.Type invalid. */
204	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
205	/** FS.Attr.A bit invalid. */
206	#define VMX_IGS_FS_ATTR_A_INVALID 542
207	/** FS.Attr.P bit invalid. */
208	#define VMX_IGS_FS_ATTR_P_INVALID 543
209	/** FS.Attr.DPL and DS RPL unequal. */
210	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
211	/** FS.Attr reserved bits not set to 0. */
212	#define VMX_IGS_FS_ATTR_RESERVED 545
213	/** FS.Attr.G bit invalid. */
214	#define VMX_IGS_FS_ATTR_G_INVALID 546
215	/** FS.Attr.Type invalid. */
216	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
217	/** GS.Attr.A bit invalid. */
218	#define VMX_IGS_GS_ATTR_A_INVALID 548
219	/** GS.Attr.P bit invalid. */
220	#define VMX_IGS_GS_ATTR_P_INVALID 549
221	/** GS.Attr.DPL and DS RPL unequal. */
222	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
223	/** GS.Attr reserved bits not set to 0. */
224	#define VMX_IGS_GS_ATTR_RESERVED 551
225	/** GS.Attr.G bit invalid. */
226	#define VMX_IGS_GS_ATTR_G_INVALID 552
227	/** GS.Attr.Type invalid. */
228	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
229	/** V86 mode CS.Base invalid. */
230	#define VMX_IGS_V86_CS_BASE_INVALID 554
231	/** V86 mode CS.Limit invalid. */
232	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
233	/** V86 mode CS.Attr invalid. */
234	#define VMX_IGS_V86_CS_ATTR_INVALID 556
235	/** V86 mode SS.Base invalid. */
236	#define VMX_IGS_V86_SS_BASE_INVALID 557
237	/** V86 mode SS.Limit invalid. */
238	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
239	/** V86 mode SS.Attr invalid. */
240	#define VMX_IGS_V86_SS_ATTR_INVALID 559
241	/** V86 mode DS.Base invalid. */
242	#define VMX_IGS_V86_DS_BASE_INVALID 560
243	/** V86 mode DS.Limit invalid. */
244	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
245	/** V86 mode DS.Attr invalid. */
246	#define VMX_IGS_V86_DS_ATTR_INVALID 562
247	/** V86 mode ES.Base invalid. */
248	#define VMX_IGS_V86_ES_BASE_INVALID 563
249	/** V86 mode ES.Limit invalid. */
250	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
251	/** V86 mode ES.Attr invalid. */
252	#define VMX_IGS_V86_ES_ATTR_INVALID 565
253	/** V86 mode FS.Base invalid. */
254	#define VMX_IGS_V86_FS_BASE_INVALID 566
255	/** V86 mode FS.Limit invalid. */
256	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
257	/** V86 mode FS.Attr invalid. */
258	#define VMX_IGS_V86_FS_ATTR_INVALID 568
259	/** V86 mode GS.Base invalid. */
260	#define VMX_IGS_V86_GS_BASE_INVALID 569
261	/** V86 mode GS.Limit invalid. */
262	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
263	/** V86 mode GS.Attr invalid. */
264	#define VMX_IGS_V86_GS_ATTR_INVALID 571
265	/** Longmode CS.Base invalid. */
266	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
267	/** Longmode SS.Base invalid. */
268	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
269	/** Longmode DS.Base invalid. */
270	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
271	/** Longmode ES.Base invalid. */
272	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
273	/** SYSENTER ESP is not canonical. */
274	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
275	/** SYSENTER EIP is not canonical. */
276	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
277	/** PAT MSR invalid. */
278	#define VMX_IGS_PAT_MSR_INVALID 578
279	/** PAT MSR reserved bits not set to 0. */
280	#define VMX_IGS_PAT_MSR_RESERVED 579
281	/** GDTR.Base is not canonical. */
282	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
283	/** IDTR.Base is not canonical. */
284	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
285	/** GDTR.Limit invalid. */
286	#define VMX_IGS_GDTR_LIMIT_INVALID 582
287	/** IDTR.Limit invalid. */
288	#define VMX_IGS_IDTR_LIMIT_INVALID 583
289	/** Longmode RIP is invalid. */
290	#define VMX_IGS_LONGMODE_RIP_INVALID 584
291	/** RFLAGS reserved bits not set to 0. */
292	#define VMX_IGS_RFLAGS_RESERVED 585
293	/** RFLAGS RA1 reserved bits not set to 1. */
294	#define VMX_IGS_RFLAGS_RESERVED1 586
295	/** RFLAGS.VM (V86 mode) invalid. */
296	#define VMX_IGS_RFLAGS_VM_INVALID 587
297	/** RFLAGS.IF invalid. */
298	#define VMX_IGS_RFLAGS_IF_INVALID 588
299	/** Activity state invalid. */
300	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
301	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
302	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
303	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
304	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
305	/** Activity state SIPI WAIT invalid. */
306	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
307	/** Interruptibility state reserved bits not set to 0. */
308	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
309	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
310	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
311	/** Interruptibility state block-by-STI invalid for EFLAGS. */
312	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
313	/** Interruptibility state invalid while trying to deliver external
314	* interrupt. */
315	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
316	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
317	* NMI. */
318	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
319	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
320	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
321	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
322	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
323	/** Interruptibility state block-by-STI (maybe) invalid when trying to
324	* deliver an NMI. */
325	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
326	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
327	* active. */
328	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
329	/** Pending debug exceptions reserved bits not set to 0. */
330	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
331	/** Longmode pending debug exceptions reserved bits not set to 0. */
332	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
333	/** Pending debug exceptions.BS bit is not set when it should be. */
334	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
335	/** Pending debug exceptions.BS bit is not clear when it should be. */
336	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
337	/** VMCS link pointer reserved bits not set to 0. */
338	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
339	/** TR cannot index into LDT, TI bit MBZ. */
340	#define VMX_IGS_TR_TI_INVALID 607
341	/** LDTR cannot index into LDT. TI bit MBZ. */
342	#define VMX_IGS_LDTR_TI_INVALID 608
343	/** TR.Base is not canonical. */
344	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
345	/** FS.Base is not canonical. */
346	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
347	/** GS.Base is not canonical. */
348	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
349	/** LDTR.Base is not canonical. */
350	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
351	/** TR is unusable. */
352	#define VMX_IGS_TR_ATTR_UNUSABLE 613
353	/** TR.Attr.S bit invalid. */
354	#define VMX_IGS_TR_ATTR_S_INVALID 614
355	/** TR is not present. */
356	#define VMX_IGS_TR_ATTR_P_INVALID 615
357	/** TR.Attr reserved bits not set to 0. */
358	#define VMX_IGS_TR_ATTR_RESERVED 616
359	/** TR.Attr.G bit invalid. */
360	#define VMX_IGS_TR_ATTR_G_INVALID 617
361	/** Longmode TR.Attr.Type invalid. */
362	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
363	/** TR.Attr.Type invalid. */
364	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
365	/** CS.Attr.S invalid. */
366	#define VMX_IGS_CS_ATTR_S_INVALID 620
367	/** CS.Attr.DPL invalid. */
368	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
369	/** PAE PDPTE reserved bits not set to 0. */
370	#define VMX_IGS_PAE_PDPTE_RESERVED 623
371	/** VMCS link pointer does not point to a shadow VMCS. */
372	#define VMX_IGS_VMCS_LINK_PTR_NOT_SHADOW 624
373	/** VMCS link pointer to a shadow VMCS with invalid VMCS revision identifer. */
374	#define VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID 625
375	/** @} */
376
377	/** @name VMX VMCS-Read cache indices.
378	* @{
379	*/
380	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
381	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
382	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
383	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
384	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
385	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
386	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
387	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
388	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
389	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
390	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
391	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
392	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
393	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
394	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
395	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
396	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
397	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
398	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
399	/** @} */
400
401	/** @name VMX Extended Page Tables (EPT) Common Bits
402	* @{ */
403	/** Bit 0 - Readable (we often think of it as present). */
404	#define EPT_E_BIT_READ 0
405	#define EPT_E_READ RT_BIT_64(EPT_E_BIT_READ) /*< @see EPT_E_BIT_READ /
406	/** Bit 1 - Writable. */
407	#define EPT_E_BIT_WRITE 1
408	#define EPT_E_WRITE RT_BIT_64(EPT_E_BIT_WRITE) /*< @see EPT_E_BIT_WRITE /
409	/** Bit 2 - Executable.
410	* @note This controls supervisor instruction fetching if mode-based
411	* execution control is enabled. */
412	#define EPT_E_BIT_EXECUTE 2
413	#define EPT_E_EXECUTE RT_BIT_64(EPT_E_BIT_EXECUTE) /*< @see EPT_E_BIT_EXECUTE /
414	/** Bits 3-5 - Memory type mask (leaf only, MBZ).
415	* The memory type is only applicable for leaf entries and MBZ for
416	* non-leaf (causes miconfiguration exit). */
417	#define EPT_E_MEMTYPE_MASK UINT64_C(0x0038)
418	/** Bits 3-5 - Memory type shifted mask. */
419	#define EPT_E_MEMTYPE_SMASK UINT64_C(0x0007)
420	/** Bits 3-5 - Memory type shift count. */
421	#define EPT_E_MEMTYPE_SHIFT 3
422	/** Bits 3-5 - Memory type: UC. */
423	#define EPT_E_MEMTYPE_UC (UINT64_C(0) << EPT_E_MEMTYPE_SHIFT)
424	/** Bits 3-5 - Memory type: WC. */
425	#define EPT_E_MEMTYPE_WC (UINT64_C(1) << EPT_E_MEMTYPE_SHIFT)
426	/** Bits 3-5 - Memory type: Invalid (2). */
427	#define EPT_E_MEMTYPE_INVALID_2 (UINT64_C(2) << EPT_E_MEMTYPE_SHIFT)
428	/** Bits 3-5 - Memory type: Invalid (3). */
429	#define EPT_E_MEMTYPE_INVALID_3 (UINT64_C(3) << EPT_E_MEMTYPE_SHIFT)
430	/** Bits 3-5 - Memory type: WT. */
431	#define EPT_E_MEMTYPE_WT (UINT64_C(4) << EPT_E_MEMTYPE_SHIFT)
432	/** Bits 3-5 - Memory type: WP. */
433	#define EPT_E_MEMTYPE_WP (UINT64_C(5) << EPT_E_MEMTYPE_SHIFT)
434	/** Bits 3-5 - Memory type: WB. */
435	#define EPT_E_MEMTYPE_WB (UINT64_C(6) << EPT_E_MEMTYPE_SHIFT)
436	/** Bits 3-5 - Memory type: Invalid (7). */
437	#define EPT_E_MEMTYPE_INVALID_7 (UINT64_C(7) << EPT_E_MEMTYPE_SHIFT)
438
439	/** Bit 6 - Ignore page attribute table (leaf, MBZ). */
440	#define EPT_E_BIT_IGNORE_PAT 6
441	#define EPT_E_IGNORE_PAT RT_BIT_64(EPT_E_BIT_IGNORE_PAT) /*< @see EPT_E_BIT_IGNORE_PAT /
442	/** Bit 7 - Leaf entry (MBZ in PML4, ignored in PT). */
443	#define EPT_E_BIT_LEAF 7
444	#define EPT_E_LEAF RT_BIT_64(EPT_E_BIT_LEAF) /*< @see EPT_E_BIT_LEAF /
445	/** Bit 8 - Accessed (all levels).
446	* @note Ignored and not written when EPTP bit 6 is 0. */
447	#define EPT_E_BIT_ACCESSED 8
448	#define EPT_E_ACCESSED RT_BIT_64(EPT_E_BIT_ACCESSED) /*< @see EPT_E_BIT_ACCESSED /
449	/** Bit 9 - Dirty (leaf only).
450	* @note Ignored and not written when EPTP bit 6 is 0. */
451	#define EPT_E_BIT_DIRTY 9
452	#define EPT_E_DIRTY RT_BIT_64(EPT_E_BIT_DIRTY) /*< @see EPT_E_BIT_DIRTY /
453	/** Bit 10 - Executable for usermode.
454	* @note This ignored if mode-based execution control is disabled. */
455	#define EPT_E_BIT_USER_EXECUTE 10
456	#define EPT_E_USER_EXECUTE RT_BIT_64(EPT_E_BIT_USER_EXECUTE) /*< @see EPT_E_BIT_USER_EXECUTE /
457
458	/* 11 is always ignored (at time of writing) */
459
460	/** Bits 12-51 - Physical Page number of the next level. */
461	#define EPT_E_PG_MASK UINT64_C(0x000ffffffffff000)
462
463	/** Bit 60 - Supervisor shadow stack (leaf only, ignored).
464	* @note Ignored if EPT bit 7 is 0. */
465	#define EPT_E_BIT_SHADOW_STACK 60
466	#define EPT_E_SHADOW_STACK RT_BIT_64(EPT_E_BIT_SHADOW_STACK) /*< @see EPT_E_BIT_SHADOW_STACK/
467
468	/* Bit 61, 62 are always ignored at time of writing. */
469
470	/** Bit 63 - Suppress \#VE (leaf only, ignored).
471	* @note Ignored if EPT violation to \#VE conversion is disabled. */
472	#define EPT_E_BIT_SUPPRESS_VE 63
473	#define EPT_E_SUPPRESS_VE RT_BIT_64(EPT_E_BIT_SUPPRESS_VE) /*< @see EPT_E_BIT_SUPPRESS_VE/
474	/** @} */
475
476
477	/**@name Bit fields for common EPT attributes.
478	@{ */
479	/** Read access. */
480	#define VMX_BF_EPT_PT_READ_SHIFT 0
481	#define VMX_BF_EPT_PT_READ_MASK UINT64_C(0x0000000000000001)
482	/** Write access. */
483	#define VMX_BF_EPT_PT_WRITE_SHIFT 1
484	#define VMX_BF_EPT_PT_WRITE_MASK UINT64_C(0x0000000000000002)
485	/** Execute access or execute access for supervisor-mode linear-addresses. */
486	#define VMX_BF_EPT_PT_EXECUTE_SHIFT 2
487	#define VMX_BF_EPT_PT_EXECUTE_MASK UINT64_C(0x0000000000000004)
488	/** EPT memory type. */
489	#define VMX_BF_EPT_PT_MEMTYPE_SHIFT 3
490	#define VMX_BF_EPT_PT_MEMTYPE_MASK UINT64_C(0x0000000000000038)
491	/** Ignore PAT. */
492	#define VMX_BF_EPT_PT_IGNORE_PAT_SHIFT 6
493	#define VMX_BF_EPT_PT_IGNORE_PAT_MASK UINT64_C(0x0000000000000040)
494	/** Ignored (bit 7). */
495	#define VMX_BF_EPT_PT_IGN_7_SHIFT 7
496	#define VMX_BF_EPT_PT_IGN_7_MASK UINT64_C(0x0000000000000080)
497	/** Accessed flag. */
498	#define VMX_BF_EPT_PT_ACCESSED_SHIFT 8
499	#define VMX_BF_EPT_PT_ACCESSED_MASK UINT64_C(0x0000000000000100)
500	/** Dirty flag. */
501	#define VMX_BF_EPT_PT_DIRTY_SHIFT 9
502	#define VMX_BF_EPT_PT_DIRTY_MASK UINT64_C(0x0000000000000200)
503	/** Execute access for user-mode linear addresses. */
504	#define VMX_BF_EPT_PT_EXECUTE_USER_SHIFT 10
505	#define VMX_BF_EPT_PT_EXECUTE_USER_MASK UINT64_C(0x0000000000000400)
506	/** Ignored (bit 59:11). */
507	#define VMX_BF_EPT_PT_IGN_59_11_SHIFT 11
508	#define VMX_BF_EPT_PT_IGN_59_11_MASK UINT64_C(0x0ffffffffffff800)
509	/** Supervisor shadow stack. */
510	#define VMX_BF_EPT_PT_SUPER_SHW_STACK_SHIFT 60
511	#define VMX_BF_EPT_PT_SUPER_SHW_STACK_MASK UINT64_C(0x1000000000000000)
512	/** Ignored (bits 62:61). */
513	#define VMX_BF_EPT_PT_IGN_62_61_SHIFT 61
514	#define VMX_BF_EPT_PT_IGN_62_61_MASK UINT64_C(0x6000000000000000)
515	/** Suppress \#VE. */
516	#define VMX_BF_EPT_PT_SUPPRESS_VE_SHIFT 63
517	#define VMX_BF_EPT_PT_SUPPRESS_VE_MASK UINT64_C(0x8000000000000000)
518	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_PT_, UINT64_C(0), UINT64_MAX,
519	(READ, WRITE, EXECUTE, MEMTYPE, IGNORE_PAT, IGN_7, ACCESSED, DIRTY, EXECUTE_USER, IGN_59_11,
520	SUPER_SHW_STACK, IGN_62_61, SUPPRESS_VE));
521	/** @} */
522
523
524	/** @name VMX Extended Page Tables (EPT) Structures
525	* @{
526	*/
527
528	/**
529	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
530	*/
531	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
532
533	/**
534	* EPT Page Directory Pointer Entry. Bit view.
535	* In accordance with the VT-x spec.
536	*
537	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
538	* this did cause trouble with one compiler/version).
539	*/
540	typedef struct EPTPML4EBITS
541	{
542	/** Present bit. */
543	RT_GCC_EXTENSION uint64_t u1Present : 1;
544	/** Writable bit. */
545	RT_GCC_EXTENSION uint64_t u1Write : 1;
546	/** Executable bit. */
547	RT_GCC_EXTENSION uint64_t u1Execute : 1;
548	/** Reserved (must be 0). */
549	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
550	/** Available for software. */
551	RT_GCC_EXTENSION uint64_t u4Available : 4;
552	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
553	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
554	/** Available for software. */
555	RT_GCC_EXTENSION uint64_t u12Available : 12;
556	} EPTPML4EBITS;
557	AssertCompileSize(EPTPML4EBITS, 8);
558
559	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
560	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
561	/** The page shift to get the PML4 index. */
562	#define EPT_PML4_SHIFT X86_PML4_SHIFT
563	/** The PML4 index mask (apply to a shifted page address). */
564	#define EPT_PML4_MASK X86_PML4_MASK
565	/** Bits - - EPT - PML4 MBZ mask. */
566	#define EPT_PML4E_MBZ_MASK UINT64_C(0x00000000000000f8)
567	/** Mask of all possible EPT PML4E attribute bits. */
568	#define EPT_PML4E_ATTR_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
569
570	/**
571	* EPT PML4E.
572	* In accordance with the VT-x spec.
573	*/
574	typedef union EPTPML4E
575	{
576	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
577	/** Normal view. */
578	EPTPML4EBITS n;
579	#endif
580	/** Unsigned integer view. */
581	X86PGPAEUINT u;
582	/** 64 bit unsigned integer view. */
583	uint64_t au64[1];
584	/** 32 bit unsigned integer view. */
585	uint32_t au32[2];
586	} EPTPML4E;
587	AssertCompileSize(EPTPML4E, 8);
588	/** Pointer to a PML4 table entry. */
589	typedef EPTPML4E *PEPTPML4E;
590	/** Pointer to a const PML4 table entry. */
591	typedef const EPTPML4E *PCEPTPML4E;
592
593	/**
594	* EPT PML4 Table.
595	* In accordance with the VT-x spec.
596	*/
597	typedef struct EPTPML4
598	{
599	EPTPML4E a[EPT_PG_ENTRIES];
600	} EPTPML4;
601	AssertCompileSize(EPTPML4, 0x1000);
602	/** Pointer to an EPT PML4 Table. */
603	typedef EPTPML4 *PEPTPML4;
604	/** Pointer to a const EPT PML4 Table. */
605	typedef const EPTPML4 *PCEPTPML4;
606
607
608	/**
609	* EPT Page Directory Pointer Entry. Bit view.
610	* In accordance with the VT-x spec.
611	*/
612	typedef struct EPTPDPTEBITS
613	{
614	/** Present bit. */
615	RT_GCC_EXTENSION uint64_t u1Present : 1;
616	/** Writable bit. */
617	RT_GCC_EXTENSION uint64_t u1Write : 1;
618	/** Executable bit. */
619	RT_GCC_EXTENSION uint64_t u1Execute : 1;
620	/** Reserved (must be 0). */
621	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
622	/** Available for software. */
623	RT_GCC_EXTENSION uint64_t u4Available : 4;
624	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
625	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
626	/** Available for software. */
627	RT_GCC_EXTENSION uint64_t u12Available : 12;
628	} EPTPDPTEBITS;
629	AssertCompileSize(EPTPDPTEBITS, 8);
630
631	/** Bit 7 - - EPT - PDPTE maps a 1GB page. */
632	#define EPT_PDPTE1G_SIZE_MASK RT_BIT_64(7)
633	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
634	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
635	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
636	#define EPT_PDPTE1G_PG_MASK X86_PDPE_PG_MASK
637
638	/** The page shift to get the PDPT index. */
639	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
640	/** The PDPT index mask (apply to a shifted page address). */
641	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
642	/** Bits 3-7 - - EPT - PDPTE MBZ Mask. */
643	#define EPT_PDPTE_MBZ_MASK UINT64_C(0x00000000000000f8)
644	/** Bits 12-29 - - EPT - 1GB PDPTE MBZ Mask. */
645	#define EPT_PDPTE1G_MBZ_MASK UINT64_C(0x000000003ffff000)
646	/** Mask of all possible EPT PDPTE (1GB) attribute bits. */
647	#define EPT_PDPTE1G_ATTR_MASK ( EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_MASK \| EPT_E_IGNORE_PAT \
648	\| EPT_E_ACCESSED \| EPT_E_DIRTY \| EPT_E_USER_EXECUTE)
649	/** Mask of all possible EPT PDPTE attribute bits. */
650	#define EPT_PDPTE_ATTR_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
651	/** */
652
653	/**
654	* EPT Page Directory Pointer.
655	* In accordance with the VT-x spec.
656	*/
657	typedef union EPTPDPTE
658	{
659	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
660	/** Normal view. */
661	EPTPDPTEBITS n;
662	#endif
663	/** Unsigned integer view. */
664	X86PGPAEUINT u;
665	/** 64 bit unsigned integer view. */
666	uint64_t au64[1];
667	/** 32 bit unsigned integer view. */
668	uint32_t au32[2];
669	} EPTPDPTE;
670	AssertCompileSize(EPTPDPTE, 8);
671	/** Pointer to an EPT Page Directory Pointer Entry. */
672	typedef EPTPDPTE *PEPTPDPTE;
673	/** Pointer to a const EPT Page Directory Pointer Entry. */
674	typedef const EPTPDPTE *PCEPTPDPTE;
675
676	/**
677	* EPT Page Directory Pointer Table.
678	* In accordance with the VT-x spec.
679	*/
680	typedef struct EPTPDPT
681	{
682	EPTPDPTE a[EPT_PG_ENTRIES];
683	} EPTPDPT;
684	AssertCompileSize(EPTPDPT, 0x1000);
685	/** Pointer to an EPT Page Directory Pointer Table. */
686	typedef EPTPDPT *PEPTPDPT;
687	/** Pointer to a const EPT Page Directory Pointer Table. */
688	typedef const EPTPDPT *PCEPTPDPT;
689
690
691	/**
692	* EPT Page Directory Table Entry. Bit view.
693	* In accordance with the VT-x spec.
694	*/
695	typedef struct EPTPDEBITS
696	{
697	/** Present bit. */
698	RT_GCC_EXTENSION uint64_t u1Present : 1;
699	/** Writable bit. */
700	RT_GCC_EXTENSION uint64_t u1Write : 1;
701	/** Executable bit. */
702	RT_GCC_EXTENSION uint64_t u1Execute : 1;
703	/** Reserved (must be 0). */
704	RT_GCC_EXTENSION uint64_t u4Reserved : 4;
705	/** Big page (must be 0 here). */
706	RT_GCC_EXTENSION uint64_t u1Size : 1;
707	/** Available for software. */
708	RT_GCC_EXTENSION uint64_t u4Available : 4;
709	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
710	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
711	/** Available for software. */
712	RT_GCC_EXTENSION uint64_t u12Available : 12;
713	} EPTPDEBITS;
714	AssertCompileSize(EPTPDEBITS, 8);
715
716	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
717	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
718	/** The page shift to get the PD index. */
719	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
720	/** The PD index mask (apply to a shifted page address). */
721	#define EPT_PD_MASK X86_PD_PAE_MASK
722	/** Bits 3-7 - EPT - PDE MBZ Mask. */
723	#define EPT_PDE_MBZ_MASK UINT64_C(0x00000000000000f8)
724	/** Mask of all possible EPT PDE (2M) attribute bits. */
725	#define EPT_PDE2M_ATTR_MASK ( EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_MASK \| EPT_E_IGNORE_PAT \
726	\| EPT_E_ACCESSED \| EPT_E_DIRTY \| EPT_E_USER_EXECUTE)
727	/** Mask of all possible EPT PDE attribute bits. */
728	#define EPT_PDE_ATTR_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
729
730
731	/**
732	* EPT 2MB Page Directory Table Entry. Bit view.
733	* In accordance with the VT-x spec.
734	*/
735	typedef struct EPTPDE2MBITS
736	{
737	/** Present bit. */
738	RT_GCC_EXTENSION uint64_t u1Present : 1;
739	/** Writable bit. */
740	RT_GCC_EXTENSION uint64_t u1Write : 1;
741	/** Executable bit. */
742	RT_GCC_EXTENSION uint64_t u1Execute : 1;
743	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
744	RT_GCC_EXTENSION uint64_t u3EMT : 3;
745	/** Ignore PAT memory type */
746	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
747	/** Big page (must be 1 here). */
748	RT_GCC_EXTENSION uint64_t u1Size : 1;
749	/** Available for software. */
750	RT_GCC_EXTENSION uint64_t u4Available : 4;
751	/** Reserved (must be 0). */
752	RT_GCC_EXTENSION uint64_t u9Reserved : 9;
753	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
754	RT_GCC_EXTENSION uint64_t u31PhysAddr : 31;
755	/** Available for software. */
756	RT_GCC_EXTENSION uint64_t u12Available : 12;
757	} EPTPDE2MBITS;
758	AssertCompileSize(EPTPDE2MBITS, 8);
759
760	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
761	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
762	/** Bits 20-12 - - EPT - PDE 2M MBZ Mask. */
763	#define EPT_PDE2M_MBZ_MASK UINT64_C(0x00000000001ff000)
764
765
766	/**
767	* EPT Page Directory Table Entry.
768	* In accordance with the VT-x spec.
769	*/
770	typedef union EPTPDE
771	{
772	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
773	/** Normal view. */
774	EPTPDEBITS n;
775	/** 2MB view (big). */
776	EPTPDE2MBITS b;
777	#endif
778	/** Unsigned integer view. */
779	X86PGPAEUINT u;
780	/** 64 bit unsigned integer view. */
781	uint64_t au64[1];
782	/** 32 bit unsigned integer view. */
783	uint32_t au32[2];
784	} EPTPDE;
785	AssertCompileSize(EPTPDE, 8);
786	/** Pointer to an EPT Page Directory Table Entry. */
787	typedef EPTPDE *PEPTPDE;
788	/** Pointer to a const EPT Page Directory Table Entry. */
789	typedef const EPTPDE *PCEPTPDE;
790
791	/**
792	* EPT Page Directory Table.
793	* In accordance with the VT-x spec.
794	*/
795	typedef struct EPTPD
796	{
797	EPTPDE a[EPT_PG_ENTRIES];
798	} EPTPD;
799	AssertCompileSize(EPTPD, 0x1000);
800	/** Pointer to an EPT Page Directory Table. */
801	typedef EPTPD *PEPTPD;
802	/** Pointer to a const EPT Page Directory Table. */
803	typedef const EPTPD *PCEPTPD;
804
805	/**
806	* EPT Page Table Entry. Bit view.
807	* In accordance with the VT-x spec.
808	*/
809	typedef struct EPTPTEBITS
810	{
811	/** 0 - Present bit.
812	* @remarks This is a convenience "misnomer". The bit actually indicates read access
813	* and the CPU will consider an entry with any of the first three bits set
814	* as present. Since all our valid entries will have this bit set, it can
815	* be used as a present indicator and allow some code sharing. */
816	RT_GCC_EXTENSION uint64_t u1Present : 1;
817	/** 1 - Writable bit. */
818	RT_GCC_EXTENSION uint64_t u1Write : 1;
819	/** 2 - Executable bit. */
820	RT_GCC_EXTENSION uint64_t u1Execute : 1;
821	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
822	RT_GCC_EXTENSION uint64_t u3EMT : 3;
823	/** 6 - Ignore PAT memory type */
824	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
825	/** 11:7 - Available for software. */
826	RT_GCC_EXTENSION uint64_t u5Available : 5;
827	/** 51:12 - Physical address of page. Restricted by maximum physical
828	* address width of the cpu. */
829	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
830	/** 63:52 - Available for software. */
831	RT_GCC_EXTENSION uint64_t u12Available : 12;
832	} EPTPTEBITS;
833	AssertCompileSize(EPTPTEBITS, 8);
834
835	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
836	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
837	/** The page shift to get the EPT PTE index. */
838	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
839	/** The EPT PT index mask (apply to a shifted page address). */
840	#define EPT_PT_MASK X86_PT_PAE_MASK
841	/** No bits - - EPT - PTE MBZ bits. */
842	#define EPT_PTE_MBZ_MASK UINT64_C(0x0000000000000000)
843	/** Mask of all possible EPT PTE attribute bits. */
844	#define EPT_PTE_ATTR_MASK ( EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_MASK \| EPT_E_IGNORE_PAT \
845	\| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
846
847
848	/**
849	* EPT Page Table Entry.
850	* In accordance with the VT-x spec.
851	*/
852	typedef union EPTPTE
853	{
854	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
855	/** Normal view. */
856	EPTPTEBITS n;
857	#endif
858	/** Unsigned integer view. */
859	X86PGPAEUINT u;
860	/** 64 bit unsigned integer view. */
861	uint64_t au64[1];
862	/** 32 bit unsigned integer view. */
863	uint32_t au32[2];
864	} EPTPTE;
865	AssertCompileSize(EPTPTE, 8);
866	/** Pointer to an EPT Page Directory Table Entry. */
867	typedef EPTPTE *PEPTPTE;
868	/** Pointer to a const EPT Page Directory Table Entry. */
869	typedef const EPTPTE *PCEPTPTE;
870
871	/**
872	* EPT Page Table.
873	* In accordance with the VT-x spec.
874	*/
875	typedef struct EPTPT
876	{
877	EPTPTE a[EPT_PG_ENTRIES];
878	} EPTPT;
879	AssertCompileSize(EPTPT, 0x1000);
880	/** Pointer to an extended page table. */
881	typedef EPTPT *PEPTPT;
882	/** Pointer to a const extended table. */
883	typedef const EPTPT *PCEPTPT;
884
885	/** EPTP page mask for the EPT PML4 table. */
886	#define EPT_EPTP_PG_MASK X86_CR3_AMD64_PAGE_MASK
887	/** @} */
888
889	/**
890	* VMX VPID flush types.
891	* Valid enum members are in accordance with the VT-x spec.
892	*/
893	typedef enum
894	{
895	/** Invalidate a specific page. */
896	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
897	/** Invalidate one context (specific VPID). */
898	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
899	/** Invalidate all contexts (all VPIDs). */
900	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
901	/** Invalidate a single VPID context retaining global mappings. */
902	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
903	/** Unsupported by VirtualBox. */
904	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
905	/** Unsupported by CPU. */
906	VMXTLBFLUSHVPID_NONE = 0xbad1
907	} VMXTLBFLUSHVPID;
908	AssertCompileSize(VMXTLBFLUSHVPID, 4);
909
910	/**
911	* VMX EPT flush types.
912	* @note Valid enums values are in accordance with the VT-x spec.
913	*/
914	typedef enum
915	{
916	/** Invalidate one context (specific EPT). */
917	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
918	/* Invalidate all contexts (all EPTs) */
919	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
920	/** Unsupported by VirtualBox. */
921	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
922	/** Unsupported by CPU. */
923	VMXTLBFLUSHEPT_NONE = 0xbad1
924	} VMXTLBFLUSHEPT;
925	AssertCompileSize(VMXTLBFLUSHEPT, 4);
926
927	/**
928	* VMX Posted Interrupt Descriptor.
929	* In accordance with the VT-x spec.
930	*/
931	typedef struct VMXPOSTEDINTRDESC
932	{
933	uint32_t aVectorBitmap[8];
934	uint32_t fOutstandingNotification : 1;
935	uint32_t uReserved0 : 31;
936	uint8_t au8Reserved0[28];
937	} VMXPOSTEDINTRDESC;
938	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
939	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
940	/** Pointer to a posted interrupt descriptor. */
941	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
942	/** Pointer to a const posted interrupt descriptor. */
943	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
944
945	/**
946	* VMX VMCS revision identifier.
947	* In accordance with the VT-x spec.
948	*/
949	typedef union
950	{
951	struct
952	{
953	/** Revision identifier. */
954	uint32_t u31RevisionId : 31;
955	/** Whether this is a shadow VMCS. */
956	uint32_t fIsShadowVmcs : 1;
957	} n;
958	/* The unsigned integer view. */
959	uint32_t u;
960	} VMXVMCSREVID;
961	AssertCompileSize(VMXVMCSREVID, 4);
962	/** Pointer to the VMXVMCSREVID union. */
963	typedef VMXVMCSREVID *PVMXVMCSREVID;
964	/** Pointer to a const VMXVMCSREVID union. */
965	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
966
967	/**
968	* VMX VM-exit instruction information.
969	* In accordance with the VT-x spec.
970	*/
971	typedef union
972	{
973	/** Plain unsigned int representation. */
974	uint32_t u;
975
976	/** INS and OUTS information. */
977	struct
978	{
979	uint32_t u7Reserved0 : 7;
980	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
981	uint32_t u3AddrSize : 3;
982	uint32_t u5Reserved1 : 5;
983	/** The segment register (X86_SREG_XXX). */
984	uint32_t iSegReg : 3;
985	uint32_t uReserved2 : 14;
986	} StrIo;
987
988	/** INVEPT, INVPCID, INVVPID information. */
989	struct
990	{
991	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
992	uint32_t u2Scaling : 2;
993	uint32_t u5Undef0 : 5;
994	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
995	uint32_t u3AddrSize : 3;
996	/** Cleared to 0. */
997	uint32_t u1Cleared0 : 1;
998	uint32_t u4Undef0 : 4;
999	/** The segment register (X86_SREG_XXX). */
1000	uint32_t iSegReg : 3;
1001	/** The index register (X86_GREG_XXX). */
1002	uint32_t iIdxReg : 4;
1003	/** Set if index register is invalid. */
1004	uint32_t fIdxRegInvalid : 1;
1005	/** The base register (X86_GREG_XXX). */
1006	uint32_t iBaseReg : 4;
1007	/** Set if base register is invalid. */
1008	uint32_t fBaseRegInvalid : 1;
1009	/** Register 2 (X86_GREG_XXX). */
1010	uint32_t iReg2 : 4;
1011	} Inv;
1012
1013	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
1014	struct
1015	{
1016	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1017	uint32_t u2Scaling : 2;
1018	uint32_t u5Reserved0 : 5;
1019	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1020	uint32_t u3AddrSize : 3;
1021	/** Cleared to 0. */
1022	uint32_t u1Cleared0 : 1;
1023	uint32_t u4Reserved0 : 4;
1024	/** The segment register (X86_SREG_XXX). */
1025	uint32_t iSegReg : 3;
1026	/** The index register (X86_GREG_XXX). */
1027	uint32_t iIdxReg : 4;
1028	/** Set if index register is invalid. */
1029	uint32_t fIdxRegInvalid : 1;
1030	/** The base register (X86_GREG_XXX). */
1031	uint32_t iBaseReg : 4;
1032	/** Set if base register is invalid. */
1033	uint32_t fBaseRegInvalid : 1;
1034	/** Register 2 (X86_GREG_XXX). */
1035	uint32_t iReg2 : 4;
1036	} VmxXsave;
1037
1038	/** LIDT, LGDT, SIDT, SGDT information. */
1039	struct
1040	{
1041	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1042	uint32_t u2Scaling : 2;
1043	uint32_t u5Undef0 : 5;
1044	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1045	uint32_t u3AddrSize : 3;
1046	/** Always cleared to 0. */
1047	uint32_t u1Cleared0 : 1;
1048	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
1049	uint32_t uOperandSize : 1;
1050	uint32_t u3Undef0 : 3;
1051	/** The segment register (X86_SREG_XXX). */
1052	uint32_t iSegReg : 3;
1053	/** The index register (X86_GREG_XXX). */
1054	uint32_t iIdxReg : 4;
1055	/** Set if index register is invalid. */
1056	uint32_t fIdxRegInvalid : 1;
1057	/** The base register (X86_GREG_XXX). */
1058	uint32_t iBaseReg : 4;
1059	/** Set if base register is invalid. */
1060	uint32_t fBaseRegInvalid : 1;
1061	/** Instruction identity (VMX_INSTR_ID_XXX). */
1062	uint32_t u2InstrId : 2;
1063	uint32_t u2Undef0 : 2;
1064	} GdtIdt;
1065
1066	/** LLDT, LTR, SLDT, STR information. */
1067	struct
1068	{
1069	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1070	uint32_t u2Scaling : 2;
1071	uint32_t u1Undef0 : 1;
1072	/** Register 1 (X86_GREG_XXX). */
1073	uint32_t iReg1 : 4;
1074	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1075	uint32_t u3AddrSize : 3;
1076	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1077	uint32_t fIsRegOperand : 1;
1078	uint32_t u4Undef0 : 4;
1079	/** The segment register (X86_SREG_XXX). */
1080	uint32_t iSegReg : 3;
1081	/** The index register (X86_GREG_XXX). */
1082	uint32_t iIdxReg : 4;
1083	/** Set if index register is invalid. */
1084	uint32_t fIdxRegInvalid : 1;
1085	/** The base register (X86_GREG_XXX). */
1086	uint32_t iBaseReg : 4;
1087	/** Set if base register is invalid. */
1088	uint32_t fBaseRegInvalid : 1;
1089	/** Instruction identity (VMX_INSTR_ID_XXX). */
1090	uint32_t u2InstrId : 2;
1091	uint32_t u2Undef0 : 2;
1092	} LdtTr;
1093
1094	/** RDRAND, RDSEED information. */
1095	struct
1096	{
1097	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1098	uint32_t u2Undef0 : 2;
1099	/** Destination register (X86_GREG_XXX). */
1100	uint32_t iReg1 : 4;
1101	uint32_t u4Undef0 : 4;
1102	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1103	uint32_t u2OperandSize : 2;
1104	uint32_t u19Def0 : 20;
1105	} RdrandRdseed;
1106
1107	/** VMREAD, VMWRITE information. */
1108	struct
1109	{
1110	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1111	uint32_t u2Scaling : 2;
1112	uint32_t u1Undef0 : 1;
1113	/** Register 1 (X86_GREG_XXX). */
1114	uint32_t iReg1 : 4;
1115	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1116	uint32_t u3AddrSize : 3;
1117	/** Memory or register operand. */
1118	uint32_t fIsRegOperand : 1;
1119	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1120	uint32_t u4Undef0 : 4;
1121	/** The segment register (X86_SREG_XXX). */
1122	uint32_t iSegReg : 3;
1123	/** The index register (X86_GREG_XXX). */
1124	uint32_t iIdxReg : 4;
1125	/** Set if index register is invalid. */
1126	uint32_t fIdxRegInvalid : 1;
1127	/** The base register (X86_GREG_XXX). */
1128	uint32_t iBaseReg : 4;
1129	/** Set if base register is invalid. */
1130	uint32_t fBaseRegInvalid : 1;
1131	/** Register 2 (X86_GREG_XXX). */
1132	uint32_t iReg2 : 4;
1133	} VmreadVmwrite;
1134
1135	struct
1136	{
1137	uint32_t u2Undef0 : 3;
1138	/** First XMM register operand. */
1139	uint32_t u4XmmReg1 : 4;
1140	uint32_t u23Undef1 : 21;
1141	/** Second XMM register operand. */
1142	uint32_t u4XmmReg2 : 4;
1143	} LoadIwkey;
1144
1145	/** This is a combination field of all instruction information. Note! Not all field
1146	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1147	* specialized fields are overwritten by their generic counterparts (e.g. no
1148	* instruction identity field). */
1149	struct
1150	{
1151	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1152	uint32_t u2Scaling : 2;
1153	uint32_t u1Undef0 : 1;
1154	/** Register 1 (X86_GREG_XXX). */
1155	uint32_t iReg1 : 4;
1156	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1157	uint32_t u3AddrSize : 3;
1158	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1159	uint32_t fIsRegOperand : 1;
1160	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1161	uint32_t uOperandSize : 2;
1162	uint32_t u2Undef0 : 2;
1163	/** The segment register (X86_SREG_XXX). */
1164	uint32_t iSegReg : 3;
1165	/** The index register (X86_GREG_XXX). */
1166	uint32_t iIdxReg : 4;
1167	/** Set if index register is invalid. */
1168	uint32_t fIdxRegInvalid : 1;
1169	/** The base register (X86_GREG_XXX). */
1170	uint32_t iBaseReg : 4;
1171	/** Set if base register is invalid. */
1172	uint32_t fBaseRegInvalid : 1;
1173	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1174	uint32_t iReg2 : 4;
1175	} All;
1176	} VMXEXITINSTRINFO;
1177	AssertCompileSize(VMXEXITINSTRINFO, 4);
1178	/** Pointer to a VMX VM-exit instruction info. struct. */
1179	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1180	/** Pointer to a const VMX VM-exit instruction info. struct. */
1181	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1182
1183
1184	/** @name VM-entry failure reported in Exit qualification.
1185	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1186	* @{
1187	*/
1188	/** No errors during VM-entry. */
1189	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1190	/** Not used. */
1191	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1192	/** Error while loading PDPTEs. */
1193	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1194	/** NMI injection when blocking-by-STI is set. */
1195	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1196	/** Invalid VMCS link pointer. */
1197	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1198	/** @} */
1199
1200
1201	/** @name VMXMSRPM_XXX - VMX MSR-bitmap permissions.
1202	* These are -not- specified by Intel but used internally by VirtualBox.
1203	* @{ */
1204	/** Guest software reads of this MSR must not cause a VM-exit. */
1205	#define VMXMSRPM_ALLOW_RD RT_BIT(0)
1206	/** Guest software reads of this MSR must cause a VM-exit. */
1207	#define VMXMSRPM_EXIT_RD RT_BIT(1)
1208	/** Guest software writes to this MSR must not cause a VM-exit. */
1209	#define VMXMSRPM_ALLOW_WR RT_BIT(2)
1210	/** Guest software writes to this MSR must cause a VM-exit. */
1211	#define VMXMSRPM_EXIT_WR RT_BIT(3)
1212	/** Guest software reads or writes of this MSR must not cause a VM-exit. */
1213	#define VMXMSRPM_ALLOW_RD_WR (VMXMSRPM_ALLOW_RD \| VMXMSRPM_ALLOW_WR)
1214	/** Guest software reads or writes of this MSR must cause a VM-exit. */
1215	#define VMXMSRPM_EXIT_RD_WR (VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR)
1216	/** Mask of valid MSR read permissions. */
1217	#define VMXMSRPM_RD_MASK (VMXMSRPM_ALLOW_RD \| VMXMSRPM_EXIT_RD)
1218	/** Mask of valid MSR write permissions. */
1219	#define VMXMSRPM_WR_MASK (VMXMSRPM_ALLOW_WR \| VMXMSRPM_EXIT_WR)
1220	/** Mask of valid MSR permissions. */
1221	#define VMXMSRPM_MASK (VMXMSRPM_RD_MASK \| VMXMSRPM_WR_MASK)
1222	/** */
1223	/** Gets whether the MSR permission is valid or not. */
1224	#define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \
1225	&& ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \
1226	&& ((a_Msrpm) & VMXMSRPM_RD_MASK) != VMXMSRPM_RD_MASK \
1227	&& ((a_Msrpm) & VMXMSRPM_WR_MASK) != VMXMSRPM_WR_MASK)
1228	/** @} */
1229
1230	/**
1231	* VMX MSR autoload/store slot.
1232	* In accordance with the VT-x spec.
1233	*/
1234	typedef struct VMXAUTOMSR
1235	{
1236	/** The MSR Id. */
1237	uint32_t u32Msr;
1238	/** Reserved (MBZ). */
1239	uint32_t u32Reserved;
1240	/** The MSR value. */
1241	uint64_t u64Value;
1242	} VMXAUTOMSR;
1243	AssertCompileSize(VMXAUTOMSR, 16);
1244	/** Pointer to an MSR load/store element. */
1245	typedef VMXAUTOMSR *PVMXAUTOMSR;
1246	/** Pointer to a const MSR load/store element. */
1247	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1248
1249	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1250	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1251
1252	/**
1253	* VMX tagged-TLB flush types.
1254	*/
1255	typedef enum
1256	{
1257	VMXTLBFLUSHTYPE_EPT,
1258	VMXTLBFLUSHTYPE_VPID,
1259	VMXTLBFLUSHTYPE_EPT_VPID,
1260	VMXTLBFLUSHTYPE_NONE
1261	} VMXTLBFLUSHTYPE;
1262	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1263	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1264	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1265	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1266
1267	/**
1268	* VMX controls MSR.
1269	* In accordance with the VT-x spec.
1270	*/
1271	typedef union
1272	{
1273	struct
1274	{
1275	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1276	uint32_t allowed0;
1277	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1278	* controls. */
1279	uint32_t allowed1;
1280	} n;
1281	uint64_t u;
1282	} VMXCTLSMSR;
1283	AssertCompileSize(VMXCTLSMSR, 8);
1284	/** Pointer to a VMXCTLSMSR union. */
1285	typedef VMXCTLSMSR *PVMXCTLSMSR;
1286	/** Pointer to a const VMXCTLSMSR union. */
1287	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1288
1289	/**
1290	* VMX MSRs.
1291	*/
1292	typedef struct VMXMSRS
1293	{
1294	/** Basic information. */
1295	uint64_t u64Basic;
1296	/** Pin-based VM-execution controls. */
1297	VMXCTLSMSR PinCtls;
1298	/** Processor-based VM-execution controls. */
1299	VMXCTLSMSR ProcCtls;
1300	/** Secondary processor-based VM-execution controls. */
1301	VMXCTLSMSR ProcCtls2;
1302	/** VM-exit controls. */
1303	VMXCTLSMSR ExitCtls;
1304	/** VM-entry controls. */
1305	VMXCTLSMSR EntryCtls;
1306	/** True pin-based VM-execution controls. */
1307	VMXCTLSMSR TruePinCtls;
1308	/** True processor-based VM-execution controls. */
1309	VMXCTLSMSR TrueProcCtls;
1310	/** True VM-entry controls. */
1311	VMXCTLSMSR TrueEntryCtls;
1312	/** True VM-exit controls. */
1313	VMXCTLSMSR TrueExitCtls;
1314	/** Miscellaneous data. */
1315	uint64_t u64Misc;
1316	/** CR0 fixed-0 - bits set here must be set in VMX operation. */
1317	uint64_t u64Cr0Fixed0;
1318	/** CR0 fixed-1 - bits clear here must be clear in VMX operation. */
1319	uint64_t u64Cr0Fixed1;
1320	/** CR4 fixed-0 - bits set here must be set in VMX operation. */
1321	uint64_t u64Cr4Fixed0;
1322	/** CR4 fixed-1 - bits clear here must be clear in VMX operation. */
1323	uint64_t u64Cr4Fixed1;
1324	/** VMCS enumeration. */
1325	uint64_t u64VmcsEnum;
1326	/** VM Functions. */
1327	uint64_t u64VmFunc;
1328	/** EPT, VPID capabilities. */
1329	uint64_t u64EptVpidCaps;
1330	/** Tertiary processor-based VM-execution controls. */
1331	uint64_t u64ProcCtls3;
1332	/** Reserved for future. */
1333	uint64_t a_u64Reserved[9];
1334	} VMXMSRS;
1335	AssertCompileSizeAlignment(VMXMSRS, 8);
1336	AssertCompileSize(VMXMSRS, 224);
1337	/** Pointer to a VMXMSRS struct. */
1338	typedef VMXMSRS *PVMXMSRS;
1339	/** Pointer to a const VMXMSRS struct. */
1340	typedef const VMXMSRS *PCVMXMSRS;
1341
1342
1343	/**
1344	* LBR MSRs.
1345	*/
1346	typedef struct LBRMSRS
1347	{
1348	/** List of LastBranch-From-IP MSRs. */
1349	uint64_t au64BranchFromIpMsr[32];
1350	/** List of LastBranch-To-IP MSRs. */
1351	uint64_t au64BranchToIpMsr[32];
1352	/** The MSR containing the index to the most recent branch record. */
1353	uint64_t uBranchTosMsr;
1354	} LBRMSRS;
1355	AssertCompileSizeAlignment(LBRMSRS, 8);
1356	/** Pointer to a VMXMSRS struct. */
1357	typedef LBRMSRS *PLBRMSRS;
1358	/** Pointer to a const VMXMSRS struct. */
1359	typedef const LBRMSRS *PCLBRMSRS;
1360
1361
1362	/** @name VMX Basic Exit Reasons.
1363	* In accordance with the VT-x spec.
1364	* Update g_aVMExitHandlers if new VM-exit reasons are added.
1365	* @{
1366	*/
1367	/** Invalid exit code */
1368	#define VMX_EXIT_INVALID (-1)
1369	/** Exception or non-maskable interrupt (NMI). */
1370	#define VMX_EXIT_XCPT_OR_NMI 0
1371	/** External interrupt. */
1372	#define VMX_EXIT_EXT_INT 1
1373	/** Triple fault. */
1374	#define VMX_EXIT_TRIPLE_FAULT 2
1375	/** INIT signal. */
1376	#define VMX_EXIT_INIT_SIGNAL 3
1377	/** Start-up IPI (SIPI). */
1378	#define VMX_EXIT_SIPI 4
1379	/** I/O system-management interrupt (SMI). */
1380	#define VMX_EXIT_IO_SMI 5
1381	/** Other SMI. */
1382	#define VMX_EXIT_SMI 6
1383	/** Interrupt window exiting. */
1384	#define VMX_EXIT_INT_WINDOW 7
1385	/** NMI window exiting. */
1386	#define VMX_EXIT_NMI_WINDOW 8
1387	/** Task switch. */
1388	#define VMX_EXIT_TASK_SWITCH 9
1389	/** CPUID. */
1390	#define VMX_EXIT_CPUID 10
1391	/** GETSEC. */
1392	#define VMX_EXIT_GETSEC 11
1393	/** HLT. */
1394	#define VMX_EXIT_HLT 12
1395	/** INVD. */
1396	#define VMX_EXIT_INVD 13
1397	/** INVLPG. */
1398	#define VMX_EXIT_INVLPG 14
1399	/** RDPMC. */
1400	#define VMX_EXIT_RDPMC 15
1401	/** RDTSC. */
1402	#define VMX_EXIT_RDTSC 16
1403	/** RSM in SMM. */
1404	#define VMX_EXIT_RSM 17
1405	/** VMCALL. */
1406	#define VMX_EXIT_VMCALL 18
1407	/** VMCLEAR. */
1408	#define VMX_EXIT_VMCLEAR 19
1409	/** VMLAUNCH. */
1410	#define VMX_EXIT_VMLAUNCH 20
1411	/** VMPTRLD. */
1412	#define VMX_EXIT_VMPTRLD 21
1413	/** VMPTRST. */
1414	#define VMX_EXIT_VMPTRST 22
1415	/** VMREAD. */
1416	#define VMX_EXIT_VMREAD 23
1417	/** VMRESUME. */
1418	#define VMX_EXIT_VMRESUME 24
1419	/** VMWRITE. */
1420	#define VMX_EXIT_VMWRITE 25
1421	/** VMXOFF. */
1422	#define VMX_EXIT_VMXOFF 26
1423	/** VMXON. */
1424	#define VMX_EXIT_VMXON 27
1425	/** Control-register accesses. */
1426	#define VMX_EXIT_MOV_CRX 28
1427	/** Debug-register accesses. */
1428	#define VMX_EXIT_MOV_DRX 29
1429	/** I/O instruction. */
1430	#define VMX_EXIT_IO_INSTR 30
1431	/** RDMSR. */
1432	#define VMX_EXIT_RDMSR 31
1433	/** WRMSR. */
1434	#define VMX_EXIT_WRMSR 32
1435	/** VM-entry failure due to invalid guest state. */
1436	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1437	/** VM-entry failure due to MSR loading. */
1438	#define VMX_EXIT_ERR_MSR_LOAD 34
1439	/** MWAIT. */
1440	#define VMX_EXIT_MWAIT 36
1441	/** VM-exit due to monitor trap flag. */
1442	#define VMX_EXIT_MTF 37
1443	/** MONITOR. */
1444	#define VMX_EXIT_MONITOR 39
1445	/** PAUSE. */
1446	#define VMX_EXIT_PAUSE 40
1447	/** VM-entry failure due to machine-check. */
1448	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1449	/** TPR below threshold. Guest software executed MOV to CR8. */
1450	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1451	/** VM-exit due to guest accessing physical address in the APIC-access page. */
1452	#define VMX_EXIT_APIC_ACCESS 44
1453	/** VM-exit due to EOI virtualization. */
1454	#define VMX_EXIT_VIRTUALIZED_EOI 45
1455	/** Access to GDTR/IDTR using LGDT, LIDT, SGDT or SIDT. */
1456	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1457	/** Access to LDTR/TR due to LLDT, LTR, SLDT, or STR. */
1458	#define VMX_EXIT_LDTR_TR_ACCESS 47
1459	/** EPT violation. */
1460	#define VMX_EXIT_EPT_VIOLATION 48
1461	/** EPT misconfiguration. */
1462	#define VMX_EXIT_EPT_MISCONFIG 49
1463	/** INVEPT. */
1464	#define VMX_EXIT_INVEPT 50
1465	/** RDTSCP. */
1466	#define VMX_EXIT_RDTSCP 51
1467	/** VMX-preemption timer expired. */
1468	#define VMX_EXIT_PREEMPT_TIMER 52
1469	/** INVVPID. */
1470	#define VMX_EXIT_INVVPID 53
1471	/** WBINVD. */
1472	#define VMX_EXIT_WBINVD 54
1473	/** XSETBV. */
1474	#define VMX_EXIT_XSETBV 55
1475	/** Guest completed write to virtual-APIC. */
1476	#define VMX_EXIT_APIC_WRITE 56
1477	/** RDRAND. */
1478	#define VMX_EXIT_RDRAND 57
1479	/** INVPCID. */
1480	#define VMX_EXIT_INVPCID 58
1481	/** VMFUNC. */
1482	#define VMX_EXIT_VMFUNC 59
1483	/** ENCLS. */
1484	#define VMX_EXIT_ENCLS 60
1485	/** RDSEED. */
1486	#define VMX_EXIT_RDSEED 61
1487	/** Page-modification log full. */
1488	#define VMX_EXIT_PML_FULL 62
1489	/** XSAVES. */
1490	#define VMX_EXIT_XSAVES 63
1491	/** XRSTORS. */
1492	#define VMX_EXIT_XRSTORS 64
1493	/** SPP-related event (SPP miss or misconfiguration). */
1494	#define VMX_EXIT_SPP_EVENT 66
1495	/* UMWAIT. */
1496	#define VMX_EXIT_UMWAIT 67
1497	/** TPAUSE. */
1498	#define VMX_EXIT_TPAUSE 68
1499	/** LOADIWKEY. */
1500	#define VMX_EXIT_LOADIWKEY 69
1501	/** The maximum VM-exit value (inclusive). */
1502	#define VMX_EXIT_MAX (VMX_EXIT_LOADIWKEY)
1503	/** @} */
1504
1505
1506	/** @name VM Instruction Errors.
1507	* In accordance with the VT-x spec.
1508	* See Intel spec. "30.4 VM Instruction Error Numbers"
1509	* @{
1510	*/
1511	typedef enum
1512	{
1513	/** VMCALL executed in VMX root operation. */
1514	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1515	/** VMCLEAR with invalid physical address. */
1516	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1517	/** VMCLEAR with VMXON pointer. */
1518	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1519	/** VMLAUNCH with non-clear VMCS. */
1520	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1521	/** VMRESUME with non-launched VMCS. */
1522	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1523	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1524	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1525	/** VM-entry with invalid control field(s). */
1526	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1527	/** VM-entry with invalid host-state field(s). */
1528	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1529	/** VMPTRLD with invalid physical address. */
1530	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1531	/** VMPTRLD with VMXON pointer. */
1532	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1533	/** VMPTRLD with incorrect VMCS revision identifier. */
1534	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1535	/** VMREAD from unsupported VMCS component. */
1536	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1537	/** VMWRITE to unsupported VMCS component. */
1538	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1539	/** VMWRITE to read-only VMCS component. */
1540	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1541	/** VMXON executed in VMX root operation. */
1542	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1543	/** VM-entry with invalid executive-VMCS pointer. */
1544	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1545	/** VM-entry with non-launched executive VMCS. */
1546	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1547	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1548	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1549	/** VMCALL with non-clear VMCS. */
1550	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1551	/** VMCALL with invalid VM-exit control fields. */
1552	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1553	/** VMCALL with incorrect MSEG revision identifier. */
1554	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1555	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1556	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1557	/** VMCALL with invalid SMM-monitor features. */
1558	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1559	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1560	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1561	/** VM-entry with events blocked by MOV SS. */
1562	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1563	/** Invalid operand to INVEPT/INVVPID. */
1564	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1565	} VMXINSTRERR;
1566	/** @} */
1567
1568
1569	/** @name VMX abort reasons.
1570	* In accordance with the VT-x spec.
1571	* See Intel spec. "27.7 VMX Aborts".
1572	* Update HMGetVmxAbortDesc() if new reasons are added.
1573	* @{
1574	*/
1575	typedef enum
1576	{
1577	/** None - don't use this / uninitialized value. */
1578	VMXABORT_NONE = 0,
1579	/** VMX abort caused during saving of guest MSRs. */
1580	VMXABORT_SAVE_GUEST_MSRS = 1,
1581	/** VMX abort caused during host PDPTE checks. */
1582	VMXBOART_HOST_PDPTE = 2,
1583	/** VMX abort caused due to current VMCS being corrupted. */
1584	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1585	/** VMX abort caused during loading of host MSRs. */
1586	VMXABORT_LOAD_HOST_MSR = 4,
1587	/** VMX abort caused due to a machine-check exception during VM-exit. */
1588	VMXABORT_MACHINE_CHECK_XCPT = 5,
1589	/** VMX abort caused due to invalid return from long mode. */
1590	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1591	/* Type size hack. */
1592	VMXABORT_32BIT_HACK = 0x7fffffff
1593	} VMXABORT;
1594	AssertCompileSize(VMXABORT, 4);
1595	/** @} */
1596
1597
1598	/** @name VMX MSR - Basic VMX information.
1599	* @{
1600	*/
1601	/** VMCS (and related regions) memory type - Uncacheable. */
1602	#define VMX_BASIC_MEM_TYPE_UC 0
1603	/** VMCS (and related regions) memory type - Write back. */
1604	#define VMX_BASIC_MEM_TYPE_WB 6
1605	/** Width of physical addresses used for VMCS and associated memory regions
1606	* (1=32-bit, 0=processor's physical address width). */
1607	#define VMX_BASIC_PHYSADDR_WIDTH_32BIT RT_BIT_64(48)
1608
1609	/** Bit fields for MSR_IA32_VMX_BASIC. */
1610	/** VMCS revision identifier used by the processor. */
1611	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1612	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1613	/** Bit 31 is reserved and RAZ. */
1614	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1615	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1616	/** VMCS size in bytes. */
1617	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1618	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1619	/** Bits 45:47 are reserved. */
1620	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1621	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1622	/** Width of physical addresses used for the VMCS and associated memory regions
1623	* (always 0 on CPUs that support Intel 64 architecture). */
1624	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1625	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1626	/** Dual-monitor treatment of SMI and SMM supported. */
1627	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1628	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1629	/** Memory type that must be used for the VMCS and associated memory regions. */
1630	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1631	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1632	/** VM-exit instruction information for INS/OUTS. */
1633	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1634	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1635	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1636	* bits in VMX control MSRs. */
1637	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1638	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1639	/** Whether VM-entry can delivery error code for all hardware exception vectors. */
1640	#define VMX_BF_BASIC_XCPT_ERRCODE_SHIFT 56
1641	#define VMX_BF_BASIC_XCPT_ERRCODE_MASK UINT64_C(0x0100000000000000)
1642	/** Bits 57:63 are reserved and RAZ. */
1643	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 57
1644	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xfe00000000000000)
1645	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1646	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1647	VMCS_INS_OUTS, TRUE_CTLS, XCPT_ERRCODE, RSVD_56_63));
1648	/** @} */
1649
1650
1651	/** @name VMX MSR - Miscellaneous data.
1652	* @{
1653	*/
1654	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1655	#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1656	/** Whether Intel PT is supported in VMX operation. */
1657	#define VMX_MISC_INTEL_PT RT_BIT(14)
1658	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1659	* VMWRITE cannot modify read-only VM-exit information fields. */
1660	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1661	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1662	* instructions. */
1663	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1664	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1665	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1666	/** Maximum CR3-target count supported by the CPU. */
1667	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1668
1669	/** Bit fields for MSR_IA32_VMX_MISC. */
1670	/** Relationship between the preemption timer and tsc. */
1671	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1672	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1673	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1674	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1675	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1676	/** Activity states supported by the implementation. */
1677	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1678	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1679	/** Bits 9:13 is reserved and RAZ. */
1680	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1681	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1682	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1683	#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1684	#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1685	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1686	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1687	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1688	/** Number of CR3 target values supported by the processor. (0-256) */
1689	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1690	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1691	/** Maximum number of MSRs in the VMCS. */
1692	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1693	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1694	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1695	* SMIs. */
1696	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1697	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1698	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1699	* VMWRITE cannot modify read-only VM-exit information fields. */
1700	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1701	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1702	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1703	* instructions. */
1704	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1705	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1706	/** Bit 31 is reserved and RAZ. */
1707	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1708	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1709	/** 32-bit MSEG revision ID used by the processor. */
1710	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1711	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1712	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1713	(PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1714	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1715	/** @} */
1716
1717	/** @name VMX MSR - VMCS enumeration.
1718	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1719	* @{
1720	*/
1721	/** Bit 0 is reserved and RAZ. */
1722	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1723	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1724	/** Highest index value used in VMCS field encoding. */
1725	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1726	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1727	/** Bit 10:63 is reserved and RAZ. */
1728	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1729	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1730	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1731	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1732	/** @} */
1733
1734
1735	/** @name VMX MSR - VM Functions.
1736	* Bit fields for MSR_IA32_VMX_VMFUNC.
1737	* @{
1738	*/
1739	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1740	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1741	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1742	/** Bits 1:63 are reserved and RAZ. */
1743	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1744	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1745	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1746	(EPTP_SWITCHING, RSVD_1_63));
1747	/** @} */
1748
1749
1750	/** @name VMX MSR - EPT/VPID capabilities.
1751	* @{
1752	*/
1753	/** Supports execute-only translations by EPT. */
1754	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1755	/** Supports page-walk length of 4. */
1756	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1757	/** Supports page-walk length of 5. */
1758	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5 RT_BIT_64(7)
1759	/** Supports EPT paging-structure memory type to be uncacheable. */
1760	#define MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC RT_BIT_64(8)
1761	/** Supports EPT paging structure memory type to be write-back. */
1762	#define MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB RT_BIT_64(14)
1763	/** Supports EPT PDE to map a 2 MB page. */
1764	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1765	/** Supports EPT PDPTE to map a 1 GB page. */
1766	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1767	/** Supports INVEPT instruction. */
1768	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1769	/** Supports accessed and dirty flags for EPT. */
1770	#define MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY RT_BIT_64(21)
1771	/** Supports advanced VM-exit info. for EPT violations. */
1772	#define MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION RT_BIT_64(22)
1773	/** Supports supervisor shadow-stack control. */
1774	#define MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK RT_BIT_64(23)
1775	/** Supports single-context INVEPT type. */
1776	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1777	/** Supports all-context INVEPT type. */
1778	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1779	/** Supports INVVPID instruction. */
1780	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1781	/** Supports individual-address INVVPID type. */
1782	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1783	/** Supports single-context INVVPID type. */
1784	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1785	/** Supports all-context INVVPID type. */
1786	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1787	/** Supports singe-context-retaining-globals INVVPID type. */
1788	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1789
1790	/** Bit fields for MSR_IA32_VMX_EPT_VPID_CAP. */
1791	#define VMX_BF_EPT_VPID_CAP_EXEC_ONLY_SHIFT 0
1792	#define VMX_BF_EPT_VPID_CAP_EXEC_ONLY_MASK UINT64_C(0x0000000000000001)
1793	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_SHIFT 1
1794	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_MASK UINT64_C(0x000000000000003e)
1795	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_SHIFT 6
1796	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_MASK UINT64_C(0x0000000000000040)
1797	#define VMX_BF_EPT_VPID_CAP_RSVD_7_SHIFT 7
1798	#define VMX_BF_EPT_VPID_CAP_RSVD_7_MASK UINT64_C(0x0000000000000080)
1799	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_UC_SHIFT 8
1800	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_UC_MASK UINT64_C(0x0000000000000100)
1801	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_SHIFT 9
1802	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1803	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_WB_SHIFT 14
1804	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_WB_MASK UINT64_C(0x0000000000004000)
1805	#define VMX_BF_EPT_VPID_CAP_RSVD_15_SHIFT 15
1806	#define VMX_BF_EPT_VPID_CAP_RSVD_15_MASK UINT64_C(0x0000000000008000)
1807	#define VMX_BF_EPT_VPID_CAP_PDE_2M_SHIFT 16
1808	#define VMX_BF_EPT_VPID_CAP_PDE_2M_MASK UINT64_C(0x0000000000010000)
1809	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_SHIFT 17
1810	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_MASK UINT64_C(0x0000000000020000)
1811	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_SHIFT 18
1812	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_MASK UINT64_C(0x00000000000c0000)
1813	#define VMX_BF_EPT_VPID_CAP_INVEPT_SHIFT 20
1814	#define VMX_BF_EPT_VPID_CAP_INVEPT_MASK UINT64_C(0x0000000000100000)
1815	#define VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY_SHIFT 21
1816	#define VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY_MASK UINT64_C(0x0000000000200000)
1817	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION_SHIFT 22
1818	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION_MASK UINT64_C(0x0000000000400000)
1819	#define VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK_SHIFT 23
1820	#define VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK_MASK UINT64_C(0x0000000000800000)
1821	#define VMX_BF_EPT_VPID_CAP_RSVD_24_SHIFT 24
1822	#define VMX_BF_EPT_VPID_CAP_RSVD_24_MASK UINT64_C(0x0000000001000000)
1823	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_SHIFT 25
1824	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_MASK UINT64_C(0x0000000002000000)
1825	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_SHIFT 26
1826	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_MASK UINT64_C(0x0000000004000000)
1827	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_SHIFT 27
1828	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_MASK UINT64_C(0x00000000f8000000)
1829	#define VMX_BF_EPT_VPID_CAP_INVVPID_SHIFT 32
1830	#define VMX_BF_EPT_VPID_CAP_INVVPID_MASK UINT64_C(0x0000000100000000)
1831	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_SHIFT 33
1832	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_MASK UINT64_C(0x000000fe00000000)
1833	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_SHIFT 40
1834	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_MASK UINT64_C(0x0000010000000000)
1835	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_SHIFT 41
1836	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_MASK UINT64_C(0x0000020000000000)
1837	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_SHIFT 42
1838	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_MASK UINT64_C(0x0000040000000000)
1839	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_SHIFT 43
1840	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_MASK UINT64_C(0x0000080000000000)
1841	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_SHIFT 44
1842	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_MASK UINT64_C(0xfffff00000000000)
1843	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_VPID_CAP_, UINT64_C(0), UINT64_MAX,
1844	(EXEC_ONLY, RSVD_1_5, PAGE_WALK_LENGTH_4, RSVD_7, MEMTYPE_UC, RSVD_9_13, MEMTYPE_WB, RSVD_15, PDE_2M,
1845	PDPTE_1G, RSVD_18_19, INVEPT, ACCESS_DIRTY, ADVEXITINFO_EPT_VIOLATION, SUPER_SHW_STACK, RSVD_24,
1846	INVEPT_SINGLE_CTX, INVEPT_ALL_CTX, RSVD_27_31, INVVPID, RSVD_33_39, INVVPID_INDIV_ADDR,
1847	INVVPID_SINGLE_CTX, INVVPID_ALL_CTX, INVVPID_SINGLE_CTX_RETAIN_GLOBALS, RSVD_44_63));
1848	/** @} */
1849
1850
1851	/** @name Extended Page Table Pointer (EPTP)
1852	* In accordance with the VT-x spec.
1853	* See Intel spec. 23.6.11 "Extended-Page-Table Pointer (EPTP)".
1854	* @{
1855	*/
1856	/** EPTP memory type: Uncachable. */
1857	#define VMX_EPTP_MEMTYPE_UC 0
1858	/** EPTP memory type: Write Back. */
1859	#define VMX_EPTP_MEMTYPE_WB 6
1860	/** Page-walk length for PML4 (4-level paging). */
1861	#define VMX_EPTP_PAGE_WALK_LENGTH_4 3
1862
1863	/** Bit fields for EPTP. */
1864	#define VMX_BF_EPTP_MEMTYPE_SHIFT 0
1865	#define VMX_BF_EPTP_MEMTYPE_MASK UINT64_C(0x0000000000000007)
1866	#define VMX_BF_EPTP_PAGE_WALK_LENGTH_SHIFT 3
1867	#define VMX_BF_EPTP_PAGE_WALK_LENGTH_MASK UINT64_C(0x0000000000000038)
1868	#define VMX_BF_EPTP_ACCESS_DIRTY_SHIFT 6
1869	#define VMX_BF_EPTP_ACCESS_DIRTY_MASK UINT64_C(0x0000000000000040)
1870	#define VMX_BF_EPTP_SUPER_SHW_STACK_SHIFT 7
1871	#define VMX_BF_EPTP_SUPER_SHW_STACK_MASK UINT64_C(0x0000000000000080)
1872	#define VMX_BF_EPTP_RSVD_8_11_SHIFT 8
1873	#define VMX_BF_EPTP_RSVD_8_11_MASK UINT64_C(0x0000000000000f00)
1874	#define VMX_BF_EPTP_PML4_TABLE_ADDR_SHIFT 12
1875	#define VMX_BF_EPTP_PML4_TABLE_ADDR_MASK UINT64_C(0xfffffffffffff000)
1876	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPTP_, UINT64_C(0), UINT64_MAX,
1877	(MEMTYPE, PAGE_WALK_LENGTH, ACCESS_DIRTY, SUPER_SHW_STACK, RSVD_8_11, PML4_TABLE_ADDR));
1878
1879	/* Mask of valid EPTP bits sans physically non-addressable bits. */
1880	#define VMX_EPTP_VALID_MASK ( VMX_BF_EPTP_MEMTYPE_MASK \
1881	\| VMX_BF_EPTP_PAGE_WALK_LENGTH_MASK \
1882	\| VMX_BF_EPTP_ACCESS_DIRTY_MASK \
1883	\| VMX_BF_EPTP_SUPER_SHW_STACK_MASK \
1884	\| VMX_BF_EPTP_PML4_TABLE_ADDR_MASK)
1885	/** @} */
1886
1887
1888	/** @name VMCS fields and encoding.
1889	*
1890	* When adding a new field:
1891	* - Always add it to g_aVmcsFields.
1892	* - Consider if it needs to be added to VMXVVMCS.
1893	* @{
1894	*/
1895	/** 16-bit control fields. */
1896	#define VMX_VMCS16_VPID 0x0000
1897	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1898	#define VMX_VMCS16_EPTP_INDEX 0x0004
1899
1900	/** 16-bit guest-state fields. */
1901	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1902	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1903	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1904	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1905	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1906	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1907	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1908	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1909	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1910	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1911
1912	/** 16-bits host-state fields. */
1913	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1914	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1915	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1916	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1917	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1918	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1919	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1920
1921	/** 64-bit control fields. */
1922	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1923	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1924	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1925	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1926	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1927	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1928	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1929	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1930	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1931	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1932	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1933	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1934	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1935	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1936	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1937	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1938	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1939	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1940	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1941	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1942	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1943	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1944	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1945	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1946	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1947	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1948	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1949	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1950	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1951	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1952	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1953	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1954	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1955	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1956	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1957	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1958	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1959	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1960	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1961	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1962	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1963	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1964	#define VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_FULL 0x202a
1965	#define VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_HIGH 0x202b
1966	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1967	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1968	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1969	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1970	#define VMX_VMCS64_CTRL_SPPTP_FULL 0x2030
1971	#define VMX_VMCS64_CTRL_SPPTP_HIGH 0x2031
1972	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1973	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1974	#define VMX_VMCS64_CTRL_PROC_EXEC3_FULL 0x2034
1975	#define VMX_VMCS64_CTRL_PROC_EXEC3_HIGH 0x2035
1976	#define VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_FULL 0x2036
1977	#define VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_HIGH 0x2037
1978
1979	/** 64-bit read-only data fields. */
1980	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1981	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1982
1983	/** 64-bit guest-state fields. */
1984	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1985	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1986	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1987	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1988	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1989	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1990	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1991	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1992	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1993	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1994	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1995	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1996	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1997	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1998	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1999	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
2000	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
2001	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
2002	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
2003	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
2004	#define VMX_VMCS64_GUEST_RTIT_CTL_FULL 0x2814
2005	#define VMX_VMCS64_GUEST_RTIT_CTL_HIGH 0x2815
2006	#define VMX_VMCS64_GUEST_PKRS_FULL 0x2818
2007	#define VMX_VMCS64_GUEST_PKRS_HIGH 0x2819
2008
2009	/** 64-bit host-state fields. */
2010	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
2011	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
2012	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
2013	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
2014	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
2015	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
2016	#define VMX_VMCS64_HOST_PKRS_FULL 0x2c06
2017	#define VMX_VMCS64_HOST_PKRS_HIGH 0x2c07
2018
2019	/** 32-bit control fields. */
2020	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
2021	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
2022	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
2023	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
2024	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
2025	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
2026	#define VMX_VMCS32_CTRL_EXIT 0x400c
2027	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
2028	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
2029	#define VMX_VMCS32_CTRL_ENTRY 0x4012
2030	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
2031	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
2032	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
2033	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
2034	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
2035	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
2036	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
2037	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
2038
2039	/** 32-bits read-only fields. */
2040	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
2041	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
2042	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
2043	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
2044	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
2045	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
2046	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
2047	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
2048
2049	/** 32-bit guest-state fields. */
2050	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
2051	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
2052	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
2053	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
2054	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
2055	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
2056	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
2057	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
2058	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
2059	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
2060	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
2061	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
2062	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
2063	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
2064	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
2065	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
2066	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
2067	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
2068	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
2069	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
2070	#define VMX_VMCS32_GUEST_SMBASE 0x4828
2071	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
2072	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
2073
2074	/** 32-bit host-state fields. */
2075	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
2076
2077	/** Natural-width control fields. */
2078	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
2079	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
2080	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
2081	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
2082	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
2083	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
2084	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
2085	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
2086
2087	/** Natural-width read-only data fields. */
2088	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
2089	#define VMX_VMCS_RO_IO_RCX 0x6402
2090	#define VMX_VMCS_RO_IO_RSI 0x6404
2091	#define VMX_VMCS_RO_IO_RDI 0x6406
2092	#define VMX_VMCS_RO_IO_RIP 0x6408
2093	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
2094
2095	/** Natural-width guest-state fields. */
2096	#define VMX_VMCS_GUEST_CR0 0x6800
2097	#define VMX_VMCS_GUEST_CR3 0x6802
2098	#define VMX_VMCS_GUEST_CR4 0x6804
2099	#define VMX_VMCS_GUEST_ES_BASE 0x6806
2100	#define VMX_VMCS_GUEST_CS_BASE 0x6808
2101	#define VMX_VMCS_GUEST_SS_BASE 0x680a
2102	#define VMX_VMCS_GUEST_DS_BASE 0x680c
2103	#define VMX_VMCS_GUEST_FS_BASE 0x680e
2104	#define VMX_VMCS_GUEST_GS_BASE 0x6810
2105	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
2106	#define VMX_VMCS_GUEST_TR_BASE 0x6814
2107	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
2108	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
2109	#define VMX_VMCS_GUEST_DR7 0x681a
2110	#define VMX_VMCS_GUEST_RSP 0x681c
2111	#define VMX_VMCS_GUEST_RIP 0x681e
2112	#define VMX_VMCS_GUEST_RFLAGS 0x6820
2113	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
2114	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
2115	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
2116	#define VMX_VMCS_GUEST_S_CET 0x6828
2117	#define VMX_VMCS_GUEST_SSP 0x682a
2118	#define VMX_VMCS_GUEST_INTR_SSP_TABLE_ADDR 0x682c
2119
2120	/** Natural-width host-state fields. */
2121	#define VMX_VMCS_HOST_CR0 0x6c00
2122	#define VMX_VMCS_HOST_CR3 0x6c02
2123	#define VMX_VMCS_HOST_CR4 0x6c04
2124	#define VMX_VMCS_HOST_FS_BASE 0x6c06
2125	#define VMX_VMCS_HOST_GS_BASE 0x6c08
2126	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
2127	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
2128	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
2129	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
2130	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
2131	#define VMX_VMCS_HOST_RSP 0x6c14
2132	#define VMX_VMCS_HOST_RIP 0x6c16
2133	#define VMX_VMCS_HOST_S_CET 0x6c18
2134	#define VMX_VMCS_HOST_SSP 0x6c1a
2135	#define VMX_VMCS_HOST_INTR_SSP_TABLE_ADDR 0x6c1c
2136
2137	#define VMX_VMCS16_GUEST_SEG_SEL(a_iSegReg) (VMX_VMCS16_GUEST_ES_SEL + (a_iSegReg) * 2)
2138	#define VMX_VMCS_GUEST_SEG_BASE(a_iSegReg) (VMX_VMCS_GUEST_ES_BASE + (a_iSegReg) * 2)
2139	#define VMX_VMCS32_GUEST_SEG_LIMIT(a_iSegReg) (VMX_VMCS32_GUEST_ES_LIMIT + (a_iSegReg) * 2)
2140	#define VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(a_iSegReg) (VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS + (a_iSegReg) * 2)
2141
2142	/**
2143	* VMCS field.
2144	* In accordance with the VT-x spec.
2145	*/
2146	typedef union
2147	{
2148	struct
2149	{
2150	/** The access type; 0=full, 1=high of 64-bit fields. */
2151	uint32_t fAccessType : 1;
2152	/** The index. */
2153	uint32_t u8Index : 8;
2154	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
2155	uint32_t u2Type : 2;
2156	/** Reserved (MBZ). */
2157	uint32_t u1Reserved0 : 1;
2158	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
2159	uint32_t u2Width : 2;
2160	/** Reserved (MBZ). */
2161	uint32_t u18Reserved0 : 18;
2162	} n;
2163
2164	/* The unsigned integer view. */
2165	uint32_t u;
2166	} VMXVMCSFIELD;
2167	AssertCompileSize(VMXVMCSFIELD, 4);
2168	/** Pointer to a VMCS field. */
2169	typedef VMXVMCSFIELD *PVMXVMCSFIELD;
2170	/** Pointer to a const VMCS field. */
2171	typedef const VMXVMCSFIELD *PCVMXVMCSFIELD;
2172
2173	/** VMCS field: Mask of reserved bits (bits 63:15 MBZ), bit 12 is not included! */
2174	#define VMX_VMCSFIELD_RSVD_MASK UINT64_C(0xffffffffffff8000)
2175
2176	/** Bits fields for a VMCS field. */
2177	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_SHIFT 0
2178	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2179	#define VMX_BF_VMCSFIELD_INDEX_SHIFT 1
2180	#define VMX_BF_VMCSFIELD_INDEX_MASK UINT32_C(0x000003fe)
2181	#define VMX_BF_VMCSFIELD_TYPE_SHIFT 10
2182	#define VMX_BF_VMCSFIELD_TYPE_MASK UINT32_C(0x00000c00)
2183	#define VMX_BF_VMCSFIELD_RSVD_12_SHIFT 12
2184	#define VMX_BF_VMCSFIELD_RSVD_12_MASK UINT32_C(0x00001000)
2185	#define VMX_BF_VMCSFIELD_WIDTH_SHIFT 13
2186	#define VMX_BF_VMCSFIELD_WIDTH_MASK UINT32_C(0x00006000)
2187	#define VMX_BF_VMCSFIELD_RSVD_15_31_SHIFT 15
2188	#define VMX_BF_VMCSFIELD_RSVD_15_31_MASK UINT32_C(0xffff8000)
2189	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCSFIELD_, UINT32_C(0), UINT32_MAX,
2190	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2191
2192	/**
2193	* VMCS field encoding: Access type.
2194	* In accordance with the VT-x spec.
2195	*/
2196	typedef enum
2197	{
2198	VMXVMCSFIELDACCESS_FULL = 0,
2199	VMXVMCSFIELDACCESS_HIGH
2200	} VMXVMCSFIELDACCESS;
2201	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
2202	/** VMCS field encoding type: Full. */
2203	#define VMX_VMCSFIELD_ACCESS_FULL 0
2204	/** VMCS field encoding type: High. */
2205	#define VMX_VMCSFIELD_ACCESS_HIGH 1
2206
2207	/**
2208	* VMCS field encoding: Type.
2209	* In accordance with the VT-x spec.
2210	*/
2211	typedef enum
2212	{
2213	VMXVMCSFIELDTYPE_CONTROL = 0,
2214	VMXVMCSFIELDTYPE_VMEXIT_INFO,
2215	VMXVMCSFIELDTYPE_GUEST_STATE,
2216	VMXVMCSFIELDTYPE_HOST_STATE
2217	} VMXVMCSFIELDTYPE;
2218	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
2219	/** VMCS field encoding type: Control. */
2220	#define VMX_VMCSFIELD_TYPE_CONTROL 0
2221	/** VMCS field encoding type: VM-exit information / read-only fields. */
2222	#define VMX_VMCSFIELD_TYPE_VMEXIT_INFO 1
2223	/** VMCS field encoding type: Guest-state. */
2224	#define VMX_VMCSFIELD_TYPE_GUEST_STATE 2
2225	/** VMCS field encoding type: Host-state. */
2226	#define VMX_VMCSFIELD_TYPE_HOST_STATE 3
2227
2228	/**
2229	* VMCS field encoding: Width.
2230	* In accordance with the VT-x spec.
2231	*/
2232	typedef enum
2233	{
2234	VMXVMCSFIELDWIDTH_16BIT = 0,
2235	VMXVMCSFIELDWIDTH_64BIT,
2236	VMXVMCSFIELDWIDTH_32BIT,
2237	VMXVMCSFIELDWIDTH_NATURAL
2238	} VMXVMCSFIELDWIDTH;
2239	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
2240	/** VMCS field encoding width: 16-bit. */
2241	#define VMX_VMCSFIELD_WIDTH_16BIT 0
2242	/** VMCS field encoding width: 64-bit. */
2243	#define VMX_VMCSFIELD_WIDTH_64BIT 1
2244	/** VMCS field encoding width: 32-bit. */
2245	#define VMX_VMCSFIELD_WIDTH_32BIT 2
2246	/** VMCS field encoding width: Natural width. */
2247	#define VMX_VMCSFIELD_WIDTH_NATURAL 3
2248	/** @} */
2249
2250
2251	/** @name VM-entry instruction length.
2252	* @{ */
2253	/** The maximum valid value for VM-entry instruction length while injecting a
2254	* software interrupt, software exception or privileged software exception. */
2255	#define VMX_ENTRY_INSTR_LEN_MAX 15
2256	/** @} */
2257
2258
2259	/** @name VM-entry register masks.
2260	* @{ */
2261	/** CR0 bits ignored on VM-entry while loading guest CR0 (ET, CD, NW, bits 6:15,
2262	* bit 17 and bits 19:28). */
2263	#define VMX_ENTRY_GUEST_CR0_IGNORE_MASK UINT64_C(0x7ffaffd0)
2264	/** DR7 bits set here are always cleared on VM-entry while loading guest DR7 (bit
2265	* 12, bits 14:15). */
2266	#define VMX_ENTRY_GUEST_DR7_MBZ_MASK UINT64_C(0xd000)
2267	/** DR7 bits set here are always set on VM-entry while loading guest DR7 (bit
2268	* 10). */
2269	#define VMX_ENTRY_GUEST_DR7_MB1_MASK UINT64_C(0x400)
2270	/** @} */
2271
2272
2273	/** @name VM-exit register masks.
2274	* @{ */
2275	/** CR0 bits ignored on VM-exit while loading host CR0 (ET, CD, NW, bits 6:15,
2276	* bit 17, bits 19:28 and bits 32:63). */
2277	#define VMX_EXIT_HOST_CR0_IGNORE_MASK UINT64_C(0xffffffff7ffaffd0)
2278	/** @} */
2279
2280
2281	/** @name Pin-based VM-execution controls.
2282	* @{
2283	*/
2284	/** External interrupt exiting. */
2285	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
2286	/** NMI exiting. */
2287	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
2288	/** Virtual NMIs. */
2289	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
2290	/** Activate VMX preemption timer. */
2291	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
2292	/** Process interrupts with the posted-interrupt notification vector. */
2293	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
2294	/** Default1 class when true capability MSRs are not supported. */
2295	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
2296
2297	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
2298	* controls field in the VMCS. */
2299	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
2300	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
2301	#define VMX_BF_PIN_CTLS_RSVD_1_2_SHIFT 1
2302	#define VMX_BF_PIN_CTLS_RSVD_1_2_MASK UINT32_C(0x00000006)
2303	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
2304	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
2305	#define VMX_BF_PIN_CTLS_RSVD_4_SHIFT 4
2306	#define VMX_BF_PIN_CTLS_RSVD_4_MASK UINT32_C(0x00000010)
2307	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
2308	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
2309	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
2310	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
2311	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
2312	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
2313	#define VMX_BF_PIN_CTLS_RSVD_8_31_SHIFT 8
2314	#define VMX_BF_PIN_CTLS_RSVD_8_31_MASK UINT32_C(0xffffff00)
2315	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
2316	(EXT_INT_EXIT, RSVD_1_2, NMI_EXIT, RSVD_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, RSVD_8_31));
2317	/** @} */
2318
2319
2320	/** @name Processor-based VM-execution controls.
2321	* @{
2322	*/
2323	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
2324	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
2325	/** Use timestamp counter offset. */
2326	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
2327	/** VM-exit when executing the HLT instruction. */
2328	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
2329	/** VM-exit when executing the INVLPG instruction. */
2330	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
2331	/** VM-exit when executing the MWAIT instruction. */
2332	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
2333	/** VM-exit when executing the RDPMC instruction. */
2334	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
2335	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
2336	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
2337	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
2338	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2339	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
2340	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
2341	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2342	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
2343	/** Whether the secondary processor based VM-execution controls are used. */
2344	#define VMX_PROC_CTLS_USE_TERTIARY_CTLS RT_BIT(17)
2345	/** VM-exit on CR8 loads. */
2346	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
2347	/** VM-exit on CR8 stores. */
2348	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
2349	/** Use TPR shadow. */
2350	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
2351	/** VM-exit when virtual NMI blocking is disabled. */
2352	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
2353	/** VM-exit when executing a MOV DRx instruction. */
2354	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
2355	/** VM-exit when executing IO instructions. */
2356	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
2357	/** Use IO bitmaps. */
2358	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
2359	/** Monitor trap flag. */
2360	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2361	/** Use MSR bitmaps. */
2362	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2363	/** VM-exit when executing the MONITOR instruction. */
2364	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2365	/** VM-exit when executing the PAUSE instruction. */
2366	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2367	/** Whether the secondary processor based VM-execution controls are used. */
2368	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2369	/** Default1 class when true-capability MSRs are not supported. */
2370	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2371
2372	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2373	* controls field in the VMCS. */
2374	#define VMX_BF_PROC_CTLS_RSVD_0_1_SHIFT 0
2375	#define VMX_BF_PROC_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2376	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2377	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2378	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2379	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2380	#define VMX_BF_PROC_CTLS_RSVD_4_6_SHIFT 4
2381	#define VMX_BF_PROC_CTLS_RSVD_4_6_MASK UINT32_C(0x00000070)
2382	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2383	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2384	#define VMX_BF_PROC_CTLS_RSVD_8_SHIFT 8
2385	#define VMX_BF_PROC_CTLS_RSVD_8_MASK UINT32_C(0x00000100)
2386	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2387	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2388	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2389	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2390	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2391	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2392	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2393	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2394	#define VMX_BF_PROC_CTLS_RSVD_13_14_SHIFT 13
2395	#define VMX_BF_PROC_CTLS_RSVD_13_14_MASK UINT32_C(0x00006000)
2396	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2397	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2398	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2399	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2400	#define VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT 17
2401	#define VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_MASK UINT32_C(0x00020000)
2402	#define VMX_BF_PROC_CTLS_RSVD_18_SHIFT 18
2403	#define VMX_BF_PROC_CTLS_RSVD_18_MASK UINT32_C(0x00040000)
2404	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2405	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2406	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2407	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2408	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2409	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2410	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2411	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2412	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2413	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2414	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2415	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2416	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2417	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2418	#define VMX_BF_PROC_CTLS_RSVD_26_SHIFT 26
2419	#define VMX_BF_PROC_CTLS_RSVD_26_MASK UINT32_C(0x4000000)
2420	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2421	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2422	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2423	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2424	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2425	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2426	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2427	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2428	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2429	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2430	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2431	(RSVD_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, RSVD_4_6, HLT_EXIT, RSVD_8, INVLPG_EXIT,
2432	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, RSVD_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, USE_TERTIARY_CTLS,
2433	RSVD_18, CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2434	USE_IO_BITMAPS, RSVD_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2435	USE_SECONDARY_CTLS));
2436	/** @} */
2437
2438
2439	/** @name Secondary Processor-based VM-execution controls.
2440	* @{
2441	*/
2442	/** Virtualize APIC accesses. */
2443	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2444	/** EPT supported/enabled. */
2445	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2446	/** Descriptor table instructions cause VM-exits. */
2447	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2448	/** RDTSCP supported/enabled. */
2449	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2450	/** Virtualize x2APIC mode. */
2451	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2452	/** VPID supported/enabled. */
2453	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2454	/** VM-exit when executing the WBINVD instruction. */
2455	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2456	/** Unrestricted guest execution. */
2457	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2458	/** APIC register virtualization. */
2459	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2460	/** Virtual-interrupt delivery. */
2461	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2462	/** A specified number of pause loops cause a VM-exit. */
2463	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2464	/** VM-exit when executing RDRAND instructions. */
2465	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2466	/** Enables INVPCID instructions. */
2467	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2468	/** Enables VMFUNC instructions. */
2469	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2470	/** Enables VMCS shadowing. */
2471	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2472	/** Enables ENCLS VM-exits. */
2473	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2474	/** VM-exit when executing RDSEED. */
2475	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2476	/** Enables page-modification logging. */
2477	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2478	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2479	#define VMX_PROC_CTLS2_EPT_XCPT_VE RT_BIT(18)
2480	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2481	#define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19)
2482	/** Enables XSAVES/XRSTORS instructions. */
2483	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2484	/** Enables supervisor/user mode based EPT execute permission for linear
2485	* addresses. */
2486	#define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22)
2487	/** Enables EPT write permissions to be specified at granularity of 128 bytes. */
2488	#define VMX_PROC_CTLS2_SPP_EPT RT_BIT(23)
2489	/** Intel PT output addresses are treated as guest-physical addresses and
2490	* translated using EPT. */
2491	#define VMX_PROC_CTLS2_PT_EPT RT_BIT(24)
2492	/** Use TSC scaling. */
2493	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2494	/** Enables TPAUSE, UMONITOR and UMWAIT instructions. */
2495	#define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26)
2496	/** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */
2497	#define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28)
2498
2499	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2500	* VM-execution controls field in the VMCS. */
2501	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2502	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2503	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2504	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2505	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2506	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2507	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2508	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2509	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2510	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2511	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2512	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2513	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2514	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2515	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2516	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2517	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2518	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2519	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2520	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2521	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2522	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2523	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2524	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2525	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2526	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2527	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2528	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2529	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2530	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2531	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2532	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2533	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2534	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2535	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2536	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2537	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2538	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2539	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19
2540	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000)
2541	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2542	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2543	#define VMX_BF_PROC_CTLS2_RSVD_21_SHIFT 21
2544	#define VMX_BF_PROC_CTLS2_RSVD_21_MASK UINT32_C(0x00200000)
2545	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22
2546	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000)
2547	#define VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT 23
2548	#define VMX_BF_PROC_CTLS2_SPP_EPT_MASK UINT32_C(0x00800000)
2549	#define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24
2550	#define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000)
2551	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2552	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2553	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26
2554	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000)
2555	#define VMX_BF_PROC_CTLS2_RSVD_27_SHIFT 27
2556	#define VMX_BF_PROC_CTLS2_RSVD_27_MASK UINT32_C(0x08000000)
2557	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28
2558	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000)
2559	#define VMX_BF_PROC_CTLS2_RSVD_29_31_SHIFT 29
2560	#define VMX_BF_PROC_CTLS2_RSVD_29_31_MASK UINT32_C(0xe0000000)
2561
2562	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2563	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2564	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2565	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, RSVD_21,
2566	MODE_BASED_EPT_PERM, SPP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, RSVD_27, ENCLV_EXIT,
2567	RSVD_29_31));
2568	/** @} */
2569
2570
2571	/** @name Tertiary Processor-based VM-execution controls.
2572	* @{
2573	*/
2574	/** VM-exit when executing LOADIWKEY. */
2575	#define VMX_PROC_CTLS3_LOADIWKEY_EXIT RT_BIT_64(0)
2576
2577	/** Bit fields for Tertiary processor-based VM-execution controls field in the VMCS. */
2578	#define VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT 0
2579	#define VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_MASK UINT64_C(0x0000000000000001)
2580	#define VMX_BF_PROC_CTLS3_RSVD_1_63_SHIFT 1
2581	#define VMX_BF_PROC_CTLS3_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
2582
2583	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS3_, UINT64_C(0), UINT64_MAX,
2584	(LOADIWKEY_EXIT, RSVD_1_63));
2585	/** @} */
2586
2587
2588	/** @name VM-entry controls.
2589	* @{
2590	*/
2591	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2592	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2593	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2594	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2595	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2596	/** In SMM mode after VM-entry. */
2597	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2598	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2599	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2600	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2601	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2602	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2603	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2604	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2605	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2606	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2607	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2608	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2609	#define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17)
2610	/** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
2611	#define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18)
2612	/** Whether the guest CET-related MSRs and SPP are loaded on VM-entry. */
2613	#define VMX_ENTRY_CTLS_LOAD_CET_STATE RT_BIT(20)
2614	/** Whether the guest IA32_PKRS MSR is loaded on VM-entry. */
2615	#define VMX_ENTRY_CTLS_LOAD_PKRS_MSR RT_BIT(22)
2616	/** Default1 class when true-capability MSRs are not supported. */
2617	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2618
2619	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2620	* VMCS. */
2621	#define VMX_BF_ENTRY_CTLS_RSVD_0_1_SHIFT 0
2622	#define VMX_BF_ENTRY_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2623	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2624	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2625	#define VMX_BF_ENTRY_CTLS_RSVD_3_8_SHIFT 3
2626	#define VMX_BF_ENTRY_CTLS_RSVD_3_8_MASK UINT32_C(0x000001f8)
2627	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2628	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2629	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2630	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2631	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2632	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2633	#define VMX_BF_ENTRY_CTLS_RSVD_12_SHIFT 12
2634	#define VMX_BF_ENTRY_CTLS_RSVD_12_MASK UINT32_C(0x00001000)
2635	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2636	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2637	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2638	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2639	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2640	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2641	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2642	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2643	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17
2644	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000)
2645	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18
2646	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000)
2647	#define VMX_BF_ENTRY_CTLS_RSVD_19_SHIFT 19
2648	#define VMX_BF_ENTRY_CTLS_RSVD_19_MASK UINT32_C(0x00080000)
2649	#define VMX_BF_ENTRY_CTLS_LOAD_CET_SHIFT 20
2650	#define VMX_BF_ENTRY_CTLS_LOAD_CET_MASK UINT32_C(0x00100000)
2651	#define VMX_BF_ENTRY_CTLS_RSVD_21_SHIFT 21
2652	#define VMX_BF_ENTRY_CTLS_RSVD_21_MASK UINT32_C(0x00200000)
2653	#define VMX_BF_ENTRY_CTLS_LOAD_PKRS_MSR_SHIFT 22
2654	#define VMX_BF_ENTRY_CTLS_LOAD_PKRS_MSR_MASK UINT32_C(0x00400000)
2655	#define VMX_BF_ENTRY_CTLS_RSVD_23_31_SHIFT 23
2656	#define VMX_BF_ENTRY_CTLS_RSVD_23_31_MASK UINT32_C(0xff800000)
2657
2658	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2659	(RSVD_0_1, LOAD_DEBUG, RSVD_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, RSVD_12,
2660	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
2661	LOAD_RTIT_CTL_MSR, RSVD_19, LOAD_CET, RSVD_21, LOAD_PKRS_MSR, RSVD_23_31));
2662	/** @} */
2663
2664
2665	/** @name VM-exit controls.
2666	* @{
2667	*/
2668	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2669	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2670	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2671	/** Return to long mode after a VM-exit. */
2672	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2673	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2674	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2675	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2676	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2677	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2678	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2679	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2680	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2681	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2682	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2683	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2684	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2685	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2686	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2687	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2688	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2689	/** Whether to conceal VMX from Intel PT. */
2690	#define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24)
2691	/** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
2692	#define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25)
2693	/** Whether CET-related MSRs and SPP are loaded on VM-exit. */
2694	#define VMX_EXIT_CTLS_LOAD_CET_STATE RT_BIT(28)
2695	/** Whether the host IA32_PKRS MSR is loaded on VM-exit. */
2696	#define VMX_EXIT_CTLS_LOAD_PKRS_MSR RT_BIT(29)
2697	/** Default1 class when true-capability MSRs are not supported. */
2698	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2699
2700	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2701	* VMCS. */
2702	#define VMX_BF_EXIT_CTLS_RSVD_0_1_SHIFT 0
2703	#define VMX_BF_EXIT_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2704	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2705	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2706	#define VMX_BF_EXIT_CTLS_RSVD_3_8_SHIFT 3
2707	#define VMX_BF_EXIT_CTLS_RSVD_3_8_MASK UINT32_C(0x000001f8)
2708	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2709	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2710	#define VMX_BF_EXIT_CTLS_RSVD_10_11_SHIFT 10
2711	#define VMX_BF_EXIT_CTLS_RSVD_10_11_MASK UINT32_C(0x00000c00)
2712	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2713	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2714	#define VMX_BF_EXIT_CTLS_RSVD_13_14_SHIFT 13
2715	#define VMX_BF_EXIT_CTLS_RSVD_13_14_MASK UINT32_C(0x00006000)
2716	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2717	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2718	#define VMX_BF_EXIT_CTLS_RSVD_16_17_SHIFT 16
2719	#define VMX_BF_EXIT_CTLS_RSVD_16_17_MASK UINT32_C(0x00030000)
2720	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2721	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2722	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2723	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2724	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2725	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2726	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2727	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2728	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2729	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2730	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23
2731	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000)
2732	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24
2733	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000)
2734	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25
2735	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000)
2736	#define VMX_BF_EXIT_CTLS_RSVD_26_27_SHIFT 26
2737	#define VMX_BF_EXIT_CTLS_RSVD_26_27_MASK UINT32_C(0x0c000000)
2738	#define VMX_BF_EXIT_CTLS_LOAD_CET_SHIFT 28
2739	#define VMX_BF_EXIT_CTLS_LOAD_CET_MASK UINT32_C(0x10000000)
2740	#define VMX_BF_EXIT_CTLS_LOAD_PKRS_MSR_SHIFT 29
2741	#define VMX_BF_EXIT_CTLS_LOAD_PKRS_MSR_MASK UINT32_C(0x20000000)
2742	#define VMX_BF_EXIT_CTLS_RSVD_30_31_SHIFT 30
2743	#define VMX_BF_EXIT_CTLS_RSVD_30_31_MASK UINT32_C(0xc0000000)
2744	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2745	(RSVD_0_1, SAVE_DEBUG, RSVD_3_8, HOST_ADDR_SPACE_SIZE, RSVD_10_11, LOAD_PERF_MSR, RSVD_13_14,
2746	ACK_EXT_INT, RSVD_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2747	SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, RSVD_26_27,
2748	LOAD_CET, LOAD_PKRS_MSR, RSVD_30_31));
2749	/** @} */
2750
2751
2752	/** @name VM-exit reason.
2753	* @{
2754	*/
2755	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2756	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2757	#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2758
2759	/** Bit fields for VM-exit reason. */
2760	/** The exit reason. */
2761	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2762	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2763	/** Bits 16:26 are reseved and MBZ. */
2764	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2765	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2766	/** Whether the VM-exit was incident to enclave mode. */
2767	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2768	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2769	/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2770	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2771	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2772	/** VM-exit from VMX root operation (only possible with SMM). */
2773	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2774	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2775	/** Bit 30 is reserved and MBZ. */
2776	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2777	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2778	/** Whether VM-entry failed (currently only happens during loading guest-state
2779	* or MSRs or machine check exceptions). */
2780	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2781	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2782	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2783	(BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2784	/** @} */
2785
2786
2787	/** @name VM-entry interruption information.
2788	* @{
2789	*/
2790	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2791	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2792	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2793	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2794	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2795	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2796	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2797	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2798	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2799	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2800	/** Construct an VM-entry interruption information field from a VM-exit interruption
2801	* info value (same except that bit 12 is reserved). */
2802	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2803	/** Construct a VM-entry interruption information field from an IDT-vectoring
2804	* information field (same except that bit 12 is reserved). */
2805	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2806	/** If the VM-entry interruption information field indicates a page-fault. */
2807	#define VMX_ENTRY_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2808	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2809	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2810	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2811	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT) \
2812	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_PF)))
2813	/** If the VM-entry interruption information field indicates an external
2814	* interrupt. */
2815	#define VMX_ENTRY_INT_INFO_IS_EXT_INT(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2816	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK)) \
2817	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2818	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_EXT_INT)))
2819	/** If the VM-entry interruption information field indicates an NMI. */
2820	#define VMX_ENTRY_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2821	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2822	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2823	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2824	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_NMI) \
2825	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_NMI)))
2826
2827	/** Bit fields for VM-entry interruption information. */
2828	/** The VM-entry interruption vector. */
2829	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2830	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2831	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2832	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2833	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2834	/** Whether this event has an error code. */
2835	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2836	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2837	/** Bits 12:30 are reserved and MBZ. */
2838	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2839	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2840	/** Whether this VM-entry interruption info is valid. */
2841	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2842	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2843	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2844	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2845	/** @} */
2846
2847
2848	/** @name VM-entry exception error code.
2849	* @{ */
2850	/** Error code valid mask. */
2851	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2852	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2853	* stack aligned for doubleword pushes, the upper half of the error code is
2854	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2855	* use below. */
2856	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2857	/** @} */
2858
2859	/** @name VM-entry interruption information types.
2860	* @{
2861	*/
2862	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2863	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2864	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2865	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2866	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2867	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2868	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2869	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2870	/** @} */
2871
2872
2873	/** @name VM-entry interruption information vector types for
2874	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2875	* @{ */
2876	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2877	/** @} */
2878
2879
2880	/** @name VM-exit interruption information.
2881	* @{
2882	*/
2883	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2884	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2885	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2886	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2887	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2888	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2889	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2890	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2891	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2892
2893	/** If the VM-exit interruption information field indicates an page-fault. */
2894	#define VMX_EXIT_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2895	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2896	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2897	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2898	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2899	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_PF)))
2900	/** If the VM-exit interruption information field indicates an double-fault. */
2901	#define VMX_EXIT_INT_INFO_IS_XCPT_DF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2902	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2903	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2904	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2905	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2906	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)))
2907	/** If the VM-exit interruption information field indicates an NMI. */
2908	#define VMX_EXIT_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2909	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2910	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2911	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2912	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI) \
2913	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI)))
2914
2915
2916	/** Bit fields for VM-exit interruption infomration. */
2917	/** The VM-exit interruption vector. */
2918	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2919	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2920	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2921	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2922	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2923	/** Whether this event has an error code. */
2924	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2925	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2926	/** Whether NMI-unblocking due to IRET is active. */
2927	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2928	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2929	/** Bits 13:30 is reserved (MBZ). */
2930	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2931	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2932	/** Whether this VM-exit interruption info is valid. */
2933	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2934	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2935	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2936	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2937	/** @} */
2938
2939
2940	/** @name VM-exit interruption information types.
2941	* @{
2942	*/
2943	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2944	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2945	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2946	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2947	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2948	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2949	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2950	/** @} */
2951
2952
2953	/** @name VM-exit instruction identity.
2954	*
2955	* These are found in VM-exit instruction information fields for certain
2956	* instructions.
2957	* @{ */
2958	typedef uint32_t VMXINSTRID;
2959	/** Whether the instruction ID field is valid. */
2960	#define VMXINSTRID_VALID RT_BIT_32(31)
2961	/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
2962	* read or write. */
2963	#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
2964	/** Gets whether the instruction ID is valid or not. */
2965	#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
2966	#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
2967	/** Gets the instruction ID. */
2968	#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W))
2969	/** No instruction ID info. */
2970	#define VMXINSTRID_NONE 0
2971
2972	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2973	#define VMXINSTRID_SGDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2974	#define VMXINSTRID_SIDT (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2975	#define VMXINSTRID_LGDT (0x2 \| VMXINSTRID_VALID)
2976	#define VMXINSTRID_LIDT (0x3 \| VMXINSTRID_VALID)
2977
2978	#define VMXINSTRID_SLDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2979	#define VMXINSTRID_STR (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2980	#define VMXINSTRID_LLDT (0x2 \| VMXINSTRID_VALID)
2981	#define VMXINSTRID_LTR (0x3 \| VMXINSTRID_VALID)
2982
2983	/** The following IDs are used internally (some for logging, others for conveying
2984	* the ModR/M primary operand write bit): */
2985	#define VMXINSTRID_VMLAUNCH (0x10 \| VMXINSTRID_VALID)
2986	#define VMXINSTRID_VMRESUME (0x11 \| VMXINSTRID_VALID)
2987	#define VMXINSTRID_VMREAD (0x12 \| VMXINSTRID_VALID)
2988	#define VMXINSTRID_VMWRITE (0x13 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2989	#define VMXINSTRID_IO_IN (0x14 \| VMXINSTRID_VALID)
2990	#define VMXINSTRID_IO_INS (0x15 \| VMXINSTRID_VALID)
2991	#define VMXINSTRID_IO_OUT (0x16 \| VMXINSTRID_VALID)
2992	#define VMXINSTRID_IO_OUTS (0x17 \| VMXINSTRID_VALID)
2993	#define VMXINSTRID_MOV_TO_DRX (0x18 \| VMXINSTRID_VALID)
2994	#define VMXINSTRID_MOV_FROM_DRX (0x19 \| VMXINSTRID_VALID)
2995	/** @} */
2996
2997
2998	/** @name IDT-vectoring information.
2999	* @{
3000	*/
3001	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
3002	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
3003	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
3004	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
3005	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
3006	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
3007	#define VMX_IDT_VECTORING_INFO_VALID RT_BIT(31)
3008
3009	/** Construct an IDT-vectoring information field from an VM-entry interruption
3010	* information field (same except that bit 12 is reserved). */
3011	#define VMX_IDT_VECTORING_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
3012	/** If the IDT-vectoring information field indicates a page-fault. */
3013	#define VMX_IDT_VECTORING_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
3014	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
3015	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
3016	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
3017	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT) \
3018	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_PF)))
3019	/** If the IDT-vectoring information field indicates an NMI. */
3020	#define VMX_IDT_VECTORING_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
3021	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
3022	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
3023	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
3024	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_NMI) \
3025	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_NMI)))
3026
3027
3028	/** Bit fields for IDT-vectoring information. */
3029	/** The IDT-vectoring info vector. */
3030	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
3031	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
3032	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
3033	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
3034	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
3035	/** Whether the event has an error code. */
3036	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
3037	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
3038	/** Bit 12 is undefined. */
3039	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
3040	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
3041	/** Bits 13:30 is reserved (MBZ). */
3042	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
3043	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
3044	/** Whether this IDT-vectoring info is valid. */
3045	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
3046	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
3047	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
3048	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
3049	/** @} */
3050
3051
3052	/** @name IDT-vectoring information vector types.
3053	* @{
3054	*/
3055	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
3056	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
3057	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
3058	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
3059	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
3060	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
3061	#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
3062	/** @} */
3063
3064
3065	/** @name TPR threshold.
3066	* @{ */
3067	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
3068	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
3069
3070	/** Bit fields for TPR threshold. */
3071	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
3072	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
3073	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
3074	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
3075	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
3076	(TPR, RSVD_4_31));
3077	/** @} */
3078
3079
3080	/** @name Guest-activity states.
3081	* @{
3082	*/
3083	/** The logical processor is active. */
3084	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
3085	/** The logical processor is inactive, because it executed a HLT instruction. */
3086	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
3087	/** The logical processor is inactive, because of a triple fault or other serious error. */
3088	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
3089	/** The logical processor is inactive, because it's waiting for a startup-IPI */
3090	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
3091	/** @} */
3092
3093
3094	/** @name Guest-interruptibility states.
3095	* @{
3096	*/
3097	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
3098	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
3099	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
3100	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
3101	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
3102
3103	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
3104	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
3105	/** @} */
3106
3107
3108	/** @name Exit qualification for debug exceptions.
3109	* @{
3110	*/
3111	/** Hardware breakpoint 0 was met. */
3112	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
3113	/** Hardware breakpoint 1 was met. */
3114	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
3115	/** Hardware breakpoint 2 was met. */
3116	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
3117	/** Hardware breakpoint 3 was met. */
3118	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
3119	/** Debug register access detected. */
3120	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
3121	/** A debug exception would have been triggered by single-step execution mode. */
3122	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
3123	/** Mask of all valid bits. */
3124	#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
3125	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
3126	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
3127	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
3128	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
3129	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
3130
3131	/** Bit fields for Exit qualifications due to debug exceptions. */
3132	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
3133	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3134	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
3135	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3136	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
3137	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3138	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
3139	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3140	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
3141	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
3142	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
3143	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
3144	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
3145	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3146	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
3147	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
3148	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
3149	(BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
3150	/** @} */
3151
3152	/** @name Exit qualification for Mov DRx.
3153	* @{
3154	*/
3155	/** 0-2: Debug register number */
3156	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
3157	/** 3: Reserved; cleared to 0. */
3158	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
3159	/** 4: Direction of move (0 = write, 1 = read) */
3160	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
3161	/** 5-7: Reserved; cleared to 0. */
3162	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
3163	/** 8-11: General purpose register number. */
3164	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
3165
3166	/** Bit fields for Exit qualification due to Mov DRx. */
3167	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
3168	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
3169	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
3170	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
3171	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
3172	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
3173	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
3174	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
3175	#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
3176	#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3177	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
3178	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
3179	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
3180	(REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
3181	/** @} */
3182
3183
3184	/** @name Exit qualification for debug exceptions types.
3185	* @{
3186	*/
3187	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
3188	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
3189	/** @} */
3190
3191
3192	/** @name Exit qualification for control-register accesses.
3193	* @{
3194	*/
3195	/** 0-3: Control register number (0 for CLTS & LMSW) */
3196	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
3197	/** 4-5: Access type. */
3198	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
3199	/** 6: LMSW operand type memory (1 for memory, 0 for register). */
3200	#define VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(a) (((a) >> 6) & 1)
3201	/** 7: Reserved; cleared to 0. */
3202	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
3203	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
3204	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
3205	/** 12-15: Reserved; cleared to 0. */
3206	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
3207	/** 16-31: LMSW source data (else 0). */
3208	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
3209
3210	/** Bit fields for Exit qualification for control-register accesses. */
3211	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
3212	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
3213	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
3214	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
3215	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
3216	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
3217	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
3218	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
3219	#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
3220	#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3221	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
3222	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
3223	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
3224	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
3225	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
3226	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3227	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
3228	(REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
3229	/** @} */
3230
3231
3232	/** @name Exit qualification for control-register access types.
3233	* @{
3234	*/
3235	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
3236	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
3237	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
3238	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
3239	/** @} */
3240
3241
3242	/** @name Exit qualification for task switch.
3243	* @{
3244	*/
3245	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
3246	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
3247	/** Task switch caused by a call instruction. */
3248	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
3249	/** Task switch caused by an iret instruction. */
3250	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
3251	/** Task switch caused by a jmp instruction. */
3252	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
3253	/** Task switch caused by an interrupt gate. */
3254	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
3255
3256	/** Bit fields for Exit qualification for task switches. */
3257	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
3258	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
3259	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
3260	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
3261	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
3262	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
3263	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
3264	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3265	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
3266	(NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
3267	/** @} */
3268
3269
3270	/** @name Exit qualification for EPT violations.
3271	* @{
3272	*/
3273	/** Set if acess causing the violation was a data read. */
3274	#define VMX_EXIT_QUAL_EPT_ACCESS_READ RT_BIT_64(0)
3275	/** Set if acess causing the violation was a data write. */
3276	#define VMX_EXIT_QUAL_EPT_ACCESS_WRITE RT_BIT_64(1)
3277	/** Set if the violation was caused by an instruction fetch. */
3278	#define VMX_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH RT_BIT_64(2)
3279	/** AND of the present bit of all EPT structures. */
3280	#define VMX_EXIT_QUAL_EPT_ENTRY_READ RT_BIT_64(3)
3281	/** AND of the write bit of all EPT structures. */
3282	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT_64(4)
3283	/** AND of the execute bit of all EPT structures. */
3284	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT_64(5)
3285	/** And of the execute bit of all EPT structures for user-mode addresses
3286	* (requires mode-based execute control). */
3287	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER RT_BIT_64(6)
3288	/** Set if the guest linear address field is valid. */
3289	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID RT_BIT_64(7)
3290	/** If bit 7 is one: (reserved otherwise)
3291	* 1 - violation due to physical address access.
3292	* 0 - violation caused by page walk or access/dirty bit updates
3293	*/
3294	#define VMX_EXIT_QUAL_EPT_ACCESS_TRANSLATE RT_BIT_64(8)
3295	/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3296	* 1 - linear address is user-mode address.
3297	* 0 - linear address is supervisor-mode address.
3298	*/
3299	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_USER RT_BIT_64(9)
3300	/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3301	* 1 - linear address translates to read-only page.
3302	* 0 - linear address translates to read-write page.
3303	*/
3304	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_RO RT_BIT_64(10)
3305	/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3306	* 1 - linear address translates to executable-disabled page.
3307	* 0 - linear address translates to executable page.
3308	*/
3309	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_XD RT_BIT_64(11)
3310	/** NMI unblocking due to IRET. */
3311	#define VMX_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET RT_BIT_64(12)
3312	/** Set if acess causing the violation was a shadow-stack access. */
3313	#define VMX_EXIT_QUAL_EPT_ACCESS_SHW_STACK RT_BIT_64(13)
3314	/** If supervisor-shadow stack is enabled: (reserved otherwise)
3315	* 1 - supervisor shadow-stack access allowed.
3316	* 0 - supervisor shadow-stack access disallowed.
3317	*/
3318	#define VMX_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER RT_BIT_64(14)
3319	/** Set if access is related to trace output by Intel PT (reserved otherwise). */
3320	#define VMX_EXIT_QUAL_EPT_ACCESS_PT_TRACE RT_BIT_64(16)
3321
3322	/** Checks whether NMI unblocking due to IRET. */
3323	#define VMX_EXIT_QUAL_EPT_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
3324
3325	/** Bit fields for Exit qualification for EPT violations. */
3326	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_READ_SHIFT 0
3327	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_READ_MASK UINT64_C(0x0000000000000001)
3328	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE_SHIFT 1
3329	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE_MASK UINT64_C(0x0000000000000002)
3330	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH_SHIFT 2
3331	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH_MASK UINT64_C(0x0000000000000004)
3332	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_READ_SHIFT 3
3333	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_READ_MASK UINT64_C(0x0000000000000008)
3334	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE_SHIFT 4
3335	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE_MASK UINT64_C(0x0000000000000010)
3336	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_SHIFT 5
3337	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_MASK UINT64_C(0x0000000000000020)
3338	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER_SHIFT 6
3339	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER_MASK UINT64_C(0x0000000000000040)
3340	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_SHIFT 7
3341	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK UINT64_C(0x0000000000000080)
3342	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_TRANSLATE_SHIFT 8
3343	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_TRANSLATE_MASK UINT64_C(0x0000000000000100)
3344	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_USER_SHIFT 9
3345	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_USER_MASK UINT64_C(0x0000000000000200)
3346	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_RO_SHIFT 10
3347	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_RO_MASK UINT64_C(0x0000000000000400)
3348	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_XD_SHIFT 11
3349	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_XD_MASK UINT64_C(0x0000000000000800)
3350	#define VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET_SHIFT 12
3351	#define VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET_MASK UINT64_C(0x0000000000001000)
3352	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_SHW_STACK_SHIFT 13
3353	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_SHW_STACK_MASK UINT64_C(0x0000000000002000)
3354	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER_SHIFT 14
3355	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER_MASK UINT64_C(0x0000000000004000)
3356	#define VMX_BF_EXIT_QUAL_EPT_RSVD_15_SHIFT 15
3357	#define VMX_BF_EXIT_QUAL_EPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3358	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_PT_TRACE_SHIFT 16
3359	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_PT_TRACE_MASK UINT64_C(0x0000000000010000)
3360	#define VMX_BF_EXIT_QUAL_EPT_RSVD_17_63_SHIFT 17
3361	#define VMX_BF_EXIT_QUAL_EPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3362	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_EPT_, UINT64_C(0), UINT64_MAX,
3363	(ACCESS_READ, ACCESS_WRITE, ACCESS_INSTR_FETCH, ENTRY_READ, ENTRY_WRITE, ENTRY_EXECUTE,
3364	ENTRY_EXECUTE_USER, LINEAR_ADDR_VALID, ACCESS_TRANSLATE, LINEAR_ADDR_USER, LINEAR_ADDR_RO,
3365	LINEAR_ADDR_XD, NMI_UNBLOCK_IRET, ACCESS_SHW_STACK, ENTRY_SHW_STACK_SUPER, RSVD_15,
3366	ACCESS_PT_TRACE, RSVD_17_63));
3367	/** @} */
3368
3369
3370	/** @name Exit qualification for I/O instructions.
3371	* @{
3372	*/
3373	/** 0-2: IO operation size 0(=1 byte), 1(=2 bytes) and 3(=4 bytes). */
3374	#define VMX_EXIT_QUAL_IO_SIZE(a) ((a) & 7)
3375	/** 3: IO operation direction. */
3376	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
3377	/** 4: String IO operation (INS / OUTS). */
3378	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
3379	/** 5: Repeated IO operation. */
3380	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
3381	/** 6: Operand encoding. */
3382	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
3383	/** 16-31: IO Port (0-0xffff). */
3384	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
3385
3386	/** Bit fields for Exit qualification for I/O instructions. */
3387	#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
3388	#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
3389	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
3390	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
3391	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
3392	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
3393	#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
3394	#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
3395	#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
3396	#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
3397	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
3398	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
3399	#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
3400	#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
3401	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
3402	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3403	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
3404	(WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
3405	/** @} */
3406
3407
3408	/** @name Exit qualification for I/O instruction types.
3409	* @{
3410	*/
3411	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
3412	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
3413	/** @} */
3414
3415
3416	/** @name Exit qualification for I/O instruction encoding.
3417	* @{
3418	*/
3419	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
3420	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
3421	/** @} */
3422
3423
3424	/** @name Exit qualification for APIC-access VM-exits from linear and
3425	* guest-physical accesses.
3426	* @{
3427	*/
3428	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
3429	* access within the APIC page. */
3430	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
3431	/** 12-15: Access type. */
3432	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
3433	/* Rest reserved. */
3434
3435	/** Bit fields for Exit qualification for APIC-access VM-exits. */
3436	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
3437	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
3438	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
3439	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
3440	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
3441	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
3442	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
3443	(OFFSET, TYPE, RSVD_16_63));
3444	/** @} */
3445
3446
3447	/** @name Exit qualification for linear address APIC-access types.
3448	* @{
3449	*/
3450	/** Linear access for a data read during instruction execution. */
3451	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
3452	/** Linear access for a data write during instruction execution. */
3453	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
3454	/** Linear access for an instruction fetch. */
3455	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
3456	/** Linear read/write access during event delivery. */
3457	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
3458	/** Physical read/write access during event delivery. */
3459	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
3460	/** Physical access for an instruction fetch or during instruction execution. */
3461	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
3462
3463	/**
3464	* APIC-access type.
3465	* In accordance with the VT-x spec.
3466	*/
3467	typedef enum
3468	{
3469	VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
3470	VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
3471	VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
3472	VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
3473	VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
3474	VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
3475	} VMXAPICACCESS;
3476	AssertCompileSize(VMXAPICACCESS, 4);
3477	/** @} */
3478
3479
3480	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
3481	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3482	* @{
3483	*/
3484	/** Address calculation scaling field (powers of two). */
3485	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
3486	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3487	/** Bits 2 thru 6 are undefined. */
3488	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
3489	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
3490	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3491	* @remarks anyone's guess why this is a 3 bit field... */
3492	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
3493	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3494	/** Bit 10 is defined as zero. */
3495	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
3496	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
3497	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
3498	* for exits from 64-bit code as the operand size there is fixed. */
3499	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
3500	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
3501	/** Bits 12 thru 14 are undefined. */
3502	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
3503	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
3504	/** Applicable segment register (X86_SREG_XXX values). */
3505	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
3506	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3507	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3508	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
3509	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3510	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3511	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3512	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3513	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3514	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
3515	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3516	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3517	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
3518	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3519	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
3520	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
3521	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3522	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
3523	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
3524	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
3525	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
3526	/** Bits 30 & 31 are undefined. */
3527	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
3528	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3529	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3530	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
3531	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3532	/** @} */
3533
3534
3535	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
3536	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3537	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
3538	* @{
3539	*/
3540	/** Address calculation scaling field (powers of two). */
3541	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
3542	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3543	/** Bit 2 is undefined. */
3544	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
3545	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
3546	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
3547	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
3548	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
3549	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3550	* @remarks anyone's guess why this is a 3 bit field... */
3551	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
3552	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3553	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
3554	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
3555	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
3556	/** Bits 11 thru 14 are undefined. */
3557	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
3558	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
3559	/** Applicable segment register (X86_SREG_XXX values). */
3560	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
3561	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3562	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3563	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
3564	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3565	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3566	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3567	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3568	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3569	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
3570	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3571	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3572	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
3573	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3574	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
3575	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
3576	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3577	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
3578	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
3579	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
3580	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
3581	/** Bits 30 & 31 are undefined. */
3582	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3583	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3584	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3585	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3586	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3587	/** @} */
3588
3589
3590	/** @name Format of Pending-Debug-Exceptions.
3591	* Bits 4-11, 13, 15 and 17-63 are reserved.
3592	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3593	* possibly valid here but not in DR6.
3594	* @{
3595	*/
3596	/** Hardware breakpoint 0 was met. */
3597	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3598	/** Hardware breakpoint 1 was met. */
3599	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3600	/** Hardware breakpoint 2 was met. */
3601	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3602	/** Hardware breakpoint 3 was met. */
3603	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3604	/** At least one data or IO breakpoint was hit. */
3605	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3606	/** A debug exception would have been triggered by single-step execution mode. */
3607	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3608	/** A debug exception occurred inside an RTM region. */
3609	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3610	/** Mask of valid bits. */
3611	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3612	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3613	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3614	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3615	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3616	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3617	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3618	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3619	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3620	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3621	/** Bit fields for Pending debug exceptions. */
3622	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3623	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3624	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3625	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3626	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3627	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3628	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3629	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3630	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3631	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3632	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3633	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3634	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3635	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3636	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3637	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3638	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3639	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3640	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3641	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3642	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3643	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3644	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3645	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3646	/** @} */
3647
3648
3649	/** @defgroup grp_hm_vmx_virt VMX virtualization.
3650	* @{
3651	*/
3652
3653	/** @name Virtual VMX MSR - Miscellaneous data.
3654	* @{ */
3655	/** Number of CR3-target values supported. */
3656	#define VMX_V_CR3_TARGET_COUNT 4
3657	/** Activity states supported. */
3658	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3659	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3660	#define VMX_V_PREEMPT_TIMER_SHIFT 5
3661	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3662	#define VMX_V_AUTOMSR_COUNT_MAX 0
3663	/** SMM MSEG revision ID. */
3664	#define VMX_V_MSEG_REV_ID 0
3665	/** @} */
3666
3667	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS launch state.
3668	* @{ */
3669	/** VMCS launch state clear. */
3670	#define VMX_V_VMCS_LAUNCH_STATE_CLEAR RT_BIT(0)
3671	/** VMCS launch state active. */
3672	#define VMX_V_VMCS_LAUNCH_STATE_ACTIVE RT_BIT(1)
3673	/** VMCS launch state current. */
3674	#define VMX_V_VMCS_LAUNCH_STATE_CURRENT RT_BIT(2)
3675	/** VMCS launch state launched. */
3676	#define VMX_V_VMCS_LAUNCH_STATE_LAUNCHED RT_BIT(3)
3677	/** The mask of valid VMCS launch states. */
3678	#define VMX_V_VMCS_LAUNCH_STATE_MASK ( VMX_V_VMCS_LAUNCH_STATE_CLEAR \
3679	\| VMX_V_VMCS_LAUNCH_STATE_ACTIVE \
3680	\| VMX_V_VMCS_LAUNCH_STATE_CURRENT \
3681	\| VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
3682	/** @} */
3683
3684	/** CR0 bits set here must always be set when in VMX operation. */
3685	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
3686	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
3687	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
3688	/** CR4 bits set here must always be set when in VMX operation. */
3689	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3690
3691	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3692	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3693	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001)
3694	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3695
3696	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3697	* complications when teleporation may be implemented). */
3698	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3699	/** The size of the virtual VMCS region (in pages). */
3700	#define VMX_V_VMCS_PAGES 1
3701
3702	/** The size of the virtual shadow VMCS region. */
3703	#define VMX_V_SHADOW_VMCS_SIZE VMX_V_VMCS_SIZE
3704	/** The size of the virtual shadow VMCS region (in pages). */
3705	#define VMX_V_SHADOW_VMCS_PAGES VMX_V_VMCS_PAGES
3706
3707	/** The size of the Virtual-APIC page (in bytes). */
3708	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3709	/** The size of the Virtual-APIC page (in pages). */
3710	#define VMX_V_VIRT_APIC_PAGES 1
3711
3712	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3713	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3714	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3715	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3716
3717	/** The size of the MSR bitmap (in bytes). */
3718	#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3719	/** The size of the MSR bitmap (in pages). */
3720	#define VMX_V_MSR_BITMAP_PAGES 1
3721
3722	/** The size of I/O bitmap A (in bytes). */
3723	#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3724	/** The size of I/O bitmap A (in pages). */
3725	#define VMX_V_IO_BITMAP_A_PAGES 1
3726
3727	/** The size of I/O bitmap B (in bytes). */
3728	#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3729	/** The size of I/O bitmap B (in pages). */
3730	#define VMX_V_IO_BITMAP_B_PAGES 1
3731
3732	/** The size of the auto-load/store MSR area (in bytes). */
3733	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3734	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3735	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3736	/** The size of the auto-load/store MSR area (in pages). */
3737	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3738
3739	/** The highest index value used for supported virtual VMCS field encoding. */
3740	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_HIGH, VMX_BF_VMCSFIELD_INDEX)
3741
3742	/**
3743	* Virtual VM-exit information.
3744	*
3745	* This is a convenience structure that bundles some VM-exit information related
3746	* fields together.
3747	*/
3748	typedef struct
3749	{
3750	/** The VM-exit reason. */
3751	uint32_t uReason;
3752	/** The VM-exit instruction length. */
3753	uint32_t cbInstr;
3754	/** The VM-exit instruction information. */
3755	VMXEXITINSTRINFO InstrInfo;
3756	/** The VM-exit instruction ID. */
3757	VMXINSTRID uInstrId;
3758
3759	/** The Exit qualification field. */
3760	uint64_t u64Qual;
3761	/** The Guest-linear address field. */
3762	uint64_t u64GuestLinearAddr;
3763	/** The Guest-physical address field. */
3764	uint64_t u64GuestPhysAddr;
3765	/** The guest pending-debug exceptions. */
3766	uint64_t u64GuestPendingDbgXcpts;
3767	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3768	* instruction VM-exit. */
3769	RTGCPTR GCPtrEffAddr;
3770	} VMXVEXITINFO;
3771	/** Pointer to the VMXVEXITINFO struct. */
3772	typedef VMXVEXITINFO *PVMXVEXITINFO;
3773	/** Pointer to a const VMXVEXITINFO struct. */
3774	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3775	AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3776
3777	/**
3778	* Virtual VM-exit information for events.
3779	*
3780	* This is a convenience structure that bundles some event-based VM-exit information
3781	* related fields together that are not included in VMXVEXITINFO.
3782	*
3783	* This is kept as a separate structure and not included in VMXVEXITINFO, to make it
3784	* easier to distinguish that IEM VM-exit handlers will set one or more of the
3785	* following fields in the virtual VMCS. Including it in the VMXVEXITINFO will not
3786	* make it ovbious which fields may get set (or cleared).
3787	*/
3788	typedef struct
3789	{
3790	/** VM-exit interruption information. */
3791	uint32_t uExitIntInfo;
3792	/** VM-exit interruption error code. */
3793	uint32_t uExitIntErrCode;
3794	/** IDT-vectoring information. */
3795	uint32_t uIdtVectoringInfo;
3796	/** IDT-vectoring error code. */
3797	uint32_t uIdtVectoringErrCode;
3798	} VMXVEXITEVENTINFO;
3799	/** Pointer to the VMXVEXITINFO2 struct. */
3800	typedef VMXVEXITEVENTINFO *PVMXVEXITEVENTINFO;
3801	/** Pointer to a const VMXVEXITINFO2 struct. */
3802	typedef const VMXVEXITEVENTINFO *PCVMXVEXITEVENTINFO;
3803
3804	/**
3805	* Virtual VMCS.
3806	*
3807	* This is our custom format. Relevant fields from this VMCS will be merged into the
3808	* actual/shadow VMCS when we execute nested-guest code using hardware-assisted
3809	* VMX.
3810	*
3811	* The first 8 bytes must be in accordance with the Intel VT-x spec.
3812	* See Intel spec. 24.2 "Format of the VMCS Region".
3813	*
3814	* The offset and size of the VMCS state field (@a fVmcsState) is also fixed (not by
3815	* the Intel spec. but for our own requirements) as we use it to offset into guest
3816	* memory.
3817	*
3818	* Although the guest is supposed to access the VMCS only through the execution of
3819	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3820	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
3821	* for teleportation purposes, any newly added fields should be added to the
3822	* appropriate reserved sections or at the end of the structure.
3823	*
3824	* We always treat natural-width fields as 64-bit in our implementation since
3825	* it's easier, allows for teleporation in the future and does not affect guest
3826	* software.
3827	*
3828	* @note Any fields that are added or modified here, make sure to update the
3829	* corresponding fields in IEM (g_aoffVmcsMap), the corresponding saved
3830	* state structure in CPUM (g_aVmxHwvirtVmcs) and bump the SSM version.
3831	* Also consider updating CPUMIsGuestVmxVmcsFieldValid and cpumR3InfoVmxVmcs.
3832	*/
3833	#pragma pack(1)
3834	typedef struct
3835	{
3836	/** @name Header.
3837	* @{
3838	*/
3839	VMXVMCSREVID u32VmcsRevId; /*< 0x000 - VMX VMCS revision identifier. /
3840	VMXABORT enmVmxAbort; /*< 0x004 - VMX-abort indicator. /
3841	uint8_t fVmcsState; /*< 0x008 - VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. /
3842	uint8_t au8Padding0[3]; /*< 0x009 - Reserved for future. /
3843	uint32_t au32Reserved0[12]; /*< 0x00c - Reserved for future. /
3844	/** @} */
3845
3846	/** @name Read-only fields.
3847	* @{ */
3848	/** 16-bit fields. */
3849	uint16_t u16Reserved0[14]; /*< 0x03c - Reserved for future. /
3850
3851	/** 32-bit fields. */
3852	uint32_t u32RoVmInstrError; /*< 0x058 - VM-instruction error. /
3853	uint32_t u32RoExitReason; /*< 0x05c - VM-exit reason. /
3854	uint32_t u32RoExitIntInfo; /*< 0x060 - VM-exit interruption information. /
3855	uint32_t u32RoExitIntErrCode; /*< 0x064 - VM-exit interruption error code. /
3856	uint32_t u32RoIdtVectoringInfo; /*< 0x068 - IDT-vectoring information. /
3857	uint32_t u32RoIdtVectoringErrCode; /*< 0x06c - IDT-vectoring error code. /
3858	uint32_t u32RoExitInstrLen; /*< 0x070 - VM-exit instruction length. /
3859	uint32_t u32RoExitInstrInfo; /*< 0x074 - VM-exit instruction information. /
3860	uint32_t au32RoReserved2[16]; /*< 0x078 - Reserved for future. /
3861
3862	/** 64-bit fields. */
3863	RTUINT64U u64RoGuestPhysAddr; /*< 0x0b8 - Guest-physical address. /
3864	RTUINT64U au64Reserved1[8]; /*< 0x0c0 - Reserved for future. /
3865
3866	/** Natural-width fields. */
3867	RTUINT64U u64RoExitQual; /*< 0x100 - Exit qualification. /
3868	RTUINT64U u64RoIoRcx; /*< 0x108 - I/O RCX. /
3869	RTUINT64U u64RoIoRsi; /*< 0x110 - I/O RSI. /
3870	RTUINT64U u64RoIoRdi; /*< 0x118 - I/O RDI. /
3871	RTUINT64U u64RoIoRip; /*< 0x120 - I/O RIP. /
3872	RTUINT64U u64RoGuestLinearAddr; /*< 0x128 - Guest-linear address. /
3873	RTUINT64U au64Reserved5[16]; /*< 0x130 - Reserved for future. /
3874	/** @} */
3875
3876	/** @name Control fields.
3877	* @{ */
3878	/** 16-bit fields. */
3879	uint16_t u16Vpid; /*< 0x1b0 - Virtual processor ID. /
3880	uint16_t u16PostIntNotifyVector; /*< 0x1b2 - Posted interrupt notify vector. /
3881	uint16_t u16EptpIndex; /*< 0x1b4 - EPTP index. /
3882	uint16_t au16Reserved0[13]; /*< 0x1b6 - Reserved for future. /
3883
3884	/** 32-bit fields. */
3885	uint32_t u32PinCtls; /*< 0x1d0 - Pin-based VM-execution controls. /
3886	uint32_t u32ProcCtls; /*< 0x1d4 - Processor-based VM-execution controls. /
3887	uint32_t u32XcptBitmap; /*< 0x1d8 - Exception bitmap. /
3888	uint32_t u32XcptPFMask; /*< 0x1dc - Page-fault exception error mask. /
3889	uint32_t u32XcptPFMatch; /*< 0x1e0 - Page-fault exception error match. /
3890	uint32_t u32Cr3TargetCount; /*< 0x1e4 - CR3-target count. /
3891	uint32_t u32ExitCtls; /*< 0x1e8 - VM-exit controls. /
3892	uint32_t u32ExitMsrStoreCount; /*< 0x1ec - VM-exit MSR store count. /
3893	uint32_t u32ExitMsrLoadCount; /*< 0x1f0 - VM-exit MSR load count. /
3894	uint32_t u32EntryCtls; /*< 0x1f4 - VM-entry controls. /
3895	uint32_t u32EntryMsrLoadCount; /*< 0x1f8 - VM-entry MSR load count. /
3896	uint32_t u32EntryIntInfo; /*< 0x1fc - VM-entry interruption information. /
3897	uint32_t u32EntryXcptErrCode; /*< 0x200 - VM-entry exception error code. /
3898	uint32_t u32EntryInstrLen; /*< 0x204 - VM-entry instruction length. /
3899	uint32_t u32TprThreshold; /*< 0x208 - TPR-threshold. /
3900	uint32_t u32ProcCtls2; /*< 0x20c - Secondary-processor based VM-execution controls. /
3901	uint32_t u32PleGap; /*< 0x210 - Pause-loop exiting Gap. /
3902	uint32_t u32PleWindow; /*< 0x214 - Pause-loop exiting Window. /
3903	uint32_t au32Reserved1[16]; /*< 0x218 - Reserved for future. /
3904
3905	/** 64-bit fields. */
3906	RTUINT64U u64AddrIoBitmapA; /*< 0x258 - I/O bitmap A address. /
3907	RTUINT64U u64AddrIoBitmapB; /*< 0x260 - I/O bitmap B address. /
3908	RTUINT64U u64AddrMsrBitmap; /*< 0x268 - MSR bitmap address. /
3909	RTUINT64U u64AddrExitMsrStore; /*< 0x270 - VM-exit MSR-store area address. /
3910	RTUINT64U u64AddrExitMsrLoad; /*< 0x278 - VM-exit MSR-load area address. /
3911	RTUINT64U u64AddrEntryMsrLoad; /*< 0x280 - VM-entry MSR-load area address. /
3912	RTUINT64U u64ExecVmcsPtr; /*< 0x288 - Executive-VMCS pointer. /
3913	RTUINT64U u64AddrPml; /*< 0x290 - Page-modification log address (PML). /
3914	RTUINT64U u64TscOffset; /*< 0x298 - TSC offset. /
3915	RTUINT64U u64AddrVirtApic; /*< 0x2a0 - Virtual-APIC address. /
3916	RTUINT64U u64AddrApicAccess; /*< 0x2a8 - APIC-access address. /
3917	RTUINT64U u64AddrPostedIntDesc; /*< 0x2b0 - Posted-interrupt descriptor address. /
3918	RTUINT64U u64VmFuncCtls; /*< 0x2b8 - VM-functions control. /
3919	RTUINT64U u64EptPtr; /*< 0x2c0 - EPT pointer. /
3920	RTUINT64U u64EoiExitBitmap0; /*< 0x2c8 - EOI-exit bitmap 0. /
3921	RTUINT64U u64EoiExitBitmap1; /*< 0x2d0 - EOI-exit bitmap 1. /
3922	RTUINT64U u64EoiExitBitmap2; /*< 0x2d8 - EOI-exit bitmap 2. /
3923	RTUINT64U u64EoiExitBitmap3; /*< 0x2e0 - EOI-exit bitmap 3. /
3924	RTUINT64U u64AddrEptpList; /*< 0x2e8 - EPTP-list address. /
3925	RTUINT64U u64AddrVmreadBitmap; /*< 0x2f0 - VMREAD-bitmap address. /
3926	RTUINT64U u64AddrVmwriteBitmap; /*< 0x2f8 - VMWRITE-bitmap address. /
3927	RTUINT64U u64AddrXcptVeInfo; /*< 0x300 - Virtualization-exception information address. /
3928	RTUINT64U u64XssExitBitmap; /*< 0x308 - XSS-exiting bitmap. /
3929	RTUINT64U u64EnclsExitBitmap; /*< 0x310 - ENCLS-exiting bitmap address. /
3930	RTUINT64U u64SppTablePtr; /*< 0x318 - Sub-page-permission-table pointer (SPPTP). /
3931	RTUINT64U u64TscMultiplier; /*< 0x320 - TSC multiplier. /
3932	RTUINT64U u64ProcCtls3; /*< 0x328 - Tertiary-Processor based VM-execution controls. /
3933	RTUINT64U u64EnclvExitBitmap; /*< 0x330 - ENCLV-exiting bitmap. /
3934	RTUINT64U au64Reserved0[13]; /*< 0x338 - Reserved for future. /
3935
3936	/** Natural-width fields. */
3937	RTUINT64U u64Cr0Mask; /*< 0x3a0 - CR0 guest/host Mask. /
3938	RTUINT64U u64Cr4Mask; /*< 0x3a8 - CR4 guest/host Mask. /
3939	RTUINT64U u64Cr0ReadShadow; /*< 0x3b0 - CR0 read shadow. /
3940	RTUINT64U u64Cr4ReadShadow; /*< 0x3b8 - CR4 read shadow. /
3941	RTUINT64U u64Cr3Target0; /*< 0x3c0 - CR3-target value 0. /
3942	RTUINT64U u64Cr3Target1; /*< 0x3c8 - CR3-target value 1. /
3943	RTUINT64U u64Cr3Target2; /*< 0x3d0 - CR3-target value 2. /
3944	RTUINT64U u64Cr3Target3; /*< 0x3d8 - CR3-target value 3. /
3945	RTUINT64U au64Reserved4[32]; /*< 0x3e0 - Reserved for future. /
3946	/** @} */
3947
3948	/** @name Host-state fields.
3949	* @{ */
3950	/** 16-bit fields. */
3951	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3952	RTSEL HostEs; /*< 0x4e0 - Host ES selector. /
3953	RTSEL HostCs; /*< 0x4e2 - Host CS selector. /
3954	RTSEL HostSs; /*< 0x4e4 - Host SS selector. /
3955	RTSEL HostDs; /*< 0x4e6 - Host DS selector. /
3956	RTSEL HostFs; /*< 0x4e8 - Host FS selector. /
3957	RTSEL HostGs; /*< 0x4ea - Host GS selector. /
3958	RTSEL HostTr; /*< 0x4ec - Host TR selector. /
3959	uint16_t au16Reserved2[13]; /*< 0x4ee - Reserved for future. /
3960
3961	/** 32-bit fields. */
3962	uint32_t u32HostSysenterCs; /*< 0x508 - Host SYSENTER CS. /
3963	uint32_t au32Reserved4[11]; /*< 0x50c - Reserved for future. /
3964
3965	/** 64-bit fields. */
3966	RTUINT64U u64HostPatMsr; /*< 0x538 - Host PAT MSR. /
3967	RTUINT64U u64HostEferMsr; /*< 0x540 - Host EFER MSR. /
3968	RTUINT64U u64HostPerfGlobalCtlMsr; /*< 0x548 - Host global performance-control MSR. /
3969	RTUINT64U u64HostPkrsMsr; /*< 0x550 - Host PKRS MSR. /
3970	RTUINT64U au64Reserved3[15]; /*< 0x558 - Reserved for future. /
3971
3972	/** Natural-width fields. */
3973	RTUINT64U u64HostCr0; /*< 0x5d0 - Host CR0. /
3974	RTUINT64U u64HostCr3; /*< 0x5d8 - Host CR3. /
3975	RTUINT64U u64HostCr4; /*< 0x5e0 - Host CR4. /
3976	RTUINT64U u64HostFsBase; /*< 0x5e8 - Host FS base. /
3977	RTUINT64U u64HostGsBase; /*< 0x5f0 - Host GS base. /
3978	RTUINT64U u64HostTrBase; /*< 0x5f8 - Host TR base. /
3979	RTUINT64U u64HostGdtrBase; /*< 0x600 - Host GDTR base. /
3980	RTUINT64U u64HostIdtrBase; /*< 0x608 - Host IDTR base. /
3981	RTUINT64U u64HostSysenterEsp; /*< 0x610 - Host SYSENTER ESP base. /
3982	RTUINT64U u64HostSysenterEip; /*< 0x618 - Host SYSENTER ESP base. /
3983	RTUINT64U u64HostRsp; /*< 0x620 - Host RSP. /
3984	RTUINT64U u64HostRip; /*< 0x628 - Host RIP. /
3985	RTUINT64U u64HostSCetMsr; /*< 0x630 - Host S_CET MSR. /
3986	RTUINT64U u64HostSsp; /*< 0x638 - Host SSP. /
3987	RTUINT64U u64HostIntrSspTableAddrMsr; /*< 0x640 - Host Interrupt SSP table address MSR. /
3988	RTUINT64U au64Reserved7[29]; /*< 0x648 - Reserved for future. /
3989	/** @} */
3990
3991	/** @name Guest-state fields.
3992	* @{ */
3993	/** 16-bit fields. */
3994	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3995	RTSEL GuestEs; /*< 0x730 - Guest ES selector. /
3996	RTSEL GuestCs; /*< 0x732 - Guest ES selector. /
3997	RTSEL GuestSs; /*< 0x734 - Guest ES selector. /
3998	RTSEL GuestDs; /*< 0x736 - Guest ES selector. /
3999	RTSEL GuestFs; /*< 0x738 - Guest ES selector. /
4000	RTSEL GuestGs; /*< 0x73a - Guest ES selector. /
4001	RTSEL GuestLdtr; /*< 0x73c - Guest LDTR selector. /
4002	RTSEL GuestTr; /*< 0x73e - Guest TR selector. /
4003	uint16_t u16GuestIntStatus; /*< 0x740 - Guest interrupt status (virtual-interrupt delivery). /
4004	uint16_t u16PmlIndex; /*< 0x742 - PML index. /
4005	uint16_t au16Reserved1[14]; /*< 0x744 - Reserved for future. /
4006
4007	/** 32-bit fields. */
4008	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
4009	uint32_t u32GuestEsLimit; /*< 0x760 - Guest ES limit. /
4010	uint32_t u32GuestCsLimit; /*< 0x764 - Guest CS limit. /
4011	uint32_t u32GuestSsLimit; /*< 0x768 - Guest SS limit. /
4012	uint32_t u32GuestDsLimit; /*< 0x76c - Guest DS limit. /
4013	uint32_t u32GuestFsLimit; /*< 0x770 - Guest FS limit. /
4014	uint32_t u32GuestGsLimit; /*< 0x774 - Guest GS limit. /
4015	uint32_t u32GuestLdtrLimit; /*< 0x778 - Guest LDTR limit. /
4016	uint32_t u32GuestTrLimit; /*< 0x77c - Guest TR limit. /
4017	uint32_t u32GuestGdtrLimit; /*< 0x780 - Guest GDTR limit. /
4018	uint32_t u32GuestIdtrLimit; /*< 0x784 - Guest IDTR limit. /
4019	uint32_t u32GuestEsAttr; /*< 0x788 - Guest ES attributes. /
4020	uint32_t u32GuestCsAttr; /*< 0x78c - Guest CS attributes. /
4021	uint32_t u32GuestSsAttr; /*< 0x790 - Guest SS attributes. /
4022	uint32_t u32GuestDsAttr; /*< 0x794 - Guest DS attributes. /
4023	uint32_t u32GuestFsAttr; /*< 0x798 - Guest FS attributes. /
4024	uint32_t u32GuestGsAttr; /*< 0x79c - Guest GS attributes. /
4025	uint32_t u32GuestLdtrAttr; /*< 0x7a0 - Guest LDTR attributes. /
4026	uint32_t u32GuestTrAttr; /*< 0x7a4 - Guest TR attributes. /
4027	uint32_t u32GuestIntrState; /*< 0x7a8 - Guest interruptibility state. /
4028	uint32_t u32GuestActivityState; /*< 0x7ac - Guest activity state. /
4029	uint32_t u32GuestSmBase; /*< 0x7b0 - Guest SMBASE. /
4030	uint32_t u32GuestSysenterCS; /*< 0x7b4 - Guest SYSENTER CS. /
4031	uint32_t u32PreemptTimer; /*< 0x7b8 - Preemption timer value. /
4032	uint32_t au32Reserved3[11]; /*< 0x7bc - Reserved for future. /
4033
4034	/** 64-bit fields. */
4035	RTUINT64U u64VmcsLinkPtr; /*< 0x7e8 - VMCS link pointer. /
4036	RTUINT64U u64GuestDebugCtlMsr; /*< 0x7f0 - Guest debug-control MSR. /
4037	RTUINT64U u64GuestPatMsr; /*< 0x7f8 - Guest PAT MSR. /
4038	RTUINT64U u64GuestEferMsr; /*< 0x800 - Guest EFER MSR. /
4039	RTUINT64U u64GuestPerfGlobalCtlMsr; /*< 0x808 - Guest global performance-control MSR. /
4040	RTUINT64U u64GuestPdpte0; /*< 0x810 - Guest PDPTE 0. /
4041	RTUINT64U u64GuestPdpte1; /*< 0x818 - Guest PDPTE 0. /
4042	RTUINT64U u64GuestPdpte2; /*< 0x820 - Guest PDPTE 1. /
4043	RTUINT64U u64GuestPdpte3; /*< 0x828 - Guest PDPTE 2. /
4044	RTUINT64U u64GuestBndcfgsMsr; /*< 0x830 - Guest Bounds config MPX MSR (Intel Memory Protection Extensions). /
4045	RTUINT64U u64GuestRtitCtlMsr; /*< 0x838 - Guest RTIT control MSR (Intel Real Time Instruction Trace). /
4046	RTUINT64U u64GuestPkrsMsr; /*< 0x840 - Guest PKRS MSR. /
4047	RTUINT64U au64Reserved2[31]; /*< 0x848 - Reserved for future. /
4048
4049	/** Natural-width fields. */
4050	RTUINT64U u64GuestCr0; /*< 0x940 - Guest CR0. /
4051	RTUINT64U u64GuestCr3; /*< 0x948 - Guest CR3. /
4052	RTUINT64U u64GuestCr4; /*< 0x950 - Guest CR4. /
4053	RTUINT64U u64GuestEsBase; /*< 0x958 - Guest ES base. /
4054	RTUINT64U u64GuestCsBase; /*< 0x960 - Guest CS base. /
4055	RTUINT64U u64GuestSsBase; /*< 0x968 - Guest SS base. /
4056	RTUINT64U u64GuestDsBase; /*< 0x970 - Guest DS base. /
4057	RTUINT64U u64GuestFsBase; /*< 0x978 - Guest FS base. /
4058	RTUINT64U u64GuestGsBase; /*< 0x980 - Guest GS base. /
4059	RTUINT64U u64GuestLdtrBase; /*< 0x988 - Guest LDTR base. /
4060	RTUINT64U u64GuestTrBase; /*< 0x990 - Guest TR base. /
4061	RTUINT64U u64GuestGdtrBase; /*< 0x998 - Guest GDTR base. /
4062	RTUINT64U u64GuestIdtrBase; /*< 0x9a0 - Guest IDTR base. /
4063	RTUINT64U u64GuestDr7; /*< 0x9a8 - Guest DR7. /
4064	RTUINT64U u64GuestRsp; /*< 0x9b0 - Guest RSP. /
4065	RTUINT64U u64GuestRip; /*< 0x9b8 - Guest RIP. /
4066	RTUINT64U u64GuestRFlags; /*< 0x9c0 - Guest RFLAGS. /
4067	RTUINT64U u64GuestPendingDbgXcpts; /*< 0x9c8 - Guest pending debug exceptions. /
4068	RTUINT64U u64GuestSysenterEsp; /*< 0x9d0 - Guest SYSENTER ESP. /
4069	RTUINT64U u64GuestSysenterEip; /*< 0x9d8 - Guest SYSENTER EIP. /
4070	RTUINT64U u64GuestSCetMsr; /*< 0x9e0 - Guest S_CET MSR. /
4071	RTUINT64U u64GuestSsp; /*< 0x9e8 - Guest SSP. /
4072	RTUINT64U u64GuestIntrSspTableAddrMsr; /*< 0x9f0 - Guest Interrupt SSP table address MSR. /
4073	RTUINT64U au64Reserved6[29]; /*< 0x9f8 - Reserved for future. /
4074	/** @} */
4075
4076	/** 0xae0 - Padding / reserved for future use. */
4077	uint8_t abPadding[X86_PAGE_4K_SIZE - 0xae0];
4078	} VMXVVMCS;
4079	#pragma pack()
4080	/** Pointer to the VMXVVMCS struct. */
4081	typedef VMXVVMCS *PVMXVVMCS;
4082	/** Pointer to a const VMXVVMCS struct. */
4083	typedef const VMXVVMCS *PCVMXVVMCS;
4084	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
4085	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
4086	AssertCompileMemberOffset(VMXVVMCS, enmVmxAbort, 0x004);
4087	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
4088	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x058);
4089	AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x0b8);
4090	AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x100);
4091	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x1b0);
4092	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x1d0);
4093	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x258);
4094	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x3a0);
4095	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x4e0);
4096	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x508);
4097	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x538);
4098	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x5d0);
4099	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x730);
4100	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x760);
4101	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x7e8);
4102	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x940);
4103
4104	/**
4105	* Virtual VMX-instruction and VM-exit diagnostics.
4106	*
4107	* These are not the same as VM instruction errors that are enumerated in the Intel
4108	* spec. These are purely internal, fine-grained definitions used for diagnostic
4109	* purposes and are not reported to guest software under the VM-instruction error
4110	* field in its VMCS.
4111	*
4112	* @note Members of this enum are used as array indices, so no gaps are allowed.
4113	* Please update g_apszVmxVDiagDesc when you add new fields to this enum.
4114	*/
4115	typedef enum
4116	{
4117	/* Internal processing errors. */
4118	kVmxVDiag_None = 0,
4119	kVmxVDiag_Ipe_1,
4120	kVmxVDiag_Ipe_2,
4121	kVmxVDiag_Ipe_3,
4122	kVmxVDiag_Ipe_4,
4123	kVmxVDiag_Ipe_5,
4124	kVmxVDiag_Ipe_6,
4125	kVmxVDiag_Ipe_7,
4126	kVmxVDiag_Ipe_8,
4127	kVmxVDiag_Ipe_9,
4128	kVmxVDiag_Ipe_10,
4129	kVmxVDiag_Ipe_11,
4130	kVmxVDiag_Ipe_12,
4131	kVmxVDiag_Ipe_13,
4132	kVmxVDiag_Ipe_14,
4133	kVmxVDiag_Ipe_15,
4134	kVmxVDiag_Ipe_16,
4135	/* VMXON. */
4136	kVmxVDiag_Vmxon_A20M,
4137	kVmxVDiag_Vmxon_Cpl,
4138	kVmxVDiag_Vmxon_Cr0Fixed0,
4139	kVmxVDiag_Vmxon_Cr0Fixed1,
4140	kVmxVDiag_Vmxon_Cr4Fixed0,
4141	kVmxVDiag_Vmxon_Cr4Fixed1,
4142	kVmxVDiag_Vmxon_Intercept,
4143	kVmxVDiag_Vmxon_LongModeCS,
4144	kVmxVDiag_Vmxon_MsrFeatCtl,
4145	kVmxVDiag_Vmxon_PtrAbnormal,
4146	kVmxVDiag_Vmxon_PtrAlign,
4147	kVmxVDiag_Vmxon_PtrMap,
4148	kVmxVDiag_Vmxon_PtrReadPhys,
4149	kVmxVDiag_Vmxon_PtrWidth,
4150	kVmxVDiag_Vmxon_RealOrV86Mode,
4151	kVmxVDiag_Vmxon_ShadowVmcs,
4152	kVmxVDiag_Vmxon_VmxAlreadyRoot,
4153	kVmxVDiag_Vmxon_Vmxe,
4154	kVmxVDiag_Vmxon_VmcsRevId,
4155	kVmxVDiag_Vmxon_VmxRootCpl,
4156	/* VMXOFF. */
4157	kVmxVDiag_Vmxoff_Cpl,
4158	kVmxVDiag_Vmxoff_Intercept,
4159	kVmxVDiag_Vmxoff_LongModeCS,
4160	kVmxVDiag_Vmxoff_RealOrV86Mode,
4161	kVmxVDiag_Vmxoff_Vmxe,
4162	kVmxVDiag_Vmxoff_VmxRoot,
4163	/* VMPTRLD. */
4164	kVmxVDiag_Vmptrld_Cpl,
4165	kVmxVDiag_Vmptrld_LongModeCS,
4166	kVmxVDiag_Vmptrld_PtrAbnormal,
4167	kVmxVDiag_Vmptrld_PtrAlign,
4168	kVmxVDiag_Vmptrld_PtrMap,
4169	kVmxVDiag_Vmptrld_PtrReadPhys,
4170	kVmxVDiag_Vmptrld_PtrVmxon,
4171	kVmxVDiag_Vmptrld_PtrWidth,
4172	kVmxVDiag_Vmptrld_RealOrV86Mode,
4173	kVmxVDiag_Vmptrld_RevPtrReadPhys,
4174	kVmxVDiag_Vmptrld_ShadowVmcs,
4175	kVmxVDiag_Vmptrld_VmcsRevId,
4176	kVmxVDiag_Vmptrld_VmxRoot,
4177	/* VMPTRST. */
4178	kVmxVDiag_Vmptrst_Cpl,
4179	kVmxVDiag_Vmptrst_LongModeCS,
4180	kVmxVDiag_Vmptrst_PtrMap,
4181	kVmxVDiag_Vmptrst_RealOrV86Mode,
4182	kVmxVDiag_Vmptrst_VmxRoot,
4183	/* VMCLEAR. */
4184	kVmxVDiag_Vmclear_Cpl,
4185	kVmxVDiag_Vmclear_LongModeCS,
4186	kVmxVDiag_Vmclear_PtrAbnormal,
4187	kVmxVDiag_Vmclear_PtrAlign,
4188	kVmxVDiag_Vmclear_PtrMap,
4189	kVmxVDiag_Vmclear_PtrReadPhys,
4190	kVmxVDiag_Vmclear_PtrVmxon,
4191	kVmxVDiag_Vmclear_PtrWidth,
4192	kVmxVDiag_Vmclear_RealOrV86Mode,
4193	kVmxVDiag_Vmclear_VmxRoot,
4194	/* VMWRITE. */
4195	kVmxVDiag_Vmwrite_Cpl,
4196	kVmxVDiag_Vmwrite_FieldInvalid,
4197	kVmxVDiag_Vmwrite_FieldRo,
4198	kVmxVDiag_Vmwrite_LinkPtrInvalid,
4199	kVmxVDiag_Vmwrite_LongModeCS,
4200	kVmxVDiag_Vmwrite_PtrInvalid,
4201	kVmxVDiag_Vmwrite_PtrMap,
4202	kVmxVDiag_Vmwrite_RealOrV86Mode,
4203	kVmxVDiag_Vmwrite_VmxRoot,
4204	/* VMREAD. */
4205	kVmxVDiag_Vmread_Cpl,
4206	kVmxVDiag_Vmread_FieldInvalid,
4207	kVmxVDiag_Vmread_LinkPtrInvalid,
4208	kVmxVDiag_Vmread_LongModeCS,
4209	kVmxVDiag_Vmread_PtrInvalid,
4210	kVmxVDiag_Vmread_PtrMap,
4211	kVmxVDiag_Vmread_RealOrV86Mode,
4212	kVmxVDiag_Vmread_VmxRoot,
4213	/* INVVPID. */
4214	kVmxVDiag_Invvpid_Cpl,
4215	kVmxVDiag_Invvpid_DescRsvd,
4216	kVmxVDiag_Invvpid_LongModeCS,
4217	kVmxVDiag_Invvpid_RealOrV86Mode,
4218	kVmxVDiag_Invvpid_TypeInvalid,
4219	kVmxVDiag_Invvpid_Type0InvalidAddr,
4220	kVmxVDiag_Invvpid_Type0InvalidVpid,
4221	kVmxVDiag_Invvpid_Type1InvalidVpid,
4222	kVmxVDiag_Invvpid_Type3InvalidVpid,
4223	kVmxVDiag_Invvpid_VmxRoot,
4224	/* VMLAUNCH/VMRESUME. */
4225	kVmxVDiag_Vmentry_AddrApicAccess,
4226	kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
4227	kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
4228	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
4229	kVmxVDiag_Vmentry_AddrExitMsrLoad,
4230	kVmxVDiag_Vmentry_AddrExitMsrStore,
4231	kVmxVDiag_Vmentry_AddrIoBitmapA,
4232	kVmxVDiag_Vmentry_AddrIoBitmapB,
4233	kVmxVDiag_Vmentry_AddrMsrBitmap,
4234	kVmxVDiag_Vmentry_AddrVirtApicPage,
4235	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
4236	kVmxVDiag_Vmentry_AddrVmreadBitmap,
4237	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
4238	kVmxVDiag_Vmentry_ApicRegVirt,
4239	kVmxVDiag_Vmentry_BlocKMovSS,
4240	kVmxVDiag_Vmentry_Cpl,
4241	kVmxVDiag_Vmentry_Cr3TargetCount,
4242	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
4243	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
4244	kVmxVDiag_Vmentry_EntryInstrLen,
4245	kVmxVDiag_Vmentry_EntryInstrLenZero,
4246	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
4247	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
4248	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
4249	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
4250	kVmxVDiag_Vmentry_EptpAccessDirty,
4251	kVmxVDiag_Vmentry_EptpPageWalkLength,
4252	kVmxVDiag_Vmentry_EptpMemType,
4253	kVmxVDiag_Vmentry_EptpRsvd,
4254	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
4255	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
4256	kVmxVDiag_Vmentry_GuestActStateHlt,
4257	kVmxVDiag_Vmentry_GuestActStateRsvd,
4258	kVmxVDiag_Vmentry_GuestActStateShutdown,
4259	kVmxVDiag_Vmentry_GuestActStateSsDpl,
4260	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
4261	kVmxVDiag_Vmentry_GuestCr0Fixed0,
4262	kVmxVDiag_Vmentry_GuestCr0Fixed1,
4263	kVmxVDiag_Vmentry_GuestCr0PgPe,
4264	kVmxVDiag_Vmentry_GuestCr3,
4265	kVmxVDiag_Vmentry_GuestCr4Fixed0,
4266	kVmxVDiag_Vmentry_GuestCr4Fixed1,
4267	kVmxVDiag_Vmentry_GuestDebugCtl,
4268	kVmxVDiag_Vmentry_GuestDr7,
4269	kVmxVDiag_Vmentry_GuestEferMsr,
4270	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
4271	kVmxVDiag_Vmentry_GuestGdtrBase,
4272	kVmxVDiag_Vmentry_GuestGdtrLimit,
4273	kVmxVDiag_Vmentry_GuestIdtrBase,
4274	kVmxVDiag_Vmentry_GuestIdtrLimit,
4275	kVmxVDiag_Vmentry_GuestIntStateEnclave,
4276	kVmxVDiag_Vmentry_GuestIntStateExtInt,
4277	kVmxVDiag_Vmentry_GuestIntStateNmi,
4278	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
4279	kVmxVDiag_Vmentry_GuestIntStateRsvd,
4280	kVmxVDiag_Vmentry_GuestIntStateSmi,
4281	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
4282	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
4283	kVmxVDiag_Vmentry_GuestPae,
4284	kVmxVDiag_Vmentry_GuestPatMsr,
4285	kVmxVDiag_Vmentry_GuestPcide,
4286	kVmxVDiag_Vmentry_GuestPdpte,
4287	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
4288	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
4289	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
4290	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
4291	kVmxVDiag_Vmentry_GuestRip,
4292	kVmxVDiag_Vmentry_GuestRipRsvd,
4293	kVmxVDiag_Vmentry_GuestRFlagsIf,
4294	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
4295	kVmxVDiag_Vmentry_GuestRFlagsVm,
4296	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
4297	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
4298	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
4299	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
4300	kVmxVDiag_Vmentry_GuestSegAttrCsType,
4301	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
4302	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
4303	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
4304	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
4305	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
4306	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
4307	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
4308	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
4309	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
4310	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
4311	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
4312	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
4313	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
4314	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
4315	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
4316	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
4317	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
4318	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
4319	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
4320	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
4321	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
4322	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
4323	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
4324	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
4325	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
4326	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
4327	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
4328	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
4329	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
4330	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
4331	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
4332	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
4333	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
4334	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
4335	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
4336	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
4337	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
4338	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
4339	kVmxVDiag_Vmentry_GuestSegAttrSsType,
4340	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
4341	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
4342	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
4343	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
4344	kVmxVDiag_Vmentry_GuestSegAttrTrType,
4345	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
4346	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
4347	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
4348	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
4349	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
4350	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
4351	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
4352	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
4353	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
4354	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
4355	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
4356	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
4357	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
4358	kVmxVDiag_Vmentry_GuestSegBaseCs,
4359	kVmxVDiag_Vmentry_GuestSegBaseDs,
4360	kVmxVDiag_Vmentry_GuestSegBaseEs,
4361	kVmxVDiag_Vmentry_GuestSegBaseFs,
4362	kVmxVDiag_Vmentry_GuestSegBaseGs,
4363	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
4364	kVmxVDiag_Vmentry_GuestSegBaseSs,
4365	kVmxVDiag_Vmentry_GuestSegBaseTr,
4366	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
4367	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
4368	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
4369	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
4370	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
4371	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
4372	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
4373	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
4374	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
4375	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
4376	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
4377	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
4378	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
4379	kVmxVDiag_Vmentry_GuestSegSelLdtr,
4380	kVmxVDiag_Vmentry_GuestSegSelTr,
4381	kVmxVDiag_Vmentry_GuestSysenterEspEip,
4382	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
4383	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
4384	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
4385	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
4386	kVmxVDiag_Vmentry_HostCr0Fixed0,
4387	kVmxVDiag_Vmentry_HostCr0Fixed1,
4388	kVmxVDiag_Vmentry_HostCr3,
4389	kVmxVDiag_Vmentry_HostCr4Fixed0,
4390	kVmxVDiag_Vmentry_HostCr4Fixed1,
4391	kVmxVDiag_Vmentry_HostCr4Pae,
4392	kVmxVDiag_Vmentry_HostCr4Pcide,
4393	kVmxVDiag_Vmentry_HostCsTr,
4394	kVmxVDiag_Vmentry_HostEferMsr,
4395	kVmxVDiag_Vmentry_HostEferMsrRsvd,
4396	kVmxVDiag_Vmentry_HostGuestLongMode,
4397	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4398	kVmxVDiag_Vmentry_HostLongMode,
4399	kVmxVDiag_Vmentry_HostPatMsr,
4400	kVmxVDiag_Vmentry_HostRip,
4401	kVmxVDiag_Vmentry_HostRipRsvd,
4402	kVmxVDiag_Vmentry_HostSel,
4403	kVmxVDiag_Vmentry_HostSegBase,
4404	kVmxVDiag_Vmentry_HostSs,
4405	kVmxVDiag_Vmentry_HostSysenterEspEip,
4406	kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys,
4407	kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys,
4408	kVmxVDiag_Vmentry_LongModeCS,
4409	kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4410	kVmxVDiag_Vmentry_MsrLoad,
4411	kVmxVDiag_Vmentry_MsrLoadCount,
4412	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4413	kVmxVDiag_Vmentry_MsrLoadRing3,
4414	kVmxVDiag_Vmentry_MsrLoadRsvd,
4415	kVmxVDiag_Vmentry_NmiWindowExit,
4416	kVmxVDiag_Vmentry_PinCtlsAllowed1,
4417	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4418	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4419	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4420	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4421	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4422	kVmxVDiag_Vmentry_PtrInvalid,
4423	kVmxVDiag_Vmentry_PtrShadowVmcs,
4424	kVmxVDiag_Vmentry_RealOrV86Mode,
4425	kVmxVDiag_Vmentry_SavePreemptTimer,
4426	kVmxVDiag_Vmentry_TprThresholdRsvd,
4427	kVmxVDiag_Vmentry_TprThresholdVTpr,
4428	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4429	kVmxVDiag_Vmentry_VirtIntDelivery,
4430	kVmxVDiag_Vmentry_VirtNmi,
4431	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4432	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4433	kVmxVDiag_Vmentry_VmcsClear,
4434	kVmxVDiag_Vmentry_VmcsLaunch,
4435	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4436	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4437	kVmxVDiag_Vmentry_VmxRoot,
4438	kVmxVDiag_Vmentry_Vpid,
4439	kVmxVDiag_Vmexit_HostPdpte,
4440	kVmxVDiag_Vmexit_MsrLoad,
4441	kVmxVDiag_Vmexit_MsrLoadCount,
4442	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4443	kVmxVDiag_Vmexit_MsrLoadRing3,
4444	kVmxVDiag_Vmexit_MsrLoadRsvd,
4445	kVmxVDiag_Vmexit_MsrStore,
4446	kVmxVDiag_Vmexit_MsrStoreCount,
4447	kVmxVDiag_Vmexit_MsrStorePtrReadPhys,
4448	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4449	kVmxVDiag_Vmexit_MsrStoreRing3,
4450	kVmxVDiag_Vmexit_MsrStoreRsvd,
4451	kVmxVDiag_Vmexit_VirtApicPagePtrWritePhys,
4452	/* Last member for determining array index limit. */
4453	kVmxVDiag_End
4454	} VMXVDIAG;
4455	AssertCompileSize(VMXVDIAG, 4);
4456
4457	/** @} */
4458
4459	/** @} */
4460
4461	#endif /* !VBOX_INCLUDED_vmm_hm_vmx_h */
4462

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 92585

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