| 1 | /** @file
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| 2 | * IEM - Interpreted Execution Manager.
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2011-2017 Oracle Corporation
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| 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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| 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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| 24 | */
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| 25 |
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| 26 | #ifndef ___VBox_vmm_iem_h
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| 27 | #define ___VBox_vmm_iem_h
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| 28 |
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| 29 | #include <VBox/types.h>
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| 30 | #include <VBox/vmm/trpm.h>
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| 31 | #include <iprt/assert.h>
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| 32 |
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| 33 |
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| 34 | RT_C_DECLS_BEGIN
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| 35 |
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| 36 | /** @defgroup grp_iem The Interpreted Execution Manager API.
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| 37 | * @ingroup grp_vmm
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| 38 | * @{
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| 39 | */
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| 40 |
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| 41 | /** @name IEMXCPTRAISEINFO_XXX - Extra info. on a recursive exception situation.
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| 42 | *
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| 43 | * This is primarily used by HM for working around a PGM limitation (see
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| 44 | * @bugref{6607}) and special NMI/IRET handling. In the future, this may be
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| 45 | * used for diagnostics.
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| 46 | *
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| 47 | * @{
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| 48 | */
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| 49 | typedef uint32_t IEMXCPTRAISEINFO;
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| 50 | /** Pointer to a IEMXCPTINFO type. */
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| 51 | typedef IEMXCPTRAISEINFO *PIEMXCPTRAISEINFO;
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| 52 | /** No addition info. available. */
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| 53 | #define IEMXCPTRAISEINFO_NONE RT_BIT_32(0)
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| 54 | /** Delivery of a \#AC caused another \#AC. */
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| 55 | #define IEMXCPTRAISEINFO_AC_AC RT_BIT_32(1)
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| 56 | /** Delivery of a \#PF caused another \#PF. */
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| 57 | #define IEMXCPTRAISEINFO_PF_PF RT_BIT_32(2)
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| 58 | /** Delivery of a \#PF caused some contributory exception. */
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| 59 | #define IEMXCPTRAISEINFO_PF_CONTRIBUTORY_XCPT RT_BIT_32(3)
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| 60 | /** Delivery of an external interrupt caused an exception. */
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| 61 | #define IEMXCPTRAISEINFO_EXT_INT_XCPT RT_BIT_32(4)
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| 62 | /** Delivery of an external interrupt caused an \#PF. */
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| 63 | #define IEMXCPTRAISEINFO_EXT_INT_PF RT_BIT_32(5)
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| 64 | /** Delivery of a software interrupt caused an exception. */
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| 65 | #define IEMXCPTRAISEINFO_SOFT_INT_XCPT RT_BIT_32(6)
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| 66 | /** Delivery of an NMI caused an exception. */
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| 67 | #define IEMXCPTRAISEINFO_NMI_XCPT RT_BIT_32(7)
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| 68 | /** Delivery of an NMI caused a \#PF. */
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| 69 | #define IEMXCPTRAISEINFO_NMI_PF RT_BIT_32(8)
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| 70 | /** Can re-execute the instruction at CS:RIP. */
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| 71 | #define IEMXCPTRAISEINFO_CAN_REEXEC_INSTR RT_BIT_32(9)
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| 72 | /** @} */
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| 73 |
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| 74 |
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| 75 | /** @name IEMXCPTRAISE_XXX - Ways to handle a recursive exception condition.
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| 76 | * @{ */
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| 77 | typedef enum IEMXCPTRAISE
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| 78 | {
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| 79 | /** Raise the current (second) exception. */
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| 80 | IEMXCPTRAISE_CURRENT_XCPT = 0,
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| 81 | /** Re-raise the previous (first) event (for HM, unused by IEM). */
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| 82 | IEMXCPTRAISE_PREV_EVENT,
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| 83 | /** Re-execute instruction at CS:RIP (for HM, unused by IEM). */
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| 84 | IEMXCPTRAISE_REEXEC_INSTR,
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| 85 | /** Raise a \#DF exception. */
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| 86 | IEMXCPTRAISE_DOUBLE_FAULT,
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| 87 | /** Raise a triple fault. */
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| 88 | IEMXCPTRAISE_TRIPLE_FAULT,
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| 89 | /** Cause a CPU hang. */
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| 90 | IEMXCPTRAISE_CPU_HANG,
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| 91 | /** Invalid sequence of events. */
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| 92 | IEMXCPTRAISE_INVALID = 0x7fffffff
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| 93 | } IEMXCPTRAISE;
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| 94 | /** Pointer to a IEMXCPTRAISE type. */
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| 95 | typedef IEMXCPTRAISE *PIEMXCPTRAISE;
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| 96 | /** @} */
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| 97 |
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| 98 |
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| 99 | /** @name Operand or addressing mode.
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| 100 | * @{ */
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| 101 | typedef uint8_t IEMMODE;
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| 102 | #define IEMMODE_16BIT 0
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| 103 | #define IEMMODE_32BIT 1
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| 104 | #define IEMMODE_64BIT 2
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| 105 | /** @} */
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| 106 |
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| 107 |
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| 108 | /** @name IEM_XCPT_FLAGS_XXX - flags for iemRaiseXcptOrInt.
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| 109 | * @{ */
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| 110 | /** CPU exception. */
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| 111 | #define IEM_XCPT_FLAGS_T_CPU_XCPT RT_BIT_32(0)
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| 112 | /** External interrupt (from PIC, APIC, whatever). */
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| 113 | #define IEM_XCPT_FLAGS_T_EXT_INT RT_BIT_32(1)
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| 114 | /** Software interrupt (int or into, not bound).
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| 115 | * Returns to the following instruction */
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| 116 | #define IEM_XCPT_FLAGS_T_SOFT_INT RT_BIT_32(2)
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| 117 | /** Takes an error code. */
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| 118 | #define IEM_XCPT_FLAGS_ERR RT_BIT_32(3)
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| 119 | /** Takes a CR2. */
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| 120 | #define IEM_XCPT_FLAGS_CR2 RT_BIT_32(4)
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| 121 | /** Generated by the breakpoint instruction. */
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| 122 | #define IEM_XCPT_FLAGS_BP_INSTR RT_BIT_32(5)
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| 123 | /** Generated by a DRx instruction breakpoint and RF should be cleared. */
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| 124 | #define IEM_XCPT_FLAGS_DRx_INSTR_BP RT_BIT_32(6)
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| 125 | /** Generated by the icebp instruction. */
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| 126 | #define IEM_XCPT_FLAGS_ICEBP_INSTR RT_BIT_32(7)
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| 127 | /** Generated by the overflow instruction. */
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| 128 | #define IEM_XCPT_FLAGS_OF_INSTR RT_BIT_32(8)
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| 129 | /** @} */
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| 130 |
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| 131 |
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| 132 | /** @name IEMTARGETCPU_XXX - IEM target CPU specification.
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| 133 | *
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| 134 | * This is a gross simpliciation of CPUMMICROARCH for dealing with really old
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| 135 | * CPUs which didn't have much in the way of hinting at supported instructions
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| 136 | * and features. This slowly changes with the introduction of CPUID with the
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| 137 | * Intel Pentium.
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| 138 | *
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| 139 | * @{
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| 140 | */
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| 141 | /** The dynamic target CPU mode is for getting thru the BIOS and then use
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| 142 | * the debugger or modifying instruction behaviour (e.g. HLT) to switch to a
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| 143 | * different target CPU. */
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| 144 | #define IEMTARGETCPU_DYNAMIC UINT32_C(0)
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| 145 | /** Intel 8086/8088. */
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| 146 | #define IEMTARGETCPU_8086 UINT32_C(1)
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| 147 | /** NEC V20/V30.
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| 148 | * @remarks must be between 8086 and 80186. */
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| 149 | #define IEMTARGETCPU_V20 UINT32_C(2)
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| 150 | /** Intel 80186/80188. */
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| 151 | #define IEMTARGETCPU_186 UINT32_C(3)
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| 152 | /** Intel 80286. */
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| 153 | #define IEMTARGETCPU_286 UINT32_C(4)
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| 154 | /** Intel 80386. */
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| 155 | #define IEMTARGETCPU_386 UINT32_C(5)
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| 156 | /** Intel 80486. */
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| 157 | #define IEMTARGETCPU_486 UINT32_C(6)
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| 158 | /** Intel Pentium . */
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| 159 | #define IEMTARGETCPU_PENTIUM UINT32_C(7)
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| 160 | /** Intel PentiumPro. */
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| 161 | #define IEMTARGETCPU_PPRO UINT32_C(8)
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| 162 | /** A reasonably current CPU, probably newer than the pentium pro when it comes
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| 163 | * to the feature set and behaviour. Generally the CPUID info and CPU vendor
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| 164 | * dicates the behaviour here. */
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| 165 | #define IEMTARGETCPU_CURRENT UINT32_C(9)
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| 166 | /** @} */
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| 167 |
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| 168 |
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| 169 | /** @name IEM status codes.
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| 170 | *
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| 171 | * Not quite sure how this will play out in the end, just aliasing safe status
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| 172 | * codes for now.
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| 173 | *
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| 174 | * @{ */
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| 175 | #define VINF_IEM_RAISED_XCPT VINF_EM_RESCHEDULE
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| 176 | /** @} */
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| 177 |
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| 178 |
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| 179 | /** The CPUMCTX_EXTRN_XXX mask required to be cleared when interpreting anything.
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| 180 | * IEM will ASSUME the caller of IEM APIs has ensured these are already present. */
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| 181 | #define IEM_CPUMCTX_EXTRN_MUST_MASK ( CPUMCTX_EXTRN_GPRS_MASK \
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| 182 | | CPUMCTX_EXTRN_RIP \
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| 183 | | CPUMCTX_EXTRN_RFLAGS \
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| 184 | | CPUMCTX_EXTRN_SS \
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| 185 | | CPUMCTX_EXTRN_CS \
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| 186 | | CPUMCTX_EXTRN_CR0 \
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| 187 | | CPUMCTX_EXTRN_CR3 \
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| 188 | | CPUMCTX_EXTRN_CR4 \
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| 189 | | CPUMCTX_EXTRN_APIC_TPR \
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| 190 | | CPUMCTX_EXTRN_EFER \
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| 191 | | CPUMCTX_EXTRN_DR7 )
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| 192 | /** The CPUMCTX_EXTRN_XXX mask needed when injecting an exception/interrupt.
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| 193 | * IEM will import missing bits, callers are encouraged to make these registers
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| 194 | * available prior to injection calls if fetching state anyway. */
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| 195 | #define IEM_CPUMCTX_EXTRN_XCPT_MASK ( IEM_CPUMCTX_EXTRN_MUST_MASK \
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| 196 | | CPUMCTX_EXTRN_CR2 \
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| 197 | | CPUMCTX_EXTRN_SREG_MASK \
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| 198 | | CPUMCTX_EXTRN_TABLE_MASK )
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| 199 | /** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
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| 200 | * IEMExecDecoded API not using memory. IEM will ASSUME the caller of IEM
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| 201 | * APIs has ensured these are already present.
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| 202 | * @note ASSUMES execution engine has checked for instruction breakpoints
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| 203 | * during decoding. */
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| 204 | #define IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ( CPUMCTX_EXTRN_RIP \
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| 205 | | CPUMCTX_EXTRN_RFLAGS \
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| 206 | | CPUMCTX_EXTRN_SS /* for CPL */ \
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| 207 | | CPUMCTX_EXTRN_CS /* for mode */ \
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| 208 | | CPUMCTX_EXTRN_CR0 /* for mode */ \
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| 209 | | CPUMCTX_EXTRN_EFER /* for mode */ )
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| 210 | /** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
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| 211 | * IEMExecDecoded API using memory. IEM will ASSUME the caller of IEM
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| 212 | * APIs has ensured these are already present.
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| 213 | * @note ASSUMES execution engine has checked for instruction breakpoints
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| 214 | * during decoding. */
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| 215 | #define IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
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| 216 | | CPUMCTX_EXTRN_CR3 /* for page tables */ \
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| 217 | | CPUMCTX_EXTRN_CR4 /* for mode paging mode */ \
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| 218 | | CPUMCTX_EXTRN_DR7 /* for memory breakpoints */ )
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| 219 |
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| 220 | #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
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| 221 | /** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecSvmVmexit().
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| 222 | * IEM will ASSUME the caller has ensured these are already present. */
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| 223 | # define IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK ( CPUMCTX_EXTRN_RSP \
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| 224 | | CPUMCTX_EXTRN_RAX \
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| 225 | | CPUMCTX_EXTRN_RIP \
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| 226 | | CPUMCTX_EXTRN_RFLAGS \
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| 227 | | CPUMCTX_EXTRN_CS \
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| 228 | | CPUMCTX_EXTRN_SS \
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| 229 | | CPUMCTX_EXTRN_DS \
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| 230 | | CPUMCTX_EXTRN_ES \
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| 231 | | CPUMCTX_EXTRN_GDTR \
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| 232 | | CPUMCTX_EXTRN_IDTR \
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| 233 | | CPUMCTX_EXTRN_CR_MASK \
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| 234 | | CPUMCTX_EXTRN_EFER \
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| 235 | | CPUMCTX_EXTRN_DR6 \
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| 236 | | CPUMCTX_EXTRN_DR7 \
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| 237 | | CPUMCTX_EXTRN_OTHER_MSRS \
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| 238 | | CPUMCTX_EXTRN_HWVIRT \
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| 239 | | CPUMCTX_EXTRN_APIC_TPR \
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| 240 | | CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
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| 241 |
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| 242 | /** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmrun().
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| 243 | * IEM will ASSUME the caller has ensured these are already present. */
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| 244 | # define IEM_CPUMCTX_EXTRN_SVM_VMRUN_MASK IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK
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| 245 | #endif
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| 246 |
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| 247 | VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPU pVCpu);
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| 248 | VMMDECL(VBOXSTRICTRC) IEMExecOneEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
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| 249 | VMMDECL(VBOXSTRICTRC) IEMExecOneWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
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| 250 | const void *pvOpcodeBytes, size_t cbOpcodeBytes);
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| 251 | VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
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| 252 | VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
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| 253 | const void *pvOpcodeBytes, size_t cbOpcodeBytes);
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| 254 | VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPCWritten(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
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| 255 | const void *pvOpcodeBytes, size_t cbOpcodeBytes,
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| 256 | uint32_t *pcbWritten);
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| 257 | VMMDECL(VBOXSTRICTRC) IEMExecLots(PVMCPU pVCpu, uint32_t *pcInstructions);
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| 258 | /** Statistics returned by IEMExecForExits. */
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| 259 | typedef struct IEMEXECFOREXITSTATS
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| 260 | {
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| 261 | uint32_t cInstructions;
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| 262 | uint32_t cExits;
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| 263 | uint32_t cMaxExitDistance;
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| 264 | uint32_t cReserved;
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| 265 | } IEMEXECFOREXITSTATS;
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| 266 | /** Pointer to statistics returned by IEMExecForExits. */
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| 267 | typedef IEMEXECFOREXITSTATS *PIEMEXECFOREXITSTATS;
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| 268 | VMMDECL(VBOXSTRICTRC) IEMExecForExits(PVMCPU pVCpu, uint32_t fWillExit, uint32_t cMinInstructions, uint32_t cMaxInstructions,
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| 269 | uint32_t cMaxInstructionsWithoutExits, PIEMEXECFOREXITSTATS pStats);
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| 270 | VMMDECL(VBOXSTRICTRC) IEMInjectTrpmEvent(PVMCPU pVCpu);
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| 271 | VMM_INT_DECL(VBOXSTRICTRC) IEMInjectTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2,
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| 272 | uint8_t cbInstr);
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| 273 |
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| 274 | VMM_INT_DECL(int) IEMBreakpointSet(PVM pVM, RTGCPTR GCPtrBp);
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| 275 | VMM_INT_DECL(int) IEMBreakpointClear(PVM pVM, RTGCPTR GCPtrBp);
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| 276 |
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| 277 | VMM_INT_DECL(void) IEMTlbInvalidateAll(PVMCPU pVCpu, bool fVmm);
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| 278 | VMM_INT_DECL(void) IEMTlbInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtr);
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| 279 | VMM_INT_DECL(void) IEMTlbInvalidateAllPhysical(PVMCPU pVCpu);
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| 280 | VMM_INT_DECL(bool) IEMGetCurrentXcpt(PVMCPU pVCpu, uint8_t *puVector, uint32_t *pfFlags, uint32_t *puErr,
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| 281 | uint64_t *puCr2);
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| 282 | VMM_INT_DECL(IEMXCPTRAISE) IEMEvaluateRecursiveXcpt(PVMCPU pVCpu, uint32_t fPrevFlags, uint8_t uPrevVector, uint32_t fCurFlags,
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| 283 | uint8_t uCurVector, PIEMXCPTRAISEINFO pXcptRaiseInfo);
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| 284 |
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| 285 | /** @name Given Instruction Interpreters
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| 286 | * @{ */
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| 287 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
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| 288 | bool fRepPrefix, uint8_t cbInstr, uint8_t iEffSeg, bool fIoChecked);
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| 289 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
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| 290 | bool fRepPrefix, uint8_t cbInstr, bool fIoChecked);
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| 291 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedOut(PVMCPU pVCpu, uint8_t cbInstr, uint16_t u16Port, uint8_t cbReg);
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| 292 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedIn(PVMCPU pVCpu, uint8_t cbInstr, uint16_t u16Port, uint8_t cbReg);
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| 293 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxWrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg);
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| 294 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxRead(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg);
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| 295 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClts(PVMCPU pVCpu, uint8_t cbInstr);
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| 296 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedLmsw(PVMCPU pVCpu, uint8_t cbInstr, uint16_t uValue);
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| 297 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedXsetbv(PVMCPU pVCpu, uint8_t cbInstr);
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| 298 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpg(PVMCPU pVCpu, uint8_t cbInstr, RTGCPTR GCPtrPage);
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| 299 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvpcid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t uType, RTGCPTR GCPtrInvpcidDesc);
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| 300 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtsc(PVMCPU pVCpu, uint8_t cbInstr);
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| 301 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtscp(PVMCPU pVCpu, uint8_t cbInstr);
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| 302 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdmsr(PVMCPU pVCpu, uint8_t cbInstr);
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| 303 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWrmsr(PVMCPU pVCpu, uint8_t cbInstr);
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| 304 |
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| 305 | #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
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| 306 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClgi(PVMCPU pVCpu, uint8_t cbInstr);
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| 307 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedStgi(PVMCPU pVCpu, uint8_t cbInstr);
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| 308 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmload(PVMCPU pVCpu, uint8_t cbInstr);
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| 309 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmsave(PVMCPU pVCpu, uint8_t cbInstr);
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| 310 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpga(PVMCPU pVCpu, uint8_t cbInstr);
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| 311 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmrun(PVMCPU pVCpu, uint8_t cbInstr);
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| 312 | VMM_INT_DECL(VBOXSTRICTRC) IEMExecSvmVmexit(PVMCPU pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2);
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| 313 | #endif
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| 314 | /** @} */
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| 315 |
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| 316 |
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| 317 | /** @defgroup grp_iem_r3 The IEM Host Context Ring-3 API.
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| 318 | * @{
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| 319 | */
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| 320 | VMMR3DECL(int) IEMR3Init(PVM pVM);
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| 321 | VMMR3DECL(int) IEMR3Term(PVM pVM);
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| 322 | VMMR3DECL(void) IEMR3Relocate(PVM pVM);
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| 323 | VMMR3_INT_DECL(VBOXSTRICTRC) IEMR3ProcessForceFlag(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rcStrict);
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| 324 | /** @} */
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| 325 |
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| 326 | /** @} */
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| 327 |
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| 328 | RT_C_DECLS_END
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| 329 |
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| 330 | #endif
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| 331 |
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