VirtualBox

source: vbox/trunk/include/VBox/vmm/iem.h@ 75150

Last change on this file since 75150 was 75150, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 VM-exit bits; for INIT and SIPI.
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1/** @file
2 * IEM - Interpreted Execution Manager.
3 */
4
5/*
6 * Copyright (C) 2011-2017 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_iem_h
27#define ___VBox_vmm_iem_h
28
29#include <VBox/types.h>
30#include <VBox/vmm/trpm.h>
31#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
32# include <VBox/vmm/hm_vmx.h>
33#endif
34#include <iprt/assert.h>
35
36
37RT_C_DECLS_BEGIN
38
39/** @defgroup grp_iem The Interpreted Execution Manager API.
40 * @ingroup grp_vmm
41 * @{
42 */
43
44/** @name IEMXCPTRAISEINFO_XXX - Extra info. on a recursive exception situation.
45 *
46 * This is primarily used by HM for working around a PGM limitation (see
47 * @bugref{6607}) and special NMI/IRET handling. In the future, this may be
48 * used for diagnostics.
49 *
50 * @{
51 */
52typedef uint32_t IEMXCPTRAISEINFO;
53/** Pointer to a IEMXCPTINFO type. */
54typedef IEMXCPTRAISEINFO *PIEMXCPTRAISEINFO;
55/** No addition info. available. */
56#define IEMXCPTRAISEINFO_NONE RT_BIT_32(0)
57/** Delivery of a \#AC caused another \#AC. */
58#define IEMXCPTRAISEINFO_AC_AC RT_BIT_32(1)
59/** Delivery of a \#PF caused another \#PF. */
60#define IEMXCPTRAISEINFO_PF_PF RT_BIT_32(2)
61/** Delivery of a \#PF caused some contributory exception. */
62#define IEMXCPTRAISEINFO_PF_CONTRIBUTORY_XCPT RT_BIT_32(3)
63/** Delivery of an external interrupt caused an exception. */
64#define IEMXCPTRAISEINFO_EXT_INT_XCPT RT_BIT_32(4)
65/** Delivery of an external interrupt caused an \#PF. */
66#define IEMXCPTRAISEINFO_EXT_INT_PF RT_BIT_32(5)
67/** Delivery of a software interrupt caused an exception. */
68#define IEMXCPTRAISEINFO_SOFT_INT_XCPT RT_BIT_32(6)
69/** Delivery of an NMI caused an exception. */
70#define IEMXCPTRAISEINFO_NMI_XCPT RT_BIT_32(7)
71/** Delivery of an NMI caused a \#PF. */
72#define IEMXCPTRAISEINFO_NMI_PF RT_BIT_32(8)
73/** Can re-execute the instruction at CS:RIP. */
74#define IEMXCPTRAISEINFO_CAN_REEXEC_INSTR RT_BIT_32(9)
75/** @} */
76
77
78/** @name IEMXCPTRAISE_XXX - Ways to handle a recursive exception condition.
79 * @{ */
80typedef enum IEMXCPTRAISE
81{
82 /** Raise the current (second) exception. */
83 IEMXCPTRAISE_CURRENT_XCPT = 0,
84 /** Re-raise the previous (first) event (for HM, unused by IEM). */
85 IEMXCPTRAISE_PREV_EVENT,
86 /** Re-execute instruction at CS:RIP (for HM, unused by IEM). */
87 IEMXCPTRAISE_REEXEC_INSTR,
88 /** Raise a \#DF exception. */
89 IEMXCPTRAISE_DOUBLE_FAULT,
90 /** Raise a triple fault. */
91 IEMXCPTRAISE_TRIPLE_FAULT,
92 /** Cause a CPU hang. */
93 IEMXCPTRAISE_CPU_HANG,
94 /** Invalid sequence of events. */
95 IEMXCPTRAISE_INVALID = 0x7fffffff
96} IEMXCPTRAISE;
97/** Pointer to a IEMXCPTRAISE type. */
98typedef IEMXCPTRAISE *PIEMXCPTRAISE;
99/** @} */
100
101
102/** @name Operand or addressing mode.
103 * @{ */
104typedef uint8_t IEMMODE;
105#define IEMMODE_16BIT 0
106#define IEMMODE_32BIT 1
107#define IEMMODE_64BIT 2
108/** @} */
109
110
111/** @name IEM_XCPT_FLAGS_XXX - flags for iemRaiseXcptOrInt.
112 * @{ */
113/** CPU exception. */
114#define IEM_XCPT_FLAGS_T_CPU_XCPT RT_BIT_32(0)
115/** External interrupt (from PIC, APIC, whatever). */
116#define IEM_XCPT_FLAGS_T_EXT_INT RT_BIT_32(1)
117/** Software interrupt (int or into, not bound).
118 * Returns to the following instruction */
119#define IEM_XCPT_FLAGS_T_SOFT_INT RT_BIT_32(2)
120/** Takes an error code. */
121#define IEM_XCPT_FLAGS_ERR RT_BIT_32(3)
122/** Takes a CR2. */
123#define IEM_XCPT_FLAGS_CR2 RT_BIT_32(4)
124/** Generated by the breakpoint instruction. */
125#define IEM_XCPT_FLAGS_BP_INSTR RT_BIT_32(5)
126/** Generated by a DRx instruction breakpoint and RF should be cleared. */
127#define IEM_XCPT_FLAGS_DRx_INSTR_BP RT_BIT_32(6)
128/** Generated by the icebp instruction. */
129#define IEM_XCPT_FLAGS_ICEBP_INSTR RT_BIT_32(7)
130/** Generated by the overflow instruction. */
131#define IEM_XCPT_FLAGS_OF_INSTR RT_BIT_32(8)
132/** @} */
133
134
135/** @name IEMTARGETCPU_XXX - IEM target CPU specification.
136 *
137 * This is a gross simpliciation of CPUMMICROARCH for dealing with really old
138 * CPUs which didn't have much in the way of hinting at supported instructions
139 * and features. This slowly changes with the introduction of CPUID with the
140 * Intel Pentium.
141 *
142 * @{
143 */
144/** The dynamic target CPU mode is for getting thru the BIOS and then use
145 * the debugger or modifying instruction behaviour (e.g. HLT) to switch to a
146 * different target CPU. */
147#define IEMTARGETCPU_DYNAMIC UINT32_C(0)
148/** Intel 8086/8088. */
149#define IEMTARGETCPU_8086 UINT32_C(1)
150/** NEC V20/V30.
151 * @remarks must be between 8086 and 80186. */
152#define IEMTARGETCPU_V20 UINT32_C(2)
153/** Intel 80186/80188. */
154#define IEMTARGETCPU_186 UINT32_C(3)
155/** Intel 80286. */
156#define IEMTARGETCPU_286 UINT32_C(4)
157/** Intel 80386. */
158#define IEMTARGETCPU_386 UINT32_C(5)
159/** Intel 80486. */
160#define IEMTARGETCPU_486 UINT32_C(6)
161/** Intel Pentium . */
162#define IEMTARGETCPU_PENTIUM UINT32_C(7)
163/** Intel PentiumPro. */
164#define IEMTARGETCPU_PPRO UINT32_C(8)
165/** A reasonably current CPU, probably newer than the pentium pro when it comes
166 * to the feature set and behaviour. Generally the CPUID info and CPU vendor
167 * dicates the behaviour here. */
168#define IEMTARGETCPU_CURRENT UINT32_C(9)
169/** @} */
170
171
172/** @name IEM status codes.
173 *
174 * Not quite sure how this will play out in the end, just aliasing safe status
175 * codes for now.
176 *
177 * @{ */
178#define VINF_IEM_RAISED_XCPT VINF_EM_RESCHEDULE
179/** @} */
180
181
182/** The CPUMCTX_EXTRN_XXX mask required to be cleared when interpreting anything.
183 * IEM will ASSUME the caller of IEM APIs has ensured these are already present. */
184#define IEM_CPUMCTX_EXTRN_MUST_MASK ( CPUMCTX_EXTRN_GPRS_MASK \
185 | CPUMCTX_EXTRN_RIP \
186 | CPUMCTX_EXTRN_RFLAGS \
187 | CPUMCTX_EXTRN_SS \
188 | CPUMCTX_EXTRN_CS \
189 | CPUMCTX_EXTRN_CR0 \
190 | CPUMCTX_EXTRN_CR3 \
191 | CPUMCTX_EXTRN_CR4 \
192 | CPUMCTX_EXTRN_APIC_TPR \
193 | CPUMCTX_EXTRN_EFER \
194 | CPUMCTX_EXTRN_DR7 )
195/** The CPUMCTX_EXTRN_XXX mask needed when injecting an exception/interrupt.
196 * IEM will import missing bits, callers are encouraged to make these registers
197 * available prior to injection calls if fetching state anyway. */
198#define IEM_CPUMCTX_EXTRN_XCPT_MASK ( IEM_CPUMCTX_EXTRN_MUST_MASK \
199 | CPUMCTX_EXTRN_CR2 \
200 | CPUMCTX_EXTRN_SREG_MASK \
201 | CPUMCTX_EXTRN_TABLE_MASK )
202/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
203 * IEMExecDecoded API not using memory. IEM will ASSUME the caller of IEM
204 * APIs has ensured these are already present.
205 * @note ASSUMES execution engine has checked for instruction breakpoints
206 * during decoding. */
207#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ( CPUMCTX_EXTRN_RIP \
208 | CPUMCTX_EXTRN_RFLAGS \
209 | CPUMCTX_EXTRN_SS /* for CPL */ \
210 | CPUMCTX_EXTRN_CS /* for mode */ \
211 | CPUMCTX_EXTRN_CR0 /* for mode */ \
212 | CPUMCTX_EXTRN_EFER /* for mode */ )
213/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
214 * IEMExecDecoded API using memory. IEM will ASSUME the caller of IEM
215 * APIs has ensured these are already present.
216 * @note ASSUMES execution engine has checked for instruction breakpoints
217 * during decoding. */
218#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
219 | CPUMCTX_EXTRN_CR3 /* for page tables */ \
220 | CPUMCTX_EXTRN_CR4 /* for mode paging mode */ \
221 | CPUMCTX_EXTRN_DR7 /* for memory breakpoints */ )
222
223#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
224# define IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK CPUMCTX_EXTRN_ABSOLUTELY_ALL
225# define IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK
226#endif
227
228#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
229/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecSvmVmexit().
230 * IEM will ASSUME the caller has ensured these are already present. */
231# define IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK ( CPUMCTX_EXTRN_RSP \
232 | CPUMCTX_EXTRN_RAX \
233 | CPUMCTX_EXTRN_RIP \
234 | CPUMCTX_EXTRN_RFLAGS \
235 | CPUMCTX_EXTRN_CS \
236 | CPUMCTX_EXTRN_SS \
237 | CPUMCTX_EXTRN_DS \
238 | CPUMCTX_EXTRN_ES \
239 | CPUMCTX_EXTRN_GDTR \
240 | CPUMCTX_EXTRN_IDTR \
241 | CPUMCTX_EXTRN_CR_MASK \
242 | CPUMCTX_EXTRN_EFER \
243 | CPUMCTX_EXTRN_DR6 \
244 | CPUMCTX_EXTRN_DR7 \
245 | CPUMCTX_EXTRN_OTHER_MSRS \
246 | CPUMCTX_EXTRN_HWVIRT \
247 | CPUMCTX_EXTRN_APIC_TPR \
248 | CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
249
250/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmrun().
251 * IEM will ASSUME the caller has ensured these are already present. */
252# define IEM_CPUMCTX_EXTRN_SVM_VMRUN_MASK IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK
253#endif
254
255VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPU pVCpu);
256VMMDECL(VBOXSTRICTRC) IEMExecOneEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
257VMMDECL(VBOXSTRICTRC) IEMExecOneWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
258 const void *pvOpcodeBytes, size_t cbOpcodeBytes);
259VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
260VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
261 const void *pvOpcodeBytes, size_t cbOpcodeBytes);
262VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPCWritten(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
263 const void *pvOpcodeBytes, size_t cbOpcodeBytes,
264 uint32_t *pcbWritten);
265VMMDECL(VBOXSTRICTRC) IEMExecLots(PVMCPU pVCpu, uint32_t *pcInstructions);
266/** Statistics returned by IEMExecForExits. */
267typedef struct IEMEXECFOREXITSTATS
268{
269 uint32_t cInstructions;
270 uint32_t cExits;
271 uint32_t cMaxExitDistance;
272 uint32_t cReserved;
273} IEMEXECFOREXITSTATS;
274/** Pointer to statistics returned by IEMExecForExits. */
275typedef IEMEXECFOREXITSTATS *PIEMEXECFOREXITSTATS;
276VMMDECL(VBOXSTRICTRC) IEMExecForExits(PVMCPU pVCpu, uint32_t fWillExit, uint32_t cMinInstructions, uint32_t cMaxInstructions,
277 uint32_t cMaxInstructionsWithoutExits, PIEMEXECFOREXITSTATS pStats);
278VMMDECL(VBOXSTRICTRC) IEMInjectTrpmEvent(PVMCPU pVCpu);
279VMM_INT_DECL(VBOXSTRICTRC) IEMInjectTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2,
280 uint8_t cbInstr);
281
282VMM_INT_DECL(int) IEMBreakpointSet(PVM pVM, RTGCPTR GCPtrBp);
283VMM_INT_DECL(int) IEMBreakpointClear(PVM pVM, RTGCPTR GCPtrBp);
284
285VMM_INT_DECL(void) IEMTlbInvalidateAll(PVMCPU pVCpu, bool fVmm);
286VMM_INT_DECL(void) IEMTlbInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtr);
287VMM_INT_DECL(void) IEMTlbInvalidateAllPhysical(PVMCPU pVCpu);
288VMM_INT_DECL(bool) IEMGetCurrentXcpt(PVMCPU pVCpu, uint8_t *puVector, uint32_t *pfFlags, uint32_t *puErr,
289 uint64_t *puCr2);
290VMM_INT_DECL(IEMXCPTRAISE) IEMEvaluateRecursiveXcpt(PVMCPU pVCpu, uint32_t fPrevFlags, uint8_t uPrevVector, uint32_t fCurFlags,
291 uint8_t uCurVector, PIEMXCPTRAISEINFO pXcptRaiseInfo);
292
293/** @name Given Instruction Interpreters
294 * @{ */
295VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
296 bool fRepPrefix, uint8_t cbInstr, uint8_t iEffSeg, bool fIoChecked);
297VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
298 bool fRepPrefix, uint8_t cbInstr, bool fIoChecked);
299VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedOut(PVMCPU pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);
300VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedIn(PVMCPU pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);
301VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxWrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg);
302VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxRead(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg);
303VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClts(PVMCPU pVCpu, uint8_t cbInstr);
304VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedLmsw(PVMCPU pVCpu, uint8_t cbInstr, uint16_t uValue, RTGCPTR GCPtrEffDst);
305VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedXsetbv(PVMCPU pVCpu, uint8_t cbInstr);
306VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWbinvd(PVMCPU pVCpu, uint8_t cbInstr);
307VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvd(PVMCPU pVCpu, uint8_t cbInstr);
308VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpg(PVMCPU pVCpu, uint8_t cbInstr, RTGCPTR GCPtrPage);
309VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedCpuid(PVMCPU pVCpu, uint8_t cbInstr);
310VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdpmc(PVMCPU pVCpu, uint8_t cbInstr);
311VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtsc(PVMCPU pVCpu, uint8_t cbInstr);
312VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtscp(PVMCPU pVCpu, uint8_t cbInstr);
313VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdmsr(PVMCPU pVCpu, uint8_t cbInstr);
314VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWrmsr(PVMCPU pVCpu, uint8_t cbInstr);
315VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMonitor(PVMCPU pVCpu, uint8_t cbInstr);
316VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMwait(PVMCPU pVCpu, uint8_t cbInstr);
317VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedHlt(PVMCPU pVCpu, uint8_t cbInstr);
318
319#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
320VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClgi(PVMCPU pVCpu, uint8_t cbInstr);
321VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedStgi(PVMCPU pVCpu, uint8_t cbInstr);
322VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmload(PVMCPU pVCpu, uint8_t cbInstr);
323VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmsave(PVMCPU pVCpu, uint8_t cbInstr);
324VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpga(PVMCPU pVCpu, uint8_t cbInstr);
325VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmrun(PVMCPU pVCpu, uint8_t cbInstr);
326VMM_INT_DECL(VBOXSTRICTRC) IEMExecSvmVmexit(PVMCPU pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2);
327#endif
328
329#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
330VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending);
331VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector);
332VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInitIpi(PVMCPU pVCpu);
333VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitIntWindow(PVMCPU pVCpu);
334VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
335VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
336VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
337VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
338VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
339VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
340VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPU pVCpu, uint8_t cbInstr);
341#endif
342/** @} */
343
344
345/** @defgroup grp_iem_r3 The IEM Host Context Ring-3 API.
346 * @{
347 */
348VMMR3DECL(int) IEMR3Init(PVM pVM);
349VMMR3DECL(int) IEMR3Term(PVM pVM);
350VMMR3DECL(void) IEMR3Relocate(PVM pVM);
351VMMR3_INT_DECL(VBOXSTRICTRC) IEMR3ProcessForceFlag(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rcStrict);
352/** @} */
353
354/** @} */
355
356RT_C_DECLS_END
357
358#endif
359
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