VirtualBox

source: vbox/trunk/include/VBox/vmm/iem.h@ 77921

Last change on this file since 77921 was 77717, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Added IEMExecVmxVmexitNmi. Might need to eventually do a more generic one that covers hardware exceptions as well as software ints. For now this will do.
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1/** @file
2 * IEM - Interpreted Execution Manager.
3 */
4
5/*
6 * Copyright (C) 2011-2019 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_iem_h
27#define VBOX_INCLUDED_vmm_iem_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/types.h>
33#include <VBox/vmm/trpm.h>
34#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
35# include <VBox/vmm/hm_vmx.h>
36#endif
37#include <iprt/assert.h>
38
39
40RT_C_DECLS_BEGIN
41
42/** @defgroup grp_iem The Interpreted Execution Manager API.
43 * @ingroup grp_vmm
44 * @{
45 */
46
47/** @name IEMXCPTRAISEINFO_XXX - Extra info. on a recursive exception situation.
48 *
49 * This is primarily used by HM for working around a PGM limitation (see
50 * @bugref{6607}) and special NMI/IRET handling. In the future, this may be
51 * used for diagnostics.
52 *
53 * @{
54 */
55typedef uint32_t IEMXCPTRAISEINFO;
56/** Pointer to a IEMXCPTINFO type. */
57typedef IEMXCPTRAISEINFO *PIEMXCPTRAISEINFO;
58/** No addition info. available. */
59#define IEMXCPTRAISEINFO_NONE RT_BIT_32(0)
60/** Delivery of a \#AC caused another \#AC. */
61#define IEMXCPTRAISEINFO_AC_AC RT_BIT_32(1)
62/** Delivery of a \#PF caused another \#PF. */
63#define IEMXCPTRAISEINFO_PF_PF RT_BIT_32(2)
64/** Delivery of a \#PF caused some contributory exception. */
65#define IEMXCPTRAISEINFO_PF_CONTRIBUTORY_XCPT RT_BIT_32(3)
66/** Delivery of an external interrupt caused an exception. */
67#define IEMXCPTRAISEINFO_EXT_INT_XCPT RT_BIT_32(4)
68/** Delivery of an external interrupt caused an \#PF. */
69#define IEMXCPTRAISEINFO_EXT_INT_PF RT_BIT_32(5)
70/** Delivery of a software interrupt caused an exception. */
71#define IEMXCPTRAISEINFO_SOFT_INT_XCPT RT_BIT_32(6)
72/** Delivery of an NMI caused an exception. */
73#define IEMXCPTRAISEINFO_NMI_XCPT RT_BIT_32(7)
74/** Delivery of an NMI caused a \#PF. */
75#define IEMXCPTRAISEINFO_NMI_PF RT_BIT_32(8)
76/** Can re-execute the instruction at CS:RIP. */
77#define IEMXCPTRAISEINFO_CAN_REEXEC_INSTR RT_BIT_32(9)
78/** @} */
79
80
81/** @name IEMXCPTRAISE_XXX - Ways to handle a recursive exception condition.
82 * @{ */
83typedef enum IEMXCPTRAISE
84{
85 /** Raise the current (second) exception. */
86 IEMXCPTRAISE_CURRENT_XCPT = 0,
87 /** Re-raise the previous (first) event (for HM, unused by IEM). */
88 IEMXCPTRAISE_PREV_EVENT,
89 /** Re-execute instruction at CS:RIP (for HM, unused by IEM). */
90 IEMXCPTRAISE_REEXEC_INSTR,
91 /** Raise a \#DF exception. */
92 IEMXCPTRAISE_DOUBLE_FAULT,
93 /** Raise a triple fault. */
94 IEMXCPTRAISE_TRIPLE_FAULT,
95 /** Cause a CPU hang. */
96 IEMXCPTRAISE_CPU_HANG,
97 /** Invalid sequence of events. */
98 IEMXCPTRAISE_INVALID = 0x7fffffff
99} IEMXCPTRAISE;
100/** Pointer to a IEMXCPTRAISE type. */
101typedef IEMXCPTRAISE *PIEMXCPTRAISE;
102/** @} */
103
104
105/** @name Operand or addressing mode.
106 * @{ */
107typedef uint8_t IEMMODE;
108#define IEMMODE_16BIT 0
109#define IEMMODE_32BIT 1
110#define IEMMODE_64BIT 2
111/** @} */
112
113
114/** @name IEM_XCPT_FLAGS_XXX - flags for iemRaiseXcptOrInt.
115 * @{ */
116/** CPU exception. */
117#define IEM_XCPT_FLAGS_T_CPU_XCPT RT_BIT_32(0)
118/** External interrupt (from PIC, APIC, whatever). */
119#define IEM_XCPT_FLAGS_T_EXT_INT RT_BIT_32(1)
120/** Software interrupt (int or into, not bound).
121 * Returns to the following instruction */
122#define IEM_XCPT_FLAGS_T_SOFT_INT RT_BIT_32(2)
123/** Takes an error code. */
124#define IEM_XCPT_FLAGS_ERR RT_BIT_32(3)
125/** Takes a CR2. */
126#define IEM_XCPT_FLAGS_CR2 RT_BIT_32(4)
127/** Generated by the breakpoint instruction. */
128#define IEM_XCPT_FLAGS_BP_INSTR RT_BIT_32(5)
129/** Generated by a DRx instruction breakpoint and RF should be cleared. */
130#define IEM_XCPT_FLAGS_DRx_INSTR_BP RT_BIT_32(6)
131/** Generated by the icebp instruction. */
132#define IEM_XCPT_FLAGS_ICEBP_INSTR RT_BIT_32(7)
133/** Generated by the overflow instruction. */
134#define IEM_XCPT_FLAGS_OF_INSTR RT_BIT_32(8)
135/** @} */
136
137
138/** @name IEMTARGETCPU_XXX - IEM target CPU specification.
139 *
140 * This is a gross simpliciation of CPUMMICROARCH for dealing with really old
141 * CPUs which didn't have much in the way of hinting at supported instructions
142 * and features. This slowly changes with the introduction of CPUID with the
143 * Intel Pentium.
144 *
145 * @{
146 */
147/** The dynamic target CPU mode is for getting thru the BIOS and then use
148 * the debugger or modifying instruction behaviour (e.g. HLT) to switch to a
149 * different target CPU. */
150#define IEMTARGETCPU_DYNAMIC UINT32_C(0)
151/** Intel 8086/8088. */
152#define IEMTARGETCPU_8086 UINT32_C(1)
153/** NEC V20/V30.
154 * @remarks must be between 8086 and 80186. */
155#define IEMTARGETCPU_V20 UINT32_C(2)
156/** Intel 80186/80188. */
157#define IEMTARGETCPU_186 UINT32_C(3)
158/** Intel 80286. */
159#define IEMTARGETCPU_286 UINT32_C(4)
160/** Intel 80386. */
161#define IEMTARGETCPU_386 UINT32_C(5)
162/** Intel 80486. */
163#define IEMTARGETCPU_486 UINT32_C(6)
164/** Intel Pentium . */
165#define IEMTARGETCPU_PENTIUM UINT32_C(7)
166/** Intel PentiumPro. */
167#define IEMTARGETCPU_PPRO UINT32_C(8)
168/** A reasonably current CPU, probably newer than the pentium pro when it comes
169 * to the feature set and behaviour. Generally the CPUID info and CPU vendor
170 * dicates the behaviour here. */
171#define IEMTARGETCPU_CURRENT UINT32_C(9)
172/** @} */
173
174
175/** @name IEM status codes.
176 *
177 * Not quite sure how this will play out in the end, just aliasing safe status
178 * codes for now.
179 *
180 * @{ */
181#define VINF_IEM_RAISED_XCPT VINF_EM_RESCHEDULE
182/** @} */
183
184
185/** The CPUMCTX_EXTRN_XXX mask required to be cleared when interpreting anything.
186 * IEM will ASSUME the caller of IEM APIs has ensured these are already present. */
187#define IEM_CPUMCTX_EXTRN_MUST_MASK ( CPUMCTX_EXTRN_GPRS_MASK \
188 | CPUMCTX_EXTRN_RIP \
189 | CPUMCTX_EXTRN_RFLAGS \
190 | CPUMCTX_EXTRN_SS \
191 | CPUMCTX_EXTRN_CS \
192 | CPUMCTX_EXTRN_CR0 \
193 | CPUMCTX_EXTRN_CR3 \
194 | CPUMCTX_EXTRN_CR4 \
195 | CPUMCTX_EXTRN_APIC_TPR \
196 | CPUMCTX_EXTRN_EFER \
197 | CPUMCTX_EXTRN_DR7 )
198/** The CPUMCTX_EXTRN_XXX mask needed when injecting an exception/interrupt.
199 * IEM will import missing bits, callers are encouraged to make these registers
200 * available prior to injection calls if fetching state anyway. */
201#define IEM_CPUMCTX_EXTRN_XCPT_MASK ( IEM_CPUMCTX_EXTRN_MUST_MASK \
202 | CPUMCTX_EXTRN_CR2 \
203 | CPUMCTX_EXTRN_SREG_MASK \
204 | CPUMCTX_EXTRN_TABLE_MASK )
205/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
206 * IEMExecDecoded API not using memory. IEM will ASSUME the caller of IEM
207 * APIs has ensured these are already present.
208 * @note ASSUMES execution engine has checked for instruction breakpoints
209 * during decoding. */
210#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ( CPUMCTX_EXTRN_RIP \
211 | CPUMCTX_EXTRN_RFLAGS \
212 | CPUMCTX_EXTRN_SS /* for CPL */ \
213 | CPUMCTX_EXTRN_CS /* for mode */ \
214 | CPUMCTX_EXTRN_CR0 /* for mode */ \
215 | CPUMCTX_EXTRN_EFER /* for mode */ )
216/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
217 * IEMExecDecoded API using memory. IEM will ASSUME the caller of IEM
218 * APIs has ensured these are already present.
219 * @note ASSUMES execution engine has checked for instruction breakpoints
220 * during decoding. */
221#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
222 | CPUMCTX_EXTRN_CR3 /* for page tables */ \
223 | CPUMCTX_EXTRN_CR4 /* for mode paging mode */ \
224 | CPUMCTX_EXTRN_DR7 /* for memory breakpoints */ )
225
226#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
227# define IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
228 | CPUMCTX_EXTRN_HWVIRT )
229#endif
230
231#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
232/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecSvmVmexit().
233 * IEM will ASSUME the caller has ensured these are already present. */
234# define IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK ( CPUMCTX_EXTRN_RSP \
235 | CPUMCTX_EXTRN_RAX \
236 | CPUMCTX_EXTRN_RIP \
237 | CPUMCTX_EXTRN_RFLAGS \
238 | CPUMCTX_EXTRN_CS \
239 | CPUMCTX_EXTRN_SS \
240 | CPUMCTX_EXTRN_DS \
241 | CPUMCTX_EXTRN_ES \
242 | CPUMCTX_EXTRN_GDTR \
243 | CPUMCTX_EXTRN_IDTR \
244 | CPUMCTX_EXTRN_CR_MASK \
245 | CPUMCTX_EXTRN_EFER \
246 | CPUMCTX_EXTRN_DR6 \
247 | CPUMCTX_EXTRN_DR7 \
248 | CPUMCTX_EXTRN_OTHER_MSRS \
249 | CPUMCTX_EXTRN_HWVIRT \
250 | CPUMCTX_EXTRN_APIC_TPR \
251 | CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
252
253/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmrun().
254 * IEM will ASSUME the caller has ensured these are already present. */
255# define IEM_CPUMCTX_EXTRN_SVM_VMRUN_MASK IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK
256#endif
257
258VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPU pVCpu);
259VMMDECL(VBOXSTRICTRC) IEMExecOneEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
260VMMDECL(VBOXSTRICTRC) IEMExecOneWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
261 const void *pvOpcodeBytes, size_t cbOpcodeBytes);
262VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
263VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
264 const void *pvOpcodeBytes, size_t cbOpcodeBytes);
265VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPCWritten(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
266 const void *pvOpcodeBytes, size_t cbOpcodeBytes,
267 uint32_t *pcbWritten);
268VMMDECL(VBOXSTRICTRC) IEMExecLots(PVMCPU pVCpu, uint32_t cMaxInstructions, uint32_t cPollRate, uint32_t *pcInstructions);
269/** Statistics returned by IEMExecForExits. */
270typedef struct IEMEXECFOREXITSTATS
271{
272 uint32_t cInstructions;
273 uint32_t cExits;
274 uint32_t cMaxExitDistance;
275 uint32_t cReserved;
276} IEMEXECFOREXITSTATS;
277/** Pointer to statistics returned by IEMExecForExits. */
278typedef IEMEXECFOREXITSTATS *PIEMEXECFOREXITSTATS;
279VMMDECL(VBOXSTRICTRC) IEMExecForExits(PVMCPU pVCpu, uint32_t fWillExit, uint32_t cMinInstructions, uint32_t cMaxInstructions,
280 uint32_t cMaxInstructionsWithoutExits, PIEMEXECFOREXITSTATS pStats);
281VMMDECL(VBOXSTRICTRC) IEMInjectTrpmEvent(PVMCPU pVCpu);
282VMM_INT_DECL(VBOXSTRICTRC) IEMInjectTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2,
283 uint8_t cbInstr);
284
285VMM_INT_DECL(int) IEMBreakpointSet(PVM pVM, RTGCPTR GCPtrBp);
286VMM_INT_DECL(int) IEMBreakpointClear(PVM pVM, RTGCPTR GCPtrBp);
287
288VMM_INT_DECL(void) IEMTlbInvalidateAll(PVMCPU pVCpu, bool fVmm);
289VMM_INT_DECL(void) IEMTlbInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtr);
290VMM_INT_DECL(void) IEMTlbInvalidateAllPhysical(PVMCPU pVCpu);
291VMM_INT_DECL(bool) IEMGetCurrentXcpt(PVMCPU pVCpu, uint8_t *puVector, uint32_t *pfFlags, uint32_t *puErr,
292 uint64_t *puCr2);
293VMM_INT_DECL(IEMXCPTRAISE) IEMEvaluateRecursiveXcpt(PVMCPU pVCpu, uint32_t fPrevFlags, uint8_t uPrevVector, uint32_t fCurFlags,
294 uint8_t uCurVector, PIEMXCPTRAISEINFO pXcptRaiseInfo);
295
296/** @name Given Instruction Interpreters
297 * @{ */
298VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
299 bool fRepPrefix, uint8_t cbInstr, uint8_t iEffSeg, bool fIoChecked);
300VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
301 bool fRepPrefix, uint8_t cbInstr, bool fIoChecked);
302VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedOut(PVMCPU pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);
303VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedIn(PVMCPU pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);
304VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxWrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg);
305VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxRead(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg);
306VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClts(PVMCPU pVCpu, uint8_t cbInstr);
307VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedLmsw(PVMCPU pVCpu, uint8_t cbInstr, uint16_t uValue, RTGCPTR GCPtrEffDst);
308VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedXsetbv(PVMCPU pVCpu, uint8_t cbInstr);
309VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWbinvd(PVMCPU pVCpu, uint8_t cbInstr);
310VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvd(PVMCPU pVCpu, uint8_t cbInstr);
311VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpg(PVMCPU pVCpu, uint8_t cbInstr, RTGCPTR GCPtrPage);
312VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedCpuid(PVMCPU pVCpu, uint8_t cbInstr);
313VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdpmc(PVMCPU pVCpu, uint8_t cbInstr);
314VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtsc(PVMCPU pVCpu, uint8_t cbInstr);
315VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtscp(PVMCPU pVCpu, uint8_t cbInstr);
316VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdmsr(PVMCPU pVCpu, uint8_t cbInstr);
317VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWrmsr(PVMCPU pVCpu, uint8_t cbInstr);
318VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMonitor(PVMCPU pVCpu, uint8_t cbInstr);
319VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMwait(PVMCPU pVCpu, uint8_t cbInstr);
320VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedHlt(PVMCPU pVCpu, uint8_t cbInstr);
321
322#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
323VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClgi(PVMCPU pVCpu, uint8_t cbInstr);
324VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedStgi(PVMCPU pVCpu, uint8_t cbInstr);
325VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmload(PVMCPU pVCpu, uint8_t cbInstr);
326VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmsave(PVMCPU pVCpu, uint8_t cbInstr);
327VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpga(PVMCPU pVCpu, uint8_t cbInstr);
328VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmrun(PVMCPU pVCpu, uint8_t cbInstr);
329VMM_INT_DECL(VBOXSTRICTRC) IEMExecSvmVmexit(PVMCPU pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2);
330#endif
331
332#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
333VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Val, bool fWrite);
334VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPU pVCpu);
335VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPU pVCpu);
336VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending);
337VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitNmi(PVMCPU pVCpu);
338VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector);
339VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInitIpi(PVMCPU pVCpu);
340VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitIntWindow(PVMCPU pVCpu);
341VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitNmiWindow(PVMCPU pVCpu);
342VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitMtf(PVMCPU pVCpu);
343VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
344VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
345VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
346VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
347VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
348VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId);
349VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo);
350VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPU pVCpu, uint8_t cbInstr);
351#endif
352/** @} */
353
354
355/** @defgroup grp_iem_r3 The IEM Host Context Ring-3 API.
356 * @{
357 */
358VMMR3DECL(int) IEMR3Init(PVM pVM);
359VMMR3DECL(int) IEMR3Term(PVM pVM);
360VMMR3DECL(void) IEMR3Relocate(PVM pVM);
361VMMR3_INT_DECL(VBOXSTRICTRC) IEMR3ProcessForceFlag(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rcStrict);
362/** @} */
363
364/** @} */
365
366RT_C_DECLS_END
367
368#endif /* !VBOX_INCLUDED_vmm_iem_h */
369
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