VirtualBox

source: vbox/trunk/include/VBox/vmm/iem.h@ 92070

Last change on this file since 92070 was 89974, checked in by vboxsync, 3 years ago

IEM: Added IEMExecOneIgnoreLock for use with split-lock cases. bugref:10052
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1/** @file
2 * IEM - Interpreted Execution Manager.
3 */
4
5/*
6 * Copyright (C) 2011-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_iem_h
27#define VBOX_INCLUDED_vmm_iem_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/types.h>
33#include <VBox/vmm/trpm.h>
34#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
35# include <VBox/vmm/hm_vmx.h>
36#endif
37#include <iprt/assert.h>
38
39
40RT_C_DECLS_BEGIN
41
42/** @defgroup grp_iem The Interpreted Execution Manager API.
43 * @ingroup grp_vmm
44 * @{
45 */
46
47/** @name IEMXCPTRAISEINFO_XXX - Extra info. on a recursive exception situation.
48 *
49 * This is primarily used by HM for working around a PGM limitation (see
50 * @bugref{6607}) and special NMI/IRET handling. In the future, this may be
51 * used for diagnostics.
52 *
53 * @{
54 */
55typedef uint32_t IEMXCPTRAISEINFO;
56/** Pointer to a IEMXCPTINFO type. */
57typedef IEMXCPTRAISEINFO *PIEMXCPTRAISEINFO;
58/** No addition info. available. */
59#define IEMXCPTRAISEINFO_NONE RT_BIT_32(0)
60/** Delivery of a \#AC caused another \#AC. */
61#define IEMXCPTRAISEINFO_AC_AC RT_BIT_32(1)
62/** Delivery of a \#PF caused another \#PF. */
63#define IEMXCPTRAISEINFO_PF_PF RT_BIT_32(2)
64/** Delivery of a \#PF caused some contributory exception. */
65#define IEMXCPTRAISEINFO_PF_CONTRIBUTORY_XCPT RT_BIT_32(3)
66/** Delivery of an external interrupt caused an exception. */
67#define IEMXCPTRAISEINFO_EXT_INT_XCPT RT_BIT_32(4)
68/** Delivery of an external interrupt caused an \#PF. */
69#define IEMXCPTRAISEINFO_EXT_INT_PF RT_BIT_32(5)
70/** Delivery of a software interrupt caused an exception. */
71#define IEMXCPTRAISEINFO_SOFT_INT_XCPT RT_BIT_32(6)
72/** Delivery of an NMI caused an exception. */
73#define IEMXCPTRAISEINFO_NMI_XCPT RT_BIT_32(7)
74/** Delivery of an NMI caused a \#PF. */
75#define IEMXCPTRAISEINFO_NMI_PF RT_BIT_32(8)
76/** Can re-execute the instruction at CS:RIP. */
77#define IEMXCPTRAISEINFO_CAN_REEXEC_INSTR RT_BIT_32(9)
78/** @} */
79
80
81/** @name IEMXCPTRAISE_XXX - Ways to handle a recursive exception condition.
82 * @{ */
83typedef enum IEMXCPTRAISE
84{
85 /** Raise the current (second) exception. */
86 IEMXCPTRAISE_CURRENT_XCPT = 0,
87 /** Re-raise the previous (first) event (for HM, unused by IEM). */
88 IEMXCPTRAISE_PREV_EVENT,
89 /** Re-execute instruction at CS:RIP (for HM, unused by IEM). */
90 IEMXCPTRAISE_REEXEC_INSTR,
91 /** Raise a \#DF exception. */
92 IEMXCPTRAISE_DOUBLE_FAULT,
93 /** Raise a triple fault. */
94 IEMXCPTRAISE_TRIPLE_FAULT,
95 /** Cause a CPU hang. */
96 IEMXCPTRAISE_CPU_HANG,
97 /** Invalid sequence of events. */
98 IEMXCPTRAISE_INVALID = 0x7fffffff
99} IEMXCPTRAISE;
100/** Pointer to a IEMXCPTRAISE type. */
101typedef IEMXCPTRAISE *PIEMXCPTRAISE;
102/** @} */
103
104
105/** @name Operand or addressing mode.
106 * @{ */
107typedef uint8_t IEMMODE;
108#define IEMMODE_16BIT 0
109#define IEMMODE_32BIT 1
110#define IEMMODE_64BIT 2
111/** @} */
112
113
114/** @name IEM_XCPT_FLAGS_XXX - flags for iemRaiseXcptOrInt.
115 * @{ */
116/** CPU exception. */
117#define IEM_XCPT_FLAGS_T_CPU_XCPT RT_BIT_32(0)
118/** External interrupt (from PIC, APIC, whatever). */
119#define IEM_XCPT_FLAGS_T_EXT_INT RT_BIT_32(1)
120/** Software interrupt (int or into, not bound).
121 * Returns to the following instruction */
122#define IEM_XCPT_FLAGS_T_SOFT_INT RT_BIT_32(2)
123/** Takes an error code. */
124#define IEM_XCPT_FLAGS_ERR RT_BIT_32(3)
125/** Takes a CR2. */
126#define IEM_XCPT_FLAGS_CR2 RT_BIT_32(4)
127/** Generated by the breakpoint instruction. */
128#define IEM_XCPT_FLAGS_BP_INSTR RT_BIT_32(5)
129/** Generated by a DRx instruction breakpoint and RF should be cleared. */
130#define IEM_XCPT_FLAGS_DRx_INSTR_BP RT_BIT_32(6)
131/** Generated by the icebp instruction. */
132#define IEM_XCPT_FLAGS_ICEBP_INSTR RT_BIT_32(7)
133/** Generated by the overflow instruction. */
134#define IEM_XCPT_FLAGS_OF_INSTR RT_BIT_32(8)
135/** @} */
136
137
138/** @name IEMTARGETCPU_XXX - IEM target CPU specification.
139 *
140 * This is a gross simpliciation of CPUMMICROARCH for dealing with really old
141 * CPUs which didn't have much in the way of hinting at supported instructions
142 * and features. This slowly changes with the introduction of CPUID with the
143 * Intel Pentium.
144 *
145 * @{
146 */
147/** The dynamic target CPU mode is for getting thru the BIOS and then use
148 * the debugger or modifying instruction behaviour (e.g. HLT) to switch to a
149 * different target CPU. */
150#define IEMTARGETCPU_DYNAMIC UINT32_C(0)
151/** Intel 8086/8088. */
152#define IEMTARGETCPU_8086 UINT32_C(1)
153/** NEC V20/V30.
154 * @remarks must be between 8086 and 80186. */
155#define IEMTARGETCPU_V20 UINT32_C(2)
156/** Intel 80186/80188. */
157#define IEMTARGETCPU_186 UINT32_C(3)
158/** Intel 80286. */
159#define IEMTARGETCPU_286 UINT32_C(4)
160/** Intel 80386. */
161#define IEMTARGETCPU_386 UINT32_C(5)
162/** Intel 80486. */
163#define IEMTARGETCPU_486 UINT32_C(6)
164/** Intel Pentium . */
165#define IEMTARGETCPU_PENTIUM UINT32_C(7)
166/** Intel PentiumPro. */
167#define IEMTARGETCPU_PPRO UINT32_C(8)
168/** A reasonably current CPU, probably newer than the pentium pro when it comes
169 * to the feature set and behaviour. Generally the CPUID info and CPU vendor
170 * dicates the behaviour here. */
171#define IEMTARGETCPU_CURRENT UINT32_C(9)
172/** @} */
173
174
175/** @name IEM status codes.
176 *
177 * Not quite sure how this will play out in the end, just aliasing safe status
178 * codes for now.
179 *
180 * @{ */
181#define VINF_IEM_RAISED_XCPT VINF_EM_RESCHEDULE
182/** @} */
183
184
185/** The CPUMCTX_EXTRN_XXX mask required to be cleared when interpreting anything.
186 * IEM will ASSUME the caller of IEM APIs has ensured these are already present. */
187#define IEM_CPUMCTX_EXTRN_MUST_MASK ( CPUMCTX_EXTRN_GPRS_MASK \
188 | CPUMCTX_EXTRN_RIP \
189 | CPUMCTX_EXTRN_RFLAGS \
190 | CPUMCTX_EXTRN_SS \
191 | CPUMCTX_EXTRN_CS \
192 | CPUMCTX_EXTRN_CR0 \
193 | CPUMCTX_EXTRN_CR3 \
194 | CPUMCTX_EXTRN_CR4 \
195 | CPUMCTX_EXTRN_APIC_TPR \
196 | CPUMCTX_EXTRN_EFER \
197 | CPUMCTX_EXTRN_DR7 )
198/** The CPUMCTX_EXTRN_XXX mask needed when injecting an exception/interrupt.
199 * IEM will import missing bits, callers are encouraged to make these registers
200 * available prior to injection calls if fetching state anyway. */
201#define IEM_CPUMCTX_EXTRN_XCPT_MASK ( IEM_CPUMCTX_EXTRN_MUST_MASK \
202 | CPUMCTX_EXTRN_CR2 \
203 | CPUMCTX_EXTRN_SREG_MASK \
204 | CPUMCTX_EXTRN_TABLE_MASK )
205/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
206 * IEMExecDecoded API not using memory. IEM will ASSUME the caller of IEM
207 * APIs has ensured these are already present.
208 * @note ASSUMES execution engine has checked for instruction breakpoints
209 * during decoding. */
210#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ( CPUMCTX_EXTRN_RIP \
211 | CPUMCTX_EXTRN_RFLAGS \
212 | CPUMCTX_EXTRN_SS /* for CPL */ \
213 | CPUMCTX_EXTRN_CS /* for mode */ \
214 | CPUMCTX_EXTRN_CR0 /* for mode */ \
215 | CPUMCTX_EXTRN_EFER /* for mode */ )
216/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
217 * IEMExecDecoded API using memory. IEM will ASSUME the caller of IEM
218 * APIs has ensured these are already present.
219 * @note ASSUMES execution engine has checked for instruction breakpoints
220 * during decoding. */
221#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
222 | CPUMCTX_EXTRN_CR3 /* for page tables */ \
223 | CPUMCTX_EXTRN_CR4 /* for mode paging mode */ \
224 | CPUMCTX_EXTRN_DR7 /* for memory breakpoints */ )
225
226#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
227/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmlaunchVmresume().
228 * IEM will ASSUME the caller has ensured these are already present. */
229# define IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
230 | CPUMCTX_EXTRN_CR2 \
231 | CPUMCTX_EXTRN_HWVIRT )
232
233/** The CPUMCTX_EXTRN_XXX mask that the IEM VM-exit code will import on-demand when
234 * needed, primarily because there are several IEM VM-exit interface functions and
235 * some of which may not cause a VM-exit at all.
236 *
237 * This is currently unused, but keeping it here in case we can get away a bit more
238 * fine-grained state handling.
239 *
240 * @note Update HM_CHANGED_VMX_VMEXIT_MASK if something here changes. */
241# define IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK ( CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 \
242 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 \
243 | CPUMCTX_EXTRN_EFER \
244 | CPUMCTX_EXTRN_SYSENTER_MSRS \
245 | CPUMCTX_EXTRN_OTHER_MSRS /* for PAT MSR */ \
246 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS \
247 | CPUMCTX_EXTRN_SREG_MASK \
248 | CPUMCTX_EXTRN_TR \
249 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR \
250 | CPUMCTX_EXTRN_HWVIRT )
251#endif
252
253#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
254/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecSvmVmexit().
255 * IEM will ASSUME the caller has ensured these are already present. */
256# define IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK ( CPUMCTX_EXTRN_RSP \
257 | CPUMCTX_EXTRN_RAX \
258 | CPUMCTX_EXTRN_RIP \
259 | CPUMCTX_EXTRN_RFLAGS \
260 | CPUMCTX_EXTRN_CS \
261 | CPUMCTX_EXTRN_SS \
262 | CPUMCTX_EXTRN_DS \
263 | CPUMCTX_EXTRN_ES \
264 | CPUMCTX_EXTRN_GDTR \
265 | CPUMCTX_EXTRN_IDTR \
266 | CPUMCTX_EXTRN_CR_MASK \
267 | CPUMCTX_EXTRN_EFER \
268 | CPUMCTX_EXTRN_DR6 \
269 | CPUMCTX_EXTRN_DR7 \
270 | CPUMCTX_EXTRN_OTHER_MSRS \
271 | CPUMCTX_EXTRN_HWVIRT \
272 | CPUMCTX_EXTRN_APIC_TPR \
273 | CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
274
275/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmrun().
276 * IEM will ASSUME the caller has ensured these are already present. */
277# define IEM_CPUMCTX_EXTRN_SVM_VMRUN_MASK IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK
278#endif
279
280VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPUCC pVCpu);
281VMMDECL(VBOXSTRICTRC) IEMExecOneEx(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
282VMMDECL(VBOXSTRICTRC) IEMExecOneWithPrefetchedByPC(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
283 const void *pvOpcodeBytes, size_t cbOpcodeBytes);
284VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
285VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPC(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
286 const void *pvOpcodeBytes, size_t cbOpcodeBytes);
287VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPCWritten(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
288 const void *pvOpcodeBytes, size_t cbOpcodeBytes,
289 uint32_t *pcbWritten);
290VMMDECL(VBOXSTRICTRC) IEMExecOneIgnoreLock(PVMCPUCC pVCpu);
291VMMDECL(VBOXSTRICTRC) IEMExecLots(PVMCPUCC pVCpu, uint32_t cMaxInstructions, uint32_t cPollRate, uint32_t *pcInstructions);
292/** Statistics returned by IEMExecForExits. */
293typedef struct IEMEXECFOREXITSTATS
294{
295 uint32_t cInstructions;
296 uint32_t cExits;
297 uint32_t cMaxExitDistance;
298 uint32_t cReserved;
299} IEMEXECFOREXITSTATS;
300/** Pointer to statistics returned by IEMExecForExits. */
301typedef IEMEXECFOREXITSTATS *PIEMEXECFOREXITSTATS;
302VMMDECL(VBOXSTRICTRC) IEMExecForExits(PVMCPUCC pVCpu, uint32_t fWillExit, uint32_t cMinInstructions, uint32_t cMaxInstructions,
303 uint32_t cMaxInstructionsWithoutExits, PIEMEXECFOREXITSTATS pStats);
304VMMDECL(VBOXSTRICTRC) IEMInjectTrpmEvent(PVMCPUCC pVCpu);
305VMM_INT_DECL(VBOXSTRICTRC) IEMInjectTrap(PVMCPUCC pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2,
306 uint8_t cbInstr);
307
308VMM_INT_DECL(int) IEMBreakpointSet(PVM pVM, RTGCPTR GCPtrBp);
309VMM_INT_DECL(int) IEMBreakpointClear(PVM pVM, RTGCPTR GCPtrBp);
310
311VMM_INT_DECL(void) IEMTlbInvalidateAll(PVMCPUCC pVCpu, bool fVmm);
312VMM_INT_DECL(void) IEMTlbInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtr);
313VMM_INT_DECL(void) IEMTlbInvalidateAllPhysical(PVMCPUCC pVCpu);
314VMM_INT_DECL(bool) IEMGetCurrentXcpt(PVMCPUCC pVCpu, uint8_t *puVector, uint32_t *pfFlags, uint32_t *puErr,
315 uint64_t *puCr2);
316VMM_INT_DECL(IEMXCPTRAISE) IEMEvaluateRecursiveXcpt(PVMCPUCC pVCpu, uint32_t fPrevFlags, uint8_t uPrevVector, uint32_t fCurFlags,
317 uint8_t uCurVector, PIEMXCPTRAISEINFO pXcptRaiseInfo);
318
319/** @name Given Instruction Interpreters
320 * @{ */
321VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPUCC pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
322 bool fRepPrefix, uint8_t cbInstr, uint8_t iEffSeg, bool fIoChecked);
323VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPUCC pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
324 bool fRepPrefix, uint8_t cbInstr, bool fIoChecked);
325VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedOut(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);
326VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedIn(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);
327VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxWrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg);
328VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxRead(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg);
329VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClts(PVMCPUCC pVCpu, uint8_t cbInstr);
330VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedLmsw(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t uValue, RTGCPTR GCPtrEffDst);
331VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedXsetbv(PVMCPUCC pVCpu, uint8_t cbInstr);
332VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWbinvd(PVMCPUCC pVCpu, uint8_t cbInstr);
333VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvd(PVMCPUCC pVCpu, uint8_t cbInstr);
334VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpg(PVMCPUCC pVCpu, uint8_t cbInstr, RTGCPTR GCPtrPage);
335VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvpcid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDesc,
336 uint64_t uType);
337VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedCpuid(PVMCPUCC pVCpu, uint8_t cbInstr);
338VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdpmc(PVMCPUCC pVCpu, uint8_t cbInstr);
339VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtsc(PVMCPUCC pVCpu, uint8_t cbInstr);
340VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtscp(PVMCPUCC pVCpu, uint8_t cbInstr);
341VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdmsr(PVMCPUCC pVCpu, uint8_t cbInstr);
342VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWrmsr(PVMCPUCC pVCpu, uint8_t cbInstr);
343VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMonitor(PVMCPUCC pVCpu, uint8_t cbInstr);
344VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMwait(PVMCPUCC pVCpu, uint8_t cbInstr);
345VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedHlt(PVMCPUCC pVCpu, uint8_t cbInstr);
346
347#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
348VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClgi(PVMCPUCC pVCpu, uint8_t cbInstr);
349VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedStgi(PVMCPUCC pVCpu, uint8_t cbInstr);
350VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmload(PVMCPUCC pVCpu, uint8_t cbInstr);
351VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmsave(PVMCPUCC pVCpu, uint8_t cbInstr);
352VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpga(PVMCPUCC pVCpu, uint8_t cbInstr);
353VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmrun(PVMCPUCC pVCpu, uint8_t cbInstr);
354VMM_INT_DECL(VBOXSTRICTRC) IEMExecSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2);
355#endif
356
357#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
358VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst);
359VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val);
360VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Val, bool fWrite);
361VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu);
362VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu);
363VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending);
364VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
365VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu);
366VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu);
367VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector);
368VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
369VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr);
370VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
371VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
372VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
373VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t uExitQual);
374VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
375VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
376VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
377VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
378VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
379VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId);
380VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
381VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr);
382VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
383#endif
384/** @} */
385
386
387/** @defgroup grp_iem_r3 The IEM Host Context Ring-3 API.
388 * @{
389 */
390VMMR3DECL(int) IEMR3Init(PVM pVM);
391VMMR3DECL(int) IEMR3Term(PVM pVM);
392VMMR3DECL(void) IEMR3Relocate(PVM pVM);
393VMMR3_INT_DECL(VBOXSTRICTRC) IEMR3ProcessForceFlag(PVM pVM, PVMCPUCC pVCpu, VBOXSTRICTRC rcStrict);
394/** @} */
395
396/** @} */
397
398RT_C_DECLS_END
399
400#endif /* !VBOX_INCLUDED_vmm_iem_h */
401
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