pdmdev.h@ 84119

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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmqueue.h>
34	#include <VBox/vmm/pdmtask.h>
35	#ifdef IN_RING3
36	# include <VBox/vmm/pdmthread.h>
37	#endif
38	#include <VBox/vmm/pdmifs.h>
39	#include <VBox/vmm/pdmins.h>
40	#include <VBox/vmm/pdmcommon.h>
41	#include <VBox/vmm/pdmpcidev.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/tm.h>
44	#include <VBox/vmm/ssm.h>
45	#include <VBox/vmm/cfgm.h>
46	#include <VBox/vmm/cpum.h>
47	#include <VBox/vmm/dbgf.h>
48	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
49	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
50	#include <iprt/stdarg.h>
51	#include <iprt/list.h>
52
53
54	RT_C_DECLS_BEGIN
55
56	/** @defgroup grp_pdm_device The PDM Devices API
57	* @ingroup grp_pdm
58	* @{
59	*/
60
61	/**
62	* Construct a device instance for a VM.
63	*
64	* @returns VBox status.
65	* @param pDevIns The device instance data. If the registration structure
66	* is needed, it can be accessed thru pDevIns->pReg.
67	* @param iInstance Instance number. Use this to figure out which registers
68	* and such to use. The instance number is also found in
69	* pDevIns->iInstance, but since it's likely to be
70	* frequently used PDM passes it as parameter.
71	* @param pCfg Configuration node handle for the driver. This is
72	* expected to be in high demand in the constructor and is
73	* therefore passed as an argument. When using it at other
74	* times, it can be found in pDevIns->pCfg.
75	*/
76	typedef DECLCALLBACK(int) FNPDMDEVCONSTRUCT(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg);
77	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
78	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
79
80	/**
81	* Destruct a device instance.
82	*
83	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
84	* resources can be freed correctly.
85	*
86	* @returns VBox status.
87	* @param pDevIns The device instance data.
88	*
89	* @remarks The device critical section is not entered. The routine may delete
90	* the critical section, so the caller cannot exit it.
91	*/
92	typedef DECLCALLBACK(int) FNPDMDEVDESTRUCT(PPDMDEVINS pDevIns);
93	/** Pointer to a FNPDMDEVDESTRUCT() function. */
94	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
95
96	/**
97	* Device relocation callback.
98	*
99	* This is called when the instance data has been relocated in raw-mode context
100	* (RC). It is also called when the RC hypervisor selects changes. The device
101	* must fixup all necessary pointers and re-query all interfaces to other RC
102	* devices and drivers.
103	*
104	* Before the RC code is executed the first time, this function will be called
105	* with a 0 delta so RC pointer calculations can be one in one place.
106	*
107	* @param pDevIns Pointer to the device instance.
108	* @param offDelta The relocation delta relative to the old location.
109	*
110	* @remarks A relocation CANNOT fail.
111	*
112	* @remarks The device critical section is not entered. The relocations should
113	* not normally require any locking.
114	*/
115	typedef DECLCALLBACK(void) FNPDMDEVRELOCATE(PPDMDEVINS pDevIns, RTGCINTPTR offDelta);
116	/** Pointer to a FNPDMDEVRELOCATE() function. */
117	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
118
119	/**
120	* Power On notification.
121	*
122	* @returns VBox status.
123	* @param pDevIns The device instance data.
124	*
125	* @remarks Caller enters the device critical section.
126	*/
127	typedef DECLCALLBACK(void) FNPDMDEVPOWERON(PPDMDEVINS pDevIns);
128	/** Pointer to a FNPDMDEVPOWERON() function. */
129	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
130
131	/**
132	* Reset notification.
133	*
134	* @returns VBox status.
135	* @param pDevIns The device instance data.
136	*
137	* @remarks Caller enters the device critical section.
138	*/
139	typedef DECLCALLBACK(void) FNPDMDEVRESET(PPDMDEVINS pDevIns);
140	/** Pointer to a FNPDMDEVRESET() function. */
141	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
142
143	/**
144	* Soft reset notification.
145	*
146	* This is mainly for emulating the 286 style protected mode exits, in which
147	* most devices should remain in their current state.
148	*
149	* @returns VBox status.
150	* @param pDevIns The device instance data.
151	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
152	*
153	* @remarks Caller enters the device critical section.
154	*/
155	typedef DECLCALLBACK(void) FNPDMDEVSOFTRESET(PPDMDEVINS pDevIns, uint32_t fFlags);
156	/** Pointer to a FNPDMDEVSOFTRESET() function. */
157	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
158
159	/** @name PDMVMRESET_F_XXX - VM reset flags.
160	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
161	* reset via PDMDevHlpVMReset.
162	* @{ */
163	/** Unknown reason. */
164	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
165	/** GIM triggered reset. */
166	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
167	/** The last source always causing hard resets. */
168	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
169	/** ACPI triggered reset. */
170	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
171	/** PS/2 system port A (92h) reset. */
172	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
173	/** Keyboard reset. */
174	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
175	/** Tripple fault. */
176	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
177	/** Reset source mask. */
178	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
179	/** @} */
180
181	/**
182	* Suspend notification.
183	*
184	* @returns VBox status.
185	* @param pDevIns The device instance data.
186	* @thread EMT(0)
187	*
188	* @remarks Caller enters the device critical section.
189	*/
190	typedef DECLCALLBACK(void) FNPDMDEVSUSPEND(PPDMDEVINS pDevIns);
191	/** Pointer to a FNPDMDEVSUSPEND() function. */
192	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
193
194	/**
195	* Resume notification.
196	*
197	* @returns VBox status.
198	* @param pDevIns The device instance data.
199	*
200	* @remarks Caller enters the device critical section.
201	*/
202	typedef DECLCALLBACK(void) FNPDMDEVRESUME(PPDMDEVINS pDevIns);
203	/** Pointer to a FNPDMDEVRESUME() function. */
204	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
205
206	/**
207	* Power Off notification.
208	*
209	* This is always called when VMR3PowerOff is called.
210	* There will be no callback when hot plugging devices.
211	*
212	* @param pDevIns The device instance data.
213	* @thread EMT(0)
214	*
215	* @remarks Caller enters the device critical section.
216	*/
217	typedef DECLCALLBACK(void) FNPDMDEVPOWEROFF(PPDMDEVINS pDevIns);
218	/** Pointer to a FNPDMDEVPOWEROFF() function. */
219	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
220
221	/**
222	* Attach command.
223	*
224	* This is called to let the device attach to a driver for a specified LUN
225	* at runtime. This is not called during VM construction, the device
226	* constructor has to attach to all the available drivers.
227	*
228	* This is like plugging in the keyboard or mouse after turning on the PC.
229	*
230	* @returns VBox status code.
231	* @param pDevIns The device instance.
232	* @param iLUN The logical unit which is being attached.
233	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
234	*
235	* @remarks Caller enters the device critical section.
236	*/
237	typedef DECLCALLBACK(int) FNPDMDEVATTACH(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags);
238	/** Pointer to a FNPDMDEVATTACH() function. */
239	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
240
241	/**
242	* Detach notification.
243	*
244	* This is called when a driver is detaching itself from a LUN of the device.
245	* The device should adjust its state to reflect this.
246	*
247	* This is like unplugging the network cable to use it for the laptop or
248	* something while the PC is still running.
249	*
250	* @param pDevIns The device instance.
251	* @param iLUN The logical unit which is being detached.
252	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
253	*
254	* @remarks Caller enters the device critical section.
255	*/
256	typedef DECLCALLBACK(void) FNPDMDEVDETACH(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags);
257	/** Pointer to a FNPDMDEVDETACH() function. */
258	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
259
260	/**
261	* Query the base interface of a logical unit.
262	*
263	* @returns VBOX status code.
264	* @param pDevIns The device instance.
265	* @param iLUN The logicial unit to query.
266	* @param ppBase Where to store the pointer to the base interface of the LUN.
267	*
268	* @remarks The device critical section is not entered.
269	*/
270	typedef DECLCALLBACK(int) FNPDMDEVQUERYINTERFACE(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase);
271	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
272	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
273
274	/**
275	* Init complete notification (after ring-0 & RC init since 5.1).
276	*
277	* This can be done to do communication with other devices and other
278	* initialization which requires everything to be in place.
279	*
280	* @returns VBOX status code.
281	* @param pDevIns The device instance.
282	*
283	* @remarks Caller enters the device critical section.
284	*/
285	typedef DECLCALLBACK(int) FNPDMDEVINITCOMPLETE(PPDMDEVINS pDevIns);
286	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
287	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
288
289
290	/**
291	* The context of a pfnMemSetup call.
292	*/
293	typedef enum PDMDEVMEMSETUPCTX
294	{
295	/** Invalid zero value. */
296	PDMDEVMEMSETUPCTX_INVALID = 0,
297	/** After construction. */
298	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
299	/** After reset. */
300	PDMDEVMEMSETUPCTX_AFTER_RESET,
301	/** Type size hack. */
302	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
303	} PDMDEVMEMSETUPCTX;
304
305
306	/**
307	* PDM Device Registration Structure.
308	*
309	* This structure is used when registering a device from VBoxInitDevices() in HC
310	* Ring-3. PDM will continue use till the VM is terminated.
311	*
312	* @note The first part is the same in every context.
313	*/
314	typedef struct PDMDEVREGR3
315	{
316	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
317	uint32_t u32Version;
318	/** Reserved, must be zero. */
319	uint32_t uReserved0;
320	/** Device name, must match the ring-3 one. */
321	char szName[32];
322	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
323	uint32_t fFlags;
324	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
325	uint32_t fClass;
326	/** Maximum number of instances (per VM). */
327	uint32_t cMaxInstances;
328	/** The shared data structure version number. */
329	uint32_t uSharedVersion;
330	/** Size of the instance data. */
331	uint32_t cbInstanceShared;
332	/** Size of the ring-0 instance data. */
333	uint32_t cbInstanceCC;
334	/** Size of the raw-mode instance data. */
335	uint32_t cbInstanceRC;
336	/** Max number of PCI devices. */
337	uint16_t cMaxPciDevices;
338	/** Max number of MSI-X vectors in any of the PCI devices. */
339	uint16_t cMaxMsixVectors;
340	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
341	* remain unchanged from registration till VM destruction. */
342	const char *pszDescription;
343
344	/** Name of the raw-mode context module (no path).
345	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
346	const char *pszRCMod;
347	/** Name of the ring-0 module (no path).
348	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
349	const char *pszR0Mod;
350
351	/** Construct instance - required. */
352	PFNPDMDEVCONSTRUCT pfnConstruct;
353	/** Destruct instance - optional.
354	* Critical section NOT entered (will be destroyed). */
355	PFNPDMDEVDESTRUCT pfnDestruct;
356	/** Relocation command - optional.
357	* Critical section NOT entered. */
358	PFNPDMDEVRELOCATE pfnRelocate;
359	/**
360	* Memory setup callback.
361	*
362	* @param pDevIns The device instance data.
363	* @param enmCtx Indicates the context of the call.
364	* @remarks The critical section is entered prior to calling this method.
365	*/
366	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
367	/** Power on notification - optional.
368	* Critical section is entered. */
369	PFNPDMDEVPOWERON pfnPowerOn;
370	/** Reset notification - optional.
371	* Critical section is entered. */
372	PFNPDMDEVRESET pfnReset;
373	/** Suspend notification - optional.
374	* Critical section is entered. */
375	PFNPDMDEVSUSPEND pfnSuspend;
376	/** Resume notification - optional.
377	* Critical section is entered. */
378	PFNPDMDEVRESUME pfnResume;
379	/** Attach command - optional.
380	* Critical section is entered. */
381	PFNPDMDEVATTACH pfnAttach;
382	/** Detach notification - optional.
383	* Critical section is entered. */
384	PFNPDMDEVDETACH pfnDetach;
385	/** Query a LUN base interface - optional.
386	* Critical section is NOT entered. */
387	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
388	/** Init complete notification - optional.
389	* Critical section is entered. */
390	PFNPDMDEVINITCOMPLETE pfnInitComplete;
391	/** Power off notification - optional.
392	* Critical section is entered. */
393	PFNPDMDEVPOWEROFF pfnPowerOff;
394	/** Software system reset notification - optional.
395	* Critical section is entered. */
396	PFNPDMDEVSOFTRESET pfnSoftReset;
397
398	/** @name Reserved for future extensions, must be zero.
399	* @{ */
400	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
401	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
402	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
403	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
406	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
407	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
408	/** @} */
409
410	/** Initialization safty marker. */
411	uint32_t u32VersionEnd;
412	} PDMDEVREGR3;
413	/** Pointer to a PDM Device Structure. */
414	typedef PDMDEVREGR3 *PPDMDEVREGR3;
415	/** Const pointer to a PDM Device Structure. */
416	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
417	/** Current DEVREGR3 version number. */
418	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
419
420
421	/** PDM Device Flags.
422	* @{ */
423	/** This flag is used to indicate that the device has a R0 component. */
424	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
425	/** Requires the ring-0 component, ignore configuration values. */
426	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
427	/** Requires the ring-0 component, ignore configuration values. */
428	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
429
430	/** This flag is used to indicate that the device has a RC component. */
431	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
432	/** Requires the raw-mode component, ignore configuration values. */
433	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
434	/** Requires the raw-mode component, ignore configuration values. */
435	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
436
437	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
438	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
439
440	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
441	* The bit count for the current host.
442	* @note Superfluous, but still around for hysterical raisins. */
443	#if HC_ARCH_BITS == 32
444	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
445	#elif HC_ARCH_BITS == 64
446	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
447	#else
448	# error Unsupported HC_ARCH_BITS value.
449	#endif
450	/** The host bit count mask. */
451	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
452
453	/** The device support only 32-bit guests. */
454	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
455	/** The device support only 64-bit guests. */
456	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
457	/** The device support both 32-bit & 64-bit guests. */
458	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
459	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
460	* The guest bit count for the current compilation. */
461	#if GC_ARCH_BITS == 32
462	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
463	#elif GC_ARCH_BITS == 64
464	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
465	#else
466	# error Unsupported GC_ARCH_BITS value.
467	#endif
468	/** The guest bit count mask. */
469	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
470
471	/** A convenience. */
472	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
473
474	/** Indicates that the device needs to be notified before the drivers when suspending. */
475	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
476	/** Indicates that the device needs to be notified before the drivers when powering off. */
477	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
478	/** Indicates that the device needs to be notified before the drivers when resetting. */
479	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
480
481	/** This flag is used to indicate that the device has been converted to the
482	* new device style. */
483	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
484
485	/** @} */
486
487
488	/** PDM Device Classes.
489	* The order is important, lower bit earlier instantiation.
490	* @{ */
491	/** Architecture device. */
492	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
493	/** Architecture BIOS device. */
494	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
495	/** PCI bus brigde. */
496	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
497	/** ISA bus brigde. */
498	#define PDM_DEVREG_CLASS_BUS_ISA RT_BIT(3)
499	/** Input device (mouse, keyboard, joystick, HID, ...). */
500	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
501	/** Interrupt controller (PIC). */
502	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
503	/** Interval controoler (PIT). */
504	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
505	/** RTC/CMOS. */
506	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
507	/** DMA controller. */
508	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
509	/** VMM Device. */
510	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
511	/** Graphics device, like VGA. */
512	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
513	/** Storage controller device. */
514	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
515	/** Network interface controller. */
516	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
517	/** Audio. */
518	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
519	/** USB HIC. */
520	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
521	/** ACPI. */
522	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
523	/** Serial controller device. */
524	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
525	/** Parallel controller device */
526	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
527	/** Host PCI pass-through device */
528	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
529	/** Misc devices (always last). */
530	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
531	/** @} */
532
533
534	/**
535	* PDM Device Registration Structure, ring-0.
536	*
537	* This structure is used when registering a device from VBoxInitDevices() in HC
538	* Ring-0. PDM will continue use till the VM is terminated.
539	*/
540	typedef struct PDMDEVREGR0
541	{
542	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
543	uint32_t u32Version;
544	/** Reserved, must be zero. */
545	uint32_t uReserved0;
546	/** Device name, must match the ring-3 one. */
547	char szName[32];
548	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
549	uint32_t fFlags;
550	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
551	uint32_t fClass;
552	/** Maximum number of instances (per VM). */
553	uint32_t cMaxInstances;
554	/** The shared data structure version number. */
555	uint32_t uSharedVersion;
556	/** Size of the instance data. */
557	uint32_t cbInstanceShared;
558	/** Size of the ring-0 instance data. */
559	uint32_t cbInstanceCC;
560	/** Size of the raw-mode instance data. */
561	uint32_t cbInstanceRC;
562	/** Max number of PCI devices. */
563	uint16_t cMaxPciDevices;
564	/** Max number of MSI-X vectors in any of the PCI devices. */
565	uint16_t cMaxMsixVectors;
566	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
567	* remain unchanged from registration till VM destruction. */
568	const char *pszDescription;
569
570	/**
571	* Early construction callback (optional).
572	*
573	* This is called right after the device instance structure has been allocated
574	* and before the ring-3 constructor gets called.
575	*
576	* @returns VBox status code.
577	* @param pDevIns The device instance data.
578	* @note The destructure is always called, regardless of the return status.
579	*/
580	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
581
582	/**
583	* Regular construction callback (optional).
584	*
585	* This is called after (or during) the ring-3 constructor.
586	*
587	* @returns VBox status code.
588	* @param pDevIns The device instance data.
589	* @note The destructure is always called, regardless of the return status.
590	*/
591	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
592
593	/**
594	* Destructor (optional).
595	*
596	* This is called after the ring-3 destruction. This is not called if ring-3
597	* fails to trigger it (e.g. process is killed or crashes).
598	*
599	* @param pDevIns The device instance data.
600	*/
601	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
602
603	/**
604	* Final destructor (optional).
605	*
606	* This is called right before the memory is freed, which happens when the
607	* VM/GVM object is destroyed. This is always called.
608	*
609	* @param pDevIns The device instance data.
610	*/
611	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
612
613	/**
614	* Generic request handler (optional).
615	*
616	* @param pDevIns The device instance data.
617	* @param uReq Device specific request.
618	* @param uArg Request argument.
619	*/
620	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
621
622	/** @name Reserved for future extensions, must be zero.
623	* @{ */
624	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
625	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
626	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
627	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
630	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
631	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
632	/** @} */
633
634	/** Initialization safty marker. */
635	uint32_t u32VersionEnd;
636	} PDMDEVREGR0;
637	/** Pointer to a ring-0 PDM device registration structure. */
638	typedef PDMDEVREGR0 *PPDMDEVREGR0;
639	/** Pointer to a const ring-0 PDM device registration structure. */
640	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
641	/** Current DEVREGR0 version number. */
642	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
643
644
645	/**
646	* PDM Device Registration Structure, raw-mode
647	*
648	* At the moment, this structure is mostly here to match the other two contexts.
649	*/
650	typedef struct PDMDEVREGRC
651	{
652	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
653	uint32_t u32Version;
654	/** Reserved, must be zero. */
655	uint32_t uReserved0;
656	/** Device name, must match the ring-3 one. */
657	char szName[32];
658	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
659	uint32_t fFlags;
660	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
661	uint32_t fClass;
662	/** Maximum number of instances (per VM). */
663	uint32_t cMaxInstances;
664	/** The shared data structure version number. */
665	uint32_t uSharedVersion;
666	/** Size of the instance data. */
667	uint32_t cbInstanceShared;
668	/** Size of the ring-0 instance data. */
669	uint32_t cbInstanceCC;
670	/** Size of the raw-mode instance data. */
671	uint32_t cbInstanceRC;
672	/** Max number of PCI devices. */
673	uint16_t cMaxPciDevices;
674	/** Max number of MSI-X vectors in any of the PCI devices. */
675	uint16_t cMaxMsixVectors;
676	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
677	* remain unchanged from registration till VM destruction. */
678	const char *pszDescription;
679
680	/**
681	* Constructor callback.
682	*
683	* This is called much later than both the ring-0 and ring-3 constructors, since
684	* raw-mode v2 require a working VMM to run actual code.
685	*
686	* @returns VBox status code.
687	* @param pDevIns The device instance data.
688	* @note The destructure is always called, regardless of the return status.
689	*/
690	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
691
692	/** @name Reserved for future extensions, must be zero.
693	* @{ */
694	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
695	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
696	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
697	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
700	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
701	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
702	/** @} */
703
704	/** Initialization safty marker. */
705	uint32_t u32VersionEnd;
706	} PDMDEVREGRC;
707	/** Pointer to a raw-mode PDM device registration structure. */
708	typedef PDMDEVREGRC *PPDMDEVREGRC;
709	/** Pointer to a const raw-mode PDM device registration structure. */
710	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
711	/** Current DEVREGRC version number. */
712	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
713
714
715
716	/** @def PDM_DEVREG_VERSION
717	* Current DEVREG version number. */
718	/** @typedef PDMDEVREGR3
719	* A current context PDM device registration structure. */
720	/** @typedef PPDMDEVREGR3
721	* Pointer to a current context PDM device registration structure. */
722	/** @typedef PCPDMDEVREGR3
723	* Pointer to a const current context PDM device registration structure. */
724	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
725	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
726	typedef PDMDEVREGR3 PDMDEVREG;
727	typedef PPDMDEVREGR3 PPDMDEVREG;
728	typedef PCPDMDEVREGR3 PCPDMDEVREG;
729	#elif defined(IN_RING0)
730	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
731	typedef PDMDEVREGR0 PDMDEVREG;
732	typedef PPDMDEVREGR0 PPDMDEVREG;
733	typedef PCPDMDEVREGR0 PCPDMDEVREG;
734	#elif defined(IN_RC)
735	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
736	typedef PDMDEVREGRC PDMDEVREG;
737	typedef PPDMDEVREGRC PPDMDEVREG;
738	typedef PCPDMDEVREGRC PCPDMDEVREG;
739	#else
740	# error "Not IN_RING3, IN_RING0 or IN_RC"
741	#endif
742
743
744	/**
745	* Device registrations for ring-0 modules.
746	*
747	* This structure is used directly and must therefore reside in persistent
748	* memory (i.e. the data section).
749	*/
750	typedef struct PDMDEVMODREGR0
751	{
752	/** The structure version (PDM_DEVMODREGR0_VERSION). */
753	uint32_t u32Version;
754	/** Number of devices in the array papDevRegs points to. */
755	uint32_t cDevRegs;
756	/** Pointer to device registration structures. */
757	PCPDMDEVREGR0 *papDevRegs;
758	/** The ring-0 module handle - PDM internal, fingers off. */
759	void *hMod;
760	/** List entry - PDM internal, fingers off. */
761	RTLISTNODE ListEntry;
762	} PDMDEVMODREGR0;
763	/** Pointer to device registriations for a ring-0 module. */
764	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
765	/** Current PDMDEVMODREGR0 version number. */
766	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
767
768
769	/** @name IRQ Level for use with the *SetIrq APIs.
770	* @{
771	*/
772	/** Assert the IRQ (can assume value 1). */
773	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
774	/** Deassert the IRQ (can assume value 0). */
775	#define PDM_IRQ_LEVEL_LOW 0
776	/** flip-flop - deassert and then assert the IRQ again immediately. */
777	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
778	/** @} */
779
780	/**
781	* Registration record for MSI/MSI-X emulation.
782	*/
783	typedef struct PDMMSIREG
784	{
785	/** Number of MSI interrupt vectors, 0 if MSI not supported */
786	uint16_t cMsiVectors;
787	/** Offset of MSI capability */
788	uint8_t iMsiCapOffset;
789	/** Offset of next capability to MSI */
790	uint8_t iMsiNextOffset;
791	/** If we support 64-bit MSI addressing */
792	bool fMsi64bit;
793	/** If we do not support per-vector masking */
794	bool fMsiNoMasking;
795
796	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
797	uint16_t cMsixVectors;
798	/** Offset of MSI-X capability */
799	uint8_t iMsixCapOffset;
800	/** Offset of next capability to MSI-X */
801	uint8_t iMsixNextOffset;
802	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
803	uint8_t iMsixBar;
804	} PDMMSIREG;
805	typedef PDMMSIREG *PPDMMSIREG;
806
807	/**
808	* PCI Bus registration structure.
809	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
810	*/
811	typedef struct PDMPCIBUSREGR3
812	{
813	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
814	uint32_t u32Version;
815
816	/**
817	* Registers the device with the default PCI bus.
818	*
819	* @returns VBox status code.
820	* @param pDevIns Device instance of the PCI Bus.
821	* @param pPciDev The PCI device structure.
822	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
823	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
824	* device number (0-31).
825	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
826	* function number (0-7).
827	* @param pszName Device name (static but not unique).
828	*
829	* @remarks Caller enters the PDM critical section.
830	*/
831	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
832	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
833
834	/**
835	* Initialize MSI or MSI-X emulation support in a PCI device.
836	*
837	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
838	* vast majority of device emulation it covers everything necessary. It's
839	* fully automatic, taking care of all BAR and config space requirements,
840	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
841	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
842	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
843	*
844	* A device not using this can still offer MSI/MSI-X. In this case it's
845	* completely up to the device (in the MSI-X case) to create/register the
846	* necessary MMIO BAR, handle all config space/BAR updating and take care
847	* of delivering the interrupts appropriately.
848	*
849	* @returns VBox status code.
850	* @param pDevIns Device instance of the PCI Bus.
851	* @param pPciDev The PCI device structure.
852	* @param pMsiReg MSI emulation registration structure
853	* @remarks Caller enters the PDM critical section.
854	*/
855	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
856
857	/**
858	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
859	*
860	* @returns VBox status code.
861	* @param pDevIns Device instance of the PCI Bus.
862	* @param pPciDev The PCI device structure.
863	* @param iRegion The region number.
864	* @param cbRegion Size of the region.
865	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
866	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
867	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
868	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
869	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
870	* @a fFlags, UINT64_MAX if no handle is passed
871	* (old style).
872	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
873	* is given.
874	* @remarks Caller enters the PDM critical section.
875	*/
876	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
877	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
878	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
879
880	/**
881	* Register PCI configuration space read/write intercept callbacks.
882	*
883	* @param pDevIns Device instance of the PCI Bus.
884	* @param pPciDev The PCI device structure.
885	* @param pfnRead Pointer to the user defined PCI config read function.
886	* @param pfnWrite Pointer to the user defined PCI config write function.
887	* to call default PCI config write function. Can be NULL.
888	* @remarks Caller enters the PDM critical section.
889	* @thread EMT
890	*/
891	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
892	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
893
894	/**
895	* Perform a PCI configuration space write, bypassing interception.
896	*
897	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
898	*
899	* @returns Strict VBox status code (mainly DBGFSTOP).
900	* @param pDevIns Device instance of the PCI Bus.
901	* @param pPciDev The PCI device which config space is being read.
902	* @param uAddress The config space address.
903	* @param cb The size of the read: 1, 2 or 4 bytes.
904	* @param u32Value The value to write.
905	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
906	* that the (root) bus will have done that already.
907	*/
908	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
909	uint32_t uAddress, unsigned cb, uint32_t u32Value));
910
911	/**
912	* Perform a PCI configuration space read, bypassing interception.
913	*
914	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
915	*
916	* @returns Strict VBox status code (mainly DBGFSTOP).
917	* @param pDevIns Device instance of the PCI Bus.
918	* @param pPciDev The PCI device which config space is being read.
919	* @param uAddress The config space address.
920	* @param cb The size of the read: 1, 2 or 4 bytes.
921	* @param pu32Value Where to return the value.
922	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
923	* that the (root) bus will have done that already.
924	*/
925	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
926	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
927
928	/**
929	* Set the IRQ for a PCI device.
930	*
931	* @param pDevIns Device instance of the PCI Bus.
932	* @param pPciDev The PCI device structure.
933	* @param iIrq IRQ number to set.
934	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
935	* @param uTagSrc The IRQ tag and source (for tracing).
936	* @remarks Caller enters the PDM critical section.
937	*/
938	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
939
940	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
941	uint32_t u32EndVersion;
942	} PDMPCIBUSREGR3;
943	/** Pointer to a PCI bus registration structure. */
944	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
945	/** Current PDMPCIBUSREGR3 version number. */
946	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
947
948	/**
949	* PCI Bus registration structure for ring-0.
950	*/
951	typedef struct PDMPCIBUSREGR0
952	{
953	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
954	uint32_t u32Version;
955	/** The PCI bus number (from ring-3 registration). */
956	uint32_t iBus;
957	/**
958	* Set the IRQ for a PCI device.
959	*
960	* @param pDevIns Device instance of the PCI Bus.
961	* @param pPciDev The PCI device structure.
962	* @param iIrq IRQ number to set.
963	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
964	* @param uTagSrc The IRQ tag and source (for tracing).
965	* @remarks Caller enters the PDM critical section.
966	*/
967	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
968	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
969	uint32_t u32EndVersion;
970	} PDMPCIBUSREGR0;
971	/** Pointer to a PCI bus ring-0 registration structure. */
972	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
973	/** Current PDMPCIBUSREGR0 version number. */
974	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
975
976	/**
977	* PCI Bus registration structure for raw-mode.
978	*/
979	typedef struct PDMPCIBUSREGRC
980	{
981	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
982	uint32_t u32Version;
983	/** The PCI bus number (from ring-3 registration). */
984	uint32_t iBus;
985	/**
986	* Set the IRQ for a PCI device.
987	*
988	* @param pDevIns Device instance of the PCI Bus.
989	* @param pPciDev The PCI device structure.
990	* @param iIrq IRQ number to set.
991	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
992	* @param uTagSrc The IRQ tag and source (for tracing).
993	* @remarks Caller enters the PDM critical section.
994	*/
995	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
996	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
997	uint32_t u32EndVersion;
998	} PDMPCIBUSREGRC;
999	/** Pointer to a PCI bus raw-mode registration structure. */
1000	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1001	/** Current PDMPCIBUSREGRC version number. */
1002	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1003
1004	/** PCI bus registration structure for the current context. */
1005	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1006	/** Pointer to a PCI bus registration structure for the current context. */
1007	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1008	/** PCI bus registration structure version for the current context. */
1009	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1010
1011
1012	/**
1013	* PCI Bus RC helpers.
1014	*/
1015	typedef struct PDMPCIHLPRC
1016	{
1017	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1018	uint32_t u32Version;
1019
1020	/**
1021	* Set an ISA IRQ.
1022	*
1023	* @param pDevIns PCI device instance.
1024	* @param iIrq IRQ number to set.
1025	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1026	* @param uTagSrc The IRQ tag and source (for tracing).
1027	* @thread EMT only.
1028	*/
1029	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1030
1031	/**
1032	* Set an I/O-APIC IRQ.
1033	*
1034	* @param pDevIns PCI device instance.
1035	* @param iIrq IRQ number to set.
1036	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1037	* @param uTagSrc The IRQ tag and source (for tracing).
1038	* @thread EMT only.
1039	*/
1040	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1041
1042	/**
1043	* Send an MSI.
1044	*
1045	* @param pDevIns PCI device instance.
1046	* @param GCPhys Physical address MSI request was written.
1047	* @param uValue Value written.
1048	* @param uTagSrc The IRQ tag and source (for tracing).
1049	* @thread EMT only.
1050	*/
1051	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1052
1053
1054	/**
1055	* Acquires the PDM lock.
1056	*
1057	* @returns VINF_SUCCESS on success.
1058	* @returns rc if we failed to acquire the lock.
1059	* @param pDevIns The PCI device instance.
1060	* @param rc What to return if we fail to acquire the lock.
1061	*/
1062	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1063
1064	/**
1065	* Releases the PDM lock.
1066	*
1067	* @param pDevIns The PCI device instance.
1068	*/
1069	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1070
1071	/**
1072	* Gets a bus by it's PDM ordinal (typically the parent bus).
1073	*
1074	* @returns Pointer to the device instance of the bus.
1075	* @param pDevIns The PCI bus device instance.
1076	* @param idxPdmBus The PDM ordinal value of the bus to get.
1077	*/
1078	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1079
1080	/** Just a safety precaution. */
1081	uint32_t u32TheEnd;
1082	} PDMPCIHLPRC;
1083	/** Pointer to PCI helpers. */
1084	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1085	/** Pointer to const PCI helpers. */
1086	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1087
1088	/** Current PDMPCIHLPRC version number. */
1089	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 3, 0)
1090
1091
1092	/**
1093	* PCI Bus R0 helpers.
1094	*/
1095	typedef struct PDMPCIHLPR0
1096	{
1097	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1098	uint32_t u32Version;
1099
1100	/**
1101	* Set an ISA IRQ.
1102	*
1103	* @param pDevIns PCI device instance.
1104	* @param iIrq IRQ number to set.
1105	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1106	* @param uTagSrc The IRQ tag and source (for tracing).
1107	* @thread EMT only.
1108	*/
1109	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1110
1111	/**
1112	* Set an I/O-APIC IRQ.
1113	*
1114	* @param pDevIns PCI device instance.
1115	* @param iIrq IRQ number to set.
1116	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1117	* @param uTagSrc The IRQ tag and source (for tracing).
1118	* @thread EMT only.
1119	*/
1120	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1121
1122	/**
1123	* Send an MSI.
1124	*
1125	* @param pDevIns PCI device instance.
1126	* @param GCPhys Physical address MSI request was written.
1127	* @param uValue Value written.
1128	* @param uTagSrc The IRQ tag and source (for tracing).
1129	* @thread EMT only.
1130	*/
1131	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1132
1133	/**
1134	* Acquires the PDM lock.
1135	*
1136	* @returns VINF_SUCCESS on success.
1137	* @returns rc if we failed to acquire the lock.
1138	* @param pDevIns The PCI device instance.
1139	* @param rc What to return if we fail to acquire the lock.
1140	*/
1141	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1142
1143	/**
1144	* Releases the PDM lock.
1145	*
1146	* @param pDevIns The PCI device instance.
1147	*/
1148	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1149
1150	/**
1151	* Gets a bus by it's PDM ordinal (typically the parent bus).
1152	*
1153	* @returns Pointer to the device instance of the bus.
1154	* @param pDevIns The PCI bus device instance.
1155	* @param idxPdmBus The PDM ordinal value of the bus to get.
1156	*/
1157	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1158
1159	/** Just a safety precaution. */
1160	uint32_t u32TheEnd;
1161	} PDMPCIHLPR0;
1162	/** Pointer to PCI helpers. */
1163	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1164	/** Pointer to const PCI helpers. */
1165	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1166
1167	/** Current PDMPCIHLPR0 version number. */
1168	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 5, 0)
1169
1170	/**
1171	* PCI device helpers.
1172	*/
1173	typedef struct PDMPCIHLPR3
1174	{
1175	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1176	uint32_t u32Version;
1177
1178	/**
1179	* Set an ISA IRQ.
1180	*
1181	* @param pDevIns The PCI device instance.
1182	* @param iIrq IRQ number to set.
1183	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1184	* @param uTagSrc The IRQ tag and source (for tracing).
1185	*/
1186	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1187
1188	/**
1189	* Set an I/O-APIC IRQ.
1190	*
1191	* @param pDevIns The PCI device instance.
1192	* @param iIrq IRQ number to set.
1193	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1194	* @param uTagSrc The IRQ tag and source (for tracing).
1195	*/
1196	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1197
1198	/**
1199	* Send an MSI.
1200	*
1201	* @param pDevIns PCI device instance.
1202	* @param GCPhys Physical address MSI request was written.
1203	* @param uValue Value written.
1204	* @param uTagSrc The IRQ tag and source (for tracing).
1205	*/
1206	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1207
1208	/**
1209	* Acquires the PDM lock.
1210	*
1211	* @returns VINF_SUCCESS on success.
1212	* @returns Fatal error on failure.
1213	* @param pDevIns The PCI device instance.
1214	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1215	*/
1216	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1217
1218	/**
1219	* Releases the PDM lock.
1220	*
1221	* @param pDevIns The PCI device instance.
1222	*/
1223	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1224
1225	/**
1226	* Gets a bus by it's PDM ordinal (typically the parent bus).
1227	*
1228	* @returns Pointer to the device instance of the bus.
1229	* @param pDevIns The PCI bus device instance.
1230	* @param idxPdmBus The PDM ordinal value of the bus to get.
1231	*/
1232	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1233
1234	/** Just a safety precaution. */
1235	uint32_t u32TheEnd;
1236	} PDMPCIHLPR3;
1237	/** Pointer to PCI helpers. */
1238	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1239	/** Pointer to const PCI helpers. */
1240	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1241
1242	/** Current PDMPCIHLPR3 version number. */
1243	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 4, 0)
1244
1245
1246	/**
1247	* IOMMU registration structure for ring-0.
1248	*/
1249	typedef struct PDMIOMMUREGR0
1250	{
1251	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1252	* version. */
1253	uint32_t u32Version;
1254	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1255	uint32_t idxIommu;
1256
1257	/**
1258	* Performs a physical memory read transaction through the IOMMU.
1259	*
1260	* @returns VBox status code.
1261	* @param pDevIns The IOMMU device instance.
1262	* @param uDevId The device identifier (bus, device, function).
1263	* @param uDva The device virtual address being read.
1264	* @param cbRead The number of bytes being read.
1265	* @param pGCPhysOut Where to store the translated physical address.
1266	*
1267	* @thread Any.
1268	*/
1269	DECLR0CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbRead,
1270	PRTGCPHYS pGCPhysOut));
1271
1272	/**
1273	* Performs a physical memory write transaction through the IOMMU.
1274	*
1275	* @returns VBox status code.
1276	* @param pDevIns The IOMMU device instance.
1277	* @param uDevId The device identifier (bus, device, function).
1278	* @param uDva The device virtual address being written.
1279	* @param cbRead The number of bytes being written.
1280	* @param pGCPhysOut Where to store the translated physical address.
1281	*
1282	* @thread Any.
1283	*/
1284	DECLR0CALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbWrite,
1285	PRTGCPHYS pGCPhysOut));
1286
1287	/** Just a safety precaution. */
1288	uint32_t u32TheEnd;
1289	} PDMIOMMUREGR0;
1290	/** Pointer to a IOMMU registration structure. */
1291	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1292
1293	/** Current PDMIOMMUREG version number. */
1294	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 1, 0)
1295
1296
1297	/**
1298	* IOMMU registration structure for raw-mode.
1299	*/
1300	typedef struct PDMIOMMUREGRC
1301	{
1302	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1303	* version. */
1304	uint32_t u32Version;
1305	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1306	uint32_t idxIommu;
1307
1308	/**
1309	* Performs a physical memory read transaction through the IOMMU.
1310	*
1311	* @returns VBox status code.
1312	* @param pDevIns The IOMMU device instance.
1313	* @param uDevId The device identifier (bus, device, function).
1314	* @param uDva The device virtual address.
1315	* @param cbRead The number of bytes being read.
1316	* @param pGCPhysOut Where to store the translated physical address.
1317	*
1318	* @thread Any.
1319	*/
1320	DECLRCCALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbRead,
1321	PRTGCPHYS pGCPhysOut));
1322
1323	/**
1324	* Performs a physical memory write transaction through the IOMMU.
1325	*
1326	* @returns VBox status code.
1327	* @param pDevIns The IOMMU device instance.
1328	* @param uDevId The device identifier (bus, device, function).
1329	* @param uDva The device virtual address being written.
1330	* @param cbRead The number of bytes being written.
1331	* @param pGCPhysOut Where to store the translated physical address.
1332	*
1333	* @thread Any.
1334	*/
1335	DECLRCCALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbWrite,
1336	PRTGCPHYS pGCPhysOut));
1337
1338	/** Just a safety precaution. */
1339	uint32_t u32TheEnd;
1340	} PDMIOMMUREGRC;
1341	/** Pointer to a IOMMU registration structure. */
1342	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1343
1344	/** Current PDMIOMMUREG version number. */
1345	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 1, 0)
1346
1347
1348	/**
1349	* IOMMU registration structure for ring-3.
1350	*/
1351	typedef struct PDMIOMMUREGR3
1352	{
1353	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1354	* version. */
1355	uint32_t u32Version;
1356	/** Padding. */
1357	uint32_t uPadding0;
1358
1359	/**
1360	* Performs a physical memory read transaction through the IOMMU.
1361	*
1362	* @returns VBox status code.
1363	* @param pDevIns The IOMMU device instance.
1364	* @param uDevId The device identifier (bus, device, function).
1365	* @param uDva The device virtual address being read.
1366	* @param cbRead The number of bytes being read.
1367	* @param pGCPhysOut Where to store the translated physical address.
1368	*
1369	* @thread Any.
1370	*/
1371	DECLR3CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbRead,
1372	PRTGCPHYS pGCPhysOut));
1373
1374	/**
1375	* Performs a physical memory write transaction through the IOMMU.
1376	*
1377	* @returns VBox status code.
1378	* @param pDevIns The IOMMU device instance.
1379	* @param uDevId The device identifier (bus, device, function).
1380	* @param uDva The device virtual address being written.
1381	* @param cbWrite The number of bytes being written.
1382	* @param pGCPhysOut Where to store the translated physical address.
1383	*
1384	* @thread Any.
1385	*/
1386	DECLR3CALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbWrite,
1387	PRTGCPHYS pGCPhysOut));
1388
1389	/** Just a safety precaution. */
1390	uint32_t u32TheEnd;
1391	} PDMIOMMUREGR3;
1392	/** Pointer to a IOMMU registration structure. */
1393	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1394
1395	/** Current PDMIOMMUREG version number. */
1396	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 1, 0)
1397
1398	/** IOMMU registration structure for the current context. */
1399	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1400	/** Pointer to an IOMMU registration structure for the current context. */
1401	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1402	/** IOMMU registration structure version for the current context. */
1403	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1404
1405
1406	/**
1407	* IOMMU helpers for ring-0.
1408	*/
1409	typedef struct PDMIOMMUHLPR0
1410	{
1411	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1412	uint32_t u32Version;
1413	/** Just a safety precaution. */
1414	uint32_t u32TheEnd;
1415	} PDMIOMMUHLPR0;
1416	/** Pointer to IOMMU helpers for ring-0. */
1417	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1418	/** Pointer to const IOMMU helpers for ring-0. */
1419	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1420
1421	/** Current PDMIOMMUHLPR0 version number. */
1422	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 1, 0)
1423
1424
1425	/**
1426	* IOMMU helpers for raw-mode.
1427	*/
1428	typedef struct PDMIOMMUHLPRC
1429	{
1430	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1431	uint32_t u32Version;
1432	/** Just a safety precaution. */
1433	uint32_t u32TheEnd;
1434	} PDMIOMMUHLPRC;
1435	/** Pointer to IOMMU helpers for raw-mode. */
1436	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1437	/** Pointer to const IOMMU helpers for raw-mode. */
1438	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1439
1440	/** Current PDMIOMMUHLPRC version number. */
1441	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 1, 0)
1442
1443
1444	/**
1445	* IOMMU helpers for ring-3.
1446	*/
1447	typedef struct PDMIOMMUHLPR3
1448	{
1449	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1450	uint32_t u32Version;
1451	/** Just a safety precaution. */
1452	uint32_t u32TheEnd;
1453	} PDMIOMMUHLPR3;
1454	/** Pointer to IOMMU helpers for raw-mode. */
1455	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1456	/** Pointer to const IOMMU helpers for raw-mode. */
1457	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1458
1459	/** Current PDMIOMMUHLPR3 version number. */
1460	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 1, 0)
1461
1462
1463	/**
1464	* Programmable Interrupt Controller registration structure (all contexts).
1465	*/
1466	typedef struct PDMPICREG
1467	{
1468	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1469	uint32_t u32Version;
1470
1471	/**
1472	* Set the an IRQ.
1473	*
1474	* @param pDevIns Device instance of the PIC.
1475	* @param iIrq IRQ number to set.
1476	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1477	* @param uTagSrc The IRQ tag and source (for tracing).
1478	* @remarks Caller enters the PDM critical section.
1479	*/
1480	DECLCALLBACKMEMBER(void, pfnSetIrq)(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc);
1481
1482	/**
1483	* Get a pending interrupt.
1484	*
1485	* @returns Pending interrupt number.
1486	* @param pDevIns Device instance of the PIC.
1487	* @param puTagSrc Where to return the IRQ tag and source.
1488	* @remarks Caller enters the PDM critical section.
1489	*/
1490	DECLCALLBACKMEMBER(int, pfnGetInterrupt)(PPDMDEVINS pDevIns, uint32_t *puTagSrc);
1491
1492	/** Just a safety precaution. */
1493	uint32_t u32TheEnd;
1494	} PDMPICREG;
1495	/** Pointer to a PIC registration structure. */
1496	typedef PDMPICREG *PPDMPICREG;
1497
1498	/** Current PDMPICREG version number. */
1499	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1500
1501	/**
1502	* PIC helpers, same in all contexts.
1503	*/
1504	typedef struct PDMPICHLP
1505	{
1506	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1507	uint32_t u32Version;
1508
1509	/**
1510	* Set the interrupt force action flag.
1511	*
1512	* @param pDevIns Device instance of the PIC.
1513	*/
1514	DECLCALLBACKMEMBER(void, pfnSetInterruptFF)(PPDMDEVINS pDevIns);
1515
1516	/**
1517	* Clear the interrupt force action flag.
1518	*
1519	* @param pDevIns Device instance of the PIC.
1520	*/
1521	DECLCALLBACKMEMBER(void, pfnClearInterruptFF)(PPDMDEVINS pDevIns);
1522
1523	/**
1524	* Acquires the PDM lock.
1525	*
1526	* @returns VINF_SUCCESS on success.
1527	* @returns rc if we failed to acquire the lock.
1528	* @param pDevIns The PIC device instance.
1529	* @param rc What to return if we fail to acquire the lock.
1530	*/
1531	DECLCALLBACKMEMBER(int, pfnLock)(PPDMDEVINS pDevIns, int rc);
1532
1533	/**
1534	* Releases the PDM lock.
1535	*
1536	* @param pDevIns The PIC device instance.
1537	*/
1538	DECLCALLBACKMEMBER(void, pfnUnlock)(PPDMDEVINS pDevIns);
1539
1540	/** Just a safety precaution. */
1541	uint32_t u32TheEnd;
1542	} PDMPICHLP;
1543	/** Pointer to PIC helpers. */
1544	typedef PDMPICHLP *PPDMPICHLP;
1545	/** Pointer to const PIC helpers. */
1546	typedef const PDMPICHLP *PCPDMPICHLP;
1547
1548	/** Current PDMPICHLP version number. */
1549	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1550
1551
1552	/**
1553	* Firmware registration structure.
1554	*/
1555	typedef struct PDMFWREG
1556	{
1557	/** Struct version+magic number (PDM_FWREG_VERSION). */
1558	uint32_t u32Version;
1559
1560	/**
1561	* Checks whether this is a hard or soft reset.
1562	*
1563	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1564	* is 5, 9 or 0xA.
1565	*
1566	* @returns true if hard reset, false if soft.
1567	* @param pDevIns Device instance of the firmware.
1568	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1569	*/
1570	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1571
1572	/** Just a safety precaution. */
1573	uint32_t u32TheEnd;
1574	} PDMFWREG;
1575	/** Pointer to a FW registration structure. */
1576	typedef PDMFWREG *PPDMFWREG;
1577	/** Pointer to a const FW registration structure. */
1578	typedef PDMFWREG const *PCPDMFWREG;
1579
1580	/** Current PDMFWREG version number. */
1581	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1582
1583	/**
1584	* Firmware R3 helpers.
1585	*/
1586	typedef struct PDMFWHLPR3
1587	{
1588	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1589	uint32_t u32Version;
1590
1591	/** Just a safety precaution. */
1592	uint32_t u32TheEnd;
1593	} PDMFWHLPR3;
1594
1595	/** Pointer to FW R3 helpers. */
1596	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1597	/** Pointer to const FW R3 helpers. */
1598	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1599
1600	/** Current PDMFWHLPR3 version number. */
1601	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1602
1603
1604	/**
1605	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1606	*
1607	* Also used in saved-states, CFGM don't change existing values.
1608	*/
1609	typedef enum PDMAPICMODE
1610	{
1611	/** Invalid 0 entry. */
1612	PDMAPICMODE_INVALID = 0,
1613	/** No APIC. */
1614	PDMAPICMODE_NONE,
1615	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1616	PDMAPICMODE_APIC,
1617	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1618	PDMAPICMODE_X2APIC,
1619	/** The usual 32-bit paranoia. */
1620	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1621	} PDMAPICMODE;
1622
1623	/**
1624	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1625	*/
1626	typedef enum PDMAPICIRQ
1627	{
1628	/** Invalid 0 entry. */
1629	PDMAPICIRQ_INVALID = 0,
1630	/** Normal hardware interrupt. */
1631	PDMAPICIRQ_HARDWARE,
1632	/** NMI. */
1633	PDMAPICIRQ_NMI,
1634	/** SMI. */
1635	PDMAPICIRQ_SMI,
1636	/** ExtINT (HW interrupt via PIC). */
1637	PDMAPICIRQ_EXTINT,
1638	/** Interrupt arrived, needs to be updated to the IRR. */
1639	PDMAPICIRQ_UPDATE_PENDING,
1640	/** The usual 32-bit paranoia. */
1641	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1642	} PDMAPICIRQ;
1643
1644
1645	/**
1646	* I/O APIC registration structure (all contexts).
1647	*/
1648	typedef struct PDMIOAPICREG
1649	{
1650	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1651	uint32_t u32Version;
1652
1653	/**
1654	* Set an IRQ.
1655	*
1656	* @param pDevIns Device instance of the I/O APIC.
1657	* @param iIrq IRQ number to set.
1658	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1659	* @param uTagSrc The IRQ tag and source (for tracing).
1660	*
1661	* @remarks Caller enters the PDM critical section
1662	* Actually, as per 2018-07-21 this isn't true (bird).
1663	*/
1664	DECLCALLBACKMEMBER(void, pfnSetIrq)(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc);
1665
1666	/**
1667	* Send a MSI.
1668	*
1669	* @param pDevIns Device instance of the I/O APIC.
1670	* @param GCPhys Request address.
1671	* @param uValue Request value.
1672	* @param uTagSrc The IRQ tag and source (for tracing).
1673	*
1674	* @remarks Caller enters the PDM critical section
1675	* Actually, as per 2018-07-21 this isn't true (bird).
1676	*/
1677	DECLCALLBACKMEMBER(void, pfnSendMsi)(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc);
1678
1679	/**
1680	* Set the EOI for an interrupt vector.
1681	*
1682	* @returns Strict VBox status code - only the following informational status codes:
1683	* @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
1684	* @retval VINF_SUCCESS
1685	*
1686	* @param pDevIns Device instance of the I/O APIC.
1687	* @param u8Vector The vector.
1688	*
1689	* @remarks Caller enters the PDM critical section
1690	* Actually, as per 2018-07-21 this isn't true (bird).
1691	*/
1692	DECLCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoi)(PPDMDEVINS pDevIns, uint8_t u8Vector);
1693
1694	/** Just a safety precaution. */
1695	uint32_t u32TheEnd;
1696	} PDMIOAPICREG;
1697	/** Pointer to an APIC registration structure. */
1698	typedef PDMIOAPICREG *PPDMIOAPICREG;
1699
1700	/** Current PDMAPICREG version number. */
1701	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 6, 0)
1702
1703
1704	/**
1705	* IOAPIC helpers, same in all contexts.
1706	*/
1707	typedef struct PDMIOAPICHLP
1708	{
1709	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1710	uint32_t u32Version;
1711
1712	/**
1713	* Private interface between the IOAPIC and APIC.
1714	*
1715	* @returns status code.
1716	* @param pDevIns Device instance of the IOAPIC.
1717	* @param u8Dest See APIC implementation.
1718	* @param u8DestMode See APIC implementation.
1719	* @param u8DeliveryMode See APIC implementation.
1720	* @param uVector See APIC implementation.
1721	* @param u8Polarity See APIC implementation.
1722	* @param u8TriggerMode See APIC implementation.
1723	* @param uTagSrc The IRQ tag and source (for tracing).
1724	*
1725	* @sa APICBusDeliver()
1726	*/
1727	DECLCALLBACKMEMBER(int, pfnApicBusDeliver)(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1728	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc);
1729
1730	/**
1731	* Acquires the PDM lock.
1732	*
1733	* @returns VINF_SUCCESS on success.
1734	* @returns rc if we failed to acquire the lock.
1735	* @param pDevIns The IOAPIC device instance.
1736	* @param rc What to return if we fail to acquire the lock.
1737	*/
1738	DECLCALLBACKMEMBER(int, pfnLock)(PPDMDEVINS pDevIns, int rc);
1739
1740	/**
1741	* Releases the PDM lock.
1742	*
1743	* @param pDevIns The IOAPIC device instance.
1744	*/
1745	DECLCALLBACKMEMBER(void, pfnUnlock)(PPDMDEVINS pDevIns);
1746
1747	/** Just a safety precaution. */
1748	uint32_t u32TheEnd;
1749	} PDMIOAPICHLP;
1750	/** Pointer to IOAPIC helpers. */
1751	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1752	/** Pointer to const IOAPIC helpers. */
1753	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1754
1755	/** Current PDMIOAPICHLP version number. */
1756	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 2, 0)
1757
1758
1759	/**
1760	* HPET registration structure.
1761	*/
1762	typedef struct PDMHPETREG
1763	{
1764	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1765	uint32_t u32Version;
1766	} PDMHPETREG;
1767	/** Pointer to an HPET registration structure. */
1768	typedef PDMHPETREG *PPDMHPETREG;
1769
1770	/** Current PDMHPETREG version number. */
1771	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1772
1773	/**
1774	* HPET RC helpers.
1775	*
1776	* @remarks Keep this around in case HPET will need PDM interaction in again RC
1777	* at some later point.
1778	*/
1779	typedef struct PDMHPETHLPRC
1780	{
1781	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
1782	uint32_t u32Version;
1783
1784	/** Just a safety precaution. */
1785	uint32_t u32TheEnd;
1786	} PDMHPETHLPRC;
1787
1788	/** Pointer to HPET RC helpers. */
1789	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
1790	/** Pointer to const HPET RC helpers. */
1791	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
1792
1793	/** Current PDMHPETHLPRC version number. */
1794	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
1795
1796
1797	/**
1798	* HPET R0 helpers.
1799	*
1800	* @remarks Keep this around in case HPET will need PDM interaction in again R0
1801	* at some later point.
1802	*/
1803	typedef struct PDMHPETHLPR0
1804	{
1805	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
1806	uint32_t u32Version;
1807
1808	/** Just a safety precaution. */
1809	uint32_t u32TheEnd;
1810	} PDMHPETHLPR0;
1811
1812	/** Pointer to HPET R0 helpers. */
1813	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
1814	/** Pointer to const HPET R0 helpers. */
1815	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
1816
1817	/** Current PDMHPETHLPR0 version number. */
1818	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
1819
1820	/**
1821	* HPET R3 helpers.
1822	*/
1823	typedef struct PDMHPETHLPR3
1824	{
1825	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
1826	uint32_t u32Version;
1827
1828	/**
1829	* Set legacy mode on PIT and RTC.
1830	*
1831	* @returns VINF_SUCCESS on success.
1832	* @returns rc if we failed to set legacy mode.
1833	* @param pDevIns Device instance of the HPET.
1834	* @param fActivated Whether legacy mode is activated or deactivated.
1835	*/
1836	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
1837
1838
1839	/**
1840	* Set IRQ, bypassing ISA bus override rules.
1841	*
1842	* @returns VINF_SUCCESS on success.
1843	* @returns rc if we failed to set legacy mode.
1844	* @param pDevIns Device instance of the HPET.
1845	* @param iIrq IRQ number to set.
1846	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1847	*/
1848	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
1849
1850	/** Just a safety precaution. */
1851	uint32_t u32TheEnd;
1852	} PDMHPETHLPR3;
1853
1854	/** Pointer to HPET R3 helpers. */
1855	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
1856	/** Pointer to const HPET R3 helpers. */
1857	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
1858
1859	/** Current PDMHPETHLPR3 version number. */
1860	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
1861
1862
1863	/**
1864	* Raw PCI device registration structure.
1865	*/
1866	typedef struct PDMPCIRAWREG
1867	{
1868	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
1869	uint32_t u32Version;
1870	/** Just a safety precaution. */
1871	uint32_t u32TheEnd;
1872	} PDMPCIRAWREG;
1873	/** Pointer to a raw PCI registration structure. */
1874	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
1875
1876	/** Current PDMPCIRAWREG version number. */
1877	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
1878
1879	/**
1880	* Raw PCI device raw-mode context helpers.
1881	*/
1882	typedef struct PDMPCIRAWHLPRC
1883	{
1884	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
1885	uint32_t u32Version;
1886	/** Just a safety precaution. */
1887	uint32_t u32TheEnd;
1888	} PDMPCIRAWHLPRC;
1889	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
1890	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
1891	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
1892	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
1893
1894	/** Current PDMPCIRAWHLPRC version number. */
1895	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
1896
1897	/**
1898	* Raw PCI device ring-0 context helpers.
1899	*/
1900	typedef struct PDMPCIRAWHLPR0
1901	{
1902	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
1903	uint32_t u32Version;
1904	/** Just a safety precaution. */
1905	uint32_t u32TheEnd;
1906	} PDMPCIRAWHLPR0;
1907	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
1908	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
1909	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
1910	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
1911
1912	/** Current PDMPCIRAWHLPR0 version number. */
1913	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
1914
1915
1916	/**
1917	* Raw PCI device ring-3 context helpers.
1918	*/
1919	typedef struct PDMPCIRAWHLPR3
1920	{
1921	/** Undefined structure version and magic number. */
1922	uint32_t u32Version;
1923
1924	/**
1925	* Gets the address of the RC raw PCI device helpers.
1926	*
1927	* This should be called at both construction and relocation time to obtain
1928	* the correct address of the RC helpers.
1929	*
1930	* @returns RC pointer to the raw PCI device helpers.
1931	* @param pDevIns Device instance of the raw PCI device.
1932	*/
1933	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
1934
1935	/**
1936	* Gets the address of the R0 raw PCI device helpers.
1937	*
1938	* This should be called at both construction and relocation time to obtain
1939	* the correct address of the R0 helpers.
1940	*
1941	* @returns R0 pointer to the raw PCI device helpers.
1942	* @param pDevIns Device instance of the raw PCI device.
1943	*/
1944	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
1945
1946	/** Just a safety precaution. */
1947	uint32_t u32TheEnd;
1948	} PDMPCIRAWHLPR3;
1949	/** Pointer to raw PCI R3 helpers. */
1950	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
1951	/** Pointer to const raw PCI R3 helpers. */
1952	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
1953
1954	/** Current PDMPCIRAWHLPR3 version number. */
1955	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
1956
1957
1958	#ifdef IN_RING3
1959
1960	/**
1961	* DMA Transfer Handler.
1962	*
1963	* @returns Number of bytes transferred.
1964	* @param pDevIns Device instance of the DMA.
1965	* @param pvUser User pointer.
1966	* @param uChannel Channel number.
1967	* @param off DMA position.
1968	* @param cb Block size.
1969	* @remarks The device lock is not taken, however, the DMA device lock is held.
1970	*/
1971	typedef DECLCALLBACK(uint32_t) FNDMATRANSFERHANDLER(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel, uint32_t off, uint32_t cb);
1972	/** Pointer to a FNDMATRANSFERHANDLER(). */
1973	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
1974
1975	/**
1976	* DMA Controller registration structure.
1977	*/
1978	typedef struct PDMDMAREG
1979	{
1980	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
1981	uint32_t u32Version;
1982
1983	/**
1984	* Execute pending transfers.
1985	*
1986	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
1987	* @param pDevIns Device instance of the DMAC.
1988	* @remarks No locks held, called on EMT(0) as a form of serialization.
1989	*/
1990	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
1991
1992	/**
1993	* Register transfer function for DMA channel.
1994	*
1995	* @param pDevIns Device instance of the DMAC.
1996	* @param uChannel Channel number.
1997	* @param pfnTransferHandler Device specific transfer function.
1998	* @param pvUser User pointer to be passed to the callback.
1999	* @remarks No locks held, called on an EMT.
2000	*/
2001	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2002
2003	/**
2004	* Read memory
2005	*
2006	* @returns Number of bytes read.
2007	* @param pDevIns Device instance of the DMAC.
2008	* @param uChannel Channel number.
2009	* @param pvBuffer Pointer to target buffer.
2010	* @param off DMA position.
2011	* @param cbBlock Block size.
2012	* @remarks No locks held, called on an EMT.
2013	*/
2014	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2015
2016	/**
2017	* Write memory
2018	*
2019	* @returns Number of bytes written.
2020	* @param pDevIns Device instance of the DMAC.
2021	* @param uChannel Channel number.
2022	* @param pvBuffer Memory to write.
2023	* @param off DMA position.
2024	* @param cbBlock Block size.
2025	* @remarks No locks held, called on an EMT.
2026	*/
2027	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2028
2029	/**
2030	* Set the DREQ line.
2031	*
2032	* @param pDevIns Device instance of the DMAC.
2033	* @param uChannel Channel number.
2034	* @param uLevel Level of the line.
2035	* @remarks No locks held, called on an EMT.
2036	*/
2037	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2038
2039	/**
2040	* Get channel mode
2041	*
2042	* @returns Channel mode.
2043	* @param pDevIns Device instance of the DMAC.
2044	* @param uChannel Channel number.
2045	* @remarks No locks held, called on an EMT.
2046	*/
2047	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2048
2049	} PDMDMACREG;
2050	/** Pointer to a DMAC registration structure. */
2051	typedef PDMDMACREG *PPDMDMACREG;
2052
2053	/** Current PDMDMACREG version number. */
2054	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 1, 0)
2055
2056
2057	/**
2058	* DMA Controller device helpers.
2059	*/
2060	typedef struct PDMDMACHLP
2061	{
2062	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2063	uint32_t u32Version;
2064
2065	/* to-be-defined */
2066
2067	} PDMDMACHLP;
2068	/** Pointer to DMAC helpers. */
2069	typedef PDMDMACHLP *PPDMDMACHLP;
2070	/** Pointer to const DMAC helpers. */
2071	typedef const PDMDMACHLP *PCPDMDMACHLP;
2072
2073	/** Current PDMDMACHLP version number. */
2074	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2075
2076	#endif /* IN_RING3 */
2077
2078
2079
2080	/**
2081	* RTC registration structure.
2082	*/
2083	typedef struct PDMRTCREG
2084	{
2085	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2086	uint32_t u32Version;
2087	uint32_t u32Alignment; /*< structure size alignment. /
2088
2089	/**
2090	* Write to a CMOS register and update the checksum if necessary.
2091	*
2092	* @returns VBox status code.
2093	* @param pDevIns Device instance of the RTC.
2094	* @param iReg The CMOS register index.
2095	* @param u8Value The CMOS register value.
2096	* @remarks Caller enters the device critical section.
2097	*/
2098	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2099
2100	/**
2101	* Read a CMOS register.
2102	*
2103	* @returns VBox status code.
2104	* @param pDevIns Device instance of the RTC.
2105	* @param iReg The CMOS register index.
2106	* @param pu8Value Where to store the CMOS register value.
2107	* @remarks Caller enters the device critical section.
2108	*/
2109	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2110
2111	} PDMRTCREG;
2112	/** Pointer to a RTC registration structure. */
2113	typedef PDMRTCREG *PPDMRTCREG;
2114	/** Pointer to a const RTC registration structure. */
2115	typedef const PDMRTCREG *PCPDMRTCREG;
2116
2117	/** Current PDMRTCREG version number. */
2118	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2119
2120
2121	/**
2122	* RTC device helpers.
2123	*/
2124	typedef struct PDMRTCHLP
2125	{
2126	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2127	uint32_t u32Version;
2128
2129	/* to-be-defined */
2130
2131	} PDMRTCHLP;
2132	/** Pointer to RTC helpers. */
2133	typedef PDMRTCHLP *PPDMRTCHLP;
2134	/** Pointer to const RTC helpers. */
2135	typedef const PDMRTCHLP *PCPDMRTCHLP;
2136
2137	/** Current PDMRTCHLP version number. */
2138	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2139
2140
2141
2142	/** @name Flags for PCI I/O region registration
2143	* @{ */
2144	/** No handle is passed. */
2145	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2146	/** An I/O port handle is passed. */
2147	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2148	/** An MMIO range handle is passed. */
2149	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2150	/** An MMIO2 handle is passed. */
2151	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2152	/** Handle type mask. */
2153	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2154	/** New-style (mostly wrt callbacks). */
2155	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2156	/** Mask of valid flags. */
2157	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2158	/** @} */
2159
2160
2161	#ifdef IN_RING3
2162
2163	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2164	* @{ */
2165	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2166	* This is handy when registering multiple PCI device functions and the device
2167	* number is left up to the PCI bus. In order to facilitate one PDM device
2168	* instance for each PCI function, this searches earlier PDM device
2169	* instances as well. */
2170	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2171	/** Use the first unused device number (all functions must be unused). */
2172	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2173	/** Use the first unused device function. */
2174	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2175
2176	/** The device and function numbers are not mandatory, just suggestions. */
2177	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2178	/** Registering a PCI bridge device. */
2179	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2180	/** Valid flag mask. */
2181	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2182	/** @} */
2183
2184	/** Current PDMDEVHLPR3 version number. */
2185	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 43, 0)
2186
2187	/**
2188	* PDM Device API.
2189	*/
2190	typedef struct PDMDEVHLPR3
2191	{
2192	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2193	uint32_t u32Version;
2194
2195	/** @name I/O ports
2196	* @{ */
2197	/**
2198	* Creates a range of I/O ports for a device.
2199	*
2200	* The I/O port range must be mapped in a separately call. Any ring-0 and
2201	* raw-mode context callback handlers needs to be set up in the respective
2202	* contexts.
2203	*
2204	* @returns VBox status.
2205	* @param pDevIns The device instance to register the ports with.
2206	* @param cPorts Number of ports to register.
2207	* @param fFlags IOM_IOPORT_F_XXX.
2208	* @param pPciDev The PCI device the range is associated with, if
2209	* applicable.
2210	* @param iPciRegion The PCI device region in the high 16-bit word and
2211	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2212	* @param pfnOut Pointer to function which is gonna handle OUT
2213	* operations. Optional.
2214	* @param pfnIn Pointer to function which is gonna handle IN operations.
2215	* Optional.
2216	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2217	* operations. Optional.
2218	* @param pfnInStr Pointer to function which is gonna handle string IN
2219	* operations. Optional.
2220	* @param pvUser User argument to pass to the callbacks.
2221	* @param pszDesc Pointer to description string. This must not be freed.
2222	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2223	* coverage is allowed. This must not be freed.
2224	* @param phIoPorts Where to return the I/O port range handle.
2225	*
2226	* @remarks Caller enters the device critical section prior to invoking the
2227	* registered callback methods.
2228	*
2229	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2230	* PDMDevHlpIoPortUnmap.
2231	*/
2232	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2233	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2234	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2235	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2236
2237	/**
2238	* Maps an I/O port range.
2239	*
2240	* @returns VBox status.
2241	* @param pDevIns The device instance to register the ports with.
2242	* @param hIoPorts The I/O port range handle.
2243	* @param Port Where to map the range.
2244	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2245	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2246	*/
2247	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2248
2249	/**
2250	* Unmaps an I/O port range.
2251	*
2252	* @returns VBox status.
2253	* @param pDevIns The device instance to register the ports with.
2254	* @param hIoPorts The I/O port range handle.
2255	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2256	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2257	*/
2258	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2259
2260	/**
2261	* Gets the mapping address of the I/O port range @a hIoPorts.
2262	*
2263	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2264	* parameters).
2265	* @param pDevIns The device instance to register the ports with.
2266	* @param hIoPorts The I/O port range handle.
2267	*/
2268	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2269	/** @} */
2270
2271	/** @name MMIO
2272	* @{ */
2273	/**
2274	* Creates a memory mapped I/O (MMIO) region for a device.
2275	*
2276	* The MMIO region must be mapped in a separately call. Any ring-0 and
2277	* raw-mode context callback handlers needs to be set up in the respective
2278	* contexts.
2279	*
2280	* @returns VBox status.
2281	* @param pDevIns The device instance to register the ports with.
2282	* @param cbRegion The size of the region in bytes.
2283	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2284	* @param pPciDev The PCI device the range is associated with, if
2285	* applicable.
2286	* @param iPciRegion The PCI device region in the high 16-bit word and
2287	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2288	* @param pfnWrite Pointer to function which is gonna handle Write
2289	* operations.
2290	* @param pfnRead Pointer to function which is gonna handle Read
2291	* operations.
2292	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2293	* operations. (optional)
2294	* @param pvUser User argument to pass to the callbacks.
2295	* @param pszDesc Pointer to description string. This must not be freed.
2296	* @param phRegion Where to return the MMIO region handle.
2297	*
2298	* @remarks Caller enters the device critical section prior to invoking the
2299	* registered callback methods.
2300	*
2301	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2302	*/
2303	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2304	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2305	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2306	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2307
2308	/**
2309	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2310	*
2311	* @returns VBox status.
2312	* @param pDevIns The device instance the region is associated with.
2313	* @param hRegion The MMIO region handle.
2314	* @param GCPhys Where to map the region.
2315	* @note An MMIO range may overlap with base memory if a lot of RAM is
2316	* configured for the VM, in which case we'll drop the base memory
2317	* pages. Presently we will make no attempt to preserve anything that
2318	* happens to be present in the base memory that is replaced, this is
2319	* technically incorrect but it's just not worth the effort to do
2320	* right, at least not at this point.
2321	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2322	* PDMDevHlpMmioSetUpContext
2323	*/
2324	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2325
2326	/**
2327	* Unmaps a memory mapped I/O (MMIO) region.
2328	*
2329	* @returns VBox status.
2330	* @param pDevIns The device instance the region is associated with.
2331	* @param hRegion The MMIO region handle.
2332	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2333	* PDMDevHlpMmioSetUpContext
2334	*/
2335	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2336
2337	/**
2338	* Reduces the length of a MMIO range.
2339	*
2340	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2341	* only work during saved state restore. It will not call the PCI bus code, as
2342	* that is expected to restore the saved resource configuration.
2343	*
2344	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2345	* called it will only map @a cbRegion bytes and not the value set during
2346	* registration.
2347	*
2348	* @return VBox status code.
2349	* @param pDevIns The device owning the range.
2350	* @param hRegion The MMIO region handle.
2351	* @param cbRegion The new size, must be smaller.
2352	*/
2353	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2354
2355	/**
2356	* Gets the mapping address of the MMIO region @a hRegion.
2357	*
2358	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2359	* @param pDevIns The device instance to register the ports with.
2360	* @param hRegion The MMIO region handle.
2361	*/
2362	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2363	/** @} */
2364
2365	/** @name MMIO2
2366	* @{ */
2367	/**
2368	* Creates a MMIO2 region.
2369	*
2370	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2371	* associated with a device. It is also non-shared memory with a permanent
2372	* ring-3 mapping and page backing (presently).
2373	*
2374	* @returns VBox status.
2375	* @param pDevIns The device instance.
2376	* @param pPciDev The PCI device the region is associated with, or
2377	* NULL if no PCI device association.
2378	* @param iPciRegion The region number. Use the PCI region number as
2379	* this must be known to the PCI bus device too. If
2380	* it's not associated with the PCI device, then
2381	* any number up to UINT8_MAX is fine.
2382	* @param cbRegion The size (in bytes) of the region.
2383	* @param fFlags Reserved for future use, must be zero.
2384	* @param pszDesc Pointer to description string. This must not be
2385	* freed.
2386	* @param ppvMapping Where to store the address of the ring-3 mapping
2387	* of the memory.
2388	* @param phRegion Where to return the MMIO2 region handle.
2389	*
2390	* @thread EMT(0)
2391	*/
2392	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2393	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2394
2395	/**
2396	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2397	*
2398	* Any physical access handlers registered for the region must be deregistered
2399	* before calling this function.
2400	*
2401	* @returns VBox status code.
2402	* @param pDevIns The device instance.
2403	* @param hRegion The MMIO2 region handle.
2404	* @thread EMT.
2405	*/
2406	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2407
2408	/**
2409	* Maps a MMIO2 region (into the guest physical address space).
2410	*
2411	* @returns VBox status.
2412	* @param pDevIns The device instance the region is associated with.
2413	* @param hRegion The MMIO2 region handle.
2414	* @param GCPhys Where to map the region.
2415	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2416	* configured for the VM, in which case we'll drop the base memory
2417	* pages. Presently we will make no attempt to preserve anything that
2418	* happens to be present in the base memory that is replaced, this is
2419	* technically incorrect but it's just not worth the effort to do
2420	* right, at least not at this point.
2421	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2422	*/
2423	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2424
2425	/**
2426	* Unmaps a MMIO2 region.
2427	*
2428	* @returns VBox status.
2429	* @param pDevIns The device instance the region is associated with.
2430	* @param hRegion The MMIO2 region handle.
2431	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2432	*/
2433	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2434
2435	/**
2436	* Reduces the length of a MMIO range.
2437	*
2438	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2439	* only work during saved state restore. It will not call the PCI bus code, as
2440	* that is expected to restore the saved resource configuration.
2441	*
2442	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2443	* called it will only map @a cbRegion bytes and not the value set during
2444	* registration.
2445	*
2446	* @return VBox status code.
2447	* @param pDevIns The device owning the range.
2448	* @param hRegion The MMIO2 region handle.
2449	* @param cbRegion The new size, must be smaller.
2450	*/
2451	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2452
2453	/**
2454	* Gets the mapping address of the MMIO region @a hRegion.
2455	*
2456	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2457	* @param pDevIns The device instance to register the ports with.
2458	* @param hRegion The MMIO2 region handle.
2459	*/
2460	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2461
2462	/**
2463	* Changes the number of an MMIO2 or pre-registered MMIO region.
2464	*
2465	* This should only be used to deal with saved state problems, so there is no
2466	* convenience inline wrapper for this method.
2467	*
2468	* @returns VBox status code.
2469	* @param pDevIns The device instance.
2470	* @param hRegion The MMIO2 region handle.
2471	* @param iNewRegion The new region index.
2472	*
2473	* @sa @bugref{9359}
2474	*/
2475	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2476	/** @} */
2477
2478	/**
2479	* Register a ROM (BIOS) region.
2480	*
2481	* It goes without saying that this is read-only memory. The memory region must be
2482	* in unassigned memory. I.e. from the top of the address space or on the PC in
2483	* the 0xa0000-0xfffff range.
2484	*
2485	* @returns VBox status.
2486	* @param pDevIns The device instance owning the ROM region.
2487	* @param GCPhysStart First physical address in the range.
2488	* Must be page aligned!
2489	* @param cbRange The size of the range (in bytes).
2490	* Must be page aligned!
2491	* @param pvBinary Pointer to the binary data backing the ROM image.
2492	* @param cbBinary The size of the binary pointer. This must
2493	* be equal or smaller than @a cbRange.
2494	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2495	* @param pszDesc Pointer to description string. This must not be freed.
2496	*
2497	* @remark There is no way to remove the rom, automatically on device cleanup or
2498	* manually from the device yet. At present I doubt we need such features...
2499	*/
2500	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2501	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2502
2503	/**
2504	* Changes the protection of shadowed ROM mapping.
2505	*
2506	* This is intented for use by the system BIOS, chipset or device in question to
2507	* change the protection of shadowed ROM code after init and on reset.
2508	*
2509	* @param pDevIns The device instance.
2510	* @param GCPhysStart Where the mapping starts.
2511	* @param cbRange The size of the mapping.
2512	* @param enmProt The new protection type.
2513	*/
2514	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2515
2516	/**
2517	* Register a save state data unit.
2518	*
2519	* @returns VBox status.
2520	* @param pDevIns The device instance.
2521	* @param uVersion Data layout version number.
2522	* @param cbGuess The approximate amount of data in the unit.
2523	* Only for progress indicators.
2524	* @param pszBefore Name of data unit which we should be put in
2525	* front of. Optional (NULL).
2526	*
2527	* @param pfnLivePrep Prepare live save callback, optional.
2528	* @param pfnLiveExec Execute live save callback, optional.
2529	* @param pfnLiveVote Vote live save callback, optional.
2530	*
2531	* @param pfnSavePrep Prepare save callback, optional.
2532	* @param pfnSaveExec Execute save callback, optional.
2533	* @param pfnSaveDone Done save callback, optional.
2534	*
2535	* @param pfnLoadPrep Prepare load callback, optional.
2536	* @param pfnLoadExec Execute load callback, optional.
2537	* @param pfnLoadDone Done load callback, optional.
2538	* @remarks Caller enters the device critical section prior to invoking the
2539	* registered callback methods.
2540	*/
2541	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2542	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2543	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2544	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2545
2546	/** @name Exported SSM Functions
2547	* @{ */
2548	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2549	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2550	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2551	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2552	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2553	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2554	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2555	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2556	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2557	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2558	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2559	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2560	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2561	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2562	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2563	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2564	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2565	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2566	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2567	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2568	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2569	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2570	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2571	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2572	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2573	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2574	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2575	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2576	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2577	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2578	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2579	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2580	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2581	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2582	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2583	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2584	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2585	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2586	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2587	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2588	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2589	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2590	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2591	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2592	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2593	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2594	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2595	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2596	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2597	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2598	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2599	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2600	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2601	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2602	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2603	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2604	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2605	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2606	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2607	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2608	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2609	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2610	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2611	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2612	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2613	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2614	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2615	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2616	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2617	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2618	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2619	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2620	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2621	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2622	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2623	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2624	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2625	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2626	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2627	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2628	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2629	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2630	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2631	/** @} */
2632
2633	/**
2634	* Creates a timer.
2635	*
2636	* @returns VBox status.
2637	* @param pDevIns The device instance.
2638	* @param enmClock The clock to use on this timer.
2639	* @param pfnCallback Callback function.
2640	* @param pvUser User argument for the callback.
2641	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2642	* @param pszDesc Pointer to description string which must stay around
2643	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2644	* @param ppTimer Where to store the timer on success.
2645	* @remarks Caller enters the device critical section prior to invoking the
2646	* callback.
2647	*/
2648	DECLR3CALLBACKMEMBER(int, pfnTMTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2649	void pvUser, uint32_t fFlags, const char pszDesc, PPTMTIMERR3 ppTimer));
2650
2651	/**
2652	* Creates a timer w/ a cross context handle.
2653	*
2654	* @returns VBox status.
2655	* @param pDevIns The device instance.
2656	* @param enmClock The clock to use on this timer.
2657	* @param pfnCallback Callback function.
2658	* @param pvUser User argument for the callback.
2659	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2660	* @param pszDesc Pointer to description string which must stay around
2661	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2662	* @param phTimer Where to store the timer handle on success.
2663	* @remarks Caller enters the device critical section prior to invoking the
2664	* callback.
2665	*/
2666	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2667	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
2668
2669	/**
2670	* Translates a timer handle to a pointer.
2671	*
2672	* @returns The time address.
2673	* @param pDevIns The device instance.
2674	* @param hTimer The timer handle.
2675	*/
2676	DECLR3CALLBACKMEMBER(PTMTIMERR3, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2677
2678	/** @name Timer handle method wrappers
2679	* @{ */
2680	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2681	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2682	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2683	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2684	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2685	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2686	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2687	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2688	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2689	/** Takes the clock lock then enters the specified critical section. */
2690	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2691	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2692	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2693	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2694	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2695	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2696	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2697	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2698	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2699	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2700	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2701	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2702	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2703	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2704	/** @sa TMR3TimerSkip */
2705	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2706	/** @} */
2707
2708	/**
2709	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2710	*
2711	* @returns pTime.
2712	* @param pDevIns The device instance.
2713	* @param pTime Where to store the time.
2714	*/
2715	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2716
2717	/** @name Exported CFGM Functions.
2718	* @{ */
2719	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2720	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2721	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
2722	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2723	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2724	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
2725	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
2726	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
2727	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2728	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2729	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
2730	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
2731	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
2732	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
2733	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
2734	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
2735	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
2736	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
2737	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
2738	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
2739	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
2740	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
2741	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
2742	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
2743	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
2744	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
2745	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2746	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2747	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
2748	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
2749	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
2750	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
2751	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
2752	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
2753	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
2754	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
2755	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
2756	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
2757	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
2758	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
2759	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
2760	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
2761	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
2762	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
2763	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
2764	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
2765	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
2766	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
2767	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
2768	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
2769	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
2770	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
2771	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
2772	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
2773	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
2774	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
2775	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
2776	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
2777	const char pszValidValues, const char pszValidNodes,
2778	const char *pszWho, uint32_t uInstance));
2779	/** @} */
2780
2781	/**
2782	* Read physical memory.
2783	*
2784	* @returns VINF_SUCCESS (for now).
2785	* @param pDevIns The device instance.
2786	* @param GCPhys Physical address start reading from.
2787	* @param pvBuf Where to put the read bits.
2788	* @param cbRead How many bytes to read.
2789	* @thread Any thread, but the call may involve the emulation thread.
2790	*/
2791	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
2792
2793	/**
2794	* Write to physical memory.
2795	*
2796	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
2797	* @param pDevIns The device instance.
2798	* @param GCPhys Physical address to write to.
2799	* @param pvBuf What to write.
2800	* @param cbWrite How many bytes to write.
2801	* @thread Any thread, but the call may involve the emulation thread.
2802	*/
2803	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
2804
2805	/**
2806	* Requests the mapping of a guest page into ring-3.
2807	*
2808	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2809	* release it.
2810	*
2811	* This API will assume your intention is to write to the page, and will
2812	* therefore replace shared and zero pages. If you do not intend to modify the
2813	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
2814	*
2815	* @returns VBox status code.
2816	* @retval VINF_SUCCESS on success.
2817	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2818	* backing or if the page has any active access handlers. The caller
2819	* must fall back on using PGMR3PhysWriteExternal.
2820	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2821	*
2822	* @param pDevIns The device instance.
2823	* @param GCPhys The guest physical address of the page that
2824	* should be mapped.
2825	* @param fFlags Flags reserved for future use, MBZ.
2826	* @param ppv Where to store the address corresponding to
2827	* GCPhys.
2828	* @param pLock Where to store the lock information that
2829	* pfnPhysReleasePageMappingLock needs.
2830	*
2831	* @remark Avoid calling this API from within critical sections (other than the
2832	* PGM one) because of the deadlock risk when we have to delegating the
2833	* task to an EMT.
2834	* @thread Any.
2835	*/
2836	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
2837	PPGMPAGEMAPLOCK pLock));
2838
2839	/**
2840	* Requests the mapping of a guest page into ring-3, external threads.
2841	*
2842	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2843	* release it.
2844	*
2845	* @returns VBox status code.
2846	* @retval VINF_SUCCESS on success.
2847	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2848	* backing or if the page as an active ALL access handler. The caller
2849	* must fall back on using PGMPhysRead.
2850	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2851	*
2852	* @param pDevIns The device instance.
2853	* @param GCPhys The guest physical address of the page that
2854	* should be mapped.
2855	* @param fFlags Flags reserved for future use, MBZ.
2856	* @param ppv Where to store the address corresponding to
2857	* GCPhys.
2858	* @param pLock Where to store the lock information that
2859	* pfnPhysReleasePageMappingLock needs.
2860	*
2861	* @remark Avoid calling this API from within critical sections.
2862	* @thread Any.
2863	*/
2864	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
2865	void const **ppv, PPGMPAGEMAPLOCK pLock));
2866
2867	/**
2868	* Release the mapping of a guest page.
2869	*
2870	* This is the counter part of pfnPhysGCPhys2CCPtr and
2871	* pfnPhysGCPhys2CCPtrReadOnly.
2872	*
2873	* @param pDevIns The device instance.
2874	* @param pLock The lock structure initialized by the mapping
2875	* function.
2876	*/
2877	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
2878
2879	/**
2880	* Read guest physical memory by virtual address.
2881	*
2882	* @param pDevIns The device instance.
2883	* @param pvDst Where to put the read bits.
2884	* @param GCVirtSrc Guest virtual address to start reading from.
2885	* @param cb How many bytes to read.
2886	* @thread The emulation thread.
2887	*/
2888	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
2889
2890	/**
2891	* Write to guest physical memory by virtual address.
2892	*
2893	* @param pDevIns The device instance.
2894	* @param GCVirtDst Guest virtual address to write to.
2895	* @param pvSrc What to write.
2896	* @param cb How many bytes to write.
2897	* @thread The emulation thread.
2898	*/
2899	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
2900
2901	/**
2902	* Convert a guest virtual address to a guest physical address.
2903	*
2904	* @returns VBox status code.
2905	* @param pDevIns The device instance.
2906	* @param GCPtr Guest virtual address.
2907	* @param pGCPhys Where to store the GC physical address
2908	* corresponding to GCPtr.
2909	* @thread The emulation thread.
2910	* @remark Careful with page boundaries.
2911	*/
2912	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
2913
2914	/**
2915	* Allocate memory which is associated with current VM instance
2916	* and automatically freed on it's destruction.
2917	*
2918	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
2919	* @param pDevIns The device instance.
2920	* @param cb Number of bytes to allocate.
2921	*/
2922	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
2923
2924	/**
2925	* Allocate memory which is associated with current VM instance
2926	* and automatically freed on it's destruction. The memory is ZEROed.
2927	*
2928	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
2929	* @param pDevIns The device instance.
2930	* @param cb Number of bytes to allocate.
2931	*/
2932	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
2933
2934	/**
2935	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
2936	*
2937	* @param pDevIns The device instance.
2938	* @param pv Pointer to the memory to free.
2939	*/
2940	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
2941
2942	/**
2943	* Gets the VM state.
2944	*
2945	* @returns VM state.
2946	* @param pDevIns The device instance.
2947	* @thread Any thread (just keep in mind that it's volatile info).
2948	*/
2949	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
2950
2951	/**
2952	* Checks if the VM was teleported and hasn't been fully resumed yet.
2953	*
2954	* @returns true / false.
2955	* @param pDevIns The device instance.
2956	* @thread Any thread.
2957	*/
2958	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
2959
2960	/**
2961	* Set the VM error message
2962	*
2963	* @returns rc.
2964	* @param pDevIns The device instance.
2965	* @param rc VBox status code.
2966	* @param SRC_POS Use RT_SRC_POS.
2967	* @param pszFormat Error message format string.
2968	* @param ... Error message arguments.
2969	*/
2970	DECLR3CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
2971	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2972
2973	/**
2974	* Set the VM error message
2975	*
2976	* @returns rc.
2977	* @param pDevIns The device instance.
2978	* @param rc VBox status code.
2979	* @param SRC_POS Use RT_SRC_POS.
2980	* @param pszFormat Error message format string.
2981	* @param va Error message arguments.
2982	*/
2983	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
2984	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2985
2986	/**
2987	* Set the VM runtime error message
2988	*
2989	* @returns VBox status code.
2990	* @param pDevIns The device instance.
2991	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
2992	* @param pszErrorId Error ID string.
2993	* @param pszFormat Error message format string.
2994	* @param ... Error message arguments.
2995	*/
2996	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
2997	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
2998
2999	/**
3000	* Set the VM runtime error message
3001	*
3002	* @returns VBox status code.
3003	* @param pDevIns The device instance.
3004	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3005	* @param pszErrorId Error ID string.
3006	* @param pszFormat Error message format string.
3007	* @param va Error message arguments.
3008	*/
3009	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3010	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3011
3012	/**
3013	* Stops the VM and enters the debugger to look at the guest state.
3014	*
3015	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3016	* invoking this function directly.
3017	*
3018	* @returns VBox status code which must be passed up to the VMM.
3019	* @param pDevIns The device instance.
3020	* @param pszFile Filename of the assertion location.
3021	* @param iLine The linenumber of the assertion location.
3022	* @param pszFunction Function of the assertion location.
3023	* @param pszFormat Message. (optional)
3024	* @param args Message parameters.
3025	*/
3026	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3027	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3028
3029	/**
3030	* Register a info handler with DBGF.
3031	*
3032	* @returns VBox status code.
3033	* @param pDevIns The device instance.
3034	* @param pszName The identifier of the info.
3035	* @param pszDesc The description of the info and any arguments
3036	* the handler may take.
3037	* @param pfnHandler The handler function to be called to display the
3038	* info.
3039	*/
3040	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3041
3042	/**
3043	* Register a info handler with DBGF, argv style.
3044	*
3045	* @returns VBox status code.
3046	* @param pDevIns The device instance.
3047	* @param pszName The identifier of the info.
3048	* @param pszDesc The description of the info and any arguments
3049	* the handler may take.
3050	* @param pfnHandler The handler function to be called to display the
3051	* info.
3052	*/
3053	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3054
3055	/**
3056	* Registers a set of registers for a device.
3057	*
3058	* The @a pvUser argument of the getter and setter callbacks will be
3059	* @a pDevIns. The register names will be prefixed by the device name followed
3060	* immediately by the instance number.
3061	*
3062	* @returns VBox status code.
3063	* @param pDevIns The device instance.
3064	* @param paRegisters The register descriptors.
3065	*
3066	* @remarks The device critical section is NOT entered prior to working the
3067	* callbacks registered via this helper!
3068	*/
3069	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3070
3071	/**
3072	* Gets the trace buffer handle.
3073	*
3074	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3075	* really inteded for direct usage, thus no inline wrapper function.
3076	*
3077	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3078	* @param pDevIns The device instance.
3079	*/
3080	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3081
3082	/**
3083	* Registers a statistics sample.
3084	*
3085	* @param pDevIns Device instance of the DMA.
3086	* @param pvSample Pointer to the sample.
3087	* @param enmType Sample type. This indicates what pvSample is
3088	* pointing at.
3089	* @param pszName Sample name, unix path style. If this does not
3090	* start with a '/', the default prefix will be
3091	* prepended, otherwise it will be used as-is.
3092	* @param enmUnit Sample unit.
3093	* @param pszDesc Sample description.
3094	*/
3095	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3096
3097	/**
3098	* Same as pfnSTAMRegister except that the name is specified in a
3099	* RTStrPrintfV like fashion.
3100	*
3101	* @returns VBox status.
3102	* @param pDevIns Device instance of the DMA.
3103	* @param pvSample Pointer to the sample.
3104	* @param enmType Sample type. This indicates what pvSample is
3105	* pointing at.
3106	* @param enmVisibility Visibility type specifying whether unused
3107	* statistics should be visible or not.
3108	* @param enmUnit Sample unit.
3109	* @param pszDesc Sample description.
3110	* @param pszName Sample name format string, unix path style. If
3111	* this does not start with a '/', the default
3112	* prefix will be prepended, otherwise it will be
3113	* used as-is.
3114	* @param args Arguments to the format string.
3115	*/
3116	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3117	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3118	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3119
3120	/**
3121	* Registers a PCI device with the default PCI bus.
3122	*
3123	* If a PDM device has more than one PCI device, they must be registered in the
3124	* order of PDMDEVINSR3::apPciDevs.
3125	*
3126	* @returns VBox status code.
3127	* @param pDevIns The device instance.
3128	* @param pPciDev The PCI device structure.
3129	* This must be kept in the instance data.
3130	* The PCI configuration must be initialized before registration.
3131	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3132	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3133	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3134	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3135	* device number (0-31). This will be ignored if
3136	* the CFGM configuration contains a PCIDeviceNo
3137	* value.
3138	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3139	* function number (0-7). This will be ignored if
3140	* the CFGM configuration contains a PCIFunctionNo
3141	* value.
3142	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3143	* The pointer is saved, so don't free or changed.
3144	* @note The PCI device configuration is now implicit from the apPciDevs
3145	* index, meaning that the zero'th entry is the primary one and
3146	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3147	*/
3148	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3149	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3150
3151	/**
3152	* Initialize MSI or MSI-X emulation support for the given PCI device.
3153	*
3154	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3155	*
3156	* @returns VBox status code.
3157	* @param pDevIns The device instance.
3158	* @param pPciDev The PCI device. NULL is an alias for the first
3159	* one registered.
3160	* @param pMsiReg MSI emulation registration structure.
3161	*/
3162	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3163
3164	/**
3165	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3166	*
3167	* @returns VBox status code.
3168	* @param pDevIns The device instance.
3169	* @param pPciDev The PCI device structure. If NULL the default
3170	* PCI device for this device instance is used.
3171	* @param iRegion The region number.
3172	* @param cbRegion Size of the region.
3173	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3174	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3175	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3176	* @a fFlags, UINT64_MAX if no handle is passed
3177	* (old style).
3178	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3179	* handle is specified. The callback will be
3180	* invoked holding only the PDM lock. The device
3181	* lock will _not_ be taken (due to lock order).
3182	*/
3183	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3184	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3185	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3186
3187	/**
3188	* Register PCI configuration space read/write callbacks.
3189	*
3190	* @returns VBox status code.
3191	* @param pDevIns The device instance.
3192	* @param pPciDev The PCI device structure. If NULL the default
3193	* PCI device for this device instance is used.
3194	* @param pfnRead Pointer to the user defined PCI config read function.
3195	* to call default PCI config read function. Can be NULL.
3196	* @param pfnWrite Pointer to the user defined PCI config write function.
3197	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3198	* is NOT take because that is very likely be a lock order violation.
3199	* @thread EMT(0)
3200	* @note Only callable during VM creation.
3201	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3202	*/
3203	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3204	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3205
3206	/**
3207	* Perform a PCI configuration space write.
3208	*
3209	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3210	*
3211	* @returns Strict VBox status code (mainly DBGFSTOP).
3212	* @param pDevIns The device instance.
3213	* @param pPciDev The PCI device which config space is being read.
3214	* @param uAddress The config space address.
3215	* @param cb The size of the read: 1, 2 or 4 bytes.
3216	* @param u32Value The value to write.
3217	*/
3218	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3219	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3220
3221	/**
3222	* Perform a PCI configuration space read.
3223	*
3224	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3225	*
3226	* @returns Strict VBox status code (mainly DBGFSTOP).
3227	* @param pDevIns The device instance.
3228	* @param pPciDev The PCI device which config space is being read.
3229	* @param uAddress The config space address.
3230	* @param cb The size of the read: 1, 2 or 4 bytes.
3231	* @param pu32Value Where to return the value.
3232	*/
3233	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3234	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3235
3236	/**
3237	* Bus master physical memory read.
3238	*
3239	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3240	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3241	* @param pDevIns The device instance.
3242	* @param pPciDev The PCI device structure. If NULL the default
3243	* PCI device for this device instance is used.
3244	* @param GCPhys Physical address start reading from.
3245	* @param pvBuf Where to put the read bits.
3246	* @param cbRead How many bytes to read.
3247	* @thread Any thread, but the call may involve the emulation thread.
3248	*/
3249	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
3250
3251	/**
3252	* Bus master physical memory write.
3253	*
3254	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3255	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3256	* @param pDevIns The device instance.
3257	* @param pPciDev The PCI device structure. If NULL the default
3258	* PCI device for this device instance is used.
3259	* @param GCPhys Physical address to write to.
3260	* @param pvBuf What to write.
3261	* @param cbWrite How many bytes to write.
3262	* @thread Any thread, but the call may involve the emulation thread.
3263	*/
3264	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
3265
3266	/**
3267	* Sets the IRQ for the given PCI device.
3268	*
3269	* @param pDevIns The device instance.
3270	* @param pPciDev The PCI device structure. If NULL the default
3271	* PCI device for this device instance is used.
3272	* @param iIrq IRQ number to set.
3273	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3274	* @thread Any thread, but will involve the emulation thread.
3275	*/
3276	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3277
3278	/**
3279	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3280	* the request when not called from EMT.
3281	*
3282	* @param pDevIns The device instance.
3283	* @param pPciDev The PCI device structure. If NULL the default
3284	* PCI device for this device instance is used.
3285	* @param iIrq IRQ number to set.
3286	* @param iLevel IRQ level.
3287	* @thread Any thread, but will involve the emulation thread.
3288	*/
3289	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3290
3291	/**
3292	* Set ISA IRQ for a device.
3293	*
3294	* @param pDevIns The device instance.
3295	* @param iIrq IRQ number to set.
3296	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3297	* @thread Any thread, but will involve the emulation thread.
3298	*/
3299	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3300
3301	/**
3302	* Set the ISA IRQ for a device, but don't wait for EMT to process
3303	* the request when not called from EMT.
3304	*
3305	* @param pDevIns The device instance.
3306	* @param iIrq IRQ number to set.
3307	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3308	* @thread Any thread, but will involve the emulation thread.
3309	*/
3310	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3311
3312	/**
3313	* Send an MSI straight to the I/O APIC.
3314	*
3315	* @param pDevIns PCI device instance.
3316	* @param GCPhys Physical address MSI request was written.
3317	* @param uValue Value written.
3318	* @thread Any thread, but will involve the emulation thread.
3319	*/
3320	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
3321
3322	/**
3323	* Attaches a driver (chain) to the device.
3324	*
3325	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3326	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3327	*
3328	* @returns VBox status code.
3329	* @param pDevIns The device instance.
3330	* @param iLun The logical unit to attach.
3331	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3332	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3333	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3334	* for the live of the device instance.
3335	*/
3336	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3337	PPDMIBASE ppBaseInterface, const char pszDesc));
3338
3339	/**
3340	* Detaches an attached driver (chain) from the device again.
3341	*
3342	* @returns VBox status code.
3343	* @param pDevIns The device instance.
3344	* @param pDrvIns The driver instance to detach.
3345	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3346	*/
3347	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3348
3349	/**
3350	* Reconfigures the driver chain for a LUN, detaching any driver currently
3351	* present there.
3352	*
3353	* Caller will have attach it, of course.
3354	*
3355	* @returns VBox status code.
3356	* @param pDevIns The device instance.
3357	* @param iLun The logical unit to reconfigure.
3358	* @param cDepth The depth of the driver chain. Determins the
3359	* size of @a papszDrivers and @a papConfigs.
3360	* @param papszDrivers The names of the drivers to configure in the
3361	* chain, first entry is the one immediately
3362	* below the device/LUN
3363	* @param papConfigs The configurations for each of the drivers
3364	* in @a papszDrivers array. NULL entries
3365	* corresponds to empty 'Config' nodes. This
3366	* function will take ownership of non-NULL
3367	* CFGM sub-trees and set the array member to
3368	* NULL, so the caller can do cleanups on
3369	* failure. This parameter is optional.
3370	* @param fFlags Reserved, MBZ.
3371	*/
3372	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3373	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3374
3375	/** @name Exported PDM Queue Functions
3376	* @{ */
3377	/**
3378	* Create a queue.
3379	*
3380	* @returns VBox status code.
3381	* @param pDevIns The device instance.
3382	* @param cbItem The size of a queue item.
3383	* @param cItems The number of items in the queue.
3384	* @param cMilliesInterval The number of milliseconds between polling the queue.
3385	* If 0 then the emulation thread will be notified whenever an item arrives.
3386	* @param pfnCallback The consumer function.
3387	* @param fRZEnabled Set if the queue should work in RC and R0.
3388	* @param pszName The queue base name. The instance number will be
3389	* appended automatically.
3390	* @param ppQueue Where to store the queue pointer on success.
3391	* @thread The emulation thread.
3392	* @remarks The device critical section will NOT be entered before calling the
3393	* callback. No locks will be held, but for now it's safe to assume
3394	* that only one EMT will do queue callbacks at any one time.
3395	*/
3396	DECLR3CALLBACKMEMBER(int, pfnQueueCreatePtr,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3397	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3398	PPDMQUEUE *ppQueue));
3399
3400	/**
3401	* Create a queue.
3402	*
3403	* @returns VBox status code.
3404	* @param pDevIns The device instance.
3405	* @param cbItem The size of a queue item.
3406	* @param cItems The number of items in the queue.
3407	* @param cMilliesInterval The number of milliseconds between polling the queue.
3408	* If 0 then the emulation thread will be notified whenever an item arrives.
3409	* @param pfnCallback The consumer function.
3410	* @param fRZEnabled Set if the queue should work in RC and R0.
3411	* @param pszName The queue base name. The instance number will be
3412	* appended automatically.
3413	* @param phQueue Where to store the queue handle on success.
3414	* @thread EMT(0)
3415	* @remarks The device critical section will NOT be entered before calling the
3416	* callback. No locks will be held, but for now it's safe to assume
3417	* that only one EMT will do queue callbacks at any one time.
3418	*/
3419	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3420	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3421	PDMQUEUEHANDLE *phQueue));
3422
3423	DECLR3CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3424	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3425	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3426	DECLR3CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
3427	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3428	/** @} */
3429
3430	/** @name PDM Task
3431	* @{ */
3432	/**
3433	* Create an asynchronous ring-3 task.
3434	*
3435	* @returns VBox status code.
3436	* @param pDevIns The device instance.
3437	* @param fFlags PDMTASK_F_XXX
3438	* @param pszName The function name or similar. Used for statistics,
3439	* so no slashes.
3440	* @param pfnCallback The task function.
3441	* @param pvUser User argument for the task function.
3442	* @param phTask Where to return the task handle.
3443	* @thread EMT(0)
3444	*/
3445	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3446	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3447	/**
3448	* Triggers the running the given task.
3449	*
3450	* @returns VBox status code.
3451	* @retval VINF_ALREADY_POSTED is the task is already pending.
3452	* @param pDevIns The device instance.
3453	* @param hTask The task to trigger.
3454	* @thread Any thread.
3455	*/
3456	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3457	/** @} */
3458
3459	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3460	* These semaphores can be signalled from ring-0.
3461	* @{ */
3462	/** @sa SUPSemEventCreate */
3463	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3464	/** @sa SUPSemEventClose */
3465	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3466	/** @sa SUPSemEventSignal */
3467	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3468	/** @sa SUPSemEventWaitNoResume */
3469	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3470	/** @sa SUPSemEventWaitNsAbsIntr */
3471	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3472	/** @sa SUPSemEventWaitNsRelIntr */
3473	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3474	/** @sa SUPSemEventGetResolution */
3475	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3476	/** @} */
3477
3478	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3479	* These semaphores can be signalled from ring-0.
3480	* @{ */
3481	/** @sa SUPSemEventMultiCreate */
3482	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3483	/** @sa SUPSemEventMultiClose */
3484	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3485	/** @sa SUPSemEventMultiSignal */
3486	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3487	/** @sa SUPSemEventMultiReset */
3488	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3489	/** @sa SUPSemEventMultiWaitNoResume */
3490	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3491	/** @sa SUPSemEventMultiWaitNsAbsIntr */
3492	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3493	/** @sa SUPSemEventMultiWaitNsRelIntr */
3494	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3495	/** @sa SUPSemEventMultiGetResolution */
3496	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3497	/** @} */
3498
3499	/**
3500	* Initializes a PDM critical section.
3501	*
3502	* The PDM critical sections are derived from the IPRT critical sections, but
3503	* works in RC and R0 as well.
3504	*
3505	* @returns VBox status code.
3506	* @param pDevIns The device instance.
3507	* @param pCritSect Pointer to the critical section.
3508	* @param SRC_POS Use RT_SRC_POS.
3509	* @param pszNameFmt Format string for naming the critical section.
3510	* For statistics and lock validation.
3511	* @param va Arguments for the format string.
3512	*/
3513	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3514	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3515
3516	/**
3517	* Gets the NOP critical section.
3518	*
3519	* @returns The ring-3 address of the NOP critical section.
3520	* @param pDevIns The device instance.
3521	*/
3522	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3523
3524	/**
3525	* Gets the NOP critical section.
3526	*
3527	* @returns The ring-0 address of the NOP critical section.
3528	* @param pDevIns The device instance.
3529	* @deprecated
3530	*/
3531	DECLR3CALLBACKMEMBER(R0PTRTYPE(PPDMCRITSECT), pfnCritSectGetNopR0,(PPDMDEVINS pDevIns));
3532
3533	/**
3534	* Gets the NOP critical section.
3535	*
3536	* @returns The raw-mode context address of the NOP critical section.
3537	* @param pDevIns The device instance.
3538	* @deprecated
3539	*/
3540	DECLR3CALLBACKMEMBER(RCPTRTYPE(PPDMCRITSECT), pfnCritSectGetNopRC,(PPDMDEVINS pDevIns));
3541
3542	/**
3543	* Changes the device level critical section from the automatically created
3544	* default to one desired by the device constructor.
3545	*
3546	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
3547	* the additional contexts.
3548	*
3549	* @returns VBox status code.
3550	* @param pDevIns The device instance.
3551	* @param pCritSect The critical section to use. NULL is not
3552	* valid, instead use the NOP critical
3553	* section.
3554	*/
3555	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3556
3557	/** @name Exported PDM Critical Section Functions
3558	* @{ */
3559	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3560	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3561	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3562	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3563	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3564	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3565	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3566	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3567	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3568	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3569	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3570	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3571	/** @} */
3572
3573	/**
3574	* Creates a PDM thread.
3575	*
3576	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3577	* resuming, and destroying the thread as the VM state changes.
3578	*
3579	* @returns VBox status code.
3580	* @param pDevIns The device instance.
3581	* @param ppThread Where to store the thread 'handle'.
3582	* @param pvUser The user argument to the thread function.
3583	* @param pfnThread The thread function.
3584	* @param pfnWakeup The wakup callback. This is called on the EMT
3585	* thread when a state change is pending.
3586	* @param cbStack See RTThreadCreate.
3587	* @param enmType See RTThreadCreate.
3588	* @param pszName See RTThreadCreate.
3589	* @remarks The device critical section will NOT be entered prior to invoking
3590	* the function pointers.
3591	*/
3592	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3593	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3594
3595	/** @name Exported PDM Thread Functions
3596	* @{ */
3597	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3598	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3599	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3600	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3601	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3602	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3603	/** @} */
3604
3605	/**
3606	* Set up asynchronous handling of a suspend, reset or power off notification.
3607	*
3608	* This shall only be called when getting the notification. It must be called
3609	* for each one.
3610	*
3611	* @returns VBox status code.
3612	* @param pDevIns The device instance.
3613	* @param pfnAsyncNotify The callback.
3614	* @thread EMT(0)
3615	* @remarks The caller will enter the device critical section prior to invoking
3616	* the callback.
3617	*/
3618	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3619
3620	/**
3621	* Notify EMT(0) that the device has completed the asynchronous notification
3622	* handling.
3623	*
3624	* This can be called at any time, spurious calls will simply be ignored.
3625	*
3626	* @param pDevIns The device instance.
3627	* @thread Any
3628	*/
3629	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
3630
3631	/**
3632	* Register the RTC device.
3633	*
3634	* @returns VBox status code.
3635	* @param pDevIns The device instance.
3636	* @param pRtcReg Pointer to a RTC registration structure.
3637	* @param ppRtcHlp Where to store the pointer to the helper
3638	* functions.
3639	*/
3640	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
3641
3642	/**
3643	* Register a PCI Bus.
3644	*
3645	* @returns VBox status code, but the positive values 0..31 are used to indicate
3646	* bus number rather than informational status codes.
3647	* @param pDevIns The device instance.
3648	* @param pPciBusReg Pointer to PCI bus registration structure.
3649	* @param ppPciHlp Where to store the pointer to the PCI Bus
3650	* helpers.
3651	* @param piBus Where to return the PDM bus number. Optional.
3652	*/
3653	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
3654	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
3655
3656	/**
3657	* Register the IOMMU device.
3658	*
3659	* @returns VBox status code.
3660	* @param pDevIns The device instance.
3661	* @param pIommuReg Pointer to a IOMMU registration structure.
3662	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
3663	* helpers.
3664	* @param pidxIommu Where to return the IOMMU index. Optional.
3665	*/
3666	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
3667	uint32_t *pidxIommu));
3668
3669	/**
3670	* Register the PIC device.
3671	*
3672	* @returns VBox status code.
3673	* @param pDevIns The device instance.
3674	* @param pPicReg Pointer to a PIC registration structure.
3675	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
3676	* helpers.
3677	* @sa PDMDevHlpPICSetUpContext
3678	*/
3679	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
3680
3681	/**
3682	* Register the APIC device.
3683	*
3684	* @returns VBox status code.
3685	* @param pDevIns The device instance.
3686	*/
3687	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
3688
3689	/**
3690	* Register the I/O APIC device.
3691	*
3692	* @returns VBox status code.
3693	* @param pDevIns The device instance.
3694	* @param pIoApicReg Pointer to a I/O APIC registration structure.
3695	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
3696	* helpers.
3697	*/
3698	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
3699
3700	/**
3701	* Register the HPET device.
3702	*
3703	* @returns VBox status code.
3704	* @param pDevIns The device instance.
3705	* @param pHpetReg Pointer to a HPET registration structure.
3706	* @param ppHpetHlpR3 Where to store the pointer to the HPET
3707	* helpers.
3708	*/
3709	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
3710
3711	/**
3712	* Register a raw PCI device.
3713	*
3714	* @returns VBox status code.
3715	* @param pDevIns The device instance.
3716	* @param pPciRawReg Pointer to a raw PCI registration structure.
3717	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
3718	* device helpers.
3719	*/
3720	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
3721
3722	/**
3723	* Register the DMA device.
3724	*
3725	* @returns VBox status code.
3726	* @param pDevIns The device instance.
3727	* @param pDmacReg Pointer to a DMAC registration structure.
3728	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
3729	*/
3730	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
3731
3732	/**
3733	* Register transfer function for DMA channel.
3734	*
3735	* @returns VBox status code.
3736	* @param pDevIns The device instance.
3737	* @param uChannel Channel number.
3738	* @param pfnTransferHandler Device specific transfer callback function.
3739	* @param pvUser User pointer to pass to the callback.
3740	* @thread EMT
3741	*/
3742	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
3743
3744	/**
3745	* Read memory.
3746	*
3747	* @returns VBox status code.
3748	* @param pDevIns The device instance.
3749	* @param uChannel Channel number.
3750	* @param pvBuffer Pointer to target buffer.
3751	* @param off DMA position.
3752	* @param cbBlock Block size.
3753	* @param pcbRead Where to store the number of bytes which was
3754	* read. optional.
3755	* @thread EMT
3756	*/
3757	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
3758
3759	/**
3760	* Write memory.
3761	*
3762	* @returns VBox status code.
3763	* @param pDevIns The device instance.
3764	* @param uChannel Channel number.
3765	* @param pvBuffer Memory to write.
3766	* @param off DMA position.
3767	* @param cbBlock Block size.
3768	* @param pcbWritten Where to store the number of bytes which was
3769	* written. optional.
3770	* @thread EMT
3771	*/
3772	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
3773
3774	/**
3775	* Set the DREQ line.
3776	*
3777	* @returns VBox status code.
3778	* @param pDevIns Device instance.
3779	* @param uChannel Channel number.
3780	* @param uLevel Level of the line.
3781	* @thread EMT
3782	*/
3783	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
3784
3785	/**
3786	* Get channel mode.
3787	*
3788	* @returns Channel mode. See specs.
3789	* @param pDevIns The device instance.
3790	* @param uChannel Channel number.
3791	* @thread EMT
3792	*/
3793	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
3794
3795	/**
3796	* Schedule DMA execution.
3797	*
3798	* @param pDevIns The device instance.
3799	* @thread Any thread.
3800	*/
3801	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
3802
3803	/**
3804	* Write CMOS value and update the checksum(s).
3805	*
3806	* @returns VBox status code.
3807	* @param pDevIns The device instance.
3808	* @param iReg The CMOS register index.
3809	* @param u8Value The CMOS register value.
3810	* @thread EMT
3811	*/
3812	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
3813
3814	/**
3815	* Read CMOS value.
3816	*
3817	* @returns VBox status code.
3818	* @param pDevIns The device instance.
3819	* @param iReg The CMOS register index.
3820	* @param pu8Value Where to store the CMOS register value.
3821	* @thread EMT
3822	*/
3823	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
3824
3825	/**
3826	* Assert that the current thread is the emulation thread.
3827	*
3828	* @returns True if correct.
3829	* @returns False if wrong.
3830	* @param pDevIns The device instance.
3831	* @param pszFile Filename of the assertion location.
3832	* @param iLine The linenumber of the assertion location.
3833	* @param pszFunction Function of the assertion location.
3834	*/
3835	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
3836
3837	/**
3838	* Assert that the current thread is NOT the emulation thread.
3839	*
3840	* @returns True if correct.
3841	* @returns False if wrong.
3842	* @param pDevIns The device instance.
3843	* @param pszFile Filename of the assertion location.
3844	* @param iLine The linenumber of the assertion location.
3845	* @param pszFunction Function of the assertion location.
3846	*/
3847	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
3848
3849	/**
3850	* Resolves the symbol for a raw-mode context interface.
3851	*
3852	* @returns VBox status code.
3853	* @param pDevIns The device instance.
3854	* @param pvInterface The interface structure.
3855	* @param cbInterface The size of the interface structure.
3856	* @param pszSymPrefix What to prefix the symbols in the list with
3857	* before resolving them. This must start with
3858	* 'dev' and contain the driver name.
3859	* @param pszSymList List of symbols corresponding to the interface.
3860	* There is generally a there is generally a define
3861	* holding this list associated with the interface
3862	* definition (INTERFACE_SYM_LIST). For more
3863	* details see PDMR3LdrGetInterfaceSymbols.
3864	* @thread EMT
3865	*/
3866	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
3867	const char pszSymPrefix, const char pszSymList));
3868
3869	/**
3870	* Resolves the symbol for a ring-0 context interface.
3871	*
3872	* @returns VBox status code.
3873	* @param pDevIns The device instance.
3874	* @param pvInterface The interface structure.
3875	* @param cbInterface The size of the interface structure.
3876	* @param pszSymPrefix What to prefix the symbols in the list with
3877	* before resolving them. This must start with
3878	* 'dev' and contain the driver name.
3879	* @param pszSymList List of symbols corresponding to the interface.
3880	* There is generally a there is generally a define
3881	* holding this list associated with the interface
3882	* definition (INTERFACE_SYM_LIST). For more
3883	* details see PDMR3LdrGetInterfaceSymbols.
3884	* @thread EMT
3885	*/
3886	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
3887	const char pszSymPrefix, const char pszSymList));
3888
3889	/**
3890	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
3891	*
3892	* @returns VBox status code.
3893	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
3894	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
3895	*
3896	* @param pDevIns The device instance.
3897	* @param uOperation The operation to perform.
3898	* @param u64Arg 64-bit integer argument.
3899	* @thread EMT
3900	*/
3901	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
3902
3903	/**
3904	* Gets the reason for the most recent VM suspend.
3905	*
3906	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
3907	* suspend has been made or if the pDevIns is invalid.
3908	* @param pDevIns The device instance.
3909	*/
3910	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
3911
3912	/**
3913	* Gets the reason for the most recent VM resume.
3914	*
3915	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
3916	* resume has been made or if the pDevIns is invalid.
3917	* @param pDevIns The device instance.
3918	*/
3919	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
3920
3921	/**
3922	* Requests the mapping of multiple guest page into ring-3.
3923	*
3924	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3925	* ASAP to release them.
3926	*
3927	* This API will assume your intention is to write to the pages, and will
3928	* therefore replace shared and zero pages. If you do not intend to modify the
3929	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
3930	*
3931	* @returns VBox status code.
3932	* @retval VINF_SUCCESS on success.
3933	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
3934	* backing or if any of the pages the page has any active access
3935	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
3936	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
3937	* an invalid physical address.
3938	*
3939	* @param pDevIns The device instance.
3940	* @param cPages Number of pages to lock.
3941	* @param paGCPhysPages The guest physical address of the pages that
3942	* should be mapped (@a cPages entries).
3943	* @param fFlags Flags reserved for future use, MBZ.
3944	* @param papvPages Where to store the ring-3 mapping addresses
3945	* corresponding to @a paGCPhysPages.
3946	* @param paLocks Where to store the locking information that
3947	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3948	* in length).
3949	*
3950	* @remark Avoid calling this API from within critical sections (other than the
3951	* PGM one) because of the deadlock risk when we have to delegating the
3952	* task to an EMT.
3953	* @thread Any.
3954	* @since 6.0.6
3955	*/
3956	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
3957	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
3958
3959	/**
3960	* Requests the mapping of multiple guest page into ring-3, for reading only.
3961	*
3962	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3963	* ASAP to release them.
3964	*
3965	* @returns VBox status code.
3966	* @retval VINF_SUCCESS on success.
3967	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
3968	* backing or if any of the pages the page has an active ALL access
3969	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
3970	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
3971	* an invalid physical address.
3972	*
3973	* @param pDevIns The device instance.
3974	* @param cPages Number of pages to lock.
3975	* @param paGCPhysPages The guest physical address of the pages that
3976	* should be mapped (@a cPages entries).
3977	* @param fFlags Flags reserved for future use, MBZ.
3978	* @param papvPages Where to store the ring-3 mapping addresses
3979	* corresponding to @a paGCPhysPages.
3980	* @param paLocks Where to store the lock information that
3981	* pfnPhysReleasePageMappingLock needs (@a cPages
3982	* in length).
3983	*
3984	* @remark Avoid calling this API from within critical sections.
3985	* @thread Any.
3986	* @since 6.0.6
3987	*/
3988	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
3989	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3990
3991	/**
3992	* Release the mappings of multiple guest pages.
3993	*
3994	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
3995	* pfnPhysBulkGCPhys2CCPtrReadOnly.
3996	*
3997	* @param pDevIns The device instance.
3998	* @param cPages Number of pages to unlock.
3999	* @param paLocks The lock structures initialized by the mapping
4000	* function (@a cPages in length).
4001	* @thread Any.
4002	* @since 6.0.6
4003	*/
4004	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4005
4006	/**
4007	* Returns the micro architecture used for the guest.
4008	*
4009	* @returns CPU micro architecture enum.
4010	* @param pDevIns The device instance.
4011	*/
4012	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4013
4014	/** Space reserved for future members.
4015	* @{ */
4016	DECLR3CALLBACKMEMBER(void, pfnReserved1,(void));
4017	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4018	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4019	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4020	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4021	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4022	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4023	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4024	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4025	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4026	/** @} */
4027
4028
4029	/** API available to trusted devices only.
4030	*
4031	* These APIs are providing unrestricted access to the guest and the VM,
4032	* or they are interacting intimately with PDM.
4033	*
4034	* @{
4035	*/
4036
4037	/**
4038	* Gets the user mode VM handle. Restricted API.
4039	*
4040	* @returns User mode VM Handle.
4041	* @param pDevIns The device instance.
4042	*/
4043	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4044
4045	/**
4046	* Gets the global VM handle. Restricted API.
4047	*
4048	* @returns VM Handle.
4049	* @param pDevIns The device instance.
4050	*/
4051	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4052
4053	/**
4054	* Gets the VMCPU handle. Restricted API.
4055	*
4056	* @returns VMCPU Handle.
4057	* @param pDevIns The device instance.
4058	*/
4059	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4060
4061	/**
4062	* The the VM CPU ID of the current thread (restricted API).
4063	*
4064	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4065	* @param pDevIns The device instance.
4066	*/
4067	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4068
4069	/**
4070	* Registers the VMM device heap or notifies about mapping/unmapping.
4071	*
4072	* This interface serves three purposes:
4073	*
4074	* -# Register the VMM device heap during device construction
4075	* for the HM to use.
4076	* -# Notify PDM/HM that it's mapped into guest address
4077	* space (i.e. usable).
4078	* -# Notify PDM/HM that it is being unmapped from the guest
4079	* address space (i.e. not usable).
4080	*
4081	* @returns VBox status code.
4082	* @param pDevIns The device instance.
4083	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4084	* not mapped.
4085	* @param pvHeap Ring 3 heap pointer.
4086	* @param cbHeap Size of the heap.
4087	* @thread EMT.
4088	*/
4089	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4090
4091	/**
4092	* Registers the firmware (BIOS, EFI) device with PDM.
4093	*
4094	* The firmware provides a callback table and gets a special PDM helper table.
4095	* There can only be one firmware device for a VM.
4096	*
4097	* @returns VBox status code.
4098	* @param pDevIns The device instance.
4099	* @param pFwReg Firmware registration structure.
4100	* @param ppFwHlp Where to return the firmware helper structure.
4101	* @remarks Only valid during device construction.
4102	* @thread EMT(0)
4103	*/
4104	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4105
4106	/**
4107	* Resets the VM.
4108	*
4109	* @returns The appropriate VBox status code to pass around on reset.
4110	* @param pDevIns The device instance.
4111	* @param fFlags PDMVMRESET_F_XXX flags.
4112	* @thread The emulation thread.
4113	*/
4114	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4115
4116	/**
4117	* Suspends the VM.
4118	*
4119	* @returns The appropriate VBox status code to pass around on suspend.
4120	* @param pDevIns The device instance.
4121	* @thread The emulation thread.
4122	*/
4123	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4124
4125	/**
4126	* Suspends, saves and powers off the VM.
4127	*
4128	* @returns The appropriate VBox status code to pass around.
4129	* @param pDevIns The device instance.
4130	* @thread An emulation thread.
4131	*/
4132	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4133
4134	/**
4135	* Power off the VM.
4136	*
4137	* @returns The appropriate VBox status code to pass around on power off.
4138	* @param pDevIns The device instance.
4139	* @thread The emulation thread.
4140	*/
4141	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4142
4143	/**
4144	* Checks if the Gate A20 is enabled or not.
4145	*
4146	* @returns true if A20 is enabled.
4147	* @returns false if A20 is disabled.
4148	* @param pDevIns The device instance.
4149	* @thread The emulation thread.
4150	*/
4151	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4152
4153	/**
4154	* Enables or disables the Gate A20.
4155	*
4156	* @param pDevIns The device instance.
4157	* @param fEnable Set this flag to enable the Gate A20; clear it
4158	* to disable.
4159	* @thread The emulation thread.
4160	*/
4161	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4162
4163	/**
4164	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4165	* thread.
4166	*
4167	* @param pDevIns The device instance.
4168	* @param iLeaf The CPUID leaf to get.
4169	* @param pEax Where to store the EAX value.
4170	* @param pEbx Where to store the EBX value.
4171	* @param pEcx Where to store the ECX value.
4172	* @param pEdx Where to store the EDX value.
4173	* @thread EMT.
4174	*/
4175	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4176
4177	/**
4178	* Get the current virtual clock time in a VM. The clock frequency must be
4179	* queried separately.
4180	*
4181	* @returns Current clock time.
4182	* @param pDevIns The device instance.
4183	*/
4184	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4185
4186	/**
4187	* Get the frequency of the virtual clock.
4188	*
4189	* @returns The clock frequency (not variable at run-time).
4190	* @param pDevIns The device instance.
4191	*/
4192	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4193
4194	/**
4195	* Get the current virtual clock time in a VM, in nanoseconds.
4196	*
4197	* @returns Current clock time (in ns).
4198	* @param pDevIns The device instance.
4199	*/
4200	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4201
4202	/**
4203	* Gets the support driver session.
4204	*
4205	* This is intended for working with the semaphore API.
4206	*
4207	* @returns Support driver session handle.
4208	* @param pDevIns The device instance.
4209	*/
4210	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4211
4212	/**
4213	* Queries a generic object from the VMM user.
4214	*
4215	* @returns Pointer to the object if found, NULL if not.
4216	* @param pDevIns The device instance.
4217	* @param pUuid The UUID of what's being queried. The UUIDs and
4218	* the usage conventions are defined by the user.
4219	*
4220	* @note It is strictly forbidden to call this internally in VBox! This
4221	* interface is exclusively for hacks in externally developed devices.
4222	*/
4223	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4224
4225	/**
4226	* Register a physical page access handler type.
4227	*
4228	* @returns VBox status code.
4229	* @param pDevIns The device instance.
4230	* @param enmKind The kind of access handler.
4231	* @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4232	* @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4233	* handler should be called.
4234	* @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4235	* ring-3 handler should be called.
4236	* @param pszHandlerRC The name of the raw-mode context handler, NULL if
4237	* the ring-3 handler should be called.
4238	* @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4239	* if the ring-3 handler should be called.
4240	* @param pszDesc The type description.
4241	* @param phType Where to return the type handle (cross context
4242	* safe).
4243	*/
4244	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4245	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4246	const char pszHandlerR0, const char pszPfHandlerR0,
4247	const char pszHandlerRC, const char pszPfHandlerRC,
4248	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4249
4250	/** @} */
4251
4252	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4253	uint32_t u32TheEnd;
4254	} PDMDEVHLPR3;
4255	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4256	/** Pointer to the R3 PDM Device API. */
4257	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4258	/** Pointer to the R3 PDM Device API, const variant. */
4259	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4260
4261
4262	/**
4263	* PDM Device API - RC Variant.
4264	*/
4265	typedef struct PDMDEVHLPRC
4266	{
4267	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4268	uint32_t u32Version;
4269
4270	/**
4271	* Sets up raw-mode context callback handlers for an I/O port range.
4272	*
4273	* The range must have been registered in ring-3 first using
4274	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4275	*
4276	* @returns VBox status.
4277	* @param pDevIns The device instance to register the ports with.
4278	* @param hIoPorts The I/O port range handle.
4279	* @param pfnOut Pointer to function which is gonna handle OUT
4280	* operations. Optional.
4281	* @param pfnIn Pointer to function which is gonna handle IN operations.
4282	* Optional.
4283	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4284	* operations. Optional.
4285	* @param pfnInStr Pointer to function which is gonna handle string IN
4286	* operations. Optional.
4287	* @param pvUser User argument to pass to the callbacks.
4288	*
4289	* @remarks Caller enters the device critical section prior to invoking the
4290	* registered callback methods.
4291	*
4292	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4293	* PDMDevHlpIoPortUnmap.
4294	*/
4295	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4296	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4297	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4298	void *pvUser));
4299
4300	/**
4301	* Sets up raw-mode context callback handlers for an MMIO region.
4302	*
4303	* The region must have been registered in ring-3 first using
4304	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4305	*
4306	* @returns VBox status.
4307	* @param pDevIns The device instance to register the ports with.
4308	* @param hRegion The MMIO region handle.
4309	* @param pfnWrite Pointer to function which is gonna handle Write
4310	* operations.
4311	* @param pfnRead Pointer to function which is gonna handle Read
4312	* operations.
4313	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4314	* operations. (optional)
4315	* @param pvUser User argument to pass to the callbacks.
4316	*
4317	* @remarks Caller enters the device critical section prior to invoking the
4318	* registered callback methods.
4319	*
4320	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4321	* PDMDevHlpMmioUnmap.
4322	*/
4323	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4324	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4325
4326	/**
4327	* Sets up a raw-mode mapping for an MMIO2 region.
4328	*
4329	* The region must have been created in ring-3 first using
4330	* PDMDevHlpMmio2Create().
4331	*
4332	* @returns VBox status.
4333	* @param pDevIns The device instance to register the ports with.
4334	* @param hRegion The MMIO2 region handle.
4335	* @param offSub Start of what to map into raw-mode. Must be page aligned.
4336	* @param cbSub Number of bytes to map into raw-mode. Must be page
4337	* aligned. Zero is an alias for everything.
4338	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4339	* @thread EMT(0)
4340	* @note Only available at VM creation time.
4341	*
4342	* @sa PDMDevHlpMmio2Create().
4343	*/
4344	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4345	size_t offSub, size_t cbSub, void **ppvMapping));
4346
4347	/**
4348	* Bus master physical memory read from the given PCI device.
4349	*
4350	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4351	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4352	* @param pDevIns The device instance.
4353	* @param pPciDev The PCI device structure. If NULL the default
4354	* PCI device for this device instance is used.
4355	* @param GCPhys Physical address start reading from.
4356	* @param pvBuf Where to put the read bits.
4357	* @param cbRead How many bytes to read.
4358	* @thread Any thread, but the call may involve the emulation thread.
4359	*/
4360	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4361	void *pvBuf, size_t cbRead));
4362
4363	/**
4364	* Bus master physical memory write from the given PCI device.
4365	*
4366	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4367	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4368	* @param pDevIns The device instance.
4369	* @param pPciDev The PCI device structure. If NULL the default
4370	* PCI device for this device instance is used.
4371	* @param GCPhys Physical address to write to.
4372	* @param pvBuf What to write.
4373	* @param cbWrite How many bytes to write.
4374	* @thread Any thread, but the call may involve the emulation thread.
4375	*/
4376	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4377	const void *pvBuf, size_t cbWrite));
4378
4379	/**
4380	* Set the IRQ for the given PCI device.
4381	*
4382	* @param pDevIns Device instance.
4383	* @param pPciDev The PCI device structure. If NULL the default
4384	* PCI device for this device instance is used.
4385	* @param iIrq IRQ number to set.
4386	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4387	* @thread Any thread, but will involve the emulation thread.
4388	*/
4389	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4390
4391	/**
4392	* Set ISA IRQ for a device.
4393	*
4394	* @param pDevIns Device instance.
4395	* @param iIrq IRQ number to set.
4396	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4397	* @thread Any thread, but will involve the emulation thread.
4398	*/
4399	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4400
4401	/**
4402	* Send an MSI straight to the I/O APIC.
4403	*
4404	* @param pDevIns PCI device instance.
4405	* @param GCPhys Physical address MSI request was written.
4406	* @param uValue Value written.
4407	* @thread Any thread, but will involve the emulation thread.
4408	*/
4409	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
4410
4411	/**
4412	* Read physical memory.
4413	*
4414	* @returns VINF_SUCCESS (for now).
4415	* @param pDevIns Device instance.
4416	* @param GCPhys Physical address start reading from.
4417	* @param pvBuf Where to put the read bits.
4418	* @param cbRead How many bytes to read.
4419	*/
4420	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
4421
4422	/**
4423	* Write to physical memory.
4424	*
4425	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4426	* @param pDevIns Device instance.
4427	* @param GCPhys Physical address to write to.
4428	* @param pvBuf What to write.
4429	* @param cbWrite How many bytes to write.
4430	*/
4431	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
4432
4433	/**
4434	* Checks if the Gate A20 is enabled or not.
4435	*
4436	* @returns true if A20 is enabled.
4437	* @returns false if A20 is disabled.
4438	* @param pDevIns Device instance.
4439	* @thread The emulation thread.
4440	*/
4441	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4442
4443	/**
4444	* Gets the VM state.
4445	*
4446	* @returns VM state.
4447	* @param pDevIns The device instance.
4448	* @thread Any thread (just keep in mind that it's volatile info).
4449	*/
4450	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4451
4452	/**
4453	* Set the VM error message
4454	*
4455	* @returns rc.
4456	* @param pDevIns Driver instance.
4457	* @param rc VBox status code.
4458	* @param SRC_POS Use RT_SRC_POS.
4459	* @param pszFormat Error message format string.
4460	* @param ... Error message arguments.
4461	*/
4462	DECLRCCALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4463	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4464
4465	/**
4466	* Set the VM error message
4467	*
4468	* @returns rc.
4469	* @param pDevIns Driver instance.
4470	* @param rc VBox status code.
4471	* @param SRC_POS Use RT_SRC_POS.
4472	* @param pszFormat Error message format string.
4473	* @param va Error message arguments.
4474	*/
4475	DECLRCCALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4476	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4477
4478	/**
4479	* Set the VM runtime error message
4480	*
4481	* @returns VBox status code.
4482	* @param pDevIns Device instance.
4483	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4484	* @param pszErrorId Error ID string.
4485	* @param pszFormat Error message format string.
4486	* @param ... Error message arguments.
4487	*/
4488	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4489	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4490
4491	/**
4492	* Set the VM runtime error message
4493	*
4494	* @returns VBox status code.
4495	* @param pDevIns Device instance.
4496	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4497	* @param pszErrorId Error ID string.
4498	* @param pszFormat Error message format string.
4499	* @param va Error message arguments.
4500	*/
4501	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4502	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
4503
4504	/**
4505	* Gets the VM handle. Restricted API.
4506	*
4507	* @returns VM Handle.
4508	* @param pDevIns Device instance.
4509	*/
4510	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4511
4512	/**
4513	* Gets the VMCPU handle. Restricted API.
4514	*
4515	* @returns VMCPU Handle.
4516	* @param pDevIns The device instance.
4517	*/
4518	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4519
4520	/**
4521	* The the VM CPU ID of the current thread (restricted API).
4522	*
4523	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4524	* @param pDevIns The device instance.
4525	*/
4526	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4527
4528	/**
4529	* Get the current virtual clock time in a VM. The clock frequency must be
4530	* queried separately.
4531	*
4532	* @returns Current clock time.
4533	* @param pDevIns The device instance.
4534	*/
4535	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4536
4537	/**
4538	* Get the frequency of the virtual clock.
4539	*
4540	* @returns The clock frequency (not variable at run-time).
4541	* @param pDevIns The device instance.
4542	*/
4543	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4544
4545	/**
4546	* Get the current virtual clock time in a VM, in nanoseconds.
4547	*
4548	* @returns Current clock time (in ns).
4549	* @param pDevIns The device instance.
4550	*/
4551	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4552
4553	/**
4554	* Gets the NOP critical section.
4555	*
4556	* @returns The ring-3 address of the NOP critical section.
4557	* @param pDevIns The device instance.
4558	*/
4559	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4560
4561	/**
4562	* Changes the device level critical section from the automatically created
4563	* default to one desired by the device constructor.
4564	*
4565	* Must first be done in ring-3.
4566	*
4567	* @returns VBox status code.
4568	* @param pDevIns The device instance.
4569	* @param pCritSect The critical section to use. NULL is not
4570	* valid, instead use the NOP critical
4571	* section.
4572	*/
4573	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4574
4575	/** @name Exported PDM Critical Section Functions
4576	* @{ */
4577	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4578	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4579	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4580	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4581	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4582	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4583	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4584	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4585	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4586	/** @} */
4587
4588	/**
4589	* Gets the trace buffer handle.
4590	*
4591	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4592	* really inteded for direct usage, thus no inline wrapper function.
4593	*
4594	* @returns Trace buffer handle or NIL_RTTRACEBUF.
4595	* @param pDevIns The device instance.
4596	*/
4597	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4598
4599	/**
4600	* Sets up the PCI bus for the raw-mode context.
4601	*
4602	* This must be called after ring-3 has registered the PCI bus using
4603	* PDMDevHlpPCIBusRegister().
4604	*
4605	* @returns VBox status code.
4606	* @param pDevIns The device instance.
4607	* @param pPciBusReg The PCI bus registration information for raw-mode,
4608	* considered volatile.
4609	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4610	*/
4611	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4612
4613	/**
4614	* Sets up the IOMMU for the raw-mode context.
4615	*
4616	* This must be called after ring-3 has registered the IOMMU using
4617	* PDMDevHlpIommuRegister().
4618	*
4619	* @returns VBox status code.
4620	* @param pDevIns The device instance.
4621	* @param pIommuReg The IOMMU registration information for raw-mode,
4622	* considered volatile.
4623	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
4624	*/
4625	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
4626
4627	/**
4628	* Sets up the PIC for the ring-0 context.
4629	*
4630	* This must be called after ring-3 has registered the PIC using
4631	* PDMDevHlpPICRegister().
4632	*
4633	* @returns VBox status code.
4634	* @param pDevIns The device instance.
4635	* @param pPicReg The PIC registration information for ring-0,
4636	* considered volatile and copied.
4637	* @param ppPicHlp Where to return the ring-0 PIC helpers.
4638	*/
4639	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4640
4641	/**
4642	* Sets up the APIC for the raw-mode context.
4643	*
4644	* This must be called after ring-3 has registered the APIC using
4645	* PDMDevHlpApicRegister().
4646	*
4647	* @returns VBox status code.
4648	* @param pDevIns The device instance.
4649	*/
4650	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
4651
4652	/**
4653	* Sets up the IOAPIC for the ring-0 context.
4654	*
4655	* This must be called after ring-3 has registered the PIC using
4656	* PDMDevHlpIoApicRegister().
4657	*
4658	* @returns VBox status code.
4659	* @param pDevIns The device instance.
4660	* @param pIoApicReg The PIC registration information for ring-0,
4661	* considered volatile and copied.
4662	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
4663	*/
4664	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4665
4666	/**
4667	* Sets up the HPET for the raw-mode context.
4668	*
4669	* This must be called after ring-3 has registered the PIC using
4670	* PDMDevHlpHpetRegister().
4671	*
4672	* @returns VBox status code.
4673	* @param pDevIns The device instance.
4674	* @param pHpetReg The PIC registration information for raw-mode,
4675	* considered volatile and copied.
4676	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
4677	*/
4678	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
4679
4680	/** Space reserved for future members.
4681	* @{ */
4682	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
4683	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
4684	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
4685	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
4686	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
4687	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
4688	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
4689	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
4690	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
4691	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
4692	/** @} */
4693
4694	/** Just a safety precaution. */
4695	uint32_t u32TheEnd;
4696	} PDMDEVHLPRC;
4697	/** Pointer PDM Device RC API. */
4698	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
4699	/** Pointer PDM Device RC API. */
4700	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
4701
4702	/** Current PDMDEVHLP version number. */
4703	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 15, 0)
4704
4705
4706	/**
4707	* PDM Device API - R0 Variant.
4708	*/
4709	typedef struct PDMDEVHLPR0
4710	{
4711	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
4712	uint32_t u32Version;
4713
4714	/**
4715	* Sets up ring-0 callback handlers for an I/O port range.
4716	*
4717	* The range must have been created in ring-3 first using
4718	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4719	*
4720	* @returns VBox status.
4721	* @param pDevIns The device instance to register the ports with.
4722	* @param hIoPorts The I/O port range handle.
4723	* @param pfnOut Pointer to function which is gonna handle OUT
4724	* operations. Optional.
4725	* @param pfnIn Pointer to function which is gonna handle IN operations.
4726	* Optional.
4727	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4728	* operations. Optional.
4729	* @param pfnInStr Pointer to function which is gonna handle string IN
4730	* operations. Optional.
4731	* @param pvUser User argument to pass to the callbacks.
4732	*
4733	* @remarks Caller enters the device critical section prior to invoking the
4734	* registered callback methods.
4735	*
4736	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
4737	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
4738	*/
4739	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4740	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4741	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4742	void *pvUser));
4743
4744	/**
4745	* Sets up ring-0 callback handlers for an MMIO region.
4746	*
4747	* The region must have been created in ring-3 first using
4748	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
4749	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
4750	*
4751	* @returns VBox status.
4752	* @param pDevIns The device instance to register the ports with.
4753	* @param hRegion The MMIO region handle.
4754	* @param pfnWrite Pointer to function which is gonna handle Write
4755	* operations.
4756	* @param pfnRead Pointer to function which is gonna handle Read
4757	* operations.
4758	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4759	* operations. (optional)
4760	* @param pvUser User argument to pass to the callbacks.
4761	*
4762	* @remarks Caller enters the device critical section prior to invoking the
4763	* registered callback methods.
4764	*
4765	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
4766	* PDMDevHlpMmioUnmap().
4767	*/
4768	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4769	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4770
4771	/**
4772	* Sets up a ring-0 mapping for an MMIO2 region.
4773	*
4774	* The region must have been created in ring-3 first using
4775	* PDMDevHlpMmio2Create().
4776	*
4777	* @returns VBox status.
4778	* @param pDevIns The device instance to register the ports with.
4779	* @param hRegion The MMIO2 region handle.
4780	* @param offSub Start of what to map into ring-0. Must be page aligned.
4781	* @param cbSub Number of bytes to map into ring-0. Must be page
4782	* aligned. Zero is an alias for everything.
4783	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4784	*
4785	* @thread EMT(0)
4786	* @note Only available at VM creation time.
4787	*
4788	* @sa PDMDevHlpMmio2Create().
4789	*/
4790	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
4791	void **ppvMapping));
4792
4793	/**
4794	* Bus master physical memory read from the given PCI device.
4795	*
4796	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
4797	* VERR_EM_MEMORY.
4798	* @param pDevIns The device instance.
4799	* @param pPciDev The PCI device structure. If NULL the default
4800	* PCI device for this device instance is used.
4801	* @param GCPhys Physical address start reading from.
4802	* @param pvBuf Where to put the read bits.
4803	* @param cbRead How many bytes to read.
4804	* @thread Any thread, but the call may involve the emulation thread.
4805	*/
4806	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4807	void *pvBuf, size_t cbRead));
4808
4809	/**
4810	* Bus master physical memory write from the given PCI device.
4811	*
4812	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
4813	* VERR_EM_MEMORY.
4814	* @param pDevIns The device instance.
4815	* @param pPciDev The PCI device structure. If NULL the default
4816	* PCI device for this device instance is used.
4817	* @param GCPhys Physical address to write to.
4818	* @param pvBuf What to write.
4819	* @param cbWrite How many bytes to write.
4820	* @thread Any thread, but the call may involve the emulation thread.
4821	*/
4822	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4823	const void *pvBuf, size_t cbWrite));
4824
4825	/**
4826	* Set the IRQ for the given PCI device.
4827	*
4828	* @param pDevIns Device instance.
4829	* @param pPciDev The PCI device structure. If NULL the default
4830	* PCI device for this device instance is used.
4831	* @param iIrq IRQ number to set.
4832	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4833	* @thread Any thread, but will involve the emulation thread.
4834	*/
4835	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4836
4837	/**
4838	* Set ISA IRQ for a device.
4839	*
4840	* @param pDevIns Device instance.
4841	* @param iIrq IRQ number to set.
4842	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4843	* @thread Any thread, but will involve the emulation thread.
4844	*/
4845	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4846
4847	/**
4848	* Send an MSI straight to the I/O APIC.
4849	*
4850	* @param pDevIns PCI device instance.
4851	* @param GCPhys Physical address MSI request was written.
4852	* @param uValue Value written.
4853	* @thread Any thread, but will involve the emulation thread.
4854	*/
4855	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
4856
4857	/**
4858	* Read physical memory.
4859	*
4860	* @returns VINF_SUCCESS (for now).
4861	* @param pDevIns Device instance.
4862	* @param GCPhys Physical address start reading from.
4863	* @param pvBuf Where to put the read bits.
4864	* @param cbRead How many bytes to read.
4865	*/
4866	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
4867
4868	/**
4869	* Write to physical memory.
4870	*
4871	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4872	* @param pDevIns Device instance.
4873	* @param GCPhys Physical address to write to.
4874	* @param pvBuf What to write.
4875	* @param cbWrite How many bytes to write.
4876	*/
4877	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
4878
4879	/**
4880	* Checks if the Gate A20 is enabled or not.
4881	*
4882	* @returns true if A20 is enabled.
4883	* @returns false if A20 is disabled.
4884	* @param pDevIns Device instance.
4885	* @thread The emulation thread.
4886	*/
4887	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4888
4889	/**
4890	* Gets the VM state.
4891	*
4892	* @returns VM state.
4893	* @param pDevIns The device instance.
4894	* @thread Any thread (just keep in mind that it's volatile info).
4895	*/
4896	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4897
4898	/**
4899	* Set the VM error message
4900	*
4901	* @returns rc.
4902	* @param pDevIns Driver instance.
4903	* @param rc VBox status code.
4904	* @param SRC_POS Use RT_SRC_POS.
4905	* @param pszFormat Error message format string.
4906	* @param ... Error message arguments.
4907	*/
4908	DECLR0CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4909	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4910
4911	/**
4912	* Set the VM error message
4913	*
4914	* @returns rc.
4915	* @param pDevIns Driver instance.
4916	* @param rc VBox status code.
4917	* @param SRC_POS Use RT_SRC_POS.
4918	* @param pszFormat Error message format string.
4919	* @param va Error message arguments.
4920	*/
4921	DECLR0CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4922	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4923
4924	/**
4925	* Set the VM runtime error message
4926	*
4927	* @returns VBox status code.
4928	* @param pDevIns Device instance.
4929	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4930	* @param pszErrorId Error ID string.
4931	* @param pszFormat Error message format string.
4932	* @param ... Error message arguments.
4933	*/
4934	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4935	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4936
4937	/**
4938	* Set the VM runtime error message
4939	*
4940	* @returns VBox status code.
4941	* @param pDevIns Device instance.
4942	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4943	* @param pszErrorId Error ID string.
4944	* @param pszFormat Error message format string.
4945	* @param va Error message arguments.
4946	*/
4947	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4948	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
4949
4950	/**
4951	* Gets the VM handle. Restricted API.
4952	*
4953	* @returns VM Handle.
4954	* @param pDevIns Device instance.
4955	*/
4956	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4957
4958	/**
4959	* Gets the VMCPU handle. Restricted API.
4960	*
4961	* @returns VMCPU Handle.
4962	* @param pDevIns The device instance.
4963	*/
4964	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4965
4966	/**
4967	* The the VM CPU ID of the current thread (restricted API).
4968	*
4969	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4970	* @param pDevIns The device instance.
4971	*/
4972	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4973
4974	/**
4975	* Translates a timer handle to a pointer.
4976	*
4977	* @returns The time address.
4978	* @param pDevIns The device instance.
4979	* @param hTimer The timer handle.
4980	*/
4981	DECLR0CALLBACKMEMBER(PTMTIMERR0, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
4982
4983	/** @name Timer handle method wrappers
4984	* @{ */
4985	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
4986	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
4987	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
4988	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
4989	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
4990	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
4991	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
4992	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
4993	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
4994	/** Takes the clock lock then enters the specified critical section. */
4995	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
4996	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
4997	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
4998	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
4999	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5000	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5001	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5002	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5003	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5004	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5005	/** @} */
5006
5007	/**
5008	* Get the current virtual clock time in a VM. The clock frequency must be
5009	* queried separately.
5010	*
5011	* @returns Current clock time.
5012	* @param pDevIns The device instance.
5013	*/
5014	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5015
5016	/**
5017	* Get the frequency of the virtual clock.
5018	*
5019	* @returns The clock frequency (not variable at run-time).
5020	* @param pDevIns The device instance.
5021	*/
5022	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5023
5024	/**
5025	* Get the current virtual clock time in a VM, in nanoseconds.
5026	*
5027	* @returns Current clock time (in ns).
5028	* @param pDevIns The device instance.
5029	*/
5030	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5031
5032	/** @name Exported PDM Queue Functions
5033	* @{ */
5034	DECLR0CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5035	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5036	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5037	DECLR0CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
5038	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5039	/** @} */
5040
5041	/** @name PDM Task
5042	* @{ */
5043	/**
5044	* Triggers the running the given task.
5045	*
5046	* @returns VBox status code.
5047	* @retval VINF_ALREADY_POSTED is the task is already pending.
5048	* @param pDevIns The device instance.
5049	* @param hTask The task to trigger.
5050	* @thread Any thread.
5051	*/
5052	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5053	/** @} */
5054
5055	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5056	* These semaphores can be signalled from ring-0.
5057	* @{ */
5058	/** @sa SUPSemEventSignal */
5059	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5060	/** @sa SUPSemEventWaitNoResume */
5061	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5062	/** @sa SUPSemEventWaitNsAbsIntr */
5063	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5064	/** @sa SUPSemEventWaitNsRelIntr */
5065	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5066	/** @sa SUPSemEventGetResolution */
5067	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5068	/** @} */
5069
5070	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5071	* These semaphores can be signalled from ring-0.
5072	* @{ */
5073	/** @sa SUPSemEventMultiSignal */
5074	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5075	/** @sa SUPSemEventMultiReset */
5076	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5077	/** @sa SUPSemEventMultiWaitNoResume */
5078	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5079	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5080	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5081	/** @sa SUPSemEventMultiWaitNsRelIntr */
5082	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5083	/** @sa SUPSemEventMultiGetResolution */
5084	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5085	/** @} */
5086
5087	/**
5088	* Gets the NOP critical section.
5089	*
5090	* @returns The ring-3 address of the NOP critical section.
5091	* @param pDevIns The device instance.
5092	*/
5093	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5094
5095	/**
5096	* Changes the device level critical section from the automatically created
5097	* default to one desired by the device constructor.
5098	*
5099	* Must first be done in ring-3.
5100	*
5101	* @returns VBox status code.
5102	* @param pDevIns The device instance.
5103	* @param pCritSect The critical section to use. NULL is not
5104	* valid, instead use the NOP critical
5105	* section.
5106	*/
5107	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5108
5109	/** @name Exported PDM Critical Section Functions
5110	* @{ */
5111	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5112	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5113	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5114	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5115	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5116	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5117	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5118	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5119	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5120	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5121	/** @} */
5122
5123	/**
5124	* Gets the trace buffer handle.
5125	*
5126	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5127	* really inteded for direct usage, thus no inline wrapper function.
5128	*
5129	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5130	* @param pDevIns The device instance.
5131	*/
5132	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5133
5134	/**
5135	* Sets up the PCI bus for the ring-0 context.
5136	*
5137	* This must be called after ring-3 has registered the PCI bus using
5138	* PDMDevHlpPCIBusRegister().
5139	*
5140	* @returns VBox status code.
5141	* @param pDevIns The device instance.
5142	* @param pPciBusReg The PCI bus registration information for ring-0,
5143	* considered volatile and copied.
5144	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5145	*/
5146	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5147
5148	/**
5149	* Sets up the IOMMU for the ring-0 context.
5150	*
5151	* This must be called after ring-3 has registered the IOMMU using
5152	* PDMDevHlpIommuRegister().
5153	*
5154	* @returns VBox status code.
5155	* @param pDevIns The device instance.
5156	* @param pIommuReg The IOMMU registration information for ring-0,
5157	* considered volatile and copied.
5158	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5159	*/
5160	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5161
5162	/**
5163	* Sets up the PIC for the ring-0 context.
5164	*
5165	* This must be called after ring-3 has registered the PIC using
5166	* PDMDevHlpPICRegister().
5167	*
5168	* @returns VBox status code.
5169	* @param pDevIns The device instance.
5170	* @param pPicReg The PIC registration information for ring-0,
5171	* considered volatile and copied.
5172	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5173	*/
5174	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5175
5176	/**
5177	* Sets up the APIC for the ring-0 context.
5178	*
5179	* This must be called after ring-3 has registered the APIC using
5180	* PDMDevHlpApicRegister().
5181	*
5182	* @returns VBox status code.
5183	* @param pDevIns The device instance.
5184	*/
5185	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5186
5187	/**
5188	* Sets up the IOAPIC for the ring-0 context.
5189	*
5190	* This must be called after ring-3 has registered the PIC using
5191	* PDMDevHlpIoApicRegister().
5192	*
5193	* @returns VBox status code.
5194	* @param pDevIns The device instance.
5195	* @param pIoApicReg The PIC registration information for ring-0,
5196	* considered volatile and copied.
5197	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5198	*/
5199	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5200
5201	/**
5202	* Sets up the HPET for the ring-0 context.
5203	*
5204	* This must be called after ring-3 has registered the PIC using
5205	* PDMDevHlpHpetRegister().
5206	*
5207	* @returns VBox status code.
5208	* @param pDevIns The device instance.
5209	* @param pHpetReg The PIC registration information for ring-0,
5210	* considered volatile and copied.
5211	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5212	*/
5213	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5214
5215	/** Space reserved for future members.
5216	* @{ */
5217	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5218	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5219	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5220	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5221	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5222	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5223	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5224	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5225	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5226	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5227	/** @} */
5228
5229	/** Just a safety precaution. */
5230	uint32_t u32TheEnd;
5231	} PDMDEVHLPR0;
5232	/** Pointer PDM Device R0 API. */
5233	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5234	/** Pointer PDM Device GC API. */
5235	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5236
5237	/** Current PDMDEVHLP version number. */
5238	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 17, 0)
5239
5240
5241	/**
5242	* PDM Device Instance.
5243	*/
5244	typedef struct PDMDEVINSR3
5245	{
5246	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5247	uint32_t u32Version;
5248	/** Device instance number. */
5249	uint32_t iInstance;
5250	/** Size of the ring-3, raw-mode and shared bits. */
5251	uint32_t cbRing3;
5252	/** Set if ring-0 context is enabled. */
5253	bool fR0Enabled;
5254	/** Set if raw-mode context is enabled. */
5255	bool fRCEnabled;
5256	/** Alignment padding. */
5257	bool afReserved[2];
5258	/** Pointer the HC PDM Device API. */
5259	PCPDMDEVHLPR3 pHlpR3;
5260	/** Pointer to the shared device instance data. */
5261	RTR3PTR pvInstanceDataR3;
5262	/** Pointer to the device instance data for ring-3. */
5263	RTR3PTR pvInstanceDataForR3;
5264	/** The critical section for the device.
5265	*
5266	* TM and IOM will enter this critical section before calling into the device
5267	* code. PDM will when doing power on, power off, reset, suspend and resume
5268	* notifications. SSM will currently not, but this will be changed later on.
5269	*
5270	* The device gets a critical section automatically assigned to it before
5271	* the constructor is called. If the constructor wishes to use a different
5272	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5273	* very early on.
5274	*/
5275	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5276	/** Pointer to device registration structure. */
5277	R3PTRTYPE(PCPDMDEVREG) pReg;
5278	/** Configuration handle. */
5279	R3PTRTYPE(PCFGMNODE) pCfg;
5280	/** The base interface of the device.
5281	*
5282	* The device constructor initializes this if it has any
5283	* device level interfaces to export. To obtain this interface
5284	* call PDMR3QueryDevice(). */
5285	PDMIBASE IBase;
5286
5287	/** Tracing indicator. */
5288	uint32_t fTracing;
5289	/** The tracing ID of this device. */
5290	uint32_t idTracing;
5291
5292	/** Ring-3 pointer to the raw-mode device instance. */
5293	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5294	/** Raw-mode address of the raw-mode device instance. */
5295	RTRGPTR pDevInsForRC;
5296	/** Ring-3 pointer to the raw-mode instance data. */
5297	RTR3PTR pvInstanceDataForRCR3;
5298
5299	/** PCI device structure size. */
5300	uint32_t cbPciDev;
5301	/** Number of PCI devices in apPciDevs. */
5302	uint32_t cPciDevs;
5303	/** Pointer to the PCI devices for this device.
5304	* (Allocated after the shared instance data.)
5305	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5306	* two devices ever needing it can use cbPciDev and do the address
5307	* calculations that for entries 8+. */
5308	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5309
5310	/** Temporarily. */
5311	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5312	/** Temporarily. */
5313	RTR0PTR pvInstanceDataR0;
5314	/** Temporarily. */
5315	RTRCPTR pvInstanceDataRC;
5316	/** Align the internal data more naturally. */
5317	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5318
5319	/** Internal data. */
5320	union
5321	{
5322	#ifdef PDMDEVINSINT_DECLARED
5323	PDMDEVINSINTR3 s;
5324	#endif
5325	uint8_t padding[HC_ARCH_BITS == 32 ? 0x30 : 0x50];
5326	} Internal;
5327
5328	/** Device instance data for ring-3. The size of this area is defined
5329	* in the PDMDEVREG::cbInstanceR3 field. */
5330	char achInstanceData[8];
5331	} PDMDEVINSR3;
5332
5333	/** Current PDMDEVINSR3 version number. */
5334	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5335
5336	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5337	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5338
5339
5340	/**
5341	* PDM ring-0 device instance.
5342	*/
5343	typedef struct PDMDEVINSR0
5344	{
5345	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5346	uint32_t u32Version;
5347	/** Device instance number. */
5348	uint32_t iInstance;
5349
5350	/** Pointer the HC PDM Device API. */
5351	PCPDMDEVHLPR0 pHlpR0;
5352	/** Pointer to the shared device instance data. */
5353	RTR0PTR pvInstanceDataR0;
5354	/** Pointer to the device instance data for ring-0. */
5355	RTR0PTR pvInstanceDataForR0;
5356	/** The critical section for the device.
5357	*
5358	* TM and IOM will enter this critical section before calling into the device
5359	* code. PDM will when doing power on, power off, reset, suspend and resume
5360	* notifications. SSM will currently not, but this will be changed later on.
5361	*
5362	* The device gets a critical section automatically assigned to it before
5363	* the constructor is called. If the constructor wishes to use a different
5364	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5365	* very early on.
5366	*/
5367	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5368	/** Pointer to the ring-0 device registration structure. */
5369	R0PTRTYPE(PCPDMDEVREGR0) pReg;
5370	/** Ring-3 address of the ring-3 device instance. */
5371	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5372	/** Ring-0 pointer to the ring-3 device instance. */
5373	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5374	/** Ring-0 pointer to the ring-3 instance data. */
5375	RTR0PTR pvInstanceDataForR3R0;
5376	/** Raw-mode address of the raw-mode device instance. */
5377	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5378	/** Ring-0 pointer to the raw-mode device instance. */
5379	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5380	/** Ring-0 pointer to the raw-mode instance data. */
5381	RTR0PTR pvInstanceDataForRCR0;
5382
5383	/** PCI device structure size. */
5384	uint32_t cbPciDev;
5385	/** Number of PCI devices in apPciDevs. */
5386	uint32_t cPciDevs;
5387	/** Pointer to the PCI devices for this device.
5388	* (Allocated after the shared instance data.)
5389	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5390	* two devices ever needing it can use cbPciDev and do the address
5391	* calculations that for entries 8+. */
5392	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5393
5394	/** Align the internal data more naturally. */
5395	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5396
5397	/** Internal data. */
5398	union
5399	{
5400	#ifdef PDMDEVINSINT_DECLARED
5401	PDMDEVINSINTR0 s;
5402	#endif
5403	uint8_t padding[HC_ARCH_BITS == 32 ? 0x20 : 0x40];
5404	} Internal;
5405
5406	/** Device instance data for ring-0. The size of this area is defined
5407	* in the PDMDEVREG::cbInstanceR0 field. */
5408	char achInstanceData[8];
5409	} PDMDEVINSR0;
5410
5411	/** Current PDMDEVINSR0 version number. */
5412	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5413
5414
5415	/**
5416	* PDM raw-mode device instance.
5417	*/
5418	typedef struct PDMDEVINSRC
5419	{
5420	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5421	uint32_t u32Version;
5422	/** Device instance number. */
5423	uint32_t iInstance;
5424
5425	/** Pointer the HC PDM Device API. */
5426	PCPDMDEVHLPRC pHlpRC;
5427	/** Pointer to the shared device instance data. */
5428	RTRGPTR pvInstanceDataRC;
5429	/** Pointer to the device instance data for raw-mode. */
5430	RTRGPTR pvInstanceDataForRC;
5431	/** The critical section for the device.
5432	*
5433	* TM and IOM will enter this critical section before calling into the device
5434	* code. PDM will when doing power on, power off, reset, suspend and resume
5435	* notifications. SSM will currently not, but this will be changed later on.
5436	*
5437	* The device gets a critical section automatically assigned to it before
5438	* the constructor is called. If the constructor wishes to use a different
5439	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5440	* very early on.
5441	*/
5442	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5443	/** Pointer to the raw-mode device registration structure. */
5444	RGPTRTYPE(PCPDMDEVREGRC) pReg;
5445
5446	/** PCI device structure size. */
5447	uint32_t cbPciDev;
5448	/** Number of PCI devices in apPciDevs. */
5449	uint32_t cPciDevs;
5450	/** Pointer to the PCI devices for this device.
5451	* (Allocated after the shared instance data.) */
5452	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5453
5454	/** Align the internal data more naturally. */
5455	uint32_t au32Padding[14];
5456
5457	/** Internal data. */
5458	union
5459	{
5460	#ifdef PDMDEVINSINT_DECLARED
5461	PDMDEVINSINTRC s;
5462	#endif
5463	uint8_t padding[0x10];
5464	} Internal;
5465
5466	/** Device instance data for ring-0. The size of this area is defined
5467	* in the PDMDEVREG::cbInstanceR0 field. */
5468	char achInstanceData[8];
5469	} PDMDEVINSRC;
5470
5471	/** Current PDMDEVINSR0 version number. */
5472	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5473
5474
5475	/** @def PDM_DEVINS_VERSION
5476	* Current PDMDEVINS version number. */
5477	/** @typedef PDMDEVINS
5478	* The device instance structure for the current context. */
5479	#ifdef IN_RING3
5480	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5481	typedef PDMDEVINSR3 PDMDEVINS;
5482	#elif defined(IN_RING0)
5483	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5484	typedef PDMDEVINSR0 PDMDEVINS;
5485	#elif defined(IN_RC)
5486	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5487	typedef PDMDEVINSRC PDMDEVINS;
5488	#else
5489	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5490	#endif
5491
5492	/**
5493	* Get the pointer to an PCI device.
5494	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5495	*/
5496	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5497	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5498	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5499
5500	/**
5501	* Calc the pointer to of a given PCI device.
5502	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5503	*/
5504	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5505	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5506	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
5507	: (PPDMPCIDEV)NULL )
5508
5509
5510	/**
5511	* Checks the structure versions of the device instance and device helpers,
5512	* returning if they are incompatible.
5513	*
5514	* This is for use in the constructor.
5515	*
5516	* @param pDevIns The device instance pointer.
5517	*/
5518	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5519	do \
5520	{ \
5521	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5522	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5523	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5524	VERR_PDM_DEVINS_VERSION_MISMATCH); \
5525	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5526	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5527	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5528	} while (0)
5529
5530	/**
5531	* Quietly checks the structure versions of the device instance and device
5532	* helpers, returning if they are incompatible.
5533	*
5534	* This is for use in the destructor.
5535	*
5536	* @param pDevIns The device instance pointer.
5537	*/
5538	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5539	do \
5540	{ \
5541	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5542	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5543	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5544	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5545	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5546	} while (0)
5547
5548	/**
5549	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
5550	* constructor - returns on failure.
5551	*
5552	* This should be invoked after having initialized the instance data
5553	* sufficiently for the correct operation of the destructor. The destructor is
5554	* always called!
5555	*
5556	* @param pDevIns Pointer to the PDM device instance.
5557	* @param pszValidValues Patterns describing the valid value names. See
5558	* RTStrSimplePatternMultiMatch for details on the
5559	* pattern syntax.
5560	* @param pszValidNodes Patterns describing the valid node (key) names.
5561	* Pass empty string if no valid nodes.
5562	*/
5563	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5564	do \
5565	{ \
5566	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5567	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5568	if (RT_SUCCESS(rcValCfg)) \
5569	{ /* likely */ } else return rcValCfg; \
5570	} while (0)
5571
5572	/** @def PDMDEV_ASSERT_EMT
5573	* Assert that the current thread is the emulation thread.
5574	*/
5575	#ifdef VBOX_STRICT
5576	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5577	#else
5578	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5579	#endif
5580
5581	/** @def PDMDEV_ASSERT_OTHER
5582	* Assert that the current thread is NOT the emulation thread.
5583	*/
5584	#ifdef VBOX_STRICT
5585	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5586	#else
5587	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5588	#endif
5589
5590	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5591	* Assert that the current thread is owner of the VM lock.
5592	*/
5593	#ifdef VBOX_STRICT
5594	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5595	#else
5596	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5597	#endif
5598
5599	/** @def PDMDEV_SET_ERROR
5600	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5601	*/
5602	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5603	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5604
5605	/** @def PDMDEV_SET_RUNTIME_ERROR
5606	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5607	*/
5608	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5609	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5610
5611	/** @def PDMDEVINS_2_RCPTR
5612	* Converts a PDM Device instance pointer a RC PDM Device instance pointer.
5613	*/
5614	#ifdef IN_RC
5615	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5616	#else
5617	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5618	#endif
5619
5620	/** @def PDMDEVINS_2_R3PTR
5621	* Converts a PDM Device instance pointer a R3 PDM Device instance pointer.
5622	*/
5623	#ifdef IN_RING3
5624	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5625	#else
5626	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5627	#endif
5628
5629	/** @def PDMDEVINS_2_R0PTR
5630	* Converts a PDM Device instance pointer a R0 PDM Device instance pointer.
5631	*/
5632	#ifdef IN_RING0
5633	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5634	#else
5635	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5636	#endif
5637
5638	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5639	* Converts a PDM device instance data pointer to a ring-0 one.
5640	* @deprecated
5641	*/
5642	#ifdef IN_RING0
5643	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5644	#else
5645	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5646	#endif
5647
5648
5649	/** @def PDMDEVINS_2_DATA
5650	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
5651	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5652	*
5653	* @note Do no use this macro in common code working on a core structure which
5654	* device specific code has expanded.
5655	*/
5656	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5657	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5658	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5659	{ \
5660	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5661	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5662	return pLambdaRet; \
5663	}(a_pDevIns))
5664	#else
5665	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5666	#endif
5667
5668	/** @def PDMDEVINS_2_DATA_CC
5669	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5670	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5671	*
5672	* @note Do no use this macro in common code working on a core structure which
5673	* device specific code has expanded.
5674	*/
5675	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5676	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5677	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5678	{ \
5679	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5680	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5681	return pLambdaRet; \
5682	}(a_pDevIns))
5683	#else
5684	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5685	#endif
5686
5687
5688	#ifdef IN_RING3
5689
5690	/**
5691	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
5692	*/
5693	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5694	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
5695	PIOMIOPORTHANDLE phIoPorts)
5696	{
5697	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5698	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5699	if (RT_SUCCESS(rc))
5700	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5701	return rc;
5702	}
5703
5704	/**
5705	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
5706	*/
5707	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5708	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
5709	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5710	{
5711	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5712	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5713	if (RT_SUCCESS(rc))
5714	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5715	return rc;
5716	}
5717
5718	/**
5719	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
5720	*/
5721	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5722	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5723	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5724	{
5725	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5726	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5727	if (RT_SUCCESS(rc))
5728	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5729	return rc;
5730	}
5731
5732	/**
5733	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
5734	*/
5735	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5736	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5737	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5738	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5739	{
5740	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5741	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5742	if (RT_SUCCESS(rc))
5743	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5744	return rc;
5745	}
5746
5747	/**
5748	* @sa PDMDevHlpIoPortCreateEx
5749	*/
5750	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5751	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
5752	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5753	{
5754	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
5755	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5756	}
5757
5758
5759	/**
5760	* @sa PDMDevHlpIoPortCreateEx
5761	*/
5762	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5763	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
5764	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5765	{
5766	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5767	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5768	}
5769
5770	/**
5771	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
5772	*/
5773	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
5774	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5775	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5776	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5777	{
5778	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
5779	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5780	}
5781
5782	/**
5783	* @copydoc PDMDEVHLPR3::pfnIoPortMap
5784	*/
5785	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
5786	{
5787	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
5788	}
5789
5790	/**
5791	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
5792	*/
5793	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5794	{
5795	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
5796	}
5797
5798	/**
5799	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
5800	*/
5801	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5802	{
5803	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
5804	}
5805
5806
5807	#endif /* IN_RING3 */
5808	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
5809
5810	/**
5811	* @sa PDMDevHlpIoPortSetUpContextEx
5812	*/
5813	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5814	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
5815	{
5816	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
5817	}
5818
5819	/**
5820	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
5821	*/
5822	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5823	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5824	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
5825	{
5826	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
5827	}
5828
5829	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
5830	#ifdef IN_RING3
5831
5832	/**
5833	* @sa PDMDevHlpMmioCreateEx
5834	*/
5835	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5836	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
5837	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
5838	{
5839	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
5840	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
5841	}
5842
5843	/**
5844	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
5845	*/
5846	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
5847	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5848	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
5849	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
5850	{
5851	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
5852	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
5853	}
5854
5855	/**
5856	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
5857	*/
5858	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
5859	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
5860	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
5861	{
5862	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
5863	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
5864	if (RT_SUCCESS(rc))
5865	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
5866	return rc;
5867	}
5868
5869	/**
5870	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
5871	*/
5872	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
5873	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
5874	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
5875	const char *pszDesc, PIOMMMIOHANDLE phRegion)
5876	{
5877	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
5878	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
5879	if (RT_SUCCESS(rc))
5880	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
5881	return rc;
5882	}
5883
5884	/**
5885	* @copydoc PDMDEVHLPR3::pfnMmioMap
5886	*/
5887	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
5888	{
5889	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
5890	}
5891
5892	/**
5893	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
5894	*/
5895	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
5896	{
5897	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
5898	}
5899
5900	/**
5901	* @copydoc PDMDEVHLPR3::pfnMmioReduce
5902	*/
5903	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
5904	{
5905	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
5906	}
5907
5908	/**
5909	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
5910	*/
5911	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
5912	{
5913	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
5914	}
5915
5916	#endif /* IN_RING3 */
5917	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
5918
5919	/**
5920	* @sa PDMDevHlpMmioSetUpContextEx
5921	*/
5922	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
5923	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
5924	{
5925	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
5926	}
5927
5928	/**
5929	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
5930	*/
5931	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5932	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
5933	{
5934	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
5935	}
5936
5937	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
5938	#ifdef IN_RING3
5939
5940	/**
5941	* @copydoc PDMDEVHLPR3::pfnMmio2Create
5942	*/
5943	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
5944	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
5945	{
5946	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
5947	}
5948
5949	/**
5950	* @copydoc PDMDEVHLPR3::pfnMmio2Map
5951	*/
5952	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
5953	{
5954	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
5955	}
5956
5957	/**
5958	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
5959	*/
5960	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
5961	{
5962	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
5963	}
5964
5965	/**
5966	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
5967	*/
5968	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
5969	{
5970	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
5971	}
5972
5973	/**
5974	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
5975	*/
5976	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
5977	{
5978	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
5979	}
5980
5981	#endif /* IN_RING3 */
5982	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
5983
5984	/**
5985	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
5986	*/
5987	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
5988	size_t offSub, size_t cbSub, void **ppvMapping)
5989	{
5990	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
5991	}
5992
5993	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
5994	#ifdef IN_RING3
5995
5996	/**
5997	* @copydoc PDMDEVHLPR3::pfnROMRegister
5998	*/
5999	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6000	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6001	{
6002	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6003	}
6004
6005	/**
6006	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6007	*/
6008	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6009	{
6010	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6011	}
6012
6013	/**
6014	* Register a save state data unit.
6015	*
6016	* @returns VBox status.
6017	* @param pDevIns The device instance.
6018	* @param uVersion Data layout version number.
6019	* @param cbGuess The approximate amount of data in the unit.
6020	* Only for progress indicators.
6021	* @param pfnSaveExec Execute save callback, optional.
6022	* @param pfnLoadExec Execute load callback, optional.
6023	*/
6024	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6025	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6026	{
6027	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6028	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6029	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6030	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6031	}
6032
6033	/**
6034	* Register a save state data unit with a live save callback as well.
6035	*
6036	* @returns VBox status.
6037	* @param pDevIns The device instance.
6038	* @param uVersion Data layout version number.
6039	* @param cbGuess The approximate amount of data in the unit.
6040	* Only for progress indicators.
6041	* @param pfnLiveExec Execute live callback, optional.
6042	* @param pfnSaveExec Execute save callback, optional.
6043	* @param pfnLoadExec Execute load callback, optional.
6044	*/
6045	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6046	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6047	{
6048	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6049	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6050	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6051	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6052	}
6053
6054	/**
6055	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6056	*/
6057	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6058	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6059	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6060	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6061	{
6062	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6063	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6064	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6065	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6066	}
6067
6068	/**
6069	* @copydoc PDMDEVHLPR3::pfnTMTimerCreate
6070	*/
6071	DECLINLINE(int) PDMDevHlpTMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6072	uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
6073	{
6074	return pDevIns->pHlpR3->pfnTMTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
6075	}
6076
6077	/**
6078	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6079	*/
6080	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6081	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6082	{
6083	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6084	}
6085
6086	#endif /* IN_RING3 */
6087
6088	/**
6089	* @copydoc PDMDEVHLPR3::pfnTimerToPtr
6090	*/
6091	DECLINLINE(PTMTIMER) PDMDevHlpTimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6092	{
6093	return pDevIns->CTX_SUFF(pHlp)->pfnTimerToPtr(pDevIns, hTimer);
6094	}
6095
6096	/**
6097	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6098	*/
6099	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6100	{
6101	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6102	}
6103
6104	/**
6105	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6106	*/
6107	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6108	{
6109	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6110	}
6111
6112	/**
6113	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6114	*/
6115	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6116	{
6117	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6118	}
6119
6120	/**
6121	* @copydoc PDMDEVHLPR3::pfnTimerGet
6122	*/
6123	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6124	{
6125	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6126	}
6127
6128	/**
6129	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6130	*/
6131	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6132	{
6133	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6134	}
6135
6136	/**
6137	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6138	*/
6139	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6140	{
6141	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6142	}
6143
6144	/**
6145	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6146	*/
6147	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6148	{
6149	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6150	}
6151
6152	/**
6153	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6154	*/
6155	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6156	{
6157	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6158	}
6159
6160	/**
6161	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
6162	*/
6163	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6164	{
6165	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6166	}
6167
6168	/**
6169	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6170	*/
6171	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6172	{
6173	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6174	}
6175
6176	/**
6177	* @copydoc PDMDEVHLPR3::pfnTimerSet
6178	*/
6179	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6180	{
6181	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6182	}
6183
6184	/**
6185	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6186	*/
6187	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6188	{
6189	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6190	}
6191
6192	/**
6193	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6194	*/
6195	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6196	{
6197	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6198	}
6199
6200	/**
6201	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6202	*/
6203	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6204	{
6205	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6206	}
6207
6208	/**
6209	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6210	*/
6211	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6212	{
6213	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6214	}
6215
6216	/**
6217	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6218	*/
6219	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6220	{
6221	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6222	}
6223
6224	/**
6225	* @copydoc PDMDEVHLPR3::pfnTimerStop
6226	*/
6227	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6228	{
6229	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6230	}
6231
6232	/**
6233	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6234	*/
6235	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6236	{
6237	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6238	}
6239
6240	/**
6241	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6242	*/
6243	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6244	{
6245	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6246	}
6247
6248	#ifdef IN_RING3
6249
6250	/**
6251	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6252	*/
6253	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6254	{
6255	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6256	}
6257
6258	/**
6259	* @copydoc PDMDEVHLPR3::pfnTimerSave
6260	*/
6261	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6262	{
6263	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6264	}
6265
6266	/**
6267	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6268	*/
6269	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6270	{
6271	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6272	}
6273
6274	/**
6275	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6276	*/
6277	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6278	{
6279	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6280	}
6281
6282	/**
6283	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6284	*/
6285	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6286	{
6287	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6288	}
6289
6290	#endif
6291
6292	/**
6293	* @copydoc PDMDEVHLPR3::pfnPhysRead
6294	*/
6295	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6296	{
6297	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
6298	}
6299
6300	/**
6301	* @copydoc PDMDEVHLPR3::pfnPhysWrite
6302	*/
6303	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6304	{
6305	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
6306	}
6307
6308	#ifdef IN_RING3
6309
6310	/**
6311	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6312	*/
6313	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6314	{
6315	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6316	}
6317
6318	/**
6319	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6320	*/
6321	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6322	PPGMPAGEMAPLOCK pLock)
6323	{
6324	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6325	}
6326
6327	/**
6328	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6329	*/
6330	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6331	{
6332	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6333	}
6334
6335	/**
6336	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6337	*/
6338	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6339	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6340	{
6341	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6342	}
6343
6344	/**
6345	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6346	*/
6347	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6348	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6349	{
6350	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6351	}
6352
6353	/**
6354	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6355	*/
6356	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6357	{
6358	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6359	}
6360
6361	/**
6362	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
6363	*/
6364	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
6365	{
6366	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
6367	}
6368
6369	/**
6370	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6371	*/
6372	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6373	{
6374	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6375	}
6376
6377	/**
6378	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6379	*/
6380	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6381	{
6382	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6383	}
6384
6385	/**
6386	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6387	*/
6388	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6389	{
6390	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6391	}
6392
6393	/**
6394	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6395	*/
6396	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6397	{
6398	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6399	}
6400
6401	/**
6402	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6403	*/
6404	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6405	{
6406	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6407	}
6408
6409	/**
6410	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
6411	*/
6412	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6413	{
6414	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6415	}
6416	#endif /* IN_RING3 */
6417
6418	/**
6419	* @copydoc PDMDEVHLPR3::pfnVMState
6420	*/
6421	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6422	{
6423	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6424	}
6425
6426	#ifdef IN_RING3
6427	/**
6428	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6429	*/
6430	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6431	{
6432	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6433	}
6434	#endif /* IN_RING3 */
6435
6436	/**
6437	* @copydoc PDMDEVHLPR3::pfnVMSetError
6438	*/
6439	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6440	const char *pszFormat, ...)
6441	{
6442	va_list va;
6443	va_start(va, pszFormat);
6444	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6445	va_end(va);
6446	return rc;
6447	}
6448
6449	/**
6450	* @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError
6451	*/
6452	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6453	const char *pszFormat, ...)
6454	{
6455	va_list va;
6456	int rc;
6457	va_start(va, pszFormat);
6458	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6459	va_end(va);
6460	return rc;
6461	}
6462
6463	/**
6464	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6465	*
6466	* @returns VBox status code which must be passed up to the VMM. This will be
6467	* VINF_SUCCESS in non-strict builds.
6468	* @param pDevIns The device instance.
6469	* @param SRC_POS Use RT_SRC_POS.
6470	* @param pszFormat Message. (optional)
6471	* @param ... Message parameters.
6472	*/
6473	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6474	{
6475	#ifdef VBOX_STRICT
6476	# ifdef IN_RING3
6477	int rc;
6478	va_list args;
6479	va_start(args, pszFormat);
6480	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6481	va_end(args);
6482	return rc;
6483	# else
6484	NOREF(pDevIns);
6485	NOREF(pszFile);
6486	NOREF(iLine);
6487	NOREF(pszFunction);
6488	NOREF(pszFormat);
6489	return VINF_EM_DBG_STOP;
6490	# endif
6491	#else
6492	NOREF(pDevIns);
6493	NOREF(pszFile);
6494	NOREF(iLine);
6495	NOREF(pszFunction);
6496	NOREF(pszFormat);
6497	return VINF_SUCCESS;
6498	#endif
6499	}
6500
6501	#ifdef IN_RING3
6502
6503	/**
6504	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6505	*/
6506	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6507	{
6508	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6509	}
6510
6511	/**
6512	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6513	*/
6514	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6515	{
6516	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6517	}
6518
6519	/**
6520	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6521	*/
6522	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6523	{
6524	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6525	}
6526
6527	/**
6528	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
6529	*/
6530	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
6531	{
6532	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6533	}
6534
6535	/**
6536	* Same as pfnSTAMRegister except that the name is specified in a
6537	* RTStrPrintf like fashion.
6538	*
6539	* @returns VBox status.
6540	* @param pDevIns Device instance of the DMA.
6541	* @param pvSample Pointer to the sample.
6542	* @param enmType Sample type. This indicates what pvSample is
6543	* pointing at.
6544	* @param enmVisibility Visibility type specifying whether unused
6545	* statistics should be visible or not.
6546	* @param enmUnit Sample unit.
6547	* @param pszDesc Sample description.
6548	* @param pszName Sample name format string, unix path style. If
6549	* this does not start with a '/', the default
6550	* prefix will be prepended, otherwise it will be
6551	* used as-is.
6552	* @param ... Arguments to the format string.
6553	*/
6554	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6555	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6556	const char pszDesc, const char pszName, ...)
6557	{
6558	va_list va;
6559	va_start(va, pszName);
6560	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6561	va_end(va);
6562	}
6563
6564	/**
6565	* Registers the device with the default PCI bus.
6566	*
6567	* @returns VBox status code.
6568	* @param pDevIns The device instance.
6569	* @param pPciDev The PCI device structure.
6570	* This must be kept in the instance data.
6571	* The PCI configuration must be initialized before registration.
6572	*/
6573	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6574	{
6575	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
6576	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6577	}
6578
6579	/**
6580	* @copydoc PDMDEVHLPR3::pfnPCIRegister
6581	*/
6582	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6583	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6584	{
6585	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6586	}
6587
6588	/**
6589	* Initialize MSI emulation support for the first PCI device.
6590	*
6591	* @returns VBox status code.
6592	* @param pDevIns The device instance.
6593	* @param pMsiReg MSI emulation registration structure.
6594	*/
6595	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6596	{
6597	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6598	}
6599
6600	/**
6601	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6602	*/
6603	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6604	{
6605	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6606	}
6607
6608	/**
6609	* Registers a I/O port region for the default PCI device.
6610	*
6611	* @returns VBox status code.
6612	* @param pDevIns The device instance.
6613	* @param iRegion The region number.
6614	* @param cbRegion Size of the region.
6615	* @param hIoPorts Handle to the I/O port region.
6616	*/
6617	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
6618	{
6619	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6620	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
6621	}
6622
6623	/**
6624	* Registers a I/O port region for the default PCI device, custom map/unmap.
6625	*
6626	* @returns VBox status code.
6627	* @param pDevIns The device instance.
6628	* @param iRegion The region number.
6629	* @param cbRegion Size of the region.
6630	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6631	* callback will be invoked holding only the PDM lock.
6632	* The device lock will _not_ be taken (due to lock
6633	* order).
6634	*/
6635	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6636	PFNPCIIOREGIONMAP pfnMapUnmap)
6637	{
6638	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6639	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6640	UINT64_MAX, pfnMapUnmap);
6641	}
6642
6643	/**
6644	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
6645	* and registering an I/O port region for the default PCI device.
6646	*
6647	* @returns VBox status code.
6648	* @param pDevIns The device instance to register the ports with.
6649	* @param cPorts The count of I/O ports in the region (the size).
6650	* @param iPciRegion The PCI device region.
6651	* @param pfnOut Pointer to function which is gonna handle OUT
6652	* operations. Optional.
6653	* @param pfnIn Pointer to function which is gonna handle IN operations.
6654	* Optional.
6655	* @param pvUser User argument to pass to the callbacks.
6656	* @param pszDesc Pointer to description string. This must not be freed.
6657	* @param paExtDescs Extended per-port descriptions, optional. Partial range
6658	* coverage is allowed. This must not be freed.
6659	* @param phIoPorts Where to return the I/O port range handle.
6660	*
6661	*/
6662	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
6663	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6664	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6665
6666	{
6667	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
6668	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6669	if (RT_SUCCESS(rc))
6670	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
6671	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6672	phIoPorts, NULL /pfnMapUnmap*/);
6673	return rc;
6674	}
6675
6676	/**
6677	* Registers an MMIO region for the default PCI device.
6678	*
6679	* @returns VBox status code.
6680	* @param pDevIns The device instance.
6681	* @param iRegion The region number.
6682	* @param cbRegion Size of the region.
6683	* @param enmType PCI_ADDRESS_SPACE_MEM or
6684	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6685	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6686	* @param hMmioRegion Handle to the MMIO region.
6687	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6688	* callback will be invoked holding only the PDM lock.
6689	* The device lock will _not_ be taken (due to lock
6690	* order).
6691	*/
6692	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
6693	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
6694	{
6695	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6696	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6697	hMmioRegion, pfnMapUnmap);
6698	}
6699
6700	/**
6701	* Registers an MMIO region for the default PCI device, extended version.
6702	*
6703	* @returns VBox status code.
6704	* @param pDevIns The device instance.
6705	* @param pPciDev The PCI device structure.
6706	* @param iRegion The region number.
6707	* @param cbRegion Size of the region.
6708	* @param enmType PCI_ADDRESS_SPACE_MEM or
6709	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6710	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6711	* @param hMmioRegion Handle to the MMIO region.
6712	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6713	* callback will be invoked holding only the PDM lock.
6714	* The device lock will _not_ be taken (due to lock
6715	* order).
6716	*/
6717	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
6718	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
6719	PFNPCIIOREGIONMAP pfnMapUnmap)
6720	{
6721	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
6722	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6723	hMmioRegion, pfnMapUnmap);
6724	}
6725
6726	/**
6727	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
6728	* and registering an MMIO region for the default PCI device.
6729	*
6730	* @returns VBox status code.
6731	* @param pDevIns The device instance to register the ports with.
6732	* @param cbRegion The size of the region in bytes.
6733	* @param iPciRegion The PCI device region.
6734	* @param enmType PCI_ADDRESS_SPACE_MEM or
6735	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6736	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6737	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
6738	* @param pfnWrite Pointer to function which is gonna handle Write
6739	* operations.
6740	* @param pfnRead Pointer to function which is gonna handle Read
6741	* operations.
6742	* @param pvUser User argument to pass to the callbacks.
6743	* @param pszDesc Pointer to description string. This must not be freed.
6744	* @param phRegion Where to return the MMIO region handle.
6745	*
6746	*/
6747	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
6748	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6749	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6750
6751	{
6752	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
6753	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
6754	if (RT_SUCCESS(rc))
6755	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
6756	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6757	phRegion, NULL /pfnMapUnmap*/);
6758	return rc;
6759	}
6760
6761
6762	/**
6763	* Registers an MMIO2 region for the default PCI device.
6764	*
6765	* @returns VBox status code.
6766	* @param pDevIns The device instance.
6767	* @param iRegion The region number.
6768	* @param cbRegion Size of the region.
6769	* @param enmType PCI_ADDRESS_SPACE_MEM or
6770	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6771	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6772	* @param hMmio2Region Handle to the MMIO2 region.
6773	*/
6774	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6775	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
6776	{
6777	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6778	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6779	hMmio2Region, NULL);
6780	}
6781
6782	/**
6783	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
6784	* and registering an MMIO2 region for the default PCI device, extended edition.
6785	*
6786	* @returns VBox status code.
6787	* @param pDevIns The device instance to register the ports with.
6788	* @param cbRegion The size of the region in bytes.
6789	* @param iPciRegion The PCI device region.
6790	* @param enmType PCI_ADDRESS_SPACE_MEM or
6791	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6792	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6793	* @param pszDesc Pointer to description string. This must not be freed.
6794	* @param ppvMapping Where to store the address of the ring-3 mapping of
6795	* the memory.
6796	* @param phRegion Where to return the MMIO2 region handle.
6797	*
6798	*/
6799	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
6800	PCIADDRESSSPACE enmType, const char *pszDesc,
6801	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
6802
6803	{
6804	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
6805	pszDesc, ppvMapping, phRegion);
6806	if (RT_SUCCESS(rc))
6807	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
6808	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6809	phRegion, NULL /pfnCallback*/);
6810	return rc;
6811	}
6812
6813	/**
6814	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
6815	* and registering an MMIO2 region for the default PCI device.
6816	*
6817	* @returns VBox status code.
6818	* @param pDevIns The device instance to register the ports with.
6819	* @param cbRegion The size of the region in bytes.
6820	* @param iPciRegion The PCI device region.
6821	* @param enmType PCI_ADDRESS_SPACE_MEM or
6822	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6823	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6824	* @param fMmio2Flags To be defined, must be zero.
6825	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6826	* callback will be invoked holding only the PDM lock.
6827	* The device lock will _not_ be taken (due to lock
6828	* order).
6829	* @param pszDesc Pointer to description string. This must not be freed.
6830	* @param ppvMapping Where to store the address of the ring-3 mapping of
6831	* the memory.
6832	* @param phRegion Where to return the MMIO2 region handle.
6833	*
6834	*/
6835	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
6836	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
6837	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6838
6839	{
6840	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
6841	pszDesc, ppvMapping, phRegion);
6842	if (RT_SUCCESS(rc))
6843	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
6844	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6845	*phRegion, pfnMapUnmap);
6846	return rc;
6847	}
6848
6849	/**
6850	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
6851	*/
6852	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
6853	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
6854	{
6855	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
6856	}
6857
6858	/**
6859	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
6860	*/
6861	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
6862	unsigned cb, uint32_t *pu32Value)
6863	{
6864	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
6865	}
6866
6867	/**
6868	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
6869	*/
6870	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
6871	unsigned cb, uint32_t u32Value)
6872	{
6873	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
6874	}
6875
6876	#endif /* IN_RING3 */
6877
6878	/**
6879	* Bus master physical memory read from the default PCI device.
6880	*
6881	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
6882	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
6883	* @param pDevIns The device instance.
6884	* @param GCPhys Physical address start reading from.
6885	* @param pvBuf Where to put the read bits.
6886	* @param cbRead How many bytes to read.
6887	* @thread Any thread, but the call may involve the emulation thread.
6888	*/
6889	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6890	{
6891	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead);
6892	}
6893
6894	/**
6895	* @copydoc PDMDEVHLPR3::pfnPCIPhysRead
6896	*/
6897	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6898	{
6899	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead);
6900	}
6901
6902	/**
6903	* Bus master physical memory write from the default PCI device.
6904	*
6905	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
6906	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
6907	* @param pDevIns The device instance.
6908	* @param GCPhys Physical address to write to.
6909	* @param pvBuf What to write.
6910	* @param cbWrite How many bytes to write.
6911	* @thread Any thread, but the call may involve the emulation thread.
6912	*/
6913	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6914	{
6915	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite);
6916	}
6917
6918	/**
6919	* @copydoc PDMDEVHLPR3::pfnPCIPhysWrite
6920	*/
6921	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6922	{
6923	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite);
6924	}
6925
6926	/**
6927	* Sets the IRQ for the default PCI device.
6928	*
6929	* @param pDevIns The device instance.
6930	* @param iIrq IRQ number to set.
6931	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
6932	* @thread Any thread, but will involve the emulation thread.
6933	*/
6934	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
6935	{
6936	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
6937	}
6938
6939	/**
6940	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
6941	*/
6942	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
6943	{
6944	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
6945	}
6946
6947	/**
6948	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
6949	* the request when not called from EMT.
6950	*
6951	* @param pDevIns The device instance.
6952	* @param iIrq IRQ number to set.
6953	* @param iLevel IRQ level.
6954	* @thread Any thread, but will involve the emulation thread.
6955	*/
6956	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
6957	{
6958	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
6959	}
6960
6961	/**
6962	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
6963	*/
6964	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
6965	{
6966	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
6967	}
6968
6969	/**
6970	* @copydoc PDMDEVHLPR3::pfnISASetIrq
6971	*/
6972	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
6973	{
6974	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
6975	}
6976
6977	/**
6978	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
6979	*/
6980	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
6981	{
6982	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
6983	}
6984
6985	/**
6986	* @copydoc PDMDEVHLPR3::pfnIoApicSendMsi
6987	*/
6988	DECLINLINE(void) PDMDevHlpIoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue)
6989	{
6990	pDevIns->CTX_SUFF(pHlp)->pfnIoApicSendMsi(pDevIns, GCPhys, uValue);
6991	}
6992
6993	#ifdef IN_RING3
6994
6995	/**
6996	* @copydoc PDMDEVHLPR3::pfnDriverAttach
6997	*/
6998	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
6999	{
7000	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7001	}
7002
7003	/**
7004	* @copydoc PDMDEVHLPR3::pfnDriverDetach
7005	*/
7006	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7007	{
7008	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7009	}
7010
7011	/**
7012	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
7013	*/
7014	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
7015	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
7016	{
7017	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
7018	}
7019
7020	/**
7021	* Reconfigures with a single driver reattachement, no config, noflags.
7022	* @sa PDMDevHlpDriverReconfigure
7023	*/
7024	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
7025	{
7026	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
7027	}
7028
7029	/**
7030	* Reconfigures with a two drivers reattachement, no config, noflags.
7031	* @sa PDMDevHlpDriverReconfigure
7032	*/
7033	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
7034	{
7035	char const * apszDrivers[2];
7036	apszDrivers[0] = pszDriver0;
7037	apszDrivers[1] = pszDriver1;
7038	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
7039	}
7040
7041	/**
7042	* @copydoc PDMDEVHLPR3::pfnQueueCreatePtr
7043	*/
7044	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7045	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PPDMQUEUE ppQueue)
7046	{
7047	return pDevIns->pHlpR3->pfnQueueCreatePtr(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
7048	}
7049
7050	/**
7051	* @copydoc PDMDEVHLPR3::pfnQueueCreate
7052	*/
7053	DECLINLINE(int) PDMDevHlpQueueCreateNew(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7054	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
7055	{
7056	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7057	}
7058
7059	#endif /* IN_RING3 */
7060
7061	/**
7062	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
7063	*/
7064	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7065	{
7066	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7067	}
7068
7069	/**
7070	* @copydoc PDMDEVHLPR3::pfnQueueInsert
7071	*/
7072	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7073	{
7074	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7075	}
7076
7077	/**
7078	* @copydoc PDMDEVHLPR3::pfnQueueInsertEx
7079	*/
7080	DECLINLINE(void) PDMDevHlpQueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay)
7081	{
7082	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsertEx(pDevIns, hQueue, pItem, cNanoMaxDelay);
7083	}
7084
7085	/**
7086	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7087	*/
7088	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7089	{
7090	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7091	}
7092
7093	#ifdef IN_RING3
7094	/**
7095	* @copydoc PDMDEVHLPR3::pfnTaskCreate
7096	*/
7097	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7098	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
7099	{
7100	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7101	}
7102	#endif
7103
7104	/**
7105	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
7106	*/
7107	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7108	{
7109	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7110	}
7111
7112	#ifdef IN_RING3
7113
7114	/**
7115	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7116	*/
7117	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7118	{
7119	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7120	}
7121
7122	/**
7123	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7124	*/
7125	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7126	{
7127	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7128	}
7129
7130	#endif /* IN_RING3 */
7131
7132	/**
7133	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7134	*/
7135	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7136	{
7137	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7138	}
7139
7140	/**
7141	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7142	*/
7143	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7144	{
7145	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7146	}
7147
7148	/**
7149	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7150	*/
7151	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7152	{
7153	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7154	}
7155
7156	/**
7157	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7158	*/
7159	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7160	{
7161	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7162	}
7163
7164	/**
7165	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7166	*/
7167	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7168	{
7169	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7170	}
7171
7172	#ifdef IN_RING3
7173
7174	/**
7175	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7176	*/
7177	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7178	{
7179	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7180	}
7181
7182	/**
7183	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7184	*/
7185	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7186	{
7187	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7188	}
7189
7190	#endif /* IN_RING3 */
7191
7192	/**
7193	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7194	*/
7195	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7196	{
7197	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7198	}
7199
7200	/**
7201	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7202	*/
7203	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7204	{
7205	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7206	}
7207
7208	/**
7209	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7210	*/
7211	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7212	{
7213	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7214	}
7215
7216	/**
7217	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7218	*/
7219	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7220	{
7221	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7222	}
7223
7224	/**
7225	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7226	*/
7227	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7228	{
7229	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7230	}
7231
7232	/**
7233	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7234	*/
7235	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7236	{
7237	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7238	}
7239
7240	#ifdef IN_RING3
7241
7242	/**
7243	* Initializes a PDM critical section.
7244	*
7245	* The PDM critical sections are derived from the IPRT critical sections, but
7246	* works in RC and R0 as well.
7247	*
7248	* @returns VBox status code.
7249	* @param pDevIns The device instance.
7250	* @param pCritSect Pointer to the critical section.
7251	* @param SRC_POS Use RT_SRC_POS.
7252	* @param pszNameFmt Format string for naming the critical section.
7253	* For statistics and lock validation.
7254	* @param ... Arguments for the format string.
7255	*/
7256	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7257	const char *pszNameFmt, ...)
7258	{
7259	int rc;
7260	va_list va;
7261	va_start(va, pszNameFmt);
7262	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7263	va_end(va);
7264	return rc;
7265	}
7266
7267	#endif /* IN_RING3 */
7268
7269	/**
7270	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7271	*/
7272	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7273	{
7274	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7275	}
7276
7277	#ifdef IN_RING3
7278
7279	/**
7280	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopR0
7281	*/
7282	DECLINLINE(R0PTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopR0(PPDMDEVINS pDevIns)
7283	{
7284	return pDevIns->pHlpR3->pfnCritSectGetNopR0(pDevIns);
7285	}
7286
7287	/**
7288	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopRC
7289	*/
7290	DECLINLINE(RCPTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopRC(PPDMDEVINS pDevIns)
7291	{
7292	return pDevIns->pHlpR3->pfnCritSectGetNopRC(pDevIns);
7293	}
7294
7295	#endif /* IN_RING3 */
7296
7297	/**
7298	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7299	*/
7300	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7301	{
7302	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7303	}
7304
7305	/**
7306	* @copydoc PDMCritSectEnter
7307	* @param pDevIns The device instance.
7308	*/
7309	DECLINLINE(int) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7310	{
7311	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7312	}
7313
7314	/**
7315	* @copydoc PDMCritSectEnterDebug
7316	* @param pDevIns The device instance.
7317	*/
7318	DECLINLINE(int) PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7319	{
7320	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7321	}
7322
7323	/**
7324	* @copydoc PDMCritSectTryEnter
7325	* @param pDevIns The device instance.
7326	*/
7327	DECLINLINE(int) PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7328	{
7329	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7330	}
7331
7332	/**
7333	* @copydoc PDMCritSectTryEnterDebug
7334	* @param pDevIns The device instance.
7335	*/
7336	DECLINLINE(int) PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7337	{
7338	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7339	}
7340
7341	/**
7342	* @copydoc PDMCritSectLeave
7343	* @param pDevIns The device instance.
7344	*/
7345	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7346	{
7347	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7348	}
7349
7350	/**
7351	* @copydoc PDMCritSectIsOwner
7352	* @param pDevIns The device instance.
7353	*/
7354	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7355	{
7356	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7357	}
7358
7359	/**
7360	* @copydoc PDMCritSectIsInitialized
7361	* @param pDevIns The device instance.
7362	*/
7363	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7364	{
7365	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
7366	}
7367
7368	/**
7369	* @copydoc PDMCritSectHasWaiters
7370	* @param pDevIns The device instance.
7371	*/
7372	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7373	{
7374	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
7375	}
7376
7377	/**
7378	* @copydoc PDMCritSectGetRecursion
7379	* @param pDevIns The device instance.
7380	*/
7381	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7382	{
7383	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
7384	}
7385
7386	#if defined(IN_RING3) \|\| defined(IN_RING0)
7387	/**
7388	* @copydoc PDMHCCritSectScheduleExitEvent
7389	* @param pDevIns The device instance.
7390	*/
7391	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
7392	{
7393	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
7394	}
7395	#endif
7396
7397	/* Strict build: Remap the two enter calls to the debug versions. */
7398	#ifdef VBOX_STRICT
7399	# ifdef IPRT_INCLUDED_asm_h
7400	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7401	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7402	# else
7403	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
7404	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
7405	# endif
7406	#endif
7407
7408	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
7409
7410	/**
7411	* @copydoc PDMR3CritSectDelete
7412	* @param pDevIns The device instance.
7413	*/
7414	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7415	{
7416	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
7417	}
7418
7419	/**
7420	* @copydoc PDMDEVHLPR3::pfnThreadCreate
7421	*/
7422	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
7423	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
7424	{
7425	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
7426	}
7427
7428	/**
7429	* @copydoc PDMR3ThreadDestroy
7430	* @param pDevIns The device instance.
7431	*/
7432	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
7433	{
7434	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
7435	}
7436
7437	/**
7438	* @copydoc PDMR3ThreadIAmSuspending
7439	* @param pDevIns The device instance.
7440	*/
7441	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7442	{
7443	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
7444	}
7445
7446	/**
7447	* @copydoc PDMR3ThreadIAmRunning
7448	* @param pDevIns The device instance.
7449	*/
7450	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7451	{
7452	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
7453	}
7454
7455	/**
7456	* @copydoc PDMR3ThreadSleep
7457	* @param pDevIns The device instance.
7458	*/
7459	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
7460	{
7461	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
7462	}
7463
7464	/**
7465	* @copydoc PDMR3ThreadSuspend
7466	* @param pDevIns The device instance.
7467	*/
7468	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7469	{
7470	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
7471	}
7472
7473	/**
7474	* @copydoc PDMR3ThreadResume
7475	* @param pDevIns The device instance.
7476	*/
7477	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7478	{
7479	return pDevIns->pHlpR3->pfnThreadResume(pThread);
7480	}
7481
7482	/**
7483	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
7484	*/
7485	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
7486	{
7487	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
7488	}
7489
7490	/**
7491	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
7492	*/
7493	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
7494	{
7495	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
7496	}
7497
7498	/**
7499	* @copydoc PDMDEVHLPR3::pfnA20Set
7500	*/
7501	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
7502	{
7503	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
7504	}
7505
7506	/**
7507	* @copydoc PDMDEVHLPR3::pfnRTCRegister
7508	*/
7509	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
7510	{
7511	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
7512	}
7513
7514	/**
7515	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
7516	*/
7517	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
7518	{
7519	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
7520	}
7521
7522	/**
7523	* @copydoc PDMDEVHLPR3::pfnIommuRegister
7524	*/
7525	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
7526	{
7527	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
7528	}
7529
7530	/**
7531	* @copydoc PDMDEVHLPR3::pfnPICRegister
7532	*/
7533	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
7534	{
7535	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
7536	}
7537
7538	/**
7539	* @copydoc PDMDEVHLPR3::pfnApicRegister
7540	*/
7541	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
7542	{
7543	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
7544	}
7545
7546	/**
7547	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
7548	*/
7549	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
7550	{
7551	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
7552	}
7553
7554	/**
7555	* @copydoc PDMDEVHLPR3::pfnHpetRegister
7556	*/
7557	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
7558	{
7559	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
7560	}
7561
7562	/**
7563	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
7564	*/
7565	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
7566	{
7567	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
7568	}
7569
7570	/**
7571	* @copydoc PDMDEVHLPR3::pfnDMACRegister
7572	*/
7573	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
7574	{
7575	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
7576	}
7577
7578	/**
7579	* @copydoc PDMDEVHLPR3::pfnDMARegister
7580	*/
7581	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
7582	{
7583	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
7584	}
7585
7586	/**
7587	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
7588	*/
7589	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
7590	{
7591	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
7592	}
7593
7594	/**
7595	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
7596	*/
7597	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
7598	{
7599	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
7600	}
7601
7602	/**
7603	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
7604	*/
7605	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
7606	{
7607	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
7608	}
7609
7610	/**
7611	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
7612	*/
7613	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
7614	{
7615	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
7616	}
7617
7618	/**
7619	* @copydoc PDMDEVHLPR3::pfnDMASchedule
7620	*/
7621	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
7622	{
7623	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
7624	}
7625
7626	/**
7627	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
7628	*/
7629	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
7630	{
7631	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
7632	}
7633
7634	/**
7635	* @copydoc PDMDEVHLPR3::pfnCMOSRead
7636	*/
7637	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
7638	{
7639	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
7640	}
7641
7642	/**
7643	* @copydoc PDMDEVHLPR3::pfnCallR0
7644	*/
7645	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
7646	{
7647	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
7648	}
7649
7650	/**
7651	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
7652	*/
7653	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
7654	{
7655	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
7656	}
7657
7658	/**
7659	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
7660	*/
7661	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
7662	{
7663	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
7664	}
7665
7666	/**
7667	* @copydoc PDMDEVHLPR3::pfnGetUVM
7668	*/
7669	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
7670	{
7671	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
7672	}
7673
7674	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
7675
7676	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
7677
7678	/**
7679	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
7680	*/
7681	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
7682	{
7683	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
7684	}
7685
7686	/**
7687	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
7688	*/
7689	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
7690	{
7691	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
7692	}
7693
7694	/**
7695	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
7696	*/
7697	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
7698	{
7699	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
7700	}
7701
7702	/**
7703	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
7704	*/
7705	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
7706	{
7707	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
7708	}
7709
7710	/**
7711	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
7712	*/
7713	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
7714	{
7715	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
7716	}
7717
7718	/**
7719	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
7720	*/
7721	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
7722	{
7723	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
7724	}
7725
7726	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
7727
7728	/**
7729	* @copydoc PDMDEVHLPR3::pfnGetVM
7730	*/
7731	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
7732	{
7733	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
7734	}
7735
7736	/**
7737	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
7738	*/
7739	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
7740	{
7741	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
7742	}
7743
7744	/**
7745	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
7746	*/
7747	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
7748	{
7749	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
7750	}
7751
7752	/**
7753	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
7754	*/
7755	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
7756	{
7757	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
7758	}
7759
7760	/**
7761	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
7762	*/
7763	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
7764	{
7765	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
7766	}
7767
7768	/**
7769	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
7770	*/
7771	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
7772	{
7773	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
7774	}
7775
7776	#ifdef IN_RING3
7777
7778	/**
7779	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
7780	*/
7781	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
7782	{
7783	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
7784	}
7785
7786	/**
7787	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
7788	*/
7789	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
7790	{
7791	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
7792	}
7793
7794	/**
7795	* @copydoc PDMDEVHLPR3::pfnVMReset
7796	*/
7797	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
7798	{
7799	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
7800	}
7801
7802	/**
7803	* @copydoc PDMDEVHLPR3::pfnVMSuspend
7804	*/
7805	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
7806	{
7807	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
7808	}
7809
7810	/**
7811	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
7812	*/
7813	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
7814	{
7815	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
7816	}
7817
7818	/**
7819	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
7820	*/
7821	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
7822	{
7823	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
7824	}
7825
7826	#endif /* IN_RING3 */
7827
7828	/**
7829	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
7830	*/
7831	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
7832	{
7833	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
7834	}
7835
7836	#ifdef IN_RING3
7837
7838	/**
7839	* @copydoc PDMDEVHLPR3::pfnGetCpuId
7840	*/
7841	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
7842	{
7843	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
7844	}
7845
7846	/**
7847	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
7848	*/
7849	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
7850	{
7851	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
7852	}
7853
7854	/**
7855	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
7856	*/
7857	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
7858	{
7859	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
7860	}
7861
7862	/**
7863	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
7864	*/
7865	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
7866	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
7867	const char pszHandlerR0, const char pszPfHandlerR0,
7868	const char pszHandlerRC, const char pszPfHandlerRC,
7869	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
7870	{
7871	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
7872	pszHandlerR0, pszPfHandlerR0,
7873	pszHandlerRC, pszPfHandlerRC,
7874	pszDesc, phType);
7875	}
7876
7877	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
7878	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
7879	do { \
7880	uint32_t u32GetEnumTmp = 0; \
7881	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
7882	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
7883	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
7884	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
7885	} while (0)
7886
7887	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
7888	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
7889	do { \
7890	uint8_t bGetEnumTmp = 0; \
7891	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
7892	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
7893	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
7894	} while (0)
7895
7896	#endif /* IN_RING3 */
7897
7898	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
7899	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
7900
7901	/**
7902	* Callbacks for VBoxDeviceRegister().
7903	*/
7904	typedef struct PDMDEVREGCB
7905	{
7906	/** Interface version.
7907	* This is set to PDM_DEVREG_CB_VERSION. */
7908	uint32_t u32Version;
7909
7910	/**
7911	* Registers a device with the current VM instance.
7912	*
7913	* @returns VBox status code.
7914	* @param pCallbacks Pointer to the callback table.
7915	* @param pReg Pointer to the device registration record.
7916	* This data must be permanent and readonly.
7917	*/
7918	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
7919	} PDMDEVREGCB;
7920
7921	/** Current version of the PDMDEVREGCB structure. */
7922	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
7923
7924
7925	/**
7926	* The VBoxDevicesRegister callback function.
7927	*
7928	* PDM will invoke this function after loading a device module and letting
7929	* the module decide which devices to register and how to handle conflicts.
7930	*
7931	* @returns VBox status code.
7932	* @param pCallbacks Pointer to the callback table.
7933	* @param u32Version VBox version number.
7934	*/
7935	typedef DECLCALLBACK(int) FNPDMVBOXDEVICESREGISTER(PPDMDEVREGCB pCallbacks, uint32_t u32Version);
7936
7937	/** @} */
7938
7939	RT_C_DECLS_END
7940
7941	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 84119

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