VirtualBox

source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 86620

Last change on this file since 86620 was 85713, checked in by vboxsync, 4 years ago

vmm/pdmdev.h: Correction to r138488 that updates the right structure versions. bugref:9654
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1/** @file
2 * PDM - Pluggable Device Manager, Devices.
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27#define VBOX_INCLUDED_vmm_pdmdev_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmqueue.h>
34#include <VBox/vmm/pdmtask.h>
35#ifdef IN_RING3
36# include <VBox/vmm/pdmthread.h>
37#endif
38#include <VBox/vmm/pdmifs.h>
39#include <VBox/vmm/pdmins.h>
40#include <VBox/vmm/pdmcommon.h>
41#include <VBox/vmm/pdmpcidev.h>
42#include <VBox/vmm/iom.h>
43#include <VBox/vmm/tm.h>
44#include <VBox/vmm/ssm.h>
45#include <VBox/vmm/cfgm.h>
46#include <VBox/vmm/cpum.h>
47#include <VBox/vmm/dbgf.h>
48#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
49#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
50#include <VBox/msi.h>
51#include <iprt/stdarg.h>
52#include <iprt/list.h>
53
54
55RT_C_DECLS_BEGIN
56
57/** @defgroup grp_pdm_device The PDM Devices API
58 * @ingroup grp_pdm
59 * @{
60 */
61
62/**
63 * Construct a device instance for a VM.
64 *
65 * @returns VBox status.
66 * @param pDevIns The device instance data. If the registration structure
67 * is needed, it can be accessed thru pDevIns->pReg.
68 * @param iInstance Instance number. Use this to figure out which registers
69 * and such to use. The instance number is also found in
70 * pDevIns->iInstance, but since it's likely to be
71 * frequently used PDM passes it as parameter.
72 * @param pCfg Configuration node handle for the driver. This is
73 * expected to be in high demand in the constructor and is
74 * therefore passed as an argument. When using it at other
75 * times, it can be found in pDevIns->pCfg.
76 */
77typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
78/** Pointer to a FNPDMDEVCONSTRUCT() function. */
79typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
80
81/**
82 * Destruct a device instance.
83 *
84 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
85 * resources can be freed correctly.
86 *
87 * @returns VBox status.
88 * @param pDevIns The device instance data.
89 *
90 * @remarks The device critical section is not entered. The routine may delete
91 * the critical section, so the caller cannot exit it.
92 */
93typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
94/** Pointer to a FNPDMDEVDESTRUCT() function. */
95typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
96
97/**
98 * Device relocation callback.
99 *
100 * This is called when the instance data has been relocated in raw-mode context
101 * (RC). It is also called when the RC hypervisor selects changes. The device
102 * must fixup all necessary pointers and re-query all interfaces to other RC
103 * devices and drivers.
104 *
105 * Before the RC code is executed the first time, this function will be called
106 * with a 0 delta so RC pointer calculations can be one in one place.
107 *
108 * @param pDevIns Pointer to the device instance.
109 * @param offDelta The relocation delta relative to the old location.
110 *
111 * @remarks A relocation CANNOT fail.
112 *
113 * @remarks The device critical section is not entered. The relocations should
114 * not normally require any locking.
115 */
116typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
117/** Pointer to a FNPDMDEVRELOCATE() function. */
118typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
119
120/**
121 * Power On notification.
122 *
123 * @returns VBox status.
124 * @param pDevIns The device instance data.
125 *
126 * @remarks Caller enters the device critical section.
127 */
128typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
129/** Pointer to a FNPDMDEVPOWERON() function. */
130typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
131
132/**
133 * Reset notification.
134 *
135 * @returns VBox status.
136 * @param pDevIns The device instance data.
137 *
138 * @remarks Caller enters the device critical section.
139 */
140typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
141/** Pointer to a FNPDMDEVRESET() function. */
142typedef FNPDMDEVRESET *PFNPDMDEVRESET;
143
144/**
145 * Soft reset notification.
146 *
147 * This is mainly for emulating the 286 style protected mode exits, in which
148 * most devices should remain in their current state.
149 *
150 * @returns VBox status.
151 * @param pDevIns The device instance data.
152 * @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
153 *
154 * @remarks Caller enters the device critical section.
155 */
156typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
157/** Pointer to a FNPDMDEVSOFTRESET() function. */
158typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
159
160/** @name PDMVMRESET_F_XXX - VM reset flags.
161 * These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
162 * reset via PDMDevHlpVMReset.
163 * @{ */
164/** Unknown reason. */
165#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
166/** GIM triggered reset. */
167#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
168/** The last source always causing hard resets. */
169#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
170/** ACPI triggered reset. */
171#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
172/** PS/2 system port A (92h) reset. */
173#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
174/** Keyboard reset. */
175#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
176/** Tripple fault. */
177#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
178/** Reset source mask. */
179#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
180/** @} */
181
182/**
183 * Suspend notification.
184 *
185 * @returns VBox status.
186 * @param pDevIns The device instance data.
187 * @thread EMT(0)
188 *
189 * @remarks Caller enters the device critical section.
190 */
191typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
192/** Pointer to a FNPDMDEVSUSPEND() function. */
193typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
194
195/**
196 * Resume notification.
197 *
198 * @returns VBox status.
199 * @param pDevIns The device instance data.
200 *
201 * @remarks Caller enters the device critical section.
202 */
203typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
204/** Pointer to a FNPDMDEVRESUME() function. */
205typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
206
207/**
208 * Power Off notification.
209 *
210 * This is always called when VMR3PowerOff is called.
211 * There will be no callback when hot plugging devices.
212 *
213 * @param pDevIns The device instance data.
214 * @thread EMT(0)
215 *
216 * @remarks Caller enters the device critical section.
217 */
218typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
219/** Pointer to a FNPDMDEVPOWEROFF() function. */
220typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
221
222/**
223 * Attach command.
224 *
225 * This is called to let the device attach to a driver for a specified LUN
226 * at runtime. This is not called during VM construction, the device
227 * constructor has to attach to all the available drivers.
228 *
229 * This is like plugging in the keyboard or mouse after turning on the PC.
230 *
231 * @returns VBox status code.
232 * @param pDevIns The device instance.
233 * @param iLUN The logical unit which is being attached.
234 * @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
235 *
236 * @remarks Caller enters the device critical section.
237 */
238typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
239/** Pointer to a FNPDMDEVATTACH() function. */
240typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
241
242/**
243 * Detach notification.
244 *
245 * This is called when a driver is detaching itself from a LUN of the device.
246 * The device should adjust its state to reflect this.
247 *
248 * This is like unplugging the network cable to use it for the laptop or
249 * something while the PC is still running.
250 *
251 * @param pDevIns The device instance.
252 * @param iLUN The logical unit which is being detached.
253 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
254 *
255 * @remarks Caller enters the device critical section.
256 */
257typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
258/** Pointer to a FNPDMDEVDETACH() function. */
259typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
260
261/**
262 * Query the base interface of a logical unit.
263 *
264 * @returns VBOX status code.
265 * @param pDevIns The device instance.
266 * @param iLUN The logicial unit to query.
267 * @param ppBase Where to store the pointer to the base interface of the LUN.
268 *
269 * @remarks The device critical section is not entered.
270 */
271typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
272/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
273typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
274
275/**
276 * Init complete notification (after ring-0 & RC init since 5.1).
277 *
278 * This can be done to do communication with other devices and other
279 * initialization which requires everything to be in place.
280 *
281 * @returns VBOX status code.
282 * @param pDevIns The device instance.
283 *
284 * @remarks Caller enters the device critical section.
285 */
286typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
287/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
288typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
289
290
291/**
292 * The context of a pfnMemSetup call.
293 */
294typedef enum PDMDEVMEMSETUPCTX
295{
296 /** Invalid zero value. */
297 PDMDEVMEMSETUPCTX_INVALID = 0,
298 /** After construction. */
299 PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
300 /** After reset. */
301 PDMDEVMEMSETUPCTX_AFTER_RESET,
302 /** Type size hack. */
303 PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
304} PDMDEVMEMSETUPCTX;
305
306
307/**
308 * PDM Device Registration Structure.
309 *
310 * This structure is used when registering a device from VBoxInitDevices() in HC
311 * Ring-3. PDM will continue use till the VM is terminated.
312 *
313 * @note The first part is the same in every context.
314 */
315typedef struct PDMDEVREGR3
316{
317 /** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
318 uint32_t u32Version;
319 /** Reserved, must be zero. */
320 uint32_t uReserved0;
321 /** Device name, must match the ring-3 one. */
322 char szName[32];
323 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
324 uint32_t fFlags;
325 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
326 uint32_t fClass;
327 /** Maximum number of instances (per VM). */
328 uint32_t cMaxInstances;
329 /** The shared data structure version number. */
330 uint32_t uSharedVersion;
331 /** Size of the instance data. */
332 uint32_t cbInstanceShared;
333 /** Size of the ring-0 instance data. */
334 uint32_t cbInstanceCC;
335 /** Size of the raw-mode instance data. */
336 uint32_t cbInstanceRC;
337 /** Max number of PCI devices. */
338 uint16_t cMaxPciDevices;
339 /** Max number of MSI-X vectors in any of the PCI devices. */
340 uint16_t cMaxMsixVectors;
341 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
342 * remain unchanged from registration till VM destruction. */
343 const char *pszDescription;
344
345 /** Name of the raw-mode context module (no path).
346 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
347 const char *pszRCMod;
348 /** Name of the ring-0 module (no path).
349 * Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
350 const char *pszR0Mod;
351
352 /** Construct instance - required. */
353 PFNPDMDEVCONSTRUCT pfnConstruct;
354 /** Destruct instance - optional.
355 * Critical section NOT entered (will be destroyed). */
356 PFNPDMDEVDESTRUCT pfnDestruct;
357 /** Relocation command - optional.
358 * Critical section NOT entered. */
359 PFNPDMDEVRELOCATE pfnRelocate;
360 /**
361 * Memory setup callback.
362 *
363 * @param pDevIns The device instance data.
364 * @param enmCtx Indicates the context of the call.
365 * @remarks The critical section is entered prior to calling this method.
366 */
367 DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
368 /** Power on notification - optional.
369 * Critical section is entered. */
370 PFNPDMDEVPOWERON pfnPowerOn;
371 /** Reset notification - optional.
372 * Critical section is entered. */
373 PFNPDMDEVRESET pfnReset;
374 /** Suspend notification - optional.
375 * Critical section is entered. */
376 PFNPDMDEVSUSPEND pfnSuspend;
377 /** Resume notification - optional.
378 * Critical section is entered. */
379 PFNPDMDEVRESUME pfnResume;
380 /** Attach command - optional.
381 * Critical section is entered. */
382 PFNPDMDEVATTACH pfnAttach;
383 /** Detach notification - optional.
384 * Critical section is entered. */
385 PFNPDMDEVDETACH pfnDetach;
386 /** Query a LUN base interface - optional.
387 * Critical section is NOT entered. */
388 PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
389 /** Init complete notification - optional.
390 * Critical section is entered. */
391 PFNPDMDEVINITCOMPLETE pfnInitComplete;
392 /** Power off notification - optional.
393 * Critical section is entered. */
394 PFNPDMDEVPOWEROFF pfnPowerOff;
395 /** Software system reset notification - optional.
396 * Critical section is entered. */
397 PFNPDMDEVSOFTRESET pfnSoftReset;
398
399 /** @name Reserved for future extensions, must be zero.
400 * @{ */
401 DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
402 DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
403 DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
404 DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
405 DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
406 DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
407 DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
408 DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
409 /** @} */
410
411 /** Initialization safty marker. */
412 uint32_t u32VersionEnd;
413} PDMDEVREGR3;
414/** Pointer to a PDM Device Structure. */
415typedef PDMDEVREGR3 *PPDMDEVREGR3;
416/** Const pointer to a PDM Device Structure. */
417typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
418/** Current DEVREGR3 version number. */
419#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
420
421
422/** PDM Device Flags.
423 * @{ */
424/** This flag is used to indicate that the device has a R0 component. */
425#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
426/** Requires the ring-0 component, ignore configuration values. */
427#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
428/** Requires the ring-0 component, ignore configuration values. */
429#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
430
431/** This flag is used to indicate that the device has a RC component. */
432#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
433/** Requires the raw-mode component, ignore configuration values. */
434#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
435/** Requires the raw-mode component, ignore configuration values. */
436#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
437
438/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
439#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_RC)
440
441/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
442 * The bit count for the current host.
443 * @note Superfluous, but still around for hysterical raisins. */
444#if HC_ARCH_BITS == 32
445# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
446#elif HC_ARCH_BITS == 64
447# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
448#else
449# error Unsupported HC_ARCH_BITS value.
450#endif
451/** The host bit count mask. */
452#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
453
454/** The device support only 32-bit guests. */
455#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
456/** The device support only 64-bit guests. */
457#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
458/** The device support both 32-bit & 64-bit guests. */
459#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
460/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
461 * The guest bit count for the current compilation. */
462#if GC_ARCH_BITS == 32
463# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
464#elif GC_ARCH_BITS == 64
465# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
466#else
467# error Unsupported GC_ARCH_BITS value.
468#endif
469/** The guest bit count mask. */
470#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
471
472/** A convenience. */
473#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
474
475/** Indicates that the device needs to be notified before the drivers when suspending. */
476#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
477/** Indicates that the device needs to be notified before the drivers when powering off. */
478#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
479/** Indicates that the device needs to be notified before the drivers when resetting. */
480#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
481
482/** This flag is used to indicate that the device has been converted to the
483 * new device style. */
484#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
485
486/** @} */
487
488
489/** PDM Device Classes.
490 * The order is important, lower bit earlier instantiation.
491 * @{ */
492/** Architecture device. */
493#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
494/** Architecture BIOS device. */
495#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
496/** PCI bus brigde. */
497#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
498/** PCI built-in device (e.g. PCI root complex devices). */
499#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
500/** Input device (mouse, keyboard, joystick, HID, ...). */
501#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
502/** Interrupt controller (PIC). */
503#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
504/** Interval controoler (PIT). */
505#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
506/** RTC/CMOS. */
507#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
508/** DMA controller. */
509#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
510/** VMM Device. */
511#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
512/** Graphics device, like VGA. */
513#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
514/** Storage controller device. */
515#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
516/** Network interface controller. */
517#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
518/** Audio. */
519#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
520/** USB HIC. */
521#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
522/** ACPI. */
523#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
524/** Serial controller device. */
525#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
526/** Parallel controller device */
527#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
528/** Host PCI pass-through device */
529#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
530/** Misc devices (always last). */
531#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
532/** @} */
533
534
535/**
536 * PDM Device Registration Structure, ring-0.
537 *
538 * This structure is used when registering a device from VBoxInitDevices() in HC
539 * Ring-0. PDM will continue use till the VM is terminated.
540 */
541typedef struct PDMDEVREGR0
542{
543 /** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
544 uint32_t u32Version;
545 /** Reserved, must be zero. */
546 uint32_t uReserved0;
547 /** Device name, must match the ring-3 one. */
548 char szName[32];
549 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
550 uint32_t fFlags;
551 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
552 uint32_t fClass;
553 /** Maximum number of instances (per VM). */
554 uint32_t cMaxInstances;
555 /** The shared data structure version number. */
556 uint32_t uSharedVersion;
557 /** Size of the instance data. */
558 uint32_t cbInstanceShared;
559 /** Size of the ring-0 instance data. */
560 uint32_t cbInstanceCC;
561 /** Size of the raw-mode instance data. */
562 uint32_t cbInstanceRC;
563 /** Max number of PCI devices. */
564 uint16_t cMaxPciDevices;
565 /** Max number of MSI-X vectors in any of the PCI devices. */
566 uint16_t cMaxMsixVectors;
567 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
568 * remain unchanged from registration till VM destruction. */
569 const char *pszDescription;
570
571 /**
572 * Early construction callback (optional).
573 *
574 * This is called right after the device instance structure has been allocated
575 * and before the ring-3 constructor gets called.
576 *
577 * @returns VBox status code.
578 * @param pDevIns The device instance data.
579 * @note The destructure is always called, regardless of the return status.
580 */
581 DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
582
583 /**
584 * Regular construction callback (optional).
585 *
586 * This is called after (or during) the ring-3 constructor.
587 *
588 * @returns VBox status code.
589 * @param pDevIns The device instance data.
590 * @note The destructure is always called, regardless of the return status.
591 */
592 DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
593
594 /**
595 * Destructor (optional).
596 *
597 * This is called after the ring-3 destruction. This is not called if ring-3
598 * fails to trigger it (e.g. process is killed or crashes).
599 *
600 * @param pDevIns The device instance data.
601 */
602 DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
603
604 /**
605 * Final destructor (optional).
606 *
607 * This is called right before the memory is freed, which happens when the
608 * VM/GVM object is destroyed. This is always called.
609 *
610 * @param pDevIns The device instance data.
611 */
612 DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
613
614 /**
615 * Generic request handler (optional).
616 *
617 * @param pDevIns The device instance data.
618 * @param uReq Device specific request.
619 * @param uArg Request argument.
620 */
621 DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
622
623 /** @name Reserved for future extensions, must be zero.
624 * @{ */
625 DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
626 DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
627 DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
628 DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
629 DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
630 DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
631 DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
632 DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
633 /** @} */
634
635 /** Initialization safty marker. */
636 uint32_t u32VersionEnd;
637} PDMDEVREGR0;
638/** Pointer to a ring-0 PDM device registration structure. */
639typedef PDMDEVREGR0 *PPDMDEVREGR0;
640/** Pointer to a const ring-0 PDM device registration structure. */
641typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
642/** Current DEVREGR0 version number. */
643#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
644
645
646/**
647 * PDM Device Registration Structure, raw-mode
648 *
649 * At the moment, this structure is mostly here to match the other two contexts.
650 */
651typedef struct PDMDEVREGRC
652{
653 /** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
654 uint32_t u32Version;
655 /** Reserved, must be zero. */
656 uint32_t uReserved0;
657 /** Device name, must match the ring-3 one. */
658 char szName[32];
659 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
660 uint32_t fFlags;
661 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
662 uint32_t fClass;
663 /** Maximum number of instances (per VM). */
664 uint32_t cMaxInstances;
665 /** The shared data structure version number. */
666 uint32_t uSharedVersion;
667 /** Size of the instance data. */
668 uint32_t cbInstanceShared;
669 /** Size of the ring-0 instance data. */
670 uint32_t cbInstanceCC;
671 /** Size of the raw-mode instance data. */
672 uint32_t cbInstanceRC;
673 /** Max number of PCI devices. */
674 uint16_t cMaxPciDevices;
675 /** Max number of MSI-X vectors in any of the PCI devices. */
676 uint16_t cMaxMsixVectors;
677 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
678 * remain unchanged from registration till VM destruction. */
679 const char *pszDescription;
680
681 /**
682 * Constructor callback.
683 *
684 * This is called much later than both the ring-0 and ring-3 constructors, since
685 * raw-mode v2 require a working VMM to run actual code.
686 *
687 * @returns VBox status code.
688 * @param pDevIns The device instance data.
689 * @note The destructure is always called, regardless of the return status.
690 */
691 DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
692
693 /** @name Reserved for future extensions, must be zero.
694 * @{ */
695 DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
696 DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
697 DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
698 DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
699 DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
700 DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
701 DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
702 DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
703 /** @} */
704
705 /** Initialization safty marker. */
706 uint32_t u32VersionEnd;
707} PDMDEVREGRC;
708/** Pointer to a raw-mode PDM device registration structure. */
709typedef PDMDEVREGRC *PPDMDEVREGRC;
710/** Pointer to a const raw-mode PDM device registration structure. */
711typedef PDMDEVREGRC const *PCPDMDEVREGRC;
712/** Current DEVREGRC version number. */
713#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
714
715
716
717/** @def PDM_DEVREG_VERSION
718 * Current DEVREG version number. */
719/** @typedef PDMDEVREGR3
720 * A current context PDM device registration structure. */
721/** @typedef PPDMDEVREGR3
722 * Pointer to a current context PDM device registration structure. */
723/** @typedef PCPDMDEVREGR3
724 * Pointer to a const current context PDM device registration structure. */
725#if defined(IN_RING3) || defined(DOXYGEN_RUNNING)
726# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
727typedef PDMDEVREGR3 PDMDEVREG;
728typedef PPDMDEVREGR3 PPDMDEVREG;
729typedef PCPDMDEVREGR3 PCPDMDEVREG;
730#elif defined(IN_RING0)
731# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
732typedef PDMDEVREGR0 PDMDEVREG;
733typedef PPDMDEVREGR0 PPDMDEVREG;
734typedef PCPDMDEVREGR0 PCPDMDEVREG;
735#elif defined(IN_RC)
736# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
737typedef PDMDEVREGRC PDMDEVREG;
738typedef PPDMDEVREGRC PPDMDEVREG;
739typedef PCPDMDEVREGRC PCPDMDEVREG;
740#else
741# error "Not IN_RING3, IN_RING0 or IN_RC"
742#endif
743
744
745/**
746 * Device registrations for ring-0 modules.
747 *
748 * This structure is used directly and must therefore reside in persistent
749 * memory (i.e. the data section).
750 */
751typedef struct PDMDEVMODREGR0
752{
753 /** The structure version (PDM_DEVMODREGR0_VERSION). */
754 uint32_t u32Version;
755 /** Number of devices in the array papDevRegs points to. */
756 uint32_t cDevRegs;
757 /** Pointer to device registration structures. */
758 PCPDMDEVREGR0 *papDevRegs;
759 /** The ring-0 module handle - PDM internal, fingers off. */
760 void *hMod;
761 /** List entry - PDM internal, fingers off. */
762 RTLISTNODE ListEntry;
763} PDMDEVMODREGR0;
764/** Pointer to device registriations for a ring-0 module. */
765typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
766/** Current PDMDEVMODREGR0 version number. */
767#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
768
769
770/** @name IRQ Level for use with the *SetIrq APIs.
771 * @{
772 */
773/** Assert the IRQ (can assume value 1). */
774#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
775/** Deassert the IRQ (can assume value 0). */
776#define PDM_IRQ_LEVEL_LOW 0
777/** flip-flop - deassert and then assert the IRQ again immediately. */
778#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) | PDM_IRQ_LEVEL_HIGH)
779/** @} */
780
781/**
782 * Registration record for MSI/MSI-X emulation.
783 */
784typedef struct PDMMSIREG
785{
786 /** Number of MSI interrupt vectors, 0 if MSI not supported */
787 uint16_t cMsiVectors;
788 /** Offset of MSI capability */
789 uint8_t iMsiCapOffset;
790 /** Offset of next capability to MSI */
791 uint8_t iMsiNextOffset;
792 /** If we support 64-bit MSI addressing */
793 bool fMsi64bit;
794 /** If we do not support per-vector masking */
795 bool fMsiNoMasking;
796
797 /** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
798 uint16_t cMsixVectors;
799 /** Offset of MSI-X capability */
800 uint8_t iMsixCapOffset;
801 /** Offset of next capability to MSI-X */
802 uint8_t iMsixNextOffset;
803 /** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
804 uint8_t iMsixBar;
805} PDMMSIREG;
806typedef PDMMSIREG *PPDMMSIREG;
807
808/**
809 * PCI Bus registration structure.
810 * All the callbacks, except the PCIBIOS hack, are working on PCI devices.
811 */
812typedef struct PDMPCIBUSREGR3
813{
814 /** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
815 uint32_t u32Version;
816
817 /**
818 * Registers the device with the default PCI bus.
819 *
820 * @returns VBox status code.
821 * @param pDevIns Device instance of the PCI Bus.
822 * @param pPciDev The PCI device structure.
823 * @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
824 * @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
825 * device number (0-31).
826 * @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
827 * function number (0-7).
828 * @param pszName Device name (static but not unique).
829 *
830 * @remarks Caller enters the PDM critical section.
831 */
832 DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
833 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
834
835 /**
836 * Initialize MSI or MSI-X emulation support in a PCI device.
837 *
838 * This cannot handle all corner cases of the MSI/MSI-X spec, but for the
839 * vast majority of device emulation it covers everything necessary. It's
840 * fully automatic, taking care of all BAR and config space requirements,
841 * and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
842 * When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
843 * the vector number (otherwise it has the usual INTA-D meaning for PCI).
844 *
845 * A device not using this can still offer MSI/MSI-X. In this case it's
846 * completely up to the device (in the MSI-X case) to create/register the
847 * necessary MMIO BAR, handle all config space/BAR updating and take care
848 * of delivering the interrupts appropriately.
849 *
850 * @returns VBox status code.
851 * @param pDevIns Device instance of the PCI Bus.
852 * @param pPciDev The PCI device structure.
853 * @param pMsiReg MSI emulation registration structure
854 * @remarks Caller enters the PDM critical section.
855 */
856 DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
857
858 /**
859 * Registers a I/O region (memory mapped or I/O ports) for a PCI device.
860 *
861 * @returns VBox status code.
862 * @param pDevIns Device instance of the PCI Bus.
863 * @param pPciDev The PCI device structure.
864 * @param iRegion The region number.
865 * @param cbRegion Size of the region.
866 * @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
867 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
868 * PCI_ADDRESS_SPACE_BAR64 or'ed in.
869 * @param fFlags PDMPCIDEV_IORGN_F_XXX.
870 * @param hHandle An I/O port, MMIO or MMIO2 handle according to
871 * @a fFlags, UINT64_MAX if no handle is passed
872 * (old style).
873 * @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
874 * is given.
875 * @remarks Caller enters the PDM critical section.
876 */
877 DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
878 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
879 uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
880
881 /**
882 * Register PCI configuration space read/write intercept callbacks.
883 *
884 * @param pDevIns Device instance of the PCI Bus.
885 * @param pPciDev The PCI device structure.
886 * @param pfnRead Pointer to the user defined PCI config read function.
887 * @param pfnWrite Pointer to the user defined PCI config write function.
888 * to call default PCI config write function. Can be NULL.
889 * @remarks Caller enters the PDM critical section.
890 * @thread EMT
891 */
892 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
893 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
894
895 /**
896 * Perform a PCI configuration space write, bypassing interception.
897 *
898 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
899 *
900 * @returns Strict VBox status code (mainly DBGFSTOP).
901 * @param pDevIns Device instance of the PCI Bus.
902 * @param pPciDev The PCI device which config space is being read.
903 * @param uAddress The config space address.
904 * @param cb The size of the read: 1, 2 or 4 bytes.
905 * @param u32Value The value to write.
906 * @note The caller (PDM) does not enter the PDM critsect, but it is possible
907 * that the (root) bus will have done that already.
908 */
909 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
910 uint32_t uAddress, unsigned cb, uint32_t u32Value));
911
912 /**
913 * Perform a PCI configuration space read, bypassing interception.
914 *
915 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
916 *
917 * @returns Strict VBox status code (mainly DBGFSTOP).
918 * @param pDevIns Device instance of the PCI Bus.
919 * @param pPciDev The PCI device which config space is being read.
920 * @param uAddress The config space address.
921 * @param cb The size of the read: 1, 2 or 4 bytes.
922 * @param pu32Value Where to return the value.
923 * @note The caller (PDM) does not enter the PDM critsect, but it is possible
924 * that the (root) bus will have done that already.
925 */
926 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
927 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
928
929 /**
930 * Set the IRQ for a PCI device.
931 *
932 * @param pDevIns Device instance of the PCI Bus.
933 * @param pPciDev The PCI device structure.
934 * @param iIrq IRQ number to set.
935 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
936 * @param uTagSrc The IRQ tag and source (for tracing).
937 * @remarks Caller enters the PDM critical section.
938 */
939 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
940
941 /** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
942 uint32_t u32EndVersion;
943} PDMPCIBUSREGR3;
944/** Pointer to a PCI bus registration structure. */
945typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
946/** Current PDMPCIBUSREGR3 version number. */
947#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
948
949/**
950 * PCI Bus registration structure for ring-0.
951 */
952typedef struct PDMPCIBUSREGR0
953{
954 /** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
955 uint32_t u32Version;
956 /** The PCI bus number (from ring-3 registration). */
957 uint32_t iBus;
958 /**
959 * Set the IRQ for a PCI device.
960 *
961 * @param pDevIns Device instance of the PCI Bus.
962 * @param pPciDev The PCI device structure.
963 * @param iIrq IRQ number to set.
964 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
965 * @param uTagSrc The IRQ tag and source (for tracing).
966 * @remarks Caller enters the PDM critical section.
967 */
968 DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
969 /** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
970 uint32_t u32EndVersion;
971} PDMPCIBUSREGR0;
972/** Pointer to a PCI bus ring-0 registration structure. */
973typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
974/** Current PDMPCIBUSREGR0 version number. */
975#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
976
977/**
978 * PCI Bus registration structure for raw-mode.
979 */
980typedef struct PDMPCIBUSREGRC
981{
982 /** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
983 uint32_t u32Version;
984 /** The PCI bus number (from ring-3 registration). */
985 uint32_t iBus;
986 /**
987 * Set the IRQ for a PCI device.
988 *
989 * @param pDevIns Device instance of the PCI Bus.
990 * @param pPciDev The PCI device structure.
991 * @param iIrq IRQ number to set.
992 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
993 * @param uTagSrc The IRQ tag and source (for tracing).
994 * @remarks Caller enters the PDM critical section.
995 */
996 DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
997 /** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
998 uint32_t u32EndVersion;
999} PDMPCIBUSREGRC;
1000/** Pointer to a PCI bus raw-mode registration structure. */
1001typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1002/** Current PDMPCIBUSREGRC version number. */
1003#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1004
1005/** PCI bus registration structure for the current context. */
1006typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1007/** Pointer to a PCI bus registration structure for the current context. */
1008typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1009/** PCI bus registration structure version for the current context. */
1010#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1011
1012
1013/**
1014 * PCI Bus RC helpers.
1015 */
1016typedef struct PDMPCIHLPRC
1017{
1018 /** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1019 uint32_t u32Version;
1020
1021 /**
1022 * Set an ISA IRQ.
1023 *
1024 * @param pDevIns PCI device instance.
1025 * @param iIrq IRQ number to set.
1026 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1027 * @param uTagSrc The IRQ tag and source (for tracing).
1028 * @thread EMT only.
1029 */
1030 DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1031
1032 /**
1033 * Set an I/O-APIC IRQ.
1034 *
1035 * @param pDevIns PCI device instance.
1036 * @param uBusDevFn The bus:device:function of the device initiating the
1037 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1038 * interrupt.
1039 * @param iIrq IRQ number to set.
1040 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1041 * @param uTagSrc The IRQ tag and source (for tracing).
1042 * @thread EMT only.
1043 */
1044 DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1045
1046 /**
1047 * Send an MSI.
1048 *
1049 * @param pDevIns PCI device instance.
1050 * @param uBusDevFn The bus:device:function of the device initiating the
1051 * MSI. Cannot be NIL_PCIBDF.
1052 * @param pMsi The MSI to send.
1053 * @param uTagSrc The IRQ tag and source (for tracing).
1054 * @thread EMT only.
1055 */
1056 DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1057
1058
1059 /**
1060 * Acquires the PDM lock.
1061 *
1062 * @returns VINF_SUCCESS on success.
1063 * @returns rc if we failed to acquire the lock.
1064 * @param pDevIns The PCI device instance.
1065 * @param rc What to return if we fail to acquire the lock.
1066 */
1067 DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1068
1069 /**
1070 * Releases the PDM lock.
1071 *
1072 * @param pDevIns The PCI device instance.
1073 */
1074 DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1075
1076 /**
1077 * Gets a bus by it's PDM ordinal (typically the parent bus).
1078 *
1079 * @returns Pointer to the device instance of the bus.
1080 * @param pDevIns The PCI bus device instance.
1081 * @param idxPdmBus The PDM ordinal value of the bus to get.
1082 */
1083 DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1084
1085 /** Just a safety precaution. */
1086 uint32_t u32TheEnd;
1087} PDMPCIHLPRC;
1088/** Pointer to PCI helpers. */
1089typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1090/** Pointer to const PCI helpers. */
1091typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1092
1093/** Current PDMPCIHLPRC version number. */
1094#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1095
1096
1097/**
1098 * PCI Bus R0 helpers.
1099 */
1100typedef struct PDMPCIHLPR0
1101{
1102 /** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1103 uint32_t u32Version;
1104
1105 /**
1106 * Set an ISA IRQ.
1107 *
1108 * @param pDevIns PCI device instance.
1109 * @param iIrq IRQ number to set.
1110 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1111 * @param uTagSrc The IRQ tag and source (for tracing).
1112 * @thread EMT only.
1113 */
1114 DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1115
1116 /**
1117 * Set an I/O-APIC IRQ.
1118 *
1119 * @param pDevIns PCI device instance.
1120 * @param uBusDevFn The bus:device:function of the device initiating the
1121 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1122 * interrupt.
1123 * @param iIrq IRQ number to set.
1124 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1125 * @param uTagSrc The IRQ tag and source (for tracing).
1126 * @thread EMT only.
1127 */
1128 DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1129
1130 /**
1131 * Send an MSI.
1132 *
1133 * @param pDevIns PCI device instance.
1134 * @param uBusDevFn The bus:device:function of the device initiating the
1135 * MSI. Cannot be NIL_PCIBDF.
1136 * @param pMsi The MSI to send.
1137 * @param uTagSrc The IRQ tag and source (for tracing).
1138 * @thread EMT only.
1139 */
1140 DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1141
1142 /**
1143 * Acquires the PDM lock.
1144 *
1145 * @returns VINF_SUCCESS on success.
1146 * @returns rc if we failed to acquire the lock.
1147 * @param pDevIns The PCI device instance.
1148 * @param rc What to return if we fail to acquire the lock.
1149 */
1150 DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1151
1152 /**
1153 * Releases the PDM lock.
1154 *
1155 * @param pDevIns The PCI device instance.
1156 */
1157 DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1158
1159 /**
1160 * Gets a bus by it's PDM ordinal (typically the parent bus).
1161 *
1162 * @returns Pointer to the device instance of the bus.
1163 * @param pDevIns The PCI bus device instance.
1164 * @param idxPdmBus The PDM ordinal value of the bus to get.
1165 */
1166 DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1167
1168 /** Just a safety precaution. */
1169 uint32_t u32TheEnd;
1170} PDMPCIHLPR0;
1171/** Pointer to PCI helpers. */
1172typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1173/** Pointer to const PCI helpers. */
1174typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1175
1176/** Current PDMPCIHLPR0 version number. */
1177#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1178
1179/**
1180 * PCI device helpers.
1181 */
1182typedef struct PDMPCIHLPR3
1183{
1184 /** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1185 uint32_t u32Version;
1186
1187 /**
1188 * Set an ISA IRQ.
1189 *
1190 * @param pDevIns The PCI device instance.
1191 * @param iIrq IRQ number to set.
1192 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1193 * @param uTagSrc The IRQ tag and source (for tracing).
1194 */
1195 DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1196
1197 /**
1198 * Set an I/O-APIC IRQ.
1199 *
1200 * @param pDevIns The PCI device instance.
1201 * @param uBusDevFn The bus:device:function of the device initiating the
1202 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1203 * interrupt.
1204 * @param iIrq IRQ number to set.
1205 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1206 * @param uTagSrc The IRQ tag and source (for tracing).
1207 */
1208 DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1209
1210 /**
1211 * Send an MSI.
1212 *
1213 * @param pDevIns PCI device instance.
1214 * @param uBusDevFn The bus:device:function of the device initiating the
1215 * MSI. Cannot be NIL_PCIBDF.
1216 * @param pMsi The MSI to send.
1217 * @param uTagSrc The IRQ tag and source (for tracing).
1218 */
1219 DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1220
1221 /**
1222 * Acquires the PDM lock.
1223 *
1224 * @returns VINF_SUCCESS on success.
1225 * @returns Fatal error on failure.
1226 * @param pDevIns The PCI device instance.
1227 * @param rc Dummy for making the interface identical to the RC and R0 versions.
1228 */
1229 DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1230
1231 /**
1232 * Releases the PDM lock.
1233 *
1234 * @param pDevIns The PCI device instance.
1235 */
1236 DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1237
1238 /**
1239 * Gets a bus by it's PDM ordinal (typically the parent bus).
1240 *
1241 * @returns Pointer to the device instance of the bus.
1242 * @param pDevIns The PCI bus device instance.
1243 * @param idxPdmBus The PDM ordinal value of the bus to get.
1244 */
1245 DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1246
1247 /** Just a safety precaution. */
1248 uint32_t u32TheEnd;
1249} PDMPCIHLPR3;
1250/** Pointer to PCI helpers. */
1251typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1252/** Pointer to const PCI helpers. */
1253typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1254
1255/** Current PDMPCIHLPR3 version number. */
1256#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1257
1258
1259/**
1260 * IOMMU registration structure for ring-0.
1261 */
1262typedef struct PDMIOMMUREGR0
1263{
1264 /** Structure version number. PDM_IOMMUREG_VERSION defines the current
1265 * version. */
1266 uint32_t u32Version;
1267 /** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1268 uint32_t idxIommu;
1269
1270 /**
1271 * Performs a physical memory read transaction through the IOMMU.
1272 *
1273 * @returns VBox status code.
1274 * @param pDevIns The IOMMU device instance.
1275 * @param uDevId The device identifier (bus, device, function).
1276 * @param uIova The I/O virtual address being read.
1277 * @param cbRead The number of bytes being read.
1278 * @param pGCPhysSpa Where to store the translated system physical address.
1279 *
1280 * @thread Any.
1281 */
1282 DECLR0CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead,
1283 PRTGCPHYS pGCPhysSpa));
1284
1285 /**
1286 * Performs a physical memory write transaction through the IOMMU.
1287 *
1288 * @returns VBox status code.
1289 * @param pDevIns The IOMMU device instance.
1290 * @param uDevId The device identifier (bus, device, function).
1291 * @param uIova The I/O virtual address being written.
1292 * @param cbRead The number of bytes being written.
1293 * @param pGCPhysSpa Where to store the translated system physical address.
1294 *
1295 * @thread Any.
1296 */
1297 DECLR0CALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,
1298 PRTGCPHYS pGCPhysSpa));
1299
1300 /**
1301 * Performs an interrupt remap request through the IOMMU.
1302 *
1303 * @returns VBox status code.
1304 * @param pDevIns The IOMMU device instance.
1305 * @param uDevId The device identifier (bus, device, function).
1306 * @param pMsiIn The source MSI.
1307 * @param pMsiOut Where to store the remapped MSI.
1308 *
1309 * @thread Any.
1310 */
1311 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1312
1313 /** Just a safety precaution. */
1314 uint32_t u32TheEnd;
1315} PDMIOMMUREGR0;
1316/** Pointer to a IOMMU registration structure. */
1317typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1318
1319/** Current PDMIOMMUREG version number. */
1320#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 1, 0)
1321
1322
1323/**
1324 * IOMMU registration structure for raw-mode.
1325 */
1326typedef struct PDMIOMMUREGRC
1327{
1328 /** Structure version number. PDM_IOMMUREG_VERSION defines the current
1329 * version. */
1330 uint32_t u32Version;
1331 /** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1332 uint32_t idxIommu;
1333
1334 /**
1335 * Performs a physical memory read transaction through the IOMMU.
1336 *
1337 * @returns VBox status code.
1338 * @param pDevIns The IOMMU device instance.
1339 * @param uDevId The device identifier (bus, device, function).
1340 * @param uIova The I/O virtual address being read.
1341 * @param cbRead The number of bytes being read.
1342 * @param pGCPhysSpa Where to store the translated system physical address.
1343 *
1344 * @thread Any.
1345 */
1346 DECLRCCALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead,
1347 PRTGCPHYS pGCPhysSpa));
1348
1349 /**
1350 * Performs a physical memory write transaction through the IOMMU.
1351 *
1352 * @returns VBox status code.
1353 * @param pDevIns The IOMMU device instance.
1354 * @param uDevId The device identifier (bus, device, function).
1355 * @param uIova The I/O virtual address being written.
1356 * @param cbRead The number of bytes being written.
1357 * @param pGCPhysSpa Where to store the translated system physical address.
1358 *
1359 * @thread Any.
1360 */
1361 DECLRCCALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,
1362 PRTGCPHYS pGCPhysSpa));
1363
1364 /**
1365 * Performs an interrupt remap request through the IOMMU.
1366 *
1367 * @returns VBox status code.
1368 * @param pDevIns The IOMMU device instance.
1369 * @param uDevId The device identifier (bus, device, function).
1370 * @param pMsiIn The source MSI.
1371 * @param pMsiOut Where to store the remapped MSI.
1372 *
1373 * @thread Any.
1374 */
1375 DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1376
1377 /** Just a safety precaution. */
1378 uint32_t u32TheEnd;
1379} PDMIOMMUREGRC;
1380/** Pointer to a IOMMU registration structure. */
1381typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1382
1383/** Current PDMIOMMUREG version number. */
1384#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 1, 0)
1385
1386
1387/**
1388 * IOMMU registration structure for ring-3.
1389 */
1390typedef struct PDMIOMMUREGR3
1391{
1392 /** Structure version number. PDM_IOMMUREG_VERSION defines the current
1393 * version. */
1394 uint32_t u32Version;
1395 /** Padding. */
1396 uint32_t uPadding0;
1397
1398 /**
1399 * Performs a physical memory read transaction through the IOMMU.
1400 *
1401 * @returns VBox status code.
1402 * @param pDevIns The IOMMU device instance.
1403 * @param uDevId The device identifier (bus, device, function).
1404 * @param uIova The I/O virtual address being read.
1405 * @param cbRead The number of bytes being read.
1406 * @param pGCPhysSpa Where to store the translated system physical address.
1407 *
1408 * @thread Any.
1409 */
1410 DECLR3CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead,
1411 PRTGCPHYS pGCPhysSpa));
1412
1413 /**
1414 * Performs a physical memory write transaction through the IOMMU.
1415 *
1416 * @returns VBox status code.
1417 * @param pDevIns The IOMMU device instance.
1418 * @param uDevId The device identifier (bus, device, function).
1419 * @param uIova The I/O virtual address being written.
1420 * @param cbWrite The number of bytes being written.
1421 * @param pGCPhysSpa Where to store the translated system physical address.
1422 *
1423 * @thread Any.
1424 */
1425 DECLR3CALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,
1426 PRTGCPHYS pGCPhysSpa));
1427
1428 /**
1429 * Performs an interrupt remap request through the IOMMU.
1430 *
1431 * @returns VBox status code.
1432 * @param pDevIns The IOMMU device instance.
1433 * @param uDevId The device identifier (bus, device, function).
1434 * @param pMsiIn The source MSI.
1435 * @param pMsiOut Where to store the remapped MSI.
1436 *
1437 * @thread Any.
1438 */
1439 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1440
1441 /** Just a safety precaution. */
1442 uint32_t u32TheEnd;
1443} PDMIOMMUREGR3;
1444/** Pointer to a IOMMU registration structure. */
1445typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1446
1447/** Current PDMIOMMUREG version number. */
1448#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 1, 0)
1449
1450/** IOMMU registration structure for the current context. */
1451typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1452/** Pointer to an IOMMU registration structure for the current context. */
1453typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1454/** IOMMU registration structure version for the current context. */
1455#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1456
1457
1458/**
1459 * IOMMU helpers for ring-0.
1460 */
1461typedef struct PDMIOMMUHLPR0
1462{
1463 /** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1464 uint32_t u32Version;
1465 /** Just a safety precaution. */
1466 uint32_t u32TheEnd;
1467} PDMIOMMUHLPR0;
1468/** Pointer to IOMMU helpers for ring-0. */
1469typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1470/** Pointer to const IOMMU helpers for ring-0. */
1471typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1472
1473/** Current PDMIOMMUHLPR0 version number. */
1474#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 1, 0)
1475
1476
1477/**
1478 * IOMMU helpers for raw-mode.
1479 */
1480typedef struct PDMIOMMUHLPRC
1481{
1482 /** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1483 uint32_t u32Version;
1484 /** Just a safety precaution. */
1485 uint32_t u32TheEnd;
1486} PDMIOMMUHLPRC;
1487/** Pointer to IOMMU helpers for raw-mode. */
1488typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1489/** Pointer to const IOMMU helpers for raw-mode. */
1490typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1491
1492/** Current PDMIOMMUHLPRC version number. */
1493#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 1, 0)
1494
1495
1496/**
1497 * IOMMU helpers for ring-3.
1498 */
1499typedef struct PDMIOMMUHLPR3
1500{
1501 /** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1502 uint32_t u32Version;
1503 /** Just a safety precaution. */
1504 uint32_t u32TheEnd;
1505} PDMIOMMUHLPR3;
1506/** Pointer to IOMMU helpers for raw-mode. */
1507typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1508/** Pointer to const IOMMU helpers for raw-mode. */
1509typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1510
1511/** Current PDMIOMMUHLPR3 version number. */
1512#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 1, 0)
1513
1514
1515/**
1516 * Programmable Interrupt Controller registration structure (all contexts).
1517 */
1518typedef struct PDMPICREG
1519{
1520 /** Structure version number. PDM_PICREG_VERSION defines the current version. */
1521 uint32_t u32Version;
1522
1523 /**
1524 * Set the an IRQ.
1525 *
1526 * @param pDevIns Device instance of the PIC.
1527 * @param iIrq IRQ number to set.
1528 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1529 * @param uTagSrc The IRQ tag and source (for tracing).
1530 * @remarks Caller enters the PDM critical section.
1531 */
1532 DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1533
1534 /**
1535 * Get a pending interrupt.
1536 *
1537 * @returns Pending interrupt number.
1538 * @param pDevIns Device instance of the PIC.
1539 * @param puTagSrc Where to return the IRQ tag and source.
1540 * @remarks Caller enters the PDM critical section.
1541 */
1542 DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1543
1544 /** Just a safety precaution. */
1545 uint32_t u32TheEnd;
1546} PDMPICREG;
1547/** Pointer to a PIC registration structure. */
1548typedef PDMPICREG *PPDMPICREG;
1549
1550/** Current PDMPICREG version number. */
1551#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1552
1553/**
1554 * PIC helpers, same in all contexts.
1555 */
1556typedef struct PDMPICHLP
1557{
1558 /** Structure version. PDM_PICHLP_VERSION defines the current version. */
1559 uint32_t u32Version;
1560
1561 /**
1562 * Set the interrupt force action flag.
1563 *
1564 * @param pDevIns Device instance of the PIC.
1565 */
1566 DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1567
1568 /**
1569 * Clear the interrupt force action flag.
1570 *
1571 * @param pDevIns Device instance of the PIC.
1572 */
1573 DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1574
1575 /**
1576 * Acquires the PDM lock.
1577 *
1578 * @returns VINF_SUCCESS on success.
1579 * @returns rc if we failed to acquire the lock.
1580 * @param pDevIns The PIC device instance.
1581 * @param rc What to return if we fail to acquire the lock.
1582 */
1583 DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1584
1585 /**
1586 * Releases the PDM lock.
1587 *
1588 * @param pDevIns The PIC device instance.
1589 */
1590 DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1591
1592 /** Just a safety precaution. */
1593 uint32_t u32TheEnd;
1594} PDMPICHLP;
1595/** Pointer to PIC helpers. */
1596typedef PDMPICHLP *PPDMPICHLP;
1597/** Pointer to const PIC helpers. */
1598typedef const PDMPICHLP *PCPDMPICHLP;
1599
1600/** Current PDMPICHLP version number. */
1601#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1602
1603
1604/**
1605 * Firmware registration structure.
1606 */
1607typedef struct PDMFWREG
1608{
1609 /** Struct version+magic number (PDM_FWREG_VERSION). */
1610 uint32_t u32Version;
1611
1612 /**
1613 * Checks whether this is a hard or soft reset.
1614 *
1615 * The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1616 * is 5, 9 or 0xA.
1617 *
1618 * @returns true if hard reset, false if soft.
1619 * @param pDevIns Device instance of the firmware.
1620 * @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1621 */
1622 DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1623
1624 /** Just a safety precaution. */
1625 uint32_t u32TheEnd;
1626} PDMFWREG;
1627/** Pointer to a FW registration structure. */
1628typedef PDMFWREG *PPDMFWREG;
1629/** Pointer to a const FW registration structure. */
1630typedef PDMFWREG const *PCPDMFWREG;
1631
1632/** Current PDMFWREG version number. */
1633#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1634
1635/**
1636 * Firmware R3 helpers.
1637 */
1638typedef struct PDMFWHLPR3
1639{
1640 /** Structure version. PDM_FWHLP_VERSION defines the current version. */
1641 uint32_t u32Version;
1642
1643 /** Just a safety precaution. */
1644 uint32_t u32TheEnd;
1645} PDMFWHLPR3;
1646
1647/** Pointer to FW R3 helpers. */
1648typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1649/** Pointer to const FW R3 helpers. */
1650typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1651
1652/** Current PDMFWHLPR3 version number. */
1653#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1654
1655
1656/**
1657 * APIC mode argument for apicR3SetCpuIdFeatureLevel.
1658 *
1659 * Also used in saved-states, CFGM don't change existing values.
1660 */
1661typedef enum PDMAPICMODE
1662{
1663 /** Invalid 0 entry. */
1664 PDMAPICMODE_INVALID = 0,
1665 /** No APIC. */
1666 PDMAPICMODE_NONE,
1667 /** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1668 PDMAPICMODE_APIC,
1669 /** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1670 PDMAPICMODE_X2APIC,
1671 /** The usual 32-bit paranoia. */
1672 PDMAPICMODE_32BIT_HACK = 0x7fffffff
1673} PDMAPICMODE;
1674
1675/**
1676 * APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1677 */
1678typedef enum PDMAPICIRQ
1679{
1680 /** Invalid 0 entry. */
1681 PDMAPICIRQ_INVALID = 0,
1682 /** Normal hardware interrupt. */
1683 PDMAPICIRQ_HARDWARE,
1684 /** NMI. */
1685 PDMAPICIRQ_NMI,
1686 /** SMI. */
1687 PDMAPICIRQ_SMI,
1688 /** ExtINT (HW interrupt via PIC). */
1689 PDMAPICIRQ_EXTINT,
1690 /** Interrupt arrived, needs to be updated to the IRR. */
1691 PDMAPICIRQ_UPDATE_PENDING,
1692 /** The usual 32-bit paranoia. */
1693 PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1694} PDMAPICIRQ;
1695
1696
1697/**
1698 * I/O APIC registration structure (all contexts).
1699 */
1700typedef struct PDMIOAPICREG
1701{
1702 /** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1703 uint32_t u32Version;
1704
1705 /**
1706 * Set an IRQ.
1707 *
1708 * @param pDevIns Device instance of the I/O APIC.
1709 * @param uBusDevFn The bus:device:function of the device initiating the
1710 * IRQ. Can be NIL_PCIBDF.
1711 * @param iIrq IRQ number to set.
1712 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1713 * @param uTagSrc The IRQ tag and source (for tracing).
1714 *
1715 * @remarks Caller enters the PDM critical section
1716 * Actually, as per 2018-07-21 this isn't true (bird).
1717 */
1718 DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1719
1720 /**
1721 * Send a MSI.
1722 *
1723 * @param pDevIns Device instance of the I/O APIC.
1724 * @param uBusDevFn The bus:device:function of the device initiating the
1725 * MSI. Cannot be NIL_PCIBDF.
1726 * @param pMsi The MSI to send.
1727 * @param uTagSrc The IRQ tag and source (for tracing).
1728 *
1729 * @remarks Caller enters the PDM critical section
1730 * Actually, as per 2018-07-21 this isn't true (bird).
1731 */
1732 DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1733
1734 /**
1735 * Set the EOI for an interrupt vector.
1736 *
1737 * @returns Strict VBox status code - only the following informational status codes:
1738 * @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
1739 * @retval VINF_SUCCESS
1740 *
1741 * @param pDevIns Device instance of the I/O APIC.
1742 * @param u8Vector The vector.
1743 *
1744 * @remarks Caller enters the PDM critical section
1745 * Actually, as per 2018-07-21 this isn't true (bird).
1746 */
1747 DECLCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1748
1749 /** Just a safety precaution. */
1750 uint32_t u32TheEnd;
1751} PDMIOAPICREG;
1752/** Pointer to an APIC registration structure. */
1753typedef PDMIOAPICREG *PPDMIOAPICREG;
1754
1755/** Current PDMAPICREG version number. */
1756#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 7, 0)
1757
1758
1759/**
1760 * IOAPIC helpers, same in all contexts.
1761 */
1762typedef struct PDMIOAPICHLP
1763{
1764 /** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1765 uint32_t u32Version;
1766
1767 /**
1768 * Private interface between the IOAPIC and APIC.
1769 *
1770 * @returns status code.
1771 * @param pDevIns Device instance of the IOAPIC.
1772 * @param u8Dest See APIC implementation.
1773 * @param u8DestMode See APIC implementation.
1774 * @param u8DeliveryMode See APIC implementation.
1775 * @param uVector See APIC implementation.
1776 * @param u8Polarity See APIC implementation.
1777 * @param u8TriggerMode See APIC implementation.
1778 * @param uTagSrc The IRQ tag and source (for tracing).
1779 *
1780 * @sa APICBusDeliver()
1781 */
1782 DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1783 uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1784
1785 /**
1786 * Acquires the PDM lock.
1787 *
1788 * @returns VINF_SUCCESS on success.
1789 * @returns rc if we failed to acquire the lock.
1790 * @param pDevIns The IOAPIC device instance.
1791 * @param rc What to return if we fail to acquire the lock.
1792 */
1793 DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1794
1795 /**
1796 * Releases the PDM lock.
1797 *
1798 * @param pDevIns The IOAPIC device instance.
1799 */
1800 DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1801
1802 /**
1803 * Private interface between the IOAPIC and IOMMU.
1804 *
1805 * @returns status code.
1806 * @param pDevIns Device instance of the IOAPIC.
1807 * @param uDevId The device ID (bus, device, function) for the source MSI.
1808 * @param pMsiIn The source MSI.
1809 * @param pMsiOut Where to store the remapped MSI.
1810 *
1811 * @sa iommuAmdDeviceMsiRemap().
1812 */
1813 DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevIt, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1814
1815 /** Just a safety precaution. */
1816 uint32_t u32TheEnd;
1817} PDMIOAPICHLP;
1818/** Pointer to IOAPIC helpers. */
1819typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1820/** Pointer to const IOAPIC helpers. */
1821typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1822
1823/** Current PDMIOAPICHLP version number. */
1824#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 2, 1)
1825
1826
1827/**
1828 * HPET registration structure.
1829 */
1830typedef struct PDMHPETREG
1831{
1832 /** Struct version+magic number (PDM_HPETREG_VERSION). */
1833 uint32_t u32Version;
1834} PDMHPETREG;
1835/** Pointer to an HPET registration structure. */
1836typedef PDMHPETREG *PPDMHPETREG;
1837
1838/** Current PDMHPETREG version number. */
1839#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1840
1841/**
1842 * HPET RC helpers.
1843 *
1844 * @remarks Keep this around in case HPET will need PDM interaction in again RC
1845 * at some later point.
1846 */
1847typedef struct PDMHPETHLPRC
1848{
1849 /** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
1850 uint32_t u32Version;
1851
1852 /** Just a safety precaution. */
1853 uint32_t u32TheEnd;
1854} PDMHPETHLPRC;
1855
1856/** Pointer to HPET RC helpers. */
1857typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
1858/** Pointer to const HPET RC helpers. */
1859typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
1860
1861/** Current PDMHPETHLPRC version number. */
1862#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
1863
1864
1865/**
1866 * HPET R0 helpers.
1867 *
1868 * @remarks Keep this around in case HPET will need PDM interaction in again R0
1869 * at some later point.
1870 */
1871typedef struct PDMHPETHLPR0
1872{
1873 /** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
1874 uint32_t u32Version;
1875
1876 /** Just a safety precaution. */
1877 uint32_t u32TheEnd;
1878} PDMHPETHLPR0;
1879
1880/** Pointer to HPET R0 helpers. */
1881typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
1882/** Pointer to const HPET R0 helpers. */
1883typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
1884
1885/** Current PDMHPETHLPR0 version number. */
1886#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
1887
1888/**
1889 * HPET R3 helpers.
1890 */
1891typedef struct PDMHPETHLPR3
1892{
1893 /** Structure version. PDM_HPETHLP_VERSION defines the current version. */
1894 uint32_t u32Version;
1895
1896 /**
1897 * Set legacy mode on PIT and RTC.
1898 *
1899 * @returns VINF_SUCCESS on success.
1900 * @returns rc if we failed to set legacy mode.
1901 * @param pDevIns Device instance of the HPET.
1902 * @param fActivated Whether legacy mode is activated or deactivated.
1903 */
1904 DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
1905
1906
1907 /**
1908 * Set IRQ, bypassing ISA bus override rules.
1909 *
1910 * @returns VINF_SUCCESS on success.
1911 * @returns rc if we failed to set legacy mode.
1912 * @param pDevIns Device instance of the HPET.
1913 * @param iIrq IRQ number to set.
1914 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1915 */
1916 DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
1917
1918 /** Just a safety precaution. */
1919 uint32_t u32TheEnd;
1920} PDMHPETHLPR3;
1921
1922/** Pointer to HPET R3 helpers. */
1923typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
1924/** Pointer to const HPET R3 helpers. */
1925typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
1926
1927/** Current PDMHPETHLPR3 version number. */
1928#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
1929
1930
1931/**
1932 * Raw PCI device registration structure.
1933 */
1934typedef struct PDMPCIRAWREG
1935{
1936 /** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
1937 uint32_t u32Version;
1938 /** Just a safety precaution. */
1939 uint32_t u32TheEnd;
1940} PDMPCIRAWREG;
1941/** Pointer to a raw PCI registration structure. */
1942typedef PDMPCIRAWREG *PPDMPCIRAWREG;
1943
1944/** Current PDMPCIRAWREG version number. */
1945#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
1946
1947/**
1948 * Raw PCI device raw-mode context helpers.
1949 */
1950typedef struct PDMPCIRAWHLPRC
1951{
1952 /** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
1953 uint32_t u32Version;
1954 /** Just a safety precaution. */
1955 uint32_t u32TheEnd;
1956} PDMPCIRAWHLPRC;
1957/** Pointer to a raw PCI deviec raw-mode context helper structure. */
1958typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
1959/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
1960typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
1961
1962/** Current PDMPCIRAWHLPRC version number. */
1963#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
1964
1965/**
1966 * Raw PCI device ring-0 context helpers.
1967 */
1968typedef struct PDMPCIRAWHLPR0
1969{
1970 /** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
1971 uint32_t u32Version;
1972 /** Just a safety precaution. */
1973 uint32_t u32TheEnd;
1974} PDMPCIRAWHLPR0;
1975/** Pointer to a raw PCI deviec ring-0 context helper structure. */
1976typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
1977/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
1978typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
1979
1980/** Current PDMPCIRAWHLPR0 version number. */
1981#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
1982
1983
1984/**
1985 * Raw PCI device ring-3 context helpers.
1986 */
1987typedef struct PDMPCIRAWHLPR3
1988{
1989 /** Undefined structure version and magic number. */
1990 uint32_t u32Version;
1991
1992 /**
1993 * Gets the address of the RC raw PCI device helpers.
1994 *
1995 * This should be called at both construction and relocation time to obtain
1996 * the correct address of the RC helpers.
1997 *
1998 * @returns RC pointer to the raw PCI device helpers.
1999 * @param pDevIns Device instance of the raw PCI device.
2000 */
2001 DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2002
2003 /**
2004 * Gets the address of the R0 raw PCI device helpers.
2005 *
2006 * This should be called at both construction and relocation time to obtain
2007 * the correct address of the R0 helpers.
2008 *
2009 * @returns R0 pointer to the raw PCI device helpers.
2010 * @param pDevIns Device instance of the raw PCI device.
2011 */
2012 DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2013
2014 /** Just a safety precaution. */
2015 uint32_t u32TheEnd;
2016} PDMPCIRAWHLPR3;
2017/** Pointer to raw PCI R3 helpers. */
2018typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2019/** Pointer to const raw PCI R3 helpers. */
2020typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2021
2022/** Current PDMPCIRAWHLPR3 version number. */
2023#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2024
2025
2026#ifdef IN_RING3
2027
2028/**
2029 * DMA Transfer Handler.
2030 *
2031 * @returns Number of bytes transferred.
2032 * @param pDevIns Device instance of the DMA.
2033 * @param pvUser User pointer.
2034 * @param uChannel Channel number.
2035 * @param off DMA position.
2036 * @param cb Block size.
2037 * @remarks The device lock is not taken, however, the DMA device lock is held.
2038 */
2039typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2040 uint32_t off, uint32_t cb));
2041/** Pointer to a FNDMATRANSFERHANDLER(). */
2042typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2043
2044/**
2045 * DMA Controller registration structure.
2046 */
2047typedef struct PDMDMAREG
2048{
2049 /** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2050 uint32_t u32Version;
2051
2052 /**
2053 * Execute pending transfers.
2054 *
2055 * @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2056 * @param pDevIns Device instance of the DMAC.
2057 * @remarks No locks held, called on EMT(0) as a form of serialization.
2058 */
2059 DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2060
2061 /**
2062 * Register transfer function for DMA channel.
2063 *
2064 * @param pDevIns Device instance of the DMAC.
2065 * @param uChannel Channel number.
2066 * @param pfnTransferHandler Device specific transfer function.
2067 * @param pvUser User pointer to be passed to the callback.
2068 * @remarks No locks held, called on an EMT.
2069 */
2070 DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2071
2072 /**
2073 * Read memory
2074 *
2075 * @returns Number of bytes read.
2076 * @param pDevIns Device instance of the DMAC.
2077 * @param uChannel Channel number.
2078 * @param pvBuffer Pointer to target buffer.
2079 * @param off DMA position.
2080 * @param cbBlock Block size.
2081 * @remarks No locks held, called on an EMT.
2082 */
2083 DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2084
2085 /**
2086 * Write memory
2087 *
2088 * @returns Number of bytes written.
2089 * @param pDevIns Device instance of the DMAC.
2090 * @param uChannel Channel number.
2091 * @param pvBuffer Memory to write.
2092 * @param off DMA position.
2093 * @param cbBlock Block size.
2094 * @remarks No locks held, called on an EMT.
2095 */
2096 DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2097
2098 /**
2099 * Set the DREQ line.
2100 *
2101 * @param pDevIns Device instance of the DMAC.
2102 * @param uChannel Channel number.
2103 * @param uLevel Level of the line.
2104 * @remarks No locks held, called on an EMT.
2105 */
2106 DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2107
2108 /**
2109 * Get channel mode
2110 *
2111 * @returns Channel mode.
2112 * @param pDevIns Device instance of the DMAC.
2113 * @param uChannel Channel number.
2114 * @remarks No locks held, called on an EMT.
2115 */
2116 DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2117
2118} PDMDMACREG;
2119/** Pointer to a DMAC registration structure. */
2120typedef PDMDMACREG *PPDMDMACREG;
2121
2122/** Current PDMDMACREG version number. */
2123#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 1, 0)
2124
2125
2126/**
2127 * DMA Controller device helpers.
2128 */
2129typedef struct PDMDMACHLP
2130{
2131 /** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2132 uint32_t u32Version;
2133
2134 /* to-be-defined */
2135
2136} PDMDMACHLP;
2137/** Pointer to DMAC helpers. */
2138typedef PDMDMACHLP *PPDMDMACHLP;
2139/** Pointer to const DMAC helpers. */
2140typedef const PDMDMACHLP *PCPDMDMACHLP;
2141
2142/** Current PDMDMACHLP version number. */
2143#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2144
2145#endif /* IN_RING3 */
2146
2147
2148
2149/**
2150 * RTC registration structure.
2151 */
2152typedef struct PDMRTCREG
2153{
2154 /** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2155 uint32_t u32Version;
2156 uint32_t u32Alignment; /**< structure size alignment. */
2157
2158 /**
2159 * Write to a CMOS register and update the checksum if necessary.
2160 *
2161 * @returns VBox status code.
2162 * @param pDevIns Device instance of the RTC.
2163 * @param iReg The CMOS register index.
2164 * @param u8Value The CMOS register value.
2165 * @remarks Caller enters the device critical section.
2166 */
2167 DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2168
2169 /**
2170 * Read a CMOS register.
2171 *
2172 * @returns VBox status code.
2173 * @param pDevIns Device instance of the RTC.
2174 * @param iReg The CMOS register index.
2175 * @param pu8Value Where to store the CMOS register value.
2176 * @remarks Caller enters the device critical section.
2177 */
2178 DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2179
2180} PDMRTCREG;
2181/** Pointer to a RTC registration structure. */
2182typedef PDMRTCREG *PPDMRTCREG;
2183/** Pointer to a const RTC registration structure. */
2184typedef const PDMRTCREG *PCPDMRTCREG;
2185
2186/** Current PDMRTCREG version number. */
2187#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2188
2189
2190/**
2191 * RTC device helpers.
2192 */
2193typedef struct PDMRTCHLP
2194{
2195 /** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2196 uint32_t u32Version;
2197
2198 /* to-be-defined */
2199
2200} PDMRTCHLP;
2201/** Pointer to RTC helpers. */
2202typedef PDMRTCHLP *PPDMRTCHLP;
2203/** Pointer to const RTC helpers. */
2204typedef const PDMRTCHLP *PCPDMRTCHLP;
2205
2206/** Current PDMRTCHLP version number. */
2207#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2208
2209
2210
2211/** @name Flags for PCI I/O region registration
2212 * @{ */
2213/** No handle is passed. */
2214#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2215/** An I/O port handle is passed. */
2216#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2217/** An MMIO range handle is passed. */
2218#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2219/** An MMIO2 handle is passed. */
2220#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2221/** Handle type mask. */
2222#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2223/** New-style (mostly wrt callbacks). */
2224#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2225/** Mask of valid flags. */
2226#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2227/** @} */
2228
2229
2230/** @name Flags for the guest physical read/write helpers
2231 * @{ */
2232/** Default flag with no indication whether the data is processed by the device or just passed through. */
2233#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2234/** The data is user data which is just passed through between the guest and the source or destination and not processed
2235 * by the device in any way. */
2236#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2237/** The data is metadata and being processed by the device in some way. */
2238#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2239/** @} */
2240
2241
2242#ifdef IN_RING3
2243
2244/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2245 * @{ */
2246/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2247 * This is handy when registering multiple PCI device functions and the device
2248 * number is left up to the PCI bus. In order to facilitate one PDM device
2249 * instance for each PCI function, this searches earlier PDM device
2250 * instances as well. */
2251# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2252/** Use the first unused device number (all functions must be unused). */
2253# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2254/** Use the first unused device function. */
2255# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2256
2257/** The device and function numbers are not mandatory, just suggestions. */
2258# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2259/** Registering a PCI bridge device. */
2260# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2261/** Valid flag mask. */
2262# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2263/** @} */
2264
2265/** Current PDMDEVHLPR3 version number. */
2266#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 44, 0)
2267
2268/**
2269 * PDM Device API.
2270 */
2271typedef struct PDMDEVHLPR3
2272{
2273 /** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2274 uint32_t u32Version;
2275
2276 /** @name I/O ports
2277 * @{ */
2278 /**
2279 * Creates a range of I/O ports for a device.
2280 *
2281 * The I/O port range must be mapped in a separately call. Any ring-0 and
2282 * raw-mode context callback handlers needs to be set up in the respective
2283 * contexts.
2284 *
2285 * @returns VBox status.
2286 * @param pDevIns The device instance to register the ports with.
2287 * @param cPorts Number of ports to register.
2288 * @param fFlags IOM_IOPORT_F_XXX.
2289 * @param pPciDev The PCI device the range is associated with, if
2290 * applicable.
2291 * @param iPciRegion The PCI device region in the high 16-bit word and
2292 * sub-region in the low 16-bit word. UINT32_MAX if NA.
2293 * @param pfnOut Pointer to function which is gonna handle OUT
2294 * operations. Optional.
2295 * @param pfnIn Pointer to function which is gonna handle IN operations.
2296 * Optional.
2297 * @param pfnOutStr Pointer to function which is gonna handle string OUT
2298 * operations. Optional.
2299 * @param pfnInStr Pointer to function which is gonna handle string IN
2300 * operations. Optional.
2301 * @param pvUser User argument to pass to the callbacks.
2302 * @param pszDesc Pointer to description string. This must not be freed.
2303 * @param paExtDescs Extended per-port descriptions, optional. Partial range
2304 * coverage is allowed. This must not be freed.
2305 * @param phIoPorts Where to return the I/O port range handle.
2306 *
2307 * @remarks Caller enters the device critical section prior to invoking the
2308 * registered callback methods.
2309 *
2310 * @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2311 * PDMDevHlpIoPortUnmap.
2312 */
2313 DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2314 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2315 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2316 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2317
2318 /**
2319 * Maps an I/O port range.
2320 *
2321 * @returns VBox status.
2322 * @param pDevIns The device instance to register the ports with.
2323 * @param hIoPorts The I/O port range handle.
2324 * @param Port Where to map the range.
2325 * @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2326 * PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2327 */
2328 DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2329
2330 /**
2331 * Unmaps an I/O port range.
2332 *
2333 * @returns VBox status.
2334 * @param pDevIns The device instance to register the ports with.
2335 * @param hIoPorts The I/O port range handle.
2336 * @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2337 * PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2338 */
2339 DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2340
2341 /**
2342 * Gets the mapping address of the I/O port range @a hIoPorts.
2343 *
2344 * @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2345 * parameters).
2346 * @param pDevIns The device instance to register the ports with.
2347 * @param hIoPorts The I/O port range handle.
2348 */
2349 DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2350 /** @} */
2351
2352 /** @name MMIO
2353 * @{ */
2354 /**
2355 * Creates a memory mapped I/O (MMIO) region for a device.
2356 *
2357 * The MMIO region must be mapped in a separately call. Any ring-0 and
2358 * raw-mode context callback handlers needs to be set up in the respective
2359 * contexts.
2360 *
2361 * @returns VBox status.
2362 * @param pDevIns The device instance to register the ports with.
2363 * @param cbRegion The size of the region in bytes.
2364 * @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2365 * @param pPciDev The PCI device the range is associated with, if
2366 * applicable.
2367 * @param iPciRegion The PCI device region in the high 16-bit word and
2368 * sub-region in the low 16-bit word. UINT32_MAX if NA.
2369 * @param pfnWrite Pointer to function which is gonna handle Write
2370 * operations.
2371 * @param pfnRead Pointer to function which is gonna handle Read
2372 * operations.
2373 * @param pfnFill Pointer to function which is gonna handle Fill/memset
2374 * operations. (optional)
2375 * @param pvUser User argument to pass to the callbacks.
2376 * @param pszDesc Pointer to description string. This must not be freed.
2377 * @param phRegion Where to return the MMIO region handle.
2378 *
2379 * @remarks Caller enters the device critical section prior to invoking the
2380 * registered callback methods.
2381 *
2382 * @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2383 */
2384 DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2385 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2386 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2387 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion));
2388
2389 /**
2390 * Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2391 *
2392 * @returns VBox status.
2393 * @param pDevIns The device instance the region is associated with.
2394 * @param hRegion The MMIO region handle.
2395 * @param GCPhys Where to map the region.
2396 * @note An MMIO range may overlap with base memory if a lot of RAM is
2397 * configured for the VM, in which case we'll drop the base memory
2398 * pages. Presently we will make no attempt to preserve anything that
2399 * happens to be present in the base memory that is replaced, this is
2400 * technically incorrect but it's just not worth the effort to do
2401 * right, at least not at this point.
2402 * @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2403 * PDMDevHlpMmioSetUpContext
2404 */
2405 DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2406
2407 /**
2408 * Unmaps a memory mapped I/O (MMIO) region.
2409 *
2410 * @returns VBox status.
2411 * @param pDevIns The device instance the region is associated with.
2412 * @param hRegion The MMIO region handle.
2413 * @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2414 * PDMDevHlpMmioSetUpContext
2415 */
2416 DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2417
2418 /**
2419 * Reduces the length of a MMIO range.
2420 *
2421 * This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2422 * only work during saved state restore. It will not call the PCI bus code, as
2423 * that is expected to restore the saved resource configuration.
2424 *
2425 * It just adjusts the mapping length of the region so that when pfnMmioMap is
2426 * called it will only map @a cbRegion bytes and not the value set during
2427 * registration.
2428 *
2429 * @return VBox status code.
2430 * @param pDevIns The device owning the range.
2431 * @param hRegion The MMIO region handle.
2432 * @param cbRegion The new size, must be smaller.
2433 */
2434 DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2435
2436 /**
2437 * Gets the mapping address of the MMIO region @a hRegion.
2438 *
2439 * @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2440 * @param pDevIns The device instance to register the ports with.
2441 * @param hRegion The MMIO region handle.
2442 */
2443 DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2444 /** @} */
2445
2446 /** @name MMIO2
2447 * @{ */
2448 /**
2449 * Creates a MMIO2 region.
2450 *
2451 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2452 * associated with a device. It is also non-shared memory with a permanent
2453 * ring-3 mapping and page backing (presently).
2454 *
2455 * @returns VBox status.
2456 * @param pDevIns The device instance.
2457 * @param pPciDev The PCI device the region is associated with, or
2458 * NULL if no PCI device association.
2459 * @param iPciRegion The region number. Use the PCI region number as
2460 * this must be known to the PCI bus device too. If
2461 * it's not associated with the PCI device, then
2462 * any number up to UINT8_MAX is fine.
2463 * @param cbRegion The size (in bytes) of the region.
2464 * @param fFlags Reserved for future use, must be zero.
2465 * @param pszDesc Pointer to description string. This must not be
2466 * freed.
2467 * @param ppvMapping Where to store the address of the ring-3 mapping
2468 * of the memory.
2469 * @param phRegion Where to return the MMIO2 region handle.
2470 *
2471 * @thread EMT(0)
2472 */
2473 DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2474 uint32_t fFlags, const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion));
2475
2476 /**
2477 * Destroys a MMIO2 region, unmapping it and freeing the memory.
2478 *
2479 * Any physical access handlers registered for the region must be deregistered
2480 * before calling this function.
2481 *
2482 * @returns VBox status code.
2483 * @param pDevIns The device instance.
2484 * @param hRegion The MMIO2 region handle.
2485 * @thread EMT.
2486 */
2487 DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2488
2489 /**
2490 * Maps a MMIO2 region (into the guest physical address space).
2491 *
2492 * @returns VBox status.
2493 * @param pDevIns The device instance the region is associated with.
2494 * @param hRegion The MMIO2 region handle.
2495 * @param GCPhys Where to map the region.
2496 * @note A MMIO2 region overlap with base memory if a lot of RAM is
2497 * configured for the VM, in which case we'll drop the base memory
2498 * pages. Presently we will make no attempt to preserve anything that
2499 * happens to be present in the base memory that is replaced, this is
2500 * technically incorrect but it's just not worth the effort to do
2501 * right, at least not at this point.
2502 * @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2503 */
2504 DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2505
2506 /**
2507 * Unmaps a MMIO2 region.
2508 *
2509 * @returns VBox status.
2510 * @param pDevIns The device instance the region is associated with.
2511 * @param hRegion The MMIO2 region handle.
2512 * @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2513 */
2514 DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2515
2516 /**
2517 * Reduces the length of a MMIO range.
2518 *
2519 * This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2520 * only work during saved state restore. It will not call the PCI bus code, as
2521 * that is expected to restore the saved resource configuration.
2522 *
2523 * It just adjusts the mapping length of the region so that when pfnMmioMap is
2524 * called it will only map @a cbRegion bytes and not the value set during
2525 * registration.
2526 *
2527 * @return VBox status code.
2528 * @param pDevIns The device owning the range.
2529 * @param hRegion The MMIO2 region handle.
2530 * @param cbRegion The new size, must be smaller.
2531 */
2532 DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2533
2534 /**
2535 * Gets the mapping address of the MMIO region @a hRegion.
2536 *
2537 * @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2538 * @param pDevIns The device instance to register the ports with.
2539 * @param hRegion The MMIO2 region handle.
2540 */
2541 DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2542
2543 /**
2544 * Changes the number of an MMIO2 or pre-registered MMIO region.
2545 *
2546 * This should only be used to deal with saved state problems, so there is no
2547 * convenience inline wrapper for this method.
2548 *
2549 * @returns VBox status code.
2550 * @param pDevIns The device instance.
2551 * @param hRegion The MMIO2 region handle.
2552 * @param iNewRegion The new region index.
2553 *
2554 * @sa @bugref{9359}
2555 */
2556 DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2557 /** @} */
2558
2559 /**
2560 * Register a ROM (BIOS) region.
2561 *
2562 * It goes without saying that this is read-only memory. The memory region must be
2563 * in unassigned memory. I.e. from the top of the address space or on the PC in
2564 * the 0xa0000-0xfffff range.
2565 *
2566 * @returns VBox status.
2567 * @param pDevIns The device instance owning the ROM region.
2568 * @param GCPhysStart First physical address in the range.
2569 * Must be page aligned!
2570 * @param cbRange The size of the range (in bytes).
2571 * Must be page aligned!
2572 * @param pvBinary Pointer to the binary data backing the ROM image.
2573 * @param cbBinary The size of the binary pointer. This must
2574 * be equal or smaller than @a cbRange.
2575 * @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2576 * @param pszDesc Pointer to description string. This must not be freed.
2577 *
2578 * @remark There is no way to remove the rom, automatically on device cleanup or
2579 * manually from the device yet. At present I doubt we need such features...
2580 */
2581 DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2582 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc));
2583
2584 /**
2585 * Changes the protection of shadowed ROM mapping.
2586 *
2587 * This is intented for use by the system BIOS, chipset or device in question to
2588 * change the protection of shadowed ROM code after init and on reset.
2589 *
2590 * @param pDevIns The device instance.
2591 * @param GCPhysStart Where the mapping starts.
2592 * @param cbRange The size of the mapping.
2593 * @param enmProt The new protection type.
2594 */
2595 DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2596
2597 /**
2598 * Register a save state data unit.
2599 *
2600 * @returns VBox status.
2601 * @param pDevIns The device instance.
2602 * @param uVersion Data layout version number.
2603 * @param cbGuess The approximate amount of data in the unit.
2604 * Only for progress indicators.
2605 * @param pszBefore Name of data unit which we should be put in
2606 * front of. Optional (NULL).
2607 *
2608 * @param pfnLivePrep Prepare live save callback, optional.
2609 * @param pfnLiveExec Execute live save callback, optional.
2610 * @param pfnLiveVote Vote live save callback, optional.
2611 *
2612 * @param pfnSavePrep Prepare save callback, optional.
2613 * @param pfnSaveExec Execute save callback, optional.
2614 * @param pfnSaveDone Done save callback, optional.
2615 *
2616 * @param pfnLoadPrep Prepare load callback, optional.
2617 * @param pfnLoadExec Execute load callback, optional.
2618 * @param pfnLoadDone Done load callback, optional.
2619 * @remarks Caller enters the device critical section prior to invoking the
2620 * registered callback methods.
2621 */
2622 DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2623 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2624 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2625 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2626
2627 /** @name Exported SSM Functions
2628 * @{ */
2629 DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2630 DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void *pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void *pvUser));
2631 DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2632 DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2633 DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2634 DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2635 DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2636 DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2637 DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2638 DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2639 DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2640 DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2641 DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2642 DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2643 DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2644 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2645 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2646 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2647 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2648 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2649 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2650 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2651 DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2652 DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2653 DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2654 DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2655 DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2656 DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2657 DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void *pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void *pvUser));
2658 DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2659 DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2660 DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2661 DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2662 DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2663 DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2664 DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2665 DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2666 DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2667 DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2668 DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2669 DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2670 DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2671 DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2672 DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2673 DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2674 DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2675 DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2676 DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2677 DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2678 DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2679 DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2680 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2681 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2682 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2683 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2684 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2685 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2686 DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2687 DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2688 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2689 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2690 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2691 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2692 DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2693 DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2694 DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2695 DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2696 DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2697 DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char *psz, size_t cbMax, size_t *pcbStr));
2698 DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2699 DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2700 DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2701 DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2702 DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2703 DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2704 DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2705 DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2706 DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2707 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2708 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2709 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2710 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2711 DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2712 /** @} */
2713
2714 /**
2715 * Creates a timer.
2716 *
2717 * @returns VBox status.
2718 * @param pDevIns The device instance.
2719 * @param enmClock The clock to use on this timer.
2720 * @param pfnCallback Callback function.
2721 * @param pvUser User argument for the callback.
2722 * @param fFlags Flags, see TMTIMER_FLAGS_*.
2723 * @param pszDesc Pointer to description string which must stay around
2724 * until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2725 * @param ppTimer Where to store the timer on success.
2726 * @remarks Caller enters the device critical section prior to invoking the
2727 * callback.
2728 */
2729 DECLR3CALLBACKMEMBER(int, pfnTMTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2730 void *pvUser, uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer));
2731
2732 /**
2733 * Creates a timer w/ a cross context handle.
2734 *
2735 * @returns VBox status.
2736 * @param pDevIns The device instance.
2737 * @param enmClock The clock to use on this timer.
2738 * @param pfnCallback Callback function.
2739 * @param pvUser User argument for the callback.
2740 * @param fFlags Flags, see TMTIMER_FLAGS_*.
2741 * @param pszDesc Pointer to description string which must stay around
2742 * until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2743 * @param phTimer Where to store the timer handle on success.
2744 * @remarks Caller enters the device critical section prior to invoking the
2745 * callback.
2746 */
2747 DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2748 void *pvUser, uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer));
2749
2750 /**
2751 * Translates a timer handle to a pointer.
2752 *
2753 * @returns The time address.
2754 * @param pDevIns The device instance.
2755 * @param hTimer The timer handle.
2756 */
2757 DECLR3CALLBACKMEMBER(PTMTIMERR3, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2758
2759 /** @name Timer handle method wrappers
2760 * @{ */
2761 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2762 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2763 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2764 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2765 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2766 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2767 DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2768 DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2769 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2770 /** Takes the clock lock then enters the specified critical section. */
2771 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2772 DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2773 DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2774 DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2775 DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2776 DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2777 DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2778 DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2779 DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2780 DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2781 DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2782 DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2783 DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2784 DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2785 /** @sa TMR3TimerSkip */
2786 DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2787 /** @} */
2788
2789 /**
2790 * Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2791 *
2792 * @returns pTime.
2793 * @param pDevIns The device instance.
2794 * @param pTime Where to store the time.
2795 */
2796 DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2797
2798 /** @name Exported CFGM Functions.
2799 * @{ */
2800 DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2801 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2802 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char *pszName, size_t *pcb));
2803 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64));
2804 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64, uint64_t u64Def));
2805 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char *pszName, char *pszString, size_t cchString));
2806 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char *pszName, char *pszString, size_t cchString, const char *pszDef));
2807 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char *pszName, void *pvData, size_t cbData));
2808 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64));
2809 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64, uint64_t u64Def));
2810 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char *pszName, int64_t *pi64));
2811 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char *pszName, int64_t *pi64, int64_t i64Def));
2812 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char *pszName, uint32_t *pu32));
2813 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char *pszName, uint32_t *pu32, uint32_t u32Def));
2814 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char *pszName, int32_t *pi32));
2815 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char *pszName, int32_t *pi32, int32_t i32Def));
2816 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char *pszName, uint16_t *pu16));
2817 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char *pszName, uint16_t *pu16, uint16_t u16Def));
2818 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char *pszName, int16_t *pi16));
2819 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char *pszName, int16_t *pi16, int16_t i16Def));
2820 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char *pszName, uint8_t *pu8));
2821 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char *pszName, uint8_t *pu8, uint8_t u8Def));
2822 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char *pszName, int8_t *pi8));
2823 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char *pszName, int8_t *pi8, int8_t i8Def));
2824 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char *pszName, bool *pf));
2825 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char *pszName, bool *pf, bool fDef));
2826 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2827 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2828 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char *pszName, unsigned int *pu));
2829 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char *pszName, unsigned int *pu, unsigned int uDef));
2830 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char *pszName, signed int *pi));
2831 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char *pszName, signed int *pi, signed int iDef));
2832 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char *pszName, void **ppv));
2833 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char *pszName, void **ppv, void *pvDef));
2834 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
2835 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
2836 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
2837 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
2838 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
2839 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
2840 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char *pszName, char **ppszString));
2841 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char *pszName, char **ppszString, const char *pszDef));
2842 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
2843 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
2844 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
2845 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
2846 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
2847 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
2848 DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
2849 DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
2850 DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
2851 DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
2852 DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
2853 DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
2854 DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
2855 DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
2856 DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
2857 DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
2858 const char *pszValidValues, const char *pszValidNodes,
2859 const char *pszWho, uint32_t uInstance));
2860 /** @} */
2861
2862 /**
2863 * Read physical memory.
2864 *
2865 * @returns VINF_SUCCESS (for now).
2866 * @param pDevIns The device instance.
2867 * @param GCPhys Physical address start reading from.
2868 * @param pvBuf Where to put the read bits.
2869 * @param cbRead How many bytes to read.
2870 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
2871 * @thread Any thread, but the call may involve the emulation thread.
2872 */
2873 DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
2874
2875 /**
2876 * Write to physical memory.
2877 *
2878 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
2879 * @param pDevIns The device instance.
2880 * @param GCPhys Physical address to write to.
2881 * @param pvBuf What to write.
2882 * @param cbWrite How many bytes to write.
2883 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
2884 * @thread Any thread, but the call may involve the emulation thread.
2885 */
2886 DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
2887
2888 /**
2889 * Requests the mapping of a guest page into ring-3.
2890 *
2891 * When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2892 * release it.
2893 *
2894 * This API will assume your intention is to write to the page, and will
2895 * therefore replace shared and zero pages. If you do not intend to modify the
2896 * page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
2897 *
2898 * @returns VBox status code.
2899 * @retval VINF_SUCCESS on success.
2900 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2901 * backing or if the page has any active access handlers. The caller
2902 * must fall back on using PGMR3PhysWriteExternal.
2903 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2904 *
2905 * @param pDevIns The device instance.
2906 * @param GCPhys The guest physical address of the page that
2907 * should be mapped.
2908 * @param fFlags Flags reserved for future use, MBZ.
2909 * @param ppv Where to store the address corresponding to
2910 * GCPhys.
2911 * @param pLock Where to store the lock information that
2912 * pfnPhysReleasePageMappingLock needs.
2913 *
2914 * @remark Avoid calling this API from within critical sections (other than the
2915 * PGM one) because of the deadlock risk when we have to delegating the
2916 * task to an EMT.
2917 * @thread Any.
2918 */
2919 DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
2920 PPGMPAGEMAPLOCK pLock));
2921
2922 /**
2923 * Requests the mapping of a guest page into ring-3, external threads.
2924 *
2925 * When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2926 * release it.
2927 *
2928 * @returns VBox status code.
2929 * @retval VINF_SUCCESS on success.
2930 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2931 * backing or if the page as an active ALL access handler. The caller
2932 * must fall back on using PGMPhysRead.
2933 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2934 *
2935 * @param pDevIns The device instance.
2936 * @param GCPhys The guest physical address of the page that
2937 * should be mapped.
2938 * @param fFlags Flags reserved for future use, MBZ.
2939 * @param ppv Where to store the address corresponding to
2940 * GCPhys.
2941 * @param pLock Where to store the lock information that
2942 * pfnPhysReleasePageMappingLock needs.
2943 *
2944 * @remark Avoid calling this API from within critical sections.
2945 * @thread Any.
2946 */
2947 DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
2948 void const **ppv, PPGMPAGEMAPLOCK pLock));
2949
2950 /**
2951 * Release the mapping of a guest page.
2952 *
2953 * This is the counter part of pfnPhysGCPhys2CCPtr and
2954 * pfnPhysGCPhys2CCPtrReadOnly.
2955 *
2956 * @param pDevIns The device instance.
2957 * @param pLock The lock structure initialized by the mapping
2958 * function.
2959 */
2960 DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
2961
2962 /**
2963 * Read guest physical memory by virtual address.
2964 *
2965 * @param pDevIns The device instance.
2966 * @param pvDst Where to put the read bits.
2967 * @param GCVirtSrc Guest virtual address to start reading from.
2968 * @param cb How many bytes to read.
2969 * @thread The emulation thread.
2970 */
2971 DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
2972
2973 /**
2974 * Write to guest physical memory by virtual address.
2975 *
2976 * @param pDevIns The device instance.
2977 * @param GCVirtDst Guest virtual address to write to.
2978 * @param pvSrc What to write.
2979 * @param cb How many bytes to write.
2980 * @thread The emulation thread.
2981 */
2982 DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
2983
2984 /**
2985 * Convert a guest virtual address to a guest physical address.
2986 *
2987 * @returns VBox status code.
2988 * @param pDevIns The device instance.
2989 * @param GCPtr Guest virtual address.
2990 * @param pGCPhys Where to store the GC physical address
2991 * corresponding to GCPtr.
2992 * @thread The emulation thread.
2993 * @remark Careful with page boundaries.
2994 */
2995 DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
2996
2997 /**
2998 * Allocate memory which is associated with current VM instance
2999 * and automatically freed on it's destruction.
3000 *
3001 * @returns Pointer to allocated memory. The memory is *NOT* zero-ed.
3002 * @param pDevIns The device instance.
3003 * @param cb Number of bytes to allocate.
3004 */
3005 DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3006
3007 /**
3008 * Allocate memory which is associated with current VM instance
3009 * and automatically freed on it's destruction. The memory is ZEROed.
3010 *
3011 * @returns Pointer to allocated memory. The memory is *NOT* zero-ed.
3012 * @param pDevIns The device instance.
3013 * @param cb Number of bytes to allocate.
3014 */
3015 DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3016
3017 /**
3018 * Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3019 *
3020 * @param pDevIns The device instance.
3021 * @param pv Pointer to the memory to free.
3022 */
3023 DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3024
3025 /**
3026 * Gets the VM state.
3027 *
3028 * @returns VM state.
3029 * @param pDevIns The device instance.
3030 * @thread Any thread (just keep in mind that it's volatile info).
3031 */
3032 DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3033
3034 /**
3035 * Checks if the VM was teleported and hasn't been fully resumed yet.
3036 *
3037 * @returns true / false.
3038 * @param pDevIns The device instance.
3039 * @thread Any thread.
3040 */
3041 DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3042
3043 /**
3044 * Set the VM error message
3045 *
3046 * @returns rc.
3047 * @param pDevIns The device instance.
3048 * @param rc VBox status code.
3049 * @param SRC_POS Use RT_SRC_POS.
3050 * @param pszFormat Error message format string.
3051 * @param ... Error message arguments.
3052 */
3053 DECLR3CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3054 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
3055
3056 /**
3057 * Set the VM error message
3058 *
3059 * @returns rc.
3060 * @param pDevIns The device instance.
3061 * @param rc VBox status code.
3062 * @param SRC_POS Use RT_SRC_POS.
3063 * @param pszFormat Error message format string.
3064 * @param va Error message arguments.
3065 */
3066 DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3067 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3068
3069 /**
3070 * Set the VM runtime error message
3071 *
3072 * @returns VBox status code.
3073 * @param pDevIns The device instance.
3074 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3075 * @param pszErrorId Error ID string.
3076 * @param pszFormat Error message format string.
3077 * @param ... Error message arguments.
3078 */
3079 DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3080 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
3081
3082 /**
3083 * Set the VM runtime error message
3084 *
3085 * @returns VBox status code.
3086 * @param pDevIns The device instance.
3087 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3088 * @param pszErrorId Error ID string.
3089 * @param pszFormat Error message format string.
3090 * @param va Error message arguments.
3091 */
3092 DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3093 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3094
3095 /**
3096 * Stops the VM and enters the debugger to look at the guest state.
3097 *
3098 * Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3099 * invoking this function directly.
3100 *
3101 * @returns VBox status code which must be passed up to the VMM.
3102 * @param pDevIns The device instance.
3103 * @param pszFile Filename of the assertion location.
3104 * @param iLine The linenumber of the assertion location.
3105 * @param pszFunction Function of the assertion location.
3106 * @param pszFormat Message. (optional)
3107 * @param args Message parameters.
3108 */
3109 DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction,
3110 const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3111
3112 /**
3113 * Register a info handler with DBGF.
3114 *
3115 * @returns VBox status code.
3116 * @param pDevIns The device instance.
3117 * @param pszName The identifier of the info.
3118 * @param pszDesc The description of the info and any arguments
3119 * the handler may take.
3120 * @param pfnHandler The handler function to be called to display the
3121 * info.
3122 */
3123 DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3124
3125 /**
3126 * Register a info handler with DBGF, argv style.
3127 *
3128 * @returns VBox status code.
3129 * @param pDevIns The device instance.
3130 * @param pszName The identifier of the info.
3131 * @param pszDesc The description of the info and any arguments
3132 * the handler may take.
3133 * @param pfnHandler The handler function to be called to display the
3134 * info.
3135 */
3136 DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3137
3138 /**
3139 * Registers a set of registers for a device.
3140 *
3141 * The @a pvUser argument of the getter and setter callbacks will be
3142 * @a pDevIns. The register names will be prefixed by the device name followed
3143 * immediately by the instance number.
3144 *
3145 * @returns VBox status code.
3146 * @param pDevIns The device instance.
3147 * @param paRegisters The register descriptors.
3148 *
3149 * @remarks The device critical section is NOT entered prior to working the
3150 * callbacks registered via this helper!
3151 */
3152 DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3153
3154 /**
3155 * Gets the trace buffer handle.
3156 *
3157 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3158 * really inteded for direct usage, thus no inline wrapper function.
3159 *
3160 * @returns Trace buffer handle or NIL_RTTRACEBUF.
3161 * @param pDevIns The device instance.
3162 */
3163 DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3164
3165 /**
3166 * Registers a statistics sample.
3167 *
3168 * @param pDevIns Device instance of the DMA.
3169 * @param pvSample Pointer to the sample.
3170 * @param enmType Sample type. This indicates what pvSample is
3171 * pointing at.
3172 * @param pszName Sample name, unix path style. If this does not
3173 * start with a '/', the default prefix will be
3174 * prepended, otherwise it will be used as-is.
3175 * @param enmUnit Sample unit.
3176 * @param pszDesc Sample description.
3177 */
3178 DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc));
3179
3180 /**
3181 * Same as pfnSTAMRegister except that the name is specified in a
3182 * RTStrPrintfV like fashion.
3183 *
3184 * @returns VBox status.
3185 * @param pDevIns Device instance of the DMA.
3186 * @param pvSample Pointer to the sample.
3187 * @param enmType Sample type. This indicates what pvSample is
3188 * pointing at.
3189 * @param enmVisibility Visibility type specifying whether unused
3190 * statistics should be visible or not.
3191 * @param enmUnit Sample unit.
3192 * @param pszDesc Sample description.
3193 * @param pszName Sample name format string, unix path style. If
3194 * this does not start with a '/', the default
3195 * prefix will be prepended, otherwise it will be
3196 * used as-is.
3197 * @param args Arguments to the format string.
3198 */
3199 DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3200 STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3201 const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3202
3203 /**
3204 * Registers a PCI device with the default PCI bus.
3205 *
3206 * If a PDM device has more than one PCI device, they must be registered in the
3207 * order of PDMDEVINSR3::apPciDevs.
3208 *
3209 * @returns VBox status code.
3210 * @param pDevIns The device instance.
3211 * @param pPciDev The PCI device structure.
3212 * This must be kept in the instance data.
3213 * The PCI configuration must be initialized before registration.
3214 * @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3215 * PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3216 * @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3217 * PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3218 * device number (0-31). This will be ignored if
3219 * the CFGM configuration contains a PCIDeviceNo
3220 * value.
3221 * @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3222 * function number (0-7). This will be ignored if
3223 * the CFGM configuration contains a PCIFunctionNo
3224 * value.
3225 * @param pszName Device name, if NULL PDMDEVREG::szName is used.
3226 * The pointer is saved, so don't free or changed.
3227 * @note The PCI device configuration is now implicit from the apPciDevs
3228 * index, meaning that the zero'th entry is the primary one and
3229 * subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3230 */
3231 DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3232 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3233
3234 /**
3235 * Initialize MSI or MSI-X emulation support for the given PCI device.
3236 *
3237 * @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3238 *
3239 * @returns VBox status code.
3240 * @param pDevIns The device instance.
3241 * @param pPciDev The PCI device. NULL is an alias for the first
3242 * one registered.
3243 * @param pMsiReg MSI emulation registration structure.
3244 */
3245 DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3246
3247 /**
3248 * Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3249 *
3250 * @returns VBox status code.
3251 * @param pDevIns The device instance.
3252 * @param pPciDev The PCI device structure. If NULL the default
3253 * PCI device for this device instance is used.
3254 * @param iRegion The region number.
3255 * @param cbRegion Size of the region.
3256 * @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3257 * @param fFlags PDMPCIDEV_IORGN_F_XXX.
3258 * @param hHandle An I/O port, MMIO or MMIO2 handle according to
3259 * @a fFlags, UINT64_MAX if no handle is passed
3260 * (old style).
3261 * @param pfnMapUnmap Callback for doing the mapping, optional when a
3262 * handle is specified. The callback will be
3263 * invoked holding only the PDM lock. The device
3264 * lock will _not_ be taken (due to lock order).
3265 */
3266 DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3267 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3268 uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3269
3270 /**
3271 * Register PCI configuration space read/write callbacks.
3272 *
3273 * @returns VBox status code.
3274 * @param pDevIns The device instance.
3275 * @param pPciDev The PCI device structure. If NULL the default
3276 * PCI device for this device instance is used.
3277 * @param pfnRead Pointer to the user defined PCI config read function.
3278 * to call default PCI config read function. Can be NULL.
3279 * @param pfnWrite Pointer to the user defined PCI config write function.
3280 * @remarks The callbacks will be invoked holding the PDM lock. The device lock
3281 * is NOT take because that is very likely be a lock order violation.
3282 * @thread EMT(0)
3283 * @note Only callable during VM creation.
3284 * @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3285 */
3286 DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3287 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3288
3289 /**
3290 * Perform a PCI configuration space write.
3291 *
3292 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3293 *
3294 * @returns Strict VBox status code (mainly DBGFSTOP).
3295 * @param pDevIns The device instance.
3296 * @param pPciDev The PCI device which config space is being read.
3297 * @param uAddress The config space address.
3298 * @param cb The size of the read: 1, 2 or 4 bytes.
3299 * @param u32Value The value to write.
3300 */
3301 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3302 uint32_t uAddress, unsigned cb, uint32_t u32Value));
3303
3304 /**
3305 * Perform a PCI configuration space read.
3306 *
3307 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3308 *
3309 * @returns Strict VBox status code (mainly DBGFSTOP).
3310 * @param pDevIns The device instance.
3311 * @param pPciDev The PCI device which config space is being read.
3312 * @param uAddress The config space address.
3313 * @param cb The size of the read: 1, 2 or 4 bytes.
3314 * @param pu32Value Where to return the value.
3315 */
3316 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3317 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3318
3319 /**
3320 * Bus master physical memory read.
3321 *
3322 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3323 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
3324 * @param pDevIns The device instance.
3325 * @param pPciDev The PCI device structure. If NULL the default
3326 * PCI device for this device instance is used.
3327 * @param GCPhys Physical address start reading from.
3328 * @param pvBuf Where to put the read bits.
3329 * @param cbRead How many bytes to read.
3330 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3331 * @thread Any thread, but the call may involve the emulation thread.
3332 */
3333 DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3334
3335 /**
3336 * Bus master physical memory write.
3337 *
3338 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3339 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
3340 * @param pDevIns The device instance.
3341 * @param pPciDev The PCI device structure. If NULL the default
3342 * PCI device for this device instance is used.
3343 * @param GCPhys Physical address to write to.
3344 * @param pvBuf What to write.
3345 * @param cbWrite How many bytes to write.
3346 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3347 * @thread Any thread, but the call may involve the emulation thread.
3348 */
3349 DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3350
3351 /**
3352 * Sets the IRQ for the given PCI device.
3353 *
3354 * @param pDevIns The device instance.
3355 * @param pPciDev The PCI device structure. If NULL the default
3356 * PCI device for this device instance is used.
3357 * @param iIrq IRQ number to set.
3358 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3359 * @thread Any thread, but will involve the emulation thread.
3360 */
3361 DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3362
3363 /**
3364 * Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3365 * the request when not called from EMT.
3366 *
3367 * @param pDevIns The device instance.
3368 * @param pPciDev The PCI device structure. If NULL the default
3369 * PCI device for this device instance is used.
3370 * @param iIrq IRQ number to set.
3371 * @param iLevel IRQ level.
3372 * @thread Any thread, but will involve the emulation thread.
3373 */
3374 DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3375
3376 /**
3377 * Set ISA IRQ for a device.
3378 *
3379 * @param pDevIns The device instance.
3380 * @param iIrq IRQ number to set.
3381 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3382 * @thread Any thread, but will involve the emulation thread.
3383 */
3384 DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3385
3386 /**
3387 * Set the ISA IRQ for a device, but don't wait for EMT to process
3388 * the request when not called from EMT.
3389 *
3390 * @param pDevIns The device instance.
3391 * @param iIrq IRQ number to set.
3392 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3393 * @thread Any thread, but will involve the emulation thread.
3394 */
3395 DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3396
3397 /**
3398 * Attaches a driver (chain) to the device.
3399 *
3400 * The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3401 * the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3402 *
3403 * @returns VBox status code.
3404 * @param pDevIns The device instance.
3405 * @param iLun The logical unit to attach.
3406 * @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3407 * @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3408 * @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3409 * for the live of the device instance.
3410 */
3411 DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3412 PPDMIBASE *ppBaseInterface, const char *pszDesc));
3413
3414 /**
3415 * Detaches an attached driver (chain) from the device again.
3416 *
3417 * @returns VBox status code.
3418 * @param pDevIns The device instance.
3419 * @param pDrvIns The driver instance to detach.
3420 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3421 */
3422 DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3423
3424 /**
3425 * Reconfigures the driver chain for a LUN, detaching any driver currently
3426 * present there.
3427 *
3428 * Caller will have attach it, of course.
3429 *
3430 * @returns VBox status code.
3431 * @param pDevIns The device instance.
3432 * @param iLun The logical unit to reconfigure.
3433 * @param cDepth The depth of the driver chain. Determins the
3434 * size of @a papszDrivers and @a papConfigs.
3435 * @param papszDrivers The names of the drivers to configure in the
3436 * chain, first entry is the one immediately
3437 * below the device/LUN
3438 * @param papConfigs The configurations for each of the drivers
3439 * in @a papszDrivers array. NULL entries
3440 * corresponds to empty 'Config' nodes. This
3441 * function will take ownership of non-NULL
3442 * CFGM sub-trees and set the array member to
3443 * NULL, so the caller can do cleanups on
3444 * failure. This parameter is optional.
3445 * @param fFlags Reserved, MBZ.
3446 */
3447 DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3448 const char * const *papszDrivers, PCFGMNODE *papConfigs, uint32_t fFlags));
3449
3450 /** @name Exported PDM Queue Functions
3451 * @{ */
3452 /**
3453 * Create a queue.
3454 *
3455 * @returns VBox status code.
3456 * @param pDevIns The device instance.
3457 * @param cbItem The size of a queue item.
3458 * @param cItems The number of items in the queue.
3459 * @param cMilliesInterval The number of milliseconds between polling the queue.
3460 * If 0 then the emulation thread will be notified whenever an item arrives.
3461 * @param pfnCallback The consumer function.
3462 * @param fRZEnabled Set if the queue should work in RC and R0.
3463 * @param pszName The queue base name. The instance number will be
3464 * appended automatically.
3465 * @param ppQueue Where to store the queue pointer on success.
3466 * @thread The emulation thread.
3467 * @remarks The device critical section will NOT be entered before calling the
3468 * callback. No locks will be held, but for now it's safe to assume
3469 * that only one EMT will do queue callbacks at any one time.
3470 */
3471 DECLR3CALLBACKMEMBER(int, pfnQueueCreatePtr,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3472 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3473 PPDMQUEUE *ppQueue));
3474
3475 /**
3476 * Create a queue.
3477 *
3478 * @returns VBox status code.
3479 * @param pDevIns The device instance.
3480 * @param cbItem The size of a queue item.
3481 * @param cItems The number of items in the queue.
3482 * @param cMilliesInterval The number of milliseconds between polling the queue.
3483 * If 0 then the emulation thread will be notified whenever an item arrives.
3484 * @param pfnCallback The consumer function.
3485 * @param fRZEnabled Set if the queue should work in RC and R0.
3486 * @param pszName The queue base name. The instance number will be
3487 * appended automatically.
3488 * @param phQueue Where to store the queue handle on success.
3489 * @thread EMT(0)
3490 * @remarks The device critical section will NOT be entered before calling the
3491 * callback. No locks will be held, but for now it's safe to assume
3492 * that only one EMT will do queue callbacks at any one time.
3493 */
3494 DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3495 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3496 PDMQUEUEHANDLE *phQueue));
3497
3498 DECLR3CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3499 DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3500 DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3501 DECLR3CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
3502 DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3503 /** @} */
3504
3505 /** @name PDM Task
3506 * @{ */
3507 /**
3508 * Create an asynchronous ring-3 task.
3509 *
3510 * @returns VBox status code.
3511 * @param pDevIns The device instance.
3512 * @param fFlags PDMTASK_F_XXX
3513 * @param pszName The function name or similar. Used for statistics,
3514 * so no slashes.
3515 * @param pfnCallback The task function.
3516 * @param pvUser User argument for the task function.
3517 * @param phTask Where to return the task handle.
3518 * @thread EMT(0)
3519 */
3520 DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3521 PFNPDMTASKDEV pfnCallback, void *pvUser, PDMTASKHANDLE *phTask));
3522 /**
3523 * Triggers the running the given task.
3524 *
3525 * @returns VBox status code.
3526 * @retval VINF_ALREADY_POSTED is the task is already pending.
3527 * @param pDevIns The device instance.
3528 * @param hTask The task to trigger.
3529 * @thread Any thread.
3530 */
3531 DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3532 /** @} */
3533
3534 /** @name SUP Event Semaphore Wrappers (single release / auto reset)
3535 * These semaphores can be signalled from ring-0.
3536 * @{ */
3537 /** @sa SUPSemEventCreate */
3538 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3539 /** @sa SUPSemEventClose */
3540 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3541 /** @sa SUPSemEventSignal */
3542 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3543 /** @sa SUPSemEventWaitNoResume */
3544 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3545 /** @sa SUPSemEventWaitNsAbsIntr */
3546 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3547 /** @sa SUPSemEventWaitNsRelIntr */
3548 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3549 /** @sa SUPSemEventGetResolution */
3550 DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3551 /** @} */
3552
3553 /** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3554 * These semaphores can be signalled from ring-0.
3555 * @{ */
3556 /** @sa SUPSemEventMultiCreate */
3557 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3558 /** @sa SUPSemEventMultiClose */
3559 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3560 /** @sa SUPSemEventMultiSignal */
3561 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3562 /** @sa SUPSemEventMultiReset */
3563 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3564 /** @sa SUPSemEventMultiWaitNoResume */
3565 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3566 /** @sa SUPSemEventMultiWaitNsAbsIntr */
3567 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3568 /** @sa SUPSemEventMultiWaitNsRelIntr */
3569 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3570 /** @sa SUPSemEventMultiGetResolution */
3571 DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3572 /** @} */
3573
3574 /**
3575 * Initializes a PDM critical section.
3576 *
3577 * The PDM critical sections are derived from the IPRT critical sections, but
3578 * works in RC and R0 as well.
3579 *
3580 * @returns VBox status code.
3581 * @param pDevIns The device instance.
3582 * @param pCritSect Pointer to the critical section.
3583 * @param SRC_POS Use RT_SRC_POS.
3584 * @param pszNameFmt Format string for naming the critical section.
3585 * For statistics and lock validation.
3586 * @param va Arguments for the format string.
3587 */
3588 DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3589 const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3590
3591 /**
3592 * Gets the NOP critical section.
3593 *
3594 * @returns The ring-3 address of the NOP critical section.
3595 * @param pDevIns The device instance.
3596 */
3597 DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3598
3599 /**
3600 * Gets the NOP critical section.
3601 *
3602 * @returns The ring-0 address of the NOP critical section.
3603 * @param pDevIns The device instance.
3604 * @deprecated
3605 */
3606 DECLR3CALLBACKMEMBER(R0PTRTYPE(PPDMCRITSECT), pfnCritSectGetNopR0,(PPDMDEVINS pDevIns));
3607
3608 /**
3609 * Gets the NOP critical section.
3610 *
3611 * @returns The raw-mode context address of the NOP critical section.
3612 * @param pDevIns The device instance.
3613 * @deprecated
3614 */
3615 DECLR3CALLBACKMEMBER(RCPTRTYPE(PPDMCRITSECT), pfnCritSectGetNopRC,(PPDMDEVINS pDevIns));
3616
3617 /**
3618 * Changes the device level critical section from the automatically created
3619 * default to one desired by the device constructor.
3620 *
3621 * For ring-0 and raw-mode capable devices, the call must be repeated in each of
3622 * the additional contexts.
3623 *
3624 * @returns VBox status code.
3625 * @param pDevIns The device instance.
3626 * @param pCritSect The critical section to use. NULL is not
3627 * valid, instead use the NOP critical
3628 * section.
3629 */
3630 DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3631
3632 /** @name Exported PDM Critical Section Functions
3633 * @{ */
3634 DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3635 DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3636 DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3637 DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3638 DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3639 DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3640 DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3641 DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3642 DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3643 DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3644 DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3645 DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3646 /** @} */
3647
3648 /**
3649 * Creates a PDM thread.
3650 *
3651 * This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3652 * resuming, and destroying the thread as the VM state changes.
3653 *
3654 * @returns VBox status code.
3655 * @param pDevIns The device instance.
3656 * @param ppThread Where to store the thread 'handle'.
3657 * @param pvUser The user argument to the thread function.
3658 * @param pfnThread The thread function.
3659 * @param pfnWakeup The wakup callback. This is called on the EMT
3660 * thread when a state change is pending.
3661 * @param cbStack See RTThreadCreate.
3662 * @param enmType See RTThreadCreate.
3663 * @param pszName See RTThreadCreate.
3664 * @remarks The device critical section will NOT be entered prior to invoking
3665 * the function pointers.
3666 */
3667 DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3668 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3669
3670 /** @name Exported PDM Thread Functions
3671 * @{ */
3672 DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3673 DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3674 DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3675 DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3676 DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3677 DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3678 /** @} */
3679
3680 /**
3681 * Set up asynchronous handling of a suspend, reset or power off notification.
3682 *
3683 * This shall only be called when getting the notification. It must be called
3684 * for each one.
3685 *
3686 * @returns VBox status code.
3687 * @param pDevIns The device instance.
3688 * @param pfnAsyncNotify The callback.
3689 * @thread EMT(0)
3690 * @remarks The caller will enter the device critical section prior to invoking
3691 * the callback.
3692 */
3693 DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3694
3695 /**
3696 * Notify EMT(0) that the device has completed the asynchronous notification
3697 * handling.
3698 *
3699 * This can be called at any time, spurious calls will simply be ignored.
3700 *
3701 * @param pDevIns The device instance.
3702 * @thread Any
3703 */
3704 DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
3705
3706 /**
3707 * Register the RTC device.
3708 *
3709 * @returns VBox status code.
3710 * @param pDevIns The device instance.
3711 * @param pRtcReg Pointer to a RTC registration structure.
3712 * @param ppRtcHlp Where to store the pointer to the helper
3713 * functions.
3714 */
3715 DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
3716
3717 /**
3718 * Register a PCI Bus.
3719 *
3720 * @returns VBox status code, but the positive values 0..31 are used to indicate
3721 * bus number rather than informational status codes.
3722 * @param pDevIns The device instance.
3723 * @param pPciBusReg Pointer to PCI bus registration structure.
3724 * @param ppPciHlp Where to store the pointer to the PCI Bus
3725 * helpers.
3726 * @param piBus Where to return the PDM bus number. Optional.
3727 */
3728 DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
3729 PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus));
3730
3731 /**
3732 * Register the IOMMU device.
3733 *
3734 * @returns VBox status code.
3735 * @param pDevIns The device instance.
3736 * @param pIommuReg Pointer to a IOMMU registration structure.
3737 * @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
3738 * helpers.
3739 * @param pidxIommu Where to return the IOMMU index. Optional.
3740 */
3741 DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
3742 uint32_t *pidxIommu));
3743
3744 /**
3745 * Register the PIC device.
3746 *
3747 * @returns VBox status code.
3748 * @param pDevIns The device instance.
3749 * @param pPicReg Pointer to a PIC registration structure.
3750 * @param ppPicHlp Where to store the pointer to the ring-3 PIC
3751 * helpers.
3752 * @sa PDMDevHlpPICSetUpContext
3753 */
3754 DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
3755
3756 /**
3757 * Register the APIC device.
3758 *
3759 * @returns VBox status code.
3760 * @param pDevIns The device instance.
3761 */
3762 DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
3763
3764 /**
3765 * Register the I/O APIC device.
3766 *
3767 * @returns VBox status code.
3768 * @param pDevIns The device instance.
3769 * @param pIoApicReg Pointer to a I/O APIC registration structure.
3770 * @param ppIoApicHlp Where to store the pointer to the IOAPIC
3771 * helpers.
3772 */
3773 DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
3774
3775 /**
3776 * Register the HPET device.
3777 *
3778 * @returns VBox status code.
3779 * @param pDevIns The device instance.
3780 * @param pHpetReg Pointer to a HPET registration structure.
3781 * @param ppHpetHlpR3 Where to store the pointer to the HPET
3782 * helpers.
3783 */
3784 DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
3785
3786 /**
3787 * Register a raw PCI device.
3788 *
3789 * @returns VBox status code.
3790 * @param pDevIns The device instance.
3791 * @param pPciRawReg Pointer to a raw PCI registration structure.
3792 * @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
3793 * device helpers.
3794 */
3795 DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
3796
3797 /**
3798 * Register the DMA device.
3799 *
3800 * @returns VBox status code.
3801 * @param pDevIns The device instance.
3802 * @param pDmacReg Pointer to a DMAC registration structure.
3803 * @param ppDmacHlp Where to store the pointer to the DMA helpers.
3804 */
3805 DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
3806
3807 /**
3808 * Register transfer function for DMA channel.
3809 *
3810 * @returns VBox status code.
3811 * @param pDevIns The device instance.
3812 * @param uChannel Channel number.
3813 * @param pfnTransferHandler Device specific transfer callback function.
3814 * @param pvUser User pointer to pass to the callback.
3815 * @thread EMT
3816 */
3817 DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
3818
3819 /**
3820 * Read memory.
3821 *
3822 * @returns VBox status code.
3823 * @param pDevIns The device instance.
3824 * @param uChannel Channel number.
3825 * @param pvBuffer Pointer to target buffer.
3826 * @param off DMA position.
3827 * @param cbBlock Block size.
3828 * @param pcbRead Where to store the number of bytes which was
3829 * read. optional.
3830 * @thread EMT
3831 */
3832 DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead));
3833
3834 /**
3835 * Write memory.
3836 *
3837 * @returns VBox status code.
3838 * @param pDevIns The device instance.
3839 * @param uChannel Channel number.
3840 * @param pvBuffer Memory to write.
3841 * @param off DMA position.
3842 * @param cbBlock Block size.
3843 * @param pcbWritten Where to store the number of bytes which was
3844 * written. optional.
3845 * @thread EMT
3846 */
3847 DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten));
3848
3849 /**
3850 * Set the DREQ line.
3851 *
3852 * @returns VBox status code.
3853 * @param pDevIns Device instance.
3854 * @param uChannel Channel number.
3855 * @param uLevel Level of the line.
3856 * @thread EMT
3857 */
3858 DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
3859
3860 /**
3861 * Get channel mode.
3862 *
3863 * @returns Channel mode. See specs.
3864 * @param pDevIns The device instance.
3865 * @param uChannel Channel number.
3866 * @thread EMT
3867 */
3868 DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
3869
3870 /**
3871 * Schedule DMA execution.
3872 *
3873 * @param pDevIns The device instance.
3874 * @thread Any thread.
3875 */
3876 DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
3877
3878 /**
3879 * Write CMOS value and update the checksum(s).
3880 *
3881 * @returns VBox status code.
3882 * @param pDevIns The device instance.
3883 * @param iReg The CMOS register index.
3884 * @param u8Value The CMOS register value.
3885 * @thread EMT
3886 */
3887 DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
3888
3889 /**
3890 * Read CMOS value.
3891 *
3892 * @returns VBox status code.
3893 * @param pDevIns The device instance.
3894 * @param iReg The CMOS register index.
3895 * @param pu8Value Where to store the CMOS register value.
3896 * @thread EMT
3897 */
3898 DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
3899
3900 /**
3901 * Assert that the current thread is the emulation thread.
3902 *
3903 * @returns True if correct.
3904 * @returns False if wrong.
3905 * @param pDevIns The device instance.
3906 * @param pszFile Filename of the assertion location.
3907 * @param iLine The linenumber of the assertion location.
3908 * @param pszFunction Function of the assertion location.
3909 */
3910 DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction));
3911
3912 /**
3913 * Assert that the current thread is NOT the emulation thread.
3914 *
3915 * @returns True if correct.
3916 * @returns False if wrong.
3917 * @param pDevIns The device instance.
3918 * @param pszFile Filename of the assertion location.
3919 * @param iLine The linenumber of the assertion location.
3920 * @param pszFunction Function of the assertion location.
3921 */
3922 DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction));
3923
3924 /**
3925 * Resolves the symbol for a raw-mode context interface.
3926 *
3927 * @returns VBox status code.
3928 * @param pDevIns The device instance.
3929 * @param pvInterface The interface structure.
3930 * @param cbInterface The size of the interface structure.
3931 * @param pszSymPrefix What to prefix the symbols in the list with
3932 * before resolving them. This must start with
3933 * 'dev' and contain the driver name.
3934 * @param pszSymList List of symbols corresponding to the interface.
3935 * There is generally a there is generally a define
3936 * holding this list associated with the interface
3937 * definition (INTERFACE_SYM_LIST). For more
3938 * details see PDMR3LdrGetInterfaceSymbols.
3939 * @thread EMT
3940 */
3941 DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
3942 const char *pszSymPrefix, const char *pszSymList));
3943
3944 /**
3945 * Resolves the symbol for a ring-0 context interface.
3946 *
3947 * @returns VBox status code.
3948 * @param pDevIns The device instance.
3949 * @param pvInterface The interface structure.
3950 * @param cbInterface The size of the interface structure.
3951 * @param pszSymPrefix What to prefix the symbols in the list with
3952 * before resolving them. This must start with
3953 * 'dev' and contain the driver name.
3954 * @param pszSymList List of symbols corresponding to the interface.
3955 * There is generally a there is generally a define
3956 * holding this list associated with the interface
3957 * definition (INTERFACE_SYM_LIST). For more
3958 * details see PDMR3LdrGetInterfaceSymbols.
3959 * @thread EMT
3960 */
3961 DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
3962 const char *pszSymPrefix, const char *pszSymList));
3963
3964 /**
3965 * Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
3966 *
3967 * @returns VBox status code.
3968 * @retval VERR_INVALID_FUNCTION if the callback member is NULL.
3969 * @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
3970 *
3971 * @param pDevIns The device instance.
3972 * @param uOperation The operation to perform.
3973 * @param u64Arg 64-bit integer argument.
3974 * @thread EMT
3975 */
3976 DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
3977
3978 /**
3979 * Gets the reason for the most recent VM suspend.
3980 *
3981 * @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
3982 * suspend has been made or if the pDevIns is invalid.
3983 * @param pDevIns The device instance.
3984 */
3985 DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
3986
3987 /**
3988 * Gets the reason for the most recent VM resume.
3989 *
3990 * @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
3991 * resume has been made or if the pDevIns is invalid.
3992 * @param pDevIns The device instance.
3993 */
3994 DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
3995
3996 /**
3997 * Requests the mapping of multiple guest page into ring-3.
3998 *
3999 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4000 * ASAP to release them.
4001 *
4002 * This API will assume your intention is to write to the pages, and will
4003 * therefore replace shared and zero pages. If you do not intend to modify the
4004 * pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4005 *
4006 * @returns VBox status code.
4007 * @retval VINF_SUCCESS on success.
4008 * @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4009 * backing or if any of the pages the page has any active access
4010 * handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4011 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4012 * an invalid physical address.
4013 *
4014 * @param pDevIns The device instance.
4015 * @param cPages Number of pages to lock.
4016 * @param paGCPhysPages The guest physical address of the pages that
4017 * should be mapped (@a cPages entries).
4018 * @param fFlags Flags reserved for future use, MBZ.
4019 * @param papvPages Where to store the ring-3 mapping addresses
4020 * corresponding to @a paGCPhysPages.
4021 * @param paLocks Where to store the locking information that
4022 * pfnPhysBulkReleasePageMappingLock needs (@a cPages
4023 * in length).
4024 *
4025 * @remark Avoid calling this API from within critical sections (other than the
4026 * PGM one) because of the deadlock risk when we have to delegating the
4027 * task to an EMT.
4028 * @thread Any.
4029 * @since 6.0.6
4030 */
4031 DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4032 uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4033
4034 /**
4035 * Requests the mapping of multiple guest page into ring-3, for reading only.
4036 *
4037 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4038 * ASAP to release them.
4039 *
4040 * @returns VBox status code.
4041 * @retval VINF_SUCCESS on success.
4042 * @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4043 * backing or if any of the pages the page has an active ALL access
4044 * handler. The caller must fall back on using PGMR3PhysWriteExternal.
4045 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4046 * an invalid physical address.
4047 *
4048 * @param pDevIns The device instance.
4049 * @param cPages Number of pages to lock.
4050 * @param paGCPhysPages The guest physical address of the pages that
4051 * should be mapped (@a cPages entries).
4052 * @param fFlags Flags reserved for future use, MBZ.
4053 * @param papvPages Where to store the ring-3 mapping addresses
4054 * corresponding to @a paGCPhysPages.
4055 * @param paLocks Where to store the lock information that
4056 * pfnPhysReleasePageMappingLock needs (@a cPages
4057 * in length).
4058 *
4059 * @remark Avoid calling this API from within critical sections.
4060 * @thread Any.
4061 * @since 6.0.6
4062 */
4063 DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4064 uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4065
4066 /**
4067 * Release the mappings of multiple guest pages.
4068 *
4069 * This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4070 * pfnPhysBulkGCPhys2CCPtrReadOnly.
4071 *
4072 * @param pDevIns The device instance.
4073 * @param cPages Number of pages to unlock.
4074 * @param paLocks The lock structures initialized by the mapping
4075 * function (@a cPages in length).
4076 * @thread Any.
4077 * @since 6.0.6
4078 */
4079 DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4080
4081 /**
4082 * Returns the micro architecture used for the guest.
4083 *
4084 * @returns CPU micro architecture enum.
4085 * @param pDevIns The device instance.
4086 */
4087 DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4088
4089 /** Space reserved for future members.
4090 * @{ */
4091 DECLR3CALLBACKMEMBER(void, pfnReserved1,(void));
4092 DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4093 DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4094 DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4095 DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4096 DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4097 DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4098 DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4099 DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4100 DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4101 /** @} */
4102
4103
4104 /** API available to trusted devices only.
4105 *
4106 * These APIs are providing unrestricted access to the guest and the VM,
4107 * or they are interacting intimately with PDM.
4108 *
4109 * @{
4110 */
4111
4112 /**
4113 * Gets the user mode VM handle. Restricted API.
4114 *
4115 * @returns User mode VM Handle.
4116 * @param pDevIns The device instance.
4117 */
4118 DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4119
4120 /**
4121 * Gets the global VM handle. Restricted API.
4122 *
4123 * @returns VM Handle.
4124 * @param pDevIns The device instance.
4125 */
4126 DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4127
4128 /**
4129 * Gets the VMCPU handle. Restricted API.
4130 *
4131 * @returns VMCPU Handle.
4132 * @param pDevIns The device instance.
4133 */
4134 DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4135
4136 /**
4137 * The the VM CPU ID of the current thread (restricted API).
4138 *
4139 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4140 * @param pDevIns The device instance.
4141 */
4142 DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4143
4144 /**
4145 * Registers the VMM device heap or notifies about mapping/unmapping.
4146 *
4147 * This interface serves three purposes:
4148 *
4149 * -# Register the VMM device heap during device construction
4150 * for the HM to use.
4151 * -# Notify PDM/HM that it's mapped into guest address
4152 * space (i.e. usable).
4153 * -# Notify PDM/HM that it is being unmapped from the guest
4154 * address space (i.e. not usable).
4155 *
4156 * @returns VBox status code.
4157 * @param pDevIns The device instance.
4158 * @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4159 * not mapped.
4160 * @param pvHeap Ring 3 heap pointer.
4161 * @param cbHeap Size of the heap.
4162 * @thread EMT.
4163 */
4164 DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4165
4166 /**
4167 * Registers the firmware (BIOS, EFI) device with PDM.
4168 *
4169 * The firmware provides a callback table and gets a special PDM helper table.
4170 * There can only be one firmware device for a VM.
4171 *
4172 * @returns VBox status code.
4173 * @param pDevIns The device instance.
4174 * @param pFwReg Firmware registration structure.
4175 * @param ppFwHlp Where to return the firmware helper structure.
4176 * @remarks Only valid during device construction.
4177 * @thread EMT(0)
4178 */
4179 DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4180
4181 /**
4182 * Resets the VM.
4183 *
4184 * @returns The appropriate VBox status code to pass around on reset.
4185 * @param pDevIns The device instance.
4186 * @param fFlags PDMVMRESET_F_XXX flags.
4187 * @thread The emulation thread.
4188 */
4189 DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4190
4191 /**
4192 * Suspends the VM.
4193 *
4194 * @returns The appropriate VBox status code to pass around on suspend.
4195 * @param pDevIns The device instance.
4196 * @thread The emulation thread.
4197 */
4198 DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4199
4200 /**
4201 * Suspends, saves and powers off the VM.
4202 *
4203 * @returns The appropriate VBox status code to pass around.
4204 * @param pDevIns The device instance.
4205 * @thread An emulation thread.
4206 */
4207 DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4208
4209 /**
4210 * Power off the VM.
4211 *
4212 * @returns The appropriate VBox status code to pass around on power off.
4213 * @param pDevIns The device instance.
4214 * @thread The emulation thread.
4215 */
4216 DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4217
4218 /**
4219 * Checks if the Gate A20 is enabled or not.
4220 *
4221 * @returns true if A20 is enabled.
4222 * @returns false if A20 is disabled.
4223 * @param pDevIns The device instance.
4224 * @thread The emulation thread.
4225 */
4226 DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4227
4228 /**
4229 * Enables or disables the Gate A20.
4230 *
4231 * @param pDevIns The device instance.
4232 * @param fEnable Set this flag to enable the Gate A20; clear it
4233 * to disable.
4234 * @thread The emulation thread.
4235 */
4236 DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4237
4238 /**
4239 * Get the specified CPUID leaf for the virtual CPU associated with the calling
4240 * thread.
4241 *
4242 * @param pDevIns The device instance.
4243 * @param iLeaf The CPUID leaf to get.
4244 * @param pEax Where to store the EAX value.
4245 * @param pEbx Where to store the EBX value.
4246 * @param pEcx Where to store the ECX value.
4247 * @param pEdx Where to store the EDX value.
4248 * @thread EMT.
4249 */
4250 DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx));
4251
4252 /**
4253 * Get the current virtual clock time in a VM. The clock frequency must be
4254 * queried separately.
4255 *
4256 * @returns Current clock time.
4257 * @param pDevIns The device instance.
4258 */
4259 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4260
4261 /**
4262 * Get the frequency of the virtual clock.
4263 *
4264 * @returns The clock frequency (not variable at run-time).
4265 * @param pDevIns The device instance.
4266 */
4267 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4268
4269 /**
4270 * Get the current virtual clock time in a VM, in nanoseconds.
4271 *
4272 * @returns Current clock time (in ns).
4273 * @param pDevIns The device instance.
4274 */
4275 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4276
4277 /**
4278 * Gets the support driver session.
4279 *
4280 * This is intended for working with the semaphore API.
4281 *
4282 * @returns Support driver session handle.
4283 * @param pDevIns The device instance.
4284 */
4285 DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4286
4287 /**
4288 * Queries a generic object from the VMM user.
4289 *
4290 * @returns Pointer to the object if found, NULL if not.
4291 * @param pDevIns The device instance.
4292 * @param pUuid The UUID of what's being queried. The UUIDs and
4293 * the usage conventions are defined by the user.
4294 *
4295 * @note It is strictly forbidden to call this internally in VBox! This
4296 * interface is exclusively for hacks in externally developed devices.
4297 */
4298 DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4299
4300 /**
4301 * Register a physical page access handler type.
4302 *
4303 * @returns VBox status code.
4304 * @param pDevIns The device instance.
4305 * @param enmKind The kind of access handler.
4306 * @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4307 * @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4308 * handler should be called.
4309 * @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4310 * ring-3 handler should be called.
4311 * @param pszHandlerRC The name of the raw-mode context handler, NULL if
4312 * the ring-3 handler should be called.
4313 * @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4314 * if the ring-3 handler should be called.
4315 * @param pszDesc The type description.
4316 * @param phType Where to return the type handle (cross context
4317 * safe).
4318 */
4319 DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4320 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4321 const char *pszHandlerR0, const char *pszPfHandlerR0,
4322 const char *pszHandlerRC, const char *pszPfHandlerRC,
4323 const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4324
4325 /** @} */
4326
4327 /** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4328 uint32_t u32TheEnd;
4329} PDMDEVHLPR3;
4330#endif /* !IN_RING3 || DOXYGEN_RUNNING */
4331/** Pointer to the R3 PDM Device API. */
4332typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4333/** Pointer to the R3 PDM Device API, const variant. */
4334typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4335
4336
4337/**
4338 * PDM Device API - RC Variant.
4339 */
4340typedef struct PDMDEVHLPRC
4341{
4342 /** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4343 uint32_t u32Version;
4344
4345 /**
4346 * Sets up raw-mode context callback handlers for an I/O port range.
4347 *
4348 * The range must have been registered in ring-3 first using
4349 * PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4350 *
4351 * @returns VBox status.
4352 * @param pDevIns The device instance to register the ports with.
4353 * @param hIoPorts The I/O port range handle.
4354 * @param pfnOut Pointer to function which is gonna handle OUT
4355 * operations. Optional.
4356 * @param pfnIn Pointer to function which is gonna handle IN operations.
4357 * Optional.
4358 * @param pfnOutStr Pointer to function which is gonna handle string OUT
4359 * operations. Optional.
4360 * @param pfnInStr Pointer to function which is gonna handle string IN
4361 * operations. Optional.
4362 * @param pvUser User argument to pass to the callbacks.
4363 *
4364 * @remarks Caller enters the device critical section prior to invoking the
4365 * registered callback methods.
4366 *
4367 * @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4368 * PDMDevHlpIoPortUnmap.
4369 */
4370 DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4371 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4372 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4373 void *pvUser));
4374
4375 /**
4376 * Sets up raw-mode context callback handlers for an MMIO region.
4377 *
4378 * The region must have been registered in ring-3 first using
4379 * PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4380 *
4381 * @returns VBox status.
4382 * @param pDevIns The device instance to register the ports with.
4383 * @param hRegion The MMIO region handle.
4384 * @param pfnWrite Pointer to function which is gonna handle Write
4385 * operations.
4386 * @param pfnRead Pointer to function which is gonna handle Read
4387 * operations.
4388 * @param pfnFill Pointer to function which is gonna handle Fill/memset
4389 * operations. (optional)
4390 * @param pvUser User argument to pass to the callbacks.
4391 *
4392 * @remarks Caller enters the device critical section prior to invoking the
4393 * registered callback methods.
4394 *
4395 * @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4396 * PDMDevHlpMmioUnmap.
4397 */
4398 DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4399 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4400
4401 /**
4402 * Sets up a raw-mode mapping for an MMIO2 region.
4403 *
4404 * The region must have been created in ring-3 first using
4405 * PDMDevHlpMmio2Create().
4406 *
4407 * @returns VBox status.
4408 * @param pDevIns The device instance to register the ports with.
4409 * @param hRegion The MMIO2 region handle.
4410 * @param offSub Start of what to map into raw-mode. Must be page aligned.
4411 * @param cbSub Number of bytes to map into raw-mode. Must be page
4412 * aligned. Zero is an alias for everything.
4413 * @param ppvMapping Where to return the mapping corresponding to @a offSub.
4414 * @thread EMT(0)
4415 * @note Only available at VM creation time.
4416 *
4417 * @sa PDMDevHlpMmio2Create().
4418 */
4419 DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4420 size_t offSub, size_t cbSub, void **ppvMapping));
4421
4422 /**
4423 * Bus master physical memory read from the given PCI device.
4424 *
4425 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4426 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
4427 * @param pDevIns The device instance.
4428 * @param pPciDev The PCI device structure. If NULL the default
4429 * PCI device for this device instance is used.
4430 * @param GCPhys Physical address start reading from.
4431 * @param pvBuf Where to put the read bits.
4432 * @param cbRead How many bytes to read.
4433 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4434 * @thread Any thread, but the call may involve the emulation thread.
4435 */
4436 DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4437 void *pvBuf, size_t cbRead, uint32_t fFlags));
4438
4439 /**
4440 * Bus master physical memory write from the given PCI device.
4441 *
4442 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4443 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
4444 * @param pDevIns The device instance.
4445 * @param pPciDev The PCI device structure. If NULL the default
4446 * PCI device for this device instance is used.
4447 * @param GCPhys Physical address to write to.
4448 * @param pvBuf What to write.
4449 * @param cbWrite How many bytes to write.
4450 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4451 * @thread Any thread, but the call may involve the emulation thread.
4452 */
4453 DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4454 const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4455
4456 /**
4457 * Set the IRQ for the given PCI device.
4458 *
4459 * @param pDevIns Device instance.
4460 * @param pPciDev The PCI device structure. If NULL the default
4461 * PCI device for this device instance is used.
4462 * @param iIrq IRQ number to set.
4463 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4464 * @thread Any thread, but will involve the emulation thread.
4465 */
4466 DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4467
4468 /**
4469 * Set ISA IRQ for a device.
4470 *
4471 * @param pDevIns Device instance.
4472 * @param iIrq IRQ number to set.
4473 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4474 * @thread Any thread, but will involve the emulation thread.
4475 */
4476 DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4477
4478 /**
4479 * Read physical memory.
4480 *
4481 * @returns VINF_SUCCESS (for now).
4482 * @param pDevIns Device instance.
4483 * @param GCPhys Physical address start reading from.
4484 * @param pvBuf Where to put the read bits.
4485 * @param cbRead How many bytes to read.
4486 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4487 */
4488 DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
4489
4490 /**
4491 * Write to physical memory.
4492 *
4493 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4494 * @param pDevIns Device instance.
4495 * @param GCPhys Physical address to write to.
4496 * @param pvBuf What to write.
4497 * @param cbWrite How many bytes to write.
4498 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4499 */
4500 DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4501
4502 /**
4503 * Checks if the Gate A20 is enabled or not.
4504 *
4505 * @returns true if A20 is enabled.
4506 * @returns false if A20 is disabled.
4507 * @param pDevIns Device instance.
4508 * @thread The emulation thread.
4509 */
4510 DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4511
4512 /**
4513 * Gets the VM state.
4514 *
4515 * @returns VM state.
4516 * @param pDevIns The device instance.
4517 * @thread Any thread (just keep in mind that it's volatile info).
4518 */
4519 DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4520
4521 /**
4522 * Set the VM error message
4523 *
4524 * @returns rc.
4525 * @param pDevIns Driver instance.
4526 * @param rc VBox status code.
4527 * @param SRC_POS Use RT_SRC_POS.
4528 * @param pszFormat Error message format string.
4529 * @param ... Error message arguments.
4530 */
4531 DECLRCCALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4532 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4533
4534 /**
4535 * Set the VM error message
4536 *
4537 * @returns rc.
4538 * @param pDevIns Driver instance.
4539 * @param rc VBox status code.
4540 * @param SRC_POS Use RT_SRC_POS.
4541 * @param pszFormat Error message format string.
4542 * @param va Error message arguments.
4543 */
4544 DECLRCCALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4545 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4546
4547 /**
4548 * Set the VM runtime error message
4549 *
4550 * @returns VBox status code.
4551 * @param pDevIns Device instance.
4552 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4553 * @param pszErrorId Error ID string.
4554 * @param pszFormat Error message format string.
4555 * @param ... Error message arguments.
4556 */
4557 DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4558 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4559
4560 /**
4561 * Set the VM runtime error message
4562 *
4563 * @returns VBox status code.
4564 * @param pDevIns Device instance.
4565 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4566 * @param pszErrorId Error ID string.
4567 * @param pszFormat Error message format string.
4568 * @param va Error message arguments.
4569 */
4570 DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4571 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
4572
4573 /**
4574 * Gets the VM handle. Restricted API.
4575 *
4576 * @returns VM Handle.
4577 * @param pDevIns Device instance.
4578 */
4579 DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4580
4581 /**
4582 * Gets the VMCPU handle. Restricted API.
4583 *
4584 * @returns VMCPU Handle.
4585 * @param pDevIns The device instance.
4586 */
4587 DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4588
4589 /**
4590 * The the VM CPU ID of the current thread (restricted API).
4591 *
4592 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4593 * @param pDevIns The device instance.
4594 */
4595 DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4596
4597 /**
4598 * Get the current virtual clock time in a VM. The clock frequency must be
4599 * queried separately.
4600 *
4601 * @returns Current clock time.
4602 * @param pDevIns The device instance.
4603 */
4604 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4605
4606 /**
4607 * Get the frequency of the virtual clock.
4608 *
4609 * @returns The clock frequency (not variable at run-time).
4610 * @param pDevIns The device instance.
4611 */
4612 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4613
4614 /**
4615 * Get the current virtual clock time in a VM, in nanoseconds.
4616 *
4617 * @returns Current clock time (in ns).
4618 * @param pDevIns The device instance.
4619 */
4620 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4621
4622 /**
4623 * Gets the NOP critical section.
4624 *
4625 * @returns The ring-3 address of the NOP critical section.
4626 * @param pDevIns The device instance.
4627 */
4628 DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4629
4630 /**
4631 * Changes the device level critical section from the automatically created
4632 * default to one desired by the device constructor.
4633 *
4634 * Must first be done in ring-3.
4635 *
4636 * @returns VBox status code.
4637 * @param pDevIns The device instance.
4638 * @param pCritSect The critical section to use. NULL is not
4639 * valid, instead use the NOP critical
4640 * section.
4641 */
4642 DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4643
4644 /** @name Exported PDM Critical Section Functions
4645 * @{ */
4646 DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4647 DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4648 DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4649 DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4650 DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4651 DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4652 DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4653 DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4654 DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4655 /** @} */
4656
4657 /**
4658 * Gets the trace buffer handle.
4659 *
4660 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4661 * really inteded for direct usage, thus no inline wrapper function.
4662 *
4663 * @returns Trace buffer handle or NIL_RTTRACEBUF.
4664 * @param pDevIns The device instance.
4665 */
4666 DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4667
4668 /**
4669 * Sets up the PCI bus for the raw-mode context.
4670 *
4671 * This must be called after ring-3 has registered the PCI bus using
4672 * PDMDevHlpPCIBusRegister().
4673 *
4674 * @returns VBox status code.
4675 * @param pDevIns The device instance.
4676 * @param pPciBusReg The PCI bus registration information for raw-mode,
4677 * considered volatile.
4678 * @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4679 */
4680 DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4681
4682 /**
4683 * Sets up the IOMMU for the raw-mode context.
4684 *
4685 * This must be called after ring-3 has registered the IOMMU using
4686 * PDMDevHlpIommuRegister().
4687 *
4688 * @returns VBox status code.
4689 * @param pDevIns The device instance.
4690 * @param pIommuReg The IOMMU registration information for raw-mode,
4691 * considered volatile.
4692 * @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
4693 */
4694 DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
4695
4696 /**
4697 * Sets up the PIC for the ring-0 context.
4698 *
4699 * This must be called after ring-3 has registered the PIC using
4700 * PDMDevHlpPICRegister().
4701 *
4702 * @returns VBox status code.
4703 * @param pDevIns The device instance.
4704 * @param pPicReg The PIC registration information for ring-0,
4705 * considered volatile and copied.
4706 * @param ppPicHlp Where to return the ring-0 PIC helpers.
4707 */
4708 DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4709
4710 /**
4711 * Sets up the APIC for the raw-mode context.
4712 *
4713 * This must be called after ring-3 has registered the APIC using
4714 * PDMDevHlpApicRegister().
4715 *
4716 * @returns VBox status code.
4717 * @param pDevIns The device instance.
4718 */
4719 DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
4720
4721 /**
4722 * Sets up the IOAPIC for the ring-0 context.
4723 *
4724 * This must be called after ring-3 has registered the PIC using
4725 * PDMDevHlpIoApicRegister().
4726 *
4727 * @returns VBox status code.
4728 * @param pDevIns The device instance.
4729 * @param pIoApicReg The PIC registration information for ring-0,
4730 * considered volatile and copied.
4731 * @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
4732 */
4733 DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4734
4735 /**
4736 * Sets up the HPET for the raw-mode context.
4737 *
4738 * This must be called after ring-3 has registered the PIC using
4739 * PDMDevHlpHpetRegister().
4740 *
4741 * @returns VBox status code.
4742 * @param pDevIns The device instance.
4743 * @param pHpetReg The PIC registration information for raw-mode,
4744 * considered volatile and copied.
4745 * @param ppHpetHlp Where to return the raw-mode HPET helpers.
4746 */
4747 DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
4748
4749 /** Space reserved for future members.
4750 * @{ */
4751 DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
4752 DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
4753 DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
4754 DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
4755 DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
4756 DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
4757 DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
4758 DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
4759 DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
4760 DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
4761 /** @} */
4762
4763 /** Just a safety precaution. */
4764 uint32_t u32TheEnd;
4765} PDMDEVHLPRC;
4766/** Pointer PDM Device RC API. */
4767typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
4768/** Pointer PDM Device RC API. */
4769typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
4770
4771/** Current PDMDEVHLP version number. */
4772#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 16, 0)
4773
4774
4775/**
4776 * PDM Device API - R0 Variant.
4777 */
4778typedef struct PDMDEVHLPR0
4779{
4780 /** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
4781 uint32_t u32Version;
4782
4783 /**
4784 * Sets up ring-0 callback handlers for an I/O port range.
4785 *
4786 * The range must have been created in ring-3 first using
4787 * PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4788 *
4789 * @returns VBox status.
4790 * @param pDevIns The device instance to register the ports with.
4791 * @param hIoPorts The I/O port range handle.
4792 * @param pfnOut Pointer to function which is gonna handle OUT
4793 * operations. Optional.
4794 * @param pfnIn Pointer to function which is gonna handle IN operations.
4795 * Optional.
4796 * @param pfnOutStr Pointer to function which is gonna handle string OUT
4797 * operations. Optional.
4798 * @param pfnInStr Pointer to function which is gonna handle string IN
4799 * operations. Optional.
4800 * @param pvUser User argument to pass to the callbacks.
4801 *
4802 * @remarks Caller enters the device critical section prior to invoking the
4803 * registered callback methods.
4804 *
4805 * @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
4806 * PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
4807 */
4808 DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4809 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4810 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4811 void *pvUser));
4812
4813 /**
4814 * Sets up ring-0 callback handlers for an MMIO region.
4815 *
4816 * The region must have been created in ring-3 first using
4817 * PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
4818 * PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
4819 *
4820 * @returns VBox status.
4821 * @param pDevIns The device instance to register the ports with.
4822 * @param hRegion The MMIO region handle.
4823 * @param pfnWrite Pointer to function which is gonna handle Write
4824 * operations.
4825 * @param pfnRead Pointer to function which is gonna handle Read
4826 * operations.
4827 * @param pfnFill Pointer to function which is gonna handle Fill/memset
4828 * operations. (optional)
4829 * @param pvUser User argument to pass to the callbacks.
4830 *
4831 * @remarks Caller enters the device critical section prior to invoking the
4832 * registered callback methods.
4833 *
4834 * @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
4835 * PDMDevHlpMmioUnmap().
4836 */
4837 DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4838 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4839
4840 /**
4841 * Sets up a ring-0 mapping for an MMIO2 region.
4842 *
4843 * The region must have been created in ring-3 first using
4844 * PDMDevHlpMmio2Create().
4845 *
4846 * @returns VBox status.
4847 * @param pDevIns The device instance to register the ports with.
4848 * @param hRegion The MMIO2 region handle.
4849 * @param offSub Start of what to map into ring-0. Must be page aligned.
4850 * @param cbSub Number of bytes to map into ring-0. Must be page
4851 * aligned. Zero is an alias for everything.
4852 * @param ppvMapping Where to return the mapping corresponding to @a offSub.
4853 *
4854 * @thread EMT(0)
4855 * @note Only available at VM creation time.
4856 *
4857 * @sa PDMDevHlpMmio2Create().
4858 */
4859 DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
4860 void **ppvMapping));
4861
4862 /**
4863 * Bus master physical memory read from the given PCI device.
4864 *
4865 * @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
4866 * VERR_EM_MEMORY.
4867 * @param pDevIns The device instance.
4868 * @param pPciDev The PCI device structure. If NULL the default
4869 * PCI device for this device instance is used.
4870 * @param GCPhys Physical address start reading from.
4871 * @param pvBuf Where to put the read bits.
4872 * @param cbRead How many bytes to read.
4873 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4874 * @thread Any thread, but the call may involve the emulation thread.
4875 */
4876 DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4877 void *pvBuf, size_t cbRead, uint32_t fFlags));
4878
4879 /**
4880 * Bus master physical memory write from the given PCI device.
4881 *
4882 * @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
4883 * VERR_EM_MEMORY.
4884 * @param pDevIns The device instance.
4885 * @param pPciDev The PCI device structure. If NULL the default
4886 * PCI device for this device instance is used.
4887 * @param GCPhys Physical address to write to.
4888 * @param pvBuf What to write.
4889 * @param cbWrite How many bytes to write.
4890 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4891 * @thread Any thread, but the call may involve the emulation thread.
4892 */
4893 DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4894 const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4895
4896 /**
4897 * Set the IRQ for the given PCI device.
4898 *
4899 * @param pDevIns Device instance.
4900 * @param pPciDev The PCI device structure. If NULL the default
4901 * PCI device for this device instance is used.
4902 * @param iIrq IRQ number to set.
4903 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4904 * @thread Any thread, but will involve the emulation thread.
4905 */
4906 DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4907
4908 /**
4909 * Set ISA IRQ for a device.
4910 *
4911 * @param pDevIns Device instance.
4912 * @param iIrq IRQ number to set.
4913 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4914 * @thread Any thread, but will involve the emulation thread.
4915 */
4916 DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4917
4918 /**
4919 * Read physical memory.
4920 *
4921 * @returns VINF_SUCCESS (for now).
4922 * @param pDevIns Device instance.
4923 * @param GCPhys Physical address start reading from.
4924 * @param pvBuf Where to put the read bits.
4925 * @param cbRead How many bytes to read.
4926 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4927 */
4928 DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
4929
4930 /**
4931 * Write to physical memory.
4932 *
4933 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4934 * @param pDevIns Device instance.
4935 * @param GCPhys Physical address to write to.
4936 * @param pvBuf What to write.
4937 * @param cbWrite How many bytes to write.
4938 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4939 */
4940 DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4941
4942 /**
4943 * Checks if the Gate A20 is enabled or not.
4944 *
4945 * @returns true if A20 is enabled.
4946 * @returns false if A20 is disabled.
4947 * @param pDevIns Device instance.
4948 * @thread The emulation thread.
4949 */
4950 DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4951
4952 /**
4953 * Gets the VM state.
4954 *
4955 * @returns VM state.
4956 * @param pDevIns The device instance.
4957 * @thread Any thread (just keep in mind that it's volatile info).
4958 */
4959 DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4960
4961 /**
4962 * Set the VM error message
4963 *
4964 * @returns rc.
4965 * @param pDevIns Driver instance.
4966 * @param rc VBox status code.
4967 * @param SRC_POS Use RT_SRC_POS.
4968 * @param pszFormat Error message format string.
4969 * @param ... Error message arguments.
4970 */
4971 DECLR0CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4972 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4973
4974 /**
4975 * Set the VM error message
4976 *
4977 * @returns rc.
4978 * @param pDevIns Driver instance.
4979 * @param rc VBox status code.
4980 * @param SRC_POS Use RT_SRC_POS.
4981 * @param pszFormat Error message format string.
4982 * @param va Error message arguments.
4983 */
4984 DECLR0CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4985 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4986
4987 /**
4988 * Set the VM runtime error message
4989 *
4990 * @returns VBox status code.
4991 * @param pDevIns Device instance.
4992 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4993 * @param pszErrorId Error ID string.
4994 * @param pszFormat Error message format string.
4995 * @param ... Error message arguments.
4996 */
4997 DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4998 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4999
5000 /**
5001 * Set the VM runtime error message
5002 *
5003 * @returns VBox status code.
5004 * @param pDevIns Device instance.
5005 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5006 * @param pszErrorId Error ID string.
5007 * @param pszFormat Error message format string.
5008 * @param va Error message arguments.
5009 */
5010 DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5011 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
5012
5013 /**
5014 * Gets the VM handle. Restricted API.
5015 *
5016 * @returns VM Handle.
5017 * @param pDevIns Device instance.
5018 */
5019 DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5020
5021 /**
5022 * Gets the VMCPU handle. Restricted API.
5023 *
5024 * @returns VMCPU Handle.
5025 * @param pDevIns The device instance.
5026 */
5027 DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5028
5029 /**
5030 * The the VM CPU ID of the current thread (restricted API).
5031 *
5032 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5033 * @param pDevIns The device instance.
5034 */
5035 DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5036
5037 /**
5038 * Translates a timer handle to a pointer.
5039 *
5040 * @returns The time address.
5041 * @param pDevIns The device instance.
5042 * @param hTimer The timer handle.
5043 */
5044 DECLR0CALLBACKMEMBER(PTMTIMERR0, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5045
5046 /** @name Timer handle method wrappers
5047 * @{ */
5048 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5049 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5050 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5051 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5052 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5053 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5054 DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5055 DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5056 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5057 /** Takes the clock lock then enters the specified critical section. */
5058 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5059 DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5060 DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5061 DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5062 DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5063 DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5064 DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5065 DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5066 DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5067 DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5068 /** @} */
5069
5070 /**
5071 * Get the current virtual clock time in a VM. The clock frequency must be
5072 * queried separately.
5073 *
5074 * @returns Current clock time.
5075 * @param pDevIns The device instance.
5076 */
5077 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5078
5079 /**
5080 * Get the frequency of the virtual clock.
5081 *
5082 * @returns The clock frequency (not variable at run-time).
5083 * @param pDevIns The device instance.
5084 */
5085 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5086
5087 /**
5088 * Get the current virtual clock time in a VM, in nanoseconds.
5089 *
5090 * @returns Current clock time (in ns).
5091 * @param pDevIns The device instance.
5092 */
5093 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5094
5095 /** @name Exported PDM Queue Functions
5096 * @{ */
5097 DECLR0CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5098 DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5099 DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5100 DECLR0CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
5101 DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5102 /** @} */
5103
5104 /** @name PDM Task
5105 * @{ */
5106 /**
5107 * Triggers the running the given task.
5108 *
5109 * @returns VBox status code.
5110 * @retval VINF_ALREADY_POSTED is the task is already pending.
5111 * @param pDevIns The device instance.
5112 * @param hTask The task to trigger.
5113 * @thread Any thread.
5114 */
5115 DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5116 /** @} */
5117
5118 /** @name SUP Event Semaphore Wrappers (single release / auto reset)
5119 * These semaphores can be signalled from ring-0.
5120 * @{ */
5121 /** @sa SUPSemEventSignal */
5122 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5123 /** @sa SUPSemEventWaitNoResume */
5124 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5125 /** @sa SUPSemEventWaitNsAbsIntr */
5126 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5127 /** @sa SUPSemEventWaitNsRelIntr */
5128 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5129 /** @sa SUPSemEventGetResolution */
5130 DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5131 /** @} */
5132
5133 /** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5134 * These semaphores can be signalled from ring-0.
5135 * @{ */
5136 /** @sa SUPSemEventMultiSignal */
5137 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5138 /** @sa SUPSemEventMultiReset */
5139 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5140 /** @sa SUPSemEventMultiWaitNoResume */
5141 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5142 /** @sa SUPSemEventMultiWaitNsAbsIntr */
5143 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5144 /** @sa SUPSemEventMultiWaitNsRelIntr */
5145 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5146 /** @sa SUPSemEventMultiGetResolution */
5147 DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5148 /** @} */
5149
5150 /**
5151 * Gets the NOP critical section.
5152 *
5153 * @returns The ring-3 address of the NOP critical section.
5154 * @param pDevIns The device instance.
5155 */
5156 DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5157
5158 /**
5159 * Changes the device level critical section from the automatically created
5160 * default to one desired by the device constructor.
5161 *
5162 * Must first be done in ring-3.
5163 *
5164 * @returns VBox status code.
5165 * @param pDevIns The device instance.
5166 * @param pCritSect The critical section to use. NULL is not
5167 * valid, instead use the NOP critical
5168 * section.
5169 */
5170 DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5171
5172 /** @name Exported PDM Critical Section Functions
5173 * @{ */
5174 DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5175 DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5176 DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5177 DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5178 DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5179 DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5180 DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5181 DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5182 DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5183 DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5184 /** @} */
5185
5186 /**
5187 * Gets the trace buffer handle.
5188 *
5189 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5190 * really inteded for direct usage, thus no inline wrapper function.
5191 *
5192 * @returns Trace buffer handle or NIL_RTTRACEBUF.
5193 * @param pDevIns The device instance.
5194 */
5195 DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5196
5197 /**
5198 * Sets up the PCI bus for the ring-0 context.
5199 *
5200 * This must be called after ring-3 has registered the PCI bus using
5201 * PDMDevHlpPCIBusRegister().
5202 *
5203 * @returns VBox status code.
5204 * @param pDevIns The device instance.
5205 * @param pPciBusReg The PCI bus registration information for ring-0,
5206 * considered volatile and copied.
5207 * @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5208 */
5209 DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5210
5211 /**
5212 * Sets up the IOMMU for the ring-0 context.
5213 *
5214 * This must be called after ring-3 has registered the IOMMU using
5215 * PDMDevHlpIommuRegister().
5216 *
5217 * @returns VBox status code.
5218 * @param pDevIns The device instance.
5219 * @param pIommuReg The IOMMU registration information for ring-0,
5220 * considered volatile and copied.
5221 * @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5222 */
5223 DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5224
5225 /**
5226 * Sets up the PIC for the ring-0 context.
5227 *
5228 * This must be called after ring-3 has registered the PIC using
5229 * PDMDevHlpPICRegister().
5230 *
5231 * @returns VBox status code.
5232 * @param pDevIns The device instance.
5233 * @param pPicReg The PIC registration information for ring-0,
5234 * considered volatile and copied.
5235 * @param ppPicHlp Where to return the ring-0 PIC helpers.
5236 */
5237 DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5238
5239 /**
5240 * Sets up the APIC for the ring-0 context.
5241 *
5242 * This must be called after ring-3 has registered the APIC using
5243 * PDMDevHlpApicRegister().
5244 *
5245 * @returns VBox status code.
5246 * @param pDevIns The device instance.
5247 */
5248 DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5249
5250 /**
5251 * Sets up the IOAPIC for the ring-0 context.
5252 *
5253 * This must be called after ring-3 has registered the PIC using
5254 * PDMDevHlpIoApicRegister().
5255 *
5256 * @returns VBox status code.
5257 * @param pDevIns The device instance.
5258 * @param pIoApicReg The PIC registration information for ring-0,
5259 * considered volatile and copied.
5260 * @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5261 */
5262 DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5263
5264 /**
5265 * Sets up the HPET for the ring-0 context.
5266 *
5267 * This must be called after ring-3 has registered the PIC using
5268 * PDMDevHlpHpetRegister().
5269 *
5270 * @returns VBox status code.
5271 * @param pDevIns The device instance.
5272 * @param pHpetReg The PIC registration information for ring-0,
5273 * considered volatile and copied.
5274 * @param ppHpetHlp Where to return the ring-0 HPET helpers.
5275 */
5276 DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5277
5278 /** Space reserved for future members.
5279 * @{ */
5280 DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5281 DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5282 DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5283 DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5284 DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5285 DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5286 DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5287 DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5288 DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5289 DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5290 /** @} */
5291
5292 /** Just a safety precaution. */
5293 uint32_t u32TheEnd;
5294} PDMDEVHLPR0;
5295/** Pointer PDM Device R0 API. */
5296typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5297/** Pointer PDM Device GC API. */
5298typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5299
5300/** Current PDMDEVHLP version number. */
5301#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 18, 0)
5302
5303
5304/**
5305 * PDM Device Instance.
5306 */
5307typedef struct PDMDEVINSR3
5308{
5309 /** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5310 uint32_t u32Version;
5311 /** Device instance number. */
5312 uint32_t iInstance;
5313 /** Size of the ring-3, raw-mode and shared bits. */
5314 uint32_t cbRing3;
5315 /** Set if ring-0 context is enabled. */
5316 bool fR0Enabled;
5317 /** Set if raw-mode context is enabled. */
5318 bool fRCEnabled;
5319 /** Alignment padding. */
5320 bool afReserved[2];
5321 /** Pointer the HC PDM Device API. */
5322 PCPDMDEVHLPR3 pHlpR3;
5323 /** Pointer to the shared device instance data. */
5324 RTR3PTR pvInstanceDataR3;
5325 /** Pointer to the device instance data for ring-3. */
5326 RTR3PTR pvInstanceDataForR3;
5327 /** The critical section for the device.
5328 *
5329 * TM and IOM will enter this critical section before calling into the device
5330 * code. PDM will when doing power on, power off, reset, suspend and resume
5331 * notifications. SSM will currently not, but this will be changed later on.
5332 *
5333 * The device gets a critical section automatically assigned to it before
5334 * the constructor is called. If the constructor wishes to use a different
5335 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5336 * very early on.
5337 */
5338 R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5339 /** Pointer to device registration structure. */
5340 R3PTRTYPE(PCPDMDEVREG) pReg;
5341 /** Configuration handle. */
5342 R3PTRTYPE(PCFGMNODE) pCfg;
5343 /** The base interface of the device.
5344 *
5345 * The device constructor initializes this if it has any
5346 * device level interfaces to export. To obtain this interface
5347 * call PDMR3QueryDevice(). */
5348 PDMIBASE IBase;
5349
5350 /** Tracing indicator. */
5351 uint32_t fTracing;
5352 /** The tracing ID of this device. */
5353 uint32_t idTracing;
5354
5355 /** Ring-3 pointer to the raw-mode device instance. */
5356 R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5357 /** Raw-mode address of the raw-mode device instance. */
5358 RTRGPTR pDevInsForRC;
5359 /** Ring-3 pointer to the raw-mode instance data. */
5360 RTR3PTR pvInstanceDataForRCR3;
5361
5362 /** PCI device structure size. */
5363 uint32_t cbPciDev;
5364 /** Number of PCI devices in apPciDevs. */
5365 uint32_t cPciDevs;
5366 /** Pointer to the PCI devices for this device.
5367 * (Allocated after the shared instance data.)
5368 * @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5369 * two devices ever needing it can use cbPciDev and do the address
5370 * calculations that for entries 8+. */
5371 R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5372
5373 /** Temporarily. */
5374 R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5375 /** Temporarily. */
5376 RTR0PTR pvInstanceDataR0;
5377 /** Temporarily. */
5378 RTRCPTR pvInstanceDataRC;
5379 /** Align the internal data more naturally. */
5380 uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5381
5382 /** Internal data. */
5383 union
5384 {
5385#ifdef PDMDEVINSINT_DECLARED
5386 PDMDEVINSINTR3 s;
5387#endif
5388 uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
5389 } Internal;
5390
5391 /** Device instance data for ring-3. The size of this area is defined
5392 * in the PDMDEVREG::cbInstanceR3 field. */
5393 char achInstanceData[8];
5394} PDMDEVINSR3;
5395
5396/** Current PDMDEVINSR3 version number. */
5397#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5398
5399/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5400#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5401
5402
5403/**
5404 * PDM ring-0 device instance.
5405 */
5406typedef struct PDMDEVINSR0
5407{
5408 /** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5409 uint32_t u32Version;
5410 /** Device instance number. */
5411 uint32_t iInstance;
5412
5413 /** Pointer the HC PDM Device API. */
5414 PCPDMDEVHLPR0 pHlpR0;
5415 /** Pointer to the shared device instance data. */
5416 RTR0PTR pvInstanceDataR0;
5417 /** Pointer to the device instance data for ring-0. */
5418 RTR0PTR pvInstanceDataForR0;
5419 /** The critical section for the device.
5420 *
5421 * TM and IOM will enter this critical section before calling into the device
5422 * code. PDM will when doing power on, power off, reset, suspend and resume
5423 * notifications. SSM will currently not, but this will be changed later on.
5424 *
5425 * The device gets a critical section automatically assigned to it before
5426 * the constructor is called. If the constructor wishes to use a different
5427 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5428 * very early on.
5429 */
5430 R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5431 /** Pointer to the ring-0 device registration structure. */
5432 R0PTRTYPE(PCPDMDEVREGR0) pReg;
5433 /** Ring-3 address of the ring-3 device instance. */
5434 R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5435 /** Ring-0 pointer to the ring-3 device instance. */
5436 R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5437 /** Ring-0 pointer to the ring-3 instance data. */
5438 RTR0PTR pvInstanceDataForR3R0;
5439 /** Raw-mode address of the raw-mode device instance. */
5440 RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5441 /** Ring-0 pointer to the raw-mode device instance. */
5442 R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5443 /** Ring-0 pointer to the raw-mode instance data. */
5444 RTR0PTR pvInstanceDataForRCR0;
5445
5446 /** PCI device structure size. */
5447 uint32_t cbPciDev;
5448 /** Number of PCI devices in apPciDevs. */
5449 uint32_t cPciDevs;
5450 /** Pointer to the PCI devices for this device.
5451 * (Allocated after the shared instance data.)
5452 * @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5453 * two devices ever needing it can use cbPciDev and do the address
5454 * calculations that for entries 8+. */
5455 R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5456
5457 /** Align the internal data more naturally. */
5458 uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5459
5460 /** Internal data. */
5461 union
5462 {
5463#ifdef PDMDEVINSINT_DECLARED
5464 PDMDEVINSINTR0 s;
5465#endif
5466 uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
5467 } Internal;
5468
5469 /** Device instance data for ring-0. The size of this area is defined
5470 * in the PDMDEVREG::cbInstanceR0 field. */
5471 char achInstanceData[8];
5472} PDMDEVINSR0;
5473
5474/** Current PDMDEVINSR0 version number. */
5475#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5476
5477
5478/**
5479 * PDM raw-mode device instance.
5480 */
5481typedef struct PDMDEVINSRC
5482{
5483 /** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5484 uint32_t u32Version;
5485 /** Device instance number. */
5486 uint32_t iInstance;
5487
5488 /** Pointer the HC PDM Device API. */
5489 PCPDMDEVHLPRC pHlpRC;
5490 /** Pointer to the shared device instance data. */
5491 RTRGPTR pvInstanceDataRC;
5492 /** Pointer to the device instance data for raw-mode. */
5493 RTRGPTR pvInstanceDataForRC;
5494 /** The critical section for the device.
5495 *
5496 * TM and IOM will enter this critical section before calling into the device
5497 * code. PDM will when doing power on, power off, reset, suspend and resume
5498 * notifications. SSM will currently not, but this will be changed later on.
5499 *
5500 * The device gets a critical section automatically assigned to it before
5501 * the constructor is called. If the constructor wishes to use a different
5502 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5503 * very early on.
5504 */
5505 RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5506 /** Pointer to the raw-mode device registration structure. */
5507 RGPTRTYPE(PCPDMDEVREGRC) pReg;
5508
5509 /** PCI device structure size. */
5510 uint32_t cbPciDev;
5511 /** Number of PCI devices in apPciDevs. */
5512 uint32_t cPciDevs;
5513 /** Pointer to the PCI devices for this device.
5514 * (Allocated after the shared instance data.) */
5515 RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5516
5517 /** Align the internal data more naturally. */
5518 uint32_t au32Padding[14];
5519
5520 /** Internal data. */
5521 union
5522 {
5523#ifdef PDMDEVINSINT_DECLARED
5524 PDMDEVINSINTRC s;
5525#endif
5526 uint8_t padding[0x10];
5527 } Internal;
5528
5529 /** Device instance data for ring-0. The size of this area is defined
5530 * in the PDMDEVREG::cbInstanceR0 field. */
5531 char achInstanceData[8];
5532} PDMDEVINSRC;
5533
5534/** Current PDMDEVINSR0 version number. */
5535#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5536
5537
5538/** @def PDM_DEVINS_VERSION
5539 * Current PDMDEVINS version number. */
5540/** @typedef PDMDEVINS
5541 * The device instance structure for the current context. */
5542#ifdef IN_RING3
5543# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5544typedef PDMDEVINSR3 PDMDEVINS;
5545#elif defined(IN_RING0)
5546# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5547typedef PDMDEVINSR0 PDMDEVINS;
5548#elif defined(IN_RC)
5549# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5550typedef PDMDEVINSRC PDMDEVINS;
5551#else
5552# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5553#endif
5554
5555/**
5556 * Get the pointer to an PCI device.
5557 * @note Returns NULL if @a a_idxPciDev is out of bounds.
5558 */
5559#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5560 ( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5561 : PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5562
5563/**
5564 * Calc the pointer to of a given PCI device.
5565 * @note Returns NULL if @a a_idxPciDev is out of bounds.
5566 */
5567#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5568 ( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5569 ? (PPDMPCIDEV)((uint8_t *)((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) * (uintptr_t)(a_idxPciDev)) \
5570 : (PPDMPCIDEV)NULL )
5571
5572
5573/**
5574 * Checks the structure versions of the device instance and device helpers,
5575 * returning if they are incompatible.
5576 *
5577 * This is for use in the constructor.
5578 *
5579 * @param pDevIns The device instance pointer.
5580 */
5581#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5582 do \
5583 { \
5584 PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5585 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5586 ("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5587 VERR_PDM_DEVINS_VERSION_MISMATCH); \
5588 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5589 ("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5590 VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5591 } while (0)
5592
5593/**
5594 * Quietly checks the structure versions of the device instance and device
5595 * helpers, returning if they are incompatible.
5596 *
5597 * This is for use in the destructor.
5598 *
5599 * @param pDevIns The device instance pointer.
5600 */
5601#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5602 do \
5603 { \
5604 PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5605 if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5606 { /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5607 if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5608 { /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5609 } while (0)
5610
5611/**
5612 * Wrapper around CFGMR3ValidateConfig for the root config for use in the
5613 * constructor - returns on failure.
5614 *
5615 * This should be invoked after having initialized the instance data
5616 * sufficiently for the correct operation of the destructor. The destructor is
5617 * always called!
5618 *
5619 * @param pDevIns Pointer to the PDM device instance.
5620 * @param pszValidValues Patterns describing the valid value names. See
5621 * RTStrSimplePatternMultiMatch for details on the
5622 * pattern syntax.
5623 * @param pszValidNodes Patterns describing the valid node (key) names.
5624 * Pass empty string if no valid nodes.
5625 */
5626#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5627 do \
5628 { \
5629 int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5630 (pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5631 if (RT_SUCCESS(rcValCfg)) \
5632 { /* likely */ } else return rcValCfg; \
5633 } while (0)
5634
5635/** @def PDMDEV_ASSERT_EMT
5636 * Assert that the current thread is the emulation thread.
5637 */
5638#ifdef VBOX_STRICT
5639# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5640#else
5641# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5642#endif
5643
5644/** @def PDMDEV_ASSERT_OTHER
5645 * Assert that the current thread is NOT the emulation thread.
5646 */
5647#ifdef VBOX_STRICT
5648# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5649#else
5650# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5651#endif
5652
5653/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5654 * Assert that the current thread is owner of the VM lock.
5655 */
5656#ifdef VBOX_STRICT
5657# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5658#else
5659# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5660#endif
5661
5662/** @def PDMDEV_SET_ERROR
5663 * Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5664 */
5665#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5666 PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5667
5668/** @def PDMDEV_SET_RUNTIME_ERROR
5669 * Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5670 */
5671#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5672 PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5673
5674/** @def PDMDEVINS_2_RCPTR
5675 * Converts a PDM Device instance pointer a RC PDM Device instance pointer.
5676 */
5677#ifdef IN_RC
5678# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5679#else
5680# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5681#endif
5682
5683/** @def PDMDEVINS_2_R3PTR
5684 * Converts a PDM Device instance pointer a R3 PDM Device instance pointer.
5685 */
5686#ifdef IN_RING3
5687# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5688#else
5689# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5690#endif
5691
5692/** @def PDMDEVINS_2_R0PTR
5693 * Converts a PDM Device instance pointer a R0 PDM Device instance pointer.
5694 */
5695#ifdef IN_RING0
5696# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5697#else
5698# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5699#endif
5700
5701/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5702 * Converts a PDM device instance data pointer to a ring-0 one.
5703 * @deprecated
5704 */
5705#ifdef IN_RING0
5706# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5707#else
5708# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5709#endif
5710
5711
5712/** @def PDMDEVINS_2_DATA
5713 * This is a safer edition of PDMINS_2_DATA that checks that the size of the
5714 * target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5715 *
5716 * @note Do no use this macro in common code working on a core structure which
5717 * device specific code has expanded.
5718 */
5719#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5720# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5721 ([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5722 { \
5723 a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5724 Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5725 return pLambdaRet; \
5726 }(a_pDevIns))
5727#else
5728# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5729#endif
5730
5731/** @def PDMDEVINS_2_DATA_CC
5732 * This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5733 * target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5734 *
5735 * @note Do no use this macro in common code working on a core structure which
5736 * device specific code has expanded.
5737 */
5738#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5739# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5740 ([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5741 { \
5742 a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5743 Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5744 return pLambdaRet; \
5745 }(a_pDevIns))
5746#else
5747# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5748#endif
5749
5750
5751#ifdef IN_RING3
5752
5753/**
5754 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
5755 */
5756DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5757 PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
5758 PIOMIOPORTHANDLE phIoPorts)
5759{
5760 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5761 pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5762 if (RT_SUCCESS(rc))
5763 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5764 return rc;
5765}
5766
5767/**
5768 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
5769 */
5770DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5771 PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
5772 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5773{
5774 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5775 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5776 if (RT_SUCCESS(rc))
5777 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5778 return rc;
5779}
5780
5781/**
5782 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
5783 */
5784DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5785 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5786 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5787{
5788 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5789 pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5790 if (RT_SUCCESS(rc))
5791 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5792 return rc;
5793}
5794
5795/**
5796 * Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
5797 */
5798DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5799 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5800 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5801 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5802{
5803 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5804 pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5805 if (RT_SUCCESS(rc))
5806 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5807 return rc;
5808}
5809
5810/**
5811 * @sa PDMDevHlpIoPortCreateEx
5812 */
5813DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5814 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser, const char *pszDesc,
5815 PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5816{
5817 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
5818 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5819}
5820
5821
5822/**
5823 * @sa PDMDevHlpIoPortCreateEx
5824 */
5825DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5826 PFNIOMIOPORTNEWIN pfnIn, void *pvUser, const char *pszDesc,
5827 PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5828{
5829 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5830 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5831}
5832
5833/**
5834 * @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
5835 */
5836DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
5837 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5838 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5839 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5840{
5841 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
5842 pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5843}
5844
5845/**
5846 * @copydoc PDMDEVHLPR3::pfnIoPortMap
5847 */
5848DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
5849{
5850 return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
5851}
5852
5853/**
5854 * @copydoc PDMDEVHLPR3::pfnIoPortUnmap
5855 */
5856DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5857{
5858 return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
5859}
5860
5861/**
5862 * @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
5863 */
5864DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5865{
5866 return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
5867}
5868
5869
5870#endif /* IN_RING3 */
5871#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
5872
5873/**
5874 * @sa PDMDevHlpIoPortSetUpContextEx
5875 */
5876DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5877 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
5878{
5879 return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
5880}
5881
5882/**
5883 * @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
5884 */
5885DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5886 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5887 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
5888{
5889 return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
5890}
5891
5892#endif /* !IN_RING3 || DOXYGEN_RUNNING */
5893#ifdef IN_RING3
5894
5895/**
5896 * @sa PDMDevHlpMmioCreateEx
5897 */
5898DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5899 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
5900 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
5901{
5902 return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
5903 pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
5904}
5905
5906/**
5907 * @copydoc PDMDEVHLPR3::pfnMmioCreateEx
5908 */
5909DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
5910 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5911 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
5912 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion)
5913{
5914 return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
5915 pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
5916}
5917
5918/**
5919 * @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
5920 */
5921DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
5922 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
5923 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
5924{
5925 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /*pPciDev*/, UINT32_MAX /*iPciRegion*/,
5926 pfnWrite, pfnRead, NULL /*pfnFill*/, NULL /*pvUser*/, pszDesc, phRegion);
5927 if (RT_SUCCESS(rc))
5928 rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
5929 return rc;
5930}
5931
5932/**
5933 * @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
5934 */
5935DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
5936 PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
5937 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
5938 const char *pszDesc, PIOMMMIOHANDLE phRegion)
5939{
5940 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
5941 pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
5942 if (RT_SUCCESS(rc))
5943 rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
5944 return rc;
5945}
5946
5947/**
5948 * @copydoc PDMDEVHLPR3::pfnMmioMap
5949 */
5950DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
5951{
5952 return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
5953}
5954
5955/**
5956 * @copydoc PDMDEVHLPR3::pfnMmioUnmap
5957 */
5958DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
5959{
5960 return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
5961}
5962
5963/**
5964 * @copydoc PDMDEVHLPR3::pfnMmioReduce
5965 */
5966DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
5967{
5968 return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
5969}
5970
5971/**
5972 * @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
5973 */
5974DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
5975{
5976 return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
5977}
5978
5979#endif /* IN_RING3 */
5980#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
5981
5982/**
5983 * @sa PDMDevHlpMmioSetUpContextEx
5984 */
5985DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
5986 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
5987{
5988 return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
5989}
5990
5991/**
5992 * @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
5993 */
5994DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5995 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
5996{
5997 return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
5998}
5999
6000#endif /* !IN_RING3 || DOXYGEN_RUNNING */
6001#ifdef IN_RING3
6002
6003/**
6004 * @copydoc PDMDEVHLPR3::pfnMmio2Create
6005 */
6006DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6007 uint32_t fFlags, const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion)
6008{
6009 return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6010}
6011
6012/**
6013 * @copydoc PDMDEVHLPR3::pfnMmio2Map
6014 */
6015DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6016{
6017 return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6018}
6019
6020/**
6021 * @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6022 */
6023DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6024{
6025 return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6026}
6027
6028/**
6029 * @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6030 */
6031DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6032{
6033 return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6034}
6035
6036/**
6037 * @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6038 */
6039DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6040{
6041 return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6042}
6043
6044#endif /* IN_RING3 */
6045#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
6046
6047/**
6048 * @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6049 */
6050DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6051 size_t offSub, size_t cbSub, void **ppvMapping)
6052{
6053 return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6054}
6055
6056#endif /* !IN_RING3 || DOXYGEN_RUNNING */
6057#ifdef IN_RING3
6058
6059/**
6060 * @copydoc PDMDEVHLPR3::pfnROMRegister
6061 */
6062DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6063 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc)
6064{
6065 return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6066}
6067
6068/**
6069 * @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6070 */
6071DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6072{
6073 return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6074}
6075
6076/**
6077 * Register a save state data unit.
6078 *
6079 * @returns VBox status.
6080 * @param pDevIns The device instance.
6081 * @param uVersion Data layout version number.
6082 * @param cbGuess The approximate amount of data in the unit.
6083 * Only for progress indicators.
6084 * @param pfnSaveExec Execute save callback, optional.
6085 * @param pfnLoadExec Execute load callback, optional.
6086 */
6087DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6088 PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6089{
6090 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /*pszBefore*/,
6091 NULL /*pfnLivePrep*/, NULL /*pfnLiveExec*/, NULL /*pfnLiveDone*/,
6092 NULL /*pfnSavePrep*/, pfnSaveExec, NULL /*pfnSaveDone*/,
6093 NULL /*pfnLoadPrep*/, pfnLoadExec, NULL /*pfnLoadDone*/);
6094}
6095
6096/**
6097 * Register a save state data unit with a live save callback as well.
6098 *
6099 * @returns VBox status.
6100 * @param pDevIns The device instance.
6101 * @param uVersion Data layout version number.
6102 * @param cbGuess The approximate amount of data in the unit.
6103 * Only for progress indicators.
6104 * @param pfnLiveExec Execute live callback, optional.
6105 * @param pfnSaveExec Execute save callback, optional.
6106 * @param pfnLoadExec Execute load callback, optional.
6107 */
6108DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6109 PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6110{
6111 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /*pszBefore*/,
6112 NULL /*pfnLivePrep*/, pfnLiveExec, NULL /*pfnLiveDone*/,
6113 NULL /*pfnSavePrep*/, pfnSaveExec, NULL /*pfnSaveDone*/,
6114 NULL /*pfnLoadPrep*/, pfnLoadExec, NULL /*pfnLoadDone*/);
6115}
6116
6117/**
6118 * @copydoc PDMDEVHLPR3::pfnSSMRegister
6119 */
6120DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6121 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6122 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6123 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6124{
6125 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6126 pfnLivePrep, pfnLiveExec, pfnLiveVote,
6127 pfnSavePrep, pfnSaveExec, pfnSaveDone,
6128 pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6129}
6130
6131/**
6132 * @copydoc PDMDEVHLPR3::pfnTMTimerCreate
6133 */
6134DECLINLINE(int) PDMDevHlpTMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6135 uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
6136{
6137 return pDevIns->pHlpR3->pfnTMTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
6138}
6139
6140/**
6141 * @copydoc PDMDEVHLPR3::pfnTimerCreate
6142 */
6143DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6144 uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6145{
6146 return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6147}
6148
6149#endif /* IN_RING3 */
6150
6151/**
6152 * @copydoc PDMDEVHLPR3::pfnTimerToPtr
6153 */
6154DECLINLINE(PTMTIMER) PDMDevHlpTimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6155{
6156 return pDevIns->CTX_SUFF(pHlp)->pfnTimerToPtr(pDevIns, hTimer);
6157}
6158
6159/**
6160 * @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6161 */
6162DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6163{
6164 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6165}
6166
6167/**
6168 * @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6169 */
6170DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6171{
6172 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6173}
6174
6175/**
6176 * @copydoc PDMDEVHLPR3::pfnTimerFromNano
6177 */
6178DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6179{
6180 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6181}
6182
6183/**
6184 * @copydoc PDMDEVHLPR3::pfnTimerGet
6185 */
6186DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6187{
6188 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6189}
6190
6191/**
6192 * @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6193 */
6194DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6195{
6196 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6197}
6198
6199/**
6200 * @copydoc PDMDEVHLPR3::pfnTimerGetNano
6201 */
6202DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6203{
6204 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6205}
6206
6207/**
6208 * @copydoc PDMDEVHLPR3::pfnTimerIsActive
6209 */
6210DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6211{
6212 return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6213}
6214
6215/**
6216 * @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6217 */
6218DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6219{
6220 return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6221}
6222
6223/**
6224 * @copydoc PDMDEVHLPR3::pfnTimerLockClock
6225 */
6226DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6227{
6228 return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6229}
6230
6231/**
6232 * @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6233 */
6234DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6235{
6236 return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6237}
6238
6239/**
6240 * @copydoc PDMDEVHLPR3::pfnTimerSet
6241 */
6242DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6243{
6244 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6245}
6246
6247/**
6248 * @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6249 */
6250DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6251{
6252 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6253}
6254
6255/**
6256 * @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6257 */
6258DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6259{
6260 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6261}
6262
6263/**
6264 * @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6265 */
6266DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6267{
6268 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6269}
6270
6271/**
6272 * @copydoc PDMDEVHLPR3::pfnTimerSetNano
6273 */
6274DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6275{
6276 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6277}
6278
6279/**
6280 * @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6281 */
6282DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6283{
6284 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6285}
6286
6287/**
6288 * @copydoc PDMDEVHLPR3::pfnTimerStop
6289 */
6290DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6291{
6292 return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6293}
6294
6295/**
6296 * @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6297 */
6298DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6299{
6300 pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6301}
6302
6303/**
6304 * @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6305 */
6306DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6307{
6308 pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6309}
6310
6311#ifdef IN_RING3
6312
6313/**
6314 * @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6315 */
6316DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6317{
6318 return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6319}
6320
6321/**
6322 * @copydoc PDMDEVHLPR3::pfnTimerSave
6323 */
6324DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6325{
6326 return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6327}
6328
6329/**
6330 * @copydoc PDMDEVHLPR3::pfnTimerLoad
6331 */
6332DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6333{
6334 return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6335}
6336
6337/**
6338 * @copydoc PDMDEVHLPR3::pfnTimerDestroy
6339 */
6340DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6341{
6342 return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6343}
6344
6345/**
6346 * @copydoc PDMDEVHLPR3::pfnTMUtcNow
6347 */
6348DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6349{
6350 return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6351}
6352
6353#endif
6354
6355/**
6356 * Read physical memory - unknown data usage.
6357 *
6358 * @returns VINF_SUCCESS (for now).
6359 * @param pDevIns The device instance.
6360 * @param GCPhys Physical address start reading from.
6361 * @param pvBuf Where to put the read bits.
6362 * @param cbRead How many bytes to read.
6363 * @thread Any thread, but the call may involve the emulation thread.
6364 */
6365DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6366{
6367 return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6368}
6369
6370/**
6371 * Write to physical memory - unknown data usage.
6372 *
6373 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6374 * @param pDevIns The device instance.
6375 * @param GCPhys Physical address to write to.
6376 * @param pvBuf What to write.
6377 * @param cbWrite How many bytes to write.
6378 * @thread Any thread, but the call may involve the emulation thread.
6379 */
6380DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6381{
6382 return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6383}
6384
6385/**
6386 * Read physical memory - reads meta data processed by the device.
6387 *
6388 * @returns VINF_SUCCESS (for now).
6389 * @param pDevIns The device instance.
6390 * @param GCPhys Physical address start reading from.
6391 * @param pvBuf Where to put the read bits.
6392 * @param cbRead How many bytes to read.
6393 * @thread Any thread, but the call may involve the emulation thread.
6394 */
6395DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6396{
6397 return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6398}
6399
6400/**
6401 * Write to physical memory - written data was created/altered by the device.
6402 *
6403 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6404 * @param pDevIns The device instance.
6405 * @param GCPhys Physical address to write to.
6406 * @param pvBuf What to write.
6407 * @param cbWrite How many bytes to write.
6408 * @thread Any thread, but the call may involve the emulation thread.
6409 */
6410DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6411{
6412 return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6413}
6414
6415/**
6416 * Read physical memory - read data will not be touched by the device.
6417 *
6418 * @returns VINF_SUCCESS (for now).
6419 * @param pDevIns The device instance.
6420 * @param GCPhys Physical address start reading from.
6421 * @param pvBuf Where to put the read bits.
6422 * @param cbRead How many bytes to read.
6423 * @thread Any thread, but the call may involve the emulation thread.
6424 */
6425DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6426{
6427 return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6428}
6429
6430/**
6431 * Write to physical memory - written data was not touched/created by the device.
6432 *
6433 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6434 * @param pDevIns The device instance.
6435 * @param GCPhys Physical address to write to.
6436 * @param pvBuf What to write.
6437 * @param cbWrite How many bytes to write.
6438 * @thread Any thread, but the call may involve the emulation thread.
6439 */
6440DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6441{
6442 return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6443}
6444
6445#ifdef IN_RING3
6446
6447/**
6448 * @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6449 */
6450DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6451{
6452 return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6453}
6454
6455/**
6456 * @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6457 */
6458DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6459 PPGMPAGEMAPLOCK pLock)
6460{
6461 return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6462}
6463
6464/**
6465 * @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6466 */
6467DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6468{
6469 pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6470}
6471
6472/**
6473 * @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6474 */
6475DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6476 uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6477{
6478 return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6479}
6480
6481/**
6482 * @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6483 */
6484DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6485 uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6486{
6487 return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6488}
6489
6490/**
6491 * @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6492 */
6493DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6494{
6495 pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6496}
6497
6498/**
6499 * @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
6500 */
6501DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
6502{
6503 return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
6504}
6505
6506/**
6507 * @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6508 */
6509DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6510{
6511 return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6512}
6513
6514/**
6515 * @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6516 */
6517DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6518{
6519 return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6520}
6521
6522/**
6523 * @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6524 */
6525DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6526{
6527 return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6528}
6529
6530/**
6531 * @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6532 */
6533DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6534{
6535 return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6536}
6537
6538/**
6539 * @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6540 */
6541DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6542{
6543 return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6544}
6545
6546/**
6547 * @copydoc PDMDEVHLPR3::pfnMMHeapFree
6548 */
6549DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6550{
6551 pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6552}
6553#endif /* IN_RING3 */
6554
6555/**
6556 * @copydoc PDMDEVHLPR3::pfnVMState
6557 */
6558DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6559{
6560 return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6561}
6562
6563#ifdef IN_RING3
6564/**
6565 * @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6566 */
6567DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6568{
6569 return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6570}
6571#endif /* IN_RING3 */
6572
6573/**
6574 * @copydoc PDMDEVHLPR3::pfnVMSetError
6575 */
6576DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6577 const char *pszFormat, ...)
6578{
6579 va_list va;
6580 va_start(va, pszFormat);
6581 pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6582 va_end(va);
6583 return rc;
6584}
6585
6586/**
6587 * @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError
6588 */
6589DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6590 const char *pszFormat, ...)
6591{
6592 va_list va;
6593 int rc;
6594 va_start(va, pszFormat);
6595 rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6596 va_end(va);
6597 return rc;
6598}
6599
6600/**
6601 * VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6602 *
6603 * @returns VBox status code which must be passed up to the VMM. This will be
6604 * VINF_SUCCESS in non-strict builds.
6605 * @param pDevIns The device instance.
6606 * @param SRC_POS Use RT_SRC_POS.
6607 * @param pszFormat Message. (optional)
6608 * @param ... Message parameters.
6609 */
6610DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6611{
6612#ifdef VBOX_STRICT
6613# ifdef IN_RING3
6614 int rc;
6615 va_list args;
6616 va_start(args, pszFormat);
6617 rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6618 va_end(args);
6619 return rc;
6620# else
6621 NOREF(pDevIns);
6622 NOREF(pszFile);
6623 NOREF(iLine);
6624 NOREF(pszFunction);
6625 NOREF(pszFormat);
6626 return VINF_EM_DBG_STOP;
6627# endif
6628#else
6629 NOREF(pDevIns);
6630 NOREF(pszFile);
6631 NOREF(iLine);
6632 NOREF(pszFunction);
6633 NOREF(pszFormat);
6634 return VINF_SUCCESS;
6635#endif
6636}
6637
6638#ifdef IN_RING3
6639
6640/**
6641 * @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6642 */
6643DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6644{
6645 return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6646}
6647
6648/**
6649 * @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6650 */
6651DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6652{
6653 return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6654}
6655
6656/**
6657 * @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6658 */
6659DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6660{
6661 return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6662}
6663
6664/**
6665 * @copydoc PDMDEVHLPR3::pfnSTAMRegister
6666 */
6667DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc)
6668{
6669 pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6670}
6671
6672/**
6673 * Same as pfnSTAMRegister except that the name is specified in a
6674 * RTStrPrintf like fashion.
6675 *
6676 * @returns VBox status.
6677 * @param pDevIns Device instance of the DMA.
6678 * @param pvSample Pointer to the sample.
6679 * @param enmType Sample type. This indicates what pvSample is
6680 * pointing at.
6681 * @param enmVisibility Visibility type specifying whether unused
6682 * statistics should be visible or not.
6683 * @param enmUnit Sample unit.
6684 * @param pszDesc Sample description.
6685 * @param pszName Sample name format string, unix path style. If
6686 * this does not start with a '/', the default
6687 * prefix will be prepended, otherwise it will be
6688 * used as-is.
6689 * @param ... Arguments to the format string.
6690 */
6691DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6692 STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6693 const char *pszDesc, const char *pszName, ...)
6694{
6695 va_list va;
6696 va_start(va, pszName);
6697 pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6698 va_end(va);
6699}
6700
6701/**
6702 * Registers the device with the default PCI bus.
6703 *
6704 * @returns VBox status code.
6705 * @param pDevIns The device instance.
6706 * @param pPciDev The PCI device structure.
6707 * This must be kept in the instance data.
6708 * The PCI configuration must be initialized before registration.
6709 */
6710DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6711{
6712 return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /*fFlags*/,
6713 PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6714}
6715
6716/**
6717 * @copydoc PDMDEVHLPR3::pfnPCIRegister
6718 */
6719DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6720 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6721{
6722 return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6723}
6724
6725/**
6726 * Initialize MSI emulation support for the first PCI device.
6727 *
6728 * @returns VBox status code.
6729 * @param pDevIns The device instance.
6730 * @param pMsiReg MSI emulation registration structure.
6731 */
6732DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6733{
6734 return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6735}
6736
6737/**
6738 * @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6739 */
6740DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6741{
6742 return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6743}
6744
6745/**
6746 * Registers a I/O port region for the default PCI device.
6747 *
6748 * @returns VBox status code.
6749 * @param pDevIns The device instance.
6750 * @param iRegion The region number.
6751 * @param cbRegion Size of the region.
6752 * @param hIoPorts Handle to the I/O port region.
6753 */
6754DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
6755{
6756 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6757 PDMPCIDEV_IORGN_F_IOPORT_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
6758}
6759
6760/**
6761 * Registers a I/O port region for the default PCI device, custom map/unmap.
6762 *
6763 * @returns VBox status code.
6764 * @param pDevIns The device instance.
6765 * @param iRegion The region number.
6766 * @param cbRegion Size of the region.
6767 * @param pfnMapUnmap Callback for doing the mapping, optional. The
6768 * callback will be invoked holding only the PDM lock.
6769 * The device lock will _not_ be taken (due to lock
6770 * order).
6771 */
6772DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6773 PFNPCIIOREGIONMAP pfnMapUnmap)
6774{
6775 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6776 PDMPCIDEV_IORGN_F_NO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6777 UINT64_MAX, pfnMapUnmap);
6778}
6779
6780/**
6781 * Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
6782 * and registering an I/O port region for the default PCI device.
6783 *
6784 * @returns VBox status code.
6785 * @param pDevIns The device instance to register the ports with.
6786 * @param cPorts The count of I/O ports in the region (the size).
6787 * @param iPciRegion The PCI device region.
6788 * @param pfnOut Pointer to function which is gonna handle OUT
6789 * operations. Optional.
6790 * @param pfnIn Pointer to function which is gonna handle IN operations.
6791 * Optional.
6792 * @param pvUser User argument to pass to the callbacks.
6793 * @param pszDesc Pointer to description string. This must not be freed.
6794 * @param paExtDescs Extended per-port descriptions, optional. Partial range
6795 * coverage is allowed. This must not be freed.
6796 * @param phIoPorts Where to return the I/O port range handle.
6797 *
6798 */
6799DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
6800 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6801 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6802
6803{
6804 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /*fFlags*/, pDevIns->apPciDevs[0], iPciRegion << 16,
6805 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6806 if (RT_SUCCESS(rc))
6807 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
6808 PDMPCIDEV_IORGN_F_IOPORT_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6809 *phIoPorts, NULL /*pfnMapUnmap*/);
6810 return rc;
6811}
6812
6813/**
6814 * Registers an MMIO region for the default PCI device.
6815 *
6816 * @returns VBox status code.
6817 * @param pDevIns The device instance.
6818 * @param iRegion The region number.
6819 * @param cbRegion Size of the region.
6820 * @param enmType PCI_ADDRESS_SPACE_MEM or
6821 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6822 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6823 * @param hMmioRegion Handle to the MMIO region.
6824 * @param pfnMapUnmap Callback for doing the mapping, optional. The
6825 * callback will be invoked holding only the PDM lock.
6826 * The device lock will _not_ be taken (due to lock
6827 * order).
6828 */
6829DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
6830 IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
6831{
6832 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6833 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6834 hMmioRegion, pfnMapUnmap);
6835}
6836
6837/**
6838 * Registers an MMIO region for the default PCI device, extended version.
6839 *
6840 * @returns VBox status code.
6841 * @param pDevIns The device instance.
6842 * @param pPciDev The PCI device structure.
6843 * @param iRegion The region number.
6844 * @param cbRegion Size of the region.
6845 * @param enmType PCI_ADDRESS_SPACE_MEM or
6846 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6847 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6848 * @param hMmioRegion Handle to the MMIO region.
6849 * @param pfnMapUnmap Callback for doing the mapping, optional. The
6850 * callback will be invoked holding only the PDM lock.
6851 * The device lock will _not_ be taken (due to lock
6852 * order).
6853 */
6854DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
6855 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
6856 PFNPCIIOREGIONMAP pfnMapUnmap)
6857{
6858 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
6859 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6860 hMmioRegion, pfnMapUnmap);
6861}
6862
6863/**
6864 * Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
6865 * and registering an MMIO region for the default PCI device.
6866 *
6867 * @returns VBox status code.
6868 * @param pDevIns The device instance to register the ports with.
6869 * @param cbRegion The size of the region in bytes.
6870 * @param iPciRegion The PCI device region.
6871 * @param enmType PCI_ADDRESS_SPACE_MEM or
6872 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6873 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6874 * @param fFlags Flags, IOMMMIO_FLAGS_XXX.
6875 * @param pfnWrite Pointer to function which is gonna handle Write
6876 * operations.
6877 * @param pfnRead Pointer to function which is gonna handle Read
6878 * operations.
6879 * @param pvUser User argument to pass to the callbacks.
6880 * @param pszDesc Pointer to description string. This must not be freed.
6881 * @param phRegion Where to return the MMIO region handle.
6882 *
6883 */
6884DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
6885 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6886 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6887
6888{
6889 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
6890 pfnWrite, pfnRead, NULL /*pfnFill*/, pvUser, pszDesc, phRegion);
6891 if (RT_SUCCESS(rc))
6892 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
6893 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6894 *phRegion, NULL /*pfnMapUnmap*/);
6895 return rc;
6896}
6897
6898
6899/**
6900 * Registers an MMIO2 region for the default PCI device.
6901 *
6902 * @returns VBox status code.
6903 * @param pDevIns The device instance.
6904 * @param iRegion The region number.
6905 * @param cbRegion Size of the region.
6906 * @param enmType PCI_ADDRESS_SPACE_MEM or
6907 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6908 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6909 * @param hMmio2Region Handle to the MMIO2 region.
6910 */
6911DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6912 PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
6913{
6914 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6915 PDMPCIDEV_IORGN_F_MMIO2_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6916 hMmio2Region, NULL);
6917}
6918
6919/**
6920 * Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
6921 * and registering an MMIO2 region for the default PCI device, extended edition.
6922 *
6923 * @returns VBox status code.
6924 * @param pDevIns The device instance to register the ports with.
6925 * @param cbRegion The size of the region in bytes.
6926 * @param iPciRegion The PCI device region.
6927 * @param enmType PCI_ADDRESS_SPACE_MEM or
6928 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6929 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6930 * @param pszDesc Pointer to description string. This must not be freed.
6931 * @param ppvMapping Where to store the address of the ring-3 mapping of
6932 * the memory.
6933 * @param phRegion Where to return the MMIO2 region handle.
6934 *
6935 */
6936DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
6937 PCIADDRESSSPACE enmType, const char *pszDesc,
6938 void **ppvMapping, PPGMMMIO2HANDLE phRegion)
6939
6940{
6941 int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /*fFlags*/,
6942 pszDesc, ppvMapping, phRegion);
6943 if (RT_SUCCESS(rc))
6944 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
6945 PDMPCIDEV_IORGN_F_MMIO2_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6946 *phRegion, NULL /*pfnCallback*/);
6947 return rc;
6948}
6949
6950/**
6951 * Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
6952 * and registering an MMIO2 region for the default PCI device.
6953 *
6954 * @returns VBox status code.
6955 * @param pDevIns The device instance to register the ports with.
6956 * @param cbRegion The size of the region in bytes.
6957 * @param iPciRegion The PCI device region.
6958 * @param enmType PCI_ADDRESS_SPACE_MEM or
6959 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6960 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6961 * @param fMmio2Flags To be defined, must be zero.
6962 * @param pfnMapUnmap Callback for doing the mapping, optional. The
6963 * callback will be invoked holding only the PDM lock.
6964 * The device lock will _not_ be taken (due to lock
6965 * order).
6966 * @param pszDesc Pointer to description string. This must not be freed.
6967 * @param ppvMapping Where to store the address of the ring-3 mapping of
6968 * the memory.
6969 * @param phRegion Where to return the MMIO2 region handle.
6970 *
6971 */
6972DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
6973 PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
6974 const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion)
6975
6976{
6977 int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
6978 pszDesc, ppvMapping, phRegion);
6979 if (RT_SUCCESS(rc))
6980 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
6981 PDMPCIDEV_IORGN_F_MMIO2_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6982 *phRegion, pfnMapUnmap);
6983 return rc;
6984}
6985
6986/**
6987 * @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
6988 */
6989DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
6990 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
6991{
6992 return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
6993}
6994
6995/**
6996 * @copydoc PDMDEVHLPR3::pfnPCIConfigRead
6997 */
6998DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
6999 unsigned cb, uint32_t *pu32Value)
7000{
7001 return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7002}
7003
7004/**
7005 * @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7006 */
7007DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7008 unsigned cb, uint32_t u32Value)
7009{
7010 return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7011}
7012
7013#endif /* IN_RING3 */
7014
7015/**
7016 * Bus master physical memory read from the default PCI device.
7017 *
7018 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7019 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7020 * @param pDevIns The device instance.
7021 * @param GCPhys Physical address start reading from.
7022 * @param pvBuf Where to put the read bits.
7023 * @param cbRead How many bytes to read.
7024 * @thread Any thread, but the call may involve the emulation thread.
7025 */
7026DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7027{
7028 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7029}
7030
7031/**
7032 * Bus master physical memory read - unknown data usage.
7033 *
7034 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7035 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7036 * @param pDevIns The device instance.
7037 * @param pPciDev The PCI device structure. If NULL the default
7038 * PCI device for this device instance is used.
7039 * @param GCPhys Physical address start reading from.
7040 * @param pvBuf Where to put the read bits.
7041 * @param cbRead How many bytes to read.
7042 * @thread Any thread, but the call may involve the emulation thread.
7043 */
7044DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7045{
7046 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7047}
7048
7049/**
7050 * Bus master physical memory read from the default PCI device.
7051 *
7052 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7053 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7054 * @param pDevIns The device instance.
7055 * @param GCPhys Physical address start reading from.
7056 * @param pvBuf Where to put the read bits.
7057 * @param cbRead How many bytes to read.
7058 * @thread Any thread, but the call may involve the emulation thread.
7059 */
7060DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7061{
7062 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7063}
7064
7065/**
7066 * Bus master physical memory read - reads meta data processed by the device.
7067 *
7068 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7069 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7070 * @param pDevIns The device instance.
7071 * @param pPciDev The PCI device structure. If NULL the default
7072 * PCI device for this device instance is used.
7073 * @param GCPhys Physical address start reading from.
7074 * @param pvBuf Where to put the read bits.
7075 * @param cbRead How many bytes to read.
7076 * @thread Any thread, but the call may involve the emulation thread.
7077 */
7078DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7079{
7080 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7081}
7082
7083/**
7084 * Bus master physical memory read from the default PCI device - read data will not be touched by the device.
7085 *
7086 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7087 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7088 * @param pDevIns The device instance.
7089 * @param GCPhys Physical address start reading from.
7090 * @param pvBuf Where to put the read bits.
7091 * @param cbRead How many bytes to read.
7092 * @thread Any thread, but the call may involve the emulation thread.
7093 */
7094DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7095{
7096 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7097}
7098
7099/**
7100 * Bus master physical memory read - read data will not be touched by the device.
7101 *
7102 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7103 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7104 * @param pDevIns The device instance.
7105 * @param pPciDev The PCI device structure. If NULL the default
7106 * PCI device for this device instance is used.
7107 * @param GCPhys Physical address start reading from.
7108 * @param pvBuf Where to put the read bits.
7109 * @param cbRead How many bytes to read.
7110 * @thread Any thread, but the call may involve the emulation thread.
7111 */
7112DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7113{
7114 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7115}
7116
7117/**
7118 * Bus master physical memory write from the default PCI device - unknown data usage.
7119 *
7120 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7121 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7122 * @param pDevIns The device instance.
7123 * @param GCPhys Physical address to write to.
7124 * @param pvBuf What to write.
7125 * @param cbWrite How many bytes to write.
7126 * @thread Any thread, but the call may involve the emulation thread.
7127 */
7128DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7129{
7130 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7131}
7132
7133/**
7134 * Bus master physical memory write - unknown data usage.
7135 *
7136 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7137 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7138 * @param pDevIns The device instance.
7139 * @param pPciDev The PCI device structure. If NULL the default
7140 * PCI device for this device instance is used.
7141 * @param GCPhys Physical address to write to.
7142 * @param pvBuf What to write.
7143 * @param cbWrite How many bytes to write.
7144 * @thread Any thread, but the call may involve the emulation thread.
7145 */
7146DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7147{
7148 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7149}
7150
7151/**
7152 * Bus master physical memory write from the default PCI device.
7153 *
7154 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7155 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7156 * @param pDevIns The device instance.
7157 * @param GCPhys Physical address to write to.
7158 * @param pvBuf What to write.
7159 * @param cbWrite How many bytes to write.
7160 * @thread Any thread, but the call may involve the emulation thread.
7161 */
7162DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7163{
7164 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7165}
7166
7167/**
7168 * Bus master physical memory write - written data was created/altered by the device.
7169 *
7170 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7171 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7172 * @param pDevIns The device instance.
7173 * @param pPciDev The PCI device structure. If NULL the default
7174 * PCI device for this device instance is used.
7175 * @param GCPhys Physical address to write to.
7176 * @param pvBuf What to write.
7177 * @param cbWrite How many bytes to write.
7178 * @thread Any thread, but the call may involve the emulation thread.
7179 */
7180DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7181{
7182 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7183}
7184
7185/**
7186 * Bus master physical memory write from the default PCI device.
7187 *
7188 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7189 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7190 * @param pDevIns The device instance.
7191 * @param GCPhys Physical address to write to.
7192 * @param pvBuf What to write.
7193 * @param cbWrite How many bytes to write.
7194 * @thread Any thread, but the call may involve the emulation thread.
7195 */
7196DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7197{
7198 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7199}
7200
7201/**
7202 * Bus master physical memory write - written data was not touched/created by the device.
7203 *
7204 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7205 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7206 * @param pDevIns The device instance.
7207 * @param pPciDev The PCI device structure. If NULL the default
7208 * PCI device for this device instance is used.
7209 * @param GCPhys Physical address to write to.
7210 * @param pvBuf What to write.
7211 * @param cbWrite How many bytes to write.
7212 * @thread Any thread, but the call may involve the emulation thread.
7213 */
7214DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7215{
7216 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7217}
7218
7219/**
7220 * Sets the IRQ for the default PCI device.
7221 *
7222 * @param pDevIns The device instance.
7223 * @param iIrq IRQ number to set.
7224 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7225 * @thread Any thread, but will involve the emulation thread.
7226 */
7227DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7228{
7229 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7230}
7231
7232/**
7233 * @copydoc PDMDEVHLPR3::pfnPCISetIrq
7234 */
7235DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7236{
7237 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7238}
7239
7240/**
7241 * Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7242 * the request when not called from EMT.
7243 *
7244 * @param pDevIns The device instance.
7245 * @param iIrq IRQ number to set.
7246 * @param iLevel IRQ level.
7247 * @thread Any thread, but will involve the emulation thread.
7248 */
7249DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7250{
7251 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7252}
7253
7254/**
7255 * @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7256 */
7257DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7258{
7259 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7260}
7261
7262/**
7263 * @copydoc PDMDEVHLPR3::pfnISASetIrq
7264 */
7265DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7266{
7267 pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7268}
7269
7270/**
7271 * @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7272 */
7273DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7274{
7275 pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7276}
7277
7278#ifdef IN_RING3
7279
7280/**
7281 * @copydoc PDMDEVHLPR3::pfnDriverAttach
7282 */
7283DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE *ppBaseInterface, const char *pszDesc)
7284{
7285 return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7286}
7287
7288/**
7289 * @copydoc PDMDEVHLPR3::pfnDriverDetach
7290 */
7291DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7292{
7293 return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7294}
7295
7296/**
7297 * @copydoc PDMDEVHLPR3::pfnDriverReconfigure
7298 */
7299DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
7300 const char * const *papszDrivers, PCFGMNODE *papConfigs, uint32_t fFlags)
7301{
7302 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
7303}
7304
7305/**
7306 * Reconfigures with a single driver reattachement, no config, noflags.
7307 * @sa PDMDevHlpDriverReconfigure
7308 */
7309DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
7310{
7311 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
7312}
7313
7314/**
7315 * Reconfigures with a two drivers reattachement, no config, noflags.
7316 * @sa PDMDevHlpDriverReconfigure
7317 */
7318DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0, const char *pszDriver1)
7319{
7320 char const * apszDrivers[2];
7321 apszDrivers[0] = pszDriver0;
7322 apszDrivers[1] = pszDriver1;
7323 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
7324}
7325
7326/**
7327 * @copydoc PDMDEVHLPR3::pfnQueueCreatePtr
7328 */
7329DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7330 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName, PPDMQUEUE *ppQueue)
7331{
7332 return pDevIns->pHlpR3->pfnQueueCreatePtr(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
7333}
7334
7335/**
7336 * @copydoc PDMDEVHLPR3::pfnQueueCreate
7337 */
7338DECLINLINE(int) PDMDevHlpQueueCreateNew(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7339 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName, PDMQUEUEHANDLE *phQueue)
7340{
7341 return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7342}
7343
7344#endif /* IN_RING3 */
7345
7346/**
7347 * @copydoc PDMDEVHLPR3::pfnQueueAlloc
7348 */
7349DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7350{
7351 return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7352}
7353
7354/**
7355 * @copydoc PDMDEVHLPR3::pfnQueueInsert
7356 */
7357DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7358{
7359 pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7360}
7361
7362/**
7363 * @copydoc PDMDEVHLPR3::pfnQueueInsertEx
7364 */
7365DECLINLINE(void) PDMDevHlpQueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay)
7366{
7367 pDevIns->CTX_SUFF(pHlp)->pfnQueueInsertEx(pDevIns, hQueue, pItem, cNanoMaxDelay);
7368}
7369
7370/**
7371 * @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7372 */
7373DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7374{
7375 return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7376}
7377
7378#ifdef IN_RING3
7379/**
7380 * @copydoc PDMDEVHLPR3::pfnTaskCreate
7381 */
7382DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7383 PFNPDMTASKDEV pfnCallback, void *pvUser, PDMTASKHANDLE *phTask)
7384{
7385 return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7386}
7387#endif
7388
7389/**
7390 * @copydoc PDMDEVHLPR3::pfnTaskTrigger
7391 */
7392DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7393{
7394 return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7395}
7396
7397#ifdef IN_RING3
7398
7399/**
7400 * @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7401 */
7402DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7403{
7404 return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7405}
7406
7407/**
7408 * @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7409 */
7410DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7411{
7412 return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7413}
7414
7415#endif /* IN_RING3 */
7416
7417/**
7418 * @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7419 */
7420DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7421{
7422 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7423}
7424
7425/**
7426 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7427 */
7428DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7429{
7430 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7431}
7432
7433/**
7434 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7435 */
7436DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7437{
7438 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7439}
7440
7441/**
7442 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7443 */
7444DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7445{
7446 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7447}
7448
7449/**
7450 * @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7451 */
7452DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7453{
7454 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7455}
7456
7457#ifdef IN_RING3
7458
7459/**
7460 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7461 */
7462DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7463{
7464 return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7465}
7466
7467/**
7468 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7469 */
7470DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7471{
7472 return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7473}
7474
7475#endif /* IN_RING3 */
7476
7477/**
7478 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7479 */
7480DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7481{
7482 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7483}
7484
7485/**
7486 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7487 */
7488DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7489{
7490 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7491}
7492
7493/**
7494 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7495 */
7496DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7497{
7498 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7499}
7500
7501/**
7502 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7503 */
7504DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7505{
7506 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7507}
7508
7509/**
7510 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7511 */
7512DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7513{
7514 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7515}
7516
7517/**
7518 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7519 */
7520DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7521{
7522 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7523}
7524
7525#ifdef IN_RING3
7526
7527/**
7528 * Initializes a PDM critical section.
7529 *
7530 * The PDM critical sections are derived from the IPRT critical sections, but
7531 * works in RC and R0 as well.
7532 *
7533 * @returns VBox status code.
7534 * @param pDevIns The device instance.
7535 * @param pCritSect Pointer to the critical section.
7536 * @param SRC_POS Use RT_SRC_POS.
7537 * @param pszNameFmt Format string for naming the critical section.
7538 * For statistics and lock validation.
7539 * @param ... Arguments for the format string.
7540 */
7541DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7542 const char *pszNameFmt, ...)
7543{
7544 int rc;
7545 va_list va;
7546 va_start(va, pszNameFmt);
7547 rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7548 va_end(va);
7549 return rc;
7550}
7551
7552#endif /* IN_RING3 */
7553
7554/**
7555 * @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7556 */
7557DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7558{
7559 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7560}
7561
7562#ifdef IN_RING3
7563
7564/**
7565 * @copydoc PDMDEVHLPR3::pfnCritSectGetNopR0
7566 */
7567DECLINLINE(R0PTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopR0(PPDMDEVINS pDevIns)
7568{
7569 return pDevIns->pHlpR3->pfnCritSectGetNopR0(pDevIns);
7570}
7571
7572/**
7573 * @copydoc PDMDEVHLPR3::pfnCritSectGetNopRC
7574 */
7575DECLINLINE(RCPTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopRC(PPDMDEVINS pDevIns)
7576{
7577 return pDevIns->pHlpR3->pfnCritSectGetNopRC(pDevIns);
7578}
7579
7580#endif /* IN_RING3 */
7581
7582/**
7583 * @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7584 */
7585DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7586{
7587 return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7588}
7589
7590/**
7591 * @copydoc PDMCritSectEnter
7592 * @param pDevIns The device instance.
7593 */
7594DECLINLINE(int) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7595{
7596 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7597}
7598
7599/**
7600 * @copydoc PDMCritSectEnterDebug
7601 * @param pDevIns The device instance.
7602 */
7603DECLINLINE(int) PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7604{
7605 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7606}
7607
7608/**
7609 * @copydoc PDMCritSectTryEnter
7610 * @param pDevIns The device instance.
7611 */
7612DECLINLINE(int) PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7613{
7614 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7615}
7616
7617/**
7618 * @copydoc PDMCritSectTryEnterDebug
7619 * @param pDevIns The device instance.
7620 */
7621DECLINLINE(int) PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7622{
7623 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7624}
7625
7626/**
7627 * @copydoc PDMCritSectLeave
7628 * @param pDevIns The device instance.
7629 */
7630DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7631{
7632 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7633}
7634
7635/**
7636 * @copydoc PDMCritSectIsOwner
7637 * @param pDevIns The device instance.
7638 */
7639DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7640{
7641 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7642}
7643
7644/**
7645 * @copydoc PDMCritSectIsInitialized
7646 * @param pDevIns The device instance.
7647 */
7648DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7649{
7650 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
7651}
7652
7653/**
7654 * @copydoc PDMCritSectHasWaiters
7655 * @param pDevIns The device instance.
7656 */
7657DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7658{
7659 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
7660}
7661
7662/**
7663 * @copydoc PDMCritSectGetRecursion
7664 * @param pDevIns The device instance.
7665 */
7666DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7667{
7668 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
7669}
7670
7671#if defined(IN_RING3) || defined(IN_RING0)
7672/**
7673 * @copydoc PDMHCCritSectScheduleExitEvent
7674 * @param pDevIns The device instance.
7675 */
7676DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
7677{
7678 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
7679}
7680#endif
7681
7682/* Strict build: Remap the two enter calls to the debug versions. */
7683#ifdef VBOX_STRICT
7684# ifdef IPRT_INCLUDED_asm_h
7685# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7686# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7687# else
7688# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
7689# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
7690# endif
7691#endif
7692
7693#if defined(IN_RING3) || defined(DOXYGEN_RUNNING)
7694
7695/**
7696 * @copydoc PDMR3CritSectDelete
7697 * @param pDevIns The device instance.
7698 */
7699DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7700{
7701 return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
7702}
7703
7704/**
7705 * @copydoc PDMDEVHLPR3::pfnThreadCreate
7706 */
7707DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
7708 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
7709{
7710 return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
7711}
7712
7713/**
7714 * @copydoc PDMR3ThreadDestroy
7715 * @param pDevIns The device instance.
7716 */
7717DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
7718{
7719 return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
7720}
7721
7722/**
7723 * @copydoc PDMR3ThreadIAmSuspending
7724 * @param pDevIns The device instance.
7725 */
7726DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7727{
7728 return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
7729}
7730
7731/**
7732 * @copydoc PDMR3ThreadIAmRunning
7733 * @param pDevIns The device instance.
7734 */
7735DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7736{
7737 return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
7738}
7739
7740/**
7741 * @copydoc PDMR3ThreadSleep
7742 * @param pDevIns The device instance.
7743 */
7744DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
7745{
7746 return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
7747}
7748
7749/**
7750 * @copydoc PDMR3ThreadSuspend
7751 * @param pDevIns The device instance.
7752 */
7753DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7754{
7755 return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
7756}
7757
7758/**
7759 * @copydoc PDMR3ThreadResume
7760 * @param pDevIns The device instance.
7761 */
7762DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7763{
7764 return pDevIns->pHlpR3->pfnThreadResume(pThread);
7765}
7766
7767/**
7768 * @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
7769 */
7770DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
7771{
7772 return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
7773}
7774
7775/**
7776 * @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
7777 */
7778DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
7779{
7780 pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
7781}
7782
7783/**
7784 * @copydoc PDMDEVHLPR3::pfnA20Set
7785 */
7786DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
7787{
7788 pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
7789}
7790
7791/**
7792 * @copydoc PDMDEVHLPR3::pfnRTCRegister
7793 */
7794DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
7795{
7796 return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
7797}
7798
7799/**
7800 * @copydoc PDMDEVHLPR3::pfnPCIBusRegister
7801 */
7802DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus)
7803{
7804 return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
7805}
7806
7807/**
7808 * @copydoc PDMDEVHLPR3::pfnIommuRegister
7809 */
7810DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp, uint32_t *pidxIommu)
7811{
7812 return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
7813}
7814
7815/**
7816 * @copydoc PDMDEVHLPR3::pfnPICRegister
7817 */
7818DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
7819{
7820 return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
7821}
7822
7823/**
7824 * @copydoc PDMDEVHLPR3::pfnApicRegister
7825 */
7826DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
7827{
7828 return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
7829}
7830
7831/**
7832 * @copydoc PDMDEVHLPR3::pfnIoApicRegister
7833 */
7834DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
7835{
7836 return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
7837}
7838
7839/**
7840 * @copydoc PDMDEVHLPR3::pfnHpetRegister
7841 */
7842DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
7843{
7844 return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
7845}
7846
7847/**
7848 * @copydoc PDMDEVHLPR3::pfnPciRawRegister
7849 */
7850DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
7851{
7852 return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
7853}
7854
7855/**
7856 * @copydoc PDMDEVHLPR3::pfnDMACRegister
7857 */
7858DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
7859{
7860 return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
7861}
7862
7863/**
7864 * @copydoc PDMDEVHLPR3::pfnDMARegister
7865 */
7866DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
7867{
7868 return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
7869}
7870
7871/**
7872 * @copydoc PDMDEVHLPR3::pfnDMAReadMemory
7873 */
7874DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead)
7875{
7876 return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
7877}
7878
7879/**
7880 * @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
7881 */
7882DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten)
7883{
7884 return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
7885}
7886
7887/**
7888 * @copydoc PDMDEVHLPR3::pfnDMASetDREQ
7889 */
7890DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
7891{
7892 return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
7893}
7894
7895/**
7896 * @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
7897 */
7898DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
7899{
7900 return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
7901}
7902
7903/**
7904 * @copydoc PDMDEVHLPR3::pfnDMASchedule
7905 */
7906DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
7907{
7908 pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
7909}
7910
7911/**
7912 * @copydoc PDMDEVHLPR3::pfnCMOSWrite
7913 */
7914DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
7915{
7916 return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
7917}
7918
7919/**
7920 * @copydoc PDMDEVHLPR3::pfnCMOSRead
7921 */
7922DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
7923{
7924 return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
7925}
7926
7927/**
7928 * @copydoc PDMDEVHLPR3::pfnCallR0
7929 */
7930DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
7931{
7932 return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
7933}
7934
7935/**
7936 * @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
7937 */
7938DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
7939{
7940 return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
7941}
7942
7943/**
7944 * @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
7945 */
7946DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
7947{
7948 return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
7949}
7950
7951/**
7952 * @copydoc PDMDEVHLPR3::pfnGetUVM
7953 */
7954DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
7955{
7956 return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
7957}
7958
7959#endif /* IN_RING3 || DOXYGEN_RUNNING */
7960
7961#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
7962
7963/**
7964 * @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
7965 */
7966DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
7967{
7968 return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
7969}
7970
7971/**
7972 * @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
7973 */
7974DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
7975{
7976 return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
7977}
7978
7979/**
7980 * @copydoc PDMDEVHLPR0::pfnPICSetUpContext
7981 */
7982DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
7983{
7984 return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
7985}
7986
7987/**
7988 * @copydoc PDMDEVHLPR0::pfnApicSetUpContext
7989 */
7990DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
7991{
7992 return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
7993}
7994
7995/**
7996 * @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
7997 */
7998DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
7999{
8000 return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
8001}
8002
8003/**
8004 * @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
8005 */
8006DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
8007{
8008 return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
8009}
8010
8011#endif /* !IN_RING3 || DOXYGEN_RUNNING */
8012
8013/**
8014 * @copydoc PDMDEVHLPR3::pfnGetVM
8015 */
8016DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
8017{
8018 return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
8019}
8020
8021/**
8022 * @copydoc PDMDEVHLPR3::pfnGetVMCPU
8023 */
8024DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
8025{
8026 return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
8027}
8028
8029/**
8030 * @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
8031 */
8032DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
8033{
8034 return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
8035}
8036
8037/**
8038 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
8039 */
8040DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
8041{
8042 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
8043}
8044
8045/**
8046 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8047 */
8048DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8049{
8050 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8051}
8052
8053/**
8054 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8055 */
8056DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8057{
8058 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8059}
8060
8061#ifdef IN_RING3
8062
8063/**
8064 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8065 */
8066DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8067{
8068 return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
8069}
8070
8071/**
8072 * @copydoc PDMDEVHLPR3::pfnFirmwareRegister
8073 */
8074DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
8075{
8076 return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
8077}
8078
8079/**
8080 * @copydoc PDMDEVHLPR3::pfnVMReset
8081 */
8082DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
8083{
8084 return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
8085}
8086
8087/**
8088 * @copydoc PDMDEVHLPR3::pfnVMSuspend
8089 */
8090DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8091{
8092 return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8093}
8094
8095/**
8096 * @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8097 */
8098DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8099{
8100 return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8101}
8102
8103/**
8104 * @copydoc PDMDEVHLPR3::pfnVMPowerOff
8105 */
8106DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8107{
8108 return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8109}
8110
8111#endif /* IN_RING3 */
8112
8113/**
8114 * @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8115 */
8116DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8117{
8118 return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8119}
8120
8121#ifdef IN_RING3
8122
8123/**
8124 * @copydoc PDMDEVHLPR3::pfnGetCpuId
8125 */
8126DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
8127{
8128 pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8129}
8130
8131/**
8132 * @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8133 */
8134DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8135{
8136 return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8137}
8138
8139/**
8140 * @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8141 */
8142DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8143{
8144 return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8145}
8146
8147/**
8148 * @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
8149 */
8150DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
8151 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
8152 const char *pszHandlerR0, const char *pszPfHandlerR0,
8153 const char *pszHandlerRC, const char *pszPfHandlerRC,
8154 const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
8155{
8156 return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
8157 pszHandlerR0, pszPfHandlerR0,
8158 pszHandlerRC, pszPfHandlerRC,
8159 pszDesc, phType);
8160}
8161
8162/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
8163# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8164 do { \
8165 uint32_t u32GetEnumTmp = 0; \
8166 int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
8167 AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8168 (a_enmDst) = (a_EnumType)u32GetEnumTmp; \
8169 AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
8170 } while (0)
8171
8172/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
8173# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8174 do { \
8175 uint8_t bGetEnumTmp = 0; \
8176 int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
8177 AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8178 (a_enmDst) = (a_EnumType)bGetEnumTmp; \
8179 } while (0)
8180
8181#endif /* IN_RING3 */
8182
8183/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
8184typedef struct PDMDEVREGCB *PPDMDEVREGCB;
8185
8186/**
8187 * Callbacks for VBoxDeviceRegister().
8188 */
8189typedef struct PDMDEVREGCB
8190{
8191 /** Interface version.
8192 * This is set to PDM_DEVREG_CB_VERSION. */
8193 uint32_t u32Version;
8194
8195 /**
8196 * Registers a device with the current VM instance.
8197 *
8198 * @returns VBox status code.
8199 * @param pCallbacks Pointer to the callback table.
8200 * @param pReg Pointer to the device registration record.
8201 * This data must be permanent and readonly.
8202 */
8203 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
8204} PDMDEVREGCB;
8205
8206/** Current version of the PDMDEVREGCB structure. */
8207#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
8208
8209
8210/**
8211 * The VBoxDevicesRegister callback function.
8212 *
8213 * PDM will invoke this function after loading a device module and letting
8214 * the module decide which devices to register and how to handle conflicts.
8215 *
8216 * @returns VBox status code.
8217 * @param pCallbacks Pointer to the callback table.
8218 * @param u32Version VBox version number.
8219 */
8220typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
8221
8222/** @} */
8223
8224RT_C_DECLS_END
8225
8226#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */
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