pdmdev.h@ 81850

Last change on this file since 81850 was 81850, checked in by vboxsync, 5 years ago
PDMDevHlp: Adding PDMDevHlpCritSectScheduleExitEvent. bugref:9218
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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmqueue.h>
34	#include <VBox/vmm/pdmtask.h>
35	#ifdef IN_RING3
36	# include <VBox/vmm/pdmthread.h>
37	#endif
38	#include <VBox/vmm/pdmifs.h>
39	#include <VBox/vmm/pdmins.h>
40	#include <VBox/vmm/pdmcommon.h>
41	#include <VBox/vmm/pdmpcidev.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/tm.h>
44	#include <VBox/vmm/ssm.h>
45	#include <VBox/vmm/cfgm.h>
46	#include <VBox/vmm/dbgf.h>
47	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
48	#include <iprt/stdarg.h>
49	#include <iprt/list.h>
50
51
52	RT_C_DECLS_BEGIN
53
54	/** @defgroup grp_pdm_device The PDM Devices API
55	* @ingroup grp_pdm
56	* @{
57	*/
58
59	/**
60	* Construct a device instance for a VM.
61	*
62	* @returns VBox status.
63	* @param pDevIns The device instance data. If the registration structure
64	* is needed, it can be accessed thru pDevIns->pReg.
65	* @param iInstance Instance number. Use this to figure out which registers
66	* and such to use. The instance number is also found in
67	* pDevIns->iInstance, but since it's likely to be
68	* frequently used PDM passes it as parameter.
69	* @param pCfg Configuration node handle for the driver. This is
70	* expected to be in high demand in the constructor and is
71	* therefore passed as an argument. When using it at other
72	* times, it can be found in pDevIns->pCfg.
73	*/
74	typedef DECLCALLBACK(int) FNPDMDEVCONSTRUCT(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg);
75	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
76	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
77
78	/**
79	* Destruct a device instance.
80	*
81	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
82	* resources can be freed correctly.
83	*
84	* @returns VBox status.
85	* @param pDevIns The device instance data.
86	*
87	* @remarks The device critical section is not entered. The routine may delete
88	* the critical section, so the caller cannot exit it.
89	*/
90	typedef DECLCALLBACK(int) FNPDMDEVDESTRUCT(PPDMDEVINS pDevIns);
91	/** Pointer to a FNPDMDEVDESTRUCT() function. */
92	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
93
94	/**
95	* Device relocation callback.
96	*
97	* This is called when the instance data has been relocated in raw-mode context
98	* (RC). It is also called when the RC hypervisor selects changes. The device
99	* must fixup all necessary pointers and re-query all interfaces to other RC
100	* devices and drivers.
101	*
102	* Before the RC code is executed the first time, this function will be called
103	* with a 0 delta so RC pointer calculations can be one in one place.
104	*
105	* @param pDevIns Pointer to the device instance.
106	* @param offDelta The relocation delta relative to the old location.
107	*
108	* @remarks A relocation CANNOT fail.
109	*
110	* @remarks The device critical section is not entered. The relocations should
111	* not normally require any locking.
112	*/
113	typedef DECLCALLBACK(void) FNPDMDEVRELOCATE(PPDMDEVINS pDevIns, RTGCINTPTR offDelta);
114	/** Pointer to a FNPDMDEVRELOCATE() function. */
115	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
116
117	/**
118	* Power On notification.
119	*
120	* @returns VBox status.
121	* @param pDevIns The device instance data.
122	*
123	* @remarks Caller enters the device critical section.
124	*/
125	typedef DECLCALLBACK(void) FNPDMDEVPOWERON(PPDMDEVINS pDevIns);
126	/** Pointer to a FNPDMDEVPOWERON() function. */
127	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
128
129	/**
130	* Reset notification.
131	*
132	* @returns VBox status.
133	* @param pDevIns The device instance data.
134	*
135	* @remarks Caller enters the device critical section.
136	*/
137	typedef DECLCALLBACK(void) FNPDMDEVRESET(PPDMDEVINS pDevIns);
138	/** Pointer to a FNPDMDEVRESET() function. */
139	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
140
141	/**
142	* Soft reset notification.
143	*
144	* This is mainly for emulating the 286 style protected mode exits, in which
145	* most devices should remain in their current state.
146	*
147	* @returns VBox status.
148	* @param pDevIns The device instance data.
149	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
150	*
151	* @remarks Caller enters the device critical section.
152	*/
153	typedef DECLCALLBACK(void) FNPDMDEVSOFTRESET(PPDMDEVINS pDevIns, uint32_t fFlags);
154	/** Pointer to a FNPDMDEVSOFTRESET() function. */
155	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
156
157	/** @name PDMVMRESET_F_XXX - VM reset flags.
158	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
159	* reset via PDMDevHlpVMReset.
160	* @{ */
161	/** Unknown reason. */
162	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
163	/** GIM triggered reset. */
164	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
165	/** The last source always causing hard resets. */
166	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
167	/** ACPI triggered reset. */
168	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
169	/** PS/2 system port A (92h) reset. */
170	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
171	/** Keyboard reset. */
172	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
173	/** Tripple fault. */
174	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
175	/** Reset source mask. */
176	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
177	/** @} */
178
179	/**
180	* Suspend notification.
181	*
182	* @returns VBox status.
183	* @param pDevIns The device instance data.
184	* @thread EMT(0)
185	*
186	* @remarks Caller enters the device critical section.
187	*/
188	typedef DECLCALLBACK(void) FNPDMDEVSUSPEND(PPDMDEVINS pDevIns);
189	/** Pointer to a FNPDMDEVSUSPEND() function. */
190	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
191
192	/**
193	* Resume notification.
194	*
195	* @returns VBox status.
196	* @param pDevIns The device instance data.
197	*
198	* @remarks Caller enters the device critical section.
199	*/
200	typedef DECLCALLBACK(void) FNPDMDEVRESUME(PPDMDEVINS pDevIns);
201	/** Pointer to a FNPDMDEVRESUME() function. */
202	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
203
204	/**
205	* Power Off notification.
206	*
207	* This is always called when VMR3PowerOff is called.
208	* There will be no callback when hot plugging devices.
209	*
210	* @param pDevIns The device instance data.
211	* @thread EMT(0)
212	*
213	* @remarks Caller enters the device critical section.
214	*/
215	typedef DECLCALLBACK(void) FNPDMDEVPOWEROFF(PPDMDEVINS pDevIns);
216	/** Pointer to a FNPDMDEVPOWEROFF() function. */
217	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
218
219	/**
220	* Attach command.
221	*
222	* This is called to let the device attach to a driver for a specified LUN
223	* at runtime. This is not called during VM construction, the device
224	* constructor has to attach to all the available drivers.
225	*
226	* This is like plugging in the keyboard or mouse after turning on the PC.
227	*
228	* @returns VBox status code.
229	* @param pDevIns The device instance.
230	* @param iLUN The logical unit which is being attached.
231	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
232	*
233	* @remarks Caller enters the device critical section.
234	*/
235	typedef DECLCALLBACK(int) FNPDMDEVATTACH(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags);
236	/** Pointer to a FNPDMDEVATTACH() function. */
237	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
238
239	/**
240	* Detach notification.
241	*
242	* This is called when a driver is detaching itself from a LUN of the device.
243	* The device should adjust its state to reflect this.
244	*
245	* This is like unplugging the network cable to use it for the laptop or
246	* something while the PC is still running.
247	*
248	* @param pDevIns The device instance.
249	* @param iLUN The logical unit which is being detached.
250	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
251	*
252	* @remarks Caller enters the device critical section.
253	*/
254	typedef DECLCALLBACK(void) FNPDMDEVDETACH(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags);
255	/** Pointer to a FNPDMDEVDETACH() function. */
256	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
257
258	/**
259	* Query the base interface of a logical unit.
260	*
261	* @returns VBOX status code.
262	* @param pDevIns The device instance.
263	* @param iLUN The logicial unit to query.
264	* @param ppBase Where to store the pointer to the base interface of the LUN.
265	*
266	* @remarks The device critical section is not entered.
267	*/
268	typedef DECLCALLBACK(int) FNPDMDEVQUERYINTERFACE(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase);
269	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
270	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
271
272	/**
273	* Init complete notification (after ring-0 & RC init since 5.1).
274	*
275	* This can be done to do communication with other devices and other
276	* initialization which requires everything to be in place.
277	*
278	* @returns VBOX status code.
279	* @param pDevIns The device instance.
280	*
281	* @remarks Caller enters the device critical section.
282	*/
283	typedef DECLCALLBACK(int) FNPDMDEVINITCOMPLETE(PPDMDEVINS pDevIns);
284	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
285	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
286
287
288	/**
289	* The context of a pfnMemSetup call.
290	*/
291	typedef enum PDMDEVMEMSETUPCTX
292	{
293	/** Invalid zero value. */
294	PDMDEVMEMSETUPCTX_INVALID = 0,
295	/** After construction. */
296	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
297	/** After reset. */
298	PDMDEVMEMSETUPCTX_AFTER_RESET,
299	/** Type size hack. */
300	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
301	} PDMDEVMEMSETUPCTX;
302
303
304	/**
305	* PDM Device Registration Structure.
306	*
307	* This structure is used when registering a device from VBoxInitDevices() in HC
308	* Ring-3. PDM will continue use till the VM is terminated.
309	*
310	* @note The first part is the same in every context.
311	*/
312	typedef struct PDMDEVREGR3
313	{
314	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
315	uint32_t u32Version;
316	/** Reserved, must be zero. */
317	uint32_t uReserved0;
318	/** Device name, must match the ring-3 one. */
319	char szName[32];
320	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
321	uint32_t fFlags;
322	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
323	uint32_t fClass;
324	/** Maximum number of instances (per VM). */
325	uint32_t cMaxInstances;
326	/** The shared data structure version number. */
327	uint32_t uSharedVersion;
328	/** Size of the instance data. */
329	uint32_t cbInstanceShared;
330	/** Size of the ring-0 instance data. */
331	uint32_t cbInstanceCC;
332	/** Size of the raw-mode instance data. */
333	uint32_t cbInstanceRC;
334	/** Max number of PCI devices. */
335	uint16_t cMaxPciDevices;
336	/** Max number of MSI-X vectors in any of the PCI devices. */
337	uint16_t cMaxMsixVectors;
338	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
339	* remain unchanged from registration till VM destruction. */
340	const char *pszDescription;
341
342	/** Name of the raw-mode context module (no path).
343	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
344	const char *pszRCMod;
345	/** Name of the ring-0 module (no path).
346	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
347	const char *pszR0Mod;
348
349	/** Construct instance - required. */
350	PFNPDMDEVCONSTRUCT pfnConstruct;
351	/** Destruct instance - optional.
352	* Critical section NOT entered (will be destroyed). */
353	PFNPDMDEVDESTRUCT pfnDestruct;
354	/** Relocation command - optional.
355	* Critical section NOT entered. */
356	PFNPDMDEVRELOCATE pfnRelocate;
357	/**
358	* Memory setup callback.
359	*
360	* @param pDevIns The device instance data.
361	* @param enmCtx Indicates the context of the call.
362	* @remarks The critical section is entered prior to calling this method.
363	*/
364	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
365	/** Power on notification - optional.
366	* Critical section is entered. */
367	PFNPDMDEVPOWERON pfnPowerOn;
368	/** Reset notification - optional.
369	* Critical section is entered. */
370	PFNPDMDEVRESET pfnReset;
371	/** Suspend notification - optional.
372	* Critical section is entered. */
373	PFNPDMDEVSUSPEND pfnSuspend;
374	/** Resume notification - optional.
375	* Critical section is entered. */
376	PFNPDMDEVRESUME pfnResume;
377	/** Attach command - optional.
378	* Critical section is entered. */
379	PFNPDMDEVATTACH pfnAttach;
380	/** Detach notification - optional.
381	* Critical section is entered. */
382	PFNPDMDEVDETACH pfnDetach;
383	/** Query a LUN base interface - optional.
384	* Critical section is NOT entered. */
385	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
386	/** Init complete notification - optional.
387	* Critical section is entered. */
388	PFNPDMDEVINITCOMPLETE pfnInitComplete;
389	/** Power off notification - optional.
390	* Critical section is entered. */
391	PFNPDMDEVPOWEROFF pfnPowerOff;
392	/** Software system reset notification - optional.
393	* Critical section is entered. */
394	PFNPDMDEVSOFTRESET pfnSoftReset;
395
396	/** @name Reserved for future extensions, must be zero.
397	* @{ */
398	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
399	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
400	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
401	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
402	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
403	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
406	/** @} */
407
408	/** Initialization safty marker. */
409	uint32_t u32VersionEnd;
410	} PDMDEVREGR3;
411	/** Pointer to a PDM Device Structure. */
412	typedef PDMDEVREGR3 *PPDMDEVREGR3;
413	/** Const pointer to a PDM Device Structure. */
414	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
415	/** Current DEVREGR3 version number. */
416	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
417
418
419	/** PDM Device Flags.
420	* @{ */
421	/** This flag is used to indicate that the device has a R0 component. */
422	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
423	/** Requires the ring-0 component, ignore configuration values. */
424	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
425	/** Requires the ring-0 component, ignore configuration values. */
426	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
427
428	/** This flag is used to indicate that the device has a RC component. */
429	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
430	/** Requires the raw-mode component, ignore configuration values. */
431	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
432	/** Requires the raw-mode component, ignore configuration values. */
433	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
434
435	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
436	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
437
438	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
439	* The bit count for the current host.
440	* @note Superfluous, but still around for hysterical raisins. */
441	#if HC_ARCH_BITS == 32
442	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
443	#elif HC_ARCH_BITS == 64
444	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
445	#else
446	# error Unsupported HC_ARCH_BITS value.
447	#endif
448	/** The host bit count mask. */
449	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
450
451	/** The device support only 32-bit guests. */
452	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
453	/** The device support only 64-bit guests. */
454	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
455	/** The device support both 32-bit & 64-bit guests. */
456	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
457	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
458	* The guest bit count for the current compilation. */
459	#if GC_ARCH_BITS == 32
460	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
461	#elif GC_ARCH_BITS == 64
462	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
463	#else
464	# error Unsupported GC_ARCH_BITS value.
465	#endif
466	/** The guest bit count mask. */
467	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
468
469	/** A convenience. */
470	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
471
472	/** Indicates that the device needs to be notified before the drivers when suspending. */
473	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
474	/** Indicates that the device needs to be notified before the drivers when powering off. */
475	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
476	/** Indicates that the device needs to be notified before the drivers when resetting. */
477	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
478
479	/** This flag is used to indicate that the device has been converted to the
480	* new device style. */
481	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
482
483	/** @} */
484
485
486	/** PDM Device Classes.
487	* The order is important, lower bit earlier instantiation.
488	* @{ */
489	/** Architecture device. */
490	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
491	/** Architecture BIOS device. */
492	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
493	/** PCI bus brigde. */
494	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
495	/** ISA bus brigde. */
496	#define PDM_DEVREG_CLASS_BUS_ISA RT_BIT(3)
497	/** Input device (mouse, keyboard, joystick, HID, ...). */
498	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
499	/** Interrupt controller (PIC). */
500	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
501	/** Interval controoler (PIT). */
502	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
503	/** RTC/CMOS. */
504	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
505	/** DMA controller. */
506	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
507	/** VMM Device. */
508	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
509	/** Graphics device, like VGA. */
510	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
511	/** Storage controller device. */
512	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
513	/** Network interface controller. */
514	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
515	/** Audio. */
516	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
517	/** USB HIC. */
518	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
519	/** ACPI. */
520	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
521	/** Serial controller device. */
522	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
523	/** Parallel controller device */
524	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
525	/** Host PCI pass-through device */
526	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
527	/** Misc devices (always last). */
528	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
529	/** @} */
530
531
532	/**
533	* PDM Device Registration Structure, ring-0.
534	*
535	* This structure is used when registering a device from VBoxInitDevices() in HC
536	* Ring-0. PDM will continue use till the VM is terminated.
537	*/
538	typedef struct PDMDEVREGR0
539	{
540	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
541	uint32_t u32Version;
542	/** Reserved, must be zero. */
543	uint32_t uReserved0;
544	/** Device name, must match the ring-3 one. */
545	char szName[32];
546	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
547	uint32_t fFlags;
548	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
549	uint32_t fClass;
550	/** Maximum number of instances (per VM). */
551	uint32_t cMaxInstances;
552	/** The shared data structure version number. */
553	uint32_t uSharedVersion;
554	/** Size of the instance data. */
555	uint32_t cbInstanceShared;
556	/** Size of the ring-0 instance data. */
557	uint32_t cbInstanceCC;
558	/** Size of the raw-mode instance data. */
559	uint32_t cbInstanceRC;
560	/** Max number of PCI devices. */
561	uint16_t cMaxPciDevices;
562	/** Max number of MSI-X vectors in any of the PCI devices. */
563	uint16_t cMaxMsixVectors;
564	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
565	* remain unchanged from registration till VM destruction. */
566	const char *pszDescription;
567
568	/**
569	* Early construction callback (optional).
570	*
571	* This is called right after the device instance structure has been allocated
572	* and before the ring-3 constructor gets called.
573	*
574	* @returns VBox status code.
575	* @param pDevIns The device instance data.
576	* @note The destructure is always called, regardless of the return status.
577	*/
578	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
579
580	/**
581	* Regular construction callback (optional).
582	*
583	* This is called after (or during) the ring-3 constructor.
584	*
585	* @returns VBox status code.
586	* @param pDevIns The device instance data.
587	* @note The destructure is always called, regardless of the return status.
588	*/
589	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
590
591	/**
592	* Destructor (optional).
593	*
594	* This is called after the ring-3 destruction. This is not called if ring-3
595	* fails to trigger it (e.g. process is killed or crashes).
596	*
597	* @param pDevIns The device instance data.
598	*/
599	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
600
601	/**
602	* Final destructor (optional).
603	*
604	* This is called right before the memory is freed, which happens when the
605	* VM/GVM object is destroyed. This is always called.
606	*
607	* @param pDevIns The device instance data.
608	*/
609	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
610
611	/**
612	* Generic request handler (optional).
613	*
614	* @param pDevIns The device instance data.
615	* @param uReq Device specific request.
616	* @param uArg Request argument.
617	*/
618	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
619
620	/** @name Reserved for future extensions, must be zero.
621	* @{ */
622	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
623	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
624	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
625	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
626	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
627	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
630	/** @} */
631
632	/** Initialization safty marker. */
633	uint32_t u32VersionEnd;
634	} PDMDEVREGR0;
635	/** Pointer to a ring-0 PDM device registration structure. */
636	typedef PDMDEVREGR0 *PPDMDEVREGR0;
637	/** Pointer to a const ring-0 PDM device registration structure. */
638	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
639	/** Current DEVREGR0 version number. */
640	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
641
642
643	/**
644	* PDM Device Registration Structure, raw-mode
645	*
646	* At the moment, this structure is mostly here to match the other two contexts.
647	*/
648	typedef struct PDMDEVREGRC
649	{
650	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
651	uint32_t u32Version;
652	/** Reserved, must be zero. */
653	uint32_t uReserved0;
654	/** Device name, must match the ring-3 one. */
655	char szName[32];
656	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
657	uint32_t fFlags;
658	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
659	uint32_t fClass;
660	/** Maximum number of instances (per VM). */
661	uint32_t cMaxInstances;
662	/** The shared data structure version number. */
663	uint32_t uSharedVersion;
664	/** Size of the instance data. */
665	uint32_t cbInstanceShared;
666	/** Size of the ring-0 instance data. */
667	uint32_t cbInstanceCC;
668	/** Size of the raw-mode instance data. */
669	uint32_t cbInstanceRC;
670	/** Max number of PCI devices. */
671	uint16_t cMaxPciDevices;
672	/** Max number of MSI-X vectors in any of the PCI devices. */
673	uint16_t cMaxMsixVectors;
674	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
675	* remain unchanged from registration till VM destruction. */
676	const char *pszDescription;
677
678	/**
679	* Constructor callback.
680	*
681	* This is called much later than both the ring-0 and ring-3 constructors, since
682	* raw-mode v2 require a working VMM to run actual code.
683	*
684	* @returns VBox status code.
685	* @param pDevIns The device instance data.
686	* @note The destructure is always called, regardless of the return status.
687	*/
688	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
689
690	/** @name Reserved for future extensions, must be zero.
691	* @{ */
692	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
693	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
694	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
695	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
696	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
697	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
700	/** @} */
701
702	/** Initialization safty marker. */
703	uint32_t u32VersionEnd;
704	} PDMDEVREGRC;
705	/** Pointer to a raw-mode PDM device registration structure. */
706	typedef PDMDEVREGRC *PPDMDEVREGRC;
707	/** Pointer to a const raw-mode PDM device registration structure. */
708	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
709	/** Current DEVREGRC version number. */
710	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
711
712
713
714	/** @def PDM_DEVREG_VERSION
715	* Current DEVREG version number. */
716	/** @typedef PDMDEVREGR3
717	* A current context PDM device registration structure. */
718	/** @typedef PPDMDEVREGR3
719	* Pointer to a current context PDM device registration structure. */
720	/** @typedef PCPDMDEVREGR3
721	* Pointer to a const current context PDM device registration structure. */
722	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
723	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
724	typedef PDMDEVREGR3 PDMDEVREG;
725	typedef PPDMDEVREGR3 PPDMDEVREG;
726	typedef PCPDMDEVREGR3 PCPDMDEVREG;
727	#elif defined(IN_RING0)
728	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
729	typedef PDMDEVREGR0 PDMDEVREG;
730	typedef PPDMDEVREGR0 PPDMDEVREG;
731	typedef PCPDMDEVREGR0 PCPDMDEVREG;
732	#elif defined(IN_RC)
733	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
734	typedef PDMDEVREGRC PDMDEVREG;
735	typedef PPDMDEVREGRC PPDMDEVREG;
736	typedef PCPDMDEVREGRC PCPDMDEVREG;
737	#else
738	# error "Not IN_RING3, IN_RING0 or IN_RC"
739	#endif
740
741
742	/**
743	* Device registrations for ring-0 modules.
744	*
745	* This structure is used directly and must therefore reside in persistent
746	* memory (i.e. the data section).
747	*/
748	typedef struct PDMDEVMODREGR0
749	{
750	/** The structure version (PDM_DEVMODREGR0_VERSION). */
751	uint32_t u32Version;
752	/** Number of devices in the array papDevRegs points to. */
753	uint32_t cDevRegs;
754	/** Pointer to device registration structures. */
755	PCPDMDEVREGR0 *papDevRegs;
756	/** The ring-0 module handle - PDM internal, fingers off. */
757	void *hMod;
758	/** List entry - PDM internal, fingers off. */
759	RTLISTNODE ListEntry;
760	} PDMDEVMODREGR0;
761	/** Pointer to device registriations for a ring-0 module. */
762	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
763	/** Current PDMDEVMODREGR0 version number. */
764	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
765
766
767	/** @name IRQ Level for use with the *SetIrq APIs.
768	* @{
769	*/
770	/** Assert the IRQ (can assume value 1). */
771	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
772	/** Deassert the IRQ (can assume value 0). */
773	#define PDM_IRQ_LEVEL_LOW 0
774	/** flip-flop - deassert and then assert the IRQ again immediately. */
775	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
776	/** @} */
777
778	/**
779	* Registration record for MSI/MSI-X emulation.
780	*/
781	typedef struct PDMMSIREG
782	{
783	/** Number of MSI interrupt vectors, 0 if MSI not supported */
784	uint16_t cMsiVectors;
785	/** Offset of MSI capability */
786	uint8_t iMsiCapOffset;
787	/** Offset of next capability to MSI */
788	uint8_t iMsiNextOffset;
789	/** If we support 64-bit MSI addressing */
790	bool fMsi64bit;
791	/** If we do not support per-vector masking */
792	bool fMsiNoMasking;
793
794	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
795	uint16_t cMsixVectors;
796	/** Offset of MSI-X capability */
797	uint8_t iMsixCapOffset;
798	/** Offset of next capability to MSI-X */
799	uint8_t iMsixNextOffset;
800	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
801	uint8_t iMsixBar;
802	} PDMMSIREG;
803	typedef PDMMSIREG *PPDMMSIREG;
804
805	/**
806	* PCI Bus registration structure.
807	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
808	*/
809	typedef struct PDMPCIBUSREGR3
810	{
811	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
812	uint32_t u32Version;
813
814	/**
815	* Registers the device with the default PCI bus.
816	*
817	* @returns VBox status code.
818	* @param pDevIns Device instance of the PCI Bus.
819	* @param pPciDev The PCI device structure.
820	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
821	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
822	* device number (0-31).
823	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
824	* function number (0-7).
825	* @param pszName Device name (static but not unique).
826	*
827	* @remarks Caller enters the PDM critical section.
828	*/
829	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
830	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
831
832	/**
833	* Initialize MSI or MSI-X emulation support in a PCI device.
834	*
835	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
836	* vast majority of device emulation it covers everything necessary. It's
837	* fully automatic, taking care of all BAR and config space requirements,
838	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
839	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
840	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
841	*
842	* A device not using this can still offer MSI/MSI-X. In this case it's
843	* completely up to the device (in the MSI-X case) to create/register the
844	* necessary MMIO BAR, handle all config space/BAR updating and take care
845	* of delivering the interrupts appropriately.
846	*
847	* @returns VBox status code.
848	* @param pDevIns Device instance of the PCI Bus.
849	* @param pPciDev The PCI device structure.
850	* @param pMsiReg MSI emulation registration structure
851	* @remarks Caller enters the PDM critical section.
852	*/
853	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
854
855	/**
856	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
857	*
858	* @returns VBox status code.
859	* @param pDevIns Device instance of the PCI Bus.
860	* @param pPciDev The PCI device structure.
861	* @param iRegion The region number.
862	* @param cbRegion Size of the region.
863	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
864	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
865	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
866	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
867	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
868	* @a fFlags, UINT64_MAX if no handle is passed
869	* (old style).
870	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
871	* is given.
872	* @remarks Caller enters the PDM critical section.
873	*/
874	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
875	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
876	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
877
878	/**
879	* Register PCI configuration space read/write intercept callbacks.
880	*
881	* @param pDevIns Device instance of the PCI Bus.
882	* @param pPciDev The PCI device structure.
883	* @param pfnRead Pointer to the user defined PCI config read function.
884	* @param pfnWrite Pointer to the user defined PCI config write function.
885	* to call default PCI config write function. Can be NULL.
886	* @remarks Caller enters the PDM critical section.
887	* @thread EMT
888	*/
889	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
890	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
891
892	/**
893	* Perform a PCI configuration space write, bypassing interception.
894	*
895	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
896	*
897	* @returns Strict VBox status code (mainly DBGFSTOP).
898	* @param pDevIns Device instance of the PCI Bus.
899	* @param pPciDev The PCI device which config space is being read.
900	* @param uAddress The config space address.
901	* @param cb The size of the read: 1, 2 or 4 bytes.
902	* @param u32Value The value to write.
903	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
904	* that the (root) bus will have done that already.
905	*/
906	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
907	uint32_t uAddress, unsigned cb, uint32_t u32Value));
908
909	/**
910	* Perform a PCI configuration space read, bypassing interception.
911	*
912	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
913	*
914	* @returns Strict VBox status code (mainly DBGFSTOP).
915	* @param pDevIns Device instance of the PCI Bus.
916	* @param pPciDev The PCI device which config space is being read.
917	* @param uAddress The config space address.
918	* @param cb The size of the read: 1, 2 or 4 bytes.
919	* @param pu32Value Where to return the value.
920	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
921	* that the (root) bus will have done that already.
922	*/
923	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
924	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
925
926	/**
927	* Set the IRQ for a PCI device.
928	*
929	* @param pDevIns Device instance of the PCI Bus.
930	* @param pPciDev The PCI device structure.
931	* @param iIrq IRQ number to set.
932	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
933	* @param uTagSrc The IRQ tag and source (for tracing).
934	* @remarks Caller enters the PDM critical section.
935	*/
936	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
937
938	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
939	uint32_t u32EndVersion;
940	} PDMPCIBUSREGR3;
941	/** Pointer to a PCI bus registration structure. */
942	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
943	/** Current PDMPCIBUSREGR3 version number. */
944	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
945
946	/**
947	* PCI Bus registration structure for ring-0.
948	*/
949	typedef struct PDMPCIBUSREGR0
950	{
951	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
952	uint32_t u32Version;
953	/** The PCI bus number (from ring-3 registration). */
954	uint32_t iBus;
955	/**
956	* Set the IRQ for a PCI device.
957	*
958	* @param pDevIns Device instance of the PCI Bus.
959	* @param pPciDev The PCI device structure.
960	* @param iIrq IRQ number to set.
961	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
962	* @param uTagSrc The IRQ tag and source (for tracing).
963	* @remarks Caller enters the PDM critical section.
964	*/
965	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
966	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
967	uint32_t u32EndVersion;
968	} PDMPCIBUSREGR0;
969	/** Pointer to a PCI bus ring-0 registration structure. */
970	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
971	/** Current PDMPCIBUSREGR0 version number. */
972	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
973
974	/**
975	* PCI Bus registration structure for raw-mode.
976	*/
977	typedef struct PDMPCIBUSREGRC
978	{
979	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
980	uint32_t u32Version;
981	/** The PCI bus number (from ring-3 registration). */
982	uint32_t iBus;
983	/**
984	* Set the IRQ for a PCI device.
985	*
986	* @param pDevIns Device instance of the PCI Bus.
987	* @param pPciDev The PCI device structure.
988	* @param iIrq IRQ number to set.
989	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
990	* @param uTagSrc The IRQ tag and source (for tracing).
991	* @remarks Caller enters the PDM critical section.
992	*/
993	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
994	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
995	uint32_t u32EndVersion;
996	} PDMPCIBUSREGRC;
997	/** Pointer to a PCI bus raw-mode registration structure. */
998	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
999	/** Current PDMPCIBUSREGRC version number. */
1000	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1001
1002	/** PCI bus registration structure for the current context. */
1003	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1004	/** Pointer to a PCI bus registration structure for the current context. */
1005	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1006	/** PCI bus registration structure version for the current context. */
1007	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1008
1009
1010	/**
1011	* PCI Bus RC helpers.
1012	*/
1013	typedef struct PDMPCIHLPRC
1014	{
1015	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1016	uint32_t u32Version;
1017
1018	/**
1019	* Set an ISA IRQ.
1020	*
1021	* @param pDevIns PCI device instance.
1022	* @param iIrq IRQ number to set.
1023	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1024	* @param uTagSrc The IRQ tag and source (for tracing).
1025	* @thread EMT only.
1026	*/
1027	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1028
1029	/**
1030	* Set an I/O-APIC IRQ.
1031	*
1032	* @param pDevIns PCI device instance.
1033	* @param iIrq IRQ number to set.
1034	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1035	* @param uTagSrc The IRQ tag and source (for tracing).
1036	* @thread EMT only.
1037	*/
1038	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1039
1040	/**
1041	* Send an MSI.
1042	*
1043	* @param pDevIns PCI device instance.
1044	* @param GCPhys Physical address MSI request was written.
1045	* @param uValue Value written.
1046	* @param uTagSrc The IRQ tag and source (for tracing).
1047	* @thread EMT only.
1048	*/
1049	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1050
1051
1052	/**
1053	* Acquires the PDM lock.
1054	*
1055	* @returns VINF_SUCCESS on success.
1056	* @returns rc if we failed to acquire the lock.
1057	* @param pDevIns The PCI device instance.
1058	* @param rc What to return if we fail to acquire the lock.
1059	*/
1060	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1061
1062	/**
1063	* Releases the PDM lock.
1064	*
1065	* @param pDevIns The PCI device instance.
1066	*/
1067	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1068
1069	/**
1070	* Gets a bus by it's PDM ordinal (typically the parent bus).
1071	*
1072	* @returns Pointer to the device instance of the bus.
1073	* @param pDevIns The PCI bus device instance.
1074	* @param idxPdmBus The PDM ordinal value of the bus to get.
1075	*/
1076	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1077
1078	/** Just a safety precaution. */
1079	uint32_t u32TheEnd;
1080	} PDMPCIHLPRC;
1081	/** Pointer to PCI helpers. */
1082	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1083	/** Pointer to const PCI helpers. */
1084	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1085
1086	/** Current PDMPCIHLPRC version number. */
1087	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 3, 0)
1088
1089
1090	/**
1091	* PCI Bus R0 helpers.
1092	*/
1093	typedef struct PDMPCIHLPR0
1094	{
1095	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1096	uint32_t u32Version;
1097
1098	/**
1099	* Set an ISA IRQ.
1100	*
1101	* @param pDevIns PCI device instance.
1102	* @param iIrq IRQ number to set.
1103	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1104	* @param uTagSrc The IRQ tag and source (for tracing).
1105	* @thread EMT only.
1106	*/
1107	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1108
1109	/**
1110	* Set an I/O-APIC IRQ.
1111	*
1112	* @param pDevIns PCI device instance.
1113	* @param iIrq IRQ number to set.
1114	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1115	* @param uTagSrc The IRQ tag and source (for tracing).
1116	* @thread EMT only.
1117	*/
1118	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1119
1120	/**
1121	* Send an MSI.
1122	*
1123	* @param pDevIns PCI device instance.
1124	* @param GCPhys Physical address MSI request was written.
1125	* @param uValue Value written.
1126	* @param uTagSrc The IRQ tag and source (for tracing).
1127	* @thread EMT only.
1128	*/
1129	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1130
1131	/**
1132	* Acquires the PDM lock.
1133	*
1134	* @returns VINF_SUCCESS on success.
1135	* @returns rc if we failed to acquire the lock.
1136	* @param pDevIns The PCI device instance.
1137	* @param rc What to return if we fail to acquire the lock.
1138	*/
1139	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1140
1141	/**
1142	* Releases the PDM lock.
1143	*
1144	* @param pDevIns The PCI device instance.
1145	*/
1146	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1147
1148	/**
1149	* Gets a bus by it's PDM ordinal (typically the parent bus).
1150	*
1151	* @returns Pointer to the device instance of the bus.
1152	* @param pDevIns The PCI bus device instance.
1153	* @param idxPdmBus The PDM ordinal value of the bus to get.
1154	*/
1155	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1156
1157	/** Just a safety precaution. */
1158	uint32_t u32TheEnd;
1159	} PDMPCIHLPR0;
1160	/** Pointer to PCI helpers. */
1161	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1162	/** Pointer to const PCI helpers. */
1163	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1164
1165	/** Current PDMPCIHLPR0 version number. */
1166	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 4, 0)
1167
1168	/**
1169	* PCI device helpers.
1170	*/
1171	typedef struct PDMPCIHLPR3
1172	{
1173	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1174	uint32_t u32Version;
1175
1176	/**
1177	* Set an ISA IRQ.
1178	*
1179	* @param pDevIns The PCI device instance.
1180	* @param iIrq IRQ number to set.
1181	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1182	* @param uTagSrc The IRQ tag and source (for tracing).
1183	*/
1184	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1185
1186	/**
1187	* Set an I/O-APIC IRQ.
1188	*
1189	* @param pDevIns The PCI device instance.
1190	* @param iIrq IRQ number to set.
1191	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1192	* @param uTagSrc The IRQ tag and source (for tracing).
1193	*/
1194	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1195
1196	/**
1197	* Send an MSI.
1198	*
1199	* @param pDevIns PCI device instance.
1200	* @param GCPhys Physical address MSI request was written.
1201	* @param uValue Value written.
1202	* @param uTagSrc The IRQ tag and source (for tracing).
1203	*/
1204	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1205
1206	/**
1207	* Checks if the given address is an MMIO2 or pre-registered MMIO base address.
1208	*
1209	* @returns true/false accordingly.
1210	* @param pDevIns The PCI device instance.
1211	* @param pOwner The owner of the memory, optional.
1212	* @param GCPhys The address to check.
1213	* @sa PGMR3PhysMMIOExIsBase
1214	*/
1215	DECLR3CALLBACKMEMBER(bool, pfnIsMMIOExBase,(PPDMDEVINS pDevIns, PPDMDEVINS pOwner, RTGCPHYS GCPhys));
1216
1217	/**
1218	* Acquires the PDM lock.
1219	*
1220	* @returns VINF_SUCCESS on success.
1221	* @returns Fatal error on failure.
1222	* @param pDevIns The PCI device instance.
1223	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1224	*/
1225	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1226
1227	/**
1228	* Releases the PDM lock.
1229	*
1230	* @param pDevIns The PCI device instance.
1231	*/
1232	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1233
1234	/**
1235	* Gets a bus by it's PDM ordinal (typically the parent bus).
1236	*
1237	* @returns Pointer to the device instance of the bus.
1238	* @param pDevIns The PCI bus device instance.
1239	* @param idxPdmBus The PDM ordinal value of the bus to get.
1240	*/
1241	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1242
1243	/** Just a safety precaution. */
1244	uint32_t u32TheEnd;
1245	} PDMPCIHLPR3;
1246	/** Pointer to PCI helpers. */
1247	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1248	/** Pointer to const PCI helpers. */
1249	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1250
1251	/** Current PDMPCIHLPR3 version number. */
1252	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 4, 0)
1253
1254
1255	/**
1256	* Programmable Interrupt Controller registration structure.
1257	*/
1258	typedef struct PDMPICREG
1259	{
1260	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1261	uint32_t u32Version;
1262
1263	/**
1264	* Set the an IRQ.
1265	*
1266	* @param pDevIns Device instance of the PIC.
1267	* @param iIrq IRQ number to set.
1268	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1269	* @param uTagSrc The IRQ tag and source (for tracing).
1270	* @remarks Caller enters the PDM critical section.
1271	*/
1272	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1273
1274	/**
1275	* Get a pending interrupt.
1276	*
1277	* @returns Pending interrupt number.
1278	* @param pDevIns Device instance of the PIC.
1279	* @param puTagSrc Where to return the IRQ tag and source.
1280	* @remarks Caller enters the PDM critical section.
1281	*/
1282	DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1283
1284	/** The name of the RC SetIrq entry point. */
1285	const char *pszSetIrqRC;
1286	/** The name of the RC GetInterrupt entry point. */
1287	const char *pszGetInterruptRC;
1288
1289	/** The name of the R0 SetIrq entry point. */
1290	const char *pszSetIrqR0;
1291	/** The name of the R0 GetInterrupt entry point. */
1292	const char *pszGetInterruptR0;
1293	} PDMPICREG;
1294	/** Pointer to a PIC registration structure. */
1295	typedef PDMPICREG *PPDMPICREG;
1296
1297	/** Current PDMPICREG version number. */
1298	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 2, 0)
1299
1300	/**
1301	* PIC RC helpers.
1302	*/
1303	typedef struct PDMPICHLPRC
1304	{
1305	/** Structure version. PDM_PICHLPRC_VERSION defines the current version. */
1306	uint32_t u32Version;
1307
1308	/**
1309	* Set the interrupt force action flag.
1310	*
1311	* @param pDevIns Device instance of the PIC.
1312	*/
1313	DECLRCCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1314
1315	/**
1316	* Clear the interrupt force action flag.
1317	*
1318	* @param pDevIns Device instance of the PIC.
1319	*/
1320	DECLRCCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1321
1322	/**
1323	* Acquires the PDM lock.
1324	*
1325	* @returns VINF_SUCCESS on success.
1326	* @returns rc if we failed to acquire the lock.
1327	* @param pDevIns The PIC device instance.
1328	* @param rc What to return if we fail to acquire the lock.
1329	*/
1330	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1331
1332	/**
1333	* Releases the PDM lock.
1334	*
1335	* @param pDevIns The PIC device instance.
1336	*/
1337	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1338
1339	/** Just a safety precaution. */
1340	uint32_t u32TheEnd;
1341	} PDMPICHLPRC;
1342
1343	/** Pointer to PIC RC helpers. */
1344	typedef RCPTRTYPE(PDMPICHLPRC *) PPDMPICHLPRC;
1345	/** Pointer to const PIC RC helpers. */
1346	typedef RCPTRTYPE(const PDMPICHLPRC *) PCPDMPICHLPRC;
1347
1348	/** Current PDMPICHLPRC version number. */
1349	#define PDM_PICHLPRC_VERSION PDM_VERSION_MAKE(0xfff9, 2, 0)
1350
1351
1352	/**
1353	* PIC R0 helpers.
1354	*/
1355	typedef struct PDMPICHLPR0
1356	{
1357	/** Structure version. PDM_PICHLPR0_VERSION defines the current version. */
1358	uint32_t u32Version;
1359
1360	/**
1361	* Set the interrupt force action flag.
1362	*
1363	* @param pDevIns Device instance of the PIC.
1364	*/
1365	DECLR0CALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1366
1367	/**
1368	* Clear the interrupt force action flag.
1369	*
1370	* @param pDevIns Device instance of the PIC.
1371	*/
1372	DECLR0CALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1373
1374	/**
1375	* Acquires the PDM lock.
1376	*
1377	* @returns VINF_SUCCESS on success.
1378	* @returns rc if we failed to acquire the lock.
1379	* @param pDevIns The PIC device instance.
1380	* @param rc What to return if we fail to acquire the lock.
1381	*/
1382	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1383
1384	/**
1385	* Releases the PDM lock.
1386	*
1387	* @param pDevIns The PCI device instance.
1388	*/
1389	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1390
1391	/** Just a safety precaution. */
1392	uint32_t u32TheEnd;
1393	} PDMPICHLPR0;
1394
1395	/** Pointer to PIC R0 helpers. */
1396	typedef R0PTRTYPE(PDMPICHLPR0 *) PPDMPICHLPR0;
1397	/** Pointer to const PIC R0 helpers. */
1398	typedef R0PTRTYPE(const PDMPICHLPR0 *) PCPDMPICHLPR0;
1399
1400	/** Current PDMPICHLPR0 version number. */
1401	#define PDM_PICHLPR0_VERSION PDM_VERSION_MAKE(0xfff8, 1, 0)
1402
1403	/**
1404	* PIC R3 helpers.
1405	*/
1406	typedef struct PDMPICHLPR3
1407	{
1408	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1409	uint32_t u32Version;
1410
1411	/**
1412	* Set the interrupt force action flag.
1413	*
1414	* @param pDevIns Device instance of the PIC.
1415	*/
1416	DECLR3CALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1417
1418	/**
1419	* Clear the interrupt force action flag.
1420	*
1421	* @param pDevIns Device instance of the PIC.
1422	*/
1423	DECLR3CALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1424
1425	/**
1426	* Acquires the PDM lock.
1427	*
1428	* @returns VINF_SUCCESS on success.
1429	* @returns Fatal error on failure.
1430	* @param pDevIns The PIC device instance.
1431	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1432	*/
1433	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1434
1435	/**
1436	* Releases the PDM lock.
1437	*
1438	* @param pDevIns The PIC device instance.
1439	*/
1440	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1441
1442	/**
1443	* Gets the address of the RC PIC helpers.
1444	*
1445	* This should be called at both construction and relocation time
1446	* to obtain the correct address of the RC helpers.
1447	*
1448	* @returns RC pointer to the PIC helpers.
1449	* @param pDevIns Device instance of the PIC.
1450	*/
1451	DECLR3CALLBACKMEMBER(PCPDMPICHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
1452
1453	/**
1454	* Gets the address of the R0 PIC helpers.
1455	*
1456	* This should be called at both construction and relocation time
1457	* to obtain the correct address of the R0 helpers.
1458	*
1459	* @returns R0 pointer to the PIC helpers.
1460	* @param pDevIns Device instance of the PIC.
1461	*/
1462	DECLR3CALLBACKMEMBER(PCPDMPICHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
1463
1464	/** Just a safety precaution. */
1465	uint32_t u32TheEnd;
1466	} PDMPICHLPR3;
1467
1468	/** Pointer to PIC R3 helpers. */
1469	typedef R3PTRTYPE(PDMPICHLPR3 *) PPDMPICHLPR3;
1470	/** Pointer to const PIC R3 helpers. */
1471	typedef R3PTRTYPE(const PDMPICHLPR3 *) PCPDMPICHLPR3;
1472
1473	/** Current PDMPICHLPR3 version number. */
1474	#define PDM_PICHLPR3_VERSION PDM_VERSION_MAKE(0xfff7, 1, 0)
1475
1476
1477
1478	/**
1479	* Firmware registration structure.
1480	*/
1481	typedef struct PDMFWREG
1482	{
1483	/** Struct version+magic number (PDM_FWREG_VERSION). */
1484	uint32_t u32Version;
1485
1486	/**
1487	* Checks whether this is a hard or soft reset.
1488	*
1489	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1490	* is 5, 9 or 0xA.
1491	*
1492	* @returns true if hard reset, false if soft.
1493	* @param pDevIns Device instance of the firmware.
1494	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1495	*/
1496	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1497
1498	/** Just a safety precaution. */
1499	uint32_t u32TheEnd;
1500	} PDMFWREG;
1501	/** Pointer to a FW registration structure. */
1502	typedef PDMFWREG *PPDMFWREG;
1503	/** Pointer to a const FW registration structure. */
1504	typedef PDMFWREG const *PCPDMFWREG;
1505
1506	/** Current PDMFWREG version number. */
1507	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1508
1509	/**
1510	* Firmware R3 helpers.
1511	*/
1512	typedef struct PDMFWHLPR3
1513	{
1514	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1515	uint32_t u32Version;
1516
1517	/** Just a safety precaution. */
1518	uint32_t u32TheEnd;
1519	} PDMFWHLPR3;
1520
1521	/** Pointer to FW R3 helpers. */
1522	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1523	/** Pointer to const FW R3 helpers. */
1524	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1525
1526	/** Current PDMFWHLPR3 version number. */
1527	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1528
1529
1530	/**
1531	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1532	*
1533	* Also used in saved-states, CFGM don't change existing values.
1534	*/
1535	typedef enum PDMAPICMODE
1536	{
1537	/** Invalid 0 entry. */
1538	PDMAPICMODE_INVALID = 0,
1539	/** No APIC. */
1540	PDMAPICMODE_NONE,
1541	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1542	PDMAPICMODE_APIC,
1543	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1544	PDMAPICMODE_X2APIC,
1545	/** The usual 32-bit paranoia. */
1546	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1547	} PDMAPICMODE;
1548
1549	/**
1550	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1551	*/
1552	typedef enum PDMAPICIRQ
1553	{
1554	/** Invalid 0 entry. */
1555	PDMAPICIRQ_INVALID = 0,
1556	/** Normal hardware interrupt. */
1557	PDMAPICIRQ_HARDWARE,
1558	/** NMI. */
1559	PDMAPICIRQ_NMI,
1560	/** SMI. */
1561	PDMAPICIRQ_SMI,
1562	/** ExtINT (HW interrupt via PIC). */
1563	PDMAPICIRQ_EXTINT,
1564	/** Interrupt arrived, needs to be updated to the IRR. */
1565	PDMAPICIRQ_UPDATE_PENDING,
1566	/** The usual 32-bit paranoia. */
1567	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1568	} PDMAPICIRQ;
1569
1570
1571	/**
1572	* I/O APIC registration structure.
1573	*/
1574	typedef struct PDMIOAPICREG
1575	{
1576	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1577	uint32_t u32Version;
1578
1579	/**
1580	* Set an IRQ.
1581	*
1582	* @param pDevIns Device instance of the I/O APIC.
1583	* @param iIrq IRQ number to set.
1584	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1585	* @param uTagSrc The IRQ tag and source (for tracing).
1586	*
1587	* @remarks Caller enters the PDM critical section
1588	* Actually, as per 2018-07-21 this isn't true (bird).
1589	*/
1590	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1591
1592	/** The name of the RC SetIrq entry point. */
1593	const char *pszSetIrqRC;
1594
1595	/** The name of the R0 SetIrq entry point. */
1596	const char *pszSetIrqR0;
1597
1598	/**
1599	* Send a MSI.
1600	*
1601	* @param pDevIns Device instance of the I/O APIC.
1602	* @param GCPhys Request address.
1603	* @param uValue Request value.
1604	* @param uTagSrc The IRQ tag and source (for tracing).
1605	*
1606	* @remarks Caller enters the PDM critical section
1607	* Actually, as per 2018-07-21 this isn't true (bird).
1608	*/
1609	DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1610
1611	/** The name of the RC SendMsi entry point. */
1612	const char *pszSendMsiRC;
1613
1614	/** The name of the R0 SendMsi entry point. */
1615	const char *pszSendMsiR0;
1616
1617	/**
1618	* Set the EOI for an interrupt vector.
1619	*
1620	* @returns Strict VBox status code - only the following informational status codes:
1621	* @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.2
1622	* @retval VINF_SUCCESS
1623	*
1624	* @param pDevIns Device instance of the I/O APIC.
1625	* @param u8Vector The vector.
1626	*
1627	* @remarks Caller enters the PDM critical section
1628	* Actually, as per 2018-07-21 this isn't true (bird).
1629	*/
1630	DECLR3CALLBACKMEMBER(int, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1631
1632	/** The name of the RC SetEoi entry point. */
1633	const char *pszSetEoiRC;
1634
1635	/** The name of the R0 SetEoi entry point. */
1636	const char *pszSetEoiR0;
1637	} PDMIOAPICREG;
1638	/** Pointer to an APIC registration structure. */
1639	typedef PDMIOAPICREG *PPDMIOAPICREG;
1640
1641	/** Current PDMAPICREG version number. */
1642	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 5, 0)
1643
1644
1645	/**
1646	* IOAPIC RC helpers.
1647	*/
1648	typedef struct PDMIOAPICHLPRC
1649	{
1650	/** Structure version. PDM_IOAPICHLPRC_VERSION defines the current version. */
1651	uint32_t u32Version;
1652
1653	/**
1654	* Private interface between the IOAPIC and APIC.
1655	*
1656	* See comments about this hack on PDMAPICREG::pfnBusDeliverR3.
1657	*
1658	* @returns status code.
1659	* @param pDevIns Device instance of the IOAPIC.
1660	* @param u8Dest See APIC implementation.
1661	* @param u8DestMode See APIC implementation.
1662	* @param u8DeliveryMode See APIC implementation.
1663	* @param uVector See APIC implementation.
1664	* @param u8Polarity See APIC implementation.
1665	* @param u8TriggerMode See APIC implementation.
1666	* @param uTagSrc The IRQ tag and source (for tracing).
1667	*/
1668	DECLRCCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1669	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1670
1671	/**
1672	* Acquires the PDM lock.
1673	*
1674	* @returns VINF_SUCCESS on success.
1675	* @returns rc if we failed to acquire the lock.
1676	* @param pDevIns The IOAPIC device instance.
1677	* @param rc What to return if we fail to acquire the lock.
1678	*/
1679	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1680
1681	/**
1682	* Releases the PDM lock.
1683	*
1684	* @param pDevIns The IOAPIC device instance.
1685	*/
1686	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1687
1688	/** Just a safety precaution. */
1689	uint32_t u32TheEnd;
1690	} PDMIOAPICHLPRC;
1691	/** Pointer to IOAPIC RC helpers. */
1692	typedef RCPTRTYPE(PDMIOAPICHLPRC *) PPDMIOAPICHLPRC;
1693	/** Pointer to const IOAPIC helpers. */
1694	typedef RCPTRTYPE(const PDMIOAPICHLPRC *) PCPDMIOAPICHLPRC;
1695
1696	/** Current PDMIOAPICHLPRC version number. */
1697	#define PDM_IOAPICHLPRC_VERSION PDM_VERSION_MAKE(0xfff1, 2, 0)
1698
1699
1700	/**
1701	* IOAPIC R0 helpers.
1702	*/
1703	typedef struct PDMIOAPICHLPR0
1704	{
1705	/** Structure version. PDM_IOAPICHLPR0_VERSION defines the current version. */
1706	uint32_t u32Version;
1707
1708	/**
1709	* Private interface between the IOAPIC and APIC.
1710	*
1711	* See comments about this hack on PDMAPICREG::pfnBusDeliverR3.
1712	*
1713	* @returns status code.
1714	* @param pDevIns Device instance of the IOAPIC.
1715	* @param u8Dest See APIC implementation.
1716	* @param u8DestMode See APIC implementation.
1717	* @param u8DeliveryMode See APIC implementation.
1718	* @param uVector See APIC implementation.
1719	* @param u8Polarity See APIC implementation.
1720	* @param u8TriggerMode See APIC implementation.
1721	* @param uTagSrc The IRQ tag and source (for tracing).
1722	*/
1723	DECLR0CALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1724	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1725
1726	/**
1727	* Acquires the PDM lock.
1728	*
1729	* @returns VINF_SUCCESS on success.
1730	* @returns rc if we failed to acquire the lock.
1731	* @param pDevIns The IOAPIC device instance.
1732	* @param rc What to return if we fail to acquire the lock.
1733	*/
1734	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1735
1736	/**
1737	* Releases the PDM lock.
1738	*
1739	* @param pDevIns The IOAPIC device instance.
1740	*/
1741	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1742
1743	/** Just a safety precaution. */
1744	uint32_t u32TheEnd;
1745	} PDMIOAPICHLPR0;
1746	/** Pointer to IOAPIC R0 helpers. */
1747	typedef R0PTRTYPE(PDMIOAPICHLPR0 *) PPDMIOAPICHLPR0;
1748	/** Pointer to const IOAPIC helpers. */
1749	typedef R0PTRTYPE(const PDMIOAPICHLPR0 *) PCPDMIOAPICHLPR0;
1750
1751	/** Current PDMIOAPICHLPR0 version number. */
1752	#define PDM_IOAPICHLPR0_VERSION PDM_VERSION_MAKE(0xfff0, 2, 0)
1753
1754	/**
1755	* IOAPIC R3 helpers.
1756	*/
1757	typedef struct PDMIOAPICHLPR3
1758	{
1759	/** Structure version. PDM_IOAPICHLPR3_VERSION defines the current version. */
1760	uint32_t u32Version;
1761
1762	/**
1763	* Private interface between the IOAPIC and APIC.
1764	*
1765	* See comments about this hack on PDMAPICREG::pfnBusDeliverR3.
1766	*
1767	* @returns status code
1768	* @param pDevIns Device instance of the IOAPIC.
1769	* @param u8Dest See APIC implementation.
1770	* @param u8DestMode See APIC implementation.
1771	* @param u8DeliveryMode See APIC implementation.
1772	* @param uVector See APIC implementation.
1773	* @param u8Polarity See APIC implementation.
1774	* @param u8TriggerMode See APIC implementation.
1775	* @param uTagSrc The IRQ tag and source (for tracing).
1776	*/
1777	DECLR3CALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1778	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1779
1780	/**
1781	* Acquires the PDM lock.
1782	*
1783	* @returns VINF_SUCCESS on success.
1784	* @returns Fatal error on failure.
1785	* @param pDevIns The IOAPIC device instance.
1786	* @param rc Dummy for making the interface identical to the GC and R0 versions.
1787	*/
1788	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1789
1790	/**
1791	* Releases the PDM lock.
1792	*
1793	* @param pDevIns The IOAPIC device instance.
1794	*/
1795	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1796
1797	/**
1798	* Gets the address of the RC IOAPIC helpers.
1799	*
1800	* This should be called at both construction and relocation time
1801	* to obtain the correct address of the RC helpers.
1802	*
1803	* @returns RC pointer to the IOAPIC helpers.
1804	* @param pDevIns Device instance of the IOAPIC.
1805	*/
1806	DECLR3CALLBACKMEMBER(PCPDMIOAPICHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
1807
1808	/**
1809	* Gets the address of the R0 IOAPIC helpers.
1810	*
1811	* This should be called at both construction and relocation time
1812	* to obtain the correct address of the R0 helpers.
1813	*
1814	* @returns R0 pointer to the IOAPIC helpers.
1815	* @param pDevIns Device instance of the IOAPIC.
1816	*/
1817	DECLR3CALLBACKMEMBER(PCPDMIOAPICHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
1818
1819	/** Just a safety precaution. */
1820	uint32_t u32TheEnd;
1821	} PDMIOAPICHLPR3;
1822	/** Pointer to IOAPIC R3 helpers. */
1823	typedef R3PTRTYPE(PDMIOAPICHLPR3 *) PPDMIOAPICHLPR3;
1824	/** Pointer to const IOAPIC helpers. */
1825	typedef R3PTRTYPE(const PDMIOAPICHLPR3 *) PCPDMIOAPICHLPR3;
1826
1827	/** Current PDMIOAPICHLPR3 version number. */
1828	#define PDM_IOAPICHLPR3_VERSION PDM_VERSION_MAKE(0xffef, 2, 0)
1829
1830
1831	/**
1832	* HPET registration structure.
1833	*/
1834	typedef struct PDMHPETREG
1835	{
1836	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1837	uint32_t u32Version;
1838
1839	} PDMHPETREG;
1840	/** Pointer to an HPET registration structure. */
1841	typedef PDMHPETREG *PPDMHPETREG;
1842
1843	/** Current PDMHPETREG version number. */
1844	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1845
1846	/**
1847	* HPET RC helpers.
1848	*
1849	* @remarks Keep this around in case HPET will need PDM interaction in again RC
1850	* at some later point.
1851	*/
1852	typedef struct PDMHPETHLPRC
1853	{
1854	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
1855	uint32_t u32Version;
1856
1857	/** Just a safety precaution. */
1858	uint32_t u32TheEnd;
1859	} PDMHPETHLPRC;
1860
1861	/** Pointer to HPET RC helpers. */
1862	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
1863	/** Pointer to const HPET RC helpers. */
1864	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
1865
1866	/** Current PDMHPETHLPRC version number. */
1867	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
1868
1869
1870	/**
1871	* HPET R0 helpers.
1872	*
1873	* @remarks Keep this around in case HPET will need PDM interaction in again R0
1874	* at some later point.
1875	*/
1876	typedef struct PDMHPETHLPR0
1877	{
1878	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
1879	uint32_t u32Version;
1880
1881	/** Just a safety precaution. */
1882	uint32_t u32TheEnd;
1883	} PDMHPETHLPR0;
1884
1885	/** Pointer to HPET R0 helpers. */
1886	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
1887	/** Pointer to const HPET R0 helpers. */
1888	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
1889
1890	/** Current PDMHPETHLPR0 version number. */
1891	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
1892
1893	/**
1894	* HPET R3 helpers.
1895	*/
1896	typedef struct PDMHPETHLPR3
1897	{
1898	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
1899	uint32_t u32Version;
1900
1901	/**
1902	* Gets the address of the RC HPET helpers.
1903	*
1904	* This should be called at both construction and relocation time
1905	* to obtain the correct address of the RC helpers.
1906	*
1907	* @returns RC pointer to the HPET helpers.
1908	* @param pDevIns Device instance of the HPET.
1909	*/
1910	DECLR3CALLBACKMEMBER(PCPDMHPETHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
1911
1912	/**
1913	* Gets the address of the R0 HPET helpers.
1914	*
1915	* This should be called at both construction and relocation time
1916	* to obtain the correct address of the R0 helpers.
1917	*
1918	* @returns R0 pointer to the HPET helpers.
1919	* @param pDevIns Device instance of the HPET.
1920	*/
1921	DECLR3CALLBACKMEMBER(PCPDMHPETHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
1922
1923	/**
1924	* Set legacy mode on PIT and RTC.
1925	*
1926	* @returns VINF_SUCCESS on success.
1927	* @returns rc if we failed to set legacy mode.
1928	* @param pDevIns Device instance of the HPET.
1929	* @param fActivated Whether legacy mode is activated or deactivated.
1930	*/
1931	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
1932
1933
1934	/**
1935	* Set IRQ, bypassing ISA bus override rules.
1936	*
1937	* @returns VINF_SUCCESS on success.
1938	* @returns rc if we failed to set legacy mode.
1939	* @param pDevIns Device instance of the HPET.
1940	* @param iIrq IRQ number to set.
1941	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1942	*/
1943	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
1944
1945	/** Just a safety precaution. */
1946	uint32_t u32TheEnd;
1947	} PDMHPETHLPR3;
1948
1949	/** Pointer to HPET R3 helpers. */
1950	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
1951	/** Pointer to const HPET R3 helpers. */
1952	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
1953
1954	/** Current PDMHPETHLPR3 version number. */
1955	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 2, 0)
1956
1957
1958	/**
1959	* Raw PCI device registration structure.
1960	*/
1961	typedef struct PDMPCIRAWREG
1962	{
1963	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
1964	uint32_t u32Version;
1965	/** Just a safety precaution. */
1966	uint32_t u32TheEnd;
1967	} PDMPCIRAWREG;
1968	/** Pointer to a raw PCI registration structure. */
1969	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
1970
1971	/** Current PDMPCIRAWREG version number. */
1972	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
1973
1974	/**
1975	* Raw PCI device raw-mode context helpers.
1976	*/
1977	typedef struct PDMPCIRAWHLPRC
1978	{
1979	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
1980	uint32_t u32Version;
1981	/** Just a safety precaution. */
1982	uint32_t u32TheEnd;
1983	} PDMPCIRAWHLPRC;
1984	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
1985	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
1986	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
1987	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
1988
1989	/** Current PDMPCIRAWHLPRC version number. */
1990	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
1991
1992	/**
1993	* Raw PCI device ring-0 context helpers.
1994	*/
1995	typedef struct PDMPCIRAWHLPR0
1996	{
1997	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
1998	uint32_t u32Version;
1999	/** Just a safety precaution. */
2000	uint32_t u32TheEnd;
2001	} PDMPCIRAWHLPR0;
2002	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2003	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2004	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2005	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2006
2007	/** Current PDMPCIRAWHLPR0 version number. */
2008	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2009
2010
2011	/**
2012	* Raw PCI device ring-3 context helpers.
2013	*/
2014	typedef struct PDMPCIRAWHLPR3
2015	{
2016	/** Undefined structure version and magic number. */
2017	uint32_t u32Version;
2018
2019	/**
2020	* Gets the address of the RC raw PCI device helpers.
2021	*
2022	* This should be called at both construction and relocation time to obtain
2023	* the correct address of the RC helpers.
2024	*
2025	* @returns RC pointer to the raw PCI device helpers.
2026	* @param pDevIns Device instance of the raw PCI device.
2027	*/
2028	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2029
2030	/**
2031	* Gets the address of the R0 raw PCI device helpers.
2032	*
2033	* This should be called at both construction and relocation time to obtain
2034	* the correct address of the R0 helpers.
2035	*
2036	* @returns R0 pointer to the raw PCI device helpers.
2037	* @param pDevIns Device instance of the raw PCI device.
2038	*/
2039	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2040
2041	/** Just a safety precaution. */
2042	uint32_t u32TheEnd;
2043	} PDMPCIRAWHLPR3;
2044	/** Pointer to raw PCI R3 helpers. */
2045	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2046	/** Pointer to const raw PCI R3 helpers. */
2047	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2048
2049	/** Current PDMPCIRAWHLPR3 version number. */
2050	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2051
2052
2053	#ifdef IN_RING3
2054
2055	/**
2056	* DMA Transfer Handler.
2057	*
2058	* @returns Number of bytes transferred.
2059	* @param pDevIns Device instance of the DMA.
2060	* @param pvUser User pointer.
2061	* @param uChannel Channel number.
2062	* @param off DMA position.
2063	* @param cb Block size.
2064	* @remarks The device lock is not taken, however, the DMA device lock is held.
2065	*/
2066	typedef DECLCALLBACK(uint32_t) FNDMATRANSFERHANDLER(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel, uint32_t off, uint32_t cb);
2067	/** Pointer to a FNDMATRANSFERHANDLER(). */
2068	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2069
2070	/**
2071	* DMA Controller registration structure.
2072	*/
2073	typedef struct PDMDMAREG
2074	{
2075	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2076	uint32_t u32Version;
2077
2078	/**
2079	* Execute pending transfers.
2080	*
2081	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2082	* @param pDevIns Device instance of the DMAC.
2083	* @remarks No locks held, called on EMT(0) as a form of serialization.
2084	*/
2085	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2086
2087	/**
2088	* Register transfer function for DMA channel.
2089	*
2090	* @param pDevIns Device instance of the DMAC.
2091	* @param uChannel Channel number.
2092	* @param pfnTransferHandler Device specific transfer function.
2093	* @param pvUser User pointer to be passed to the callback.
2094	* @remarks No locks held, called on an EMT.
2095	*/
2096	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2097
2098	/**
2099	* Read memory
2100	*
2101	* @returns Number of bytes read.
2102	* @param pDevIns Device instance of the DMAC.
2103	* @param uChannel Channel number.
2104	* @param pvBuffer Pointer to target buffer.
2105	* @param off DMA position.
2106	* @param cbBlock Block size.
2107	* @remarks No locks held, called on an EMT.
2108	*/
2109	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2110
2111	/**
2112	* Write memory
2113	*
2114	* @returns Number of bytes written.
2115	* @param pDevIns Device instance of the DMAC.
2116	* @param uChannel Channel number.
2117	* @param pvBuffer Memory to write.
2118	* @param off DMA position.
2119	* @param cbBlock Block size.
2120	* @remarks No locks held, called on an EMT.
2121	*/
2122	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2123
2124	/**
2125	* Set the DREQ line.
2126	*
2127	* @param pDevIns Device instance of the DMAC.
2128	* @param uChannel Channel number.
2129	* @param uLevel Level of the line.
2130	* @remarks No locks held, called on an EMT.
2131	*/
2132	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2133
2134	/**
2135	* Get channel mode
2136	*
2137	* @returns Channel mode.
2138	* @param pDevIns Device instance of the DMAC.
2139	* @param uChannel Channel number.
2140	* @remarks No locks held, called on an EMT.
2141	*/
2142	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2143
2144	} PDMDMACREG;
2145	/** Pointer to a DMAC registration structure. */
2146	typedef PDMDMACREG *PPDMDMACREG;
2147
2148	/** Current PDMDMACREG version number. */
2149	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 1, 0)
2150
2151
2152	/**
2153	* DMA Controller device helpers.
2154	*/
2155	typedef struct PDMDMACHLP
2156	{
2157	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2158	uint32_t u32Version;
2159
2160	/* to-be-defined */
2161
2162	} PDMDMACHLP;
2163	/** Pointer to DMAC helpers. */
2164	typedef PDMDMACHLP *PPDMDMACHLP;
2165	/** Pointer to const DMAC helpers. */
2166	typedef const PDMDMACHLP *PCPDMDMACHLP;
2167
2168	/** Current PDMDMACHLP version number. */
2169	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2170
2171	#endif /* IN_RING3 */
2172
2173
2174
2175	/**
2176	* RTC registration structure.
2177	*/
2178	typedef struct PDMRTCREG
2179	{
2180	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2181	uint32_t u32Version;
2182	uint32_t u32Alignment; /*< structure size alignment. /
2183
2184	/**
2185	* Write to a CMOS register and update the checksum if necessary.
2186	*
2187	* @returns VBox status code.
2188	* @param pDevIns Device instance of the RTC.
2189	* @param iReg The CMOS register index.
2190	* @param u8Value The CMOS register value.
2191	* @remarks Caller enters the device critical section.
2192	*/
2193	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2194
2195	/**
2196	* Read a CMOS register.
2197	*
2198	* @returns VBox status code.
2199	* @param pDevIns Device instance of the RTC.
2200	* @param iReg The CMOS register index.
2201	* @param pu8Value Where to store the CMOS register value.
2202	* @remarks Caller enters the device critical section.
2203	*/
2204	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2205
2206	} PDMRTCREG;
2207	/** Pointer to a RTC registration structure. */
2208	typedef PDMRTCREG *PPDMRTCREG;
2209	/** Pointer to a const RTC registration structure. */
2210	typedef const PDMRTCREG *PCPDMRTCREG;
2211
2212	/** Current PDMRTCREG version number. */
2213	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2214
2215
2216	/**
2217	* RTC device helpers.
2218	*/
2219	typedef struct PDMRTCHLP
2220	{
2221	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2222	uint32_t u32Version;
2223
2224	/* to-be-defined */
2225
2226	} PDMRTCHLP;
2227	/** Pointer to RTC helpers. */
2228	typedef PDMRTCHLP *PPDMRTCHLP;
2229	/** Pointer to const RTC helpers. */
2230	typedef const PDMRTCHLP *PCPDMRTCHLP;
2231
2232	/** Current PDMRTCHLP version number. */
2233	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2234
2235
2236
2237	/** @name Flags for PCI I/O region registration
2238	* @{ */
2239	/** No handle is passed. */
2240	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2241	/** An I/O port handle is passed. */
2242	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2243	/** An MMIO range handle is passed. */
2244	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2245	/** An MMIO2 handle is passed. */
2246	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2247	/** Handle type mask. */
2248	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2249	/** New-style (mostly wrt callbacks). */
2250	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2251	/** Mask of valid flags. */
2252	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2253	/** @} */
2254
2255
2256	#ifdef IN_RING3
2257
2258	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2259	* @{ */
2260	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2261	* This is handy when registering multiple PCI device functions and the device
2262	* number is left up to the PCI bus. In order to facilitate one PDM device
2263	* instance for each PCI function, this searches earlier PDM device
2264	* instances as well. */
2265	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2266	/** Use the first unused device number (all functions must be unused). */
2267	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2268	/** Use the first unused device function. */
2269	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2270
2271	/** The device and function numbers are not mandatory, just suggestions. */
2272	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2273	/** Registering a PCI bridge device. */
2274	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2275	/** Valid flag mask. */
2276	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2277	/** @} */
2278
2279	/** Current PDMDEVHLPR3 version number. */
2280	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 35, 0)
2281
2282	/**
2283	* PDM Device API.
2284	*/
2285	typedef struct PDMDEVHLPR3
2286	{
2287	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2288	uint32_t u32Version;
2289
2290	/** @name I/O ports
2291	* @{ */
2292	/**
2293	* Creates a range of I/O ports for a device.
2294	*
2295	* The I/O port range must be mapped in a separately call. Any ring-0 and
2296	* raw-mode context callback handlers needs to be set up in the respective
2297	* contexts.
2298	*
2299	* @returns VBox status.
2300	* @param pDevIns The device instance to register the ports with.
2301	* @param cPorts Number of ports to register.
2302	* @param fFlags IOM_IOPORT_F_XXX.
2303	* @param pPciDev The PCI device the range is associated with, if
2304	* applicable.
2305	* @param iPciRegion The PCI device region in the high 16-bit word and
2306	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2307	* @param pfnOut Pointer to function which is gonna handle OUT
2308	* operations. Optional.
2309	* @param pfnIn Pointer to function which is gonna handle IN operations.
2310	* Optional.
2311	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2312	* operations. Optional.
2313	* @param pfnInStr Pointer to function which is gonna handle string IN
2314	* operations. Optional.
2315	* @param pvUser User argument to pass to the callbacks.
2316	* @param pszDesc Pointer to description string. This must not be freed.
2317	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2318	* coverage is allowed. This must not be freed.
2319	* @param phIoPorts Where to return the I/O port range handle.
2320	*
2321	* @remarks Caller enters the device critical section prior to invoking the
2322	* registered callback methods.
2323	*
2324	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2325	* PDMDevHlpIoPortUnmap.
2326	*/
2327	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2328	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2329	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2330	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2331
2332	/**
2333	* Maps an I/O port range.
2334	*
2335	* @returns VBox status.
2336	* @param pDevIns The device instance to register the ports with.
2337	* @param hIoPorts The I/O port range handle.
2338	* @param Port Where to map the range.
2339	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2340	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2341	*/
2342	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2343
2344	/**
2345	* Unmaps an I/O port range.
2346	*
2347	* @returns VBox status.
2348	* @param pDevIns The device instance to register the ports with.
2349	* @param hIoPorts The I/O port range handle.
2350	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2351	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2352	*/
2353	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2354
2355	/**
2356	* Gets the mapping address of the I/O port range @a hIoPorts.
2357	*
2358	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2359	* parameters).
2360	* @param pDevIns The device instance to register the ports with.
2361	* @param hIoPorts The I/O port range handle.
2362	*/
2363	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2364	/** @} */
2365
2366	/**
2367	* Register a number of I/O ports with a device.
2368	*
2369	* These callbacks are of course for the host context (HC).
2370	* Register HC handlers before guest context (GC) handlers! There must be a
2371	* HC handler for every GC handler!
2372	*
2373	* @returns VBox status.
2374	* @param pDevIns The device instance to register the ports with.
2375	* @param Port First port number in the range.
2376	* @param cPorts Number of ports to register.
2377	* @param pvUser User argument.
2378	* @param pfnOut Pointer to function which is gonna handle OUT operations.
2379	* @param pfnIn Pointer to function which is gonna handle IN operations.
2380	* @param pfnOutStr Pointer to function which is gonna handle string OUT operations.
2381	* @param pfnInStr Pointer to function which is gonna handle string IN operations.
2382	* @param pszDesc Pointer to description string. This must not be freed.
2383	* @remarks Caller enters the device critical section prior to invoking the
2384	* registered callback methods.
2385	* @deprecated
2386	*/
2387	DECLR3CALLBACKMEMBER(int, pfnIOPortRegister,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTHCPTR pvUser,
2388	PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
2389	PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc));
2390
2391	/**
2392	* Register a number of I/O ports with a device for RC.
2393	*
2394	* These callbacks are for the raw-mode context (RC). Register ring-3 context
2395	* (R3) handlers before raw-mode context handlers! There must be a R3 handler
2396	* for every RC handler!
2397	*
2398	* @returns VBox status.
2399	* @param pDevIns The device instance to register the ports with
2400	* and which RC module to resolve the names
2401	* against.
2402	* @param Port First port number in the range.
2403	* @param cPorts Number of ports to register.
2404	* @param pvUser User argument.
2405	* @param pszOut Name of the RC function which is gonna handle OUT operations.
2406	* @param pszIn Name of the RC function which is gonna handle IN operations.
2407	* @param pszOutStr Name of the RC function which is gonna handle string OUT operations.
2408	* @param pszInStr Name of the RC function which is gonna handle string IN operations.
2409	* @param pszDesc Pointer to description string. This must not be freed.
2410	* @remarks Caller enters the device critical section prior to invoking the
2411	* registered callback methods.
2412	* @deprecated
2413	*/
2414	DECLR3CALLBACKMEMBER(int, pfnIOPortRegisterRC,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTRCPTR pvUser,
2415	const char pszOut, const char pszIn,
2416	const char pszOutStr, const char pszInStr, const char *pszDesc));
2417
2418	/**
2419	* Register a number of I/O ports with a device.
2420	*
2421	* These callbacks are of course for the ring-0 host context (R0).
2422	* Register R3 (HC) handlers before R0 (R0) handlers! There must be a R3 (HC) handler for every R0 handler!
2423	*
2424	* @returns VBox status.
2425	* @param pDevIns The device instance to register the ports with.
2426	* @param Port First port number in the range.
2427	* @param cPorts Number of ports to register.
2428	* @param pvUser User argument. (if pointer, then it must be in locked memory!)
2429	* @param pszOut Name of the R0 function which is gonna handle OUT operations.
2430	* @param pszIn Name of the R0 function which is gonna handle IN operations.
2431	* @param pszOutStr Name of the R0 function which is gonna handle string OUT operations.
2432	* @param pszInStr Name of the R0 function which is gonna handle string IN operations.
2433	* @param pszDesc Pointer to description string. This must not be freed.
2434	* @remarks Caller enters the device critical section prior to invoking the
2435	* registered callback methods.
2436	* @deprecated
2437	*/
2438	DECLR3CALLBACKMEMBER(int, pfnIOPortRegisterR0,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTR0PTR pvUser,
2439	const char pszOut, const char pszIn,
2440	const char pszOutStr, const char pszInStr, const char *pszDesc));
2441
2442	/**
2443	* Deregister I/O ports.
2444	*
2445	* This naturally affects both guest context (GC), ring-0 (R0) and ring-3 (R3/HC) handlers.
2446	*
2447	* @returns VBox status.
2448	* @param pDevIns The device instance owning the ports.
2449	* @param Port First port number in the range.
2450	* @param cPorts Number of ports to deregister.
2451	*/
2452	DECLR3CALLBACKMEMBER(int, pfnIOPortDeregister,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts));
2453
2454	/** @name MMIO
2455	* @{ */
2456	/**
2457	* Creates a memory mapped I/O (MMIO) region for a device.
2458	*
2459	* The MMIO region must be mapped in a separately call. Any ring-0 and
2460	* raw-mode context callback handlers needs to be set up in the respective
2461	* contexts.
2462	*
2463	* @returns VBox status.
2464	* @param pDevIns The device instance to register the ports with.
2465	* @param cbRegion The size of the region in bytes.
2466	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2467	* @param pPciDev The PCI device the range is associated with, if
2468	* applicable.
2469	* @param iPciRegion The PCI device region in the high 16-bit word and
2470	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2471	* @param pfnWrite Pointer to function which is gonna handle Write
2472	* operations.
2473	* @param pfnRead Pointer to function which is gonna handle Read
2474	* operations.
2475	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2476	* operations. (optional)
2477	* @param pvUser User argument to pass to the callbacks.
2478	* @param pszDesc Pointer to description string. This must not be freed.
2479	* @param phRegion Where to return the MMIO region handle.
2480	*
2481	* @remarks Caller enters the device critical section prior to invoking the
2482	* registered callback methods.
2483	*
2484	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2485	*/
2486	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2487	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2488	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2489	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2490
2491	/**
2492	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2493	*
2494	* @returns VBox status.
2495	* @param pDevIns The device instance the region is associated with.
2496	* @param hRegion The MMIO region handle.
2497	* @param GCPhys Where to map the region.
2498	* @note An MMIO range may overlap with base memory if a lot of RAM is
2499	* configured for the VM, in which case we'll drop the base memory
2500	* pages. Presently we will make no attempt to preserve anything that
2501	* happens to be present in the base memory that is replaced, this is
2502	* technically incorrect but it's just not worth the effort to do
2503	* right, at least not at this point.
2504	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2505	* PDMDevHlpMmioSetUpContext
2506	*/
2507	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2508
2509	/**
2510	* Unmaps a memory mapped I/O (MMIO) region.
2511	*
2512	* @returns VBox status.
2513	* @param pDevIns The device instance the region is associated with.
2514	* @param hRegion The MMIO region handle.
2515	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2516	* PDMDevHlpMmioSetUpContext
2517	*/
2518	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2519
2520	/**
2521	* Reduces the length of a MMIO range.
2522	*
2523	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2524	* only work during saved state restore. It will not call the PCI bus code, as
2525	* that is expected to restore the saved resource configuration.
2526	*
2527	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2528	* called it will only map @a cbRegion bytes and not the value set during
2529	* registration.
2530	*
2531	* @return VBox status code.
2532	* @param pDevIns The device owning the range.
2533	* @param hRegion The MMIO region handle.
2534	* @param cbRegion The new size, must be smaller.
2535	*/
2536	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2537
2538	/**
2539	* Gets the mapping address of the MMIO region @a hRegion.
2540	*
2541	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2542	* @param pDevIns The device instance to register the ports with.
2543	* @param hRegion The MMIO region handle.
2544	*/
2545	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2546	/** @} */
2547
2548	/**
2549	* Register a Memory Mapped I/O (MMIO) region.
2550	*
2551	* These callbacks are of course for the ring-3 context (R3). Register HC
2552	* handlers before raw-mode context (RC) and ring-0 context (R0) handlers! There
2553	* must be a R3 handler for every RC and R0 handler!
2554	*
2555	* @returns VBox status.
2556	* @param pDevIns The device instance to register the MMIO with.
2557	* @param GCPhysStart First physical address in the range.
2558	* @param cbRange The size of the range (in bytes).
2559	* @param pvUser User argument.
2560	* @param pfnWrite Pointer to function which is gonna handle Write operations.
2561	* @param pfnRead Pointer to function which is gonna handle Read operations.
2562	* @param pfnFill Pointer to function which is gonna handle Fill/memset operations. (optional)
2563	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2564	* @param pszDesc Pointer to description string. This must not be freed.
2565	* @remarks Caller enters the device critical section prior to invoking the
2566	* registered callback methods.
2567	* @deprecated
2568	*/
2569	DECLR3CALLBACKMEMBER(int, pfnMMIORegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
2570	PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
2571	uint32_t fFlags, const char *pszDesc));
2572
2573	/**
2574	* Register a Memory Mapped I/O (MMIO) region for RC.
2575	*
2576	* These callbacks are for the raw-mode context (RC). Register ring-3 context
2577	* (R3) handlers before guest context handlers! There must be a R3 handler for
2578	* every RC handler!
2579	*
2580	* @returns VBox status.
2581	* @param pDevIns The device instance to register the MMIO with.
2582	* @param GCPhysStart First physical address in the range.
2583	* @param cbRange The size of the range (in bytes).
2584	* @param pvUser User argument.
2585	* @param pszWrite Name of the RC function which is gonna handle Write operations.
2586	* @param pszRead Name of the RC function which is gonna handle Read operations.
2587	* @param pszFill Name of the RC function which is gonna handle Fill/memset operations. (optional)
2588	* @remarks Caller enters the device critical section prior to invoking the
2589	* registered callback methods.
2590	* @deprecated
2591	*/
2592	DECLR3CALLBACKMEMBER(int, pfnMMIORegisterRC,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
2593	const char pszWrite, const char pszRead, const char *pszFill));
2594
2595	/**
2596	* Register a Memory Mapped I/O (MMIO) region for R0.
2597	*
2598	* These callbacks are for the ring-0 host context (R0). Register ring-3
2599	* constext (R3) handlers before R0 handlers! There must be a R3 handler for
2600	* every R0 handler!
2601	*
2602	* @returns VBox status.
2603	* @param pDevIns The device instance to register the MMIO with.
2604	* @param GCPhysStart First physical address in the range.
2605	* @param cbRange The size of the range (in bytes).
2606	* @param pvUser User argument. (if pointer, then it must be in locked memory!)
2607	* @param pszWrite Name of the RC function which is gonna handle Write operations.
2608	* @param pszRead Name of the RC function which is gonna handle Read operations.
2609	* @param pszFill Name of the RC function which is gonna handle Fill/memset operations. (optional)
2610	* @remarks Caller enters the device critical section prior to invoking the
2611	* registered callback methods.
2612	* @deprecated
2613	*/
2614	DECLR3CALLBACKMEMBER(int, pfnMMIORegisterR0,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
2615	const char pszWrite, const char pszRead, const char *pszFill));
2616
2617	/**
2618	* Deregister a Memory Mapped I/O (MMIO) region.
2619	*
2620	* This naturally affects both guest context (GC), ring-0 (R0) and ring-3 (R3/HC) handlers.
2621	*
2622	* @returns VBox status.
2623	* @param pDevIns The device instance owning the MMIO region(s).
2624	* @param GCPhysStart First physical address in the range.
2625	* @param cbRange The size of the range (in bytes).
2626	* @deprecated
2627	*/
2628	DECLR3CALLBACKMEMBER(int, pfnMMIODeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange));
2629
2630	/** @name MMIO2
2631	* @{ */
2632	/**
2633	* Creates a MMIO2 region.
2634	*
2635	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2636	* associated with a device. It is also non-shared memory with a permanent
2637	* ring-3 mapping and page backing (presently).
2638	*
2639	* @returns VBox status.
2640	* @param pDevIns The device instance.
2641	* @param pPciDev The PCI device the region is associated with, or
2642	* NULL if no PCI device association.
2643	* @param iPciRegion The region number. Use the PCI region number as
2644	* this must be known to the PCI bus device too. If
2645	* it's not associated with the PCI device, then
2646	* any number up to UINT8_MAX is fine.
2647	* @param cbRegion The size (in bytes) of the region.
2648	* @param fFlags Reserved for future use, must be zero.
2649	* @param pszDesc Pointer to description string. This must not be
2650	* freed.
2651	* @param ppvMapping Where to store the address of the ring-3 mapping
2652	* of the memory.
2653	* @param phRegion Where to return the MMIO2 region handle.
2654	*
2655	* @thread EMT(0)
2656	*/
2657	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2658	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2659
2660	/**
2661	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2662	*
2663	* Any physical access handlers registered for the region must be deregistered
2664	* before calling this function.
2665	*
2666	* @returns VBox status code.
2667	* @param pDevIns The device instance.
2668	* @param hRegion The MMIO2 region handle.
2669	* @thread EMT.
2670	*/
2671	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2672
2673	/**
2674	* Maps a MMIO2 region (into the guest physical address space).
2675	*
2676	* @returns VBox status.
2677	* @param pDevIns The device instance the region is associated with.
2678	* @param hRegion The MMIO2 region handle.
2679	* @param GCPhys Where to map the region.
2680	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2681	* configured for the VM, in which case we'll drop the base memory
2682	* pages. Presently we will make no attempt to preserve anything that
2683	* happens to be present in the base memory that is replaced, this is
2684	* technically incorrect but it's just not worth the effort to do
2685	* right, at least not at this point.
2686	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2687	*/
2688	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2689
2690	/**
2691	* Unmaps a MMIO2 region.
2692	*
2693	* @returns VBox status.
2694	* @param pDevIns The device instance the region is associated with.
2695	* @param hRegion The MMIO2 region handle.
2696	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2697	*/
2698	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2699
2700	/**
2701	* Reduces the length of a MMIO range.
2702	*
2703	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2704	* only work during saved state restore. It will not call the PCI bus code, as
2705	* that is expected to restore the saved resource configuration.
2706	*
2707	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2708	* called it will only map @a cbRegion bytes and not the value set during
2709	* registration.
2710	*
2711	* @return VBox status code.
2712	* @param pDevIns The device owning the range.
2713	* @param hRegion The MMIO2 region handle.
2714	* @param cbRegion The new size, must be smaller.
2715	*/
2716	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2717
2718	/**
2719	* Gets the mapping address of the MMIO region @a hRegion.
2720	*
2721	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2722	* @param pDevIns The device instance to register the ports with.
2723	* @param hRegion The MMIO2 region handle.
2724	*/
2725	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2726
2727	/**
2728	* Changes the number of an MMIO2 or pre-registered MMIO region.
2729	*
2730	* This should only be used to deal with saved state problems, so there is no
2731	* convenience inline wrapper for this method.
2732	*
2733	* @returns VBox status code.
2734	* @param pDevIns The device instance.
2735	* @param hRegion The MMIO2 region handle.
2736	* @param iNewRegion The new region index.
2737	*
2738	* @sa @bugref{9359}
2739	*/
2740	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2741	/** @} */
2742
2743	/**
2744	* Allocate and register a MMIO2 region.
2745	*
2746	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2747	* associated with a device. It is also non-shared memory with a permanent
2748	* ring-3 mapping and page backing (presently).
2749	*
2750	* @returns VBox status.
2751	* @param pDevIns The device instance.
2752	* @param pPciDev The PCI device the region is associated with, or
2753	* NULL if no PCI device association.
2754	* @param iRegion The region number. Use the PCI region number as
2755	* this must be known to the PCI bus device too. If
2756	* it's not associated with the PCI device, then
2757	* any number up to UINT8_MAX is fine.
2758	* @param cb The size (in bytes) of the region.
2759	* @param fFlags Reserved for future use, must be zero.
2760	* @param ppv Where to store the address of the ring-3 mapping
2761	* of the memory.
2762	* @param pszDesc Pointer to description string. This must not be
2763	* freed.
2764	* @thread EMT.
2765	* @deprecated
2766	*/
2767	DECLR3CALLBACKMEMBER(int, pfnMMIO2Register,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cb,
2768	uint32_t fFlags, void *ppv, const char pszDesc));
2769
2770	/**
2771	* Deregisters and frees a MMIO or MMIO2 region.
2772	*
2773	* Any physical (and virtual) access handlers registered for the region must
2774	* be deregistered before calling this function (MMIO2 only).
2775	*
2776	* @returns VBox status code.
2777	* @param pDevIns The device instance.
2778	* @param pPciDev The PCI device the region is associated with, or
2779	* NULL if not associated with any.
2780	* @param iRegion The region number used during registration.
2781	* @thread EMT.
2782	* @deprecated
2783	*/
2784	DECLR3CALLBACKMEMBER(int, pfnMMIOExDeregister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion));
2785
2786	/**
2787	* Maps a MMIO or MMIO2 region into the physical memory space.
2788	*
2789	* A MMIO2 range or a pre-registered MMIO range may overlap with base memory if
2790	* a lot of RAM is configured for the VM, in which case we'll drop the base
2791	* memory pages. Presently we will make no attempt to preserve anything that
2792	* happens to be present in the base memory that is replaced, this is of course
2793	* incorrect but it's too much effort.
2794	*
2795	* @returns VBox status code.
2796	* @param pDevIns The device instance.
2797	* @param pPciDev The PCI device the region is associated with, or
2798	* NULL if not associated with any.
2799	* @param iRegion The region number used during registration.
2800	* @param GCPhys The physical address to map it at.
2801	* @thread EMT.
2802	* @deprecated for MMIO
2803	*/
2804	DECLR3CALLBACKMEMBER(int, pfnMMIOExMap,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys));
2805
2806	/**
2807	* Unmaps a MMIO or MMIO2 region previously mapped using pfnMMIOExMap.
2808	*
2809	* @returns VBox status code.
2810	* @param pDevIns The device instance.
2811	* @param pPciDev The PCI device the region is associated with, or
2812	* NULL if not associated with any.
2813	* @param iRegion The region number used during registration.
2814	* @param GCPhys The physical address it's currently mapped at.
2815	* @thread EMT.
2816	* @deprecated for MMIO
2817	*/
2818	DECLR3CALLBACKMEMBER(int, pfnMMIOExUnmap,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys));
2819
2820	/**
2821	* Reduces the length of a MMIO2 or pre-registered MMIO range.
2822	*
2823	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2824	* only work during saved state restore. It will not call the PCI bus code, as
2825	* that is expected to restore the saved resource configuration.
2826	*
2827	* It just adjusts the mapping length of the region so that when pfnMMIOExMap is
2828	* called it will only map @a cbRegion bytes and not the value set during
2829	* registration.
2830	*
2831	* @return VBox status code.
2832	* @param pDevIns The device owning the range.
2833	* @param pPciDev The PCI device the region is associated with, or
2834	* NULL if not associated with any.
2835	* @param iRegion The region.
2836	* @param cbRegion The new size, must be smaller.
2837	*/
2838	DECLR3CALLBACKMEMBER(int, pfnMMIOExReduce,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion));
2839
2840	/**
2841	* Maps a portion of an MMIO2 region into the hypervisor region.
2842	*
2843	* Callers of this API must never deregister the MMIO2 region before the
2844	* VM is powered off.
2845	*
2846	* @return VBox status code.
2847	* @param pDevIns The device owning the MMIO2 memory.
2848	* @param pPciDev The PCI device the region is associated with, or
2849	* NULL if not associated with any.
2850	* @param iRegion The region.
2851	* @param off The offset into the region. Will be rounded down
2852	* to closest page boundary.
2853	* @param cb The number of bytes to map. Will be rounded up
2854	* to the closest page boundary.
2855	* @param pszDesc Mapping description.
2856	* @param pRCPtr Where to store the RC address.
2857	*/
2858	DECLR3CALLBACKMEMBER(int, pfnMMHyperMapMMIO2,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
2859	RTGCPHYS cb, const char *pszDesc, PRTRCPTR pRCPtr));
2860
2861	/**
2862	* Maps a portion of an MMIO2 region into kernel space (host).
2863	*
2864	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
2865	* or the VM is terminated.
2866	*
2867	* @return VBox status code.
2868	* @param pDevIns The device owning the MMIO2 memory.
2869	* @param pPciDev The PCI device the region is associated with, or
2870	* NULL if not associated with any.
2871	* @param iRegion The region.
2872	* @param off The offset into the region. Must be page
2873	* aligned.
2874	* @param cb The number of bytes to map. Must be page
2875	* aligned.
2876	* @param pszDesc Mapping description.
2877	* @param pR0Ptr Where to store the R0 address.
2878	*/
2879	DECLR3CALLBACKMEMBER(int, pfnMMIO2MapKernel,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
2880	RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr));
2881
2882	/**
2883	* Register a ROM (BIOS) region.
2884	*
2885	* It goes without saying that this is read-only memory. The memory region must be
2886	* in unassigned memory. I.e. from the top of the address space or on the PC in
2887	* the 0xa0000-0xfffff range.
2888	*
2889	* @returns VBox status.
2890	* @param pDevIns The device instance owning the ROM region.
2891	* @param GCPhysStart First physical address in the range.
2892	* Must be page aligned!
2893	* @param cbRange The size of the range (in bytes).
2894	* Must be page aligned!
2895	* @param pvBinary Pointer to the binary data backing the ROM image.
2896	* @param cbBinary The size of the binary pointer. This must
2897	* be equal or smaller than @a cbRange.
2898	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2899	* @param pszDesc Pointer to description string. This must not be freed.
2900	*
2901	* @remark There is no way to remove the rom, automatically on device cleanup or
2902	* manually from the device yet. At present I doubt we need such features...
2903	*/
2904	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2905	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2906
2907	/**
2908	* Changes the protection of shadowed ROM mapping.
2909	*
2910	* This is intented for use by the system BIOS, chipset or device in question to
2911	* change the protection of shadowed ROM code after init and on reset.
2912	*
2913	* @param pDevIns The device instance.
2914	* @param GCPhysStart Where the mapping starts.
2915	* @param cbRange The size of the mapping.
2916	* @param enmProt The new protection type.
2917	*/
2918	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2919
2920	/**
2921	* Register a save state data unit.
2922	*
2923	* @returns VBox status.
2924	* @param pDevIns The device instance.
2925	* @param uVersion Data layout version number.
2926	* @param cbGuess The approximate amount of data in the unit.
2927	* Only for progress indicators.
2928	* @param pszBefore Name of data unit which we should be put in
2929	* front of. Optional (NULL).
2930	*
2931	* @param pfnLivePrep Prepare live save callback, optional.
2932	* @param pfnLiveExec Execute live save callback, optional.
2933	* @param pfnLiveVote Vote live save callback, optional.
2934	*
2935	* @param pfnSavePrep Prepare save callback, optional.
2936	* @param pfnSaveExec Execute save callback, optional.
2937	* @param pfnSaveDone Done save callback, optional.
2938	*
2939	* @param pfnLoadPrep Prepare load callback, optional.
2940	* @param pfnLoadExec Execute load callback, optional.
2941	* @param pfnLoadDone Done load callback, optional.
2942	* @remarks Caller enters the device critical section prior to invoking the
2943	* registered callback methods.
2944	*/
2945	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2946	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2947	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2948	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2949
2950	/** @name Exported SSM Functions
2951	* @{ */
2952	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2953	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2954	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2955	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2956	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2957	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2958	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2959	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2960	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2961	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2962	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2963	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2964	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2965	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2966	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2967	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2968	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2969	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2970	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2971	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2972	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2973	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2974	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2975	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2976	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2977	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2978	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2979	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2980	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2981	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2982	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2983	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2984	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2985	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2986	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2987	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2988	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2989	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2990	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2991	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2992	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2993	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2994	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2995	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2996	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2997	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2998	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2999	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
3000	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
3001	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
3002	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
3003	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
3004	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
3005	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
3006	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
3007	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
3008	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
3009	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
3010	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
3011	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
3012	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
3013	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
3014	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
3015	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
3016	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
3017	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
3018	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
3019	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
3020	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
3021	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
3022	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
3023	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
3024	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3025	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
3026	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
3027	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
3028	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
3029	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
3030	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
3031	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
3032	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
3033	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
3034	/** @} */
3035
3036	/**
3037	* Creates a timer.
3038	*
3039	* @returns VBox status.
3040	* @param pDevIns The device instance.
3041	* @param enmClock The clock to use on this timer.
3042	* @param pfnCallback Callback function.
3043	* @param pvUser User argument for the callback.
3044	* @param fFlags Flags, see TMTIMER_FLAGS_*.
3045	* @param pszDesc Pointer to description string which must stay around
3046	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
3047	* @param ppTimer Where to store the timer on success.
3048	* @remarks Caller enters the device critical section prior to invoking the
3049	* callback.
3050	*/
3051	DECLR3CALLBACKMEMBER(int, pfnTMTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
3052	void pvUser, uint32_t fFlags, const char pszDesc, PPTMTIMERR3 ppTimer));
3053
3054	/**
3055	* Creates a timer w/ a cross context handle.
3056	*
3057	* @returns VBox status.
3058	* @param pDevIns The device instance.
3059	* @param enmClock The clock to use on this timer.
3060	* @param pfnCallback Callback function.
3061	* @param pvUser User argument for the callback.
3062	* @param fFlags Flags, see TMTIMER_FLAGS_*.
3063	* @param pszDesc Pointer to description string which must stay around
3064	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
3065	* @param phTimer Where to store the timer handle on success.
3066	* @remarks Caller enters the device critical section prior to invoking the
3067	* callback.
3068	*/
3069	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
3070	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
3071
3072	/**
3073	* Translates a timer handle to a pointer.
3074	*
3075	* @returns The time address.
3076	* @param pDevIns The device instance.
3077	* @param hTimer The timer handle.
3078	*/
3079	DECLR3CALLBACKMEMBER(PTMTIMERR3, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3080
3081	/** @name Timer handle method wrappers
3082	* @{ */
3083	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
3084	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
3085	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
3086	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3087	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3088	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3089	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3090	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3091	DECLR3CALLBACKMEMBER(int, pfnTimerLock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
3092	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
3093	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
3094	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
3095	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
3096	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
3097	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
3098	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3099	DECLR3CALLBACKMEMBER(void, pfnTimerUnlock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3100	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
3101	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3102	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3103	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3104	/** @sa TMR3TimerSkip */
3105	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
3106	/** @} */
3107
3108	/**
3109	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
3110	*
3111	* @returns pTime.
3112	* @param pDevIns The device instance.
3113	* @param pTime Where to store the time.
3114	*/
3115	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
3116
3117	/** @name Exported CFGM Functions.
3118	* @{ */
3119	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
3120	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
3121	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
3122	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3123	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3124	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
3125	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
3126	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
3127	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3128	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3129	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
3130	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
3131	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
3132	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
3133	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
3134	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
3135	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
3136	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
3137	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
3138	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
3139	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
3140	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
3141	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
3142	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
3143	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
3144	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
3145	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
3146	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
3147	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
3148	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
3149	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
3150	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
3151	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
3152	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
3153	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
3154	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
3155	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
3156	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
3157	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
3158	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
3159	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
3160	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
3161	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
3162	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
3163	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
3164	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
3165	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
3166	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
3167	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
3168	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
3169	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
3170	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
3171	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
3172	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
3173	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
3174	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
3175	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
3176	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
3177	const char pszValidValues, const char pszValidNodes,
3178	const char *pszWho, uint32_t uInstance));
3179	/** @} */
3180
3181	/**
3182	* Read physical memory.
3183	*
3184	* @returns VINF_SUCCESS (for now).
3185	* @param pDevIns The device instance.
3186	* @param GCPhys Physical address start reading from.
3187	* @param pvBuf Where to put the read bits.
3188	* @param cbRead How many bytes to read.
3189	* @thread Any thread, but the call may involve the emulation thread.
3190	*/
3191	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
3192
3193	/**
3194	* Write to physical memory.
3195	*
3196	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3197	* @param pDevIns The device instance.
3198	* @param GCPhys Physical address to write to.
3199	* @param pvBuf What to write.
3200	* @param cbWrite How many bytes to write.
3201	* @thread Any thread, but the call may involve the emulation thread.
3202	*/
3203	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
3204
3205	/**
3206	* Requests the mapping of a guest page into ring-3.
3207	*
3208	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3209	* release it.
3210	*
3211	* This API will assume your intention is to write to the page, and will
3212	* therefore replace shared and zero pages. If you do not intend to modify the
3213	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3214	*
3215	* @returns VBox status code.
3216	* @retval VINF_SUCCESS on success.
3217	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3218	* backing or if the page has any active access handlers. The caller
3219	* must fall back on using PGMR3PhysWriteExternal.
3220	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3221	*
3222	* @param pDevIns The device instance.
3223	* @param GCPhys The guest physical address of the page that
3224	* should be mapped.
3225	* @param fFlags Flags reserved for future use, MBZ.
3226	* @param ppv Where to store the address corresponding to
3227	* GCPhys.
3228	* @param pLock Where to store the lock information that
3229	* pfnPhysReleasePageMappingLock needs.
3230	*
3231	* @remark Avoid calling this API from within critical sections (other than the
3232	* PGM one) because of the deadlock risk when we have to delegating the
3233	* task to an EMT.
3234	* @thread Any.
3235	*/
3236	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3237	PPGMPAGEMAPLOCK pLock));
3238
3239	/**
3240	* Requests the mapping of a guest page into ring-3, external threads.
3241	*
3242	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3243	* release it.
3244	*
3245	* @returns VBox status code.
3246	* @retval VINF_SUCCESS on success.
3247	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3248	* backing or if the page as an active ALL access handler. The caller
3249	* must fall back on using PGMPhysRead.
3250	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3251	*
3252	* @param pDevIns The device instance.
3253	* @param GCPhys The guest physical address of the page that
3254	* should be mapped.
3255	* @param fFlags Flags reserved for future use, MBZ.
3256	* @param ppv Where to store the address corresponding to
3257	* GCPhys.
3258	* @param pLock Where to store the lock information that
3259	* pfnPhysReleasePageMappingLock needs.
3260	*
3261	* @remark Avoid calling this API from within critical sections.
3262	* @thread Any.
3263	*/
3264	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3265	void const **ppv, PPGMPAGEMAPLOCK pLock));
3266
3267	/**
3268	* Release the mapping of a guest page.
3269	*
3270	* This is the counter part of pfnPhysGCPhys2CCPtr and
3271	* pfnPhysGCPhys2CCPtrReadOnly.
3272	*
3273	* @param pDevIns The device instance.
3274	* @param pLock The lock structure initialized by the mapping
3275	* function.
3276	*/
3277	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3278
3279	/**
3280	* Read guest physical memory by virtual address.
3281	*
3282	* @param pDevIns The device instance.
3283	* @param pvDst Where to put the read bits.
3284	* @param GCVirtSrc Guest virtual address to start reading from.
3285	* @param cb How many bytes to read.
3286	* @thread The emulation thread.
3287	*/
3288	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3289
3290	/**
3291	* Write to guest physical memory by virtual address.
3292	*
3293	* @param pDevIns The device instance.
3294	* @param GCVirtDst Guest virtual address to write to.
3295	* @param pvSrc What to write.
3296	* @param cb How many bytes to write.
3297	* @thread The emulation thread.
3298	*/
3299	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3300
3301	/**
3302	* Convert a guest virtual address to a guest physical address.
3303	*
3304	* @returns VBox status code.
3305	* @param pDevIns The device instance.
3306	* @param GCPtr Guest virtual address.
3307	* @param pGCPhys Where to store the GC physical address
3308	* corresponding to GCPtr.
3309	* @thread The emulation thread.
3310	* @remark Careful with page boundaries.
3311	*/
3312	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3313
3314	/**
3315	* Allocate memory which is associated with current VM instance
3316	* and automatically freed on it's destruction.
3317	*
3318	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3319	* @param pDevIns The device instance.
3320	* @param cb Number of bytes to allocate.
3321	*/
3322	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3323
3324	/**
3325	* Allocate memory which is associated with current VM instance
3326	* and automatically freed on it's destruction. The memory is ZEROed.
3327	*
3328	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3329	* @param pDevIns The device instance.
3330	* @param cb Number of bytes to allocate.
3331	*/
3332	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3333
3334	/**
3335	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3336	*
3337	* @param pDevIns The device instance.
3338	* @param pv Pointer to the memory to free.
3339	*/
3340	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3341
3342	/**
3343	* Gets the VM state.
3344	*
3345	* @returns VM state.
3346	* @param pDevIns The device instance.
3347	* @thread Any thread (just keep in mind that it's volatile info).
3348	*/
3349	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3350
3351	/**
3352	* Checks if the VM was teleported and hasn't been fully resumed yet.
3353	*
3354	* @returns true / false.
3355	* @param pDevIns The device instance.
3356	* @thread Any thread.
3357	*/
3358	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3359
3360	/**
3361	* Set the VM error message
3362	*
3363	* @returns rc.
3364	* @param pDevIns The device instance.
3365	* @param rc VBox status code.
3366	* @param SRC_POS Use RT_SRC_POS.
3367	* @param pszFormat Error message format string.
3368	* @param ... Error message arguments.
3369	*/
3370	DECLR3CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3371	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
3372
3373	/**
3374	* Set the VM error message
3375	*
3376	* @returns rc.
3377	* @param pDevIns The device instance.
3378	* @param rc VBox status code.
3379	* @param SRC_POS Use RT_SRC_POS.
3380	* @param pszFormat Error message format string.
3381	* @param va Error message arguments.
3382	*/
3383	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3384	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3385
3386	/**
3387	* Set the VM runtime error message
3388	*
3389	* @returns VBox status code.
3390	* @param pDevIns The device instance.
3391	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3392	* @param pszErrorId Error ID string.
3393	* @param pszFormat Error message format string.
3394	* @param ... Error message arguments.
3395	*/
3396	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3397	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
3398
3399	/**
3400	* Set the VM runtime error message
3401	*
3402	* @returns VBox status code.
3403	* @param pDevIns The device instance.
3404	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3405	* @param pszErrorId Error ID string.
3406	* @param pszFormat Error message format string.
3407	* @param va Error message arguments.
3408	*/
3409	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3410	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3411
3412	/**
3413	* Stops the VM and enters the debugger to look at the guest state.
3414	*
3415	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3416	* invoking this function directly.
3417	*
3418	* @returns VBox status code which must be passed up to the VMM.
3419	* @param pDevIns The device instance.
3420	* @param pszFile Filename of the assertion location.
3421	* @param iLine The linenumber of the assertion location.
3422	* @param pszFunction Function of the assertion location.
3423	* @param pszFormat Message. (optional)
3424	* @param args Message parameters.
3425	*/
3426	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3427	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3428
3429	/**
3430	* Register a info handler with DBGF.
3431	*
3432	* @returns VBox status code.
3433	* @param pDevIns The device instance.
3434	* @param pszName The identifier of the info.
3435	* @param pszDesc The description of the info and any arguments
3436	* the handler may take.
3437	* @param pfnHandler The handler function to be called to display the
3438	* info.
3439	*/
3440	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3441
3442	/**
3443	* Register a info handler with DBGF, argv style.
3444	*
3445	* @returns VBox status code.
3446	* @param pDevIns The device instance.
3447	* @param pszName The identifier of the info.
3448	* @param pszDesc The description of the info and any arguments
3449	* the handler may take.
3450	* @param pfnHandler The handler function to be called to display the
3451	* info.
3452	*/
3453	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3454
3455	/**
3456	* Registers a set of registers for a device.
3457	*
3458	* The @a pvUser argument of the getter and setter callbacks will be
3459	* @a pDevIns. The register names will be prefixed by the device name followed
3460	* immediately by the instance number.
3461	*
3462	* @returns VBox status code.
3463	* @param pDevIns The device instance.
3464	* @param paRegisters The register descriptors.
3465	*
3466	* @remarks The device critical section is NOT entered prior to working the
3467	* callbacks registered via this helper!
3468	*/
3469	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3470
3471	/**
3472	* Gets the trace buffer handle.
3473	*
3474	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3475	* really inteded for direct usage, thus no inline wrapper function.
3476	*
3477	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3478	* @param pDevIns The device instance.
3479	*/
3480	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3481
3482	/**
3483	* Registers a statistics sample.
3484	*
3485	* @param pDevIns Device instance of the DMA.
3486	* @param pvSample Pointer to the sample.
3487	* @param enmType Sample type. This indicates what pvSample is
3488	* pointing at.
3489	* @param pszName Sample name, unix path style. If this does not
3490	* start with a '/', the default prefix will be
3491	* prepended, otherwise it will be used as-is.
3492	* @param enmUnit Sample unit.
3493	* @param pszDesc Sample description.
3494	*/
3495	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3496
3497	/**
3498	* Same as pfnSTAMRegister except that the name is specified in a
3499	* RTStrPrintfV like fashion.
3500	*
3501	* @returns VBox status.
3502	* @param pDevIns Device instance of the DMA.
3503	* @param pvSample Pointer to the sample.
3504	* @param enmType Sample type. This indicates what pvSample is
3505	* pointing at.
3506	* @param enmVisibility Visibility type specifying whether unused
3507	* statistics should be visible or not.
3508	* @param enmUnit Sample unit.
3509	* @param pszDesc Sample description.
3510	* @param pszName Sample name format string, unix path style. If
3511	* this does not start with a '/', the default
3512	* prefix will be prepended, otherwise it will be
3513	* used as-is.
3514	* @param args Arguments to the format string.
3515	*/
3516	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3517	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3518	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3519
3520	/**
3521	* Registers a PCI device with the default PCI bus.
3522	*
3523	* If a PDM device has more than one PCI device, they must be registered in the
3524	* order of PDMDEVINSR3::apPciDevs.
3525	*
3526	* @returns VBox status code.
3527	* @param pDevIns The device instance.
3528	* @param pPciDev The PCI device structure.
3529	* This must be kept in the instance data.
3530	* The PCI configuration must be initialized before registration.
3531	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
3532	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3533	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3534	* device number (0-31). This will be ignored if
3535	* the CFGM configuration contains a PCIDeviceNo
3536	* value.
3537	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3538	* function number (0-7). This will be ignored if
3539	* the CFGM configuration contains a PCIFunctionNo
3540	* value.
3541	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3542	* The pointer is saved, so don't free or changed.
3543	* @note The PCI device configuration is now implicit from the apPciDevs
3544	* index, meaning that the zero'th entry is the primary one and
3545	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3546	*/
3547	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3548	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3549
3550	/**
3551	* Initialize MSI or MSI-X emulation support for the given PCI device.
3552	*
3553	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3554	*
3555	* @returns VBox status code.
3556	* @param pDevIns The device instance.
3557	* @param pPciDev The PCI device. NULL is an alias for the first
3558	* one registered.
3559	* @param pMsiReg MSI emulation registration structure.
3560	*/
3561	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3562
3563	/**
3564	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3565	*
3566	* @returns VBox status code.
3567	* @param pDevIns The device instance.
3568	* @param pPciDev The PCI device structure. If NULL the default
3569	* PCI device for this device instance is used.
3570	* @param iRegion The region number.
3571	* @param cbRegion Size of the region.
3572	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3573	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3574	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3575	* @a fFlags, UINT64_MAX if no handle is passed
3576	* (old style).
3577	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3578	* handle is specified. The callback will be
3579	* invoked holding only the PDM lock. The device
3580	* lock will _not_ be taken (due to lock order).
3581	*/
3582	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3583	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3584	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3585
3586	/**
3587	* Register PCI configuration space read/write callbacks.
3588	*
3589	* @returns VBox status code.
3590	* @param pDevIns The device instance.
3591	* @param pPciDev The PCI device structure. If NULL the default
3592	* PCI device for this device instance is used.
3593	* @param pfnRead Pointer to the user defined PCI config read function.
3594	* to call default PCI config read function. Can be NULL.
3595	* @param pfnWrite Pointer to the user defined PCI config write function.
3596	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3597	* is NOT take because that is very likely be a lock order violation.
3598	* @thread EMT(0)
3599	* @note Only callable during VM creation.
3600	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3601	*/
3602	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3603	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3604
3605	/**
3606	* Perform a PCI configuration space write.
3607	*
3608	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3609	*
3610	* @returns Strict VBox status code (mainly DBGFSTOP).
3611	* @param pDevIns The device instance.
3612	* @param pPciDev The PCI device which config space is being read.
3613	* @param uAddress The config space address.
3614	* @param cb The size of the read: 1, 2 or 4 bytes.
3615	* @param u32Value The value to write.
3616	*/
3617	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3618	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3619
3620	/**
3621	* Perform a PCI configuration space read.
3622	*
3623	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3624	*
3625	* @returns Strict VBox status code (mainly DBGFSTOP).
3626	* @param pDevIns The device instance.
3627	* @param pPciDev The PCI device which config space is being read.
3628	* @param uAddress The config space address.
3629	* @param cb The size of the read: 1, 2 or 4 bytes.
3630	* @param pu32Value Where to return the value.
3631	*/
3632	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3633	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3634
3635	/**
3636	* Bus master physical memory read.
3637	*
3638	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3639	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3640	* @param pDevIns The device instance.
3641	* @param pPciDev The PCI device structure. If NULL the default
3642	* PCI device for this device instance is used.
3643	* @param GCPhys Physical address start reading from.
3644	* @param pvBuf Where to put the read bits.
3645	* @param cbRead How many bytes to read.
3646	* @thread Any thread, but the call may involve the emulation thread.
3647	*/
3648	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
3649
3650	/**
3651	* Bus master physical memory write.
3652	*
3653	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3654	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3655	* @param pDevIns The device instance.
3656	* @param pPciDev The PCI device structure. If NULL the default
3657	* PCI device for this device instance is used.
3658	* @param GCPhys Physical address to write to.
3659	* @param pvBuf What to write.
3660	* @param cbWrite How many bytes to write.
3661	* @thread Any thread, but the call may involve the emulation thread.
3662	*/
3663	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
3664
3665	/**
3666	* Sets the IRQ for the given PCI device.
3667	*
3668	* @param pDevIns The device instance.
3669	* @param pPciDev The PCI device structure. If NULL the default
3670	* PCI device for this device instance is used.
3671	* @param iIrq IRQ number to set.
3672	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3673	* @thread Any thread, but will involve the emulation thread.
3674	*/
3675	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3676
3677	/**
3678	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3679	* the request when not called from EMT.
3680	*
3681	* @param pDevIns The device instance.
3682	* @param pPciDev The PCI device structure. If NULL the default
3683	* PCI device for this device instance is used.
3684	* @param iIrq IRQ number to set.
3685	* @param iLevel IRQ level.
3686	* @thread Any thread, but will involve the emulation thread.
3687	*/
3688	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3689
3690	/**
3691	* Set ISA IRQ for a device.
3692	*
3693	* @param pDevIns The device instance.
3694	* @param iIrq IRQ number to set.
3695	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3696	* @thread Any thread, but will involve the emulation thread.
3697	*/
3698	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3699
3700	/**
3701	* Set the ISA IRQ for a device, but don't wait for EMT to process
3702	* the request when not called from EMT.
3703	*
3704	* @param pDevIns The device instance.
3705	* @param iIrq IRQ number to set.
3706	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3707	* @thread Any thread, but will involve the emulation thread.
3708	*/
3709	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3710
3711	/**
3712	* Send an MSI straight to the I/O APIC.
3713	*
3714	* @param pDevIns PCI device instance.
3715	* @param GCPhys Physical address MSI request was written.
3716	* @param uValue Value written.
3717	* @thread Any thread, but will involve the emulation thread.
3718	*/
3719	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
3720
3721	/**
3722	* Attaches a driver (chain) to the device.
3723	*
3724	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3725	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3726	*
3727	* @returns VBox status code.
3728	* @param pDevIns The device instance.
3729	* @param iLun The logical unit to attach.
3730	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3731	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3732	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3733	* for the live of the device instance.
3734	*/
3735	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3736	PPDMIBASE ppBaseInterface, const char pszDesc));
3737
3738	/**
3739	* Detaches an attached driver (chain) from the device again.
3740	*
3741	* @returns VBox status code.
3742	* @param pDevIns The device instance.
3743	* @param pDrvIns The driver instance to detach.
3744	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3745	*/
3746	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3747
3748	/** @name Exported PDM Queue Functions
3749	* @{ */
3750	/**
3751	* Create a queue.
3752	*
3753	* @returns VBox status code.
3754	* @param pDevIns The device instance.
3755	* @param cbItem The size of a queue item.
3756	* @param cItems The number of items in the queue.
3757	* @param cMilliesInterval The number of milliseconds between polling the queue.
3758	* If 0 then the emulation thread will be notified whenever an item arrives.
3759	* @param pfnCallback The consumer function.
3760	* @param fRZEnabled Set if the queue should work in RC and R0.
3761	* @param pszName The queue base name. The instance number will be
3762	* appended automatically.
3763	* @param ppQueue Where to store the queue pointer on success.
3764	* @thread The emulation thread.
3765	* @remarks The device critical section will NOT be entered before calling the
3766	* callback. No locks will be held, but for now it's safe to assume
3767	* that only one EMT will do queue callbacks at any one time.
3768	*/
3769	DECLR3CALLBACKMEMBER(int, pfnQueueCreatePtr,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3770	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3771	PPDMQUEUE *ppQueue));
3772
3773	/**
3774	* Create a queue.
3775	*
3776	* @returns VBox status code.
3777	* @param pDevIns The device instance.
3778	* @param cbItem The size of a queue item.
3779	* @param cItems The number of items in the queue.
3780	* @param cMilliesInterval The number of milliseconds between polling the queue.
3781	* If 0 then the emulation thread will be notified whenever an item arrives.
3782	* @param pfnCallback The consumer function.
3783	* @param fRZEnabled Set if the queue should work in RC and R0.
3784	* @param pszName The queue base name. The instance number will be
3785	* appended automatically.
3786	* @param phQueue Where to store the queue handle on success.
3787	* @thread EMT(0)
3788	* @remarks The device critical section will NOT be entered before calling the
3789	* callback. No locks will be held, but for now it's safe to assume
3790	* that only one EMT will do queue callbacks at any one time.
3791	*/
3792	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3793	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3794	PDMQUEUEHANDLE *phQueue));
3795
3796	DECLR3CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3797	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3798	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3799	DECLR3CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
3800	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3801	/** @} */
3802
3803	/** @name PDM Task
3804	* @{ */
3805	/**
3806	* Create an asynchronous ring-3 task.
3807	*
3808	* @returns VBox status code.
3809	* @param pDevIns The device instance.
3810	* @param fFlags PDMTASK_F_XXX
3811	* @param pszName The function name or similar. Used for statistics,
3812	* so no slashes.
3813	* @param pfnCallback The task function.
3814	* @param pvUser User argument for the task function.
3815	* @param phTask Where to return the task handle.
3816	* @thread EMT(0)
3817	*/
3818	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3819	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3820	/**
3821	* Triggers the running the given task.
3822	*
3823	* @returns VBox status code.
3824	* @retval VINF_ALREADY_POSTED is the task is already pending.
3825	* @param pDevIns The device instance.
3826	* @param hTask The task to trigger.
3827	* @thread Any thread.
3828	*/
3829	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3830	/** @} */
3831
3832	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3833	* These semaphores can be signalled from ring-0.
3834	* @{ */
3835	/** @sa SUPSemEventCreate */
3836	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3837	/** @sa SUPSemEventClose */
3838	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3839	/** @sa SUPSemEventSignal */
3840	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3841	/** @sa SUPSemEventWaitNoResume */
3842	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3843	/** @sa SUPSemEventWaitNsAbsIntr */
3844	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3845	/** @sa SUPSemEventWaitNsRelIntr */
3846	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3847	/** @sa SUPSemEventGetResolution */
3848	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3849	/** @} */
3850
3851	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3852	* These semaphores can be signalled from ring-0.
3853	* @{ */
3854	/** @sa SUPSemEventMultiCreate */
3855	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3856	/** @sa SUPSemEventMultiClose */
3857	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3858	/** @sa SUPSemEventMultiSignal */
3859	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3860	/** @sa SUPSemEventMultiReset */
3861	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3862	/** @sa SUPSemEventMultiWaitNoResume */
3863	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3864	/** @sa SUPSemEventMultiWaitNsAbsIntr */
3865	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3866	/** @sa SUPSemEventMultiWaitNsRelIntr */
3867	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3868	/** @sa SUPSemEventMultiGetResolution */
3869	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3870	/** @} */
3871
3872	/**
3873	* Initializes a PDM critical section.
3874	*
3875	* The PDM critical sections are derived from the IPRT critical sections, but
3876	* works in RC and R0 as well.
3877	*
3878	* @returns VBox status code.
3879	* @param pDevIns The device instance.
3880	* @param pCritSect Pointer to the critical section.
3881	* @param SRC_POS Use RT_SRC_POS.
3882	* @param pszNameFmt Format string for naming the critical section.
3883	* For statistics and lock validation.
3884	* @param va Arguments for the format string.
3885	*/
3886	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3887	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3888
3889	/**
3890	* Gets the NOP critical section.
3891	*
3892	* @returns The ring-3 address of the NOP critical section.
3893	* @param pDevIns The device instance.
3894	*/
3895	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3896
3897	/**
3898	* Gets the NOP critical section.
3899	*
3900	* @returns The ring-0 address of the NOP critical section.
3901	* @param pDevIns The device instance.
3902	* @deprecated
3903	*/
3904	DECLR3CALLBACKMEMBER(R0PTRTYPE(PPDMCRITSECT), pfnCritSectGetNopR0,(PPDMDEVINS pDevIns));
3905
3906	/**
3907	* Gets the NOP critical section.
3908	*
3909	* @returns The raw-mode context address of the NOP critical section.
3910	* @param pDevIns The device instance.
3911	* @deprecated
3912	*/
3913	DECLR3CALLBACKMEMBER(RCPTRTYPE(PPDMCRITSECT), pfnCritSectGetNopRC,(PPDMDEVINS pDevIns));
3914
3915	/**
3916	* Changes the device level critical section from the automatically created
3917	* default to one desired by the device constructor.
3918	*
3919	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
3920	* the additional contexts.
3921	*
3922	* @returns VBox status code.
3923	* @param pDevIns The device instance.
3924	* @param pCritSect The critical section to use. NULL is not
3925	* valid, instead use the NOP critical
3926	* section.
3927	*/
3928	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3929
3930	/** @name Exported PDM Critical Section Functions
3931	* @{ */
3932	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3933	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3934	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3935	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3936	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3937	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3938	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3939	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3940	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3941	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3942	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3943	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3944	/** @} */
3945
3946	/**
3947	* Creates a PDM thread.
3948	*
3949	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3950	* resuming, and destroying the thread as the VM state changes.
3951	*
3952	* @returns VBox status code.
3953	* @param pDevIns The device instance.
3954	* @param ppThread Where to store the thread 'handle'.
3955	* @param pvUser The user argument to the thread function.
3956	* @param pfnThread The thread function.
3957	* @param pfnWakeup The wakup callback. This is called on the EMT
3958	* thread when a state change is pending.
3959	* @param cbStack See RTThreadCreate.
3960	* @param enmType See RTThreadCreate.
3961	* @param pszName See RTThreadCreate.
3962	* @remarks The device critical section will NOT be entered prior to invoking
3963	* the function pointers.
3964	*/
3965	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3966	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3967
3968	/** @name Exported PDM Thread Functions
3969	* @{ */
3970	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3971	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3972	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3973	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3974	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3975	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3976	/** @} */
3977
3978	/**
3979	* Set up asynchronous handling of a suspend, reset or power off notification.
3980	*
3981	* This shall only be called when getting the notification. It must be called
3982	* for each one.
3983	*
3984	* @returns VBox status code.
3985	* @param pDevIns The device instance.
3986	* @param pfnAsyncNotify The callback.
3987	* @thread EMT(0)
3988	* @remarks The caller will enter the device critical section prior to invoking
3989	* the callback.
3990	*/
3991	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3992
3993	/**
3994	* Notify EMT(0) that the device has completed the asynchronous notification
3995	* handling.
3996	*
3997	* This can be called at any time, spurious calls will simply be ignored.
3998	*
3999	* @param pDevIns The device instance.
4000	* @thread Any
4001	*/
4002	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
4003
4004	/**
4005	* Register the RTC device.
4006	*
4007	* @returns VBox status code.
4008	* @param pDevIns The device instance.
4009	* @param pRtcReg Pointer to a RTC registration structure.
4010	* @param ppRtcHlp Where to store the pointer to the helper
4011	* functions.
4012	*/
4013	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
4014
4015	/**
4016	* Register a PCI Bus.
4017	*
4018	* @returns VBox status code, but the positive values 0..31 are used to indicate
4019	* bus number rather than informational status codes.
4020	* @param pDevIns The device instance.
4021	* @param pPciBusReg Pointer to PCI bus registration structure.
4022	* @param ppPciHlp Where to store the pointer to the PCI Bus
4023	* helpers.
4024	* @param piBus Where to return the PDM bus number. Optional.
4025	*/
4026	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
4027	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
4028
4029	/**
4030	* Register the PIC device.
4031	*
4032	* @returns VBox status code.
4033	* @param pDevIns The device instance.
4034	* @param pPicReg Pointer to a PIC registration structure.
4035	* @param ppPicHlpR3 Where to store the pointer to the PIC HC
4036	* helpers.
4037	*/
4038	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3));
4039
4040	/**
4041	* Register the APIC device.
4042	*
4043	* @returns VBox status code.
4044	* @param pDevIns The device instance.
4045	*/
4046	DECLR3CALLBACKMEMBER(int, pfnAPICRegister,(PPDMDEVINS pDevIns));
4047
4048	/**
4049	* Register the I/O APIC device.
4050	*
4051	* @returns VBox status code.
4052	* @param pDevIns The device instance.
4053	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4054	* @param ppIoApicHlpR3 Where to store the pointer to the IOAPIC
4055	* helpers.
4056	*/
4057	DECLR3CALLBACKMEMBER(int, pfnIOAPICRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3));
4058
4059	/**
4060	* Register the HPET device.
4061	*
4062	* @returns VBox status code.
4063	* @param pDevIns The device instance.
4064	* @param pHpetReg Pointer to a HPET registration structure.
4065	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4066	* helpers.
4067	*/
4068	DECLR3CALLBACKMEMBER(int, pfnHPETRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4069
4070	/**
4071	* Register a raw PCI device.
4072	*
4073	* @returns VBox status code.
4074	* @param pDevIns The device instance.
4075	* @param pPciRawReg Pointer to a raw PCI registration structure.
4076	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4077	* device helpers.
4078	*/
4079	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4080
4081	/**
4082	* Register the DMA device.
4083	*
4084	* @returns VBox status code.
4085	* @param pDevIns The device instance.
4086	* @param pDmacReg Pointer to a DMAC registration structure.
4087	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4088	*/
4089	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4090
4091	/**
4092	* Register transfer function for DMA channel.
4093	*
4094	* @returns VBox status code.
4095	* @param pDevIns The device instance.
4096	* @param uChannel Channel number.
4097	* @param pfnTransferHandler Device specific transfer callback function.
4098	* @param pvUser User pointer to pass to the callback.
4099	* @thread EMT
4100	*/
4101	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4102
4103	/**
4104	* Read memory.
4105	*
4106	* @returns VBox status code.
4107	* @param pDevIns The device instance.
4108	* @param uChannel Channel number.
4109	* @param pvBuffer Pointer to target buffer.
4110	* @param off DMA position.
4111	* @param cbBlock Block size.
4112	* @param pcbRead Where to store the number of bytes which was
4113	* read. optional.
4114	* @thread EMT
4115	*/
4116	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4117
4118	/**
4119	* Write memory.
4120	*
4121	* @returns VBox status code.
4122	* @param pDevIns The device instance.
4123	* @param uChannel Channel number.
4124	* @param pvBuffer Memory to write.
4125	* @param off DMA position.
4126	* @param cbBlock Block size.
4127	* @param pcbWritten Where to store the number of bytes which was
4128	* written. optional.
4129	* @thread EMT
4130	*/
4131	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4132
4133	/**
4134	* Set the DREQ line.
4135	*
4136	* @returns VBox status code.
4137	* @param pDevIns Device instance.
4138	* @param uChannel Channel number.
4139	* @param uLevel Level of the line.
4140	* @thread EMT
4141	*/
4142	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4143
4144	/**
4145	* Get channel mode.
4146	*
4147	* @returns Channel mode. See specs.
4148	* @param pDevIns The device instance.
4149	* @param uChannel Channel number.
4150	* @thread EMT
4151	*/
4152	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4153
4154	/**
4155	* Schedule DMA execution.
4156	*
4157	* @param pDevIns The device instance.
4158	* @thread Any thread.
4159	*/
4160	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4161
4162	/**
4163	* Write CMOS value and update the checksum(s).
4164	*
4165	* @returns VBox status code.
4166	* @param pDevIns The device instance.
4167	* @param iReg The CMOS register index.
4168	* @param u8Value The CMOS register value.
4169	* @thread EMT
4170	*/
4171	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4172
4173	/**
4174	* Read CMOS value.
4175	*
4176	* @returns VBox status code.
4177	* @param pDevIns The device instance.
4178	* @param iReg The CMOS register index.
4179	* @param pu8Value Where to store the CMOS register value.
4180	* @thread EMT
4181	*/
4182	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4183
4184	/**
4185	* Assert that the current thread is the emulation thread.
4186	*
4187	* @returns True if correct.
4188	* @returns False if wrong.
4189	* @param pDevIns The device instance.
4190	* @param pszFile Filename of the assertion location.
4191	* @param iLine The linenumber of the assertion location.
4192	* @param pszFunction Function of the assertion location.
4193	*/
4194	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4195
4196	/**
4197	* Assert that the current thread is NOT the emulation thread.
4198	*
4199	* @returns True if correct.
4200	* @returns False if wrong.
4201	* @param pDevIns The device instance.
4202	* @param pszFile Filename of the assertion location.
4203	* @param iLine The linenumber of the assertion location.
4204	* @param pszFunction Function of the assertion location.
4205	*/
4206	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4207
4208	/**
4209	* Resolves the symbol for a raw-mode context interface.
4210	*
4211	* @returns VBox status code.
4212	* @param pDevIns The device instance.
4213	* @param pvInterface The interface structure.
4214	* @param cbInterface The size of the interface structure.
4215	* @param pszSymPrefix What to prefix the symbols in the list with
4216	* before resolving them. This must start with
4217	* 'dev' and contain the driver name.
4218	* @param pszSymList List of symbols corresponding to the interface.
4219	* There is generally a there is generally a define
4220	* holding this list associated with the interface
4221	* definition (INTERFACE_SYM_LIST). For more
4222	* details see PDMR3LdrGetInterfaceSymbols.
4223	* @thread EMT
4224	*/
4225	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4226	const char pszSymPrefix, const char pszSymList));
4227
4228	/**
4229	* Resolves the symbol for a ring-0 context interface.
4230	*
4231	* @returns VBox status code.
4232	* @param pDevIns The device instance.
4233	* @param pvInterface The interface structure.
4234	* @param cbInterface The size of the interface structure.
4235	* @param pszSymPrefix What to prefix the symbols in the list with
4236	* before resolving them. This must start with
4237	* 'dev' and contain the driver name.
4238	* @param pszSymList List of symbols corresponding to the interface.
4239	* There is generally a there is generally a define
4240	* holding this list associated with the interface
4241	* definition (INTERFACE_SYM_LIST). For more
4242	* details see PDMR3LdrGetInterfaceSymbols.
4243	* @thread EMT
4244	*/
4245	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4246	const char pszSymPrefix, const char pszSymList));
4247
4248	/**
4249	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4250	*
4251	* @returns VBox status code.
4252	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4253	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4254	*
4255	* @param pDevIns The device instance.
4256	* @param uOperation The operation to perform.
4257	* @param u64Arg 64-bit integer argument.
4258	* @thread EMT
4259	*/
4260	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4261
4262	/**
4263	* Gets the reason for the most recent VM suspend.
4264	*
4265	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4266	* suspend has been made or if the pDevIns is invalid.
4267	* @param pDevIns The device instance.
4268	*/
4269	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4270
4271	/**
4272	* Gets the reason for the most recent VM resume.
4273	*
4274	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4275	* resume has been made or if the pDevIns is invalid.
4276	* @param pDevIns The device instance.
4277	*/
4278	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4279
4280	/**
4281	* Requests the mapping of multiple guest page into ring-3.
4282	*
4283	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4284	* ASAP to release them.
4285	*
4286	* This API will assume your intention is to write to the pages, and will
4287	* therefore replace shared and zero pages. If you do not intend to modify the
4288	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4289	*
4290	* @returns VBox status code.
4291	* @retval VINF_SUCCESS on success.
4292	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4293	* backing or if any of the pages the page has any active access
4294	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4295	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4296	* an invalid physical address.
4297	*
4298	* @param pDevIns The device instance.
4299	* @param cPages Number of pages to lock.
4300	* @param paGCPhysPages The guest physical address of the pages that
4301	* should be mapped (@a cPages entries).
4302	* @param fFlags Flags reserved for future use, MBZ.
4303	* @param papvPages Where to store the ring-3 mapping addresses
4304	* corresponding to @a paGCPhysPages.
4305	* @param paLocks Where to store the locking information that
4306	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4307	* in length).
4308	*
4309	* @remark Avoid calling this API from within critical sections (other than the
4310	* PGM one) because of the deadlock risk when we have to delegating the
4311	* task to an EMT.
4312	* @thread Any.
4313	* @since 6.0.6
4314	*/
4315	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4316	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4317
4318	/**
4319	* Requests the mapping of multiple guest page into ring-3, for reading only.
4320	*
4321	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4322	* ASAP to release them.
4323	*
4324	* @returns VBox status code.
4325	* @retval VINF_SUCCESS on success.
4326	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4327	* backing or if any of the pages the page has an active ALL access
4328	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4329	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4330	* an invalid physical address.
4331	*
4332	* @param pDevIns The device instance.
4333	* @param cPages Number of pages to lock.
4334	* @param paGCPhysPages The guest physical address of the pages that
4335	* should be mapped (@a cPages entries).
4336	* @param fFlags Flags reserved for future use, MBZ.
4337	* @param papvPages Where to store the ring-3 mapping addresses
4338	* corresponding to @a paGCPhysPages.
4339	* @param paLocks Where to store the lock information that
4340	* pfnPhysReleasePageMappingLock needs (@a cPages
4341	* in length).
4342	*
4343	* @remark Avoid calling this API from within critical sections.
4344	* @thread Any.
4345	* @since 6.0.6
4346	*/
4347	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4348	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4349
4350	/**
4351	* Release the mappings of multiple guest pages.
4352	*
4353	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4354	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4355	*
4356	* @param pDevIns The device instance.
4357	* @param cPages Number of pages to unlock.
4358	* @param paLocks The lock structures initialized by the mapping
4359	* function (@a cPages in length).
4360	* @thread Any.
4361	* @since 6.0.6
4362	*/
4363	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4364
4365	/**
4366	* Changes the number of an MMIO2 or pre-registered MMIO region.
4367	*
4368	* This should only be used to deal with saved state problems, so there is no
4369	* convenience inline wrapper for this method.
4370	*
4371	* @returns VBox status code.
4372	* @param pDevIns The device instance.
4373	* @param pPciDev The PCI device the region is associated with, or
4374	* NULL if not associated with any.
4375	* @param iRegion The region.
4376	* @param iNewRegion The new region index.
4377	*
4378	* @sa @bugref{9359}
4379	*/
4380	DECLR3CALLBACKMEMBER(int, pfnMMIOExChangeRegionNo,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4381	uint32_t iNewRegion));
4382
4383	/** Space reserved for future members.
4384	* @{ */
4385	DECLR3CALLBACKMEMBER(void, pfnReserved1,(void));
4386	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4387	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4388	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4389	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4390	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4391	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4392	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4393	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4394	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4395	/** @} */
4396
4397
4398	/** API available to trusted devices only.
4399	*
4400	* These APIs are providing unrestricted access to the guest and the VM,
4401	* or they are interacting intimately with PDM.
4402	*
4403	* @{
4404	*/
4405
4406	/**
4407	* Gets the user mode VM handle. Restricted API.
4408	*
4409	* @returns User mode VM Handle.
4410	* @param pDevIns The device instance.
4411	*/
4412	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4413
4414	/**
4415	* Gets the global VM handle. Restricted API.
4416	*
4417	* @returns VM Handle.
4418	* @param pDevIns The device instance.
4419	*/
4420	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4421
4422	/**
4423	* Gets the VMCPU handle. Restricted API.
4424	*
4425	* @returns VMCPU Handle.
4426	* @param pDevIns The device instance.
4427	*/
4428	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4429
4430	/**
4431	* The the VM CPU ID of the current thread (restricted API).
4432	*
4433	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4434	* @param pDevIns The device instance.
4435	*/
4436	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4437
4438	/**
4439	* Registers the VMM device heap or notifies about mapping/unmapping.
4440	*
4441	* This interface serves three purposes:
4442	*
4443	* -# Register the VMM device heap during device construction
4444	* for the HM to use.
4445	* -# Notify PDM/HM that it's mapped into guest address
4446	* space (i.e. usable).
4447	* -# Notify PDM/HM that it is being unmapped from the guest
4448	* address space (i.e. not usable).
4449	*
4450	* @returns VBox status code.
4451	* @param pDevIns The device instance.
4452	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4453	* not mapped.
4454	* @param pvHeap Ring 3 heap pointer.
4455	* @param cbHeap Size of the heap.
4456	* @thread EMT.
4457	*/
4458	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4459
4460	/**
4461	* Registers the firmware (BIOS, EFI) device with PDM.
4462	*
4463	* The firmware provides a callback table and gets a special PDM helper table.
4464	* There can only be one firmware device for a VM.
4465	*
4466	* @returns VBox status code.
4467	* @param pDevIns The device instance.
4468	* @param pFwReg Firmware registration structure.
4469	* @param ppFwHlp Where to return the firmware helper structure.
4470	* @remarks Only valid during device construction.
4471	* @thread EMT(0)
4472	*/
4473	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4474
4475	/**
4476	* Resets the VM.
4477	*
4478	* @returns The appropriate VBox status code to pass around on reset.
4479	* @param pDevIns The device instance.
4480	* @param fFlags PDMVMRESET_F_XXX flags.
4481	* @thread The emulation thread.
4482	*/
4483	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4484
4485	/**
4486	* Suspends the VM.
4487	*
4488	* @returns The appropriate VBox status code to pass around on suspend.
4489	* @param pDevIns The device instance.
4490	* @thread The emulation thread.
4491	*/
4492	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4493
4494	/**
4495	* Suspends, saves and powers off the VM.
4496	*
4497	* @returns The appropriate VBox status code to pass around.
4498	* @param pDevIns The device instance.
4499	* @thread An emulation thread.
4500	*/
4501	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4502
4503	/**
4504	* Power off the VM.
4505	*
4506	* @returns The appropriate VBox status code to pass around on power off.
4507	* @param pDevIns The device instance.
4508	* @thread The emulation thread.
4509	*/
4510	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4511
4512	/**
4513	* Checks if the Gate A20 is enabled or not.
4514	*
4515	* @returns true if A20 is enabled.
4516	* @returns false if A20 is disabled.
4517	* @param pDevIns The device instance.
4518	* @thread The emulation thread.
4519	*/
4520	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4521
4522	/**
4523	* Enables or disables the Gate A20.
4524	*
4525	* @param pDevIns The device instance.
4526	* @param fEnable Set this flag to enable the Gate A20; clear it
4527	* to disable.
4528	* @thread The emulation thread.
4529	*/
4530	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4531
4532	/**
4533	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4534	* thread.
4535	*
4536	* @param pDevIns The device instance.
4537	* @param iLeaf The CPUID leaf to get.
4538	* @param pEax Where to store the EAX value.
4539	* @param pEbx Where to store the EBX value.
4540	* @param pEcx Where to store the ECX value.
4541	* @param pEdx Where to store the EDX value.
4542	* @thread EMT.
4543	*/
4544	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4545
4546	/**
4547	* Get the current virtual clock time in a VM. The clock frequency must be
4548	* queried separately.
4549	*
4550	* @returns Current clock time.
4551	* @param pDevIns The device instance.
4552	*/
4553	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4554
4555	/**
4556	* Get the frequency of the virtual clock.
4557	*
4558	* @returns The clock frequency (not variable at run-time).
4559	* @param pDevIns The device instance.
4560	*/
4561	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4562
4563	/**
4564	* Get the current virtual clock time in a VM, in nanoseconds.
4565	*
4566	* @returns Current clock time (in ns).
4567	* @param pDevIns The device instance.
4568	*/
4569	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4570
4571	/**
4572	* Gets the support driver session.
4573	*
4574	* This is intended for working with the semaphore API.
4575	*
4576	* @returns Support driver session handle.
4577	* @param pDevIns The device instance.
4578	*/
4579	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4580
4581	/**
4582	* Queries a generic object from the VMM user.
4583	*
4584	* @returns Pointer to the object if found, NULL if not.
4585	* @param pDevIns The device instance.
4586	* @param pUuid The UUID of what's being queried. The UUIDs and
4587	* the usage conventions are defined by the user.
4588	*
4589	* @note It is strictly forbidden to call this internally in VBox! This
4590	* interface is exclusively for hacks in externally developed devices.
4591	*/
4592	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4593
4594	/** @} */
4595
4596	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4597	uint32_t u32TheEnd;
4598	} PDMDEVHLPR3;
4599	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4600	/** Pointer to the R3 PDM Device API. */
4601	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4602	/** Pointer to the R3 PDM Device API, const variant. */
4603	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4604
4605
4606	/**
4607	* PDM Device API - RC Variant.
4608	*/
4609	typedef struct PDMDEVHLPRC
4610	{
4611	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4612	uint32_t u32Version;
4613
4614	/**
4615	* Sets up raw-mode context callback handlers for an I/O port range.
4616	*
4617	* The range must have been registered in ring-3 first using
4618	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4619	*
4620	* @returns VBox status.
4621	* @param pDevIns The device instance to register the ports with.
4622	* @param hIoPorts The I/O port range handle.
4623	* @param pfnOut Pointer to function which is gonna handle OUT
4624	* operations. Optional.
4625	* @param pfnIn Pointer to function which is gonna handle IN operations.
4626	* Optional.
4627	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4628	* operations. Optional.
4629	* @param pfnInStr Pointer to function which is gonna handle string IN
4630	* operations. Optional.
4631	* @param pvUser User argument to pass to the callbacks.
4632	*
4633	* @remarks Caller enters the device critical section prior to invoking the
4634	* registered callback methods.
4635	*
4636	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4637	* PDMDevHlpIoPortUnmap.
4638	*/
4639	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4640	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4641	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4642	void *pvUser));
4643
4644	/**
4645	* Sets up raw-mode context callback handlers for an MMIO region.
4646	*
4647	* The region must have been registered in ring-3 first using
4648	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4649	*
4650	* @returns VBox status.
4651	* @param pDevIns The device instance to register the ports with.
4652	* @param hRegion The MMIO region handle.
4653	* @param pfnWrite Pointer to function which is gonna handle Write
4654	* operations.
4655	* @param pfnRead Pointer to function which is gonna handle Read
4656	* operations.
4657	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4658	* operations. (optional)
4659	* @param pvUser User argument to pass to the callbacks.
4660	*
4661	* @remarks Caller enters the device critical section prior to invoking the
4662	* registered callback methods.
4663	*
4664	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4665	* PDMDevHlpMmioUnmap.
4666	*/
4667	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4668	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4669
4670	/**
4671	* Sets up a raw-mode mapping for an MMIO2 region.
4672	*
4673	* The region must have been created in ring-3 first using
4674	* PDMDevHlpMmio2Create().
4675	*
4676	* @returns VBox status.
4677	* @param pDevIns The device instance to register the ports with.
4678	* @param hRegion The MMIO2 region handle.
4679	* @param offSub Start of what to map into raw-mode. Must be page aligned.
4680	* @param cbSub Number of bytes to map into raw-mode. Must be page
4681	* aligned. Zero is an alias for everything.
4682	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4683	* @thread EMT(0)
4684	* @note Only available at VM creation time.
4685	*
4686	* @sa PDMDevHlpMmio2Create().
4687	*/
4688	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4689	size_t offSub, size_t cbSub, void **ppvMapping));
4690
4691	/**
4692	* Bus master physical memory read from the given PCI device.
4693	*
4694	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4695	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4696	* @param pDevIns The device instance.
4697	* @param pPciDev The PCI device structure. If NULL the default
4698	* PCI device for this device instance is used.
4699	* @param GCPhys Physical address start reading from.
4700	* @param pvBuf Where to put the read bits.
4701	* @param cbRead How many bytes to read.
4702	* @thread Any thread, but the call may involve the emulation thread.
4703	*/
4704	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4705	void *pvBuf, size_t cbRead));
4706
4707	/**
4708	* Bus master physical memory write from the given PCI device.
4709	*
4710	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4711	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4712	* @param pDevIns The device instance.
4713	* @param pPciDev The PCI device structure. If NULL the default
4714	* PCI device for this device instance is used.
4715	* @param GCPhys Physical address to write to.
4716	* @param pvBuf What to write.
4717	* @param cbWrite How many bytes to write.
4718	* @thread Any thread, but the call may involve the emulation thread.
4719	*/
4720	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4721	const void *pvBuf, size_t cbWrite));
4722
4723	/**
4724	* Set the IRQ for the given PCI device.
4725	*
4726	* @param pDevIns Device instance.
4727	* @param pPciDev The PCI device structure. If NULL the default
4728	* PCI device for this device instance is used.
4729	* @param iIrq IRQ number to set.
4730	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4731	* @thread Any thread, but will involve the emulation thread.
4732	*/
4733	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4734
4735	/**
4736	* Set ISA IRQ for a device.
4737	*
4738	* @param pDevIns Device instance.
4739	* @param iIrq IRQ number to set.
4740	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4741	* @thread Any thread, but will involve the emulation thread.
4742	*/
4743	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4744
4745	/**
4746	* Send an MSI straight to the I/O APIC.
4747	*
4748	* @param pDevIns PCI device instance.
4749	* @param GCPhys Physical address MSI request was written.
4750	* @param uValue Value written.
4751	* @thread Any thread, but will involve the emulation thread.
4752	*/
4753	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
4754
4755	/**
4756	* Read physical memory.
4757	*
4758	* @returns VINF_SUCCESS (for now).
4759	* @param pDevIns Device instance.
4760	* @param GCPhys Physical address start reading from.
4761	* @param pvBuf Where to put the read bits.
4762	* @param cbRead How many bytes to read.
4763	*/
4764	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
4765
4766	/**
4767	* Write to physical memory.
4768	*
4769	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4770	* @param pDevIns Device instance.
4771	* @param GCPhys Physical address to write to.
4772	* @param pvBuf What to write.
4773	* @param cbWrite How many bytes to write.
4774	*/
4775	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
4776
4777	/**
4778	* Checks if the Gate A20 is enabled or not.
4779	*
4780	* @returns true if A20 is enabled.
4781	* @returns false if A20 is disabled.
4782	* @param pDevIns Device instance.
4783	* @thread The emulation thread.
4784	*/
4785	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4786
4787	/**
4788	* Gets the VM state.
4789	*
4790	* @returns VM state.
4791	* @param pDevIns The device instance.
4792	* @thread Any thread (just keep in mind that it's volatile info).
4793	*/
4794	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4795
4796	/**
4797	* Set the VM error message
4798	*
4799	* @returns rc.
4800	* @param pDevIns Driver instance.
4801	* @param rc VBox status code.
4802	* @param SRC_POS Use RT_SRC_POS.
4803	* @param pszFormat Error message format string.
4804	* @param ... Error message arguments.
4805	*/
4806	DECLRCCALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4807	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4808
4809	/**
4810	* Set the VM error message
4811	*
4812	* @returns rc.
4813	* @param pDevIns Driver instance.
4814	* @param rc VBox status code.
4815	* @param SRC_POS Use RT_SRC_POS.
4816	* @param pszFormat Error message format string.
4817	* @param va Error message arguments.
4818	*/
4819	DECLRCCALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4820	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4821
4822	/**
4823	* Set the VM runtime error message
4824	*
4825	* @returns VBox status code.
4826	* @param pDevIns Device instance.
4827	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4828	* @param pszErrorId Error ID string.
4829	* @param pszFormat Error message format string.
4830	* @param ... Error message arguments.
4831	*/
4832	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4833	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4834
4835	/**
4836	* Set the VM runtime error message
4837	*
4838	* @returns VBox status code.
4839	* @param pDevIns Device instance.
4840	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4841	* @param pszErrorId Error ID string.
4842	* @param pszFormat Error message format string.
4843	* @param va Error message arguments.
4844	*/
4845	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4846	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
4847
4848	/**
4849	* Gets the VM handle. Restricted API.
4850	*
4851	* @returns VM Handle.
4852	* @param pDevIns Device instance.
4853	*/
4854	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4855
4856	/**
4857	* Gets the VMCPU handle. Restricted API.
4858	*
4859	* @returns VMCPU Handle.
4860	* @param pDevIns The device instance.
4861	*/
4862	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4863
4864	/**
4865	* The the VM CPU ID of the current thread (restricted API).
4866	*
4867	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4868	* @param pDevIns The device instance.
4869	*/
4870	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4871
4872	/**
4873	* Get the current virtual clock time in a VM. The clock frequency must be
4874	* queried separately.
4875	*
4876	* @returns Current clock time.
4877	* @param pDevIns The device instance.
4878	*/
4879	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4880
4881	/**
4882	* Get the frequency of the virtual clock.
4883	*
4884	* @returns The clock frequency (not variable at run-time).
4885	* @param pDevIns The device instance.
4886	*/
4887	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4888
4889	/**
4890	* Get the current virtual clock time in a VM, in nanoseconds.
4891	*
4892	* @returns Current clock time (in ns).
4893	* @param pDevIns The device instance.
4894	*/
4895	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4896
4897	/**
4898	* Gets the NOP critical section.
4899	*
4900	* @returns The ring-3 address of the NOP critical section.
4901	* @param pDevIns The device instance.
4902	*/
4903	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4904
4905	/**
4906	* Changes the device level critical section from the automatically created
4907	* default to one desired by the device constructor.
4908	*
4909	* Must first be done in ring-3.
4910	*
4911	* @returns VBox status code.
4912	* @param pDevIns The device instance.
4913	* @param pCritSect The critical section to use. NULL is not
4914	* valid, instead use the NOP critical
4915	* section.
4916	*/
4917	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4918
4919	/** @name Exported PDM Critical Section Functions
4920	* @{ */
4921	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4922	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4923	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4924	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4925	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4926	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4927	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4928	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4929	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4930	/** @} */
4931
4932	/**
4933	* Gets the trace buffer handle.
4934	*
4935	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4936	* really inteded for direct usage, thus no inline wrapper function.
4937	*
4938	* @returns Trace buffer handle or NIL_RTTRACEBUF.
4939	* @param pDevIns The device instance.
4940	*/
4941	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4942
4943	/**
4944	* Sets up the PCI bus for the raw-mode context.
4945	*
4946	* This must be called after ring-3 has registered the PCI bus using
4947	* PDMDevHlpPCIBusRegister().
4948	*
4949	* @returns VBox status code.
4950	* @param pDevIns The device instance.
4951	* @param pPciBusReg The PCI bus registration information for raw-mode,
4952	* considered volatile.
4953	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4954	*/
4955	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4956
4957	/** Space reserved for future members.
4958	* @{ */
4959	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
4960	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
4961	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
4962	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
4963	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
4964	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
4965	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
4966	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
4967	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
4968	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
4969	/** @} */
4970
4971	/** Just a safety precaution. */
4972	uint32_t u32TheEnd;
4973	} PDMDEVHLPRC;
4974	/** Pointer PDM Device RC API. */
4975	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
4976	/** Pointer PDM Device RC API. */
4977	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
4978
4979	/** Current PDMDEVHLP version number. */
4980	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 10, 0)
4981
4982
4983	/**
4984	* PDM Device API - R0 Variant.
4985	*/
4986	typedef struct PDMDEVHLPR0
4987	{
4988	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
4989	uint32_t u32Version;
4990
4991	/**
4992	* Sets up ring-0 callback handlers for an I/O port range.
4993	*
4994	* The range must have been created in ring-3 first using
4995	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4996	*
4997	* @returns VBox status.
4998	* @param pDevIns The device instance to register the ports with.
4999	* @param hIoPorts The I/O port range handle.
5000	* @param pfnOut Pointer to function which is gonna handle OUT
5001	* operations. Optional.
5002	* @param pfnIn Pointer to function which is gonna handle IN operations.
5003	* Optional.
5004	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5005	* operations. Optional.
5006	* @param pfnInStr Pointer to function which is gonna handle string IN
5007	* operations. Optional.
5008	* @param pvUser User argument to pass to the callbacks.
5009	*
5010	* @remarks Caller enters the device critical section prior to invoking the
5011	* registered callback methods.
5012	*
5013	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5014	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5015	*/
5016	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5017	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5018	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5019	void *pvUser));
5020
5021	/**
5022	* Sets up ring-0 callback handlers for an MMIO region.
5023	*
5024	* The region must have been created in ring-3 first using
5025	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5026	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5027	*
5028	* @returns VBox status.
5029	* @param pDevIns The device instance to register the ports with.
5030	* @param hRegion The MMIO region handle.
5031	* @param pfnWrite Pointer to function which is gonna handle Write
5032	* operations.
5033	* @param pfnRead Pointer to function which is gonna handle Read
5034	* operations.
5035	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5036	* operations. (optional)
5037	* @param pvUser User argument to pass to the callbacks.
5038	*
5039	* @remarks Caller enters the device critical section prior to invoking the
5040	* registered callback methods.
5041	*
5042	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5043	* PDMDevHlpMmioUnmap().
5044	*/
5045	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5046	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5047
5048	/**
5049	* Sets up a ring-0 mapping for an MMIO2 region.
5050	*
5051	* The region must have been created in ring-3 first using
5052	* PDMDevHlpMmio2Create().
5053	*
5054	* @returns VBox status.
5055	* @param pDevIns The device instance to register the ports with.
5056	* @param hRegion The MMIO2 region handle.
5057	* @param offSub Start of what to map into ring-0. Must be page aligned.
5058	* @param cbSub Number of bytes to map into ring-0. Must be page
5059	* aligned. Zero is an alias for everything.
5060	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5061	*
5062	* @thread EMT(0)
5063	* @note Only available at VM creation time.
5064	*
5065	* @sa PDMDevHlpMmio2Create().
5066	*/
5067	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5068	void **ppvMapping));
5069
5070	/**
5071	* Bus master physical memory read from the given PCI device.
5072	*
5073	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5074	* VERR_EM_MEMORY.
5075	* @param pDevIns The device instance.
5076	* @param pPciDev The PCI device structure. If NULL the default
5077	* PCI device for this device instance is used.
5078	* @param GCPhys Physical address start reading from.
5079	* @param pvBuf Where to put the read bits.
5080	* @param cbRead How many bytes to read.
5081	* @thread Any thread, but the call may involve the emulation thread.
5082	*/
5083	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5084	void *pvBuf, size_t cbRead));
5085
5086	/**
5087	* Bus master physical memory write from the given PCI device.
5088	*
5089	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5090	* VERR_EM_MEMORY.
5091	* @param pDevIns The device instance.
5092	* @param pPciDev The PCI device structure. If NULL the default
5093	* PCI device for this device instance is used.
5094	* @param GCPhys Physical address to write to.
5095	* @param pvBuf What to write.
5096	* @param cbWrite How many bytes to write.
5097	* @thread Any thread, but the call may involve the emulation thread.
5098	*/
5099	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5100	const void *pvBuf, size_t cbWrite));
5101
5102	/**
5103	* Set the IRQ for the given PCI device.
5104	*
5105	* @param pDevIns Device instance.
5106	* @param pPciDev The PCI device structure. If NULL the default
5107	* PCI device for this device instance is used.
5108	* @param iIrq IRQ number to set.
5109	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5110	* @thread Any thread, but will involve the emulation thread.
5111	*/
5112	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5113
5114	/**
5115	* Set ISA IRQ for a device.
5116	*
5117	* @param pDevIns Device instance.
5118	* @param iIrq IRQ number to set.
5119	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5120	* @thread Any thread, but will involve the emulation thread.
5121	*/
5122	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5123
5124	/**
5125	* Send an MSI straight to the I/O APIC.
5126	*
5127	* @param pDevIns PCI device instance.
5128	* @param GCPhys Physical address MSI request was written.
5129	* @param uValue Value written.
5130	* @thread Any thread, but will involve the emulation thread.
5131	*/
5132	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
5133
5134	/**
5135	* Read physical memory.
5136	*
5137	* @returns VINF_SUCCESS (for now).
5138	* @param pDevIns Device instance.
5139	* @param GCPhys Physical address start reading from.
5140	* @param pvBuf Where to put the read bits.
5141	* @param cbRead How many bytes to read.
5142	*/
5143	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
5144
5145	/**
5146	* Write to physical memory.
5147	*
5148	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5149	* @param pDevIns Device instance.
5150	* @param GCPhys Physical address to write to.
5151	* @param pvBuf What to write.
5152	* @param cbWrite How many bytes to write.
5153	*/
5154	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
5155
5156	/**
5157	* Checks if the Gate A20 is enabled or not.
5158	*
5159	* @returns true if A20 is enabled.
5160	* @returns false if A20 is disabled.
5161	* @param pDevIns Device instance.
5162	* @thread The emulation thread.
5163	*/
5164	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5165
5166	/**
5167	* Gets the VM state.
5168	*
5169	* @returns VM state.
5170	* @param pDevIns The device instance.
5171	* @thread Any thread (just keep in mind that it's volatile info).
5172	*/
5173	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5174
5175	/**
5176	* Set the VM error message
5177	*
5178	* @returns rc.
5179	* @param pDevIns Driver instance.
5180	* @param rc VBox status code.
5181	* @param SRC_POS Use RT_SRC_POS.
5182	* @param pszFormat Error message format string.
5183	* @param ... Error message arguments.
5184	*/
5185	DECLR0CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5186	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
5187
5188	/**
5189	* Set the VM error message
5190	*
5191	* @returns rc.
5192	* @param pDevIns Driver instance.
5193	* @param rc VBox status code.
5194	* @param SRC_POS Use RT_SRC_POS.
5195	* @param pszFormat Error message format string.
5196	* @param va Error message arguments.
5197	*/
5198	DECLR0CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5199	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
5200
5201	/**
5202	* Set the VM runtime error message
5203	*
5204	* @returns VBox status code.
5205	* @param pDevIns Device instance.
5206	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5207	* @param pszErrorId Error ID string.
5208	* @param pszFormat Error message format string.
5209	* @param ... Error message arguments.
5210	*/
5211	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5212	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
5213
5214	/**
5215	* Set the VM runtime error message
5216	*
5217	* @returns VBox status code.
5218	* @param pDevIns Device instance.
5219	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5220	* @param pszErrorId Error ID string.
5221	* @param pszFormat Error message format string.
5222	* @param va Error message arguments.
5223	*/
5224	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5225	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
5226
5227	/**
5228	* Gets the VM handle. Restricted API.
5229	*
5230	* @returns VM Handle.
5231	* @param pDevIns Device instance.
5232	*/
5233	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5234
5235	/**
5236	* Gets the VMCPU handle. Restricted API.
5237	*
5238	* @returns VMCPU Handle.
5239	* @param pDevIns The device instance.
5240	*/
5241	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5242
5243	/**
5244	* The the VM CPU ID of the current thread (restricted API).
5245	*
5246	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5247	* @param pDevIns The device instance.
5248	*/
5249	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5250
5251	/**
5252	* Translates a timer handle to a pointer.
5253	*
5254	* @returns The time address.
5255	* @param pDevIns The device instance.
5256	* @param hTimer The timer handle.
5257	*/
5258	DECLR0CALLBACKMEMBER(PTMTIMERR0, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5259
5260	/** @name Timer handle method wrappers
5261	* @{ */
5262	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5263	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5264	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5265	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5266	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5267	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5268	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5269	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5270	DECLR0CALLBACKMEMBER(int, pfnTimerLock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5271	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5272	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5273	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5274	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5275	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5276	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5277	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5278	DECLR0CALLBACKMEMBER(void, pfnTimerUnlock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5279	/** @} */
5280
5281	/**
5282	* Get the current virtual clock time in a VM. The clock frequency must be
5283	* queried separately.
5284	*
5285	* @returns Current clock time.
5286	* @param pDevIns The device instance.
5287	*/
5288	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5289
5290	/**
5291	* Get the frequency of the virtual clock.
5292	*
5293	* @returns The clock frequency (not variable at run-time).
5294	* @param pDevIns The device instance.
5295	*/
5296	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5297
5298	/**
5299	* Get the current virtual clock time in a VM, in nanoseconds.
5300	*
5301	* @returns Current clock time (in ns).
5302	* @param pDevIns The device instance.
5303	*/
5304	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5305
5306	/** @name Exported PDM Queue Functions
5307	* @{ */
5308	DECLR0CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5309	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5310	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5311	DECLR0CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
5312	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5313	/** @} */
5314
5315	/** @name PDM Task
5316	* @{ */
5317	/**
5318	* Triggers the running the given task.
5319	*
5320	* @returns VBox status code.
5321	* @retval VINF_ALREADY_POSTED is the task is already pending.
5322	* @param pDevIns The device instance.
5323	* @param hTask The task to trigger.
5324	* @thread Any thread.
5325	*/
5326	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5327	/** @} */
5328
5329	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5330	* These semaphores can be signalled from ring-0.
5331	* @{ */
5332	/** @sa SUPSemEventSignal */
5333	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5334	/** @sa SUPSemEventWaitNoResume */
5335	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5336	/** @sa SUPSemEventWaitNsAbsIntr */
5337	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5338	/** @sa SUPSemEventWaitNsRelIntr */
5339	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5340	/** @sa SUPSemEventGetResolution */
5341	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5342	/** @} */
5343
5344	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5345	* These semaphores can be signalled from ring-0.
5346	* @{ */
5347	/** @sa SUPSemEventMultiSignal */
5348	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5349	/** @sa SUPSemEventMultiReset */
5350	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5351	/** @sa SUPSemEventMultiWaitNoResume */
5352	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5353	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5354	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5355	/** @sa SUPSemEventMultiWaitNsRelIntr */
5356	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5357	/** @sa SUPSemEventMultiGetResolution */
5358	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5359	/** @} */
5360
5361	/**
5362	* Gets the NOP critical section.
5363	*
5364	* @returns The ring-3 address of the NOP critical section.
5365	* @param pDevIns The device instance.
5366	*/
5367	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5368
5369	/**
5370	* Changes the device level critical section from the automatically created
5371	* default to one desired by the device constructor.
5372	*
5373	* Must first be done in ring-3.
5374	*
5375	* @returns VBox status code.
5376	* @param pDevIns The device instance.
5377	* @param pCritSect The critical section to use. NULL is not
5378	* valid, instead use the NOP critical
5379	* section.
5380	*/
5381	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5382
5383	/** @name Exported PDM Critical Section Functions
5384	* @{ */
5385	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5386	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5387	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5388	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5389	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5390	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5391	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5392	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5393	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5394	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5395	/** @} */
5396
5397	/**
5398	* Gets the trace buffer handle.
5399	*
5400	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5401	* really inteded for direct usage, thus no inline wrapper function.
5402	*
5403	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5404	* @param pDevIns The device instance.
5405	*/
5406	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5407
5408	/**
5409	* Sets up the PCI bus for the ring-0 context.
5410	*
5411	* This must be called after ring-3 has registered the PCI bus using
5412	* PDMDevHlpPCIBusRegister().
5413	*
5414	* @returns VBox status code.
5415	* @param pDevIns The device instance.
5416	* @param pPciBusReg The PCI bus registration information for ring-0,
5417	* considered volatile.
5418	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5419	*/
5420	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5421
5422	/** Space reserved for future members.
5423	* @{ */
5424	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5425	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5426	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5427	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5428	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5429	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5430	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5431	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5432	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5433	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5434	/** @} */
5435
5436	/** Just a safety precaution. */
5437	uint32_t u32TheEnd;
5438	} PDMDEVHLPR0;
5439	/** Pointer PDM Device R0 API. */
5440	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5441	/** Pointer PDM Device GC API. */
5442	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5443
5444	/** Current PDMDEVHLP version number. */
5445	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 11, 0)
5446
5447
5448	/**
5449	* PDM Device Instance.
5450	*/
5451	typedef struct PDMDEVINSR3
5452	{
5453	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5454	uint32_t u32Version;
5455	/** Device instance number. */
5456	uint32_t iInstance;
5457	/** Size of the ring-3, raw-mode and shared bits. */
5458	uint32_t cbRing3;
5459	/** Set if ring-0 context is enabled. */
5460	bool fR0Enabled;
5461	/** Set if raw-mode context is enabled. */
5462	bool fRCEnabled;
5463	/** Alignment padding. */
5464	bool afReserved[2];
5465	/** Pointer the HC PDM Device API. */
5466	PCPDMDEVHLPR3 pHlpR3;
5467	/** Pointer to the shared device instance data. */
5468	RTR3PTR pvInstanceDataR3;
5469	/** Pointer to the device instance data for ring-3. */
5470	RTR3PTR pvInstanceDataForR3;
5471	/** The critical section for the device.
5472	*
5473	* TM and IOM will enter this critical section before calling into the device
5474	* code. PDM will when doing power on, power off, reset, suspend and resume
5475	* notifications. SSM will currently not, but this will be changed later on.
5476	*
5477	* The device gets a critical section automatically assigned to it before
5478	* the constructor is called. If the constructor wishes to use a different
5479	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5480	* very early on.
5481	*/
5482	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5483	/** Pointer to device registration structure. */
5484	R3PTRTYPE(PCPDMDEVREG) pReg;
5485	/** Configuration handle. */
5486	R3PTRTYPE(PCFGMNODE) pCfg;
5487	/** The base interface of the device.
5488	*
5489	* The device constructor initializes this if it has any
5490	* device level interfaces to export. To obtain this interface
5491	* call PDMR3QueryDevice(). */
5492	PDMIBASE IBase;
5493
5494	/** Tracing indicator. */
5495	uint32_t fTracing;
5496	/** The tracing ID of this device. */
5497	uint32_t idTracing;
5498
5499	/** Ring-3 pointer to the raw-mode device instance. */
5500	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5501	/** Raw-mode address of the raw-mode device instance. */
5502	RTRGPTR pDevInsForRC;
5503	/** Ring-3 pointer to the raw-mode instance data. */
5504	RTR3PTR pvInstanceDataForRCR3;
5505
5506	/** PCI device structure size. */
5507	uint32_t cbPciDev;
5508	/** Number of PCI devices in apPciDevs. */
5509	uint32_t cPciDevs;
5510	/** Pointer to the PCI devices for this device.
5511	* (Allocated after the shared instance data.)
5512	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5513	* two devices ever needing it can use cbPciDev and do the address
5514	* calculations that for entries 8+. */
5515	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5516
5517	/** Temporarily. */
5518	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5519	/** Temporarily. */
5520	RTR0PTR pvInstanceDataR0;
5521	/** Temporarily. */
5522	RTRCPTR pvInstanceDataRC;
5523	/** Align the internal data more naturally. */
5524	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5525
5526	/** Internal data. */
5527	union
5528	{
5529	#ifdef PDMDEVINSINT_DECLARED
5530	PDMDEVINSINTR3 s;
5531	#endif
5532	uint8_t padding[HC_ARCH_BITS == 32 ? 0x30 : 0x50];
5533	} Internal;
5534
5535	/** Device instance data for ring-3. The size of this area is defined
5536	* in the PDMDEVREG::cbInstanceR3 field. */
5537	char achInstanceData[8];
5538	} PDMDEVINSR3;
5539
5540	/** Current PDMDEVINSR3 version number. */
5541	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5542
5543	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5544	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5545
5546
5547	/**
5548	* PDM ring-0 device instance.
5549	*/
5550	typedef struct PDMDEVINSR0
5551	{
5552	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5553	uint32_t u32Version;
5554	/** Device instance number. */
5555	uint32_t iInstance;
5556
5557	/** Pointer the HC PDM Device API. */
5558	PCPDMDEVHLPR0 pHlpR0;
5559	/** Pointer to the shared device instance data. */
5560	RTR0PTR pvInstanceDataR0;
5561	/** Pointer to the device instance data for ring-0. */
5562	RTR0PTR pvInstanceDataForR0;
5563	/** The critical section for the device.
5564	*
5565	* TM and IOM will enter this critical section before calling into the device
5566	* code. PDM will when doing power on, power off, reset, suspend and resume
5567	* notifications. SSM will currently not, but this will be changed later on.
5568	*
5569	* The device gets a critical section automatically assigned to it before
5570	* the constructor is called. If the constructor wishes to use a different
5571	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5572	* very early on.
5573	*/
5574	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5575	/** Pointer to the ring-0 device registration structure. */
5576	R0PTRTYPE(PCPDMDEVREGR0) pReg;
5577	/** Ring-3 address of the ring-3 device instance. */
5578	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5579	/** Ring-0 pointer to the ring-3 device instance. */
5580	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5581	/** Ring-0 pointer to the ring-3 instance data. */
5582	RTR0PTR pvInstanceDataForR3R0;
5583	/** Raw-mode address of the raw-mode device instance. */
5584	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5585	/** Ring-0 pointer to the raw-mode device instance. */
5586	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5587	/** Ring-0 pointer to the raw-mode instance data. */
5588	RTR0PTR pvInstanceDataForRCR0;
5589
5590	/** PCI device structure size. */
5591	uint32_t cbPciDev;
5592	/** Number of PCI devices in apPciDevs. */
5593	uint32_t cPciDevs;
5594	/** Pointer to the PCI devices for this device.
5595	* (Allocated after the shared instance data.)
5596	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5597	* two devices ever needing it can use cbPciDev and do the address
5598	* calculations that for entries 8+. */
5599	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5600
5601	/** Align the internal data more naturally. */
5602	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5603
5604	/** Internal data. */
5605	union
5606	{
5607	#ifdef PDMDEVINSINT_DECLARED
5608	PDMDEVINSINTR0 s;
5609	#endif
5610	uint8_t padding[HC_ARCH_BITS == 32 ? 0x20 : 0x40];
5611	} Internal;
5612
5613	/** Device instance data for ring-0. The size of this area is defined
5614	* in the PDMDEVREG::cbInstanceR0 field. */
5615	char achInstanceData[8];
5616	} PDMDEVINSR0;
5617
5618	/** Current PDMDEVINSR0 version number. */
5619	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5620
5621
5622	/**
5623	* PDM raw-mode device instance.
5624	*/
5625	typedef struct PDMDEVINSRC
5626	{
5627	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5628	uint32_t u32Version;
5629	/** Device instance number. */
5630	uint32_t iInstance;
5631
5632	/** Pointer the HC PDM Device API. */
5633	PCPDMDEVHLPRC pHlpRC;
5634	/** Pointer to the shared device instance data. */
5635	RTRGPTR pvInstanceDataRC;
5636	/** Pointer to the device instance data for raw-mode. */
5637	RTRGPTR pvInstanceDataForRC;
5638	/** The critical section for the device.
5639	*
5640	* TM and IOM will enter this critical section before calling into the device
5641	* code. PDM will when doing power on, power off, reset, suspend and resume
5642	* notifications. SSM will currently not, but this will be changed later on.
5643	*
5644	* The device gets a critical section automatically assigned to it before
5645	* the constructor is called. If the constructor wishes to use a different
5646	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5647	* very early on.
5648	*/
5649	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5650	/** Pointer to the raw-mode device registration structure. */
5651	RGPTRTYPE(PCPDMDEVREGRC) pReg;
5652
5653	/** PCI device structure size. */
5654	uint32_t cbPciDev;
5655	/** Number of PCI devices in apPciDevs. */
5656	uint32_t cPciDevs;
5657	/** Pointer to the PCI devices for this device.
5658	* (Allocated after the shared instance data.) */
5659	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5660
5661	/** Align the internal data more naturally. */
5662	uint32_t au32Padding[14];
5663
5664	/** Internal data. */
5665	union
5666	{
5667	#ifdef PDMDEVINSINT_DECLARED
5668	PDMDEVINSINTRC s;
5669	#endif
5670	uint8_t padding[0x10];
5671	} Internal;
5672
5673	/** Device instance data for ring-0. The size of this area is defined
5674	* in the PDMDEVREG::cbInstanceR0 field. */
5675	char achInstanceData[8];
5676	} PDMDEVINSRC;
5677
5678	/** Current PDMDEVINSR0 version number. */
5679	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5680
5681
5682	/** @def PDM_DEVINS_VERSION
5683	* Current PDMDEVINS version number. */
5684	/** @typedef PDMDEVINS
5685	* The device instance structure for the current context. */
5686	#ifdef IN_RING3
5687	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5688	typedef PDMDEVINSR3 PDMDEVINS;
5689	#elif defined(IN_RING0)
5690	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5691	typedef PDMDEVINSR0 PDMDEVINS;
5692	#elif defined(IN_RC)
5693	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5694	typedef PDMDEVINSRC PDMDEVINS;
5695	#else
5696	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5697	#endif
5698
5699	/**
5700	* Get the pointer to an PCI device.
5701	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5702	*/
5703	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5704	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5705	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5706
5707	/**
5708	* Calc the pointer to of a given PCI device.
5709	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5710	*/
5711	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5712	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5713	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
5714	: (PPDMPCIDEV)NULL )
5715
5716
5717	/**
5718	* Checks the structure versions of the device instance and device helpers,
5719	* returning if they are incompatible.
5720	*
5721	* This is for use in the constructor.
5722	*
5723	* @param pDevIns The device instance pointer.
5724	*/
5725	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5726	do \
5727	{ \
5728	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5729	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5730	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5731	VERR_PDM_DEVINS_VERSION_MISMATCH); \
5732	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5733	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5734	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5735	} while (0)
5736
5737	/**
5738	* Quietly checks the structure versions of the device instance and device
5739	* helpers, returning if they are incompatible.
5740	*
5741	* This is for use in the destructor.
5742	*
5743	* @param pDevIns The device instance pointer.
5744	*/
5745	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5746	do \
5747	{ \
5748	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5749	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5750	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5751	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5752	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5753	} while (0)
5754
5755	/**
5756	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
5757	* constructor - returns on failure.
5758	*
5759	* This should be invoked after having initialized the instance data
5760	* sufficiently for the correct operation of the destructor. The destructor is
5761	* always called!
5762	*
5763	* @param pDevIns Pointer to the PDM device instance.
5764	* @param pszValidValues Patterns describing the valid value names. See
5765	* RTStrSimplePatternMultiMatch for details on the
5766	* pattern syntax.
5767	* @param pszValidNodes Patterns describing the valid node (key) names.
5768	* Pass empty string if no valid nodes.
5769	*/
5770	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5771	do \
5772	{ \
5773	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5774	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5775	if (RT_SUCCESS(rcValCfg)) \
5776	{ /* likely */ } else return rcValCfg; \
5777	} while (0)
5778
5779	/** @def PDMDEV_ASSERT_EMT
5780	* Assert that the current thread is the emulation thread.
5781	*/
5782	#ifdef VBOX_STRICT
5783	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5784	#else
5785	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5786	#endif
5787
5788	/** @def PDMDEV_ASSERT_OTHER
5789	* Assert that the current thread is NOT the emulation thread.
5790	*/
5791	#ifdef VBOX_STRICT
5792	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5793	#else
5794	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5795	#endif
5796
5797	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5798	* Assert that the current thread is owner of the VM lock.
5799	*/
5800	#ifdef VBOX_STRICT
5801	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5802	#else
5803	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5804	#endif
5805
5806	/** @def PDMDEV_SET_ERROR
5807	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5808	*/
5809	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5810	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5811
5812	/** @def PDMDEV_SET_RUNTIME_ERROR
5813	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5814	*/
5815	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5816	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5817
5818	/** @def PDMDEVINS_2_RCPTR
5819	* Converts a PDM Device instance pointer a RC PDM Device instance pointer.
5820	*/
5821	#ifdef IN_RC
5822	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5823	#else
5824	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5825	#endif
5826
5827	/** @def PDMDEVINS_2_R3PTR
5828	* Converts a PDM Device instance pointer a R3 PDM Device instance pointer.
5829	*/
5830	#ifdef IN_RING3
5831	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5832	#else
5833	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5834	#endif
5835
5836	/** @def PDMDEVINS_2_R0PTR
5837	* Converts a PDM Device instance pointer a R0 PDM Device instance pointer.
5838	*/
5839	#ifdef IN_RING0
5840	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5841	#else
5842	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5843	#endif
5844
5845	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5846	* Converts a PDM device instance data pointer to a ring-0 one.
5847	* @deprecated
5848	*/
5849	#ifdef IN_RING0
5850	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5851	#else
5852	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5853	#endif
5854
5855
5856	/** @def PDMDEVINS_2_DATA
5857	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
5858	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5859	*
5860	* @note Do no use this macro in common code working on a core structure which
5861	* device specific code has expanded.
5862	*/
5863	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5864	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5865	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5866	{ \
5867	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5868	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5869	return pLambdaRet; \
5870	}(a_pDevIns))
5871	#else
5872	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5873	#endif
5874
5875	/** @def PDMDEVINS_2_DATA_CC
5876	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5877	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5878	*
5879	* @note Do no use this macro in common code working on a core structure which
5880	* device specific code has expanded.
5881	*/
5882	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5883	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5884	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5885	{ \
5886	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5887	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5888	return pLambdaRet; \
5889	}(a_pDevIns))
5890	#else
5891	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5892	#endif
5893
5894
5895	#ifdef IN_RING3
5896
5897	/**
5898	* @copydoc PDMDEVHLPR3::pfnIOPortRegister
5899	*/
5900	DECLINLINE(int) PDMDevHlpIOPortRegister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTHCPTR pvUser,
5901	PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
5902	PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc)
5903	{
5904	return pDevIns->pHlpR3->pfnIOPortRegister(pDevIns, Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc);
5905	}
5906
5907	/**
5908	* @copydoc PDMDEVHLPR3::pfnIOPortRegisterRC
5909	*/
5910	DECLINLINE(int) PDMDevHlpIOPortRegisterRC(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTRCPTR pvUser,
5911	const char pszOut, const char pszIn, const char *pszOutStr,
5912	const char pszInStr, const char pszDesc)
5913	{
5914	return pDevIns->pHlpR3->pfnIOPortRegisterRC(pDevIns, Port, cPorts, pvUser, pszOut, pszIn, pszOutStr, pszInStr, pszDesc);
5915	}
5916
5917	/**
5918	* @copydoc PDMDEVHLPR3::pfnIOPortRegisterR0
5919	*/
5920	DECLINLINE(int) PDMDevHlpIOPortRegisterR0(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTR0PTR pvUser,
5921	const char pszOut, const char pszIn, const char *pszOutStr,
5922	const char pszInStr, const char pszDesc)
5923	{
5924	return pDevIns->pHlpR3->pfnIOPortRegisterR0(pDevIns, Port, cPorts, pvUser, pszOut, pszIn, pszOutStr, pszInStr, pszDesc);
5925	}
5926
5927	/**
5928	* @copydoc PDMDEVHLPR3::pfnIOPortDeregister
5929	*/
5930	DECLINLINE(int) PDMDevHlpIOPortDeregister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts)
5931	{
5932	return pDevIns->pHlpR3->pfnIOPortDeregister(pDevIns, Port, cPorts);
5933	}
5934
5935	/**
5936	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
5937	*/
5938	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5939	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
5940	PIOMIOPORTHANDLE phIoPorts)
5941	{
5942	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5943	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5944	if (RT_SUCCESS(rc))
5945	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5946	return rc;
5947	}
5948
5949	/**
5950	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
5951	*/
5952	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts,
5953	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5954	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5955	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5956	{
5957	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5958	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5959	if (RT_SUCCESS(rc))
5960	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5961	return rc;
5962	}
5963
5964	/**
5965	* @sa PDMDevHlpIoPortCreateEx
5966	*/
5967	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5968	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
5969	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5970	{
5971	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
5972	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5973	}
5974
5975	/**
5976	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
5977	*/
5978	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
5979	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5980	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5981	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5982	{
5983	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
5984	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5985	}
5986
5987	/**
5988	* @copydoc PDMDEVHLPR3::pfnIoPortMap
5989	*/
5990	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
5991	{
5992	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
5993	}
5994
5995	/**
5996	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
5997	*/
5998	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5999	{
6000	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6001	}
6002
6003	/**
6004	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6005	*/
6006	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6007	{
6008	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6009	}
6010
6011
6012	#endif /* IN_RING3 */
6013	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6014
6015	/**
6016	* @sa PDMDevHlpIoPortSetUpContextEx
6017	*/
6018	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6019	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6020	{
6021	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6022	}
6023
6024	/**
6025	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6026	*/
6027	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6028	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6029	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6030	{
6031	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6032	}
6033
6034	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6035	#ifdef IN_RING3
6036
6037	/**
6038	* @sa PDMDevHlpMmioCreateEx
6039	*/
6040	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6041	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6042	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6043	{
6044	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6045	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6046	}
6047
6048	/**
6049	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6050	*/
6051	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6052	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6053	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6054	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6055	{
6056	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6057	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6058	}
6059
6060	/**
6061	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6062	*/
6063	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6064	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6065	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6066	{
6067	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6068	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6069	if (RT_SUCCESS(rc))
6070	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6071	return rc;
6072	}
6073
6074	/**
6075	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6076	*/
6077	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6078	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6079	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6080	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6081	{
6082	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6083	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6084	if (RT_SUCCESS(rc))
6085	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6086	return rc;
6087	}
6088
6089	/**
6090	* @copydoc PDMDEVHLPR3::pfnMmioMap
6091	*/
6092	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6093	{
6094	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6095	}
6096
6097	/**
6098	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6099	*/
6100	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6101	{
6102	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6103	}
6104
6105	/**
6106	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6107	*/
6108	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6109	{
6110	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6111	}
6112
6113	/**
6114	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6115	*/
6116	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6117	{
6118	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6119	}
6120
6121	#endif /* IN_RING3 */
6122	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6123
6124	/**
6125	* @sa PDMDevHlpMmioSetUpContextEx
6126	*/
6127	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6128	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6129	{
6130	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6131	}
6132
6133	/**
6134	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6135	*/
6136	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6137	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6138	{
6139	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6140	}
6141
6142	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6143	#ifdef IN_RING3
6144
6145	/**
6146	* Register a Memory Mapped I/O (MMIO) region.
6147	*
6148	* These callbacks are of course for the ring-3 context (R3). Register HC
6149	* handlers before raw-mode context (RC) and ring-0 context (R0) handlers! There
6150	* must be a R3 handler for every RC and R0 handler!
6151	*
6152	* @returns VBox status.
6153	* @param pDevIns The device instance to register the MMIO with.
6154	* @param GCPhysStart First physical address in the range.
6155	* @param cbRange The size of the range (in bytes).
6156	* @param pvUser User argument.
6157	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
6158	* @param pfnWrite Pointer to function which is gonna handle Write operations.
6159	* @param pfnRead Pointer to function which is gonna handle Read operations.
6160	* @param pszDesc Pointer to description string. This must not be freed.
6161	*/
6162	DECLINLINE(int) PDMDevHlpMMIORegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
6163	uint32_t fFlags, PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, const char *pszDesc)
6164	{
6165	return pDevIns->pHlpR3->pfnMMIORegister(pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, NULL /pfnFill/,
6166	fFlags, pszDesc);
6167	}
6168
6169	/**
6170	* Register a Memory Mapped I/O (MMIO) region for RC.
6171	*
6172	* These callbacks are for the raw-mode context (RC). Register ring-3 context
6173	* (R3) handlers before guest context handlers! There must be a R3 handler for
6174	* every RC handler!
6175	*
6176	* @returns VBox status.
6177	* @param pDevIns The device instance to register the MMIO with.
6178	* @param GCPhysStart First physical address in the range.
6179	* @param cbRange The size of the range (in bytes).
6180	* @param pvUser User argument.
6181	* @param pszWrite Name of the RC function which is gonna handle Write operations.
6182	* @param pszRead Name of the RC function which is gonna handle Read operations.
6183	*/
6184	DECLINLINE(int) PDMDevHlpMMIORegisterRC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
6185	const char pszWrite, const char pszRead)
6186	{
6187	return pDevIns->pHlpR3->pfnMMIORegisterRC(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, NULL /pszFill/);
6188	}
6189
6190	/**
6191	* Register a Memory Mapped I/O (MMIO) region for R0.
6192	*
6193	* These callbacks are for the ring-0 host context (R0). Register ring-3
6194	* constext (R3) handlers before R0 handlers! There must be a R3 handler for
6195	* every R0 handler!
6196	*
6197	* @returns VBox status.
6198	* @param pDevIns The device instance to register the MMIO with.
6199	* @param GCPhysStart First physical address in the range.
6200	* @param cbRange The size of the range (in bytes).
6201	* @param pvUser User argument. (if pointer, then it must be in locked memory!)
6202	* @param pszWrite Name of the RC function which is gonna handle Write operations.
6203	* @param pszRead Name of the RC function which is gonna handle Read operations.
6204	* @remarks Caller enters the device critical section prior to invoking the
6205	* registered callback methods.
6206	*/
6207	DECLINLINE(int) PDMDevHlpMMIORegisterR0(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
6208	const char pszWrite, const char pszRead)
6209	{
6210	return pDevIns->pHlpR3->pfnMMIORegisterR0(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, NULL /pszFill/);
6211	}
6212
6213	/**
6214	* @copydoc PDMDEVHLPR3::pfnMMIORegister
6215	*/
6216	DECLINLINE(int) PDMDevHlpMMIORegisterEx(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
6217	uint32_t fFlags, PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead,
6218	PFNIOMMMIOFILL pfnFill, const char *pszDesc)
6219	{
6220	return pDevIns->pHlpR3->pfnMMIORegister(pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill,
6221	fFlags, pszDesc);
6222	}
6223
6224	/**
6225	* @copydoc PDMDEVHLPR3::pfnMMIORegisterRC
6226	*/
6227	DECLINLINE(int) PDMDevHlpMMIORegisterRCEx(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
6228	const char pszWrite, const char pszRead, const char *pszFill)
6229	{
6230	return pDevIns->pHlpR3->pfnMMIORegisterRC(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, pszFill);
6231	}
6232
6233	/**
6234	* @copydoc PDMDEVHLPR3::pfnMMIORegisterR0
6235	*/
6236	DECLINLINE(int) PDMDevHlpMMIORegisterR0Ex(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
6237	const char pszWrite, const char pszRead, const char *pszFill)
6238	{
6239	return pDevIns->pHlpR3->pfnMMIORegisterR0(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, pszFill);
6240	}
6241
6242	/**
6243	* @copydoc PDMDEVHLPR3::pfnMMIODeregister
6244	*/
6245	DECLINLINE(int) PDMDevHlpMMIODeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange)
6246	{
6247	return pDevIns->pHlpR3->pfnMMIODeregister(pDevIns, GCPhysStart, cbRange);
6248	}
6249
6250	/**
6251	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6252	*/
6253	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6254	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6255	{
6256	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6257	}
6258
6259	/**
6260	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6261	*/
6262	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6263	{
6264	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6265	}
6266
6267	/**
6268	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6269	*/
6270	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6271	{
6272	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6273	}
6274
6275	/**
6276	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6277	*/
6278	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6279	{
6280	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6281	}
6282
6283	/**
6284	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6285	*/
6286	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6287	{
6288	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6289	}
6290
6291	#endif /* IN_RING3 */
6292	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6293
6294	/**
6295	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6296	*/
6297	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6298	size_t offSub, size_t cbSub, void **ppvMapping)
6299	{
6300	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6301	}
6302
6303	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6304	#ifdef IN_RING3
6305
6306	/**
6307	* @copydoc PDMDEVHLPR3::pfnMMIO2Register
6308	*/
6309	DECLINLINE(int) PDMDevHlpMMIO2Register(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cb,
6310	uint32_t fFlags, void *ppv, const char pszDesc)
6311	{
6312	return pDevIns->pHlpR3->pfnMMIO2Register(pDevIns, pPciDev, iRegion, cb, fFlags, ppv, pszDesc);
6313	}
6314
6315	/**
6316	* @copydoc PDMDEVHLPR3::pfnMMIOExDeregister
6317	* @param pPciDev The PCI device the region is associated with, use
6318	* NULL to indicate it is not associated with a device.
6319	*/
6320	DECLINLINE(int) PDMDevHlpMMIOExDeregister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion)
6321	{
6322	return pDevIns->pHlpR3->pfnMMIOExDeregister(pDevIns, pPciDev, iRegion);
6323	}
6324
6325	/**
6326	* @copydoc PDMDEVHLPR3::pfnMMIOExMap
6327	* @param pPciDev The PCI device the region is associated with, use
6328	* NULL to indicate it is not associated with a device.
6329	*/
6330	DECLINLINE(int) PDMDevHlpMMIOExMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
6331	{
6332	return pDevIns->pHlpR3->pfnMMIOExMap(pDevIns, pPciDev, iRegion, GCPhys);
6333	}
6334
6335	/**
6336	* @copydoc PDMDEVHLPR3::pfnMMIOExUnmap
6337	* @param pPciDev The PCI device the region is associated with, use
6338	* NULL to indicate it is not associated with a device.
6339	*/
6340	DECLINLINE(int) PDMDevHlpMMIOExUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
6341	{
6342	return pDevIns->pHlpR3->pfnMMIOExUnmap(pDevIns, pPciDev, iRegion, GCPhys);
6343	}
6344
6345	/**
6346	* @copydoc PDMDEVHLPR3::pfnMMIOExReduce
6347	*/
6348	DECLINLINE(int) PDMDevHlpMMIOExReduce(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion)
6349	{
6350	return pDevIns->pHlpR3->pfnMMIOExReduce(pDevIns, pPciDev, iRegion, cbRegion);
6351	}
6352
6353	#ifdef VBOX_WITH_RAW_MODE_KEEP
6354	/**
6355	* @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2
6356	*/
6357	DECLINLINE(int) PDMDevHlpMMHyperMapMMIO2(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
6358	const char *pszDesc, PRTRCPTR pRCPtr)
6359	{
6360	return pDevIns->pHlpR3->pfnMMHyperMapMMIO2(pDevIns, pPciDev, iRegion, off, cb, pszDesc, pRCPtr);
6361	}
6362	#endif
6363
6364	/**
6365	* @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel
6366	*/
6367	DECLINLINE(int) PDMDevHlpMMIO2MapKernel(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
6368	const char *pszDesc, PRTR0PTR pR0Ptr)
6369	{
6370	return pDevIns->pHlpR3->pfnMMIO2MapKernel(pDevIns, pPciDev, iRegion, off, cb, pszDesc, pR0Ptr);
6371	}
6372
6373	/**
6374	* @copydoc PDMDEVHLPR3::pfnROMRegister
6375	*/
6376	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6377	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6378	{
6379	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6380	}
6381
6382	/**
6383	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6384	*/
6385	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6386	{
6387	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6388	}
6389
6390	/**
6391	* Register a save state data unit.
6392	*
6393	* @returns VBox status.
6394	* @param pDevIns The device instance.
6395	* @param uVersion Data layout version number.
6396	* @param cbGuess The approximate amount of data in the unit.
6397	* Only for progress indicators.
6398	* @param pfnSaveExec Execute save callback, optional.
6399	* @param pfnLoadExec Execute load callback, optional.
6400	*/
6401	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6402	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6403	{
6404	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6405	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6406	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6407	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6408	}
6409
6410	/**
6411	* Register a save state data unit with a live save callback as well.
6412	*
6413	* @returns VBox status.
6414	* @param pDevIns The device instance.
6415	* @param uVersion Data layout version number.
6416	* @param cbGuess The approximate amount of data in the unit.
6417	* Only for progress indicators.
6418	* @param pfnLiveExec Execute live callback, optional.
6419	* @param pfnSaveExec Execute save callback, optional.
6420	* @param pfnLoadExec Execute load callback, optional.
6421	*/
6422	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6423	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6424	{
6425	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6426	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6427	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6428	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6429	}
6430
6431	/**
6432	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6433	*/
6434	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6435	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6436	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6437	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6438	{
6439	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6440	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6441	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6442	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6443	}
6444
6445	/**
6446	* @copydoc PDMDEVHLPR3::pfnTMTimerCreate
6447	*/
6448	DECLINLINE(int) PDMDevHlpTMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6449	uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
6450	{
6451	return pDevIns->pHlpR3->pfnTMTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
6452	}
6453
6454	/**
6455	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6456	*/
6457	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6458	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6459	{
6460	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6461	}
6462
6463	#endif /* IN_RING3 */
6464
6465	/**
6466	* @copydoc PDMDEVHLPR3::pfnTimerToPtr
6467	*/
6468	DECLINLINE(PTMTIMER) PDMDevHlpTimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6469	{
6470	return pDevIns->CTX_SUFF(pHlp)->pfnTimerToPtr(pDevIns, hTimer);
6471	}
6472
6473	/**
6474	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6475	*/
6476	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6477	{
6478	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6479	}
6480
6481	/**
6482	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6483	*/
6484	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6485	{
6486	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6487	}
6488
6489	/**
6490	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6491	*/
6492	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6493	{
6494	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6495	}
6496
6497	/**
6498	* @copydoc PDMDEVHLPR3::pfnTimerGet
6499	*/
6500	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6501	{
6502	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6503	}
6504
6505	/**
6506	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6507	*/
6508	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6509	{
6510	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6511	}
6512
6513	/**
6514	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6515	*/
6516	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6517	{
6518	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6519	}
6520
6521	/**
6522	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6523	*/
6524	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6525	{
6526	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6527	}
6528
6529	/**
6530	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6531	*/
6532	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6533	{
6534	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6535	}
6536
6537	/**
6538	* @copydoc PDMDEVHLPR3::pfnTimerLock
6539	*/
6540	DECLINLINE(int) PDMDevHlpTimerLock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6541	{
6542	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLock(pDevIns, hTimer, rcBusy);
6543	}
6544
6545	/**
6546	* @copydoc PDMDEVHLPR3::pfnTimerSet
6547	*/
6548	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6549	{
6550	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6551	}
6552
6553	/**
6554	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6555	*/
6556	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6557	{
6558	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6559	}
6560
6561	/**
6562	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6563	*/
6564	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6565	{
6566	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6567	}
6568
6569	/**
6570	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6571	*/
6572	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6573	{
6574	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6575	}
6576
6577	/**
6578	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6579	*/
6580	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6581	{
6582	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6583	}
6584
6585	/**
6586	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6587	*/
6588	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6589	{
6590	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6591	}
6592
6593	/**
6594	* @copydoc PDMDEVHLPR3::pfnTimerStop
6595	*/
6596	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6597	{
6598	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6599	}
6600
6601	/**
6602	* @copydoc PDMDEVHLPR3::pfnTimerUnlock
6603	*/
6604	DECLINLINE(void) PDMDevHlpTimerUnlock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6605	{
6606	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlock(pDevIns, hTimer);
6607	}
6608
6609	#ifdef IN_RING3
6610
6611	/**
6612	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6613	*/
6614	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6615	{
6616	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6617	}
6618
6619	/**
6620	* @copydoc PDMDEVHLPR3::pfnTimerSave
6621	*/
6622	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6623	{
6624	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6625	}
6626
6627	/**
6628	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6629	*/
6630	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6631	{
6632	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6633	}
6634
6635	/**
6636	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6637	*/
6638	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6639	{
6640	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6641	}
6642
6643	/**
6644	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6645	*/
6646	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6647	{
6648	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6649	}
6650
6651	#endif
6652
6653	/**
6654	* @copydoc PDMDEVHLPR3::pfnPhysRead
6655	*/
6656	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6657	{
6658	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
6659	}
6660
6661	/**
6662	* @copydoc PDMDEVHLPR3::pfnPhysWrite
6663	*/
6664	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6665	{
6666	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
6667	}
6668
6669	#ifdef IN_RING3
6670
6671	/**
6672	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6673	*/
6674	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6675	{
6676	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6677	}
6678
6679	/**
6680	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6681	*/
6682	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6683	PPGMPAGEMAPLOCK pLock)
6684	{
6685	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6686	}
6687
6688	/**
6689	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6690	*/
6691	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6692	{
6693	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6694	}
6695
6696	/**
6697	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6698	*/
6699	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6700	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6701	{
6702	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6703	}
6704
6705	/**
6706	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6707	*/
6708	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6709	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6710	{
6711	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6712	}
6713
6714	/**
6715	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6716	*/
6717	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6718	{
6719	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6720	}
6721
6722	/**
6723	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6724	*/
6725	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6726	{
6727	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6728	}
6729
6730	/**
6731	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6732	*/
6733	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6734	{
6735	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6736	}
6737
6738	/**
6739	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6740	*/
6741	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6742	{
6743	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6744	}
6745
6746	/**
6747	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6748	*/
6749	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6750	{
6751	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6752	}
6753
6754	/**
6755	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6756	*/
6757	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6758	{
6759	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6760	}
6761
6762	/**
6763	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
6764	*/
6765	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6766	{
6767	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6768	}
6769	#endif /* IN_RING3 */
6770
6771	/**
6772	* @copydoc PDMDEVHLPR3::pfnVMState
6773	*/
6774	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6775	{
6776	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6777	}
6778
6779	#ifdef IN_RING3
6780	/**
6781	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6782	*/
6783	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6784	{
6785	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6786	}
6787	#endif /* IN_RING3 */
6788
6789	/**
6790	* @copydoc PDMDEVHLPR3::pfnVMSetError
6791	*/
6792	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6793	const char *pszFormat, ...)
6794	{
6795	va_list va;
6796	va_start(va, pszFormat);
6797	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6798	va_end(va);
6799	return rc;
6800	}
6801
6802	/**
6803	* @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError
6804	*/
6805	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6806	const char *pszFormat, ...)
6807	{
6808	va_list va;
6809	int rc;
6810	va_start(va, pszFormat);
6811	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6812	va_end(va);
6813	return rc;
6814	}
6815
6816	/**
6817	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6818	*
6819	* @returns VBox status code which must be passed up to the VMM. This will be
6820	* VINF_SUCCESS in non-strict builds.
6821	* @param pDevIns The device instance.
6822	* @param SRC_POS Use RT_SRC_POS.
6823	* @param pszFormat Message. (optional)
6824	* @param ... Message parameters.
6825	*/
6826	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6827	{
6828	#ifdef VBOX_STRICT
6829	# ifdef IN_RING3
6830	int rc;
6831	va_list args;
6832	va_start(args, pszFormat);
6833	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6834	va_end(args);
6835	return rc;
6836	# else
6837	NOREF(pDevIns);
6838	NOREF(pszFile);
6839	NOREF(iLine);
6840	NOREF(pszFunction);
6841	NOREF(pszFormat);
6842	return VINF_EM_DBG_STOP;
6843	# endif
6844	#else
6845	NOREF(pDevIns);
6846	NOREF(pszFile);
6847	NOREF(iLine);
6848	NOREF(pszFunction);
6849	NOREF(pszFormat);
6850	return VINF_SUCCESS;
6851	#endif
6852	}
6853
6854	#ifdef IN_RING3
6855
6856	/**
6857	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6858	*/
6859	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6860	{
6861	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6862	}
6863
6864	/**
6865	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6866	*/
6867	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6868	{
6869	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6870	}
6871
6872	/**
6873	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6874	*/
6875	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6876	{
6877	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6878	}
6879
6880	/**
6881	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
6882	*/
6883	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
6884	{
6885	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6886	}
6887
6888	/**
6889	* Same as pfnSTAMRegister except that the name is specified in a
6890	* RTStrPrintf like fashion.
6891	*
6892	* @returns VBox status.
6893	* @param pDevIns Device instance of the DMA.
6894	* @param pvSample Pointer to the sample.
6895	* @param enmType Sample type. This indicates what pvSample is
6896	* pointing at.
6897	* @param enmVisibility Visibility type specifying whether unused
6898	* statistics should be visible or not.
6899	* @param enmUnit Sample unit.
6900	* @param pszDesc Sample description.
6901	* @param pszName Sample name format string, unix path style. If
6902	* this does not start with a '/', the default
6903	* prefix will be prepended, otherwise it will be
6904	* used as-is.
6905	* @param ... Arguments to the format string.
6906	*/
6907	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6908	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6909	const char pszDesc, const char pszName, ...)
6910	{
6911	va_list va;
6912	va_start(va, pszName);
6913	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6914	va_end(va);
6915	}
6916
6917	/**
6918	* Registers the device with the default PCI bus.
6919	*
6920	* @returns VBox status code.
6921	* @param pDevIns The device instance.
6922	* @param pPciDev The PCI device structure.
6923	* This must be kept in the instance data.
6924	* The PCI configuration must be initialized before registration.
6925	*/
6926	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6927	{
6928	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
6929	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6930	}
6931
6932	/**
6933	* @copydoc PDMDEVHLPR3::pfnPCIRegister
6934	*/
6935	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6936	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6937	{
6938	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6939	}
6940
6941	/**
6942	* Initialize MSI emulation support for the first PCI device.
6943	*
6944	* @returns VBox status code.
6945	* @param pDevIns The device instance.
6946	* @param pMsiReg MSI emulation registration structure.
6947	*/
6948	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6949	{
6950	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6951	}
6952
6953	/**
6954	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6955	*/
6956	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6957	{
6958	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6959	}
6960
6961	/**
6962	* Registers a I/O region (memory mapped or I/O ports) for the default PCI
6963	* device.
6964	*
6965	* @returns VBox status code.
6966	* @param pDevIns The device instance.
6967	* @param iRegion The region number.
6968	* @param cbRegion Size of the region.
6969	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
6970	* @param pfnMapUnmap Callback for doing the mapping.
6971	* @remarks The callback will be invoked holding the PDM lock. The device lock
6972	* is NOT take because that is very likely be a lock order violation.
6973	* @remarks Old callback style, won't get unmap calls.
6974	*/
6975	DECLINLINE(int) PDMDevHlpPCIIORegionRegister(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6976	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnMapUnmap)
6977	{
6978	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6979	PDMPCIDEV_IORGN_F_NO_HANDLE, UINT64_MAX, pfnMapUnmap);
6980	}
6981
6982	/**
6983	* @sa PDMDEVHLPR3::pfnPCIIORegionRegister
6984	* @remarks Old callback style, won't get unmap calls.
6985	*/
6986	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion,
6987	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnMapUnmap)
6988	{
6989	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
6990	PDMPCIDEV_IORGN_F_NO_HANDLE, UINT64_MAX, pfnMapUnmap);
6991	}
6992
6993	/**
6994	* Registers a I/O port region for the default PCI device.
6995	*
6996	* @returns VBox status code.
6997	* @param pDevIns The device instance.
6998	* @param iRegion The region number.
6999	* @param cbRegion Size of the region.
7000	* @param hIoPorts Handle to the I/O port region.
7001	*/
7002	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
7003	{
7004	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7005	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
7006	}
7007
7008	/**
7009	* Registers a I/O port region for the default PCI device, custom map/unmap.
7010	*
7011	* @returns VBox status code.
7012	* @param pDevIns The device instance.
7013	* @param iRegion The region number.
7014	* @param cbRegion Size of the region.
7015	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7016	* callback will be invoked holding only the PDM lock.
7017	* The device lock will _not_ be taken (due to lock
7018	* order).
7019	*/
7020	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7021	PFNPCIIOREGIONMAP pfnMapUnmap)
7022	{
7023	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7024	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7025	UINT64_MAX, pfnMapUnmap);
7026	}
7027
7028	/**
7029	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7030	* and registering an I/O port region for the default PCI device.
7031	*
7032	* @returns VBox status code.
7033	* @param pDevIns The device instance to register the ports with.
7034	* @param cbPorts The size of the region in I/O ports.
7035	* @param iPciRegion The PCI device region.
7036	* @param pfnOut Pointer to function which is gonna handle OUT
7037	* operations. Optional.
7038	* @param pfnIn Pointer to function which is gonna handle IN operations.
7039	* Optional.
7040	* @param pvUser User argument to pass to the callbacks.
7041	* @param pszDesc Pointer to description string. This must not be freed.
7042	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7043	* coverage is allowed. This must not be freed.
7044	* @param phIoPorts Where to return the I/O port range handle.
7045	*
7046	*/
7047	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cbPorts,
7048	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7049	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7050
7051	{
7052	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cbPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7053	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7054	if (RT_SUCCESS(rc))
7055	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbPorts, PCI_ADDRESS_SPACE_IO,
7056	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7057	phIoPorts, NULL /pfnMapUnmap*/);
7058	return rc;
7059	}
7060
7061	/**
7062	* Registers an MMIO region for the default PCI device.
7063	*
7064	* @returns VBox status code.
7065	* @param pDevIns The device instance.
7066	* @param iRegion The region number.
7067	* @param cbRegion Size of the region.
7068	* @param enmType PCI_ADDRESS_SPACE_MEM or
7069	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7070	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7071	* @param hMmioRegion Handle to the MMIO region.
7072	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7073	* callback will be invoked holding only the PDM lock.
7074	* The device lock will _not_ be taken (due to lock
7075	* order).
7076	*/
7077	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7078	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7079	{
7080	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7081	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7082	hMmioRegion, pfnMapUnmap);
7083	}
7084
7085	/**
7086	* Registers an MMIO region for the default PCI device, extended version.
7087	*
7088	* @returns VBox status code.
7089	* @param pDevIns The device instance.
7090	* @param pPciDev The PCI device structure.
7091	* @param iRegion The region number.
7092	* @param cbRegion Size of the region.
7093	* @param enmType PCI_ADDRESS_SPACE_MEM or
7094	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7095	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7096	* @param hMmioRegion Handle to the MMIO region.
7097	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7098	* callback will be invoked holding only the PDM lock.
7099	* The device lock will _not_ be taken (due to lock
7100	* order).
7101	*/
7102	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7103	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7104	PFNPCIIOREGIONMAP pfnMapUnmap)
7105	{
7106	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7107	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7108	hMmioRegion, pfnMapUnmap);
7109	}
7110
7111	/**
7112	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7113	* and registering an MMIO region for the default PCI device.
7114	*
7115	* @returns VBox status code.
7116	* @param pDevIns The device instance to register the ports with.
7117	* @param cbRegion The size of the region in bytes.
7118	* @param iPciRegion The PCI device region.
7119	* @param enmType PCI_ADDRESS_SPACE_MEM or
7120	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7121	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7122	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7123	* @param pfnWrite Pointer to function which is gonna handle Write
7124	* operations.
7125	* @param pfnRead Pointer to function which is gonna handle Read
7126	* operations.
7127	* @param pvUser User argument to pass to the callbacks.
7128	* @param pszDesc Pointer to description string. This must not be freed.
7129	* @param phRegion Where to return the MMIO region handle.
7130	*
7131	*/
7132	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7133	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7134	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7135
7136	{
7137	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7138	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7139	if (RT_SUCCESS(rc))
7140	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7141	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7142	phRegion, NULL /pfnMapUnmap*/);
7143	return rc;
7144	}
7145
7146
7147	/**
7148	* Registers an MMIO2 region for the default PCI device.
7149	*
7150	* @returns VBox status code.
7151	* @param pDevIns The device instance.
7152	* @param iRegion The region number.
7153	* @param cbRegion Size of the region.
7154	* @param enmType PCI_ADDRESS_SPACE_MEM or
7155	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7156	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7157	* @param hMmio2Region Handle to the MMIO2 region.
7158	*/
7159	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7160	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7161	{
7162	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7163	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7164	hMmio2Region, NULL);
7165	}
7166
7167	/**
7168	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7169	* and registering an MMIO2 region for the default PCI device, extended edition.
7170	*
7171	* @returns VBox status code.
7172	* @param pDevIns The device instance to register the ports with.
7173	* @param cbRegion The size of the region in bytes.
7174	* @param iPciRegion The PCI device region.
7175	* @param enmType PCI_ADDRESS_SPACE_MEM or
7176	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7177	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7178	* @param pszDesc Pointer to description string. This must not be freed.
7179	* @param ppvMapping Where to store the address of the ring-3 mapping of
7180	* the memory.
7181	* @param phRegion Where to return the MMIO2 region handle.
7182	*
7183	*/
7184	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7185	PCIADDRESSSPACE enmType, const char *pszDesc,
7186	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7187
7188	{
7189	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7190	pszDesc, ppvMapping, phRegion);
7191	if (RT_SUCCESS(rc))
7192	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7193	PDMPCIDEV_IORGN_F_MMIO2_HANDLE, phRegion, NULL /pfnCallback*/);
7194	return rc;
7195	}
7196
7197	/**
7198	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7199	* and registering an MMIO2 region for the default PCI device.
7200	*
7201	* @returns VBox status code.
7202	* @param pDevIns The device instance to register the ports with.
7203	* @param cbRegion The size of the region in bytes.
7204	* @param iPciRegion The PCI device region.
7205	* @param enmType PCI_ADDRESS_SPACE_MEM or
7206	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7207	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7208	* @param fMmio2Flags To be defined, must be zero.
7209	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7210	* callback will be invoked holding only the PDM lock.
7211	* The device lock will _not_ be taken (due to lock
7212	* order).
7213	* @param pszDesc Pointer to description string. This must not be freed.
7214	* @param ppvMapping Where to store the address of the ring-3 mapping of
7215	* the memory.
7216	* @param phRegion Where to return the MMIO2 region handle.
7217	*
7218	*/
7219	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7220	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7221	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
7222
7223	{
7224	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7225	pszDesc, ppvMapping, phRegion);
7226	if (RT_SUCCESS(rc))
7227	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7228	PDMPCIDEV_IORGN_F_MMIO2_HANDLE, *phRegion, pfnMapUnmap);
7229	return rc;
7230	}
7231
7232	/**
7233	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7234	*/
7235	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7236	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7237	{
7238	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7239	}
7240
7241	/**
7242	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7243	*/
7244	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7245	unsigned cb, uint32_t *pu32Value)
7246	{
7247	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7248	}
7249
7250	/**
7251	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7252	*/
7253	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7254	unsigned cb, uint32_t u32Value)
7255	{
7256	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7257	}
7258
7259	#endif /* IN_RING3 */
7260
7261	/**
7262	* Bus master physical memory read from the default PCI device.
7263	*
7264	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7265	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7266	* @param pDevIns The device instance.
7267	* @param GCPhys Physical address start reading from.
7268	* @param pvBuf Where to put the read bits.
7269	* @param cbRead How many bytes to read.
7270	* @thread Any thread, but the call may involve the emulation thread.
7271	*/
7272	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7273	{
7274	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead);
7275	}
7276
7277	/**
7278	* @copydoc PDMDEVHLPR3::pfnPCIPhysRead
7279	*/
7280	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7281	{
7282	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead);
7283	}
7284
7285	/**
7286	* Bus master physical memory write from the default PCI device.
7287	*
7288	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7289	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7290	* @param pDevIns The device instance.
7291	* @param GCPhys Physical address to write to.
7292	* @param pvBuf What to write.
7293	* @param cbWrite How many bytes to write.
7294	* @thread Any thread, but the call may involve the emulation thread.
7295	*/
7296	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7297	{
7298	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite);
7299	}
7300
7301	/**
7302	* @copydoc PDMDEVHLPR3::pfnPCIPhysWrite
7303	*/
7304	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7305	{
7306	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite);
7307	}
7308
7309	/**
7310	* Sets the IRQ for the default PCI device.
7311	*
7312	* @param pDevIns The device instance.
7313	* @param iIrq IRQ number to set.
7314	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7315	* @thread Any thread, but will involve the emulation thread.
7316	*/
7317	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7318	{
7319	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7320	}
7321
7322	/**
7323	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
7324	*/
7325	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7326	{
7327	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7328	}
7329
7330	/**
7331	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7332	* the request when not called from EMT.
7333	*
7334	* @param pDevIns The device instance.
7335	* @param iIrq IRQ number to set.
7336	* @param iLevel IRQ level.
7337	* @thread Any thread, but will involve the emulation thread.
7338	*/
7339	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7340	{
7341	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7342	}
7343
7344	/**
7345	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7346	*/
7347	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7348	{
7349	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7350	}
7351
7352	/**
7353	* @copydoc PDMDEVHLPR3::pfnISASetIrq
7354	*/
7355	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7356	{
7357	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7358	}
7359
7360	/**
7361	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7362	*/
7363	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7364	{
7365	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7366	}
7367
7368	/**
7369	* @copydoc PDMDEVHLPR3::pfnIoApicSendMsi
7370	*/
7371	DECLINLINE(void) PDMDevHlpIoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue)
7372	{
7373	pDevIns->CTX_SUFF(pHlp)->pfnIoApicSendMsi(pDevIns, GCPhys, uValue);
7374	}
7375
7376	#ifdef IN_RING3
7377
7378	/**
7379	* @copydoc PDMDEVHLPR3::pfnDriverAttach
7380	*/
7381	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
7382	{
7383	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7384	}
7385
7386	/**
7387	* @copydoc PDMDEVHLPR3::pfnDriverDetach
7388	*/
7389	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7390	{
7391	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7392	}
7393
7394	/**
7395	* @copydoc PDMDEVHLPR3::pfnQueueCreatePtr
7396	*/
7397	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7398	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PPDMQUEUE ppQueue)
7399	{
7400	return pDevIns->pHlpR3->pfnQueueCreatePtr(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
7401	}
7402
7403	/**
7404	* @copydoc PDMDEVHLPR3::pfnQueueCreate
7405	*/
7406	DECLINLINE(int) PDMDevHlpQueueCreateNew(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7407	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
7408	{
7409	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7410	}
7411
7412	#endif /* IN_RING3 */
7413
7414	/**
7415	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
7416	*/
7417	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7418	{
7419	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7420	}
7421
7422	/**
7423	* @copydoc PDMDEVHLPR3::pfnQueueInsert
7424	*/
7425	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7426	{
7427	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7428	}
7429
7430	/**
7431	* @copydoc PDMDEVHLPR3::pfnQueueInsertEx
7432	*/
7433	DECLINLINE(void) PDMDevHlpQueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay)
7434	{
7435	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsertEx(pDevIns, hQueue, pItem, cNanoMaxDelay);
7436	}
7437
7438	/**
7439	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7440	*/
7441	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7442	{
7443	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7444	}
7445
7446	#ifdef IN_RING3
7447	/**
7448	* @copydoc PDMDEVHLPR3::pfnTaskCreate
7449	*/
7450	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7451	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
7452	{
7453	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7454	}
7455	#endif
7456
7457	/**
7458	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
7459	*/
7460	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7461	{
7462	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7463	}
7464
7465	#ifdef IN_RING3
7466
7467	/**
7468	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7469	*/
7470	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7471	{
7472	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7473	}
7474
7475	/**
7476	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7477	*/
7478	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7479	{
7480	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7481	}
7482
7483	#endif /* IN_RING3 */
7484
7485	/**
7486	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7487	*/
7488	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7489	{
7490	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7491	}
7492
7493	/**
7494	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7495	*/
7496	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7497	{
7498	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7499	}
7500
7501	/**
7502	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7503	*/
7504	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7505	{
7506	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7507	}
7508
7509	/**
7510	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7511	*/
7512	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7513	{
7514	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7515	}
7516
7517	/**
7518	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7519	*/
7520	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7521	{
7522	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7523	}
7524
7525	#ifdef IN_RING3
7526
7527	/**
7528	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7529	*/
7530	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7531	{
7532	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7533	}
7534
7535	/**
7536	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7537	*/
7538	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7539	{
7540	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7541	}
7542
7543	#endif /* IN_RING3 */
7544
7545	/**
7546	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7547	*/
7548	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7549	{
7550	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7551	}
7552
7553	/**
7554	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7555	*/
7556	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7557	{
7558	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7559	}
7560
7561	/**
7562	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7563	*/
7564	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7565	{
7566	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7567	}
7568
7569	/**
7570	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7571	*/
7572	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7573	{
7574	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7575	}
7576
7577	/**
7578	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7579	*/
7580	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7581	{
7582	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7583	}
7584
7585	/**
7586	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7587	*/
7588	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7589	{
7590	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7591	}
7592
7593	#ifdef IN_RING3
7594
7595	/**
7596	* Initializes a PDM critical section.
7597	*
7598	* The PDM critical sections are derived from the IPRT critical sections, but
7599	* works in RC and R0 as well.
7600	*
7601	* @returns VBox status code.
7602	* @param pDevIns The device instance.
7603	* @param pCritSect Pointer to the critical section.
7604	* @param SRC_POS Use RT_SRC_POS.
7605	* @param pszNameFmt Format string for naming the critical section.
7606	* For statistics and lock validation.
7607	* @param ... Arguments for the format string.
7608	*/
7609	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7610	const char *pszNameFmt, ...)
7611	{
7612	int rc;
7613	va_list va;
7614	va_start(va, pszNameFmt);
7615	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7616	va_end(va);
7617	return rc;
7618	}
7619
7620	#endif /* IN_RING3 */
7621
7622	/**
7623	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7624	*/
7625	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7626	{
7627	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7628	}
7629
7630	#ifdef IN_RING3
7631
7632	/**
7633	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopR0
7634	*/
7635	DECLINLINE(R0PTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopR0(PPDMDEVINS pDevIns)
7636	{
7637	return pDevIns->pHlpR3->pfnCritSectGetNopR0(pDevIns);
7638	}
7639
7640	/**
7641	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopRC
7642	*/
7643	DECLINLINE(RCPTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopRC(PPDMDEVINS pDevIns)
7644	{
7645	return pDevIns->pHlpR3->pfnCritSectGetNopRC(pDevIns);
7646	}
7647
7648	#endif /* IN_RING3 */
7649
7650	/**
7651	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7652	*/
7653	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7654	{
7655	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7656	}
7657
7658	/**
7659	* @copydoc PDMCritSectEnter
7660	* @param pDevIns The device instance.
7661	*/
7662	DECLINLINE(int) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7663	{
7664	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7665	}
7666
7667	/**
7668	* @copydoc PDMCritSectEnterDebug
7669	* @param pDevIns The device instance.
7670	*/
7671	DECLINLINE(int) PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7672	{
7673	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7674	}
7675
7676	/**
7677	* @copydoc PDMCritSectTryEnter
7678	* @param pDevIns The device instance.
7679	*/
7680	DECLINLINE(int) PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7681	{
7682	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7683	}
7684
7685	/**
7686	* @copydoc PDMCritSectTryEnterDebug
7687	* @param pDevIns The device instance.
7688	*/
7689	DECLINLINE(int) PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7690	{
7691	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7692	}
7693
7694	/**
7695	* @copydoc PDMCritSectLeave
7696	* @param pDevIns The device instance.
7697	*/
7698	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7699	{
7700	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7701	}
7702
7703	/**
7704	* @copydoc PDMCritSectIsOwner
7705	* @param pDevIns The device instance.
7706	*/
7707	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7708	{
7709	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7710	}
7711
7712	/**
7713	* @copydoc PDMCritSectIsInitialized
7714	* @param pDevIns The device instance.
7715	*/
7716	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7717	{
7718	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
7719	}
7720
7721	/**
7722	* @copydoc PDMCritSectHasWaiters
7723	* @param pDevIns The device instance.
7724	*/
7725	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7726	{
7727	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
7728	}
7729
7730	/**
7731	* @copydoc PDMCritSectGetRecursion
7732	* @param pDevIns The device instance.
7733	*/
7734	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7735	{
7736	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
7737	}
7738
7739	#if defined(IN_RING3) \|\| defined(IN_RING0)
7740	/**
7741	* @copydoc PDMHCCritSectScheduleExitEvent
7742	* @param pDevIns The device instance.
7743	*/
7744	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
7745	{
7746	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
7747	}
7748	#endif
7749
7750	/* Strict build: Remap the two enter calls to the debug versions. */
7751	#ifdef VBOX_STRICT
7752	# ifdef IPRT_INCLUDED_asm_h
7753	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7754	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7755	# else
7756	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
7757	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
7758	# endif
7759	#endif
7760
7761	#ifdef IN_RING3
7762
7763	/**
7764	* @copydoc PDMR3CritSectDelete
7765	* @param pDevIns The device instance.
7766	*/
7767	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7768	{
7769	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
7770	}
7771
7772	/**
7773	* @copydoc PDMDEVHLPR3::pfnThreadCreate
7774	*/
7775	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
7776	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
7777	{
7778	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
7779	}
7780
7781	/**
7782	* @copydoc PDMR3ThreadDestroy
7783	* @param pDevIns The device instance.
7784	*/
7785	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
7786	{
7787	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
7788	}
7789
7790	/**
7791	* @copydoc PDMR3ThreadIAmSuspending
7792	* @param pDevIns The device instance.
7793	*/
7794	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7795	{
7796	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
7797	}
7798
7799	/**
7800	* @copydoc PDMR3ThreadIAmRunning
7801	* @param pDevIns The device instance.
7802	*/
7803	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7804	{
7805	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
7806	}
7807
7808	/**
7809	* @copydoc PDMR3ThreadSleep
7810	* @param pDevIns The device instance.
7811	*/
7812	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
7813	{
7814	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
7815	}
7816
7817	/**
7818	* @copydoc PDMR3ThreadSuspend
7819	* @param pDevIns The device instance.
7820	*/
7821	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7822	{
7823	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
7824	}
7825
7826	/**
7827	* @copydoc PDMR3ThreadResume
7828	* @param pDevIns The device instance.
7829	*/
7830	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7831	{
7832	return pDevIns->pHlpR3->pfnThreadResume(pThread);
7833	}
7834
7835	/**
7836	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
7837	*/
7838	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
7839	{
7840	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
7841	}
7842
7843	/**
7844	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
7845	*/
7846	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
7847	{
7848	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
7849	}
7850
7851	/**
7852	* @copydoc PDMDEVHLPR3::pfnA20Set
7853	*/
7854	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
7855	{
7856	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
7857	}
7858
7859	/**
7860	* @copydoc PDMDEVHLPR3::pfnRTCRegister
7861	*/
7862	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
7863	{
7864	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
7865	}
7866
7867	/**
7868	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
7869	*/
7870	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
7871	{
7872	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
7873	}
7874
7875	/**
7876	* @copydoc PDMDEVHLPR3::pfnPICRegister
7877	*/
7878	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3)
7879	{
7880	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlpR3);
7881	}
7882
7883	/**
7884	* @copydoc PDMDEVHLPR3::pfnAPICRegister
7885	*/
7886	DECLINLINE(int) PDMDevHlpAPICRegister(PPDMDEVINS pDevIns)
7887	{
7888	return pDevIns->pHlpR3->pfnAPICRegister(pDevIns);
7889	}
7890
7891	/**
7892	* @copydoc PDMDEVHLPR3::pfnIOAPICRegister
7893	*/
7894	DECLINLINE(int) PDMDevHlpIOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3)
7895	{
7896	return pDevIns->pHlpR3->pfnIOAPICRegister(pDevIns, pIoApicReg, ppIoApicHlpR3);
7897	}
7898
7899	/**
7900	* @copydoc PDMDEVHLPR3::pfnHPETRegister
7901	*/
7902	DECLINLINE(int) PDMDevHlpHPETRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
7903	{
7904	return pDevIns->pHlpR3->pfnHPETRegister(pDevIns, pHpetReg, ppHpetHlpR3);
7905	}
7906
7907	/**
7908	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
7909	*/
7910	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
7911	{
7912	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
7913	}
7914
7915	/**
7916	* @copydoc PDMDEVHLPR3::pfnDMACRegister
7917	*/
7918	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
7919	{
7920	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
7921	}
7922
7923	/**
7924	* @copydoc PDMDEVHLPR3::pfnDMARegister
7925	*/
7926	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
7927	{
7928	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
7929	}
7930
7931	/**
7932	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
7933	*/
7934	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
7935	{
7936	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
7937	}
7938
7939	/**
7940	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
7941	*/
7942	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
7943	{
7944	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
7945	}
7946
7947	/**
7948	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
7949	*/
7950	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
7951	{
7952	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
7953	}
7954
7955	/**
7956	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
7957	*/
7958	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
7959	{
7960	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
7961	}
7962
7963	/**
7964	* @copydoc PDMDEVHLPR3::pfnDMASchedule
7965	*/
7966	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
7967	{
7968	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
7969	}
7970
7971	/**
7972	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
7973	*/
7974	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
7975	{
7976	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
7977	}
7978
7979	/**
7980	* @copydoc PDMDEVHLPR3::pfnCMOSRead
7981	*/
7982	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
7983	{
7984	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
7985	}
7986
7987	/**
7988	* @copydoc PDMDEVHLPR3::pfnCallR0
7989	*/
7990	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
7991	{
7992	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
7993	}
7994
7995	/**
7996	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
7997	*/
7998	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
7999	{
8000	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
8001	}
8002
8003	/**
8004	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
8005	*/
8006	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
8007	{
8008	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
8009	}
8010
8011	/**
8012	* @copydoc PDMDEVHLPR3::pfnGetUVM
8013	*/
8014	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
8015	{
8016	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
8017	}
8018
8019	#else /* !IN_RING3 */
8020
8021	/**
8022	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUp
8023	*/
8024	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
8025	{
8026	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
8027	}
8028
8029	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
8030
8031	/**
8032	* @copydoc PDMDEVHLPR3::pfnGetVM
8033	*/
8034	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
8035	{
8036	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
8037	}
8038
8039	/**
8040	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
8041	*/
8042	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
8043	{
8044	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
8045	}
8046
8047	/**
8048	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
8049	*/
8050	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
8051	{
8052	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
8053	}
8054
8055	/**
8056	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
8057	*/
8058	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
8059	{
8060	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
8061	}
8062
8063	/**
8064	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8065	*/
8066	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8067	{
8068	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8069	}
8070
8071	/**
8072	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8073	*/
8074	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8075	{
8076	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8077	}
8078
8079	#ifdef IN_RING3
8080
8081	/**
8082	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8083	*/
8084	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8085	{
8086	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
8087	}
8088
8089	/**
8090	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
8091	*/
8092	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
8093	{
8094	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
8095	}
8096
8097	/**
8098	* @copydoc PDMDEVHLPR3::pfnVMReset
8099	*/
8100	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
8101	{
8102	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
8103	}
8104
8105	/**
8106	* @copydoc PDMDEVHLPR3::pfnVMSuspend
8107	*/
8108	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8109	{
8110	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8111	}
8112
8113	/**
8114	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8115	*/
8116	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8117	{
8118	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8119	}
8120
8121	/**
8122	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
8123	*/
8124	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8125	{
8126	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8127	}
8128
8129	#endif /* IN_RING3 */
8130
8131	/**
8132	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8133	*/
8134	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8135	{
8136	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8137	}
8138
8139	#ifdef IN_RING3
8140
8141	/**
8142	* @copydoc PDMDEVHLPR3::pfnGetCpuId
8143	*/
8144	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
8145	{
8146	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8147	}
8148
8149	/**
8150	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8151	*/
8152	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8153	{
8154	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8155	}
8156
8157	/**
8158	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8159	*/
8160	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8161	{
8162	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8163	}
8164
8165	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
8166	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8167	do { \
8168	uint32_t u32GetEnumTmp = 0; \
8169	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
8170	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8171	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
8172	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
8173	} while (0)
8174
8175	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
8176	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8177	do { \
8178	uint8_t bGetEnumTmp = 0; \
8179	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
8180	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8181	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
8182	} while (0)
8183
8184	#endif /* IN_RING3 */
8185
8186	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
8187	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
8188
8189	/**
8190	* Callbacks for VBoxDeviceRegister().
8191	*/
8192	typedef struct PDMDEVREGCB
8193	{
8194	/** Interface version.
8195	* This is set to PDM_DEVREG_CB_VERSION. */
8196	uint32_t u32Version;
8197
8198	/**
8199	* Registers a device with the current VM instance.
8200	*
8201	* @returns VBox status code.
8202	* @param pCallbacks Pointer to the callback table.
8203	* @param pReg Pointer to the device registration record.
8204	* This data must be permanent and readonly.
8205	*/
8206	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
8207	} PDMDEVREGCB;
8208
8209	/** Current version of the PDMDEVREGCB structure. */
8210	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
8211
8212
8213	/**
8214	* The VBoxDevicesRegister callback function.
8215	*
8216	* PDM will invoke this function after loading a device module and letting
8217	* the module decide which devices to register and how to handle conflicts.
8218	*
8219	* @returns VBox status code.
8220	* @param pCallbacks Pointer to the callback table.
8221	* @param u32Version VBox version number.
8222	*/
8223	typedef DECLCALLBACK(int) FNPDMVBOXDEVICESREGISTER(PPDMDEVREGCB pCallbacks, uint32_t u32Version);
8224
8225	/** @} */
8226
8227	RT_C_DECLS_END
8228
8229	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 81850

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