VirtualBox

source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 82261

Last change on this file since 82261 was 82224, checked in by vboxsync, 5 years ago

PDMDevHlp: Adding PDMDevHlpDriverReconfigure[|1|2] for the audio devices to use when falling back on the 'NullAudio' driver. bugref:9218
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File size: 341.0 KB
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1/** @file
2 * PDM - Pluggable Device Manager, Devices.
3 */
4
5/*
6 * Copyright (C) 2006-2019 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27#define VBOX_INCLUDED_vmm_pdmdev_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmqueue.h>
34#include <VBox/vmm/pdmtask.h>
35#ifdef IN_RING3
36# include <VBox/vmm/pdmthread.h>
37#endif
38#include <VBox/vmm/pdmifs.h>
39#include <VBox/vmm/pdmins.h>
40#include <VBox/vmm/pdmcommon.h>
41#include <VBox/vmm/pdmpcidev.h>
42#include <VBox/vmm/iom.h>
43#include <VBox/vmm/tm.h>
44#include <VBox/vmm/ssm.h>
45#include <VBox/vmm/cfgm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
48#include <iprt/stdarg.h>
49#include <iprt/list.h>
50
51
52RT_C_DECLS_BEGIN
53
54/** @defgroup grp_pdm_device The PDM Devices API
55 * @ingroup grp_pdm
56 * @{
57 */
58
59/**
60 * Construct a device instance for a VM.
61 *
62 * @returns VBox status.
63 * @param pDevIns The device instance data. If the registration structure
64 * is needed, it can be accessed thru pDevIns->pReg.
65 * @param iInstance Instance number. Use this to figure out which registers
66 * and such to use. The instance number is also found in
67 * pDevIns->iInstance, but since it's likely to be
68 * frequently used PDM passes it as parameter.
69 * @param pCfg Configuration node handle for the driver. This is
70 * expected to be in high demand in the constructor and is
71 * therefore passed as an argument. When using it at other
72 * times, it can be found in pDevIns->pCfg.
73 */
74typedef DECLCALLBACK(int) FNPDMDEVCONSTRUCT(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg);
75/** Pointer to a FNPDMDEVCONSTRUCT() function. */
76typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
77
78/**
79 * Destruct a device instance.
80 *
81 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
82 * resources can be freed correctly.
83 *
84 * @returns VBox status.
85 * @param pDevIns The device instance data.
86 *
87 * @remarks The device critical section is not entered. The routine may delete
88 * the critical section, so the caller cannot exit it.
89 */
90typedef DECLCALLBACK(int) FNPDMDEVDESTRUCT(PPDMDEVINS pDevIns);
91/** Pointer to a FNPDMDEVDESTRUCT() function. */
92typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
93
94/**
95 * Device relocation callback.
96 *
97 * This is called when the instance data has been relocated in raw-mode context
98 * (RC). It is also called when the RC hypervisor selects changes. The device
99 * must fixup all necessary pointers and re-query all interfaces to other RC
100 * devices and drivers.
101 *
102 * Before the RC code is executed the first time, this function will be called
103 * with a 0 delta so RC pointer calculations can be one in one place.
104 *
105 * @param pDevIns Pointer to the device instance.
106 * @param offDelta The relocation delta relative to the old location.
107 *
108 * @remarks A relocation CANNOT fail.
109 *
110 * @remarks The device critical section is not entered. The relocations should
111 * not normally require any locking.
112 */
113typedef DECLCALLBACK(void) FNPDMDEVRELOCATE(PPDMDEVINS pDevIns, RTGCINTPTR offDelta);
114/** Pointer to a FNPDMDEVRELOCATE() function. */
115typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
116
117/**
118 * Power On notification.
119 *
120 * @returns VBox status.
121 * @param pDevIns The device instance data.
122 *
123 * @remarks Caller enters the device critical section.
124 */
125typedef DECLCALLBACK(void) FNPDMDEVPOWERON(PPDMDEVINS pDevIns);
126/** Pointer to a FNPDMDEVPOWERON() function. */
127typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
128
129/**
130 * Reset notification.
131 *
132 * @returns VBox status.
133 * @param pDevIns The device instance data.
134 *
135 * @remarks Caller enters the device critical section.
136 */
137typedef DECLCALLBACK(void) FNPDMDEVRESET(PPDMDEVINS pDevIns);
138/** Pointer to a FNPDMDEVRESET() function. */
139typedef FNPDMDEVRESET *PFNPDMDEVRESET;
140
141/**
142 * Soft reset notification.
143 *
144 * This is mainly for emulating the 286 style protected mode exits, in which
145 * most devices should remain in their current state.
146 *
147 * @returns VBox status.
148 * @param pDevIns The device instance data.
149 * @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
150 *
151 * @remarks Caller enters the device critical section.
152 */
153typedef DECLCALLBACK(void) FNPDMDEVSOFTRESET(PPDMDEVINS pDevIns, uint32_t fFlags);
154/** Pointer to a FNPDMDEVSOFTRESET() function. */
155typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
156
157/** @name PDMVMRESET_F_XXX - VM reset flags.
158 * These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
159 * reset via PDMDevHlpVMReset.
160 * @{ */
161/** Unknown reason. */
162#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
163/** GIM triggered reset. */
164#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
165/** The last source always causing hard resets. */
166#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
167/** ACPI triggered reset. */
168#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
169/** PS/2 system port A (92h) reset. */
170#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
171/** Keyboard reset. */
172#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
173/** Tripple fault. */
174#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
175/** Reset source mask. */
176#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
177/** @} */
178
179/**
180 * Suspend notification.
181 *
182 * @returns VBox status.
183 * @param pDevIns The device instance data.
184 * @thread EMT(0)
185 *
186 * @remarks Caller enters the device critical section.
187 */
188typedef DECLCALLBACK(void) FNPDMDEVSUSPEND(PPDMDEVINS pDevIns);
189/** Pointer to a FNPDMDEVSUSPEND() function. */
190typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
191
192/**
193 * Resume notification.
194 *
195 * @returns VBox status.
196 * @param pDevIns The device instance data.
197 *
198 * @remarks Caller enters the device critical section.
199 */
200typedef DECLCALLBACK(void) FNPDMDEVRESUME(PPDMDEVINS pDevIns);
201/** Pointer to a FNPDMDEVRESUME() function. */
202typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
203
204/**
205 * Power Off notification.
206 *
207 * This is always called when VMR3PowerOff is called.
208 * There will be no callback when hot plugging devices.
209 *
210 * @param pDevIns The device instance data.
211 * @thread EMT(0)
212 *
213 * @remarks Caller enters the device critical section.
214 */
215typedef DECLCALLBACK(void) FNPDMDEVPOWEROFF(PPDMDEVINS pDevIns);
216/** Pointer to a FNPDMDEVPOWEROFF() function. */
217typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
218
219/**
220 * Attach command.
221 *
222 * This is called to let the device attach to a driver for a specified LUN
223 * at runtime. This is not called during VM construction, the device
224 * constructor has to attach to all the available drivers.
225 *
226 * This is like plugging in the keyboard or mouse after turning on the PC.
227 *
228 * @returns VBox status code.
229 * @param pDevIns The device instance.
230 * @param iLUN The logical unit which is being attached.
231 * @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
232 *
233 * @remarks Caller enters the device critical section.
234 */
235typedef DECLCALLBACK(int) FNPDMDEVATTACH(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags);
236/** Pointer to a FNPDMDEVATTACH() function. */
237typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
238
239/**
240 * Detach notification.
241 *
242 * This is called when a driver is detaching itself from a LUN of the device.
243 * The device should adjust its state to reflect this.
244 *
245 * This is like unplugging the network cable to use it for the laptop or
246 * something while the PC is still running.
247 *
248 * @param pDevIns The device instance.
249 * @param iLUN The logical unit which is being detached.
250 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
251 *
252 * @remarks Caller enters the device critical section.
253 */
254typedef DECLCALLBACK(void) FNPDMDEVDETACH(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags);
255/** Pointer to a FNPDMDEVDETACH() function. */
256typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
257
258/**
259 * Query the base interface of a logical unit.
260 *
261 * @returns VBOX status code.
262 * @param pDevIns The device instance.
263 * @param iLUN The logicial unit to query.
264 * @param ppBase Where to store the pointer to the base interface of the LUN.
265 *
266 * @remarks The device critical section is not entered.
267 */
268typedef DECLCALLBACK(int) FNPDMDEVQUERYINTERFACE(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase);
269/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
270typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
271
272/**
273 * Init complete notification (after ring-0 & RC init since 5.1).
274 *
275 * This can be done to do communication with other devices and other
276 * initialization which requires everything to be in place.
277 *
278 * @returns VBOX status code.
279 * @param pDevIns The device instance.
280 *
281 * @remarks Caller enters the device critical section.
282 */
283typedef DECLCALLBACK(int) FNPDMDEVINITCOMPLETE(PPDMDEVINS pDevIns);
284/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
285typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
286
287
288/**
289 * The context of a pfnMemSetup call.
290 */
291typedef enum PDMDEVMEMSETUPCTX
292{
293 /** Invalid zero value. */
294 PDMDEVMEMSETUPCTX_INVALID = 0,
295 /** After construction. */
296 PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
297 /** After reset. */
298 PDMDEVMEMSETUPCTX_AFTER_RESET,
299 /** Type size hack. */
300 PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
301} PDMDEVMEMSETUPCTX;
302
303
304/**
305 * PDM Device Registration Structure.
306 *
307 * This structure is used when registering a device from VBoxInitDevices() in HC
308 * Ring-3. PDM will continue use till the VM is terminated.
309 *
310 * @note The first part is the same in every context.
311 */
312typedef struct PDMDEVREGR3
313{
314 /** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
315 uint32_t u32Version;
316 /** Reserved, must be zero. */
317 uint32_t uReserved0;
318 /** Device name, must match the ring-3 one. */
319 char szName[32];
320 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
321 uint32_t fFlags;
322 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
323 uint32_t fClass;
324 /** Maximum number of instances (per VM). */
325 uint32_t cMaxInstances;
326 /** The shared data structure version number. */
327 uint32_t uSharedVersion;
328 /** Size of the instance data. */
329 uint32_t cbInstanceShared;
330 /** Size of the ring-0 instance data. */
331 uint32_t cbInstanceCC;
332 /** Size of the raw-mode instance data. */
333 uint32_t cbInstanceRC;
334 /** Max number of PCI devices. */
335 uint16_t cMaxPciDevices;
336 /** Max number of MSI-X vectors in any of the PCI devices. */
337 uint16_t cMaxMsixVectors;
338 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
339 * remain unchanged from registration till VM destruction. */
340 const char *pszDescription;
341
342 /** Name of the raw-mode context module (no path).
343 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
344 const char *pszRCMod;
345 /** Name of the ring-0 module (no path).
346 * Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
347 const char *pszR0Mod;
348
349 /** Construct instance - required. */
350 PFNPDMDEVCONSTRUCT pfnConstruct;
351 /** Destruct instance - optional.
352 * Critical section NOT entered (will be destroyed). */
353 PFNPDMDEVDESTRUCT pfnDestruct;
354 /** Relocation command - optional.
355 * Critical section NOT entered. */
356 PFNPDMDEVRELOCATE pfnRelocate;
357 /**
358 * Memory setup callback.
359 *
360 * @param pDevIns The device instance data.
361 * @param enmCtx Indicates the context of the call.
362 * @remarks The critical section is entered prior to calling this method.
363 */
364 DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
365 /** Power on notification - optional.
366 * Critical section is entered. */
367 PFNPDMDEVPOWERON pfnPowerOn;
368 /** Reset notification - optional.
369 * Critical section is entered. */
370 PFNPDMDEVRESET pfnReset;
371 /** Suspend notification - optional.
372 * Critical section is entered. */
373 PFNPDMDEVSUSPEND pfnSuspend;
374 /** Resume notification - optional.
375 * Critical section is entered. */
376 PFNPDMDEVRESUME pfnResume;
377 /** Attach command - optional.
378 * Critical section is entered. */
379 PFNPDMDEVATTACH pfnAttach;
380 /** Detach notification - optional.
381 * Critical section is entered. */
382 PFNPDMDEVDETACH pfnDetach;
383 /** Query a LUN base interface - optional.
384 * Critical section is NOT entered. */
385 PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
386 /** Init complete notification - optional.
387 * Critical section is entered. */
388 PFNPDMDEVINITCOMPLETE pfnInitComplete;
389 /** Power off notification - optional.
390 * Critical section is entered. */
391 PFNPDMDEVPOWEROFF pfnPowerOff;
392 /** Software system reset notification - optional.
393 * Critical section is entered. */
394 PFNPDMDEVSOFTRESET pfnSoftReset;
395
396 /** @name Reserved for future extensions, must be zero.
397 * @{ */
398 DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
399 DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
400 DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
401 DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
402 DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
403 DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
404 DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
405 DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
406 /** @} */
407
408 /** Initialization safty marker. */
409 uint32_t u32VersionEnd;
410} PDMDEVREGR3;
411/** Pointer to a PDM Device Structure. */
412typedef PDMDEVREGR3 *PPDMDEVREGR3;
413/** Const pointer to a PDM Device Structure. */
414typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
415/** Current DEVREGR3 version number. */
416#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
417
418
419/** PDM Device Flags.
420 * @{ */
421/** This flag is used to indicate that the device has a R0 component. */
422#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
423/** Requires the ring-0 component, ignore configuration values. */
424#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
425/** Requires the ring-0 component, ignore configuration values. */
426#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
427
428/** This flag is used to indicate that the device has a RC component. */
429#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
430/** Requires the raw-mode component, ignore configuration values. */
431#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
432/** Requires the raw-mode component, ignore configuration values. */
433#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
434
435/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
436#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_RC)
437
438/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
439 * The bit count for the current host.
440 * @note Superfluous, but still around for hysterical raisins. */
441#if HC_ARCH_BITS == 32
442# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
443#elif HC_ARCH_BITS == 64
444# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
445#else
446# error Unsupported HC_ARCH_BITS value.
447#endif
448/** The host bit count mask. */
449#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
450
451/** The device support only 32-bit guests. */
452#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
453/** The device support only 64-bit guests. */
454#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
455/** The device support both 32-bit & 64-bit guests. */
456#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
457/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
458 * The guest bit count for the current compilation. */
459#if GC_ARCH_BITS == 32
460# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
461#elif GC_ARCH_BITS == 64
462# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
463#else
464# error Unsupported GC_ARCH_BITS value.
465#endif
466/** The guest bit count mask. */
467#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
468
469/** A convenience. */
470#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
471
472/** Indicates that the device needs to be notified before the drivers when suspending. */
473#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
474/** Indicates that the device needs to be notified before the drivers when powering off. */
475#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
476/** Indicates that the device needs to be notified before the drivers when resetting. */
477#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
478
479/** This flag is used to indicate that the device has been converted to the
480 * new device style. */
481#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
482
483/** @} */
484
485
486/** PDM Device Classes.
487 * The order is important, lower bit earlier instantiation.
488 * @{ */
489/** Architecture device. */
490#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
491/** Architecture BIOS device. */
492#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
493/** PCI bus brigde. */
494#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
495/** ISA bus brigde. */
496#define PDM_DEVREG_CLASS_BUS_ISA RT_BIT(3)
497/** Input device (mouse, keyboard, joystick, HID, ...). */
498#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
499/** Interrupt controller (PIC). */
500#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
501/** Interval controoler (PIT). */
502#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
503/** RTC/CMOS. */
504#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
505/** DMA controller. */
506#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
507/** VMM Device. */
508#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
509/** Graphics device, like VGA. */
510#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
511/** Storage controller device. */
512#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
513/** Network interface controller. */
514#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
515/** Audio. */
516#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
517/** USB HIC. */
518#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
519/** ACPI. */
520#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
521/** Serial controller device. */
522#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
523/** Parallel controller device */
524#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
525/** Host PCI pass-through device */
526#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
527/** Misc devices (always last). */
528#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
529/** @} */
530
531
532/**
533 * PDM Device Registration Structure, ring-0.
534 *
535 * This structure is used when registering a device from VBoxInitDevices() in HC
536 * Ring-0. PDM will continue use till the VM is terminated.
537 */
538typedef struct PDMDEVREGR0
539{
540 /** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
541 uint32_t u32Version;
542 /** Reserved, must be zero. */
543 uint32_t uReserved0;
544 /** Device name, must match the ring-3 one. */
545 char szName[32];
546 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
547 uint32_t fFlags;
548 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
549 uint32_t fClass;
550 /** Maximum number of instances (per VM). */
551 uint32_t cMaxInstances;
552 /** The shared data structure version number. */
553 uint32_t uSharedVersion;
554 /** Size of the instance data. */
555 uint32_t cbInstanceShared;
556 /** Size of the ring-0 instance data. */
557 uint32_t cbInstanceCC;
558 /** Size of the raw-mode instance data. */
559 uint32_t cbInstanceRC;
560 /** Max number of PCI devices. */
561 uint16_t cMaxPciDevices;
562 /** Max number of MSI-X vectors in any of the PCI devices. */
563 uint16_t cMaxMsixVectors;
564 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
565 * remain unchanged from registration till VM destruction. */
566 const char *pszDescription;
567
568 /**
569 * Early construction callback (optional).
570 *
571 * This is called right after the device instance structure has been allocated
572 * and before the ring-3 constructor gets called.
573 *
574 * @returns VBox status code.
575 * @param pDevIns The device instance data.
576 * @note The destructure is always called, regardless of the return status.
577 */
578 DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
579
580 /**
581 * Regular construction callback (optional).
582 *
583 * This is called after (or during) the ring-3 constructor.
584 *
585 * @returns VBox status code.
586 * @param pDevIns The device instance data.
587 * @note The destructure is always called, regardless of the return status.
588 */
589 DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
590
591 /**
592 * Destructor (optional).
593 *
594 * This is called after the ring-3 destruction. This is not called if ring-3
595 * fails to trigger it (e.g. process is killed or crashes).
596 *
597 * @param pDevIns The device instance data.
598 */
599 DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
600
601 /**
602 * Final destructor (optional).
603 *
604 * This is called right before the memory is freed, which happens when the
605 * VM/GVM object is destroyed. This is always called.
606 *
607 * @param pDevIns The device instance data.
608 */
609 DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
610
611 /**
612 * Generic request handler (optional).
613 *
614 * @param pDevIns The device instance data.
615 * @param uReq Device specific request.
616 * @param uArg Request argument.
617 */
618 DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
619
620 /** @name Reserved for future extensions, must be zero.
621 * @{ */
622 DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
623 DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
624 DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
625 DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
626 DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
627 DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
628 DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
629 DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
630 /** @} */
631
632 /** Initialization safty marker. */
633 uint32_t u32VersionEnd;
634} PDMDEVREGR0;
635/** Pointer to a ring-0 PDM device registration structure. */
636typedef PDMDEVREGR0 *PPDMDEVREGR0;
637/** Pointer to a const ring-0 PDM device registration structure. */
638typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
639/** Current DEVREGR0 version number. */
640#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
641
642
643/**
644 * PDM Device Registration Structure, raw-mode
645 *
646 * At the moment, this structure is mostly here to match the other two contexts.
647 */
648typedef struct PDMDEVREGRC
649{
650 /** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
651 uint32_t u32Version;
652 /** Reserved, must be zero. */
653 uint32_t uReserved0;
654 /** Device name, must match the ring-3 one. */
655 char szName[32];
656 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
657 uint32_t fFlags;
658 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
659 uint32_t fClass;
660 /** Maximum number of instances (per VM). */
661 uint32_t cMaxInstances;
662 /** The shared data structure version number. */
663 uint32_t uSharedVersion;
664 /** Size of the instance data. */
665 uint32_t cbInstanceShared;
666 /** Size of the ring-0 instance data. */
667 uint32_t cbInstanceCC;
668 /** Size of the raw-mode instance data. */
669 uint32_t cbInstanceRC;
670 /** Max number of PCI devices. */
671 uint16_t cMaxPciDevices;
672 /** Max number of MSI-X vectors in any of the PCI devices. */
673 uint16_t cMaxMsixVectors;
674 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
675 * remain unchanged from registration till VM destruction. */
676 const char *pszDescription;
677
678 /**
679 * Constructor callback.
680 *
681 * This is called much later than both the ring-0 and ring-3 constructors, since
682 * raw-mode v2 require a working VMM to run actual code.
683 *
684 * @returns VBox status code.
685 * @param pDevIns The device instance data.
686 * @note The destructure is always called, regardless of the return status.
687 */
688 DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
689
690 /** @name Reserved for future extensions, must be zero.
691 * @{ */
692 DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
693 DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
694 DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
695 DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
696 DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
697 DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
698 DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
699 DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
700 /** @} */
701
702 /** Initialization safty marker. */
703 uint32_t u32VersionEnd;
704} PDMDEVREGRC;
705/** Pointer to a raw-mode PDM device registration structure. */
706typedef PDMDEVREGRC *PPDMDEVREGRC;
707/** Pointer to a const raw-mode PDM device registration structure. */
708typedef PDMDEVREGRC const *PCPDMDEVREGRC;
709/** Current DEVREGRC version number. */
710#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
711
712
713
714/** @def PDM_DEVREG_VERSION
715 * Current DEVREG version number. */
716/** @typedef PDMDEVREGR3
717 * A current context PDM device registration structure. */
718/** @typedef PPDMDEVREGR3
719 * Pointer to a current context PDM device registration structure. */
720/** @typedef PCPDMDEVREGR3
721 * Pointer to a const current context PDM device registration structure. */
722#if defined(IN_RING3) || defined(DOXYGEN_RUNNING)
723# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
724typedef PDMDEVREGR3 PDMDEVREG;
725typedef PPDMDEVREGR3 PPDMDEVREG;
726typedef PCPDMDEVREGR3 PCPDMDEVREG;
727#elif defined(IN_RING0)
728# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
729typedef PDMDEVREGR0 PDMDEVREG;
730typedef PPDMDEVREGR0 PPDMDEVREG;
731typedef PCPDMDEVREGR0 PCPDMDEVREG;
732#elif defined(IN_RC)
733# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
734typedef PDMDEVREGRC PDMDEVREG;
735typedef PPDMDEVREGRC PPDMDEVREG;
736typedef PCPDMDEVREGRC PCPDMDEVREG;
737#else
738# error "Not IN_RING3, IN_RING0 or IN_RC"
739#endif
740
741
742/**
743 * Device registrations for ring-0 modules.
744 *
745 * This structure is used directly and must therefore reside in persistent
746 * memory (i.e. the data section).
747 */
748typedef struct PDMDEVMODREGR0
749{
750 /** The structure version (PDM_DEVMODREGR0_VERSION). */
751 uint32_t u32Version;
752 /** Number of devices in the array papDevRegs points to. */
753 uint32_t cDevRegs;
754 /** Pointer to device registration structures. */
755 PCPDMDEVREGR0 *papDevRegs;
756 /** The ring-0 module handle - PDM internal, fingers off. */
757 void *hMod;
758 /** List entry - PDM internal, fingers off. */
759 RTLISTNODE ListEntry;
760} PDMDEVMODREGR0;
761/** Pointer to device registriations for a ring-0 module. */
762typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
763/** Current PDMDEVMODREGR0 version number. */
764#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
765
766
767/** @name IRQ Level for use with the *SetIrq APIs.
768 * @{
769 */
770/** Assert the IRQ (can assume value 1). */
771#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
772/** Deassert the IRQ (can assume value 0). */
773#define PDM_IRQ_LEVEL_LOW 0
774/** flip-flop - deassert and then assert the IRQ again immediately. */
775#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) | PDM_IRQ_LEVEL_HIGH)
776/** @} */
777
778/**
779 * Registration record for MSI/MSI-X emulation.
780 */
781typedef struct PDMMSIREG
782{
783 /** Number of MSI interrupt vectors, 0 if MSI not supported */
784 uint16_t cMsiVectors;
785 /** Offset of MSI capability */
786 uint8_t iMsiCapOffset;
787 /** Offset of next capability to MSI */
788 uint8_t iMsiNextOffset;
789 /** If we support 64-bit MSI addressing */
790 bool fMsi64bit;
791 /** If we do not support per-vector masking */
792 bool fMsiNoMasking;
793
794 /** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
795 uint16_t cMsixVectors;
796 /** Offset of MSI-X capability */
797 uint8_t iMsixCapOffset;
798 /** Offset of next capability to MSI-X */
799 uint8_t iMsixNextOffset;
800 /** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
801 uint8_t iMsixBar;
802} PDMMSIREG;
803typedef PDMMSIREG *PPDMMSIREG;
804
805/**
806 * PCI Bus registration structure.
807 * All the callbacks, except the PCIBIOS hack, are working on PCI devices.
808 */
809typedef struct PDMPCIBUSREGR3
810{
811 /** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
812 uint32_t u32Version;
813
814 /**
815 * Registers the device with the default PCI bus.
816 *
817 * @returns VBox status code.
818 * @param pDevIns Device instance of the PCI Bus.
819 * @param pPciDev The PCI device structure.
820 * @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
821 * @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
822 * device number (0-31).
823 * @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
824 * function number (0-7).
825 * @param pszName Device name (static but not unique).
826 *
827 * @remarks Caller enters the PDM critical section.
828 */
829 DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
830 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
831
832 /**
833 * Initialize MSI or MSI-X emulation support in a PCI device.
834 *
835 * This cannot handle all corner cases of the MSI/MSI-X spec, but for the
836 * vast majority of device emulation it covers everything necessary. It's
837 * fully automatic, taking care of all BAR and config space requirements,
838 * and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
839 * When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
840 * the vector number (otherwise it has the usual INTA-D meaning for PCI).
841 *
842 * A device not using this can still offer MSI/MSI-X. In this case it's
843 * completely up to the device (in the MSI-X case) to create/register the
844 * necessary MMIO BAR, handle all config space/BAR updating and take care
845 * of delivering the interrupts appropriately.
846 *
847 * @returns VBox status code.
848 * @param pDevIns Device instance of the PCI Bus.
849 * @param pPciDev The PCI device structure.
850 * @param pMsiReg MSI emulation registration structure
851 * @remarks Caller enters the PDM critical section.
852 */
853 DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
854
855 /**
856 * Registers a I/O region (memory mapped or I/O ports) for a PCI device.
857 *
858 * @returns VBox status code.
859 * @param pDevIns Device instance of the PCI Bus.
860 * @param pPciDev The PCI device structure.
861 * @param iRegion The region number.
862 * @param cbRegion Size of the region.
863 * @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
864 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
865 * PCI_ADDRESS_SPACE_BAR64 or'ed in.
866 * @param fFlags PDMPCIDEV_IORGN_F_XXX.
867 * @param hHandle An I/O port, MMIO or MMIO2 handle according to
868 * @a fFlags, UINT64_MAX if no handle is passed
869 * (old style).
870 * @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
871 * is given.
872 * @remarks Caller enters the PDM critical section.
873 */
874 DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
875 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
876 uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
877
878 /**
879 * Register PCI configuration space read/write intercept callbacks.
880 *
881 * @param pDevIns Device instance of the PCI Bus.
882 * @param pPciDev The PCI device structure.
883 * @param pfnRead Pointer to the user defined PCI config read function.
884 * @param pfnWrite Pointer to the user defined PCI config write function.
885 * to call default PCI config write function. Can be NULL.
886 * @remarks Caller enters the PDM critical section.
887 * @thread EMT
888 */
889 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
890 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
891
892 /**
893 * Perform a PCI configuration space write, bypassing interception.
894 *
895 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
896 *
897 * @returns Strict VBox status code (mainly DBGFSTOP).
898 * @param pDevIns Device instance of the PCI Bus.
899 * @param pPciDev The PCI device which config space is being read.
900 * @param uAddress The config space address.
901 * @param cb The size of the read: 1, 2 or 4 bytes.
902 * @param u32Value The value to write.
903 * @note The caller (PDM) does not enter the PDM critsect, but it is possible
904 * that the (root) bus will have done that already.
905 */
906 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
907 uint32_t uAddress, unsigned cb, uint32_t u32Value));
908
909 /**
910 * Perform a PCI configuration space read, bypassing interception.
911 *
912 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
913 *
914 * @returns Strict VBox status code (mainly DBGFSTOP).
915 * @param pDevIns Device instance of the PCI Bus.
916 * @param pPciDev The PCI device which config space is being read.
917 * @param uAddress The config space address.
918 * @param cb The size of the read: 1, 2 or 4 bytes.
919 * @param pu32Value Where to return the value.
920 * @note The caller (PDM) does not enter the PDM critsect, but it is possible
921 * that the (root) bus will have done that already.
922 */
923 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
924 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
925
926 /**
927 * Set the IRQ for a PCI device.
928 *
929 * @param pDevIns Device instance of the PCI Bus.
930 * @param pPciDev The PCI device structure.
931 * @param iIrq IRQ number to set.
932 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
933 * @param uTagSrc The IRQ tag and source (for tracing).
934 * @remarks Caller enters the PDM critical section.
935 */
936 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
937
938 /** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
939 uint32_t u32EndVersion;
940} PDMPCIBUSREGR3;
941/** Pointer to a PCI bus registration structure. */
942typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
943/** Current PDMPCIBUSREGR3 version number. */
944#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
945
946/**
947 * PCI Bus registration structure for ring-0.
948 */
949typedef struct PDMPCIBUSREGR0
950{
951 /** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
952 uint32_t u32Version;
953 /** The PCI bus number (from ring-3 registration). */
954 uint32_t iBus;
955 /**
956 * Set the IRQ for a PCI device.
957 *
958 * @param pDevIns Device instance of the PCI Bus.
959 * @param pPciDev The PCI device structure.
960 * @param iIrq IRQ number to set.
961 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
962 * @param uTagSrc The IRQ tag and source (for tracing).
963 * @remarks Caller enters the PDM critical section.
964 */
965 DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
966 /** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
967 uint32_t u32EndVersion;
968} PDMPCIBUSREGR0;
969/** Pointer to a PCI bus ring-0 registration structure. */
970typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
971/** Current PDMPCIBUSREGR0 version number. */
972#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
973
974/**
975 * PCI Bus registration structure for raw-mode.
976 */
977typedef struct PDMPCIBUSREGRC
978{
979 /** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
980 uint32_t u32Version;
981 /** The PCI bus number (from ring-3 registration). */
982 uint32_t iBus;
983 /**
984 * Set the IRQ for a PCI device.
985 *
986 * @param pDevIns Device instance of the PCI Bus.
987 * @param pPciDev The PCI device structure.
988 * @param iIrq IRQ number to set.
989 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
990 * @param uTagSrc The IRQ tag and source (for tracing).
991 * @remarks Caller enters the PDM critical section.
992 */
993 DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
994 /** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
995 uint32_t u32EndVersion;
996} PDMPCIBUSREGRC;
997/** Pointer to a PCI bus raw-mode registration structure. */
998typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
999/** Current PDMPCIBUSREGRC version number. */
1000#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1001
1002/** PCI bus registration structure for the current context. */
1003typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1004/** Pointer to a PCI bus registration structure for the current context. */
1005typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1006/** PCI bus registration structure version for the current context. */
1007#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1008
1009
1010/**
1011 * PCI Bus RC helpers.
1012 */
1013typedef struct PDMPCIHLPRC
1014{
1015 /** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1016 uint32_t u32Version;
1017
1018 /**
1019 * Set an ISA IRQ.
1020 *
1021 * @param pDevIns PCI device instance.
1022 * @param iIrq IRQ number to set.
1023 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1024 * @param uTagSrc The IRQ tag and source (for tracing).
1025 * @thread EMT only.
1026 */
1027 DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1028
1029 /**
1030 * Set an I/O-APIC IRQ.
1031 *
1032 * @param pDevIns PCI device instance.
1033 * @param iIrq IRQ number to set.
1034 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1035 * @param uTagSrc The IRQ tag and source (for tracing).
1036 * @thread EMT only.
1037 */
1038 DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1039
1040 /**
1041 * Send an MSI.
1042 *
1043 * @param pDevIns PCI device instance.
1044 * @param GCPhys Physical address MSI request was written.
1045 * @param uValue Value written.
1046 * @param uTagSrc The IRQ tag and source (for tracing).
1047 * @thread EMT only.
1048 */
1049 DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1050
1051
1052 /**
1053 * Acquires the PDM lock.
1054 *
1055 * @returns VINF_SUCCESS on success.
1056 * @returns rc if we failed to acquire the lock.
1057 * @param pDevIns The PCI device instance.
1058 * @param rc What to return if we fail to acquire the lock.
1059 */
1060 DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1061
1062 /**
1063 * Releases the PDM lock.
1064 *
1065 * @param pDevIns The PCI device instance.
1066 */
1067 DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1068
1069 /**
1070 * Gets a bus by it's PDM ordinal (typically the parent bus).
1071 *
1072 * @returns Pointer to the device instance of the bus.
1073 * @param pDevIns The PCI bus device instance.
1074 * @param idxPdmBus The PDM ordinal value of the bus to get.
1075 */
1076 DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1077
1078 /** Just a safety precaution. */
1079 uint32_t u32TheEnd;
1080} PDMPCIHLPRC;
1081/** Pointer to PCI helpers. */
1082typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1083/** Pointer to const PCI helpers. */
1084typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1085
1086/** Current PDMPCIHLPRC version number. */
1087#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 3, 0)
1088
1089
1090/**
1091 * PCI Bus R0 helpers.
1092 */
1093typedef struct PDMPCIHLPR0
1094{
1095 /** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1096 uint32_t u32Version;
1097
1098 /**
1099 * Set an ISA IRQ.
1100 *
1101 * @param pDevIns PCI device instance.
1102 * @param iIrq IRQ number to set.
1103 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1104 * @param uTagSrc The IRQ tag and source (for tracing).
1105 * @thread EMT only.
1106 */
1107 DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1108
1109 /**
1110 * Set an I/O-APIC IRQ.
1111 *
1112 * @param pDevIns PCI device instance.
1113 * @param iIrq IRQ number to set.
1114 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1115 * @param uTagSrc The IRQ tag and source (for tracing).
1116 * @thread EMT only.
1117 */
1118 DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1119
1120 /**
1121 * Send an MSI.
1122 *
1123 * @param pDevIns PCI device instance.
1124 * @param GCPhys Physical address MSI request was written.
1125 * @param uValue Value written.
1126 * @param uTagSrc The IRQ tag and source (for tracing).
1127 * @thread EMT only.
1128 */
1129 DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1130
1131 /**
1132 * Acquires the PDM lock.
1133 *
1134 * @returns VINF_SUCCESS on success.
1135 * @returns rc if we failed to acquire the lock.
1136 * @param pDevIns The PCI device instance.
1137 * @param rc What to return if we fail to acquire the lock.
1138 */
1139 DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1140
1141 /**
1142 * Releases the PDM lock.
1143 *
1144 * @param pDevIns The PCI device instance.
1145 */
1146 DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1147
1148 /**
1149 * Gets a bus by it's PDM ordinal (typically the parent bus).
1150 *
1151 * @returns Pointer to the device instance of the bus.
1152 * @param pDevIns The PCI bus device instance.
1153 * @param idxPdmBus The PDM ordinal value of the bus to get.
1154 */
1155 DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1156
1157 /** Just a safety precaution. */
1158 uint32_t u32TheEnd;
1159} PDMPCIHLPR0;
1160/** Pointer to PCI helpers. */
1161typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1162/** Pointer to const PCI helpers. */
1163typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1164
1165/** Current PDMPCIHLPR0 version number. */
1166#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 4, 0)
1167
1168/**
1169 * PCI device helpers.
1170 */
1171typedef struct PDMPCIHLPR3
1172{
1173 /** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1174 uint32_t u32Version;
1175
1176 /**
1177 * Set an ISA IRQ.
1178 *
1179 * @param pDevIns The PCI device instance.
1180 * @param iIrq IRQ number to set.
1181 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1182 * @param uTagSrc The IRQ tag and source (for tracing).
1183 */
1184 DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1185
1186 /**
1187 * Set an I/O-APIC IRQ.
1188 *
1189 * @param pDevIns The PCI device instance.
1190 * @param iIrq IRQ number to set.
1191 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1192 * @param uTagSrc The IRQ tag and source (for tracing).
1193 */
1194 DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1195
1196 /**
1197 * Send an MSI.
1198 *
1199 * @param pDevIns PCI device instance.
1200 * @param GCPhys Physical address MSI request was written.
1201 * @param uValue Value written.
1202 * @param uTagSrc The IRQ tag and source (for tracing).
1203 */
1204 DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1205
1206 /**
1207 * Checks if the given address is an MMIO2 or pre-registered MMIO base address.
1208 *
1209 * @returns true/false accordingly.
1210 * @param pDevIns The PCI device instance.
1211 * @param pOwner The owner of the memory, optional.
1212 * @param GCPhys The address to check.
1213 * @sa PGMR3PhysMMIOExIsBase
1214 */
1215 DECLR3CALLBACKMEMBER(bool, pfnIsMMIOExBase,(PPDMDEVINS pDevIns, PPDMDEVINS pOwner, RTGCPHYS GCPhys));
1216
1217 /**
1218 * Acquires the PDM lock.
1219 *
1220 * @returns VINF_SUCCESS on success.
1221 * @returns Fatal error on failure.
1222 * @param pDevIns The PCI device instance.
1223 * @param rc Dummy for making the interface identical to the RC and R0 versions.
1224 */
1225 DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1226
1227 /**
1228 * Releases the PDM lock.
1229 *
1230 * @param pDevIns The PCI device instance.
1231 */
1232 DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1233
1234 /**
1235 * Gets a bus by it's PDM ordinal (typically the parent bus).
1236 *
1237 * @returns Pointer to the device instance of the bus.
1238 * @param pDevIns The PCI bus device instance.
1239 * @param idxPdmBus The PDM ordinal value of the bus to get.
1240 */
1241 DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1242
1243 /** Just a safety precaution. */
1244 uint32_t u32TheEnd;
1245} PDMPCIHLPR3;
1246/** Pointer to PCI helpers. */
1247typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1248/** Pointer to const PCI helpers. */
1249typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1250
1251/** Current PDMPCIHLPR3 version number. */
1252#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 4, 0)
1253
1254
1255/**
1256 * Programmable Interrupt Controller registration structure (all contexts).
1257 */
1258typedef struct PDMPICREG
1259{
1260 /** Structure version number. PDM_PICREG_VERSION defines the current version. */
1261 uint32_t u32Version;
1262
1263 /**
1264 * Set the an IRQ.
1265 *
1266 * @param pDevIns Device instance of the PIC.
1267 * @param iIrq IRQ number to set.
1268 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1269 * @param uTagSrc The IRQ tag and source (for tracing).
1270 * @remarks Caller enters the PDM critical section.
1271 */
1272 DECLCALLBACKMEMBER(void, pfnSetIrq)(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc);
1273
1274 /**
1275 * Get a pending interrupt.
1276 *
1277 * @returns Pending interrupt number.
1278 * @param pDevIns Device instance of the PIC.
1279 * @param puTagSrc Where to return the IRQ tag and source.
1280 * @remarks Caller enters the PDM critical section.
1281 */
1282 DECLCALLBACKMEMBER(int, pfnGetInterrupt)(PPDMDEVINS pDevIns, uint32_t *puTagSrc);
1283
1284 /** Just a safety precaution. */
1285 uint32_t u32TheEnd;
1286} PDMPICREG;
1287/** Pointer to a PIC registration structure. */
1288typedef PDMPICREG *PPDMPICREG;
1289
1290/** Current PDMPICREG version number. */
1291#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1292
1293/**
1294 * PIC helpers, same in all contexts.
1295 */
1296typedef struct PDMPICHLP
1297{
1298 /** Structure version. PDM_PICHLP_VERSION defines the current version. */
1299 uint32_t u32Version;
1300
1301 /**
1302 * Set the interrupt force action flag.
1303 *
1304 * @param pDevIns Device instance of the PIC.
1305 */
1306 DECLCALLBACKMEMBER(void, pfnSetInterruptFF)(PPDMDEVINS pDevIns);
1307
1308 /**
1309 * Clear the interrupt force action flag.
1310 *
1311 * @param pDevIns Device instance of the PIC.
1312 */
1313 DECLCALLBACKMEMBER(void, pfnClearInterruptFF)(PPDMDEVINS pDevIns);
1314
1315 /**
1316 * Acquires the PDM lock.
1317 *
1318 * @returns VINF_SUCCESS on success.
1319 * @returns rc if we failed to acquire the lock.
1320 * @param pDevIns The PIC device instance.
1321 * @param rc What to return if we fail to acquire the lock.
1322 */
1323 DECLCALLBACKMEMBER(int, pfnLock)(PPDMDEVINS pDevIns, int rc);
1324
1325 /**
1326 * Releases the PDM lock.
1327 *
1328 * @param pDevIns The PIC device instance.
1329 */
1330 DECLCALLBACKMEMBER(void, pfnUnlock)(PPDMDEVINS pDevIns);
1331
1332 /** Just a safety precaution. */
1333 uint32_t u32TheEnd;
1334} PDMPICHLP;
1335/** Pointer to PIC helpers. */
1336typedef PDMPICHLP *PPDMPICHLP;
1337/** Pointer to const PIC helpers. */
1338typedef const PDMPICHLP *PCPDMPICHLP;
1339
1340/** Current PDMPICHLP version number. */
1341#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1342
1343
1344/**
1345 * Firmware registration structure.
1346 */
1347typedef struct PDMFWREG
1348{
1349 /** Struct version+magic number (PDM_FWREG_VERSION). */
1350 uint32_t u32Version;
1351
1352 /**
1353 * Checks whether this is a hard or soft reset.
1354 *
1355 * The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1356 * is 5, 9 or 0xA.
1357 *
1358 * @returns true if hard reset, false if soft.
1359 * @param pDevIns Device instance of the firmware.
1360 * @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1361 */
1362 DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1363
1364 /** Just a safety precaution. */
1365 uint32_t u32TheEnd;
1366} PDMFWREG;
1367/** Pointer to a FW registration structure. */
1368typedef PDMFWREG *PPDMFWREG;
1369/** Pointer to a const FW registration structure. */
1370typedef PDMFWREG const *PCPDMFWREG;
1371
1372/** Current PDMFWREG version number. */
1373#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1374
1375/**
1376 * Firmware R3 helpers.
1377 */
1378typedef struct PDMFWHLPR3
1379{
1380 /** Structure version. PDM_FWHLP_VERSION defines the current version. */
1381 uint32_t u32Version;
1382
1383 /** Just a safety precaution. */
1384 uint32_t u32TheEnd;
1385} PDMFWHLPR3;
1386
1387/** Pointer to FW R3 helpers. */
1388typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1389/** Pointer to const FW R3 helpers. */
1390typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1391
1392/** Current PDMFWHLPR3 version number. */
1393#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1394
1395
1396/**
1397 * APIC mode argument for apicR3SetCpuIdFeatureLevel.
1398 *
1399 * Also used in saved-states, CFGM don't change existing values.
1400 */
1401typedef enum PDMAPICMODE
1402{
1403 /** Invalid 0 entry. */
1404 PDMAPICMODE_INVALID = 0,
1405 /** No APIC. */
1406 PDMAPICMODE_NONE,
1407 /** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1408 PDMAPICMODE_APIC,
1409 /** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1410 PDMAPICMODE_X2APIC,
1411 /** The usual 32-bit paranoia. */
1412 PDMAPICMODE_32BIT_HACK = 0x7fffffff
1413} PDMAPICMODE;
1414
1415/**
1416 * APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1417 */
1418typedef enum PDMAPICIRQ
1419{
1420 /** Invalid 0 entry. */
1421 PDMAPICIRQ_INVALID = 0,
1422 /** Normal hardware interrupt. */
1423 PDMAPICIRQ_HARDWARE,
1424 /** NMI. */
1425 PDMAPICIRQ_NMI,
1426 /** SMI. */
1427 PDMAPICIRQ_SMI,
1428 /** ExtINT (HW interrupt via PIC). */
1429 PDMAPICIRQ_EXTINT,
1430 /** Interrupt arrived, needs to be updated to the IRR. */
1431 PDMAPICIRQ_UPDATE_PENDING,
1432 /** The usual 32-bit paranoia. */
1433 PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1434} PDMAPICIRQ;
1435
1436
1437/**
1438 * I/O APIC registration structure (all contexts).
1439 */
1440typedef struct PDMIOAPICREG
1441{
1442 /** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1443 uint32_t u32Version;
1444
1445 /**
1446 * Set an IRQ.
1447 *
1448 * @param pDevIns Device instance of the I/O APIC.
1449 * @param iIrq IRQ number to set.
1450 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1451 * @param uTagSrc The IRQ tag and source (for tracing).
1452 *
1453 * @remarks Caller enters the PDM critical section
1454 * Actually, as per 2018-07-21 this isn't true (bird).
1455 */
1456 DECLCALLBACKMEMBER(void, pfnSetIrq)(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc);
1457
1458 /**
1459 * Send a MSI.
1460 *
1461 * @param pDevIns Device instance of the I/O APIC.
1462 * @param GCPhys Request address.
1463 * @param uValue Request value.
1464 * @param uTagSrc The IRQ tag and source (for tracing).
1465 *
1466 * @remarks Caller enters the PDM critical section
1467 * Actually, as per 2018-07-21 this isn't true (bird).
1468 */
1469 DECLCALLBACKMEMBER(void, pfnSendMsi)(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc);
1470
1471 /**
1472 * Set the EOI for an interrupt vector.
1473 *
1474 * @returns Strict VBox status code - only the following informational status codes:
1475 * @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
1476 * @retval VINF_SUCCESS
1477 *
1478 * @param pDevIns Device instance of the I/O APIC.
1479 * @param u8Vector The vector.
1480 *
1481 * @remarks Caller enters the PDM critical section
1482 * Actually, as per 2018-07-21 this isn't true (bird).
1483 */
1484 DECLCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoi)(PPDMDEVINS pDevIns, uint8_t u8Vector);
1485
1486 /** Just a safety precaution. */
1487 uint32_t u32TheEnd;
1488} PDMIOAPICREG;
1489/** Pointer to an APIC registration structure. */
1490typedef PDMIOAPICREG *PPDMIOAPICREG;
1491
1492/** Current PDMAPICREG version number. */
1493#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 6, 0)
1494
1495
1496/**
1497 * IOAPIC helpers, same in all contexts.
1498 */
1499typedef struct PDMIOAPICHLP
1500{
1501 /** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1502 uint32_t u32Version;
1503
1504 /**
1505 * Private interface between the IOAPIC and APIC.
1506 *
1507 * @returns status code.
1508 * @param pDevIns Device instance of the IOAPIC.
1509 * @param u8Dest See APIC implementation.
1510 * @param u8DestMode See APIC implementation.
1511 * @param u8DeliveryMode See APIC implementation.
1512 * @param uVector See APIC implementation.
1513 * @param u8Polarity See APIC implementation.
1514 * @param u8TriggerMode See APIC implementation.
1515 * @param uTagSrc The IRQ tag and source (for tracing).
1516 *
1517 * @sa APICBusDeliver()
1518 */
1519 DECLCALLBACKMEMBER(int, pfnApicBusDeliver)(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1520 uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc);
1521
1522 /**
1523 * Acquires the PDM lock.
1524 *
1525 * @returns VINF_SUCCESS on success.
1526 * @returns rc if we failed to acquire the lock.
1527 * @param pDevIns The IOAPIC device instance.
1528 * @param rc What to return if we fail to acquire the lock.
1529 */
1530 DECLCALLBACKMEMBER(int, pfnLock)(PPDMDEVINS pDevIns, int rc);
1531
1532 /**
1533 * Releases the PDM lock.
1534 *
1535 * @param pDevIns The IOAPIC device instance.
1536 */
1537 DECLCALLBACKMEMBER(void, pfnUnlock)(PPDMDEVINS pDevIns);
1538
1539 /** Just a safety precaution. */
1540 uint32_t u32TheEnd;
1541} PDMIOAPICHLP;
1542/** Pointer to IOAPIC helpers. */
1543typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1544/** Pointer to const IOAPIC helpers. */
1545typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1546
1547/** Current PDMIOAPICHLP version number. */
1548#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 2, 0)
1549
1550
1551/**
1552 * HPET registration structure.
1553 */
1554typedef struct PDMHPETREG
1555{
1556 /** Struct version+magic number (PDM_HPETREG_VERSION). */
1557 uint32_t u32Version;
1558} PDMHPETREG;
1559/** Pointer to an HPET registration structure. */
1560typedef PDMHPETREG *PPDMHPETREG;
1561
1562/** Current PDMHPETREG version number. */
1563#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1564
1565/**
1566 * HPET RC helpers.
1567 *
1568 * @remarks Keep this around in case HPET will need PDM interaction in again RC
1569 * at some later point.
1570 */
1571typedef struct PDMHPETHLPRC
1572{
1573 /** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
1574 uint32_t u32Version;
1575
1576 /** Just a safety precaution. */
1577 uint32_t u32TheEnd;
1578} PDMHPETHLPRC;
1579
1580/** Pointer to HPET RC helpers. */
1581typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
1582/** Pointer to const HPET RC helpers. */
1583typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
1584
1585/** Current PDMHPETHLPRC version number. */
1586#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
1587
1588
1589/**
1590 * HPET R0 helpers.
1591 *
1592 * @remarks Keep this around in case HPET will need PDM interaction in again R0
1593 * at some later point.
1594 */
1595typedef struct PDMHPETHLPR0
1596{
1597 /** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
1598 uint32_t u32Version;
1599
1600 /** Just a safety precaution. */
1601 uint32_t u32TheEnd;
1602} PDMHPETHLPR0;
1603
1604/** Pointer to HPET R0 helpers. */
1605typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
1606/** Pointer to const HPET R0 helpers. */
1607typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
1608
1609/** Current PDMHPETHLPR0 version number. */
1610#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
1611
1612/**
1613 * HPET R3 helpers.
1614 */
1615typedef struct PDMHPETHLPR3
1616{
1617 /** Structure version. PDM_HPETHLP_VERSION defines the current version. */
1618 uint32_t u32Version;
1619
1620 /**
1621 * Set legacy mode on PIT and RTC.
1622 *
1623 * @returns VINF_SUCCESS on success.
1624 * @returns rc if we failed to set legacy mode.
1625 * @param pDevIns Device instance of the HPET.
1626 * @param fActivated Whether legacy mode is activated or deactivated.
1627 */
1628 DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
1629
1630
1631 /**
1632 * Set IRQ, bypassing ISA bus override rules.
1633 *
1634 * @returns VINF_SUCCESS on success.
1635 * @returns rc if we failed to set legacy mode.
1636 * @param pDevIns Device instance of the HPET.
1637 * @param iIrq IRQ number to set.
1638 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1639 */
1640 DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
1641
1642 /** Just a safety precaution. */
1643 uint32_t u32TheEnd;
1644} PDMHPETHLPR3;
1645
1646/** Pointer to HPET R3 helpers. */
1647typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
1648/** Pointer to const HPET R3 helpers. */
1649typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
1650
1651/** Current PDMHPETHLPR3 version number. */
1652#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
1653
1654
1655/**
1656 * Raw PCI device registration structure.
1657 */
1658typedef struct PDMPCIRAWREG
1659{
1660 /** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
1661 uint32_t u32Version;
1662 /** Just a safety precaution. */
1663 uint32_t u32TheEnd;
1664} PDMPCIRAWREG;
1665/** Pointer to a raw PCI registration structure. */
1666typedef PDMPCIRAWREG *PPDMPCIRAWREG;
1667
1668/** Current PDMPCIRAWREG version number. */
1669#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
1670
1671/**
1672 * Raw PCI device raw-mode context helpers.
1673 */
1674typedef struct PDMPCIRAWHLPRC
1675{
1676 /** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
1677 uint32_t u32Version;
1678 /** Just a safety precaution. */
1679 uint32_t u32TheEnd;
1680} PDMPCIRAWHLPRC;
1681/** Pointer to a raw PCI deviec raw-mode context helper structure. */
1682typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
1683/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
1684typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
1685
1686/** Current PDMPCIRAWHLPRC version number. */
1687#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
1688
1689/**
1690 * Raw PCI device ring-0 context helpers.
1691 */
1692typedef struct PDMPCIRAWHLPR0
1693{
1694 /** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
1695 uint32_t u32Version;
1696 /** Just a safety precaution. */
1697 uint32_t u32TheEnd;
1698} PDMPCIRAWHLPR0;
1699/** Pointer to a raw PCI deviec ring-0 context helper structure. */
1700typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
1701/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
1702typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
1703
1704/** Current PDMPCIRAWHLPR0 version number. */
1705#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
1706
1707
1708/**
1709 * Raw PCI device ring-3 context helpers.
1710 */
1711typedef struct PDMPCIRAWHLPR3
1712{
1713 /** Undefined structure version and magic number. */
1714 uint32_t u32Version;
1715
1716 /**
1717 * Gets the address of the RC raw PCI device helpers.
1718 *
1719 * This should be called at both construction and relocation time to obtain
1720 * the correct address of the RC helpers.
1721 *
1722 * @returns RC pointer to the raw PCI device helpers.
1723 * @param pDevIns Device instance of the raw PCI device.
1724 */
1725 DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
1726
1727 /**
1728 * Gets the address of the R0 raw PCI device helpers.
1729 *
1730 * This should be called at both construction and relocation time to obtain
1731 * the correct address of the R0 helpers.
1732 *
1733 * @returns R0 pointer to the raw PCI device helpers.
1734 * @param pDevIns Device instance of the raw PCI device.
1735 */
1736 DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
1737
1738 /** Just a safety precaution. */
1739 uint32_t u32TheEnd;
1740} PDMPCIRAWHLPR3;
1741/** Pointer to raw PCI R3 helpers. */
1742typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
1743/** Pointer to const raw PCI R3 helpers. */
1744typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
1745
1746/** Current PDMPCIRAWHLPR3 version number. */
1747#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
1748
1749
1750#ifdef IN_RING3
1751
1752/**
1753 * DMA Transfer Handler.
1754 *
1755 * @returns Number of bytes transferred.
1756 * @param pDevIns Device instance of the DMA.
1757 * @param pvUser User pointer.
1758 * @param uChannel Channel number.
1759 * @param off DMA position.
1760 * @param cb Block size.
1761 * @remarks The device lock is not taken, however, the DMA device lock is held.
1762 */
1763typedef DECLCALLBACK(uint32_t) FNDMATRANSFERHANDLER(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel, uint32_t off, uint32_t cb);
1764/** Pointer to a FNDMATRANSFERHANDLER(). */
1765typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
1766
1767/**
1768 * DMA Controller registration structure.
1769 */
1770typedef struct PDMDMAREG
1771{
1772 /** Structure version number. PDM_DMACREG_VERSION defines the current version. */
1773 uint32_t u32Version;
1774
1775 /**
1776 * Execute pending transfers.
1777 *
1778 * @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
1779 * @param pDevIns Device instance of the DMAC.
1780 * @remarks No locks held, called on EMT(0) as a form of serialization.
1781 */
1782 DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
1783
1784 /**
1785 * Register transfer function for DMA channel.
1786 *
1787 * @param pDevIns Device instance of the DMAC.
1788 * @param uChannel Channel number.
1789 * @param pfnTransferHandler Device specific transfer function.
1790 * @param pvUser User pointer to be passed to the callback.
1791 * @remarks No locks held, called on an EMT.
1792 */
1793 DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
1794
1795 /**
1796 * Read memory
1797 *
1798 * @returns Number of bytes read.
1799 * @param pDevIns Device instance of the DMAC.
1800 * @param uChannel Channel number.
1801 * @param pvBuffer Pointer to target buffer.
1802 * @param off DMA position.
1803 * @param cbBlock Block size.
1804 * @remarks No locks held, called on an EMT.
1805 */
1806 DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
1807
1808 /**
1809 * Write memory
1810 *
1811 * @returns Number of bytes written.
1812 * @param pDevIns Device instance of the DMAC.
1813 * @param uChannel Channel number.
1814 * @param pvBuffer Memory to write.
1815 * @param off DMA position.
1816 * @param cbBlock Block size.
1817 * @remarks No locks held, called on an EMT.
1818 */
1819 DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
1820
1821 /**
1822 * Set the DREQ line.
1823 *
1824 * @param pDevIns Device instance of the DMAC.
1825 * @param uChannel Channel number.
1826 * @param uLevel Level of the line.
1827 * @remarks No locks held, called on an EMT.
1828 */
1829 DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
1830
1831 /**
1832 * Get channel mode
1833 *
1834 * @returns Channel mode.
1835 * @param pDevIns Device instance of the DMAC.
1836 * @param uChannel Channel number.
1837 * @remarks No locks held, called on an EMT.
1838 */
1839 DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
1840
1841} PDMDMACREG;
1842/** Pointer to a DMAC registration structure. */
1843typedef PDMDMACREG *PPDMDMACREG;
1844
1845/** Current PDMDMACREG version number. */
1846#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 1, 0)
1847
1848
1849/**
1850 * DMA Controller device helpers.
1851 */
1852typedef struct PDMDMACHLP
1853{
1854 /** Structure version. PDM_DMACHLP_VERSION defines the current version. */
1855 uint32_t u32Version;
1856
1857 /* to-be-defined */
1858
1859} PDMDMACHLP;
1860/** Pointer to DMAC helpers. */
1861typedef PDMDMACHLP *PPDMDMACHLP;
1862/** Pointer to const DMAC helpers. */
1863typedef const PDMDMACHLP *PCPDMDMACHLP;
1864
1865/** Current PDMDMACHLP version number. */
1866#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
1867
1868#endif /* IN_RING3 */
1869
1870
1871
1872/**
1873 * RTC registration structure.
1874 */
1875typedef struct PDMRTCREG
1876{
1877 /** Structure version number. PDM_RTCREG_VERSION defines the current version. */
1878 uint32_t u32Version;
1879 uint32_t u32Alignment; /**< structure size alignment. */
1880
1881 /**
1882 * Write to a CMOS register and update the checksum if necessary.
1883 *
1884 * @returns VBox status code.
1885 * @param pDevIns Device instance of the RTC.
1886 * @param iReg The CMOS register index.
1887 * @param u8Value The CMOS register value.
1888 * @remarks Caller enters the device critical section.
1889 */
1890 DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
1891
1892 /**
1893 * Read a CMOS register.
1894 *
1895 * @returns VBox status code.
1896 * @param pDevIns Device instance of the RTC.
1897 * @param iReg The CMOS register index.
1898 * @param pu8Value Where to store the CMOS register value.
1899 * @remarks Caller enters the device critical section.
1900 */
1901 DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
1902
1903} PDMRTCREG;
1904/** Pointer to a RTC registration structure. */
1905typedef PDMRTCREG *PPDMRTCREG;
1906/** Pointer to a const RTC registration structure. */
1907typedef const PDMRTCREG *PCPDMRTCREG;
1908
1909/** Current PDMRTCREG version number. */
1910#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
1911
1912
1913/**
1914 * RTC device helpers.
1915 */
1916typedef struct PDMRTCHLP
1917{
1918 /** Structure version. PDM_RTCHLP_VERSION defines the current version. */
1919 uint32_t u32Version;
1920
1921 /* to-be-defined */
1922
1923} PDMRTCHLP;
1924/** Pointer to RTC helpers. */
1925typedef PDMRTCHLP *PPDMRTCHLP;
1926/** Pointer to const RTC helpers. */
1927typedef const PDMRTCHLP *PCPDMRTCHLP;
1928
1929/** Current PDMRTCHLP version number. */
1930#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
1931
1932
1933
1934/** @name Flags for PCI I/O region registration
1935 * @{ */
1936/** No handle is passed. */
1937#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
1938/** An I/O port handle is passed. */
1939#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
1940/** An MMIO range handle is passed. */
1941#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
1942/** An MMIO2 handle is passed. */
1943#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
1944/** Handle type mask. */
1945#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
1946/** New-style (mostly wrt callbacks). */
1947#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
1948/** Mask of valid flags. */
1949#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
1950/** @} */
1951
1952
1953#ifdef IN_RING3
1954
1955/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
1956 * @{ */
1957/** Same device number (and bus) as the previous PCI device registered with the PDM device.
1958 * This is handy when registering multiple PCI device functions and the device
1959 * number is left up to the PCI bus. In order to facilitate one PDM device
1960 * instance for each PCI function, this searches earlier PDM device
1961 * instances as well. */
1962# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
1963/** Use the first unused device number (all functions must be unused). */
1964# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
1965/** Use the first unused device function. */
1966# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
1967
1968/** The device and function numbers are not mandatory, just suggestions. */
1969# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
1970/** Registering a PCI bridge device. */
1971# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
1972/** Valid flag mask. */
1973# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
1974/** @} */
1975
1976/** Current PDMDEVHLPR3 version number. */
1977#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 38, 0)
1978
1979/**
1980 * PDM Device API.
1981 */
1982typedef struct PDMDEVHLPR3
1983{
1984 /** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
1985 uint32_t u32Version;
1986
1987 /** @name I/O ports
1988 * @{ */
1989 /**
1990 * Creates a range of I/O ports for a device.
1991 *
1992 * The I/O port range must be mapped in a separately call. Any ring-0 and
1993 * raw-mode context callback handlers needs to be set up in the respective
1994 * contexts.
1995 *
1996 * @returns VBox status.
1997 * @param pDevIns The device instance to register the ports with.
1998 * @param cPorts Number of ports to register.
1999 * @param fFlags IOM_IOPORT_F_XXX.
2000 * @param pPciDev The PCI device the range is associated with, if
2001 * applicable.
2002 * @param iPciRegion The PCI device region in the high 16-bit word and
2003 * sub-region in the low 16-bit word. UINT32_MAX if NA.
2004 * @param pfnOut Pointer to function which is gonna handle OUT
2005 * operations. Optional.
2006 * @param pfnIn Pointer to function which is gonna handle IN operations.
2007 * Optional.
2008 * @param pfnOutStr Pointer to function which is gonna handle string OUT
2009 * operations. Optional.
2010 * @param pfnInStr Pointer to function which is gonna handle string IN
2011 * operations. Optional.
2012 * @param pvUser User argument to pass to the callbacks.
2013 * @param pszDesc Pointer to description string. This must not be freed.
2014 * @param paExtDescs Extended per-port descriptions, optional. Partial range
2015 * coverage is allowed. This must not be freed.
2016 * @param phIoPorts Where to return the I/O port range handle.
2017 *
2018 * @remarks Caller enters the device critical section prior to invoking the
2019 * registered callback methods.
2020 *
2021 * @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2022 * PDMDevHlpIoPortUnmap.
2023 */
2024 DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2025 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2026 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2027 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2028
2029 /**
2030 * Maps an I/O port range.
2031 *
2032 * @returns VBox status.
2033 * @param pDevIns The device instance to register the ports with.
2034 * @param hIoPorts The I/O port range handle.
2035 * @param Port Where to map the range.
2036 * @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2037 * PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2038 */
2039 DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2040
2041 /**
2042 * Unmaps an I/O port range.
2043 *
2044 * @returns VBox status.
2045 * @param pDevIns The device instance to register the ports with.
2046 * @param hIoPorts The I/O port range handle.
2047 * @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2048 * PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2049 */
2050 DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2051
2052 /**
2053 * Gets the mapping address of the I/O port range @a hIoPorts.
2054 *
2055 * @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2056 * parameters).
2057 * @param pDevIns The device instance to register the ports with.
2058 * @param hIoPorts The I/O port range handle.
2059 */
2060 DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2061 /** @} */
2062
2063 /**
2064 * Register a number of I/O ports with a device.
2065 *
2066 * These callbacks are of course for the host context (HC).
2067 * Register HC handlers before guest context (GC) handlers! There must be a
2068 * HC handler for every GC handler!
2069 *
2070 * @returns VBox status.
2071 * @param pDevIns The device instance to register the ports with.
2072 * @param Port First port number in the range.
2073 * @param cPorts Number of ports to register.
2074 * @param pvUser User argument.
2075 * @param pfnOut Pointer to function which is gonna handle OUT operations.
2076 * @param pfnIn Pointer to function which is gonna handle IN operations.
2077 * @param pfnOutStr Pointer to function which is gonna handle string OUT operations.
2078 * @param pfnInStr Pointer to function which is gonna handle string IN operations.
2079 * @param pszDesc Pointer to description string. This must not be freed.
2080 * @remarks Caller enters the device critical section prior to invoking the
2081 * registered callback methods.
2082 * @deprecated
2083 */
2084 DECLR3CALLBACKMEMBER(int, pfnIOPortRegister,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTHCPTR pvUser,
2085 PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
2086 PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc));
2087
2088 /**
2089 * Register a number of I/O ports with a device for RC.
2090 *
2091 * These callbacks are for the raw-mode context (RC). Register ring-3 context
2092 * (R3) handlers before raw-mode context handlers! There must be a R3 handler
2093 * for every RC handler!
2094 *
2095 * @returns VBox status.
2096 * @param pDevIns The device instance to register the ports with
2097 * and which RC module to resolve the names
2098 * against.
2099 * @param Port First port number in the range.
2100 * @param cPorts Number of ports to register.
2101 * @param pvUser User argument.
2102 * @param pszOut Name of the RC function which is gonna handle OUT operations.
2103 * @param pszIn Name of the RC function which is gonna handle IN operations.
2104 * @param pszOutStr Name of the RC function which is gonna handle string OUT operations.
2105 * @param pszInStr Name of the RC function which is gonna handle string IN operations.
2106 * @param pszDesc Pointer to description string. This must not be freed.
2107 * @remarks Caller enters the device critical section prior to invoking the
2108 * registered callback methods.
2109 * @deprecated
2110 */
2111 DECLR3CALLBACKMEMBER(int, pfnIOPortRegisterRC,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTRCPTR pvUser,
2112 const char *pszOut, const char *pszIn,
2113 const char *pszOutStr, const char *pszInStr, const char *pszDesc));
2114
2115 /**
2116 * Register a number of I/O ports with a device.
2117 *
2118 * These callbacks are of course for the ring-0 host context (R0).
2119 * Register R3 (HC) handlers before R0 (R0) handlers! There must be a R3 (HC) handler for every R0 handler!
2120 *
2121 * @returns VBox status.
2122 * @param pDevIns The device instance to register the ports with.
2123 * @param Port First port number in the range.
2124 * @param cPorts Number of ports to register.
2125 * @param pvUser User argument. (if pointer, then it must be in locked memory!)
2126 * @param pszOut Name of the R0 function which is gonna handle OUT operations.
2127 * @param pszIn Name of the R0 function which is gonna handle IN operations.
2128 * @param pszOutStr Name of the R0 function which is gonna handle string OUT operations.
2129 * @param pszInStr Name of the R0 function which is gonna handle string IN operations.
2130 * @param pszDesc Pointer to description string. This must not be freed.
2131 * @remarks Caller enters the device critical section prior to invoking the
2132 * registered callback methods.
2133 * @deprecated
2134 */
2135 DECLR3CALLBACKMEMBER(int, pfnIOPortRegisterR0,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTR0PTR pvUser,
2136 const char *pszOut, const char *pszIn,
2137 const char *pszOutStr, const char *pszInStr, const char *pszDesc));
2138
2139 /**
2140 * Deregister I/O ports.
2141 *
2142 * This naturally affects both guest context (GC), ring-0 (R0) and ring-3 (R3/HC) handlers.
2143 *
2144 * @returns VBox status.
2145 * @param pDevIns The device instance owning the ports.
2146 * @param Port First port number in the range.
2147 * @param cPorts Number of ports to deregister.
2148 */
2149 DECLR3CALLBACKMEMBER(int, pfnIOPortDeregister,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts));
2150
2151 /** @name MMIO
2152 * @{ */
2153 /**
2154 * Creates a memory mapped I/O (MMIO) region for a device.
2155 *
2156 * The MMIO region must be mapped in a separately call. Any ring-0 and
2157 * raw-mode context callback handlers needs to be set up in the respective
2158 * contexts.
2159 *
2160 * @returns VBox status.
2161 * @param pDevIns The device instance to register the ports with.
2162 * @param cbRegion The size of the region in bytes.
2163 * @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2164 * @param pPciDev The PCI device the range is associated with, if
2165 * applicable.
2166 * @param iPciRegion The PCI device region in the high 16-bit word and
2167 * sub-region in the low 16-bit word. UINT32_MAX if NA.
2168 * @param pfnWrite Pointer to function which is gonna handle Write
2169 * operations.
2170 * @param pfnRead Pointer to function which is gonna handle Read
2171 * operations.
2172 * @param pfnFill Pointer to function which is gonna handle Fill/memset
2173 * operations. (optional)
2174 * @param pvUser User argument to pass to the callbacks.
2175 * @param pszDesc Pointer to description string. This must not be freed.
2176 * @param phRegion Where to return the MMIO region handle.
2177 *
2178 * @remarks Caller enters the device critical section prior to invoking the
2179 * registered callback methods.
2180 *
2181 * @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2182 */
2183 DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2184 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2185 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2186 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion));
2187
2188 /**
2189 * Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2190 *
2191 * @returns VBox status.
2192 * @param pDevIns The device instance the region is associated with.
2193 * @param hRegion The MMIO region handle.
2194 * @param GCPhys Where to map the region.
2195 * @note An MMIO range may overlap with base memory if a lot of RAM is
2196 * configured for the VM, in which case we'll drop the base memory
2197 * pages. Presently we will make no attempt to preserve anything that
2198 * happens to be present in the base memory that is replaced, this is
2199 * technically incorrect but it's just not worth the effort to do
2200 * right, at least not at this point.
2201 * @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2202 * PDMDevHlpMmioSetUpContext
2203 */
2204 DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2205
2206 /**
2207 * Unmaps a memory mapped I/O (MMIO) region.
2208 *
2209 * @returns VBox status.
2210 * @param pDevIns The device instance the region is associated with.
2211 * @param hRegion The MMIO region handle.
2212 * @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2213 * PDMDevHlpMmioSetUpContext
2214 */
2215 DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2216
2217 /**
2218 * Reduces the length of a MMIO range.
2219 *
2220 * This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2221 * only work during saved state restore. It will not call the PCI bus code, as
2222 * that is expected to restore the saved resource configuration.
2223 *
2224 * It just adjusts the mapping length of the region so that when pfnMmioMap is
2225 * called it will only map @a cbRegion bytes and not the value set during
2226 * registration.
2227 *
2228 * @return VBox status code.
2229 * @param pDevIns The device owning the range.
2230 * @param hRegion The MMIO region handle.
2231 * @param cbRegion The new size, must be smaller.
2232 */
2233 DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2234
2235 /**
2236 * Gets the mapping address of the MMIO region @a hRegion.
2237 *
2238 * @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2239 * @param pDevIns The device instance to register the ports with.
2240 * @param hRegion The MMIO region handle.
2241 */
2242 DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2243 /** @} */
2244
2245 /**
2246 * Register a Memory Mapped I/O (MMIO) region.
2247 *
2248 * These callbacks are of course for the ring-3 context (R3). Register HC
2249 * handlers before raw-mode context (RC) and ring-0 context (R0) handlers! There
2250 * must be a R3 handler for every RC and R0 handler!
2251 *
2252 * @returns VBox status.
2253 * @param pDevIns The device instance to register the MMIO with.
2254 * @param GCPhysStart First physical address in the range.
2255 * @param cbRange The size of the range (in bytes).
2256 * @param pvUser User argument.
2257 * @param pfnWrite Pointer to function which is gonna handle Write operations.
2258 * @param pfnRead Pointer to function which is gonna handle Read operations.
2259 * @param pfnFill Pointer to function which is gonna handle Fill/memset operations. (optional)
2260 * @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2261 * @param pszDesc Pointer to description string. This must not be freed.
2262 * @remarks Caller enters the device critical section prior to invoking the
2263 * registered callback methods.
2264 * @deprecated
2265 */
2266 DECLR3CALLBACKMEMBER(int, pfnMMIORegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
2267 PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
2268 uint32_t fFlags, const char *pszDesc));
2269
2270 /**
2271 * Register a Memory Mapped I/O (MMIO) region for RC.
2272 *
2273 * These callbacks are for the raw-mode context (RC). Register ring-3 context
2274 * (R3) handlers before guest context handlers! There must be a R3 handler for
2275 * every RC handler!
2276 *
2277 * @returns VBox status.
2278 * @param pDevIns The device instance to register the MMIO with.
2279 * @param GCPhysStart First physical address in the range.
2280 * @param cbRange The size of the range (in bytes).
2281 * @param pvUser User argument.
2282 * @param pszWrite Name of the RC function which is gonna handle Write operations.
2283 * @param pszRead Name of the RC function which is gonna handle Read operations.
2284 * @param pszFill Name of the RC function which is gonna handle Fill/memset operations. (optional)
2285 * @remarks Caller enters the device critical section prior to invoking the
2286 * registered callback methods.
2287 * @deprecated
2288 */
2289 DECLR3CALLBACKMEMBER(int, pfnMMIORegisterRC,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
2290 const char *pszWrite, const char *pszRead, const char *pszFill));
2291
2292 /**
2293 * Register a Memory Mapped I/O (MMIO) region for R0.
2294 *
2295 * These callbacks are for the ring-0 host context (R0). Register ring-3
2296 * constext (R3) handlers before R0 handlers! There must be a R3 handler for
2297 * every R0 handler!
2298 *
2299 * @returns VBox status.
2300 * @param pDevIns The device instance to register the MMIO with.
2301 * @param GCPhysStart First physical address in the range.
2302 * @param cbRange The size of the range (in bytes).
2303 * @param pvUser User argument. (if pointer, then it must be in locked memory!)
2304 * @param pszWrite Name of the RC function which is gonna handle Write operations.
2305 * @param pszRead Name of the RC function which is gonna handle Read operations.
2306 * @param pszFill Name of the RC function which is gonna handle Fill/memset operations. (optional)
2307 * @remarks Caller enters the device critical section prior to invoking the
2308 * registered callback methods.
2309 * @deprecated
2310 */
2311 DECLR3CALLBACKMEMBER(int, pfnMMIORegisterR0,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
2312 const char *pszWrite, const char *pszRead, const char *pszFill));
2313
2314 /**
2315 * Deregister a Memory Mapped I/O (MMIO) region.
2316 *
2317 * This naturally affects both guest context (GC), ring-0 (R0) and ring-3 (R3/HC) handlers.
2318 *
2319 * @returns VBox status.
2320 * @param pDevIns The device instance owning the MMIO region(s).
2321 * @param GCPhysStart First physical address in the range.
2322 * @param cbRange The size of the range (in bytes).
2323 * @deprecated
2324 */
2325 DECLR3CALLBACKMEMBER(int, pfnMMIODeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange));
2326
2327 /** @name MMIO2
2328 * @{ */
2329 /**
2330 * Creates a MMIO2 region.
2331 *
2332 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2333 * associated with a device. It is also non-shared memory with a permanent
2334 * ring-3 mapping and page backing (presently).
2335 *
2336 * @returns VBox status.
2337 * @param pDevIns The device instance.
2338 * @param pPciDev The PCI device the region is associated with, or
2339 * NULL if no PCI device association.
2340 * @param iPciRegion The region number. Use the PCI region number as
2341 * this must be known to the PCI bus device too. If
2342 * it's not associated with the PCI device, then
2343 * any number up to UINT8_MAX is fine.
2344 * @param cbRegion The size (in bytes) of the region.
2345 * @param fFlags Reserved for future use, must be zero.
2346 * @param pszDesc Pointer to description string. This must not be
2347 * freed.
2348 * @param ppvMapping Where to store the address of the ring-3 mapping
2349 * of the memory.
2350 * @param phRegion Where to return the MMIO2 region handle.
2351 *
2352 * @thread EMT(0)
2353 */
2354 DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2355 uint32_t fFlags, const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion));
2356
2357 /**
2358 * Destroys a MMIO2 region, unmapping it and freeing the memory.
2359 *
2360 * Any physical access handlers registered for the region must be deregistered
2361 * before calling this function.
2362 *
2363 * @returns VBox status code.
2364 * @param pDevIns The device instance.
2365 * @param hRegion The MMIO2 region handle.
2366 * @thread EMT.
2367 */
2368 DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2369
2370 /**
2371 * Maps a MMIO2 region (into the guest physical address space).
2372 *
2373 * @returns VBox status.
2374 * @param pDevIns The device instance the region is associated with.
2375 * @param hRegion The MMIO2 region handle.
2376 * @param GCPhys Where to map the region.
2377 * @note A MMIO2 region overlap with base memory if a lot of RAM is
2378 * configured for the VM, in which case we'll drop the base memory
2379 * pages. Presently we will make no attempt to preserve anything that
2380 * happens to be present in the base memory that is replaced, this is
2381 * technically incorrect but it's just not worth the effort to do
2382 * right, at least not at this point.
2383 * @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2384 */
2385 DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2386
2387 /**
2388 * Unmaps a MMIO2 region.
2389 *
2390 * @returns VBox status.
2391 * @param pDevIns The device instance the region is associated with.
2392 * @param hRegion The MMIO2 region handle.
2393 * @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2394 */
2395 DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2396
2397 /**
2398 * Reduces the length of a MMIO range.
2399 *
2400 * This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2401 * only work during saved state restore. It will not call the PCI bus code, as
2402 * that is expected to restore the saved resource configuration.
2403 *
2404 * It just adjusts the mapping length of the region so that when pfnMmioMap is
2405 * called it will only map @a cbRegion bytes and not the value set during
2406 * registration.
2407 *
2408 * @return VBox status code.
2409 * @param pDevIns The device owning the range.
2410 * @param hRegion The MMIO2 region handle.
2411 * @param cbRegion The new size, must be smaller.
2412 */
2413 DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2414
2415 /**
2416 * Gets the mapping address of the MMIO region @a hRegion.
2417 *
2418 * @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2419 * @param pDevIns The device instance to register the ports with.
2420 * @param hRegion The MMIO2 region handle.
2421 */
2422 DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2423
2424 /**
2425 * Changes the number of an MMIO2 or pre-registered MMIO region.
2426 *
2427 * This should only be used to deal with saved state problems, so there is no
2428 * convenience inline wrapper for this method.
2429 *
2430 * @returns VBox status code.
2431 * @param pDevIns The device instance.
2432 * @param hRegion The MMIO2 region handle.
2433 * @param iNewRegion The new region index.
2434 *
2435 * @sa @bugref{9359}
2436 */
2437 DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2438 /** @} */
2439
2440 /**
2441 * Allocate and register a MMIO2 region.
2442 *
2443 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2444 * associated with a device. It is also non-shared memory with a permanent
2445 * ring-3 mapping and page backing (presently).
2446 *
2447 * @returns VBox status.
2448 * @param pDevIns The device instance.
2449 * @param pPciDev The PCI device the region is associated with, or
2450 * NULL if no PCI device association.
2451 * @param iRegion The region number. Use the PCI region number as
2452 * this must be known to the PCI bus device too. If
2453 * it's not associated with the PCI device, then
2454 * any number up to UINT8_MAX is fine.
2455 * @param cb The size (in bytes) of the region.
2456 * @param fFlags Reserved for future use, must be zero.
2457 * @param ppv Where to store the address of the ring-3 mapping
2458 * of the memory.
2459 * @param pszDesc Pointer to description string. This must not be
2460 * freed.
2461 * @thread EMT.
2462 * @deprecated
2463 */
2464 DECLR3CALLBACKMEMBER(int, pfnMMIO2Register,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cb,
2465 uint32_t fFlags, void **ppv, const char *pszDesc));
2466
2467 /**
2468 * Deregisters and frees a MMIO or MMIO2 region.
2469 *
2470 * Any physical (and virtual) access handlers registered for the region must
2471 * be deregistered before calling this function (MMIO2 only).
2472 *
2473 * @returns VBox status code.
2474 * @param pDevIns The device instance.
2475 * @param pPciDev The PCI device the region is associated with, or
2476 * NULL if not associated with any.
2477 * @param iRegion The region number used during registration.
2478 * @thread EMT.
2479 * @deprecated
2480 */
2481 DECLR3CALLBACKMEMBER(int, pfnMMIOExDeregister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion));
2482
2483 /**
2484 * Maps a MMIO or MMIO2 region into the physical memory space.
2485 *
2486 * A MMIO2 range or a pre-registered MMIO range may overlap with base memory if
2487 * a lot of RAM is configured for the VM, in which case we'll drop the base
2488 * memory pages. Presently we will make no attempt to preserve anything that
2489 * happens to be present in the base memory that is replaced, this is of course
2490 * incorrect but it's too much effort.
2491 *
2492 * @returns VBox status code.
2493 * @param pDevIns The device instance.
2494 * @param pPciDev The PCI device the region is associated with, or
2495 * NULL if not associated with any.
2496 * @param iRegion The region number used during registration.
2497 * @param GCPhys The physical address to map it at.
2498 * @thread EMT.
2499 * @deprecated for MMIO
2500 */
2501 DECLR3CALLBACKMEMBER(int, pfnMMIOExMap,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys));
2502
2503 /**
2504 * Unmaps a MMIO or MMIO2 region previously mapped using pfnMMIOExMap.
2505 *
2506 * @returns VBox status code.
2507 * @param pDevIns The device instance.
2508 * @param pPciDev The PCI device the region is associated with, or
2509 * NULL if not associated with any.
2510 * @param iRegion The region number used during registration.
2511 * @param GCPhys The physical address it's currently mapped at.
2512 * @thread EMT.
2513 * @deprecated for MMIO
2514 */
2515 DECLR3CALLBACKMEMBER(int, pfnMMIOExUnmap,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys));
2516
2517 /**
2518 * Reduces the length of a MMIO2 or pre-registered MMIO range.
2519 *
2520 * This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2521 * only work during saved state restore. It will not call the PCI bus code, as
2522 * that is expected to restore the saved resource configuration.
2523 *
2524 * It just adjusts the mapping length of the region so that when pfnMMIOExMap is
2525 * called it will only map @a cbRegion bytes and not the value set during
2526 * registration.
2527 *
2528 * @return VBox status code.
2529 * @param pDevIns The device owning the range.
2530 * @param pPciDev The PCI device the region is associated with, or
2531 * NULL if not associated with any.
2532 * @param iRegion The region.
2533 * @param cbRegion The new size, must be smaller.
2534 */
2535 DECLR3CALLBACKMEMBER(int, pfnMMIOExReduce,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion));
2536
2537 /**
2538 * Maps a portion of an MMIO2 region into the hypervisor region.
2539 *
2540 * Callers of this API must never deregister the MMIO2 region before the
2541 * VM is powered off.
2542 *
2543 * @return VBox status code.
2544 * @param pDevIns The device owning the MMIO2 memory.
2545 * @param pPciDev The PCI device the region is associated with, or
2546 * NULL if not associated with any.
2547 * @param iRegion The region.
2548 * @param off The offset into the region. Will be rounded down
2549 * to closest page boundary.
2550 * @param cb The number of bytes to map. Will be rounded up
2551 * to the closest page boundary.
2552 * @param pszDesc Mapping description.
2553 * @param pRCPtr Where to store the RC address.
2554 */
2555 DECLR3CALLBACKMEMBER(int, pfnMMHyperMapMMIO2,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
2556 RTGCPHYS cb, const char *pszDesc, PRTRCPTR pRCPtr));
2557
2558 /**
2559 * Maps a portion of an MMIO2 region into kernel space (host).
2560 *
2561 * The kernel mapping will become invalid when the MMIO2 memory is deregistered
2562 * or the VM is terminated.
2563 *
2564 * @return VBox status code.
2565 * @param pDevIns The device owning the MMIO2 memory.
2566 * @param pPciDev The PCI device the region is associated with, or
2567 * NULL if not associated with any.
2568 * @param iRegion The region.
2569 * @param off The offset into the region. Must be page
2570 * aligned.
2571 * @param cb The number of bytes to map. Must be page
2572 * aligned.
2573 * @param pszDesc Mapping description.
2574 * @param pR0Ptr Where to store the R0 address.
2575 */
2576 DECLR3CALLBACKMEMBER(int, pfnMMIO2MapKernel,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
2577 RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr));
2578
2579 /**
2580 * Register a ROM (BIOS) region.
2581 *
2582 * It goes without saying that this is read-only memory. The memory region must be
2583 * in unassigned memory. I.e. from the top of the address space or on the PC in
2584 * the 0xa0000-0xfffff range.
2585 *
2586 * @returns VBox status.
2587 * @param pDevIns The device instance owning the ROM region.
2588 * @param GCPhysStart First physical address in the range.
2589 * Must be page aligned!
2590 * @param cbRange The size of the range (in bytes).
2591 * Must be page aligned!
2592 * @param pvBinary Pointer to the binary data backing the ROM image.
2593 * @param cbBinary The size of the binary pointer. This must
2594 * be equal or smaller than @a cbRange.
2595 * @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2596 * @param pszDesc Pointer to description string. This must not be freed.
2597 *
2598 * @remark There is no way to remove the rom, automatically on device cleanup or
2599 * manually from the device yet. At present I doubt we need such features...
2600 */
2601 DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2602 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc));
2603
2604 /**
2605 * Changes the protection of shadowed ROM mapping.
2606 *
2607 * This is intented for use by the system BIOS, chipset or device in question to
2608 * change the protection of shadowed ROM code after init and on reset.
2609 *
2610 * @param pDevIns The device instance.
2611 * @param GCPhysStart Where the mapping starts.
2612 * @param cbRange The size of the mapping.
2613 * @param enmProt The new protection type.
2614 */
2615 DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2616
2617 /**
2618 * Register a save state data unit.
2619 *
2620 * @returns VBox status.
2621 * @param pDevIns The device instance.
2622 * @param uVersion Data layout version number.
2623 * @param cbGuess The approximate amount of data in the unit.
2624 * Only for progress indicators.
2625 * @param pszBefore Name of data unit which we should be put in
2626 * front of. Optional (NULL).
2627 *
2628 * @param pfnLivePrep Prepare live save callback, optional.
2629 * @param pfnLiveExec Execute live save callback, optional.
2630 * @param pfnLiveVote Vote live save callback, optional.
2631 *
2632 * @param pfnSavePrep Prepare save callback, optional.
2633 * @param pfnSaveExec Execute save callback, optional.
2634 * @param pfnSaveDone Done save callback, optional.
2635 *
2636 * @param pfnLoadPrep Prepare load callback, optional.
2637 * @param pfnLoadExec Execute load callback, optional.
2638 * @param pfnLoadDone Done load callback, optional.
2639 * @remarks Caller enters the device critical section prior to invoking the
2640 * registered callback methods.
2641 */
2642 DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2643 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2644 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2645 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2646
2647 /** @name Exported SSM Functions
2648 * @{ */
2649 DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2650 DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void *pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void *pvUser));
2651 DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2652 DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2653 DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2654 DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2655 DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2656 DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2657 DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2658 DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2659 DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2660 DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2661 DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2662 DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2663 DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2664 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2665 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2666 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2667 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2668 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2669 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2670 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2671 DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2672 DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2673 DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2674 DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2675 DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2676 DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2677 DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void *pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void *pvUser));
2678 DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2679 DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2680 DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2681 DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2682 DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2683 DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2684 DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2685 DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2686 DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2687 DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2688 DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2689 DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2690 DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2691 DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2692 DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2693 DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2694 DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2695 DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2696 DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2697 DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2698 DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2699 DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2700 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2701 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2702 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2703 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2704 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2705 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2706 DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2707 DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2708 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2709 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2710 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2711 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2712 DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2713 DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2714 DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2715 DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2716 DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2717 DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char *psz, size_t cbMax, size_t *pcbStr));
2718 DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2719 DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2720 DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2721 DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2722 DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2723 DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2724 DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2725 DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2726 DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2727 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2728 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2729 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2730 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2731 DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2732 /** @} */
2733
2734 /**
2735 * Creates a timer.
2736 *
2737 * @returns VBox status.
2738 * @param pDevIns The device instance.
2739 * @param enmClock The clock to use on this timer.
2740 * @param pfnCallback Callback function.
2741 * @param pvUser User argument for the callback.
2742 * @param fFlags Flags, see TMTIMER_FLAGS_*.
2743 * @param pszDesc Pointer to description string which must stay around
2744 * until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2745 * @param ppTimer Where to store the timer on success.
2746 * @remarks Caller enters the device critical section prior to invoking the
2747 * callback.
2748 */
2749 DECLR3CALLBACKMEMBER(int, pfnTMTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2750 void *pvUser, uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer));
2751
2752 /**
2753 * Creates a timer w/ a cross context handle.
2754 *
2755 * @returns VBox status.
2756 * @param pDevIns The device instance.
2757 * @param enmClock The clock to use on this timer.
2758 * @param pfnCallback Callback function.
2759 * @param pvUser User argument for the callback.
2760 * @param fFlags Flags, see TMTIMER_FLAGS_*.
2761 * @param pszDesc Pointer to description string which must stay around
2762 * until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2763 * @param phTimer Where to store the timer handle on success.
2764 * @remarks Caller enters the device critical section prior to invoking the
2765 * callback.
2766 */
2767 DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2768 void *pvUser, uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer));
2769
2770 /**
2771 * Translates a timer handle to a pointer.
2772 *
2773 * @returns The time address.
2774 * @param pDevIns The device instance.
2775 * @param hTimer The timer handle.
2776 */
2777 DECLR3CALLBACKMEMBER(PTMTIMERR3, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2778
2779 /** @name Timer handle method wrappers
2780 * @{ */
2781 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2782 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2783 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2784 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2785 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2786 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2787 DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2788 DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2789 DECLR3CALLBACKMEMBER(int, pfnTimerLock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2790 DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2791 DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2792 DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2793 DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2794 DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2795 DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2796 DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2797 DECLR3CALLBACKMEMBER(void, pfnTimerUnlock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2798 DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2799 DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2800 DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2801 DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2802 /** @sa TMR3TimerSkip */
2803 DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2804 /** @} */
2805
2806 /**
2807 * Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2808 *
2809 * @returns pTime.
2810 * @param pDevIns The device instance.
2811 * @param pTime Where to store the time.
2812 */
2813 DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2814
2815 /** @name Exported CFGM Functions.
2816 * @{ */
2817 DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2818 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2819 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char *pszName, size_t *pcb));
2820 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64));
2821 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64, uint64_t u64Def));
2822 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char *pszName, char *pszString, size_t cchString));
2823 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char *pszName, char *pszString, size_t cchString, const char *pszDef));
2824 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char *pszName, void *pvData, size_t cbData));
2825 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64));
2826 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64, uint64_t u64Def));
2827 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char *pszName, int64_t *pi64));
2828 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char *pszName, int64_t *pi64, int64_t i64Def));
2829 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char *pszName, uint32_t *pu32));
2830 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char *pszName, uint32_t *pu32, uint32_t u32Def));
2831 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char *pszName, int32_t *pi32));
2832 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char *pszName, int32_t *pi32, int32_t i32Def));
2833 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char *pszName, uint16_t *pu16));
2834 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char *pszName, uint16_t *pu16, uint16_t u16Def));
2835 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char *pszName, int16_t *pi16));
2836 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char *pszName, int16_t *pi16, int16_t i16Def));
2837 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char *pszName, uint8_t *pu8));
2838 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char *pszName, uint8_t *pu8, uint8_t u8Def));
2839 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char *pszName, int8_t *pi8));
2840 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char *pszName, int8_t *pi8, int8_t i8Def));
2841 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char *pszName, bool *pf));
2842 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char *pszName, bool *pf, bool fDef));
2843 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2844 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2845 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char *pszName, unsigned int *pu));
2846 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char *pszName, unsigned int *pu, unsigned int uDef));
2847 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char *pszName, signed int *pi));
2848 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char *pszName, signed int *pi, signed int iDef));
2849 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char *pszName, void **ppv));
2850 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char *pszName, void **ppv, void *pvDef));
2851 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
2852 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
2853 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
2854 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
2855 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
2856 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
2857 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char *pszName, char **ppszString));
2858 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char *pszName, char **ppszString, const char *pszDef));
2859 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
2860 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
2861 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
2862 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
2863 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
2864 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
2865 DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
2866 DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
2867 DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
2868 DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
2869 DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
2870 DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
2871 DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
2872 DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
2873 DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
2874 DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
2875 const char *pszValidValues, const char *pszValidNodes,
2876 const char *pszWho, uint32_t uInstance));
2877 /** @} */
2878
2879 /**
2880 * Read physical memory.
2881 *
2882 * @returns VINF_SUCCESS (for now).
2883 * @param pDevIns The device instance.
2884 * @param GCPhys Physical address start reading from.
2885 * @param pvBuf Where to put the read bits.
2886 * @param cbRead How many bytes to read.
2887 * @thread Any thread, but the call may involve the emulation thread.
2888 */
2889 DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
2890
2891 /**
2892 * Write to physical memory.
2893 *
2894 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
2895 * @param pDevIns The device instance.
2896 * @param GCPhys Physical address to write to.
2897 * @param pvBuf What to write.
2898 * @param cbWrite How many bytes to write.
2899 * @thread Any thread, but the call may involve the emulation thread.
2900 */
2901 DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
2902
2903 /**
2904 * Requests the mapping of a guest page into ring-3.
2905 *
2906 * When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2907 * release it.
2908 *
2909 * This API will assume your intention is to write to the page, and will
2910 * therefore replace shared and zero pages. If you do not intend to modify the
2911 * page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
2912 *
2913 * @returns VBox status code.
2914 * @retval VINF_SUCCESS on success.
2915 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2916 * backing or if the page has any active access handlers. The caller
2917 * must fall back on using PGMR3PhysWriteExternal.
2918 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2919 *
2920 * @param pDevIns The device instance.
2921 * @param GCPhys The guest physical address of the page that
2922 * should be mapped.
2923 * @param fFlags Flags reserved for future use, MBZ.
2924 * @param ppv Where to store the address corresponding to
2925 * GCPhys.
2926 * @param pLock Where to store the lock information that
2927 * pfnPhysReleasePageMappingLock needs.
2928 *
2929 * @remark Avoid calling this API from within critical sections (other than the
2930 * PGM one) because of the deadlock risk when we have to delegating the
2931 * task to an EMT.
2932 * @thread Any.
2933 */
2934 DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
2935 PPGMPAGEMAPLOCK pLock));
2936
2937 /**
2938 * Requests the mapping of a guest page into ring-3, external threads.
2939 *
2940 * When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2941 * release it.
2942 *
2943 * @returns VBox status code.
2944 * @retval VINF_SUCCESS on success.
2945 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2946 * backing or if the page as an active ALL access handler. The caller
2947 * must fall back on using PGMPhysRead.
2948 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2949 *
2950 * @param pDevIns The device instance.
2951 * @param GCPhys The guest physical address of the page that
2952 * should be mapped.
2953 * @param fFlags Flags reserved for future use, MBZ.
2954 * @param ppv Where to store the address corresponding to
2955 * GCPhys.
2956 * @param pLock Where to store the lock information that
2957 * pfnPhysReleasePageMappingLock needs.
2958 *
2959 * @remark Avoid calling this API from within critical sections.
2960 * @thread Any.
2961 */
2962 DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
2963 void const **ppv, PPGMPAGEMAPLOCK pLock));
2964
2965 /**
2966 * Release the mapping of a guest page.
2967 *
2968 * This is the counter part of pfnPhysGCPhys2CCPtr and
2969 * pfnPhysGCPhys2CCPtrReadOnly.
2970 *
2971 * @param pDevIns The device instance.
2972 * @param pLock The lock structure initialized by the mapping
2973 * function.
2974 */
2975 DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
2976
2977 /**
2978 * Read guest physical memory by virtual address.
2979 *
2980 * @param pDevIns The device instance.
2981 * @param pvDst Where to put the read bits.
2982 * @param GCVirtSrc Guest virtual address to start reading from.
2983 * @param cb How many bytes to read.
2984 * @thread The emulation thread.
2985 */
2986 DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
2987
2988 /**
2989 * Write to guest physical memory by virtual address.
2990 *
2991 * @param pDevIns The device instance.
2992 * @param GCVirtDst Guest virtual address to write to.
2993 * @param pvSrc What to write.
2994 * @param cb How many bytes to write.
2995 * @thread The emulation thread.
2996 */
2997 DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
2998
2999 /**
3000 * Convert a guest virtual address to a guest physical address.
3001 *
3002 * @returns VBox status code.
3003 * @param pDevIns The device instance.
3004 * @param GCPtr Guest virtual address.
3005 * @param pGCPhys Where to store the GC physical address
3006 * corresponding to GCPtr.
3007 * @thread The emulation thread.
3008 * @remark Careful with page boundaries.
3009 */
3010 DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3011
3012 /**
3013 * Allocate memory which is associated with current VM instance
3014 * and automatically freed on it's destruction.
3015 *
3016 * @returns Pointer to allocated memory. The memory is *NOT* zero-ed.
3017 * @param pDevIns The device instance.
3018 * @param cb Number of bytes to allocate.
3019 */
3020 DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3021
3022 /**
3023 * Allocate memory which is associated with current VM instance
3024 * and automatically freed on it's destruction. The memory is ZEROed.
3025 *
3026 * @returns Pointer to allocated memory. The memory is *NOT* zero-ed.
3027 * @param pDevIns The device instance.
3028 * @param cb Number of bytes to allocate.
3029 */
3030 DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3031
3032 /**
3033 * Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3034 *
3035 * @param pDevIns The device instance.
3036 * @param pv Pointer to the memory to free.
3037 */
3038 DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3039
3040 /**
3041 * Gets the VM state.
3042 *
3043 * @returns VM state.
3044 * @param pDevIns The device instance.
3045 * @thread Any thread (just keep in mind that it's volatile info).
3046 */
3047 DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3048
3049 /**
3050 * Checks if the VM was teleported and hasn't been fully resumed yet.
3051 *
3052 * @returns true / false.
3053 * @param pDevIns The device instance.
3054 * @thread Any thread.
3055 */
3056 DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3057
3058 /**
3059 * Set the VM error message
3060 *
3061 * @returns rc.
3062 * @param pDevIns The device instance.
3063 * @param rc VBox status code.
3064 * @param SRC_POS Use RT_SRC_POS.
3065 * @param pszFormat Error message format string.
3066 * @param ... Error message arguments.
3067 */
3068 DECLR3CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3069 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
3070
3071 /**
3072 * Set the VM error message
3073 *
3074 * @returns rc.
3075 * @param pDevIns The device instance.
3076 * @param rc VBox status code.
3077 * @param SRC_POS Use RT_SRC_POS.
3078 * @param pszFormat Error message format string.
3079 * @param va Error message arguments.
3080 */
3081 DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3082 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3083
3084 /**
3085 * Set the VM runtime error message
3086 *
3087 * @returns VBox status code.
3088 * @param pDevIns The device instance.
3089 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3090 * @param pszErrorId Error ID string.
3091 * @param pszFormat Error message format string.
3092 * @param ... Error message arguments.
3093 */
3094 DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3095 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
3096
3097 /**
3098 * Set the VM runtime error message
3099 *
3100 * @returns VBox status code.
3101 * @param pDevIns The device instance.
3102 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3103 * @param pszErrorId Error ID string.
3104 * @param pszFormat Error message format string.
3105 * @param va Error message arguments.
3106 */
3107 DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3108 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3109
3110 /**
3111 * Stops the VM and enters the debugger to look at the guest state.
3112 *
3113 * Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3114 * invoking this function directly.
3115 *
3116 * @returns VBox status code which must be passed up to the VMM.
3117 * @param pDevIns The device instance.
3118 * @param pszFile Filename of the assertion location.
3119 * @param iLine The linenumber of the assertion location.
3120 * @param pszFunction Function of the assertion location.
3121 * @param pszFormat Message. (optional)
3122 * @param args Message parameters.
3123 */
3124 DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction,
3125 const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3126
3127 /**
3128 * Register a info handler with DBGF.
3129 *
3130 * @returns VBox status code.
3131 * @param pDevIns The device instance.
3132 * @param pszName The identifier of the info.
3133 * @param pszDesc The description of the info and any arguments
3134 * the handler may take.
3135 * @param pfnHandler The handler function to be called to display the
3136 * info.
3137 */
3138 DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3139
3140 /**
3141 * Register a info handler with DBGF, argv style.
3142 *
3143 * @returns VBox status code.
3144 * @param pDevIns The device instance.
3145 * @param pszName The identifier of the info.
3146 * @param pszDesc The description of the info and any arguments
3147 * the handler may take.
3148 * @param pfnHandler The handler function to be called to display the
3149 * info.
3150 */
3151 DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3152
3153 /**
3154 * Registers a set of registers for a device.
3155 *
3156 * The @a pvUser argument of the getter and setter callbacks will be
3157 * @a pDevIns. The register names will be prefixed by the device name followed
3158 * immediately by the instance number.
3159 *
3160 * @returns VBox status code.
3161 * @param pDevIns The device instance.
3162 * @param paRegisters The register descriptors.
3163 *
3164 * @remarks The device critical section is NOT entered prior to working the
3165 * callbacks registered via this helper!
3166 */
3167 DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3168
3169 /**
3170 * Gets the trace buffer handle.
3171 *
3172 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3173 * really inteded for direct usage, thus no inline wrapper function.
3174 *
3175 * @returns Trace buffer handle or NIL_RTTRACEBUF.
3176 * @param pDevIns The device instance.
3177 */
3178 DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3179
3180 /**
3181 * Registers a statistics sample.
3182 *
3183 * @param pDevIns Device instance of the DMA.
3184 * @param pvSample Pointer to the sample.
3185 * @param enmType Sample type. This indicates what pvSample is
3186 * pointing at.
3187 * @param pszName Sample name, unix path style. If this does not
3188 * start with a '/', the default prefix will be
3189 * prepended, otherwise it will be used as-is.
3190 * @param enmUnit Sample unit.
3191 * @param pszDesc Sample description.
3192 */
3193 DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc));
3194
3195 /**
3196 * Same as pfnSTAMRegister except that the name is specified in a
3197 * RTStrPrintfV like fashion.
3198 *
3199 * @returns VBox status.
3200 * @param pDevIns Device instance of the DMA.
3201 * @param pvSample Pointer to the sample.
3202 * @param enmType Sample type. This indicates what pvSample is
3203 * pointing at.
3204 * @param enmVisibility Visibility type specifying whether unused
3205 * statistics should be visible or not.
3206 * @param enmUnit Sample unit.
3207 * @param pszDesc Sample description.
3208 * @param pszName Sample name format string, unix path style. If
3209 * this does not start with a '/', the default
3210 * prefix will be prepended, otherwise it will be
3211 * used as-is.
3212 * @param args Arguments to the format string.
3213 */
3214 DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3215 STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3216 const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3217
3218 /**
3219 * Registers a PCI device with the default PCI bus.
3220 *
3221 * If a PDM device has more than one PCI device, they must be registered in the
3222 * order of PDMDEVINSR3::apPciDevs.
3223 *
3224 * @returns VBox status code.
3225 * @param pDevIns The device instance.
3226 * @param pPciDev The PCI device structure.
3227 * This must be kept in the instance data.
3228 * The PCI configuration must be initialized before registration.
3229 * @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
3230 * @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3231 * PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3232 * device number (0-31). This will be ignored if
3233 * the CFGM configuration contains a PCIDeviceNo
3234 * value.
3235 * @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3236 * function number (0-7). This will be ignored if
3237 * the CFGM configuration contains a PCIFunctionNo
3238 * value.
3239 * @param pszName Device name, if NULL PDMDEVREG::szName is used.
3240 * The pointer is saved, so don't free or changed.
3241 * @note The PCI device configuration is now implicit from the apPciDevs
3242 * index, meaning that the zero'th entry is the primary one and
3243 * subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3244 */
3245 DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3246 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3247
3248 /**
3249 * Initialize MSI or MSI-X emulation support for the given PCI device.
3250 *
3251 * @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3252 *
3253 * @returns VBox status code.
3254 * @param pDevIns The device instance.
3255 * @param pPciDev The PCI device. NULL is an alias for the first
3256 * one registered.
3257 * @param pMsiReg MSI emulation registration structure.
3258 */
3259 DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3260
3261 /**
3262 * Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3263 *
3264 * @returns VBox status code.
3265 * @param pDevIns The device instance.
3266 * @param pPciDev The PCI device structure. If NULL the default
3267 * PCI device for this device instance is used.
3268 * @param iRegion The region number.
3269 * @param cbRegion Size of the region.
3270 * @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3271 * @param fFlags PDMPCIDEV_IORGN_F_XXX.
3272 * @param hHandle An I/O port, MMIO or MMIO2 handle according to
3273 * @a fFlags, UINT64_MAX if no handle is passed
3274 * (old style).
3275 * @param pfnMapUnmap Callback for doing the mapping, optional when a
3276 * handle is specified. The callback will be
3277 * invoked holding only the PDM lock. The device
3278 * lock will _not_ be taken (due to lock order).
3279 */
3280 DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3281 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3282 uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3283
3284 /**
3285 * Register PCI configuration space read/write callbacks.
3286 *
3287 * @returns VBox status code.
3288 * @param pDevIns The device instance.
3289 * @param pPciDev The PCI device structure. If NULL the default
3290 * PCI device for this device instance is used.
3291 * @param pfnRead Pointer to the user defined PCI config read function.
3292 * to call default PCI config read function. Can be NULL.
3293 * @param pfnWrite Pointer to the user defined PCI config write function.
3294 * @remarks The callbacks will be invoked holding the PDM lock. The device lock
3295 * is NOT take because that is very likely be a lock order violation.
3296 * @thread EMT(0)
3297 * @note Only callable during VM creation.
3298 * @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3299 */
3300 DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3301 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3302
3303 /**
3304 * Perform a PCI configuration space write.
3305 *
3306 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3307 *
3308 * @returns Strict VBox status code (mainly DBGFSTOP).
3309 * @param pDevIns The device instance.
3310 * @param pPciDev The PCI device which config space is being read.
3311 * @param uAddress The config space address.
3312 * @param cb The size of the read: 1, 2 or 4 bytes.
3313 * @param u32Value The value to write.
3314 */
3315 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3316 uint32_t uAddress, unsigned cb, uint32_t u32Value));
3317
3318 /**
3319 * Perform a PCI configuration space read.
3320 *
3321 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3322 *
3323 * @returns Strict VBox status code (mainly DBGFSTOP).
3324 * @param pDevIns The device instance.
3325 * @param pPciDev The PCI device which config space is being read.
3326 * @param uAddress The config space address.
3327 * @param cb The size of the read: 1, 2 or 4 bytes.
3328 * @param pu32Value Where to return the value.
3329 */
3330 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3331 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3332
3333 /**
3334 * Bus master physical memory read.
3335 *
3336 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3337 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
3338 * @param pDevIns The device instance.
3339 * @param pPciDev The PCI device structure. If NULL the default
3340 * PCI device for this device instance is used.
3341 * @param GCPhys Physical address start reading from.
3342 * @param pvBuf Where to put the read bits.
3343 * @param cbRead How many bytes to read.
3344 * @thread Any thread, but the call may involve the emulation thread.
3345 */
3346 DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
3347
3348 /**
3349 * Bus master physical memory write.
3350 *
3351 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3352 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
3353 * @param pDevIns The device instance.
3354 * @param pPciDev The PCI device structure. If NULL the default
3355 * PCI device for this device instance is used.
3356 * @param GCPhys Physical address to write to.
3357 * @param pvBuf What to write.
3358 * @param cbWrite How many bytes to write.
3359 * @thread Any thread, but the call may involve the emulation thread.
3360 */
3361 DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
3362
3363 /**
3364 * Sets the IRQ for the given PCI device.
3365 *
3366 * @param pDevIns The device instance.
3367 * @param pPciDev The PCI device structure. If NULL the default
3368 * PCI device for this device instance is used.
3369 * @param iIrq IRQ number to set.
3370 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3371 * @thread Any thread, but will involve the emulation thread.
3372 */
3373 DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3374
3375 /**
3376 * Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3377 * the request when not called from EMT.
3378 *
3379 * @param pDevIns The device instance.
3380 * @param pPciDev The PCI device structure. If NULL the default
3381 * PCI device for this device instance is used.
3382 * @param iIrq IRQ number to set.
3383 * @param iLevel IRQ level.
3384 * @thread Any thread, but will involve the emulation thread.
3385 */
3386 DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3387
3388 /**
3389 * Set ISA IRQ for a device.
3390 *
3391 * @param pDevIns The device instance.
3392 * @param iIrq IRQ number to set.
3393 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3394 * @thread Any thread, but will involve the emulation thread.
3395 */
3396 DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3397
3398 /**
3399 * Set the ISA IRQ for a device, but don't wait for EMT to process
3400 * the request when not called from EMT.
3401 *
3402 * @param pDevIns The device instance.
3403 * @param iIrq IRQ number to set.
3404 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3405 * @thread Any thread, but will involve the emulation thread.
3406 */
3407 DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3408
3409 /**
3410 * Send an MSI straight to the I/O APIC.
3411 *
3412 * @param pDevIns PCI device instance.
3413 * @param GCPhys Physical address MSI request was written.
3414 * @param uValue Value written.
3415 * @thread Any thread, but will involve the emulation thread.
3416 */
3417 DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
3418
3419 /**
3420 * Attaches a driver (chain) to the device.
3421 *
3422 * The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3423 * the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3424 *
3425 * @returns VBox status code.
3426 * @param pDevIns The device instance.
3427 * @param iLun The logical unit to attach.
3428 * @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3429 * @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3430 * @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3431 * for the live of the device instance.
3432 */
3433 DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3434 PPDMIBASE *ppBaseInterface, const char *pszDesc));
3435
3436 /**
3437 * Detaches an attached driver (chain) from the device again.
3438 *
3439 * @returns VBox status code.
3440 * @param pDevIns The device instance.
3441 * @param pDrvIns The driver instance to detach.
3442 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3443 */
3444 DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3445
3446 /**
3447 * Reconfigures the driver chain for a LUN, detaching any driver currently
3448 * present there.
3449 *
3450 * Caller will have attach it, of course.
3451 *
3452 * @returns VBox status code.
3453 * @param pDevIns The device instance.
3454 * @param iLun The logical unit to reconfigure.
3455 * @param cDepth The depth of the driver chain. Determins the
3456 * size of @a papszDrivers and @a papConfigs.
3457 * @param papszDrivers The names of the drivers to configure in the
3458 * chain, first entry is the one immediately
3459 * below the device/LUN
3460 * @param papConfigs The configurations for each of the drivers
3461 * in @a papszDrivers array. NULL entries
3462 * corresponds to empty 'Config' nodes. This
3463 * function will take ownership of non-NULL
3464 * CFGM sub-trees and set the array member to
3465 * NULL, so the caller can do cleanups on
3466 * failure. This parameter is optional.
3467 * @param fFlags Reserved, MBZ.
3468 */
3469 DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3470 const char * const *papszDrivers, PCFGMNODE *papConfigs, uint32_t fFlags));
3471
3472 /** @name Exported PDM Queue Functions
3473 * @{ */
3474 /**
3475 * Create a queue.
3476 *
3477 * @returns VBox status code.
3478 * @param pDevIns The device instance.
3479 * @param cbItem The size of a queue item.
3480 * @param cItems The number of items in the queue.
3481 * @param cMilliesInterval The number of milliseconds between polling the queue.
3482 * If 0 then the emulation thread will be notified whenever an item arrives.
3483 * @param pfnCallback The consumer function.
3484 * @param fRZEnabled Set if the queue should work in RC and R0.
3485 * @param pszName The queue base name. The instance number will be
3486 * appended automatically.
3487 * @param ppQueue Where to store the queue pointer on success.
3488 * @thread The emulation thread.
3489 * @remarks The device critical section will NOT be entered before calling the
3490 * callback. No locks will be held, but for now it's safe to assume
3491 * that only one EMT will do queue callbacks at any one time.
3492 */
3493 DECLR3CALLBACKMEMBER(int, pfnQueueCreatePtr,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3494 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3495 PPDMQUEUE *ppQueue));
3496
3497 /**
3498 * Create a queue.
3499 *
3500 * @returns VBox status code.
3501 * @param pDevIns The device instance.
3502 * @param cbItem The size of a queue item.
3503 * @param cItems The number of items in the queue.
3504 * @param cMilliesInterval The number of milliseconds between polling the queue.
3505 * If 0 then the emulation thread will be notified whenever an item arrives.
3506 * @param pfnCallback The consumer function.
3507 * @param fRZEnabled Set if the queue should work in RC and R0.
3508 * @param pszName The queue base name. The instance number will be
3509 * appended automatically.
3510 * @param phQueue Where to store the queue handle on success.
3511 * @thread EMT(0)
3512 * @remarks The device critical section will NOT be entered before calling the
3513 * callback. No locks will be held, but for now it's safe to assume
3514 * that only one EMT will do queue callbacks at any one time.
3515 */
3516 DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3517 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3518 PDMQUEUEHANDLE *phQueue));
3519
3520 DECLR3CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3521 DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3522 DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3523 DECLR3CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
3524 DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3525 /** @} */
3526
3527 /** @name PDM Task
3528 * @{ */
3529 /**
3530 * Create an asynchronous ring-3 task.
3531 *
3532 * @returns VBox status code.
3533 * @param pDevIns The device instance.
3534 * @param fFlags PDMTASK_F_XXX
3535 * @param pszName The function name or similar. Used for statistics,
3536 * so no slashes.
3537 * @param pfnCallback The task function.
3538 * @param pvUser User argument for the task function.
3539 * @param phTask Where to return the task handle.
3540 * @thread EMT(0)
3541 */
3542 DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3543 PFNPDMTASKDEV pfnCallback, void *pvUser, PDMTASKHANDLE *phTask));
3544 /**
3545 * Triggers the running the given task.
3546 *
3547 * @returns VBox status code.
3548 * @retval VINF_ALREADY_POSTED is the task is already pending.
3549 * @param pDevIns The device instance.
3550 * @param hTask The task to trigger.
3551 * @thread Any thread.
3552 */
3553 DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3554 /** @} */
3555
3556 /** @name SUP Event Semaphore Wrappers (single release / auto reset)
3557 * These semaphores can be signalled from ring-0.
3558 * @{ */
3559 /** @sa SUPSemEventCreate */
3560 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3561 /** @sa SUPSemEventClose */
3562 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3563 /** @sa SUPSemEventSignal */
3564 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3565 /** @sa SUPSemEventWaitNoResume */
3566 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3567 /** @sa SUPSemEventWaitNsAbsIntr */
3568 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3569 /** @sa SUPSemEventWaitNsRelIntr */
3570 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3571 /** @sa SUPSemEventGetResolution */
3572 DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3573 /** @} */
3574
3575 /** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3576 * These semaphores can be signalled from ring-0.
3577 * @{ */
3578 /** @sa SUPSemEventMultiCreate */
3579 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3580 /** @sa SUPSemEventMultiClose */
3581 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3582 /** @sa SUPSemEventMultiSignal */
3583 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3584 /** @sa SUPSemEventMultiReset */
3585 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3586 /** @sa SUPSemEventMultiWaitNoResume */
3587 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3588 /** @sa SUPSemEventMultiWaitNsAbsIntr */
3589 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3590 /** @sa SUPSemEventMultiWaitNsRelIntr */
3591 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3592 /** @sa SUPSemEventMultiGetResolution */
3593 DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3594 /** @} */
3595
3596 /**
3597 * Initializes a PDM critical section.
3598 *
3599 * The PDM critical sections are derived from the IPRT critical sections, but
3600 * works in RC and R0 as well.
3601 *
3602 * @returns VBox status code.
3603 * @param pDevIns The device instance.
3604 * @param pCritSect Pointer to the critical section.
3605 * @param SRC_POS Use RT_SRC_POS.
3606 * @param pszNameFmt Format string for naming the critical section.
3607 * For statistics and lock validation.
3608 * @param va Arguments for the format string.
3609 */
3610 DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3611 const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3612
3613 /**
3614 * Gets the NOP critical section.
3615 *
3616 * @returns The ring-3 address of the NOP critical section.
3617 * @param pDevIns The device instance.
3618 */
3619 DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3620
3621 /**
3622 * Gets the NOP critical section.
3623 *
3624 * @returns The ring-0 address of the NOP critical section.
3625 * @param pDevIns The device instance.
3626 * @deprecated
3627 */
3628 DECLR3CALLBACKMEMBER(R0PTRTYPE(PPDMCRITSECT), pfnCritSectGetNopR0,(PPDMDEVINS pDevIns));
3629
3630 /**
3631 * Gets the NOP critical section.
3632 *
3633 * @returns The raw-mode context address of the NOP critical section.
3634 * @param pDevIns The device instance.
3635 * @deprecated
3636 */
3637 DECLR3CALLBACKMEMBER(RCPTRTYPE(PPDMCRITSECT), pfnCritSectGetNopRC,(PPDMDEVINS pDevIns));
3638
3639 /**
3640 * Changes the device level critical section from the automatically created
3641 * default to one desired by the device constructor.
3642 *
3643 * For ring-0 and raw-mode capable devices, the call must be repeated in each of
3644 * the additional contexts.
3645 *
3646 * @returns VBox status code.
3647 * @param pDevIns The device instance.
3648 * @param pCritSect The critical section to use. NULL is not
3649 * valid, instead use the NOP critical
3650 * section.
3651 */
3652 DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3653
3654 /** @name Exported PDM Critical Section Functions
3655 * @{ */
3656 DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3657 DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3658 DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3659 DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3660 DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3661 DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3662 DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3663 DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3664 DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3665 DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3666 DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3667 DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3668 /** @} */
3669
3670 /**
3671 * Creates a PDM thread.
3672 *
3673 * This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3674 * resuming, and destroying the thread as the VM state changes.
3675 *
3676 * @returns VBox status code.
3677 * @param pDevIns The device instance.
3678 * @param ppThread Where to store the thread 'handle'.
3679 * @param pvUser The user argument to the thread function.
3680 * @param pfnThread The thread function.
3681 * @param pfnWakeup The wakup callback. This is called on the EMT
3682 * thread when a state change is pending.
3683 * @param cbStack See RTThreadCreate.
3684 * @param enmType See RTThreadCreate.
3685 * @param pszName See RTThreadCreate.
3686 * @remarks The device critical section will NOT be entered prior to invoking
3687 * the function pointers.
3688 */
3689 DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3690 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3691
3692 /** @name Exported PDM Thread Functions
3693 * @{ */
3694 DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3695 DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3696 DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3697 DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3698 DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3699 DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3700 /** @} */
3701
3702 /**
3703 * Set up asynchronous handling of a suspend, reset or power off notification.
3704 *
3705 * This shall only be called when getting the notification. It must be called
3706 * for each one.
3707 *
3708 * @returns VBox status code.
3709 * @param pDevIns The device instance.
3710 * @param pfnAsyncNotify The callback.
3711 * @thread EMT(0)
3712 * @remarks The caller will enter the device critical section prior to invoking
3713 * the callback.
3714 */
3715 DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3716
3717 /**
3718 * Notify EMT(0) that the device has completed the asynchronous notification
3719 * handling.
3720 *
3721 * This can be called at any time, spurious calls will simply be ignored.
3722 *
3723 * @param pDevIns The device instance.
3724 * @thread Any
3725 */
3726 DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
3727
3728 /**
3729 * Register the RTC device.
3730 *
3731 * @returns VBox status code.
3732 * @param pDevIns The device instance.
3733 * @param pRtcReg Pointer to a RTC registration structure.
3734 * @param ppRtcHlp Where to store the pointer to the helper
3735 * functions.
3736 */
3737 DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
3738
3739 /**
3740 * Register a PCI Bus.
3741 *
3742 * @returns VBox status code, but the positive values 0..31 are used to indicate
3743 * bus number rather than informational status codes.
3744 * @param pDevIns The device instance.
3745 * @param pPciBusReg Pointer to PCI bus registration structure.
3746 * @param ppPciHlp Where to store the pointer to the PCI Bus
3747 * helpers.
3748 * @param piBus Where to return the PDM bus number. Optional.
3749 */
3750 DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
3751 PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus));
3752
3753 /**
3754 * Register the PIC device.
3755 *
3756 * @returns VBox status code.
3757 * @param pDevIns The device instance.
3758 * @param pPicReg Pointer to a PIC registration structure.
3759 * @param ppPicHlp Where to store the pointer to the ring-3 PIC
3760 * helpers.
3761 * @sa PDMDevHlpPICSetUpContext
3762 */
3763 DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
3764
3765 /**
3766 * Register the APIC device.
3767 *
3768 * @returns VBox status code.
3769 * @param pDevIns The device instance.
3770 */
3771 DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
3772
3773 /**
3774 * Register the I/O APIC device.
3775 *
3776 * @returns VBox status code.
3777 * @param pDevIns The device instance.
3778 * @param pIoApicReg Pointer to a I/O APIC registration structure.
3779 * @param ppIoApicHlp Where to store the pointer to the IOAPIC
3780 * helpers.
3781 */
3782 DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
3783
3784 /**
3785 * Register the HPET device.
3786 *
3787 * @returns VBox status code.
3788 * @param pDevIns The device instance.
3789 * @param pHpetReg Pointer to a HPET registration structure.
3790 * @param ppHpetHlpR3 Where to store the pointer to the HPET
3791 * helpers.
3792 */
3793 DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
3794
3795 /**
3796 * Register a raw PCI device.
3797 *
3798 * @returns VBox status code.
3799 * @param pDevIns The device instance.
3800 * @param pPciRawReg Pointer to a raw PCI registration structure.
3801 * @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
3802 * device helpers.
3803 */
3804 DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
3805
3806 /**
3807 * Register the DMA device.
3808 *
3809 * @returns VBox status code.
3810 * @param pDevIns The device instance.
3811 * @param pDmacReg Pointer to a DMAC registration structure.
3812 * @param ppDmacHlp Where to store the pointer to the DMA helpers.
3813 */
3814 DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
3815
3816 /**
3817 * Register transfer function for DMA channel.
3818 *
3819 * @returns VBox status code.
3820 * @param pDevIns The device instance.
3821 * @param uChannel Channel number.
3822 * @param pfnTransferHandler Device specific transfer callback function.
3823 * @param pvUser User pointer to pass to the callback.
3824 * @thread EMT
3825 */
3826 DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
3827
3828 /**
3829 * Read memory.
3830 *
3831 * @returns VBox status code.
3832 * @param pDevIns The device instance.
3833 * @param uChannel Channel number.
3834 * @param pvBuffer Pointer to target buffer.
3835 * @param off DMA position.
3836 * @param cbBlock Block size.
3837 * @param pcbRead Where to store the number of bytes which was
3838 * read. optional.
3839 * @thread EMT
3840 */
3841 DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead));
3842
3843 /**
3844 * Write memory.
3845 *
3846 * @returns VBox status code.
3847 * @param pDevIns The device instance.
3848 * @param uChannel Channel number.
3849 * @param pvBuffer Memory to write.
3850 * @param off DMA position.
3851 * @param cbBlock Block size.
3852 * @param pcbWritten Where to store the number of bytes which was
3853 * written. optional.
3854 * @thread EMT
3855 */
3856 DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten));
3857
3858 /**
3859 * Set the DREQ line.
3860 *
3861 * @returns VBox status code.
3862 * @param pDevIns Device instance.
3863 * @param uChannel Channel number.
3864 * @param uLevel Level of the line.
3865 * @thread EMT
3866 */
3867 DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
3868
3869 /**
3870 * Get channel mode.
3871 *
3872 * @returns Channel mode. See specs.
3873 * @param pDevIns The device instance.
3874 * @param uChannel Channel number.
3875 * @thread EMT
3876 */
3877 DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
3878
3879 /**
3880 * Schedule DMA execution.
3881 *
3882 * @param pDevIns The device instance.
3883 * @thread Any thread.
3884 */
3885 DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
3886
3887 /**
3888 * Write CMOS value and update the checksum(s).
3889 *
3890 * @returns VBox status code.
3891 * @param pDevIns The device instance.
3892 * @param iReg The CMOS register index.
3893 * @param u8Value The CMOS register value.
3894 * @thread EMT
3895 */
3896 DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
3897
3898 /**
3899 * Read CMOS value.
3900 *
3901 * @returns VBox status code.
3902 * @param pDevIns The device instance.
3903 * @param iReg The CMOS register index.
3904 * @param pu8Value Where to store the CMOS register value.
3905 * @thread EMT
3906 */
3907 DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
3908
3909 /**
3910 * Assert that the current thread is the emulation thread.
3911 *
3912 * @returns True if correct.
3913 * @returns False if wrong.
3914 * @param pDevIns The device instance.
3915 * @param pszFile Filename of the assertion location.
3916 * @param iLine The linenumber of the assertion location.
3917 * @param pszFunction Function of the assertion location.
3918 */
3919 DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction));
3920
3921 /**
3922 * Assert that the current thread is NOT the emulation thread.
3923 *
3924 * @returns True if correct.
3925 * @returns False if wrong.
3926 * @param pDevIns The device instance.
3927 * @param pszFile Filename of the assertion location.
3928 * @param iLine The linenumber of the assertion location.
3929 * @param pszFunction Function of the assertion location.
3930 */
3931 DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction));
3932
3933 /**
3934 * Resolves the symbol for a raw-mode context interface.
3935 *
3936 * @returns VBox status code.
3937 * @param pDevIns The device instance.
3938 * @param pvInterface The interface structure.
3939 * @param cbInterface The size of the interface structure.
3940 * @param pszSymPrefix What to prefix the symbols in the list with
3941 * before resolving them. This must start with
3942 * 'dev' and contain the driver name.
3943 * @param pszSymList List of symbols corresponding to the interface.
3944 * There is generally a there is generally a define
3945 * holding this list associated with the interface
3946 * definition (INTERFACE_SYM_LIST). For more
3947 * details see PDMR3LdrGetInterfaceSymbols.
3948 * @thread EMT
3949 */
3950 DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
3951 const char *pszSymPrefix, const char *pszSymList));
3952
3953 /**
3954 * Resolves the symbol for a ring-0 context interface.
3955 *
3956 * @returns VBox status code.
3957 * @param pDevIns The device instance.
3958 * @param pvInterface The interface structure.
3959 * @param cbInterface The size of the interface structure.
3960 * @param pszSymPrefix What to prefix the symbols in the list with
3961 * before resolving them. This must start with
3962 * 'dev' and contain the driver name.
3963 * @param pszSymList List of symbols corresponding to the interface.
3964 * There is generally a there is generally a define
3965 * holding this list associated with the interface
3966 * definition (INTERFACE_SYM_LIST). For more
3967 * details see PDMR3LdrGetInterfaceSymbols.
3968 * @thread EMT
3969 */
3970 DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
3971 const char *pszSymPrefix, const char *pszSymList));
3972
3973 /**
3974 * Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
3975 *
3976 * @returns VBox status code.
3977 * @retval VERR_INVALID_FUNCTION if the callback member is NULL.
3978 * @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
3979 *
3980 * @param pDevIns The device instance.
3981 * @param uOperation The operation to perform.
3982 * @param u64Arg 64-bit integer argument.
3983 * @thread EMT
3984 */
3985 DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
3986
3987 /**
3988 * Gets the reason for the most recent VM suspend.
3989 *
3990 * @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
3991 * suspend has been made or if the pDevIns is invalid.
3992 * @param pDevIns The device instance.
3993 */
3994 DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
3995
3996 /**
3997 * Gets the reason for the most recent VM resume.
3998 *
3999 * @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4000 * resume has been made or if the pDevIns is invalid.
4001 * @param pDevIns The device instance.
4002 */
4003 DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4004
4005 /**
4006 * Requests the mapping of multiple guest page into ring-3.
4007 *
4008 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4009 * ASAP to release them.
4010 *
4011 * This API will assume your intention is to write to the pages, and will
4012 * therefore replace shared and zero pages. If you do not intend to modify the
4013 * pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4014 *
4015 * @returns VBox status code.
4016 * @retval VINF_SUCCESS on success.
4017 * @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4018 * backing or if any of the pages the page has any active access
4019 * handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4020 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4021 * an invalid physical address.
4022 *
4023 * @param pDevIns The device instance.
4024 * @param cPages Number of pages to lock.
4025 * @param paGCPhysPages The guest physical address of the pages that
4026 * should be mapped (@a cPages entries).
4027 * @param fFlags Flags reserved for future use, MBZ.
4028 * @param papvPages Where to store the ring-3 mapping addresses
4029 * corresponding to @a paGCPhysPages.
4030 * @param paLocks Where to store the locking information that
4031 * pfnPhysBulkReleasePageMappingLock needs (@a cPages
4032 * in length).
4033 *
4034 * @remark Avoid calling this API from within critical sections (other than the
4035 * PGM one) because of the deadlock risk when we have to delegating the
4036 * task to an EMT.
4037 * @thread Any.
4038 * @since 6.0.6
4039 */
4040 DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4041 uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4042
4043 /**
4044 * Requests the mapping of multiple guest page into ring-3, for reading only.
4045 *
4046 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4047 * ASAP to release them.
4048 *
4049 * @returns VBox status code.
4050 * @retval VINF_SUCCESS on success.
4051 * @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4052 * backing or if any of the pages the page has an active ALL access
4053 * handler. The caller must fall back on using PGMR3PhysWriteExternal.
4054 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4055 * an invalid physical address.
4056 *
4057 * @param pDevIns The device instance.
4058 * @param cPages Number of pages to lock.
4059 * @param paGCPhysPages The guest physical address of the pages that
4060 * should be mapped (@a cPages entries).
4061 * @param fFlags Flags reserved for future use, MBZ.
4062 * @param papvPages Where to store the ring-3 mapping addresses
4063 * corresponding to @a paGCPhysPages.
4064 * @param paLocks Where to store the lock information that
4065 * pfnPhysReleasePageMappingLock needs (@a cPages
4066 * in length).
4067 *
4068 * @remark Avoid calling this API from within critical sections.
4069 * @thread Any.
4070 * @since 6.0.6
4071 */
4072 DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4073 uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4074
4075 /**
4076 * Release the mappings of multiple guest pages.
4077 *
4078 * This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4079 * pfnPhysBulkGCPhys2CCPtrReadOnly.
4080 *
4081 * @param pDevIns The device instance.
4082 * @param cPages Number of pages to unlock.
4083 * @param paLocks The lock structures initialized by the mapping
4084 * function (@a cPages in length).
4085 * @thread Any.
4086 * @since 6.0.6
4087 */
4088 DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4089
4090 /**
4091 * Changes the number of an MMIO2 or pre-registered MMIO region.
4092 *
4093 * This should only be used to deal with saved state problems, so there is no
4094 * convenience inline wrapper for this method.
4095 *
4096 * @returns VBox status code.
4097 * @param pDevIns The device instance.
4098 * @param pPciDev The PCI device the region is associated with, or
4099 * NULL if not associated with any.
4100 * @param iRegion The region.
4101 * @param iNewRegion The new region index.
4102 *
4103 * @sa @bugref{9359}
4104 */
4105 DECLR3CALLBACKMEMBER(int, pfnMMIOExChangeRegionNo,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4106 uint32_t iNewRegion));
4107
4108 /** Space reserved for future members.
4109 * @{ */
4110 DECLR3CALLBACKMEMBER(void, pfnReserved1,(void));
4111 DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4112 DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4113 DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4114 DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4115 DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4116 DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4117 DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4118 DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4119 DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4120 /** @} */
4121
4122
4123 /** API available to trusted devices only.
4124 *
4125 * These APIs are providing unrestricted access to the guest and the VM,
4126 * or they are interacting intimately with PDM.
4127 *
4128 * @{
4129 */
4130
4131 /**
4132 * Gets the user mode VM handle. Restricted API.
4133 *
4134 * @returns User mode VM Handle.
4135 * @param pDevIns The device instance.
4136 */
4137 DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4138
4139 /**
4140 * Gets the global VM handle. Restricted API.
4141 *
4142 * @returns VM Handle.
4143 * @param pDevIns The device instance.
4144 */
4145 DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4146
4147 /**
4148 * Gets the VMCPU handle. Restricted API.
4149 *
4150 * @returns VMCPU Handle.
4151 * @param pDevIns The device instance.
4152 */
4153 DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4154
4155 /**
4156 * The the VM CPU ID of the current thread (restricted API).
4157 *
4158 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4159 * @param pDevIns The device instance.
4160 */
4161 DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4162
4163 /**
4164 * Registers the VMM device heap or notifies about mapping/unmapping.
4165 *
4166 * This interface serves three purposes:
4167 *
4168 * -# Register the VMM device heap during device construction
4169 * for the HM to use.
4170 * -# Notify PDM/HM that it's mapped into guest address
4171 * space (i.e. usable).
4172 * -# Notify PDM/HM that it is being unmapped from the guest
4173 * address space (i.e. not usable).
4174 *
4175 * @returns VBox status code.
4176 * @param pDevIns The device instance.
4177 * @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4178 * not mapped.
4179 * @param pvHeap Ring 3 heap pointer.
4180 * @param cbHeap Size of the heap.
4181 * @thread EMT.
4182 */
4183 DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4184
4185 /**
4186 * Registers the firmware (BIOS, EFI) device with PDM.
4187 *
4188 * The firmware provides a callback table and gets a special PDM helper table.
4189 * There can only be one firmware device for a VM.
4190 *
4191 * @returns VBox status code.
4192 * @param pDevIns The device instance.
4193 * @param pFwReg Firmware registration structure.
4194 * @param ppFwHlp Where to return the firmware helper structure.
4195 * @remarks Only valid during device construction.
4196 * @thread EMT(0)
4197 */
4198 DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4199
4200 /**
4201 * Resets the VM.
4202 *
4203 * @returns The appropriate VBox status code to pass around on reset.
4204 * @param pDevIns The device instance.
4205 * @param fFlags PDMVMRESET_F_XXX flags.
4206 * @thread The emulation thread.
4207 */
4208 DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4209
4210 /**
4211 * Suspends the VM.
4212 *
4213 * @returns The appropriate VBox status code to pass around on suspend.
4214 * @param pDevIns The device instance.
4215 * @thread The emulation thread.
4216 */
4217 DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4218
4219 /**
4220 * Suspends, saves and powers off the VM.
4221 *
4222 * @returns The appropriate VBox status code to pass around.
4223 * @param pDevIns The device instance.
4224 * @thread An emulation thread.
4225 */
4226 DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4227
4228 /**
4229 * Power off the VM.
4230 *
4231 * @returns The appropriate VBox status code to pass around on power off.
4232 * @param pDevIns The device instance.
4233 * @thread The emulation thread.
4234 */
4235 DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4236
4237 /**
4238 * Checks if the Gate A20 is enabled or not.
4239 *
4240 * @returns true if A20 is enabled.
4241 * @returns false if A20 is disabled.
4242 * @param pDevIns The device instance.
4243 * @thread The emulation thread.
4244 */
4245 DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4246
4247 /**
4248 * Enables or disables the Gate A20.
4249 *
4250 * @param pDevIns The device instance.
4251 * @param fEnable Set this flag to enable the Gate A20; clear it
4252 * to disable.
4253 * @thread The emulation thread.
4254 */
4255 DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4256
4257 /**
4258 * Get the specified CPUID leaf for the virtual CPU associated with the calling
4259 * thread.
4260 *
4261 * @param pDevIns The device instance.
4262 * @param iLeaf The CPUID leaf to get.
4263 * @param pEax Where to store the EAX value.
4264 * @param pEbx Where to store the EBX value.
4265 * @param pEcx Where to store the ECX value.
4266 * @param pEdx Where to store the EDX value.
4267 * @thread EMT.
4268 */
4269 DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx));
4270
4271 /**
4272 * Get the current virtual clock time in a VM. The clock frequency must be
4273 * queried separately.
4274 *
4275 * @returns Current clock time.
4276 * @param pDevIns The device instance.
4277 */
4278 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4279
4280 /**
4281 * Get the frequency of the virtual clock.
4282 *
4283 * @returns The clock frequency (not variable at run-time).
4284 * @param pDevIns The device instance.
4285 */
4286 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4287
4288 /**
4289 * Get the current virtual clock time in a VM, in nanoseconds.
4290 *
4291 * @returns Current clock time (in ns).
4292 * @param pDevIns The device instance.
4293 */
4294 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4295
4296 /**
4297 * Gets the support driver session.
4298 *
4299 * This is intended for working with the semaphore API.
4300 *
4301 * @returns Support driver session handle.
4302 * @param pDevIns The device instance.
4303 */
4304 DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4305
4306 /**
4307 * Queries a generic object from the VMM user.
4308 *
4309 * @returns Pointer to the object if found, NULL if not.
4310 * @param pDevIns The device instance.
4311 * @param pUuid The UUID of what's being queried. The UUIDs and
4312 * the usage conventions are defined by the user.
4313 *
4314 * @note It is strictly forbidden to call this internally in VBox! This
4315 * interface is exclusively for hacks in externally developed devices.
4316 */
4317 DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4318
4319 /** @} */
4320
4321 /** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4322 uint32_t u32TheEnd;
4323} PDMDEVHLPR3;
4324#endif /* !IN_RING3 || DOXYGEN_RUNNING */
4325/** Pointer to the R3 PDM Device API. */
4326typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4327/** Pointer to the R3 PDM Device API, const variant. */
4328typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4329
4330
4331/**
4332 * PDM Device API - RC Variant.
4333 */
4334typedef struct PDMDEVHLPRC
4335{
4336 /** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4337 uint32_t u32Version;
4338
4339 /**
4340 * Sets up raw-mode context callback handlers for an I/O port range.
4341 *
4342 * The range must have been registered in ring-3 first using
4343 * PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4344 *
4345 * @returns VBox status.
4346 * @param pDevIns The device instance to register the ports with.
4347 * @param hIoPorts The I/O port range handle.
4348 * @param pfnOut Pointer to function which is gonna handle OUT
4349 * operations. Optional.
4350 * @param pfnIn Pointer to function which is gonna handle IN operations.
4351 * Optional.
4352 * @param pfnOutStr Pointer to function which is gonna handle string OUT
4353 * operations. Optional.
4354 * @param pfnInStr Pointer to function which is gonna handle string IN
4355 * operations. Optional.
4356 * @param pvUser User argument to pass to the callbacks.
4357 *
4358 * @remarks Caller enters the device critical section prior to invoking the
4359 * registered callback methods.
4360 *
4361 * @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4362 * PDMDevHlpIoPortUnmap.
4363 */
4364 DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4365 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4366 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4367 void *pvUser));
4368
4369 /**
4370 * Sets up raw-mode context callback handlers for an MMIO region.
4371 *
4372 * The region must have been registered in ring-3 first using
4373 * PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4374 *
4375 * @returns VBox status.
4376 * @param pDevIns The device instance to register the ports with.
4377 * @param hRegion The MMIO region handle.
4378 * @param pfnWrite Pointer to function which is gonna handle Write
4379 * operations.
4380 * @param pfnRead Pointer to function which is gonna handle Read
4381 * operations.
4382 * @param pfnFill Pointer to function which is gonna handle Fill/memset
4383 * operations. (optional)
4384 * @param pvUser User argument to pass to the callbacks.
4385 *
4386 * @remarks Caller enters the device critical section prior to invoking the
4387 * registered callback methods.
4388 *
4389 * @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4390 * PDMDevHlpMmioUnmap.
4391 */
4392 DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4393 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4394
4395 /**
4396 * Sets up a raw-mode mapping for an MMIO2 region.
4397 *
4398 * The region must have been created in ring-3 first using
4399 * PDMDevHlpMmio2Create().
4400 *
4401 * @returns VBox status.
4402 * @param pDevIns The device instance to register the ports with.
4403 * @param hRegion The MMIO2 region handle.
4404 * @param offSub Start of what to map into raw-mode. Must be page aligned.
4405 * @param cbSub Number of bytes to map into raw-mode. Must be page
4406 * aligned. Zero is an alias for everything.
4407 * @param ppvMapping Where to return the mapping corresponding to @a offSub.
4408 * @thread EMT(0)
4409 * @note Only available at VM creation time.
4410 *
4411 * @sa PDMDevHlpMmio2Create().
4412 */
4413 DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4414 size_t offSub, size_t cbSub, void **ppvMapping));
4415
4416 /**
4417 * Bus master physical memory read from the given PCI device.
4418 *
4419 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4420 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
4421 * @param pDevIns The device instance.
4422 * @param pPciDev The PCI device structure. If NULL the default
4423 * PCI device for this device instance is used.
4424 * @param GCPhys Physical address start reading from.
4425 * @param pvBuf Where to put the read bits.
4426 * @param cbRead How many bytes to read.
4427 * @thread Any thread, but the call may involve the emulation thread.
4428 */
4429 DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4430 void *pvBuf, size_t cbRead));
4431
4432 /**
4433 * Bus master physical memory write from the given PCI device.
4434 *
4435 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4436 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
4437 * @param pDevIns The device instance.
4438 * @param pPciDev The PCI device structure. If NULL the default
4439 * PCI device for this device instance is used.
4440 * @param GCPhys Physical address to write to.
4441 * @param pvBuf What to write.
4442 * @param cbWrite How many bytes to write.
4443 * @thread Any thread, but the call may involve the emulation thread.
4444 */
4445 DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4446 const void *pvBuf, size_t cbWrite));
4447
4448 /**
4449 * Set the IRQ for the given PCI device.
4450 *
4451 * @param pDevIns Device instance.
4452 * @param pPciDev The PCI device structure. If NULL the default
4453 * PCI device for this device instance is used.
4454 * @param iIrq IRQ number to set.
4455 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4456 * @thread Any thread, but will involve the emulation thread.
4457 */
4458 DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4459
4460 /**
4461 * Set ISA IRQ for a device.
4462 *
4463 * @param pDevIns Device instance.
4464 * @param iIrq IRQ number to set.
4465 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4466 * @thread Any thread, but will involve the emulation thread.
4467 */
4468 DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4469
4470 /**
4471 * Send an MSI straight to the I/O APIC.
4472 *
4473 * @param pDevIns PCI device instance.
4474 * @param GCPhys Physical address MSI request was written.
4475 * @param uValue Value written.
4476 * @thread Any thread, but will involve the emulation thread.
4477 */
4478 DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
4479
4480 /**
4481 * Read physical memory.
4482 *
4483 * @returns VINF_SUCCESS (for now).
4484 * @param pDevIns Device instance.
4485 * @param GCPhys Physical address start reading from.
4486 * @param pvBuf Where to put the read bits.
4487 * @param cbRead How many bytes to read.
4488 */
4489 DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
4490
4491 /**
4492 * Write to physical memory.
4493 *
4494 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4495 * @param pDevIns Device instance.
4496 * @param GCPhys Physical address to write to.
4497 * @param pvBuf What to write.
4498 * @param cbWrite How many bytes to write.
4499 */
4500 DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
4501
4502 /**
4503 * Checks if the Gate A20 is enabled or not.
4504 *
4505 * @returns true if A20 is enabled.
4506 * @returns false if A20 is disabled.
4507 * @param pDevIns Device instance.
4508 * @thread The emulation thread.
4509 */
4510 DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4511
4512 /**
4513 * Gets the VM state.
4514 *
4515 * @returns VM state.
4516 * @param pDevIns The device instance.
4517 * @thread Any thread (just keep in mind that it's volatile info).
4518 */
4519 DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4520
4521 /**
4522 * Set the VM error message
4523 *
4524 * @returns rc.
4525 * @param pDevIns Driver instance.
4526 * @param rc VBox status code.
4527 * @param SRC_POS Use RT_SRC_POS.
4528 * @param pszFormat Error message format string.
4529 * @param ... Error message arguments.
4530 */
4531 DECLRCCALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4532 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4533
4534 /**
4535 * Set the VM error message
4536 *
4537 * @returns rc.
4538 * @param pDevIns Driver instance.
4539 * @param rc VBox status code.
4540 * @param SRC_POS Use RT_SRC_POS.
4541 * @param pszFormat Error message format string.
4542 * @param va Error message arguments.
4543 */
4544 DECLRCCALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4545 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4546
4547 /**
4548 * Set the VM runtime error message
4549 *
4550 * @returns VBox status code.
4551 * @param pDevIns Device instance.
4552 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4553 * @param pszErrorId Error ID string.
4554 * @param pszFormat Error message format string.
4555 * @param ... Error message arguments.
4556 */
4557 DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4558 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4559
4560 /**
4561 * Set the VM runtime error message
4562 *
4563 * @returns VBox status code.
4564 * @param pDevIns Device instance.
4565 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4566 * @param pszErrorId Error ID string.
4567 * @param pszFormat Error message format string.
4568 * @param va Error message arguments.
4569 */
4570 DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4571 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
4572
4573 /**
4574 * Gets the VM handle. Restricted API.
4575 *
4576 * @returns VM Handle.
4577 * @param pDevIns Device instance.
4578 */
4579 DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4580
4581 /**
4582 * Gets the VMCPU handle. Restricted API.
4583 *
4584 * @returns VMCPU Handle.
4585 * @param pDevIns The device instance.
4586 */
4587 DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4588
4589 /**
4590 * The the VM CPU ID of the current thread (restricted API).
4591 *
4592 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4593 * @param pDevIns The device instance.
4594 */
4595 DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4596
4597 /**
4598 * Get the current virtual clock time in a VM. The clock frequency must be
4599 * queried separately.
4600 *
4601 * @returns Current clock time.
4602 * @param pDevIns The device instance.
4603 */
4604 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4605
4606 /**
4607 * Get the frequency of the virtual clock.
4608 *
4609 * @returns The clock frequency (not variable at run-time).
4610 * @param pDevIns The device instance.
4611 */
4612 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4613
4614 /**
4615 * Get the current virtual clock time in a VM, in nanoseconds.
4616 *
4617 * @returns Current clock time (in ns).
4618 * @param pDevIns The device instance.
4619 */
4620 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4621
4622 /**
4623 * Gets the NOP critical section.
4624 *
4625 * @returns The ring-3 address of the NOP critical section.
4626 * @param pDevIns The device instance.
4627 */
4628 DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4629
4630 /**
4631 * Changes the device level critical section from the automatically created
4632 * default to one desired by the device constructor.
4633 *
4634 * Must first be done in ring-3.
4635 *
4636 * @returns VBox status code.
4637 * @param pDevIns The device instance.
4638 * @param pCritSect The critical section to use. NULL is not
4639 * valid, instead use the NOP critical
4640 * section.
4641 */
4642 DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4643
4644 /** @name Exported PDM Critical Section Functions
4645 * @{ */
4646 DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4647 DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4648 DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4649 DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4650 DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4651 DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4652 DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4653 DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4654 DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4655 /** @} */
4656
4657 /**
4658 * Gets the trace buffer handle.
4659 *
4660 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4661 * really inteded for direct usage, thus no inline wrapper function.
4662 *
4663 * @returns Trace buffer handle or NIL_RTTRACEBUF.
4664 * @param pDevIns The device instance.
4665 */
4666 DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4667
4668 /**
4669 * Sets up the PCI bus for the raw-mode context.
4670 *
4671 * This must be called after ring-3 has registered the PCI bus using
4672 * PDMDevHlpPCIBusRegister().
4673 *
4674 * @returns VBox status code.
4675 * @param pDevIns The device instance.
4676 * @param pPciBusReg The PCI bus registration information for raw-mode,
4677 * considered volatile.
4678 * @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4679 */
4680 DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4681
4682 /**
4683 * Sets up the PIC for the ring-0 context.
4684 *
4685 * This must be called after ring-3 has registered the PIC using
4686 * PDMDevHlpPICRegister().
4687 *
4688 * @returns VBox status code.
4689 * @param pDevIns The device instance.
4690 * @param pPicReg The PIC registration information for ring-0,
4691 * considered volatile and copied.
4692 * @param ppPicHlp Where to return the ring-0 PIC helpers.
4693 */
4694 DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4695
4696 /**
4697 * Sets up the APIC for the raw-mode context.
4698 *
4699 * This must be called after ring-3 has registered the APIC using
4700 * PDMDevHlpApicRegister().
4701 *
4702 * @returns VBox status code.
4703 * @param pDevIns The device instance.
4704 */
4705 DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
4706
4707 /**
4708 * Sets up the IOAPIC for the ring-0 context.
4709 *
4710 * This must be called after ring-3 has registered the PIC using
4711 * PDMDevHlpIoApicRegister().
4712 *
4713 * @returns VBox status code.
4714 * @param pDevIns The device instance.
4715 * @param pIoApicReg The PIC registration information for ring-0,
4716 * considered volatile and copied.
4717 * @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
4718 */
4719 DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4720
4721 /**
4722 * Sets up the HPET for the raw-mode context.
4723 *
4724 * This must be called after ring-3 has registered the PIC using
4725 * PDMDevHlpHpetRegister().
4726 *
4727 * @returns VBox status code.
4728 * @param pDevIns The device instance.
4729 * @param pHpetReg The PIC registration information for raw-mode,
4730 * considered volatile and copied.
4731 * @param ppHpetHlp Where to return the raw-mode HPET helpers.
4732 */
4733 DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
4734
4735 /** Space reserved for future members.
4736 * @{ */
4737 DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
4738 DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
4739 DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
4740 DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
4741 DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
4742 DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
4743 DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
4744 DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
4745 DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
4746 DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
4747 /** @} */
4748
4749 /** Just a safety precaution. */
4750 uint32_t u32TheEnd;
4751} PDMDEVHLPRC;
4752/** Pointer PDM Device RC API. */
4753typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
4754/** Pointer PDM Device RC API. */
4755typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
4756
4757/** Current PDMDEVHLP version number. */
4758#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 14, 0)
4759
4760
4761/**
4762 * PDM Device API - R0 Variant.
4763 */
4764typedef struct PDMDEVHLPR0
4765{
4766 /** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
4767 uint32_t u32Version;
4768
4769 /**
4770 * Sets up ring-0 callback handlers for an I/O port range.
4771 *
4772 * The range must have been created in ring-3 first using
4773 * PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4774 *
4775 * @returns VBox status.
4776 * @param pDevIns The device instance to register the ports with.
4777 * @param hIoPorts The I/O port range handle.
4778 * @param pfnOut Pointer to function which is gonna handle OUT
4779 * operations. Optional.
4780 * @param pfnIn Pointer to function which is gonna handle IN operations.
4781 * Optional.
4782 * @param pfnOutStr Pointer to function which is gonna handle string OUT
4783 * operations. Optional.
4784 * @param pfnInStr Pointer to function which is gonna handle string IN
4785 * operations. Optional.
4786 * @param pvUser User argument to pass to the callbacks.
4787 *
4788 * @remarks Caller enters the device critical section prior to invoking the
4789 * registered callback methods.
4790 *
4791 * @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
4792 * PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
4793 */
4794 DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4795 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4796 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4797 void *pvUser));
4798
4799 /**
4800 * Sets up ring-0 callback handlers for an MMIO region.
4801 *
4802 * The region must have been created in ring-3 first using
4803 * PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
4804 * PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
4805 *
4806 * @returns VBox status.
4807 * @param pDevIns The device instance to register the ports with.
4808 * @param hRegion The MMIO region handle.
4809 * @param pfnWrite Pointer to function which is gonna handle Write
4810 * operations.
4811 * @param pfnRead Pointer to function which is gonna handle Read
4812 * operations.
4813 * @param pfnFill Pointer to function which is gonna handle Fill/memset
4814 * operations. (optional)
4815 * @param pvUser User argument to pass to the callbacks.
4816 *
4817 * @remarks Caller enters the device critical section prior to invoking the
4818 * registered callback methods.
4819 *
4820 * @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
4821 * PDMDevHlpMmioUnmap().
4822 */
4823 DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4824 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4825
4826 /**
4827 * Sets up a ring-0 mapping for an MMIO2 region.
4828 *
4829 * The region must have been created in ring-3 first using
4830 * PDMDevHlpMmio2Create().
4831 *
4832 * @returns VBox status.
4833 * @param pDevIns The device instance to register the ports with.
4834 * @param hRegion The MMIO2 region handle.
4835 * @param offSub Start of what to map into ring-0. Must be page aligned.
4836 * @param cbSub Number of bytes to map into ring-0. Must be page
4837 * aligned. Zero is an alias for everything.
4838 * @param ppvMapping Where to return the mapping corresponding to @a offSub.
4839 *
4840 * @thread EMT(0)
4841 * @note Only available at VM creation time.
4842 *
4843 * @sa PDMDevHlpMmio2Create().
4844 */
4845 DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
4846 void **ppvMapping));
4847
4848 /**
4849 * Bus master physical memory read from the given PCI device.
4850 *
4851 * @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
4852 * VERR_EM_MEMORY.
4853 * @param pDevIns The device instance.
4854 * @param pPciDev The PCI device structure. If NULL the default
4855 * PCI device for this device instance is used.
4856 * @param GCPhys Physical address start reading from.
4857 * @param pvBuf Where to put the read bits.
4858 * @param cbRead How many bytes to read.
4859 * @thread Any thread, but the call may involve the emulation thread.
4860 */
4861 DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4862 void *pvBuf, size_t cbRead));
4863
4864 /**
4865 * Bus master physical memory write from the given PCI device.
4866 *
4867 * @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
4868 * VERR_EM_MEMORY.
4869 * @param pDevIns The device instance.
4870 * @param pPciDev The PCI device structure. If NULL the default
4871 * PCI device for this device instance is used.
4872 * @param GCPhys Physical address to write to.
4873 * @param pvBuf What to write.
4874 * @param cbWrite How many bytes to write.
4875 * @thread Any thread, but the call may involve the emulation thread.
4876 */
4877 DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4878 const void *pvBuf, size_t cbWrite));
4879
4880 /**
4881 * Set the IRQ for the given PCI device.
4882 *
4883 * @param pDevIns Device instance.
4884 * @param pPciDev The PCI device structure. If NULL the default
4885 * PCI device for this device instance is used.
4886 * @param iIrq IRQ number to set.
4887 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4888 * @thread Any thread, but will involve the emulation thread.
4889 */
4890 DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4891
4892 /**
4893 * Set ISA IRQ for a device.
4894 *
4895 * @param pDevIns Device instance.
4896 * @param iIrq IRQ number to set.
4897 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4898 * @thread Any thread, but will involve the emulation thread.
4899 */
4900 DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4901
4902 /**
4903 * Send an MSI straight to the I/O APIC.
4904 *
4905 * @param pDevIns PCI device instance.
4906 * @param GCPhys Physical address MSI request was written.
4907 * @param uValue Value written.
4908 * @thread Any thread, but will involve the emulation thread.
4909 */
4910 DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
4911
4912 /**
4913 * Read physical memory.
4914 *
4915 * @returns VINF_SUCCESS (for now).
4916 * @param pDevIns Device instance.
4917 * @param GCPhys Physical address start reading from.
4918 * @param pvBuf Where to put the read bits.
4919 * @param cbRead How many bytes to read.
4920 */
4921 DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
4922
4923 /**
4924 * Write to physical memory.
4925 *
4926 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4927 * @param pDevIns Device instance.
4928 * @param GCPhys Physical address to write to.
4929 * @param pvBuf What to write.
4930 * @param cbWrite How many bytes to write.
4931 */
4932 DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
4933
4934 /**
4935 * Checks if the Gate A20 is enabled or not.
4936 *
4937 * @returns true if A20 is enabled.
4938 * @returns false if A20 is disabled.
4939 * @param pDevIns Device instance.
4940 * @thread The emulation thread.
4941 */
4942 DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4943
4944 /**
4945 * Gets the VM state.
4946 *
4947 * @returns VM state.
4948 * @param pDevIns The device instance.
4949 * @thread Any thread (just keep in mind that it's volatile info).
4950 */
4951 DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4952
4953 /**
4954 * Set the VM error message
4955 *
4956 * @returns rc.
4957 * @param pDevIns Driver instance.
4958 * @param rc VBox status code.
4959 * @param SRC_POS Use RT_SRC_POS.
4960 * @param pszFormat Error message format string.
4961 * @param ... Error message arguments.
4962 */
4963 DECLR0CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4964 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4965
4966 /**
4967 * Set the VM error message
4968 *
4969 * @returns rc.
4970 * @param pDevIns Driver instance.
4971 * @param rc VBox status code.
4972 * @param SRC_POS Use RT_SRC_POS.
4973 * @param pszFormat Error message format string.
4974 * @param va Error message arguments.
4975 */
4976 DECLR0CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4977 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4978
4979 /**
4980 * Set the VM runtime error message
4981 *
4982 * @returns VBox status code.
4983 * @param pDevIns Device instance.
4984 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4985 * @param pszErrorId Error ID string.
4986 * @param pszFormat Error message format string.
4987 * @param ... Error message arguments.
4988 */
4989 DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4990 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4991
4992 /**
4993 * Set the VM runtime error message
4994 *
4995 * @returns VBox status code.
4996 * @param pDevIns Device instance.
4997 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4998 * @param pszErrorId Error ID string.
4999 * @param pszFormat Error message format string.
5000 * @param va Error message arguments.
5001 */
5002 DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5003 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
5004
5005 /**
5006 * Gets the VM handle. Restricted API.
5007 *
5008 * @returns VM Handle.
5009 * @param pDevIns Device instance.
5010 */
5011 DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5012
5013 /**
5014 * Gets the VMCPU handle. Restricted API.
5015 *
5016 * @returns VMCPU Handle.
5017 * @param pDevIns The device instance.
5018 */
5019 DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5020
5021 /**
5022 * The the VM CPU ID of the current thread (restricted API).
5023 *
5024 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5025 * @param pDevIns The device instance.
5026 */
5027 DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5028
5029 /**
5030 * Translates a timer handle to a pointer.
5031 *
5032 * @returns The time address.
5033 * @param pDevIns The device instance.
5034 * @param hTimer The timer handle.
5035 */
5036 DECLR0CALLBACKMEMBER(PTMTIMERR0, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5037
5038 /** @name Timer handle method wrappers
5039 * @{ */
5040 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5041 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5042 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5043 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5044 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5045 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5046 DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5047 DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5048 DECLR0CALLBACKMEMBER(int, pfnTimerLock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5049 DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5050 DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5051 DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5052 DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5053 DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5054 DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5055 DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5056 DECLR0CALLBACKMEMBER(void, pfnTimerUnlock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5057 /** @} */
5058
5059 /**
5060 * Get the current virtual clock time in a VM. The clock frequency must be
5061 * queried separately.
5062 *
5063 * @returns Current clock time.
5064 * @param pDevIns The device instance.
5065 */
5066 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5067
5068 /**
5069 * Get the frequency of the virtual clock.
5070 *
5071 * @returns The clock frequency (not variable at run-time).
5072 * @param pDevIns The device instance.
5073 */
5074 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5075
5076 /**
5077 * Get the current virtual clock time in a VM, in nanoseconds.
5078 *
5079 * @returns Current clock time (in ns).
5080 * @param pDevIns The device instance.
5081 */
5082 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5083
5084 /** @name Exported PDM Queue Functions
5085 * @{ */
5086 DECLR0CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5087 DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5088 DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5089 DECLR0CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
5090 DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5091 /** @} */
5092
5093 /** @name PDM Task
5094 * @{ */
5095 /**
5096 * Triggers the running the given task.
5097 *
5098 * @returns VBox status code.
5099 * @retval VINF_ALREADY_POSTED is the task is already pending.
5100 * @param pDevIns The device instance.
5101 * @param hTask The task to trigger.
5102 * @thread Any thread.
5103 */
5104 DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5105 /** @} */
5106
5107 /** @name SUP Event Semaphore Wrappers (single release / auto reset)
5108 * These semaphores can be signalled from ring-0.
5109 * @{ */
5110 /** @sa SUPSemEventSignal */
5111 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5112 /** @sa SUPSemEventWaitNoResume */
5113 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5114 /** @sa SUPSemEventWaitNsAbsIntr */
5115 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5116 /** @sa SUPSemEventWaitNsRelIntr */
5117 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5118 /** @sa SUPSemEventGetResolution */
5119 DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5120 /** @} */
5121
5122 /** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5123 * These semaphores can be signalled from ring-0.
5124 * @{ */
5125 /** @sa SUPSemEventMultiSignal */
5126 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5127 /** @sa SUPSemEventMultiReset */
5128 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5129 /** @sa SUPSemEventMultiWaitNoResume */
5130 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5131 /** @sa SUPSemEventMultiWaitNsAbsIntr */
5132 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5133 /** @sa SUPSemEventMultiWaitNsRelIntr */
5134 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5135 /** @sa SUPSemEventMultiGetResolution */
5136 DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5137 /** @} */
5138
5139 /**
5140 * Gets the NOP critical section.
5141 *
5142 * @returns The ring-3 address of the NOP critical section.
5143 * @param pDevIns The device instance.
5144 */
5145 DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5146
5147 /**
5148 * Changes the device level critical section from the automatically created
5149 * default to one desired by the device constructor.
5150 *
5151 * Must first be done in ring-3.
5152 *
5153 * @returns VBox status code.
5154 * @param pDevIns The device instance.
5155 * @param pCritSect The critical section to use. NULL is not
5156 * valid, instead use the NOP critical
5157 * section.
5158 */
5159 DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5160
5161 /** @name Exported PDM Critical Section Functions
5162 * @{ */
5163 DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5164 DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5165 DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5166 DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5167 DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5168 DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5169 DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5170 DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5171 DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5172 DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5173 /** @} */
5174
5175 /**
5176 * Gets the trace buffer handle.
5177 *
5178 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5179 * really inteded for direct usage, thus no inline wrapper function.
5180 *
5181 * @returns Trace buffer handle or NIL_RTTRACEBUF.
5182 * @param pDevIns The device instance.
5183 */
5184 DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5185
5186 /**
5187 * Sets up the PCI bus for the ring-0 context.
5188 *
5189 * This must be called after ring-3 has registered the PCI bus using
5190 * PDMDevHlpPCIBusRegister().
5191 *
5192 * @returns VBox status code.
5193 * @param pDevIns The device instance.
5194 * @param pPciBusReg The PCI bus registration information for ring-0,
5195 * considered volatile and copied.
5196 * @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5197 */
5198 DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5199
5200 /**
5201 * Sets up the PIC for the ring-0 context.
5202 *
5203 * This must be called after ring-3 has registered the PIC using
5204 * PDMDevHlpPICRegister().
5205 *
5206 * @returns VBox status code.
5207 * @param pDevIns The device instance.
5208 * @param pPicReg The PIC registration information for ring-0,
5209 * considered volatile and copied.
5210 * @param ppPicHlp Where to return the ring-0 PIC helpers.
5211 */
5212 DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5213
5214 /**
5215 * Sets up the APIC for the ring-0 context.
5216 *
5217 * This must be called after ring-3 has registered the APIC using
5218 * PDMDevHlpApicRegister().
5219 *
5220 * @returns VBox status code.
5221 * @param pDevIns The device instance.
5222 */
5223 DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5224
5225 /**
5226 * Sets up the IOAPIC for the ring-0 context.
5227 *
5228 * This must be called after ring-3 has registered the PIC using
5229 * PDMDevHlpIoApicRegister().
5230 *
5231 * @returns VBox status code.
5232 * @param pDevIns The device instance.
5233 * @param pIoApicReg The PIC registration information for ring-0,
5234 * considered volatile and copied.
5235 * @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5236 */
5237 DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5238
5239 /**
5240 * Sets up the HPET for the ring-0 context.
5241 *
5242 * This must be called after ring-3 has registered the PIC using
5243 * PDMDevHlpHpetRegister().
5244 *
5245 * @returns VBox status code.
5246 * @param pDevIns The device instance.
5247 * @param pHpetReg The PIC registration information for ring-0,
5248 * considered volatile and copied.
5249 * @param ppHpetHlp Where to return the ring-0 HPET helpers.
5250 */
5251 DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5252
5253 /** Space reserved for future members.
5254 * @{ */
5255 DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5256 DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5257 DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5258 DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5259 DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5260 DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5261 DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5262 DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5263 DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5264 DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5265 /** @} */
5266
5267 /** Just a safety precaution. */
5268 uint32_t u32TheEnd;
5269} PDMDEVHLPR0;
5270/** Pointer PDM Device R0 API. */
5271typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5272/** Pointer PDM Device GC API. */
5273typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5274
5275/** Current PDMDEVHLP version number. */
5276#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 15, 0)
5277
5278
5279/**
5280 * PDM Device Instance.
5281 */
5282typedef struct PDMDEVINSR3
5283{
5284 /** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5285 uint32_t u32Version;
5286 /** Device instance number. */
5287 uint32_t iInstance;
5288 /** Size of the ring-3, raw-mode and shared bits. */
5289 uint32_t cbRing3;
5290 /** Set if ring-0 context is enabled. */
5291 bool fR0Enabled;
5292 /** Set if raw-mode context is enabled. */
5293 bool fRCEnabled;
5294 /** Alignment padding. */
5295 bool afReserved[2];
5296 /** Pointer the HC PDM Device API. */
5297 PCPDMDEVHLPR3 pHlpR3;
5298 /** Pointer to the shared device instance data. */
5299 RTR3PTR pvInstanceDataR3;
5300 /** Pointer to the device instance data for ring-3. */
5301 RTR3PTR pvInstanceDataForR3;
5302 /** The critical section for the device.
5303 *
5304 * TM and IOM will enter this critical section before calling into the device
5305 * code. PDM will when doing power on, power off, reset, suspend and resume
5306 * notifications. SSM will currently not, but this will be changed later on.
5307 *
5308 * The device gets a critical section automatically assigned to it before
5309 * the constructor is called. If the constructor wishes to use a different
5310 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5311 * very early on.
5312 */
5313 R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5314 /** Pointer to device registration structure. */
5315 R3PTRTYPE(PCPDMDEVREG) pReg;
5316 /** Configuration handle. */
5317 R3PTRTYPE(PCFGMNODE) pCfg;
5318 /** The base interface of the device.
5319 *
5320 * The device constructor initializes this if it has any
5321 * device level interfaces to export. To obtain this interface
5322 * call PDMR3QueryDevice(). */
5323 PDMIBASE IBase;
5324
5325 /** Tracing indicator. */
5326 uint32_t fTracing;
5327 /** The tracing ID of this device. */
5328 uint32_t idTracing;
5329
5330 /** Ring-3 pointer to the raw-mode device instance. */
5331 R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5332 /** Raw-mode address of the raw-mode device instance. */
5333 RTRGPTR pDevInsForRC;
5334 /** Ring-3 pointer to the raw-mode instance data. */
5335 RTR3PTR pvInstanceDataForRCR3;
5336
5337 /** PCI device structure size. */
5338 uint32_t cbPciDev;
5339 /** Number of PCI devices in apPciDevs. */
5340 uint32_t cPciDevs;
5341 /** Pointer to the PCI devices for this device.
5342 * (Allocated after the shared instance data.)
5343 * @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5344 * two devices ever needing it can use cbPciDev and do the address
5345 * calculations that for entries 8+. */
5346 R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5347
5348 /** Temporarily. */
5349 R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5350 /** Temporarily. */
5351 RTR0PTR pvInstanceDataR0;
5352 /** Temporarily. */
5353 RTRCPTR pvInstanceDataRC;
5354 /** Align the internal data more naturally. */
5355 uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5356
5357 /** Internal data. */
5358 union
5359 {
5360#ifdef PDMDEVINSINT_DECLARED
5361 PDMDEVINSINTR3 s;
5362#endif
5363 uint8_t padding[HC_ARCH_BITS == 32 ? 0x30 : 0x50];
5364 } Internal;
5365
5366 /** Device instance data for ring-3. The size of this area is defined
5367 * in the PDMDEVREG::cbInstanceR3 field. */
5368 char achInstanceData[8];
5369} PDMDEVINSR3;
5370
5371/** Current PDMDEVINSR3 version number. */
5372#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5373
5374/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5375#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5376
5377
5378/**
5379 * PDM ring-0 device instance.
5380 */
5381typedef struct PDMDEVINSR0
5382{
5383 /** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5384 uint32_t u32Version;
5385 /** Device instance number. */
5386 uint32_t iInstance;
5387
5388 /** Pointer the HC PDM Device API. */
5389 PCPDMDEVHLPR0 pHlpR0;
5390 /** Pointer to the shared device instance data. */
5391 RTR0PTR pvInstanceDataR0;
5392 /** Pointer to the device instance data for ring-0. */
5393 RTR0PTR pvInstanceDataForR0;
5394 /** The critical section for the device.
5395 *
5396 * TM and IOM will enter this critical section before calling into the device
5397 * code. PDM will when doing power on, power off, reset, suspend and resume
5398 * notifications. SSM will currently not, but this will be changed later on.
5399 *
5400 * The device gets a critical section automatically assigned to it before
5401 * the constructor is called. If the constructor wishes to use a different
5402 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5403 * very early on.
5404 */
5405 R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5406 /** Pointer to the ring-0 device registration structure. */
5407 R0PTRTYPE(PCPDMDEVREGR0) pReg;
5408 /** Ring-3 address of the ring-3 device instance. */
5409 R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5410 /** Ring-0 pointer to the ring-3 device instance. */
5411 R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5412 /** Ring-0 pointer to the ring-3 instance data. */
5413 RTR0PTR pvInstanceDataForR3R0;
5414 /** Raw-mode address of the raw-mode device instance. */
5415 RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5416 /** Ring-0 pointer to the raw-mode device instance. */
5417 R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5418 /** Ring-0 pointer to the raw-mode instance data. */
5419 RTR0PTR pvInstanceDataForRCR0;
5420
5421 /** PCI device structure size. */
5422 uint32_t cbPciDev;
5423 /** Number of PCI devices in apPciDevs. */
5424 uint32_t cPciDevs;
5425 /** Pointer to the PCI devices for this device.
5426 * (Allocated after the shared instance data.)
5427 * @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5428 * two devices ever needing it can use cbPciDev and do the address
5429 * calculations that for entries 8+. */
5430 R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5431
5432 /** Align the internal data more naturally. */
5433 uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5434
5435 /** Internal data. */
5436 union
5437 {
5438#ifdef PDMDEVINSINT_DECLARED
5439 PDMDEVINSINTR0 s;
5440#endif
5441 uint8_t padding[HC_ARCH_BITS == 32 ? 0x20 : 0x40];
5442 } Internal;
5443
5444 /** Device instance data for ring-0. The size of this area is defined
5445 * in the PDMDEVREG::cbInstanceR0 field. */
5446 char achInstanceData[8];
5447} PDMDEVINSR0;
5448
5449/** Current PDMDEVINSR0 version number. */
5450#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5451
5452
5453/**
5454 * PDM raw-mode device instance.
5455 */
5456typedef struct PDMDEVINSRC
5457{
5458 /** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5459 uint32_t u32Version;
5460 /** Device instance number. */
5461 uint32_t iInstance;
5462
5463 /** Pointer the HC PDM Device API. */
5464 PCPDMDEVHLPRC pHlpRC;
5465 /** Pointer to the shared device instance data. */
5466 RTRGPTR pvInstanceDataRC;
5467 /** Pointer to the device instance data for raw-mode. */
5468 RTRGPTR pvInstanceDataForRC;
5469 /** The critical section for the device.
5470 *
5471 * TM and IOM will enter this critical section before calling into the device
5472 * code. PDM will when doing power on, power off, reset, suspend and resume
5473 * notifications. SSM will currently not, but this will be changed later on.
5474 *
5475 * The device gets a critical section automatically assigned to it before
5476 * the constructor is called. If the constructor wishes to use a different
5477 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5478 * very early on.
5479 */
5480 RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5481 /** Pointer to the raw-mode device registration structure. */
5482 RGPTRTYPE(PCPDMDEVREGRC) pReg;
5483
5484 /** PCI device structure size. */
5485 uint32_t cbPciDev;
5486 /** Number of PCI devices in apPciDevs. */
5487 uint32_t cPciDevs;
5488 /** Pointer to the PCI devices for this device.
5489 * (Allocated after the shared instance data.) */
5490 RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5491
5492 /** Align the internal data more naturally. */
5493 uint32_t au32Padding[14];
5494
5495 /** Internal data. */
5496 union
5497 {
5498#ifdef PDMDEVINSINT_DECLARED
5499 PDMDEVINSINTRC s;
5500#endif
5501 uint8_t padding[0x10];
5502 } Internal;
5503
5504 /** Device instance data for ring-0. The size of this area is defined
5505 * in the PDMDEVREG::cbInstanceR0 field. */
5506 char achInstanceData[8];
5507} PDMDEVINSRC;
5508
5509/** Current PDMDEVINSR0 version number. */
5510#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5511
5512
5513/** @def PDM_DEVINS_VERSION
5514 * Current PDMDEVINS version number. */
5515/** @typedef PDMDEVINS
5516 * The device instance structure for the current context. */
5517#ifdef IN_RING3
5518# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5519typedef PDMDEVINSR3 PDMDEVINS;
5520#elif defined(IN_RING0)
5521# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5522typedef PDMDEVINSR0 PDMDEVINS;
5523#elif defined(IN_RC)
5524# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5525typedef PDMDEVINSRC PDMDEVINS;
5526#else
5527# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5528#endif
5529
5530/**
5531 * Get the pointer to an PCI device.
5532 * @note Returns NULL if @a a_idxPciDev is out of bounds.
5533 */
5534#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5535 ( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5536 : PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5537
5538/**
5539 * Calc the pointer to of a given PCI device.
5540 * @note Returns NULL if @a a_idxPciDev is out of bounds.
5541 */
5542#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5543 ( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5544 ? (PPDMPCIDEV)((uint8_t *)((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) * (uintptr_t)(a_idxPciDev)) \
5545 : (PPDMPCIDEV)NULL )
5546
5547
5548/**
5549 * Checks the structure versions of the device instance and device helpers,
5550 * returning if they are incompatible.
5551 *
5552 * This is for use in the constructor.
5553 *
5554 * @param pDevIns The device instance pointer.
5555 */
5556#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5557 do \
5558 { \
5559 PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5560 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5561 ("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5562 VERR_PDM_DEVINS_VERSION_MISMATCH); \
5563 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5564 ("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5565 VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5566 } while (0)
5567
5568/**
5569 * Quietly checks the structure versions of the device instance and device
5570 * helpers, returning if they are incompatible.
5571 *
5572 * This is for use in the destructor.
5573 *
5574 * @param pDevIns The device instance pointer.
5575 */
5576#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5577 do \
5578 { \
5579 PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5580 if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5581 { /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5582 if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5583 { /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5584 } while (0)
5585
5586/**
5587 * Wrapper around CFGMR3ValidateConfig for the root config for use in the
5588 * constructor - returns on failure.
5589 *
5590 * This should be invoked after having initialized the instance data
5591 * sufficiently for the correct operation of the destructor. The destructor is
5592 * always called!
5593 *
5594 * @param pDevIns Pointer to the PDM device instance.
5595 * @param pszValidValues Patterns describing the valid value names. See
5596 * RTStrSimplePatternMultiMatch for details on the
5597 * pattern syntax.
5598 * @param pszValidNodes Patterns describing the valid node (key) names.
5599 * Pass empty string if no valid nodes.
5600 */
5601#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5602 do \
5603 { \
5604 int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5605 (pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5606 if (RT_SUCCESS(rcValCfg)) \
5607 { /* likely */ } else return rcValCfg; \
5608 } while (0)
5609
5610/** @def PDMDEV_ASSERT_EMT
5611 * Assert that the current thread is the emulation thread.
5612 */
5613#ifdef VBOX_STRICT
5614# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5615#else
5616# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5617#endif
5618
5619/** @def PDMDEV_ASSERT_OTHER
5620 * Assert that the current thread is NOT the emulation thread.
5621 */
5622#ifdef VBOX_STRICT
5623# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5624#else
5625# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5626#endif
5627
5628/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5629 * Assert that the current thread is owner of the VM lock.
5630 */
5631#ifdef VBOX_STRICT
5632# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5633#else
5634# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5635#endif
5636
5637/** @def PDMDEV_SET_ERROR
5638 * Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5639 */
5640#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5641 PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5642
5643/** @def PDMDEV_SET_RUNTIME_ERROR
5644 * Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5645 */
5646#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5647 PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5648
5649/** @def PDMDEVINS_2_RCPTR
5650 * Converts a PDM Device instance pointer a RC PDM Device instance pointer.
5651 */
5652#ifdef IN_RC
5653# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5654#else
5655# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5656#endif
5657
5658/** @def PDMDEVINS_2_R3PTR
5659 * Converts a PDM Device instance pointer a R3 PDM Device instance pointer.
5660 */
5661#ifdef IN_RING3
5662# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5663#else
5664# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5665#endif
5666
5667/** @def PDMDEVINS_2_R0PTR
5668 * Converts a PDM Device instance pointer a R0 PDM Device instance pointer.
5669 */
5670#ifdef IN_RING0
5671# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5672#else
5673# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5674#endif
5675
5676/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5677 * Converts a PDM device instance data pointer to a ring-0 one.
5678 * @deprecated
5679 */
5680#ifdef IN_RING0
5681# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5682#else
5683# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5684#endif
5685
5686
5687/** @def PDMDEVINS_2_DATA
5688 * This is a safer edition of PDMINS_2_DATA that checks that the size of the
5689 * target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5690 *
5691 * @note Do no use this macro in common code working on a core structure which
5692 * device specific code has expanded.
5693 */
5694#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5695# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5696 ([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5697 { \
5698 a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5699 Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5700 return pLambdaRet; \
5701 }(a_pDevIns))
5702#else
5703# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5704#endif
5705
5706/** @def PDMDEVINS_2_DATA_CC
5707 * This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5708 * target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5709 *
5710 * @note Do no use this macro in common code working on a core structure which
5711 * device specific code has expanded.
5712 */
5713#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5714# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5715 ([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5716 { \
5717 a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5718 Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5719 return pLambdaRet; \
5720 }(a_pDevIns))
5721#else
5722# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5723#endif
5724
5725
5726#ifdef IN_RING3
5727
5728/**
5729 * @copydoc PDMDEVHLPR3::pfnIOPortRegister
5730 */
5731DECLINLINE(int) PDMDevHlpIOPortRegister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTHCPTR pvUser,
5732 PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
5733 PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc)
5734{
5735 return pDevIns->pHlpR3->pfnIOPortRegister(pDevIns, Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc);
5736}
5737
5738/**
5739 * @copydoc PDMDEVHLPR3::pfnIOPortRegisterRC
5740 */
5741DECLINLINE(int) PDMDevHlpIOPortRegisterRC(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTRCPTR pvUser,
5742 const char *pszOut, const char *pszIn, const char *pszOutStr,
5743 const char *pszInStr, const char *pszDesc)
5744{
5745 return pDevIns->pHlpR3->pfnIOPortRegisterRC(pDevIns, Port, cPorts, pvUser, pszOut, pszIn, pszOutStr, pszInStr, pszDesc);
5746}
5747
5748/**
5749 * @copydoc PDMDEVHLPR3::pfnIOPortRegisterR0
5750 */
5751DECLINLINE(int) PDMDevHlpIOPortRegisterR0(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTR0PTR pvUser,
5752 const char *pszOut, const char *pszIn, const char *pszOutStr,
5753 const char *pszInStr, const char *pszDesc)
5754{
5755 return pDevIns->pHlpR3->pfnIOPortRegisterR0(pDevIns, Port, cPorts, pvUser, pszOut, pszIn, pszOutStr, pszInStr, pszDesc);
5756}
5757
5758/**
5759 * @copydoc PDMDEVHLPR3::pfnIOPortDeregister
5760 */
5761DECLINLINE(int) PDMDevHlpIOPortDeregister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts)
5762{
5763 return pDevIns->pHlpR3->pfnIOPortDeregister(pDevIns, Port, cPorts);
5764}
5765
5766/**
5767 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
5768 */
5769DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5770 PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
5771 PIOMIOPORTHANDLE phIoPorts)
5772{
5773 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5774 pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5775 if (RT_SUCCESS(rc))
5776 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5777 return rc;
5778}
5779
5780/**
5781 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
5782 */
5783DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5784 PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
5785 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5786{
5787 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5788 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5789 if (RT_SUCCESS(rc))
5790 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5791 return rc;
5792}
5793
5794/**
5795 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
5796 */
5797DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5798 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5799 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5800{
5801 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5802 pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5803 if (RT_SUCCESS(rc))
5804 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5805 return rc;
5806}
5807
5808/**
5809 * Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
5810 */
5811DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5812 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5813 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5814 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5815{
5816 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5817 pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5818 if (RT_SUCCESS(rc))
5819 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5820 return rc;
5821}
5822
5823/**
5824 * @sa PDMDevHlpIoPortCreateEx
5825 */
5826DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5827 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser, const char *pszDesc,
5828 PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5829{
5830 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
5831 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5832}
5833
5834
5835/**
5836 * @sa PDMDevHlpIoPortCreateEx
5837 */
5838DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5839 PFNIOMIOPORTNEWIN pfnIn, void *pvUser, const char *pszDesc,
5840 PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5841{
5842 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5843 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5844}
5845
5846/**
5847 * @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
5848 */
5849DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
5850 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5851 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5852 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5853{
5854 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
5855 pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5856}
5857
5858/**
5859 * @copydoc PDMDEVHLPR3::pfnIoPortMap
5860 */
5861DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
5862{
5863 return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
5864}
5865
5866/**
5867 * @copydoc PDMDEVHLPR3::pfnIoPortUnmap
5868 */
5869DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5870{
5871 return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
5872}
5873
5874/**
5875 * @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
5876 */
5877DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5878{
5879 return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
5880}
5881
5882
5883#endif /* IN_RING3 */
5884#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
5885
5886/**
5887 * @sa PDMDevHlpIoPortSetUpContextEx
5888 */
5889DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5890 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
5891{
5892 return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
5893}
5894
5895/**
5896 * @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
5897 */
5898DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5899 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5900 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
5901{
5902 return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
5903}
5904
5905#endif /* !IN_RING3 || DOXYGEN_RUNNING */
5906#ifdef IN_RING3
5907
5908/**
5909 * @sa PDMDevHlpMmioCreateEx
5910 */
5911DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5912 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
5913 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
5914{
5915 return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
5916 pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
5917}
5918
5919/**
5920 * @copydoc PDMDEVHLPR3::pfnMmioCreateEx
5921 */
5922DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
5923 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5924 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
5925 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion)
5926{
5927 return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
5928 pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
5929}
5930
5931/**
5932 * @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
5933 */
5934DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
5935 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
5936 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
5937{
5938 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /*pPciDev*/, UINT32_MAX /*iPciRegion*/,
5939 pfnWrite, pfnRead, NULL /*pfnFill*/, NULL /*pvUser*/, pszDesc, phRegion);
5940 if (RT_SUCCESS(rc))
5941 rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
5942 return rc;
5943}
5944
5945/**
5946 * @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
5947 */
5948DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
5949 PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
5950 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
5951 const char *pszDesc, PIOMMMIOHANDLE phRegion)
5952{
5953 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
5954 pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
5955 if (RT_SUCCESS(rc))
5956 rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
5957 return rc;
5958}
5959
5960/**
5961 * @copydoc PDMDEVHLPR3::pfnMmioMap
5962 */
5963DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
5964{
5965 return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
5966}
5967
5968/**
5969 * @copydoc PDMDEVHLPR3::pfnMmioUnmap
5970 */
5971DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
5972{
5973 return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
5974}
5975
5976/**
5977 * @copydoc PDMDEVHLPR3::pfnMmioReduce
5978 */
5979DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
5980{
5981 return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
5982}
5983
5984/**
5985 * @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
5986 */
5987DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
5988{
5989 return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
5990}
5991
5992#endif /* IN_RING3 */
5993#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
5994
5995/**
5996 * @sa PDMDevHlpMmioSetUpContextEx
5997 */
5998DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
5999 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6000{
6001 return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6002}
6003
6004/**
6005 * @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6006 */
6007DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6008 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6009{
6010 return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6011}
6012
6013#endif /* !IN_RING3 || DOXYGEN_RUNNING */
6014#ifdef IN_RING3
6015
6016/**
6017 * Register a Memory Mapped I/O (MMIO) region.
6018 *
6019 * These callbacks are of course for the ring-3 context (R3). Register HC
6020 * handlers before raw-mode context (RC) and ring-0 context (R0) handlers! There
6021 * must be a R3 handler for every RC and R0 handler!
6022 *
6023 * @returns VBox status.
6024 * @param pDevIns The device instance to register the MMIO with.
6025 * @param GCPhysStart First physical address in the range.
6026 * @param cbRange The size of the range (in bytes).
6027 * @param pvUser User argument.
6028 * @param fFlags Flags, IOMMMIO_FLAGS_XXX.
6029 * @param pfnWrite Pointer to function which is gonna handle Write operations.
6030 * @param pfnRead Pointer to function which is gonna handle Read operations.
6031 * @param pszDesc Pointer to description string. This must not be freed.
6032 */
6033DECLINLINE(int) PDMDevHlpMMIORegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
6034 uint32_t fFlags, PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, const char *pszDesc)
6035{
6036 return pDevIns->pHlpR3->pfnMMIORegister(pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, NULL /*pfnFill*/,
6037 fFlags, pszDesc);
6038}
6039
6040/**
6041 * Register a Memory Mapped I/O (MMIO) region for RC.
6042 *
6043 * These callbacks are for the raw-mode context (RC). Register ring-3 context
6044 * (R3) handlers before guest context handlers! There must be a R3 handler for
6045 * every RC handler!
6046 *
6047 * @returns VBox status.
6048 * @param pDevIns The device instance to register the MMIO with.
6049 * @param GCPhysStart First physical address in the range.
6050 * @param cbRange The size of the range (in bytes).
6051 * @param pvUser User argument.
6052 * @param pszWrite Name of the RC function which is gonna handle Write operations.
6053 * @param pszRead Name of the RC function which is gonna handle Read operations.
6054 */
6055DECLINLINE(int) PDMDevHlpMMIORegisterRC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
6056 const char *pszWrite, const char *pszRead)
6057{
6058 return pDevIns->pHlpR3->pfnMMIORegisterRC(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, NULL /*pszFill*/);
6059}
6060
6061/**
6062 * Register a Memory Mapped I/O (MMIO) region for R0.
6063 *
6064 * These callbacks are for the ring-0 host context (R0). Register ring-3
6065 * constext (R3) handlers before R0 handlers! There must be a R3 handler for
6066 * every R0 handler!
6067 *
6068 * @returns VBox status.
6069 * @param pDevIns The device instance to register the MMIO with.
6070 * @param GCPhysStart First physical address in the range.
6071 * @param cbRange The size of the range (in bytes).
6072 * @param pvUser User argument. (if pointer, then it must be in locked memory!)
6073 * @param pszWrite Name of the RC function which is gonna handle Write operations.
6074 * @param pszRead Name of the RC function which is gonna handle Read operations.
6075 * @remarks Caller enters the device critical section prior to invoking the
6076 * registered callback methods.
6077 */
6078DECLINLINE(int) PDMDevHlpMMIORegisterR0(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
6079 const char *pszWrite, const char *pszRead)
6080{
6081 return pDevIns->pHlpR3->pfnMMIORegisterR0(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, NULL /*pszFill*/);
6082}
6083
6084/**
6085 * @copydoc PDMDEVHLPR3::pfnMMIORegister
6086 */
6087DECLINLINE(int) PDMDevHlpMMIORegisterEx(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
6088 uint32_t fFlags, PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead,
6089 PFNIOMMMIOFILL pfnFill, const char *pszDesc)
6090{
6091 return pDevIns->pHlpR3->pfnMMIORegister(pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill,
6092 fFlags, pszDesc);
6093}
6094
6095/**
6096 * @copydoc PDMDEVHLPR3::pfnMMIORegisterRC
6097 */
6098DECLINLINE(int) PDMDevHlpMMIORegisterRCEx(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
6099 const char *pszWrite, const char *pszRead, const char *pszFill)
6100{
6101 return pDevIns->pHlpR3->pfnMMIORegisterRC(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, pszFill);
6102}
6103
6104/**
6105 * @copydoc PDMDEVHLPR3::pfnMMIORegisterR0
6106 */
6107DECLINLINE(int) PDMDevHlpMMIORegisterR0Ex(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
6108 const char *pszWrite, const char *pszRead, const char *pszFill)
6109{
6110 return pDevIns->pHlpR3->pfnMMIORegisterR0(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, pszFill);
6111}
6112
6113/**
6114 * @copydoc PDMDEVHLPR3::pfnMMIODeregister
6115 */
6116DECLINLINE(int) PDMDevHlpMMIODeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange)
6117{
6118 return pDevIns->pHlpR3->pfnMMIODeregister(pDevIns, GCPhysStart, cbRange);
6119}
6120
6121/**
6122 * @copydoc PDMDEVHLPR3::pfnMmio2Create
6123 */
6124DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6125 uint32_t fFlags, const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion)
6126{
6127 return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6128}
6129
6130/**
6131 * @copydoc PDMDEVHLPR3::pfnMmio2Map
6132 */
6133DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6134{
6135 return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6136}
6137
6138/**
6139 * @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6140 */
6141DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6142{
6143 return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6144}
6145
6146/**
6147 * @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6148 */
6149DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6150{
6151 return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6152}
6153
6154/**
6155 * @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6156 */
6157DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6158{
6159 return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6160}
6161
6162#endif /* IN_RING3 */
6163#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
6164
6165/**
6166 * @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6167 */
6168DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6169 size_t offSub, size_t cbSub, void **ppvMapping)
6170{
6171 return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6172}
6173
6174#endif /* !IN_RING3 || DOXYGEN_RUNNING */
6175#ifdef IN_RING3
6176
6177/**
6178 * @copydoc PDMDEVHLPR3::pfnMMIO2Register
6179 */
6180DECLINLINE(int) PDMDevHlpMMIO2Register(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cb,
6181 uint32_t fFlags, void **ppv, const char *pszDesc)
6182{
6183 return pDevIns->pHlpR3->pfnMMIO2Register(pDevIns, pPciDev, iRegion, cb, fFlags, ppv, pszDesc);
6184}
6185
6186/**
6187 * @copydoc PDMDEVHLPR3::pfnMMIOExDeregister
6188 * @param pPciDev The PCI device the region is associated with, use
6189 * NULL to indicate it is not associated with a device.
6190 */
6191DECLINLINE(int) PDMDevHlpMMIOExDeregister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion)
6192{
6193 return pDevIns->pHlpR3->pfnMMIOExDeregister(pDevIns, pPciDev, iRegion);
6194}
6195
6196/**
6197 * @copydoc PDMDEVHLPR3::pfnMMIOExMap
6198 * @param pPciDev The PCI device the region is associated with, use
6199 * NULL to indicate it is not associated with a device.
6200 */
6201DECLINLINE(int) PDMDevHlpMMIOExMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
6202{
6203 return pDevIns->pHlpR3->pfnMMIOExMap(pDevIns, pPciDev, iRegion, GCPhys);
6204}
6205
6206/**
6207 * @copydoc PDMDEVHLPR3::pfnMMIOExUnmap
6208 * @param pPciDev The PCI device the region is associated with, use
6209 * NULL to indicate it is not associated with a device.
6210 */
6211DECLINLINE(int) PDMDevHlpMMIOExUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
6212{
6213 return pDevIns->pHlpR3->pfnMMIOExUnmap(pDevIns, pPciDev, iRegion, GCPhys);
6214}
6215
6216/**
6217 * @copydoc PDMDEVHLPR3::pfnMMIOExReduce
6218 */
6219DECLINLINE(int) PDMDevHlpMMIOExReduce(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion)
6220{
6221 return pDevIns->pHlpR3->pfnMMIOExReduce(pDevIns, pPciDev, iRegion, cbRegion);
6222}
6223
6224#ifdef VBOX_WITH_RAW_MODE_KEEP
6225/**
6226 * @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2
6227 */
6228DECLINLINE(int) PDMDevHlpMMHyperMapMMIO2(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
6229 const char *pszDesc, PRTRCPTR pRCPtr)
6230{
6231 return pDevIns->pHlpR3->pfnMMHyperMapMMIO2(pDevIns, pPciDev, iRegion, off, cb, pszDesc, pRCPtr);
6232}
6233#endif
6234
6235/**
6236 * @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel
6237 */
6238DECLINLINE(int) PDMDevHlpMMIO2MapKernel(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
6239 const char *pszDesc, PRTR0PTR pR0Ptr)
6240{
6241 return pDevIns->pHlpR3->pfnMMIO2MapKernel(pDevIns, pPciDev, iRegion, off, cb, pszDesc, pR0Ptr);
6242}
6243
6244/**
6245 * @copydoc PDMDEVHLPR3::pfnROMRegister
6246 */
6247DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6248 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc)
6249{
6250 return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6251}
6252
6253/**
6254 * @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6255 */
6256DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6257{
6258 return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6259}
6260
6261/**
6262 * Register a save state data unit.
6263 *
6264 * @returns VBox status.
6265 * @param pDevIns The device instance.
6266 * @param uVersion Data layout version number.
6267 * @param cbGuess The approximate amount of data in the unit.
6268 * Only for progress indicators.
6269 * @param pfnSaveExec Execute save callback, optional.
6270 * @param pfnLoadExec Execute load callback, optional.
6271 */
6272DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6273 PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6274{
6275 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /*pszBefore*/,
6276 NULL /*pfnLivePrep*/, NULL /*pfnLiveExec*/, NULL /*pfnLiveDone*/,
6277 NULL /*pfnSavePrep*/, pfnSaveExec, NULL /*pfnSaveDone*/,
6278 NULL /*pfnLoadPrep*/, pfnLoadExec, NULL /*pfnLoadDone*/);
6279}
6280
6281/**
6282 * Register a save state data unit with a live save callback as well.
6283 *
6284 * @returns VBox status.
6285 * @param pDevIns The device instance.
6286 * @param uVersion Data layout version number.
6287 * @param cbGuess The approximate amount of data in the unit.
6288 * Only for progress indicators.
6289 * @param pfnLiveExec Execute live callback, optional.
6290 * @param pfnSaveExec Execute save callback, optional.
6291 * @param pfnLoadExec Execute load callback, optional.
6292 */
6293DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6294 PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6295{
6296 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /*pszBefore*/,
6297 NULL /*pfnLivePrep*/, pfnLiveExec, NULL /*pfnLiveDone*/,
6298 NULL /*pfnSavePrep*/, pfnSaveExec, NULL /*pfnSaveDone*/,
6299 NULL /*pfnLoadPrep*/, pfnLoadExec, NULL /*pfnLoadDone*/);
6300}
6301
6302/**
6303 * @copydoc PDMDEVHLPR3::pfnSSMRegister
6304 */
6305DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6306 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6307 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6308 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6309{
6310 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6311 pfnLivePrep, pfnLiveExec, pfnLiveVote,
6312 pfnSavePrep, pfnSaveExec, pfnSaveDone,
6313 pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6314}
6315
6316/**
6317 * @copydoc PDMDEVHLPR3::pfnTMTimerCreate
6318 */
6319DECLINLINE(int) PDMDevHlpTMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6320 uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
6321{
6322 return pDevIns->pHlpR3->pfnTMTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
6323}
6324
6325/**
6326 * @copydoc PDMDEVHLPR3::pfnTimerCreate
6327 */
6328DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6329 uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6330{
6331 return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6332}
6333
6334#endif /* IN_RING3 */
6335
6336/**
6337 * @copydoc PDMDEVHLPR3::pfnTimerToPtr
6338 */
6339DECLINLINE(PTMTIMER) PDMDevHlpTimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6340{
6341 return pDevIns->CTX_SUFF(pHlp)->pfnTimerToPtr(pDevIns, hTimer);
6342}
6343
6344/**
6345 * @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6346 */
6347DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6348{
6349 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6350}
6351
6352/**
6353 * @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6354 */
6355DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6356{
6357 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6358}
6359
6360/**
6361 * @copydoc PDMDEVHLPR3::pfnTimerFromNano
6362 */
6363DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6364{
6365 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6366}
6367
6368/**
6369 * @copydoc PDMDEVHLPR3::pfnTimerGet
6370 */
6371DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6372{
6373 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6374}
6375
6376/**
6377 * @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6378 */
6379DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6380{
6381 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6382}
6383
6384/**
6385 * @copydoc PDMDEVHLPR3::pfnTimerGetNano
6386 */
6387DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6388{
6389 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6390}
6391
6392/**
6393 * @copydoc PDMDEVHLPR3::pfnTimerIsActive
6394 */
6395DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6396{
6397 return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6398}
6399
6400/**
6401 * @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6402 */
6403DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6404{
6405 return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6406}
6407
6408/**
6409 * @copydoc PDMDEVHLPR3::pfnTimerLock
6410 */
6411DECLINLINE(int) PDMDevHlpTimerLock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6412{
6413 return pDevIns->CTX_SUFF(pHlp)->pfnTimerLock(pDevIns, hTimer, rcBusy);
6414}
6415
6416/**
6417 * @copydoc PDMDEVHLPR3::pfnTimerSet
6418 */
6419DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6420{
6421 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6422}
6423
6424/**
6425 * @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6426 */
6427DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6428{
6429 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6430}
6431
6432/**
6433 * @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6434 */
6435DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6436{
6437 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6438}
6439
6440/**
6441 * @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6442 */
6443DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6444{
6445 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6446}
6447
6448/**
6449 * @copydoc PDMDEVHLPR3::pfnTimerSetNano
6450 */
6451DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6452{
6453 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6454}
6455
6456/**
6457 * @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6458 */
6459DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6460{
6461 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6462}
6463
6464/**
6465 * @copydoc PDMDEVHLPR3::pfnTimerStop
6466 */
6467DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6468{
6469 return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6470}
6471
6472/**
6473 * @copydoc PDMDEVHLPR3::pfnTimerUnlock
6474 */
6475DECLINLINE(void) PDMDevHlpTimerUnlock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6476{
6477 pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlock(pDevIns, hTimer);
6478}
6479
6480#ifdef IN_RING3
6481
6482/**
6483 * @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6484 */
6485DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6486{
6487 return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6488}
6489
6490/**
6491 * @copydoc PDMDEVHLPR3::pfnTimerSave
6492 */
6493DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6494{
6495 return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6496}
6497
6498/**
6499 * @copydoc PDMDEVHLPR3::pfnTimerLoad
6500 */
6501DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6502{
6503 return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6504}
6505
6506/**
6507 * @copydoc PDMDEVHLPR3::pfnTimerDestroy
6508 */
6509DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6510{
6511 return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6512}
6513
6514/**
6515 * @copydoc PDMDEVHLPR3::pfnTMUtcNow
6516 */
6517DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6518{
6519 return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6520}
6521
6522#endif
6523
6524/**
6525 * @copydoc PDMDEVHLPR3::pfnPhysRead
6526 */
6527DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6528{
6529 return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
6530}
6531
6532/**
6533 * @copydoc PDMDEVHLPR3::pfnPhysWrite
6534 */
6535DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6536{
6537 return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
6538}
6539
6540#ifdef IN_RING3
6541
6542/**
6543 * @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6544 */
6545DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6546{
6547 return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6548}
6549
6550/**
6551 * @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6552 */
6553DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6554 PPGMPAGEMAPLOCK pLock)
6555{
6556 return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6557}
6558
6559/**
6560 * @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6561 */
6562DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6563{
6564 pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6565}
6566
6567/**
6568 * @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6569 */
6570DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6571 uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6572{
6573 return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6574}
6575
6576/**
6577 * @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6578 */
6579DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6580 uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6581{
6582 return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6583}
6584
6585/**
6586 * @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6587 */
6588DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6589{
6590 pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6591}
6592
6593/**
6594 * @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6595 */
6596DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6597{
6598 return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6599}
6600
6601/**
6602 * @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6603 */
6604DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6605{
6606 return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6607}
6608
6609/**
6610 * @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6611 */
6612DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6613{
6614 return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6615}
6616
6617/**
6618 * @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6619 */
6620DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6621{
6622 return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6623}
6624
6625/**
6626 * @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6627 */
6628DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6629{
6630 return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6631}
6632
6633/**
6634 * @copydoc PDMDEVHLPR3::pfnMMHeapFree
6635 */
6636DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6637{
6638 pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6639}
6640#endif /* IN_RING3 */
6641
6642/**
6643 * @copydoc PDMDEVHLPR3::pfnVMState
6644 */
6645DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6646{
6647 return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6648}
6649
6650#ifdef IN_RING3
6651/**
6652 * @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6653 */
6654DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6655{
6656 return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6657}
6658#endif /* IN_RING3 */
6659
6660/**
6661 * @copydoc PDMDEVHLPR3::pfnVMSetError
6662 */
6663DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6664 const char *pszFormat, ...)
6665{
6666 va_list va;
6667 va_start(va, pszFormat);
6668 pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6669 va_end(va);
6670 return rc;
6671}
6672
6673/**
6674 * @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError
6675 */
6676DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6677 const char *pszFormat, ...)
6678{
6679 va_list va;
6680 int rc;
6681 va_start(va, pszFormat);
6682 rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6683 va_end(va);
6684 return rc;
6685}
6686
6687/**
6688 * VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6689 *
6690 * @returns VBox status code which must be passed up to the VMM. This will be
6691 * VINF_SUCCESS in non-strict builds.
6692 * @param pDevIns The device instance.
6693 * @param SRC_POS Use RT_SRC_POS.
6694 * @param pszFormat Message. (optional)
6695 * @param ... Message parameters.
6696 */
6697DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6698{
6699#ifdef VBOX_STRICT
6700# ifdef IN_RING3
6701 int rc;
6702 va_list args;
6703 va_start(args, pszFormat);
6704 rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6705 va_end(args);
6706 return rc;
6707# else
6708 NOREF(pDevIns);
6709 NOREF(pszFile);
6710 NOREF(iLine);
6711 NOREF(pszFunction);
6712 NOREF(pszFormat);
6713 return VINF_EM_DBG_STOP;
6714# endif
6715#else
6716 NOREF(pDevIns);
6717 NOREF(pszFile);
6718 NOREF(iLine);
6719 NOREF(pszFunction);
6720 NOREF(pszFormat);
6721 return VINF_SUCCESS;
6722#endif
6723}
6724
6725#ifdef IN_RING3
6726
6727/**
6728 * @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6729 */
6730DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6731{
6732 return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6733}
6734
6735/**
6736 * @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6737 */
6738DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6739{
6740 return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6741}
6742
6743/**
6744 * @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6745 */
6746DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6747{
6748 return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6749}
6750
6751/**
6752 * @copydoc PDMDEVHLPR3::pfnSTAMRegister
6753 */
6754DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc)
6755{
6756 pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6757}
6758
6759/**
6760 * Same as pfnSTAMRegister except that the name is specified in a
6761 * RTStrPrintf like fashion.
6762 *
6763 * @returns VBox status.
6764 * @param pDevIns Device instance of the DMA.
6765 * @param pvSample Pointer to the sample.
6766 * @param enmType Sample type. This indicates what pvSample is
6767 * pointing at.
6768 * @param enmVisibility Visibility type specifying whether unused
6769 * statistics should be visible or not.
6770 * @param enmUnit Sample unit.
6771 * @param pszDesc Sample description.
6772 * @param pszName Sample name format string, unix path style. If
6773 * this does not start with a '/', the default
6774 * prefix will be prepended, otherwise it will be
6775 * used as-is.
6776 * @param ... Arguments to the format string.
6777 */
6778DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6779 STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6780 const char *pszDesc, const char *pszName, ...)
6781{
6782 va_list va;
6783 va_start(va, pszName);
6784 pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6785 va_end(va);
6786}
6787
6788/**
6789 * Registers the device with the default PCI bus.
6790 *
6791 * @returns VBox status code.
6792 * @param pDevIns The device instance.
6793 * @param pPciDev The PCI device structure.
6794 * This must be kept in the instance data.
6795 * The PCI configuration must be initialized before registration.
6796 */
6797DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6798{
6799 return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /*fFlags*/,
6800 PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6801}
6802
6803/**
6804 * @copydoc PDMDEVHLPR3::pfnPCIRegister
6805 */
6806DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6807 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6808{
6809 return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6810}
6811
6812/**
6813 * Initialize MSI emulation support for the first PCI device.
6814 *
6815 * @returns VBox status code.
6816 * @param pDevIns The device instance.
6817 * @param pMsiReg MSI emulation registration structure.
6818 */
6819DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6820{
6821 return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6822}
6823
6824/**
6825 * @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6826 */
6827DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6828{
6829 return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6830}
6831
6832/**
6833 * Registers a I/O region (memory mapped or I/O ports) for the default PCI
6834 * device.
6835 *
6836 * @returns VBox status code.
6837 * @param pDevIns The device instance.
6838 * @param iRegion The region number.
6839 * @param cbRegion Size of the region.
6840 * @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
6841 * @param pfnMapUnmap Callback for doing the mapping.
6842 * @remarks The callback will be invoked holding the PDM lock. The device lock
6843 * is NOT take because that is very likely be a lock order violation.
6844 * @remarks Old callback style, won't get unmap calls.
6845 */
6846DECLINLINE(int) PDMDevHlpPCIIORegionRegister(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6847 PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnMapUnmap)
6848{
6849 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6850 PDMPCIDEV_IORGN_F_NO_HANDLE, UINT64_MAX, pfnMapUnmap);
6851}
6852
6853/**
6854 * @sa PDMDEVHLPR3::pfnPCIIORegionRegister
6855 * @remarks Old callback style, won't get unmap calls.
6856 */
6857DECLINLINE(int) PDMDevHlpPCIIORegionRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion,
6858 PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnMapUnmap)
6859{
6860 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
6861 PDMPCIDEV_IORGN_F_NO_HANDLE, UINT64_MAX, pfnMapUnmap);
6862}
6863
6864/**
6865 * Registers a I/O port region for the default PCI device.
6866 *
6867 * @returns VBox status code.
6868 * @param pDevIns The device instance.
6869 * @param iRegion The region number.
6870 * @param cbRegion Size of the region.
6871 * @param hIoPorts Handle to the I/O port region.
6872 */
6873DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
6874{
6875 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6876 PDMPCIDEV_IORGN_F_IOPORT_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
6877}
6878
6879/**
6880 * Registers a I/O port region for the default PCI device, custom map/unmap.
6881 *
6882 * @returns VBox status code.
6883 * @param pDevIns The device instance.
6884 * @param iRegion The region number.
6885 * @param cbRegion Size of the region.
6886 * @param pfnMapUnmap Callback for doing the mapping, optional. The
6887 * callback will be invoked holding only the PDM lock.
6888 * The device lock will _not_ be taken (due to lock
6889 * order).
6890 */
6891DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6892 PFNPCIIOREGIONMAP pfnMapUnmap)
6893{
6894 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6895 PDMPCIDEV_IORGN_F_NO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6896 UINT64_MAX, pfnMapUnmap);
6897}
6898
6899/**
6900 * Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
6901 * and registering an I/O port region for the default PCI device.
6902 *
6903 * @returns VBox status code.
6904 * @param pDevIns The device instance to register the ports with.
6905 * @param cPorts The count of I/O ports in the region (the size).
6906 * @param iPciRegion The PCI device region.
6907 * @param pfnOut Pointer to function which is gonna handle OUT
6908 * operations. Optional.
6909 * @param pfnIn Pointer to function which is gonna handle IN operations.
6910 * Optional.
6911 * @param pvUser User argument to pass to the callbacks.
6912 * @param pszDesc Pointer to description string. This must not be freed.
6913 * @param paExtDescs Extended per-port descriptions, optional. Partial range
6914 * coverage is allowed. This must not be freed.
6915 * @param phIoPorts Where to return the I/O port range handle.
6916 *
6917 */
6918DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
6919 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6920 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6921
6922{
6923 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /*fFlags*/, pDevIns->apPciDevs[0], iPciRegion << 16,
6924 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6925 if (RT_SUCCESS(rc))
6926 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
6927 PDMPCIDEV_IORGN_F_IOPORT_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6928 *phIoPorts, NULL /*pfnMapUnmap*/);
6929 return rc;
6930}
6931
6932/**
6933 * Registers an MMIO region for the default PCI device.
6934 *
6935 * @returns VBox status code.
6936 * @param pDevIns The device instance.
6937 * @param iRegion The region number.
6938 * @param cbRegion Size of the region.
6939 * @param enmType PCI_ADDRESS_SPACE_MEM or
6940 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6941 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6942 * @param hMmioRegion Handle to the MMIO region.
6943 * @param pfnMapUnmap Callback for doing the mapping, optional. The
6944 * callback will be invoked holding only the PDM lock.
6945 * The device lock will _not_ be taken (due to lock
6946 * order).
6947 */
6948DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
6949 IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
6950{
6951 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6952 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6953 hMmioRegion, pfnMapUnmap);
6954}
6955
6956/**
6957 * Registers an MMIO region for the default PCI device, extended version.
6958 *
6959 * @returns VBox status code.
6960 * @param pDevIns The device instance.
6961 * @param pPciDev The PCI device structure.
6962 * @param iRegion The region number.
6963 * @param cbRegion Size of the region.
6964 * @param enmType PCI_ADDRESS_SPACE_MEM or
6965 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6966 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6967 * @param hMmioRegion Handle to the MMIO region.
6968 * @param pfnMapUnmap Callback for doing the mapping, optional. The
6969 * callback will be invoked holding only the PDM lock.
6970 * The device lock will _not_ be taken (due to lock
6971 * order).
6972 */
6973DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
6974 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
6975 PFNPCIIOREGIONMAP pfnMapUnmap)
6976{
6977 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
6978 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6979 hMmioRegion, pfnMapUnmap);
6980}
6981
6982/**
6983 * Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
6984 * and registering an MMIO region for the default PCI device.
6985 *
6986 * @returns VBox status code.
6987 * @param pDevIns The device instance to register the ports with.
6988 * @param cbRegion The size of the region in bytes.
6989 * @param iPciRegion The PCI device region.
6990 * @param enmType PCI_ADDRESS_SPACE_MEM or
6991 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6992 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6993 * @param fFlags Flags, IOMMMIO_FLAGS_XXX.
6994 * @param pfnWrite Pointer to function which is gonna handle Write
6995 * operations.
6996 * @param pfnRead Pointer to function which is gonna handle Read
6997 * operations.
6998 * @param pvUser User argument to pass to the callbacks.
6999 * @param pszDesc Pointer to description string. This must not be freed.
7000 * @param phRegion Where to return the MMIO region handle.
7001 *
7002 */
7003DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7004 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7005 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7006
7007{
7008 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7009 pfnWrite, pfnRead, NULL /*pfnFill*/, pvUser, pszDesc, phRegion);
7010 if (RT_SUCCESS(rc))
7011 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7012 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7013 *phRegion, NULL /*pfnMapUnmap*/);
7014 return rc;
7015}
7016
7017
7018/**
7019 * Registers an MMIO2 region for the default PCI device.
7020 *
7021 * @returns VBox status code.
7022 * @param pDevIns The device instance.
7023 * @param iRegion The region number.
7024 * @param cbRegion Size of the region.
7025 * @param enmType PCI_ADDRESS_SPACE_MEM or
7026 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7027 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7028 * @param hMmio2Region Handle to the MMIO2 region.
7029 */
7030DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7031 PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7032{
7033 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7034 PDMPCIDEV_IORGN_F_MMIO2_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7035 hMmio2Region, NULL);
7036}
7037
7038/**
7039 * Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7040 * and registering an MMIO2 region for the default PCI device, extended edition.
7041 *
7042 * @returns VBox status code.
7043 * @param pDevIns The device instance to register the ports with.
7044 * @param cbRegion The size of the region in bytes.
7045 * @param iPciRegion The PCI device region.
7046 * @param enmType PCI_ADDRESS_SPACE_MEM or
7047 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7048 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7049 * @param pszDesc Pointer to description string. This must not be freed.
7050 * @param ppvMapping Where to store the address of the ring-3 mapping of
7051 * the memory.
7052 * @param phRegion Where to return the MMIO2 region handle.
7053 *
7054 */
7055DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7056 PCIADDRESSSPACE enmType, const char *pszDesc,
7057 void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7058
7059{
7060 int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /*fFlags*/,
7061 pszDesc, ppvMapping, phRegion);
7062 if (RT_SUCCESS(rc))
7063 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7064 PDMPCIDEV_IORGN_F_MMIO2_HANDLE, *phRegion, NULL /*pfnCallback*/);
7065 return rc;
7066}
7067
7068/**
7069 * Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7070 * and registering an MMIO2 region for the default PCI device.
7071 *
7072 * @returns VBox status code.
7073 * @param pDevIns The device instance to register the ports with.
7074 * @param cbRegion The size of the region in bytes.
7075 * @param iPciRegion The PCI device region.
7076 * @param enmType PCI_ADDRESS_SPACE_MEM or
7077 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7078 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7079 * @param fMmio2Flags To be defined, must be zero.
7080 * @param pfnMapUnmap Callback for doing the mapping, optional. The
7081 * callback will be invoked holding only the PDM lock.
7082 * The device lock will _not_ be taken (due to lock
7083 * order).
7084 * @param pszDesc Pointer to description string. This must not be freed.
7085 * @param ppvMapping Where to store the address of the ring-3 mapping of
7086 * the memory.
7087 * @param phRegion Where to return the MMIO2 region handle.
7088 *
7089 */
7090DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7091 PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7092 const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7093
7094{
7095 int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7096 pszDesc, ppvMapping, phRegion);
7097 if (RT_SUCCESS(rc))
7098 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7099 PDMPCIDEV_IORGN_F_MMIO2_HANDLE, *phRegion, pfnMapUnmap);
7100 return rc;
7101}
7102
7103/**
7104 * @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7105 */
7106DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7107 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7108{
7109 return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7110}
7111
7112/**
7113 * @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7114 */
7115DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7116 unsigned cb, uint32_t *pu32Value)
7117{
7118 return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7119}
7120
7121/**
7122 * @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7123 */
7124DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7125 unsigned cb, uint32_t u32Value)
7126{
7127 return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7128}
7129
7130#endif /* IN_RING3 */
7131
7132/**
7133 * Bus master physical memory read from the default PCI device.
7134 *
7135 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7136 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7137 * @param pDevIns The device instance.
7138 * @param GCPhys Physical address start reading from.
7139 * @param pvBuf Where to put the read bits.
7140 * @param cbRead How many bytes to read.
7141 * @thread Any thread, but the call may involve the emulation thread.
7142 */
7143DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7144{
7145 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead);
7146}
7147
7148/**
7149 * @copydoc PDMDEVHLPR3::pfnPCIPhysRead
7150 */
7151DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7152{
7153 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead);
7154}
7155
7156/**
7157 * Bus master physical memory write from the default PCI device.
7158 *
7159 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7160 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7161 * @param pDevIns The device instance.
7162 * @param GCPhys Physical address to write to.
7163 * @param pvBuf What to write.
7164 * @param cbWrite How many bytes to write.
7165 * @thread Any thread, but the call may involve the emulation thread.
7166 */
7167DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7168{
7169 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite);
7170}
7171
7172/**
7173 * @copydoc PDMDEVHLPR3::pfnPCIPhysWrite
7174 */
7175DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7176{
7177 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite);
7178}
7179
7180/**
7181 * Sets the IRQ for the default PCI device.
7182 *
7183 * @param pDevIns The device instance.
7184 * @param iIrq IRQ number to set.
7185 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7186 * @thread Any thread, but will involve the emulation thread.
7187 */
7188DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7189{
7190 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7191}
7192
7193/**
7194 * @copydoc PDMDEVHLPR3::pfnPCISetIrq
7195 */
7196DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7197{
7198 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7199}
7200
7201/**
7202 * Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7203 * the request when not called from EMT.
7204 *
7205 * @param pDevIns The device instance.
7206 * @param iIrq IRQ number to set.
7207 * @param iLevel IRQ level.
7208 * @thread Any thread, but will involve the emulation thread.
7209 */
7210DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7211{
7212 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7213}
7214
7215/**
7216 * @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7217 */
7218DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7219{
7220 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7221}
7222
7223/**
7224 * @copydoc PDMDEVHLPR3::pfnISASetIrq
7225 */
7226DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7227{
7228 pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7229}
7230
7231/**
7232 * @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7233 */
7234DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7235{
7236 pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7237}
7238
7239/**
7240 * @copydoc PDMDEVHLPR3::pfnIoApicSendMsi
7241 */
7242DECLINLINE(void) PDMDevHlpIoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue)
7243{
7244 pDevIns->CTX_SUFF(pHlp)->pfnIoApicSendMsi(pDevIns, GCPhys, uValue);
7245}
7246
7247#ifdef IN_RING3
7248
7249/**
7250 * @copydoc PDMDEVHLPR3::pfnDriverAttach
7251 */
7252DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE *ppBaseInterface, const char *pszDesc)
7253{
7254 return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7255}
7256
7257/**
7258 * @copydoc PDMDEVHLPR3::pfnDriverDetach
7259 */
7260DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7261{
7262 return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7263}
7264
7265/**
7266 * @copydoc PDMDEVHLPR3::pfnDriverReconfigure
7267 */
7268DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
7269 const char * const *papszDrivers, PCFGMNODE *papConfigs, uint32_t fFlags)
7270{
7271 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
7272}
7273
7274/**
7275 * Reconfigures with a single driver reattachement, no config, noflags.
7276 * @sa PDMDevHlpDriverReconfigure
7277 */
7278DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
7279{
7280 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
7281}
7282
7283/**
7284 * Reconfigures with a two drivers reattachement, no config, noflags.
7285 * @sa PDMDevHlpDriverReconfigure
7286 */
7287DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0, const char *pszDriver1)
7288{
7289 char const * apszDrivers[2];
7290 apszDrivers[0] = pszDriver0;
7291 apszDrivers[1] = pszDriver1;
7292 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
7293}
7294
7295/**
7296 * @copydoc PDMDEVHLPR3::pfnQueueCreatePtr
7297 */
7298DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7299 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName, PPDMQUEUE *ppQueue)
7300{
7301 return pDevIns->pHlpR3->pfnQueueCreatePtr(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
7302}
7303
7304/**
7305 * @copydoc PDMDEVHLPR3::pfnQueueCreate
7306 */
7307DECLINLINE(int) PDMDevHlpQueueCreateNew(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7308 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName, PDMQUEUEHANDLE *phQueue)
7309{
7310 return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7311}
7312
7313#endif /* IN_RING3 */
7314
7315/**
7316 * @copydoc PDMDEVHLPR3::pfnQueueAlloc
7317 */
7318DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7319{
7320 return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7321}
7322
7323/**
7324 * @copydoc PDMDEVHLPR3::pfnQueueInsert
7325 */
7326DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7327{
7328 pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7329}
7330
7331/**
7332 * @copydoc PDMDEVHLPR3::pfnQueueInsertEx
7333 */
7334DECLINLINE(void) PDMDevHlpQueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay)
7335{
7336 pDevIns->CTX_SUFF(pHlp)->pfnQueueInsertEx(pDevIns, hQueue, pItem, cNanoMaxDelay);
7337}
7338
7339/**
7340 * @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7341 */
7342DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7343{
7344 return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7345}
7346
7347#ifdef IN_RING3
7348/**
7349 * @copydoc PDMDEVHLPR3::pfnTaskCreate
7350 */
7351DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7352 PFNPDMTASKDEV pfnCallback, void *pvUser, PDMTASKHANDLE *phTask)
7353{
7354 return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7355}
7356#endif
7357
7358/**
7359 * @copydoc PDMDEVHLPR3::pfnTaskTrigger
7360 */
7361DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7362{
7363 return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7364}
7365
7366#ifdef IN_RING3
7367
7368/**
7369 * @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7370 */
7371DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7372{
7373 return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7374}
7375
7376/**
7377 * @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7378 */
7379DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7380{
7381 return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7382}
7383
7384#endif /* IN_RING3 */
7385
7386/**
7387 * @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7388 */
7389DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7390{
7391 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7392}
7393
7394/**
7395 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7396 */
7397DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7398{
7399 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7400}
7401
7402/**
7403 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7404 */
7405DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7406{
7407 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7408}
7409
7410/**
7411 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7412 */
7413DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7414{
7415 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7416}
7417
7418/**
7419 * @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7420 */
7421DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7422{
7423 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7424}
7425
7426#ifdef IN_RING3
7427
7428/**
7429 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7430 */
7431DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7432{
7433 return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7434}
7435
7436/**
7437 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7438 */
7439DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7440{
7441 return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7442}
7443
7444#endif /* IN_RING3 */
7445
7446/**
7447 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7448 */
7449DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7450{
7451 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7452}
7453
7454/**
7455 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7456 */
7457DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7458{
7459 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7460}
7461
7462/**
7463 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7464 */
7465DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7466{
7467 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7468}
7469
7470/**
7471 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7472 */
7473DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7474{
7475 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7476}
7477
7478/**
7479 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7480 */
7481DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7482{
7483 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7484}
7485
7486/**
7487 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7488 */
7489DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7490{
7491 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7492}
7493
7494#ifdef IN_RING3
7495
7496/**
7497 * Initializes a PDM critical section.
7498 *
7499 * The PDM critical sections are derived from the IPRT critical sections, but
7500 * works in RC and R0 as well.
7501 *
7502 * @returns VBox status code.
7503 * @param pDevIns The device instance.
7504 * @param pCritSect Pointer to the critical section.
7505 * @param SRC_POS Use RT_SRC_POS.
7506 * @param pszNameFmt Format string for naming the critical section.
7507 * For statistics and lock validation.
7508 * @param ... Arguments for the format string.
7509 */
7510DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7511 const char *pszNameFmt, ...)
7512{
7513 int rc;
7514 va_list va;
7515 va_start(va, pszNameFmt);
7516 rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7517 va_end(va);
7518 return rc;
7519}
7520
7521#endif /* IN_RING3 */
7522
7523/**
7524 * @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7525 */
7526DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7527{
7528 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7529}
7530
7531#ifdef IN_RING3
7532
7533/**
7534 * @copydoc PDMDEVHLPR3::pfnCritSectGetNopR0
7535 */
7536DECLINLINE(R0PTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopR0(PPDMDEVINS pDevIns)
7537{
7538 return pDevIns->pHlpR3->pfnCritSectGetNopR0(pDevIns);
7539}
7540
7541/**
7542 * @copydoc PDMDEVHLPR3::pfnCritSectGetNopRC
7543 */
7544DECLINLINE(RCPTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopRC(PPDMDEVINS pDevIns)
7545{
7546 return pDevIns->pHlpR3->pfnCritSectGetNopRC(pDevIns);
7547}
7548
7549#endif /* IN_RING3 */
7550
7551/**
7552 * @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7553 */
7554DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7555{
7556 return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7557}
7558
7559/**
7560 * @copydoc PDMCritSectEnter
7561 * @param pDevIns The device instance.
7562 */
7563DECLINLINE(int) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7564{
7565 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7566}
7567
7568/**
7569 * @copydoc PDMCritSectEnterDebug
7570 * @param pDevIns The device instance.
7571 */
7572DECLINLINE(int) PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7573{
7574 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7575}
7576
7577/**
7578 * @copydoc PDMCritSectTryEnter
7579 * @param pDevIns The device instance.
7580 */
7581DECLINLINE(int) PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7582{
7583 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7584}
7585
7586/**
7587 * @copydoc PDMCritSectTryEnterDebug
7588 * @param pDevIns The device instance.
7589 */
7590DECLINLINE(int) PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7591{
7592 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7593}
7594
7595/**
7596 * @copydoc PDMCritSectLeave
7597 * @param pDevIns The device instance.
7598 */
7599DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7600{
7601 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7602}
7603
7604/**
7605 * @copydoc PDMCritSectIsOwner
7606 * @param pDevIns The device instance.
7607 */
7608DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7609{
7610 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7611}
7612
7613/**
7614 * @copydoc PDMCritSectIsInitialized
7615 * @param pDevIns The device instance.
7616 */
7617DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7618{
7619 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
7620}
7621
7622/**
7623 * @copydoc PDMCritSectHasWaiters
7624 * @param pDevIns The device instance.
7625 */
7626DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7627{
7628 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
7629}
7630
7631/**
7632 * @copydoc PDMCritSectGetRecursion
7633 * @param pDevIns The device instance.
7634 */
7635DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7636{
7637 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
7638}
7639
7640#if defined(IN_RING3) || defined(IN_RING0)
7641/**
7642 * @copydoc PDMHCCritSectScheduleExitEvent
7643 * @param pDevIns The device instance.
7644 */
7645DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
7646{
7647 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
7648}
7649#endif
7650
7651/* Strict build: Remap the two enter calls to the debug versions. */
7652#ifdef VBOX_STRICT
7653# ifdef IPRT_INCLUDED_asm_h
7654# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7655# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7656# else
7657# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
7658# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
7659# endif
7660#endif
7661
7662#if defined(IN_RING3) || defined(DOXYGEN_RUNNING)
7663
7664/**
7665 * @copydoc PDMR3CritSectDelete
7666 * @param pDevIns The device instance.
7667 */
7668DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7669{
7670 return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
7671}
7672
7673/**
7674 * @copydoc PDMDEVHLPR3::pfnThreadCreate
7675 */
7676DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
7677 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
7678{
7679 return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
7680}
7681
7682/**
7683 * @copydoc PDMR3ThreadDestroy
7684 * @param pDevIns The device instance.
7685 */
7686DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
7687{
7688 return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
7689}
7690
7691/**
7692 * @copydoc PDMR3ThreadIAmSuspending
7693 * @param pDevIns The device instance.
7694 */
7695DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7696{
7697 return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
7698}
7699
7700/**
7701 * @copydoc PDMR3ThreadIAmRunning
7702 * @param pDevIns The device instance.
7703 */
7704DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7705{
7706 return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
7707}
7708
7709/**
7710 * @copydoc PDMR3ThreadSleep
7711 * @param pDevIns The device instance.
7712 */
7713DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
7714{
7715 return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
7716}
7717
7718/**
7719 * @copydoc PDMR3ThreadSuspend
7720 * @param pDevIns The device instance.
7721 */
7722DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7723{
7724 return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
7725}
7726
7727/**
7728 * @copydoc PDMR3ThreadResume
7729 * @param pDevIns The device instance.
7730 */
7731DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7732{
7733 return pDevIns->pHlpR3->pfnThreadResume(pThread);
7734}
7735
7736/**
7737 * @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
7738 */
7739DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
7740{
7741 return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
7742}
7743
7744/**
7745 * @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
7746 */
7747DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
7748{
7749 pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
7750}
7751
7752/**
7753 * @copydoc PDMDEVHLPR3::pfnA20Set
7754 */
7755DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
7756{
7757 pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
7758}
7759
7760/**
7761 * @copydoc PDMDEVHLPR3::pfnRTCRegister
7762 */
7763DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
7764{
7765 return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
7766}
7767
7768/**
7769 * @copydoc PDMDEVHLPR3::pfnPCIBusRegister
7770 */
7771DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus)
7772{
7773 return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
7774}
7775
7776/**
7777 * @copydoc PDMDEVHLPR3::pfnPICRegister
7778 */
7779DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
7780{
7781 return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
7782}
7783
7784/**
7785 * @copydoc PDMDEVHLPR3::pfnApicRegister
7786 */
7787DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
7788{
7789 return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
7790}
7791
7792/**
7793 * @copydoc PDMDEVHLPR3::pfnIoApicRegister
7794 */
7795DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
7796{
7797 return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
7798}
7799
7800/**
7801 * @copydoc PDMDEVHLPR3::pfnHpetRegister
7802 */
7803DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
7804{
7805 return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
7806}
7807
7808/**
7809 * @copydoc PDMDEVHLPR3::pfnPciRawRegister
7810 */
7811DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
7812{
7813 return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
7814}
7815
7816/**
7817 * @copydoc PDMDEVHLPR3::pfnDMACRegister
7818 */
7819DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
7820{
7821 return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
7822}
7823
7824/**
7825 * @copydoc PDMDEVHLPR3::pfnDMARegister
7826 */
7827DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
7828{
7829 return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
7830}
7831
7832/**
7833 * @copydoc PDMDEVHLPR3::pfnDMAReadMemory
7834 */
7835DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead)
7836{
7837 return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
7838}
7839
7840/**
7841 * @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
7842 */
7843DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten)
7844{
7845 return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
7846}
7847
7848/**
7849 * @copydoc PDMDEVHLPR3::pfnDMASetDREQ
7850 */
7851DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
7852{
7853 return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
7854}
7855
7856/**
7857 * @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
7858 */
7859DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
7860{
7861 return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
7862}
7863
7864/**
7865 * @copydoc PDMDEVHLPR3::pfnDMASchedule
7866 */
7867DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
7868{
7869 pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
7870}
7871
7872/**
7873 * @copydoc PDMDEVHLPR3::pfnCMOSWrite
7874 */
7875DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
7876{
7877 return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
7878}
7879
7880/**
7881 * @copydoc PDMDEVHLPR3::pfnCMOSRead
7882 */
7883DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
7884{
7885 return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
7886}
7887
7888/**
7889 * @copydoc PDMDEVHLPR3::pfnCallR0
7890 */
7891DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
7892{
7893 return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
7894}
7895
7896/**
7897 * @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
7898 */
7899DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
7900{
7901 return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
7902}
7903
7904/**
7905 * @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
7906 */
7907DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
7908{
7909 return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
7910}
7911
7912/**
7913 * @copydoc PDMDEVHLPR3::pfnGetUVM
7914 */
7915DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
7916{
7917 return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
7918}
7919
7920#endif /* IN_RING3 || DOXYGEN_RUNNING */
7921
7922#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
7923
7924/**
7925 * @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
7926 */
7927DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
7928{
7929 return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
7930}
7931
7932/**
7933 * @copydoc PDMDEVHLPR0::pfnPICSetUpContext
7934 */
7935DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
7936{
7937 return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
7938}
7939
7940/**
7941 * @copydoc PDMDEVHLPR0::pfnApicSetUpContext
7942 */
7943DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
7944{
7945 return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
7946}
7947
7948/**
7949 * @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
7950 */
7951DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
7952{
7953 return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
7954}
7955
7956/**
7957 * @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
7958 */
7959DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
7960{
7961 return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
7962}
7963
7964#endif /* !IN_RING3 || DOXYGEN_RUNNING */
7965
7966/**
7967 * @copydoc PDMDEVHLPR3::pfnGetVM
7968 */
7969DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
7970{
7971 return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
7972}
7973
7974/**
7975 * @copydoc PDMDEVHLPR3::pfnGetVMCPU
7976 */
7977DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
7978{
7979 return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
7980}
7981
7982/**
7983 * @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
7984 */
7985DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
7986{
7987 return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
7988}
7989
7990/**
7991 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
7992 */
7993DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
7994{
7995 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
7996}
7997
7998/**
7999 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8000 */
8001DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8002{
8003 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8004}
8005
8006/**
8007 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8008 */
8009DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8010{
8011 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8012}
8013
8014#ifdef IN_RING3
8015
8016/**
8017 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8018 */
8019DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8020{
8021 return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
8022}
8023
8024/**
8025 * @copydoc PDMDEVHLPR3::pfnFirmwareRegister
8026 */
8027DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
8028{
8029 return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
8030}
8031
8032/**
8033 * @copydoc PDMDEVHLPR3::pfnVMReset
8034 */
8035DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
8036{
8037 return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
8038}
8039
8040/**
8041 * @copydoc PDMDEVHLPR3::pfnVMSuspend
8042 */
8043DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8044{
8045 return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8046}
8047
8048/**
8049 * @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8050 */
8051DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8052{
8053 return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8054}
8055
8056/**
8057 * @copydoc PDMDEVHLPR3::pfnVMPowerOff
8058 */
8059DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8060{
8061 return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8062}
8063
8064#endif /* IN_RING3 */
8065
8066/**
8067 * @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8068 */
8069DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8070{
8071 return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8072}
8073
8074#ifdef IN_RING3
8075
8076/**
8077 * @copydoc PDMDEVHLPR3::pfnGetCpuId
8078 */
8079DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
8080{
8081 pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8082}
8083
8084/**
8085 * @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8086 */
8087DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8088{
8089 return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8090}
8091
8092/**
8093 * @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8094 */
8095DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8096{
8097 return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8098}
8099
8100/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
8101# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8102 do { \
8103 uint32_t u32GetEnumTmp = 0; \
8104 int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
8105 AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8106 (a_enmDst) = (a_EnumType)u32GetEnumTmp; \
8107 AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
8108 } while (0)
8109
8110/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
8111# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8112 do { \
8113 uint8_t bGetEnumTmp = 0; \
8114 int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
8115 AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8116 (a_enmDst) = (a_EnumType)bGetEnumTmp; \
8117 } while (0)
8118
8119#endif /* IN_RING3 */
8120
8121/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
8122typedef struct PDMDEVREGCB *PPDMDEVREGCB;
8123
8124/**
8125 * Callbacks for VBoxDeviceRegister().
8126 */
8127typedef struct PDMDEVREGCB
8128{
8129 /** Interface version.
8130 * This is set to PDM_DEVREG_CB_VERSION. */
8131 uint32_t u32Version;
8132
8133 /**
8134 * Registers a device with the current VM instance.
8135 *
8136 * @returns VBox status code.
8137 * @param pCallbacks Pointer to the callback table.
8138 * @param pReg Pointer to the device registration record.
8139 * This data must be permanent and readonly.
8140 */
8141 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
8142} PDMDEVREGCB;
8143
8144/** Current version of the PDMDEVREGCB structure. */
8145#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
8146
8147
8148/**
8149 * The VBoxDevicesRegister callback function.
8150 *
8151 * PDM will invoke this function after loading a device module and letting
8152 * the module decide which devices to register and how to handle conflicts.
8153 *
8154 * @returns VBox status code.
8155 * @param pCallbacks Pointer to the callback table.
8156 * @param u32Version VBox version number.
8157 */
8158typedef DECLCALLBACK(int) FNPDMVBOXDEVICESREGISTER(PPDMDEVREGCB pCallbacks, uint32_t u32Version);
8159
8160/** @} */
8161
8162RT_C_DECLS_END
8163
8164#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */
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