pdmdev.h@ 86661

Last change on this file since 86661 was 86661, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654: Add PDM interfaces for pfnPCIPhysGCPhys2CCPtr[ReadOnly] and merge IOMMU memory read/write interface into memory access interface with a flag.
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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmqueue.h>
34	#include <VBox/vmm/pdmtask.h>
35	#ifdef IN_RING3
36	# include <VBox/vmm/pdmthread.h>
37	#endif
38	#include <VBox/vmm/pdmifs.h>
39	#include <VBox/vmm/pdmins.h>
40	#include <VBox/vmm/pdmcommon.h>
41	#include <VBox/vmm/pdmpcidev.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/tm.h>
44	#include <VBox/vmm/ssm.h>
45	#include <VBox/vmm/cfgm.h>
46	#include <VBox/vmm/cpum.h>
47	#include <VBox/vmm/dbgf.h>
48	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
49	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
50	#include <VBox/msi.h>
51	#include <iprt/stdarg.h>
52	#include <iprt/list.h>
53
54
55	RT_C_DECLS_BEGIN
56
57	/** @defgroup grp_pdm_device The PDM Devices API
58	* @ingroup grp_pdm
59	* @{
60	*/
61
62	/**
63	* Construct a device instance for a VM.
64	*
65	* @returns VBox status.
66	* @param pDevIns The device instance data. If the registration structure
67	* is needed, it can be accessed thru pDevIns->pReg.
68	* @param iInstance Instance number. Use this to figure out which registers
69	* and such to use. The instance number is also found in
70	* pDevIns->iInstance, but since it's likely to be
71	* frequently used PDM passes it as parameter.
72	* @param pCfg Configuration node handle for the driver. This is
73	* expected to be in high demand in the constructor and is
74	* therefore passed as an argument. When using it at other
75	* times, it can be found in pDevIns->pCfg.
76	*/
77	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
78	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
79	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
80
81	/**
82	* Destruct a device instance.
83	*
84	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
85	* resources can be freed correctly.
86	*
87	* @returns VBox status.
88	* @param pDevIns The device instance data.
89	*
90	* @remarks The device critical section is not entered. The routine may delete
91	* the critical section, so the caller cannot exit it.
92	*/
93	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
94	/** Pointer to a FNPDMDEVDESTRUCT() function. */
95	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
96
97	/**
98	* Device relocation callback.
99	*
100	* This is called when the instance data has been relocated in raw-mode context
101	* (RC). It is also called when the RC hypervisor selects changes. The device
102	* must fixup all necessary pointers and re-query all interfaces to other RC
103	* devices and drivers.
104	*
105	* Before the RC code is executed the first time, this function will be called
106	* with a 0 delta so RC pointer calculations can be one in one place.
107	*
108	* @param pDevIns Pointer to the device instance.
109	* @param offDelta The relocation delta relative to the old location.
110	*
111	* @remarks A relocation CANNOT fail.
112	*
113	* @remarks The device critical section is not entered. The relocations should
114	* not normally require any locking.
115	*/
116	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
117	/** Pointer to a FNPDMDEVRELOCATE() function. */
118	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
119
120	/**
121	* Power On notification.
122	*
123	* @returns VBox status.
124	* @param pDevIns The device instance data.
125	*
126	* @remarks Caller enters the device critical section.
127	*/
128	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
129	/** Pointer to a FNPDMDEVPOWERON() function. */
130	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
131
132	/**
133	* Reset notification.
134	*
135	* @returns VBox status.
136	* @param pDevIns The device instance data.
137	*
138	* @remarks Caller enters the device critical section.
139	*/
140	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
141	/** Pointer to a FNPDMDEVRESET() function. */
142	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
143
144	/**
145	* Soft reset notification.
146	*
147	* This is mainly for emulating the 286 style protected mode exits, in which
148	* most devices should remain in their current state.
149	*
150	* @returns VBox status.
151	* @param pDevIns The device instance data.
152	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
153	*
154	* @remarks Caller enters the device critical section.
155	*/
156	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
157	/** Pointer to a FNPDMDEVSOFTRESET() function. */
158	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
159
160	/** @name PDMVMRESET_F_XXX - VM reset flags.
161	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
162	* reset via PDMDevHlpVMReset.
163	* @{ */
164	/** Unknown reason. */
165	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
166	/** GIM triggered reset. */
167	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
168	/** The last source always causing hard resets. */
169	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
170	/** ACPI triggered reset. */
171	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
172	/** PS/2 system port A (92h) reset. */
173	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
174	/** Keyboard reset. */
175	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
176	/** Tripple fault. */
177	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
178	/** Reset source mask. */
179	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
180	/** @} */
181
182	/**
183	* Suspend notification.
184	*
185	* @returns VBox status.
186	* @param pDevIns The device instance data.
187	* @thread EMT(0)
188	*
189	* @remarks Caller enters the device critical section.
190	*/
191	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
192	/** Pointer to a FNPDMDEVSUSPEND() function. */
193	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
194
195	/**
196	* Resume notification.
197	*
198	* @returns VBox status.
199	* @param pDevIns The device instance data.
200	*
201	* @remarks Caller enters the device critical section.
202	*/
203	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
204	/** Pointer to a FNPDMDEVRESUME() function. */
205	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
206
207	/**
208	* Power Off notification.
209	*
210	* This is always called when VMR3PowerOff is called.
211	* There will be no callback when hot plugging devices.
212	*
213	* @param pDevIns The device instance data.
214	* @thread EMT(0)
215	*
216	* @remarks Caller enters the device critical section.
217	*/
218	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
219	/** Pointer to a FNPDMDEVPOWEROFF() function. */
220	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
221
222	/**
223	* Attach command.
224	*
225	* This is called to let the device attach to a driver for a specified LUN
226	* at runtime. This is not called during VM construction, the device
227	* constructor has to attach to all the available drivers.
228	*
229	* This is like plugging in the keyboard or mouse after turning on the PC.
230	*
231	* @returns VBox status code.
232	* @param pDevIns The device instance.
233	* @param iLUN The logical unit which is being attached.
234	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
235	*
236	* @remarks Caller enters the device critical section.
237	*/
238	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
239	/** Pointer to a FNPDMDEVATTACH() function. */
240	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
241
242	/**
243	* Detach notification.
244	*
245	* This is called when a driver is detaching itself from a LUN of the device.
246	* The device should adjust its state to reflect this.
247	*
248	* This is like unplugging the network cable to use it for the laptop or
249	* something while the PC is still running.
250	*
251	* @param pDevIns The device instance.
252	* @param iLUN The logical unit which is being detached.
253	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
254	*
255	* @remarks Caller enters the device critical section.
256	*/
257	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
258	/** Pointer to a FNPDMDEVDETACH() function. */
259	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
260
261	/**
262	* Query the base interface of a logical unit.
263	*
264	* @returns VBOX status code.
265	* @param pDevIns The device instance.
266	* @param iLUN The logicial unit to query.
267	* @param ppBase Where to store the pointer to the base interface of the LUN.
268	*
269	* @remarks The device critical section is not entered.
270	*/
271	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
272	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
273	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
274
275	/**
276	* Init complete notification (after ring-0 & RC init since 5.1).
277	*
278	* This can be done to do communication with other devices and other
279	* initialization which requires everything to be in place.
280	*
281	* @returns VBOX status code.
282	* @param pDevIns The device instance.
283	*
284	* @remarks Caller enters the device critical section.
285	*/
286	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
287	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
288	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
289
290
291	/**
292	* The context of a pfnMemSetup call.
293	*/
294	typedef enum PDMDEVMEMSETUPCTX
295	{
296	/** Invalid zero value. */
297	PDMDEVMEMSETUPCTX_INVALID = 0,
298	/** After construction. */
299	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
300	/** After reset. */
301	PDMDEVMEMSETUPCTX_AFTER_RESET,
302	/** Type size hack. */
303	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
304	} PDMDEVMEMSETUPCTX;
305
306
307	/**
308	* PDM Device Registration Structure.
309	*
310	* This structure is used when registering a device from VBoxInitDevices() in HC
311	* Ring-3. PDM will continue use till the VM is terminated.
312	*
313	* @note The first part is the same in every context.
314	*/
315	typedef struct PDMDEVREGR3
316	{
317	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
318	uint32_t u32Version;
319	/** Reserved, must be zero. */
320	uint32_t uReserved0;
321	/** Device name, must match the ring-3 one. */
322	char szName[32];
323	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
324	uint32_t fFlags;
325	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
326	uint32_t fClass;
327	/** Maximum number of instances (per VM). */
328	uint32_t cMaxInstances;
329	/** The shared data structure version number. */
330	uint32_t uSharedVersion;
331	/** Size of the instance data. */
332	uint32_t cbInstanceShared;
333	/** Size of the ring-0 instance data. */
334	uint32_t cbInstanceCC;
335	/** Size of the raw-mode instance data. */
336	uint32_t cbInstanceRC;
337	/** Max number of PCI devices. */
338	uint16_t cMaxPciDevices;
339	/** Max number of MSI-X vectors in any of the PCI devices. */
340	uint16_t cMaxMsixVectors;
341	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
342	* remain unchanged from registration till VM destruction. */
343	const char *pszDescription;
344
345	/** Name of the raw-mode context module (no path).
346	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
347	const char *pszRCMod;
348	/** Name of the ring-0 module (no path).
349	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
350	const char *pszR0Mod;
351
352	/** Construct instance - required. */
353	PFNPDMDEVCONSTRUCT pfnConstruct;
354	/** Destruct instance - optional.
355	* Critical section NOT entered (will be destroyed). */
356	PFNPDMDEVDESTRUCT pfnDestruct;
357	/** Relocation command - optional.
358	* Critical section NOT entered. */
359	PFNPDMDEVRELOCATE pfnRelocate;
360	/**
361	* Memory setup callback.
362	*
363	* @param pDevIns The device instance data.
364	* @param enmCtx Indicates the context of the call.
365	* @remarks The critical section is entered prior to calling this method.
366	*/
367	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
368	/** Power on notification - optional.
369	* Critical section is entered. */
370	PFNPDMDEVPOWERON pfnPowerOn;
371	/** Reset notification - optional.
372	* Critical section is entered. */
373	PFNPDMDEVRESET pfnReset;
374	/** Suspend notification - optional.
375	* Critical section is entered. */
376	PFNPDMDEVSUSPEND pfnSuspend;
377	/** Resume notification - optional.
378	* Critical section is entered. */
379	PFNPDMDEVRESUME pfnResume;
380	/** Attach command - optional.
381	* Critical section is entered. */
382	PFNPDMDEVATTACH pfnAttach;
383	/** Detach notification - optional.
384	* Critical section is entered. */
385	PFNPDMDEVDETACH pfnDetach;
386	/** Query a LUN base interface - optional.
387	* Critical section is NOT entered. */
388	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
389	/** Init complete notification - optional.
390	* Critical section is entered. */
391	PFNPDMDEVINITCOMPLETE pfnInitComplete;
392	/** Power off notification - optional.
393	* Critical section is entered. */
394	PFNPDMDEVPOWEROFF pfnPowerOff;
395	/** Software system reset notification - optional.
396	* Critical section is entered. */
397	PFNPDMDEVSOFTRESET pfnSoftReset;
398
399	/** @name Reserved for future extensions, must be zero.
400	* @{ */
401	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
402	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
403	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
406	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
407	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
408	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
409	/** @} */
410
411	/** Initialization safty marker. */
412	uint32_t u32VersionEnd;
413	} PDMDEVREGR3;
414	/** Pointer to a PDM Device Structure. */
415	typedef PDMDEVREGR3 *PPDMDEVREGR3;
416	/** Const pointer to a PDM Device Structure. */
417	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
418	/** Current DEVREGR3 version number. */
419	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
420
421
422	/** PDM Device Flags.
423	* @{ */
424	/** This flag is used to indicate that the device has a R0 component. */
425	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
426	/** Requires the ring-0 component, ignore configuration values. */
427	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
428	/** Requires the ring-0 component, ignore configuration values. */
429	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
430
431	/** This flag is used to indicate that the device has a RC component. */
432	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
433	/** Requires the raw-mode component, ignore configuration values. */
434	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
435	/** Requires the raw-mode component, ignore configuration values. */
436	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
437
438	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
439	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
440
441	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
442	* The bit count for the current host.
443	* @note Superfluous, but still around for hysterical raisins. */
444	#if HC_ARCH_BITS == 32
445	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
446	#elif HC_ARCH_BITS == 64
447	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
448	#else
449	# error Unsupported HC_ARCH_BITS value.
450	#endif
451	/** The host bit count mask. */
452	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
453
454	/** The device support only 32-bit guests. */
455	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
456	/** The device support only 64-bit guests. */
457	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
458	/** The device support both 32-bit & 64-bit guests. */
459	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
460	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
461	* The guest bit count for the current compilation. */
462	#if GC_ARCH_BITS == 32
463	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
464	#elif GC_ARCH_BITS == 64
465	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
466	#else
467	# error Unsupported GC_ARCH_BITS value.
468	#endif
469	/** The guest bit count mask. */
470	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
471
472	/** A convenience. */
473	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
474
475	/** Indicates that the device needs to be notified before the drivers when suspending. */
476	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
477	/** Indicates that the device needs to be notified before the drivers when powering off. */
478	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
479	/** Indicates that the device needs to be notified before the drivers when resetting. */
480	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
481
482	/** This flag is used to indicate that the device has been converted to the
483	* new device style. */
484	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
485
486	/** @} */
487
488
489	/** PDM Device Classes.
490	* The order is important, lower bit earlier instantiation.
491	* @{ */
492	/** Architecture device. */
493	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
494	/** Architecture BIOS device. */
495	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
496	/** PCI bus brigde. */
497	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
498	/** PCI built-in device (e.g. PCI root complex devices). */
499	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
500	/** Input device (mouse, keyboard, joystick, HID, ...). */
501	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
502	/** Interrupt controller (PIC). */
503	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
504	/** Interval controoler (PIT). */
505	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
506	/** RTC/CMOS. */
507	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
508	/** DMA controller. */
509	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
510	/** VMM Device. */
511	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
512	/** Graphics device, like VGA. */
513	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
514	/** Storage controller device. */
515	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
516	/** Network interface controller. */
517	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
518	/** Audio. */
519	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
520	/** USB HIC. */
521	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
522	/** ACPI. */
523	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
524	/** Serial controller device. */
525	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
526	/** Parallel controller device */
527	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
528	/** Host PCI pass-through device */
529	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
530	/** Misc devices (always last). */
531	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
532	/** @} */
533
534
535	/**
536	* PDM Device Registration Structure, ring-0.
537	*
538	* This structure is used when registering a device from VBoxInitDevices() in HC
539	* Ring-0. PDM will continue use till the VM is terminated.
540	*/
541	typedef struct PDMDEVREGR0
542	{
543	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
544	uint32_t u32Version;
545	/** Reserved, must be zero. */
546	uint32_t uReserved0;
547	/** Device name, must match the ring-3 one. */
548	char szName[32];
549	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
550	uint32_t fFlags;
551	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
552	uint32_t fClass;
553	/** Maximum number of instances (per VM). */
554	uint32_t cMaxInstances;
555	/** The shared data structure version number. */
556	uint32_t uSharedVersion;
557	/** Size of the instance data. */
558	uint32_t cbInstanceShared;
559	/** Size of the ring-0 instance data. */
560	uint32_t cbInstanceCC;
561	/** Size of the raw-mode instance data. */
562	uint32_t cbInstanceRC;
563	/** Max number of PCI devices. */
564	uint16_t cMaxPciDevices;
565	/** Max number of MSI-X vectors in any of the PCI devices. */
566	uint16_t cMaxMsixVectors;
567	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
568	* remain unchanged from registration till VM destruction. */
569	const char *pszDescription;
570
571	/**
572	* Early construction callback (optional).
573	*
574	* This is called right after the device instance structure has been allocated
575	* and before the ring-3 constructor gets called.
576	*
577	* @returns VBox status code.
578	* @param pDevIns The device instance data.
579	* @note The destructure is always called, regardless of the return status.
580	*/
581	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
582
583	/**
584	* Regular construction callback (optional).
585	*
586	* This is called after (or during) the ring-3 constructor.
587	*
588	* @returns VBox status code.
589	* @param pDevIns The device instance data.
590	* @note The destructure is always called, regardless of the return status.
591	*/
592	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
593
594	/**
595	* Destructor (optional).
596	*
597	* This is called after the ring-3 destruction. This is not called if ring-3
598	* fails to trigger it (e.g. process is killed or crashes).
599	*
600	* @param pDevIns The device instance data.
601	*/
602	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
603
604	/**
605	* Final destructor (optional).
606	*
607	* This is called right before the memory is freed, which happens when the
608	* VM/GVM object is destroyed. This is always called.
609	*
610	* @param pDevIns The device instance data.
611	*/
612	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
613
614	/**
615	* Generic request handler (optional).
616	*
617	* @param pDevIns The device instance data.
618	* @param uReq Device specific request.
619	* @param uArg Request argument.
620	*/
621	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
622
623	/** @name Reserved for future extensions, must be zero.
624	* @{ */
625	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
626	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
627	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
630	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
631	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
632	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
633	/** @} */
634
635	/** Initialization safty marker. */
636	uint32_t u32VersionEnd;
637	} PDMDEVREGR0;
638	/** Pointer to a ring-0 PDM device registration structure. */
639	typedef PDMDEVREGR0 *PPDMDEVREGR0;
640	/** Pointer to a const ring-0 PDM device registration structure. */
641	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
642	/** Current DEVREGR0 version number. */
643	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
644
645
646	/**
647	* PDM Device Registration Structure, raw-mode
648	*
649	* At the moment, this structure is mostly here to match the other two contexts.
650	*/
651	typedef struct PDMDEVREGRC
652	{
653	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
654	uint32_t u32Version;
655	/** Reserved, must be zero. */
656	uint32_t uReserved0;
657	/** Device name, must match the ring-3 one. */
658	char szName[32];
659	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
660	uint32_t fFlags;
661	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
662	uint32_t fClass;
663	/** Maximum number of instances (per VM). */
664	uint32_t cMaxInstances;
665	/** The shared data structure version number. */
666	uint32_t uSharedVersion;
667	/** Size of the instance data. */
668	uint32_t cbInstanceShared;
669	/** Size of the ring-0 instance data. */
670	uint32_t cbInstanceCC;
671	/** Size of the raw-mode instance data. */
672	uint32_t cbInstanceRC;
673	/** Max number of PCI devices. */
674	uint16_t cMaxPciDevices;
675	/** Max number of MSI-X vectors in any of the PCI devices. */
676	uint16_t cMaxMsixVectors;
677	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
678	* remain unchanged from registration till VM destruction. */
679	const char *pszDescription;
680
681	/**
682	* Constructor callback.
683	*
684	* This is called much later than both the ring-0 and ring-3 constructors, since
685	* raw-mode v2 require a working VMM to run actual code.
686	*
687	* @returns VBox status code.
688	* @param pDevIns The device instance data.
689	* @note The destructure is always called, regardless of the return status.
690	*/
691	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
692
693	/** @name Reserved for future extensions, must be zero.
694	* @{ */
695	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
696	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
697	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
700	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
701	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
702	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
703	/** @} */
704
705	/** Initialization safty marker. */
706	uint32_t u32VersionEnd;
707	} PDMDEVREGRC;
708	/** Pointer to a raw-mode PDM device registration structure. */
709	typedef PDMDEVREGRC *PPDMDEVREGRC;
710	/** Pointer to a const raw-mode PDM device registration structure. */
711	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
712	/** Current DEVREGRC version number. */
713	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
714
715
716
717	/** @def PDM_DEVREG_VERSION
718	* Current DEVREG version number. */
719	/** @typedef PDMDEVREGR3
720	* A current context PDM device registration structure. */
721	/** @typedef PPDMDEVREGR3
722	* Pointer to a current context PDM device registration structure. */
723	/** @typedef PCPDMDEVREGR3
724	* Pointer to a const current context PDM device registration structure. */
725	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
726	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
727	typedef PDMDEVREGR3 PDMDEVREG;
728	typedef PPDMDEVREGR3 PPDMDEVREG;
729	typedef PCPDMDEVREGR3 PCPDMDEVREG;
730	#elif defined(IN_RING0)
731	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
732	typedef PDMDEVREGR0 PDMDEVREG;
733	typedef PPDMDEVREGR0 PPDMDEVREG;
734	typedef PCPDMDEVREGR0 PCPDMDEVREG;
735	#elif defined(IN_RC)
736	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
737	typedef PDMDEVREGRC PDMDEVREG;
738	typedef PPDMDEVREGRC PPDMDEVREG;
739	typedef PCPDMDEVREGRC PCPDMDEVREG;
740	#else
741	# error "Not IN_RING3, IN_RING0 or IN_RC"
742	#endif
743
744
745	/**
746	* Device registrations for ring-0 modules.
747	*
748	* This structure is used directly and must therefore reside in persistent
749	* memory (i.e. the data section).
750	*/
751	typedef struct PDMDEVMODREGR0
752	{
753	/** The structure version (PDM_DEVMODREGR0_VERSION). */
754	uint32_t u32Version;
755	/** Number of devices in the array papDevRegs points to. */
756	uint32_t cDevRegs;
757	/** Pointer to device registration structures. */
758	PCPDMDEVREGR0 *papDevRegs;
759	/** The ring-0 module handle - PDM internal, fingers off. */
760	void *hMod;
761	/** List entry - PDM internal, fingers off. */
762	RTLISTNODE ListEntry;
763	} PDMDEVMODREGR0;
764	/** Pointer to device registriations for a ring-0 module. */
765	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
766	/** Current PDMDEVMODREGR0 version number. */
767	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
768
769
770	/** @name IRQ Level for use with the *SetIrq APIs.
771	* @{
772	*/
773	/** Assert the IRQ (can assume value 1). */
774	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
775	/** Deassert the IRQ (can assume value 0). */
776	#define PDM_IRQ_LEVEL_LOW 0
777	/** flip-flop - deassert and then assert the IRQ again immediately. */
778	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
779	/** @} */
780
781	/**
782	* Registration record for MSI/MSI-X emulation.
783	*/
784	typedef struct PDMMSIREG
785	{
786	/** Number of MSI interrupt vectors, 0 if MSI not supported */
787	uint16_t cMsiVectors;
788	/** Offset of MSI capability */
789	uint8_t iMsiCapOffset;
790	/** Offset of next capability to MSI */
791	uint8_t iMsiNextOffset;
792	/** If we support 64-bit MSI addressing */
793	bool fMsi64bit;
794	/** If we do not support per-vector masking */
795	bool fMsiNoMasking;
796
797	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
798	uint16_t cMsixVectors;
799	/** Offset of MSI-X capability */
800	uint8_t iMsixCapOffset;
801	/** Offset of next capability to MSI-X */
802	uint8_t iMsixNextOffset;
803	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
804	uint8_t iMsixBar;
805	} PDMMSIREG;
806	typedef PDMMSIREG *PPDMMSIREG;
807
808	/**
809	* PCI Bus registration structure.
810	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
811	*/
812	typedef struct PDMPCIBUSREGR3
813	{
814	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
815	uint32_t u32Version;
816
817	/**
818	* Registers the device with the default PCI bus.
819	*
820	* @returns VBox status code.
821	* @param pDevIns Device instance of the PCI Bus.
822	* @param pPciDev The PCI device structure.
823	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
824	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
825	* device number (0-31).
826	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
827	* function number (0-7).
828	* @param pszName Device name (static but not unique).
829	*
830	* @remarks Caller enters the PDM critical section.
831	*/
832	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
833	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
834
835	/**
836	* Initialize MSI or MSI-X emulation support in a PCI device.
837	*
838	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
839	* vast majority of device emulation it covers everything necessary. It's
840	* fully automatic, taking care of all BAR and config space requirements,
841	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
842	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
843	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
844	*
845	* A device not using this can still offer MSI/MSI-X. In this case it's
846	* completely up to the device (in the MSI-X case) to create/register the
847	* necessary MMIO BAR, handle all config space/BAR updating and take care
848	* of delivering the interrupts appropriately.
849	*
850	* @returns VBox status code.
851	* @param pDevIns Device instance of the PCI Bus.
852	* @param pPciDev The PCI device structure.
853	* @param pMsiReg MSI emulation registration structure
854	* @remarks Caller enters the PDM critical section.
855	*/
856	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
857
858	/**
859	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
860	*
861	* @returns VBox status code.
862	* @param pDevIns Device instance of the PCI Bus.
863	* @param pPciDev The PCI device structure.
864	* @param iRegion The region number.
865	* @param cbRegion Size of the region.
866	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
867	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
868	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
869	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
870	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
871	* @a fFlags, UINT64_MAX if no handle is passed
872	* (old style).
873	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
874	* is given.
875	* @remarks Caller enters the PDM critical section.
876	*/
877	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
878	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
879	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
880
881	/**
882	* Register PCI configuration space read/write intercept callbacks.
883	*
884	* @param pDevIns Device instance of the PCI Bus.
885	* @param pPciDev The PCI device structure.
886	* @param pfnRead Pointer to the user defined PCI config read function.
887	* @param pfnWrite Pointer to the user defined PCI config write function.
888	* to call default PCI config write function. Can be NULL.
889	* @remarks Caller enters the PDM critical section.
890	* @thread EMT
891	*/
892	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
893	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
894
895	/**
896	* Perform a PCI configuration space write, bypassing interception.
897	*
898	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
899	*
900	* @returns Strict VBox status code (mainly DBGFSTOP).
901	* @param pDevIns Device instance of the PCI Bus.
902	* @param pPciDev The PCI device which config space is being read.
903	* @param uAddress The config space address.
904	* @param cb The size of the read: 1, 2 or 4 bytes.
905	* @param u32Value The value to write.
906	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
907	* that the (root) bus will have done that already.
908	*/
909	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
910	uint32_t uAddress, unsigned cb, uint32_t u32Value));
911
912	/**
913	* Perform a PCI configuration space read, bypassing interception.
914	*
915	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
916	*
917	* @returns Strict VBox status code (mainly DBGFSTOP).
918	* @param pDevIns Device instance of the PCI Bus.
919	* @param pPciDev The PCI device which config space is being read.
920	* @param uAddress The config space address.
921	* @param cb The size of the read: 1, 2 or 4 bytes.
922	* @param pu32Value Where to return the value.
923	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
924	* that the (root) bus will have done that already.
925	*/
926	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
927	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
928
929	/**
930	* Set the IRQ for a PCI device.
931	*
932	* @param pDevIns Device instance of the PCI Bus.
933	* @param pPciDev The PCI device structure.
934	* @param iIrq IRQ number to set.
935	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
936	* @param uTagSrc The IRQ tag and source (for tracing).
937	* @remarks Caller enters the PDM critical section.
938	*/
939	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
940
941	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
942	uint32_t u32EndVersion;
943	} PDMPCIBUSREGR3;
944	/** Pointer to a PCI bus registration structure. */
945	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
946	/** Current PDMPCIBUSREGR3 version number. */
947	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
948
949	/**
950	* PCI Bus registration structure for ring-0.
951	*/
952	typedef struct PDMPCIBUSREGR0
953	{
954	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
955	uint32_t u32Version;
956	/** The PCI bus number (from ring-3 registration). */
957	uint32_t iBus;
958	/**
959	* Set the IRQ for a PCI device.
960	*
961	* @param pDevIns Device instance of the PCI Bus.
962	* @param pPciDev The PCI device structure.
963	* @param iIrq IRQ number to set.
964	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
965	* @param uTagSrc The IRQ tag and source (for tracing).
966	* @remarks Caller enters the PDM critical section.
967	*/
968	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
969	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
970	uint32_t u32EndVersion;
971	} PDMPCIBUSREGR0;
972	/** Pointer to a PCI bus ring-0 registration structure. */
973	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
974	/** Current PDMPCIBUSREGR0 version number. */
975	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
976
977	/**
978	* PCI Bus registration structure for raw-mode.
979	*/
980	typedef struct PDMPCIBUSREGRC
981	{
982	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
983	uint32_t u32Version;
984	/** The PCI bus number (from ring-3 registration). */
985	uint32_t iBus;
986	/**
987	* Set the IRQ for a PCI device.
988	*
989	* @param pDevIns Device instance of the PCI Bus.
990	* @param pPciDev The PCI device structure.
991	* @param iIrq IRQ number to set.
992	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
993	* @param uTagSrc The IRQ tag and source (for tracing).
994	* @remarks Caller enters the PDM critical section.
995	*/
996	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
997	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
998	uint32_t u32EndVersion;
999	} PDMPCIBUSREGRC;
1000	/** Pointer to a PCI bus raw-mode registration structure. */
1001	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1002	/** Current PDMPCIBUSREGRC version number. */
1003	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1004
1005	/** PCI bus registration structure for the current context. */
1006	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1007	/** Pointer to a PCI bus registration structure for the current context. */
1008	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1009	/** PCI bus registration structure version for the current context. */
1010	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1011
1012
1013	/**
1014	* PCI Bus RC helpers.
1015	*/
1016	typedef struct PDMPCIHLPRC
1017	{
1018	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1019	uint32_t u32Version;
1020
1021	/**
1022	* Set an ISA IRQ.
1023	*
1024	* @param pDevIns PCI device instance.
1025	* @param iIrq IRQ number to set.
1026	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1027	* @param uTagSrc The IRQ tag and source (for tracing).
1028	* @thread EMT only.
1029	*/
1030	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1031
1032	/**
1033	* Set an I/O-APIC IRQ.
1034	*
1035	* @param pDevIns PCI device instance.
1036	* @param uBusDevFn The bus:device:function of the device initiating the
1037	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1038	* interrupt.
1039	* @param iIrq IRQ number to set.
1040	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1041	* @param uTagSrc The IRQ tag and source (for tracing).
1042	* @thread EMT only.
1043	*/
1044	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1045
1046	/**
1047	* Send an MSI.
1048	*
1049	* @param pDevIns PCI device instance.
1050	* @param uBusDevFn The bus:device:function of the device initiating the
1051	* MSI. Cannot be NIL_PCIBDF.
1052	* @param pMsi The MSI to send.
1053	* @param uTagSrc The IRQ tag and source (for tracing).
1054	* @thread EMT only.
1055	*/
1056	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1057
1058
1059	/**
1060	* Acquires the PDM lock.
1061	*
1062	* @returns VINF_SUCCESS on success.
1063	* @returns rc if we failed to acquire the lock.
1064	* @param pDevIns The PCI device instance.
1065	* @param rc What to return if we fail to acquire the lock.
1066	*/
1067	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1068
1069	/**
1070	* Releases the PDM lock.
1071	*
1072	* @param pDevIns The PCI device instance.
1073	*/
1074	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1075
1076	/**
1077	* Gets a bus by it's PDM ordinal (typically the parent bus).
1078	*
1079	* @returns Pointer to the device instance of the bus.
1080	* @param pDevIns The PCI bus device instance.
1081	* @param idxPdmBus The PDM ordinal value of the bus to get.
1082	*/
1083	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1084
1085	/** Just a safety precaution. */
1086	uint32_t u32TheEnd;
1087	} PDMPCIHLPRC;
1088	/** Pointer to PCI helpers. */
1089	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1090	/** Pointer to const PCI helpers. */
1091	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1092
1093	/** Current PDMPCIHLPRC version number. */
1094	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1095
1096
1097	/**
1098	* PCI Bus R0 helpers.
1099	*/
1100	typedef struct PDMPCIHLPR0
1101	{
1102	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1103	uint32_t u32Version;
1104
1105	/**
1106	* Set an ISA IRQ.
1107	*
1108	* @param pDevIns PCI device instance.
1109	* @param iIrq IRQ number to set.
1110	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1111	* @param uTagSrc The IRQ tag and source (for tracing).
1112	* @thread EMT only.
1113	*/
1114	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1115
1116	/**
1117	* Set an I/O-APIC IRQ.
1118	*
1119	* @param pDevIns PCI device instance.
1120	* @param uBusDevFn The bus:device:function of the device initiating the
1121	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1122	* interrupt.
1123	* @param iIrq IRQ number to set.
1124	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1125	* @param uTagSrc The IRQ tag and source (for tracing).
1126	* @thread EMT only.
1127	*/
1128	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1129
1130	/**
1131	* Send an MSI.
1132	*
1133	* @param pDevIns PCI device instance.
1134	* @param uBusDevFn The bus:device:function of the device initiating the
1135	* MSI. Cannot be NIL_PCIBDF.
1136	* @param pMsi The MSI to send.
1137	* @param uTagSrc The IRQ tag and source (for tracing).
1138	* @thread EMT only.
1139	*/
1140	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1141
1142	/**
1143	* Acquires the PDM lock.
1144	*
1145	* @returns VINF_SUCCESS on success.
1146	* @returns rc if we failed to acquire the lock.
1147	* @param pDevIns The PCI device instance.
1148	* @param rc What to return if we fail to acquire the lock.
1149	*/
1150	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1151
1152	/**
1153	* Releases the PDM lock.
1154	*
1155	* @param pDevIns The PCI device instance.
1156	*/
1157	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1158
1159	/**
1160	* Gets a bus by it's PDM ordinal (typically the parent bus).
1161	*
1162	* @returns Pointer to the device instance of the bus.
1163	* @param pDevIns The PCI bus device instance.
1164	* @param idxPdmBus The PDM ordinal value of the bus to get.
1165	*/
1166	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1167
1168	/** Just a safety precaution. */
1169	uint32_t u32TheEnd;
1170	} PDMPCIHLPR0;
1171	/** Pointer to PCI helpers. */
1172	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1173	/** Pointer to const PCI helpers. */
1174	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1175
1176	/** Current PDMPCIHLPR0 version number. */
1177	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1178
1179	/**
1180	* PCI device helpers.
1181	*/
1182	typedef struct PDMPCIHLPR3
1183	{
1184	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1185	uint32_t u32Version;
1186
1187	/**
1188	* Set an ISA IRQ.
1189	*
1190	* @param pDevIns The PCI device instance.
1191	* @param iIrq IRQ number to set.
1192	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1193	* @param uTagSrc The IRQ tag and source (for tracing).
1194	*/
1195	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1196
1197	/**
1198	* Set an I/O-APIC IRQ.
1199	*
1200	* @param pDevIns The PCI device instance.
1201	* @param uBusDevFn The bus:device:function of the device initiating the
1202	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1203	* interrupt.
1204	* @param iIrq IRQ number to set.
1205	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1206	* @param uTagSrc The IRQ tag and source (for tracing).
1207	*/
1208	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1209
1210	/**
1211	* Send an MSI.
1212	*
1213	* @param pDevIns PCI device instance.
1214	* @param uBusDevFn The bus:device:function of the device initiating the
1215	* MSI. Cannot be NIL_PCIBDF.
1216	* @param pMsi The MSI to send.
1217	* @param uTagSrc The IRQ tag and source (for tracing).
1218	*/
1219	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1220
1221	/**
1222	* Acquires the PDM lock.
1223	*
1224	* @returns VINF_SUCCESS on success.
1225	* @returns Fatal error on failure.
1226	* @param pDevIns The PCI device instance.
1227	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1228	*/
1229	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1230
1231	/**
1232	* Releases the PDM lock.
1233	*
1234	* @param pDevIns The PCI device instance.
1235	*/
1236	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1237
1238	/**
1239	* Gets a bus by it's PDM ordinal (typically the parent bus).
1240	*
1241	* @returns Pointer to the device instance of the bus.
1242	* @param pDevIns The PCI bus device instance.
1243	* @param idxPdmBus The PDM ordinal value of the bus to get.
1244	*/
1245	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1246
1247	/** Just a safety precaution. */
1248	uint32_t u32TheEnd;
1249	} PDMPCIHLPR3;
1250	/** Pointer to PCI helpers. */
1251	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1252	/** Pointer to const PCI helpers. */
1253	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1254
1255	/** Current PDMPCIHLPR3 version number. */
1256	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1257
1258
1259	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1260	* These flags are used for memory access transactions via the IOMMU interface.
1261	* @{ */
1262	/** Memory read. */
1263	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1264	/** Memory write. */
1265	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1266	/** Valid flag mask. */
1267	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1268	/** @} */
1269
1270	/**
1271	* IOMMU registration structure for ring-0.
1272	*/
1273	typedef struct PDMIOMMUREGR0
1274	{
1275	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1276	* version. */
1277	uint32_t u32Version;
1278	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1279	uint32_t idxIommu;
1280
1281	/**
1282	* Translates the physical address for a memory transaction through the IOMMU.
1283	*
1284	* @returns VBox status code.
1285	* @param pDevIns The IOMMU device instance.
1286	* @param uDevId The device identifier (bus, device, function).
1287	* @param uIova The I/O virtual address being accessed.
1288	* @param cbAccess The number of bytes being accessed.
1289	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1290	* @param pGCPhysSpa Where to store the translated system physical address.
1291	*
1292	* @thread Any.
1293	*/
1294	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
1295	uint32_t fFlags, PRTGCPHYS pGCPhysSpa));
1296
1297	/**
1298	* Translates in bulk physical page addresses for memory transactions through the
1299	* IOMMU.
1300	*
1301	* @returns VBox status code.
1302	* @param pDevIns The IOMMU device instance.
1303	* @param uDevId The device identifier (bus, device, function).
1304	* @param cIovas The number of I/O virtual addresses being accessed.
1305	* @param pauIovas The I/O virtual addresses being accessed.
1306	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1307	* @param paGCPhysSpa Where to store the translated system physical page
1308	* addresses.
1309	*
1310	* @thread Any.
1311	*/
1312	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
1313	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1314
1315	/**
1316	* Performs an interrupt remap request through the IOMMU.
1317	*
1318	* @returns VBox status code.
1319	* @param pDevIns The IOMMU device instance.
1320	* @param uDevId The device identifier (bus, device, function).
1321	* @param pMsiIn The source MSI.
1322	* @param pMsiOut Where to store the remapped MSI.
1323	*
1324	* @thread Any.
1325	*/
1326	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1327
1328	/** Just a safety precaution. */
1329	uint32_t u32TheEnd;
1330	} PDMIOMMUREGR0;
1331	/** Pointer to a IOMMU registration structure. */
1332	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1333
1334	/** Current PDMIOMMUREG version number. */
1335	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 2, 0)
1336
1337
1338	/**
1339	* IOMMU registration structure for raw-mode.
1340	*/
1341	typedef struct PDMIOMMUREGRC
1342	{
1343	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1344	* version. */
1345	uint32_t u32Version;
1346	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1347	uint32_t idxIommu;
1348
1349	/**
1350	* Translates the physical address for a memory transaction through the IOMMU.
1351	*
1352	* @returns VBox status code.
1353	* @param pDevIns The IOMMU device instance.
1354	* @param uDevId The device identifier (bus, device, function).
1355	* @param uIova The I/O virtual address being accessed.
1356	* @param cbAccess The number of bytes being accessed.
1357	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1358	* @param pGCPhysSpa Where to store the translated system physical address.
1359	*
1360	* @thread Any.
1361	*/
1362	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
1363	uint32_t fFlags, PRTGCPHYS pGCPhysSpa));
1364
1365	/**
1366	* Translates in bulk physical page addresses for memory transactions through the
1367	* IOMMU.
1368	*
1369	* @returns VBox status code.
1370	* @param pDevIns The IOMMU device instance.
1371	* @param uDevId The device identifier (bus, device, function).
1372	* @param cIovas The number of I/O virtual addresses being accessed.
1373	* @param pauIovas The I/O virtual addresses being accessed.
1374	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1375	* @param paGCPhysSpa Where to store the translated system physical page
1376	* addresses.
1377	*
1378	* @thread Any.
1379	*/
1380	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
1381	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1382
1383	/**
1384	* Performs an interrupt remap request through the IOMMU.
1385	*
1386	* @returns VBox status code.
1387	* @param pDevIns The IOMMU device instance.
1388	* @param uDevId The device identifier (bus, device, function).
1389	* @param pMsiIn The source MSI.
1390	* @param pMsiOut Where to store the remapped MSI.
1391	*
1392	* @thread Any.
1393	*/
1394	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1395
1396	/** Just a safety precaution. */
1397	uint32_t u32TheEnd;
1398	} PDMIOMMUREGRC;
1399	/** Pointer to a IOMMU registration structure. */
1400	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1401
1402	/** Current PDMIOMMUREG version number. */
1403	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 2, 0)
1404
1405
1406	/**
1407	* IOMMU registration structure for ring-3.
1408	*/
1409	typedef struct PDMIOMMUREGR3
1410	{
1411	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1412	* version. */
1413	uint32_t u32Version;
1414	/** Padding. */
1415	uint32_t uPadding0;
1416
1417	/**
1418	* Translates the physical address for a memory transaction through the IOMMU.
1419	*
1420	* @returns VBox status code.
1421	* @param pDevIns The IOMMU device instance.
1422	* @param uDevId The device identifier (bus, device, function).
1423	* @param uIova The I/O virtual address being accessed.
1424	* @param cbAccess The number of bytes being accessed.
1425	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1426	* @param pGCPhysSpa Where to store the translated system physical address.
1427	*
1428	* @thread Any.
1429	*/
1430	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
1431	uint32_t fFlags, PRTGCPHYS pGCPhysSpa));
1432
1433	/**
1434	* Translates in bulk physical page addresses for memory transactions through the
1435	* IOMMU.
1436	*
1437	* @returns VBox status code.
1438	* @param pDevIns The IOMMU device instance.
1439	* @param uDevId The device identifier (bus, device, function).
1440	* @param cIovas The number of I/O virtual addresses being accessed.
1441	* @param pauIovas The I/O virtual addresses being accessed.
1442	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1443	* @param paGCPhysSpa Where to store the translated system physical page
1444	* addresses.
1445	*
1446	* @thread Any.
1447	*/
1448	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
1449	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1450
1451	/**
1452	* Performs an interrupt remap request through the IOMMU.
1453	*
1454	* @returns VBox status code.
1455	* @param pDevIns The IOMMU device instance.
1456	* @param uDevId The device identifier (bus, device, function).
1457	* @param pMsiIn The source MSI.
1458	* @param pMsiOut Where to store the remapped MSI.
1459	*
1460	* @thread Any.
1461	*/
1462	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1463
1464	/** Just a safety precaution. */
1465	uint32_t u32TheEnd;
1466	} PDMIOMMUREGR3;
1467	/** Pointer to a IOMMU registration structure. */
1468	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1469
1470	/** Current PDMIOMMUREG version number. */
1471	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 2, 0)
1472
1473	/** IOMMU registration structure for the current context. */
1474	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1475	/** Pointer to an IOMMU registration structure for the current context. */
1476	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1477	/** IOMMU registration structure version for the current context. */
1478	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1479
1480
1481	/**
1482	* IOMMU helpers for ring-0.
1483	*/
1484	typedef struct PDMIOMMUHLPR0
1485	{
1486	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1487	uint32_t u32Version;
1488	/** Just a safety precaution. */
1489	uint32_t u32TheEnd;
1490	} PDMIOMMUHLPR0;
1491	/** Pointer to IOMMU helpers for ring-0. */
1492	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1493	/** Pointer to const IOMMU helpers for ring-0. */
1494	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1495
1496	/** Current PDMIOMMUHLPR0 version number. */
1497	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 1, 0)
1498
1499
1500	/**
1501	* IOMMU helpers for raw-mode.
1502	*/
1503	typedef struct PDMIOMMUHLPRC
1504	{
1505	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1506	uint32_t u32Version;
1507	/** Just a safety precaution. */
1508	uint32_t u32TheEnd;
1509	} PDMIOMMUHLPRC;
1510	/** Pointer to IOMMU helpers for raw-mode. */
1511	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1512	/** Pointer to const IOMMU helpers for raw-mode. */
1513	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1514
1515	/** Current PDMIOMMUHLPRC version number. */
1516	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 1, 0)
1517
1518
1519	/**
1520	* IOMMU helpers for ring-3.
1521	*/
1522	typedef struct PDMIOMMUHLPR3
1523	{
1524	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1525	uint32_t u32Version;
1526	/** Just a safety precaution. */
1527	uint32_t u32TheEnd;
1528	} PDMIOMMUHLPR3;
1529	/** Pointer to IOMMU helpers for raw-mode. */
1530	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1531	/** Pointer to const IOMMU helpers for raw-mode. */
1532	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1533
1534	/** Current PDMIOMMUHLPR3 version number. */
1535	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 1, 0)
1536
1537
1538	/**
1539	* Programmable Interrupt Controller registration structure (all contexts).
1540	*/
1541	typedef struct PDMPICREG
1542	{
1543	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1544	uint32_t u32Version;
1545
1546	/**
1547	* Set the an IRQ.
1548	*
1549	* @param pDevIns Device instance of the PIC.
1550	* @param iIrq IRQ number to set.
1551	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1552	* @param uTagSrc The IRQ tag and source (for tracing).
1553	* @remarks Caller enters the PDM critical section.
1554	*/
1555	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1556
1557	/**
1558	* Get a pending interrupt.
1559	*
1560	* @returns Pending interrupt number.
1561	* @param pDevIns Device instance of the PIC.
1562	* @param puTagSrc Where to return the IRQ tag and source.
1563	* @remarks Caller enters the PDM critical section.
1564	*/
1565	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1566
1567	/** Just a safety precaution. */
1568	uint32_t u32TheEnd;
1569	} PDMPICREG;
1570	/** Pointer to a PIC registration structure. */
1571	typedef PDMPICREG *PPDMPICREG;
1572
1573	/** Current PDMPICREG version number. */
1574	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1575
1576	/**
1577	* PIC helpers, same in all contexts.
1578	*/
1579	typedef struct PDMPICHLP
1580	{
1581	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1582	uint32_t u32Version;
1583
1584	/**
1585	* Set the interrupt force action flag.
1586	*
1587	* @param pDevIns Device instance of the PIC.
1588	*/
1589	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1590
1591	/**
1592	* Clear the interrupt force action flag.
1593	*
1594	* @param pDevIns Device instance of the PIC.
1595	*/
1596	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1597
1598	/**
1599	* Acquires the PDM lock.
1600	*
1601	* @returns VINF_SUCCESS on success.
1602	* @returns rc if we failed to acquire the lock.
1603	* @param pDevIns The PIC device instance.
1604	* @param rc What to return if we fail to acquire the lock.
1605	*/
1606	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1607
1608	/**
1609	* Releases the PDM lock.
1610	*
1611	* @param pDevIns The PIC device instance.
1612	*/
1613	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1614
1615	/** Just a safety precaution. */
1616	uint32_t u32TheEnd;
1617	} PDMPICHLP;
1618	/** Pointer to PIC helpers. */
1619	typedef PDMPICHLP *PPDMPICHLP;
1620	/** Pointer to const PIC helpers. */
1621	typedef const PDMPICHLP *PCPDMPICHLP;
1622
1623	/** Current PDMPICHLP version number. */
1624	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1625
1626
1627	/**
1628	* Firmware registration structure.
1629	*/
1630	typedef struct PDMFWREG
1631	{
1632	/** Struct version+magic number (PDM_FWREG_VERSION). */
1633	uint32_t u32Version;
1634
1635	/**
1636	* Checks whether this is a hard or soft reset.
1637	*
1638	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1639	* is 5, 9 or 0xA.
1640	*
1641	* @returns true if hard reset, false if soft.
1642	* @param pDevIns Device instance of the firmware.
1643	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1644	*/
1645	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1646
1647	/** Just a safety precaution. */
1648	uint32_t u32TheEnd;
1649	} PDMFWREG;
1650	/** Pointer to a FW registration structure. */
1651	typedef PDMFWREG *PPDMFWREG;
1652	/** Pointer to a const FW registration structure. */
1653	typedef PDMFWREG const *PCPDMFWREG;
1654
1655	/** Current PDMFWREG version number. */
1656	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1657
1658	/**
1659	* Firmware R3 helpers.
1660	*/
1661	typedef struct PDMFWHLPR3
1662	{
1663	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1664	uint32_t u32Version;
1665
1666	/** Just a safety precaution. */
1667	uint32_t u32TheEnd;
1668	} PDMFWHLPR3;
1669
1670	/** Pointer to FW R3 helpers. */
1671	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1672	/** Pointer to const FW R3 helpers. */
1673	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1674
1675	/** Current PDMFWHLPR3 version number. */
1676	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1677
1678
1679	/**
1680	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1681	*
1682	* Also used in saved-states, CFGM don't change existing values.
1683	*/
1684	typedef enum PDMAPICMODE
1685	{
1686	/** Invalid 0 entry. */
1687	PDMAPICMODE_INVALID = 0,
1688	/** No APIC. */
1689	PDMAPICMODE_NONE,
1690	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1691	PDMAPICMODE_APIC,
1692	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1693	PDMAPICMODE_X2APIC,
1694	/** The usual 32-bit paranoia. */
1695	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1696	} PDMAPICMODE;
1697
1698	/**
1699	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1700	*/
1701	typedef enum PDMAPICIRQ
1702	{
1703	/** Invalid 0 entry. */
1704	PDMAPICIRQ_INVALID = 0,
1705	/** Normal hardware interrupt. */
1706	PDMAPICIRQ_HARDWARE,
1707	/** NMI. */
1708	PDMAPICIRQ_NMI,
1709	/** SMI. */
1710	PDMAPICIRQ_SMI,
1711	/** ExtINT (HW interrupt via PIC). */
1712	PDMAPICIRQ_EXTINT,
1713	/** Interrupt arrived, needs to be updated to the IRR. */
1714	PDMAPICIRQ_UPDATE_PENDING,
1715	/** The usual 32-bit paranoia. */
1716	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1717	} PDMAPICIRQ;
1718
1719
1720	/**
1721	* I/O APIC registration structure (all contexts).
1722	*/
1723	typedef struct PDMIOAPICREG
1724	{
1725	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1726	uint32_t u32Version;
1727
1728	/**
1729	* Set an IRQ.
1730	*
1731	* @param pDevIns Device instance of the I/O APIC.
1732	* @param uBusDevFn The bus:device:function of the device initiating the
1733	* IRQ. Can be NIL_PCIBDF.
1734	* @param iIrq IRQ number to set.
1735	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1736	* @param uTagSrc The IRQ tag and source (for tracing).
1737	*
1738	* @remarks Caller enters the PDM critical section
1739	* Actually, as per 2018-07-21 this isn't true (bird).
1740	*/
1741	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1742
1743	/**
1744	* Send a MSI.
1745	*
1746	* @param pDevIns Device instance of the I/O APIC.
1747	* @param uBusDevFn The bus:device:function of the device initiating the
1748	* MSI. Cannot be NIL_PCIBDF.
1749	* @param pMsi The MSI to send.
1750	* @param uTagSrc The IRQ tag and source (for tracing).
1751	*
1752	* @remarks Caller enters the PDM critical section
1753	* Actually, as per 2018-07-21 this isn't true (bird).
1754	*/
1755	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1756
1757	/**
1758	* Set the EOI for an interrupt vector.
1759	*
1760	* @returns Strict VBox status code - only the following informational status codes:
1761	* @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
1762	* @retval VINF_SUCCESS
1763	*
1764	* @param pDevIns Device instance of the I/O APIC.
1765	* @param u8Vector The vector.
1766	*
1767	* @remarks Caller enters the PDM critical section
1768	* Actually, as per 2018-07-21 this isn't true (bird).
1769	*/
1770	DECLCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1771
1772	/** Just a safety precaution. */
1773	uint32_t u32TheEnd;
1774	} PDMIOAPICREG;
1775	/** Pointer to an APIC registration structure. */
1776	typedef PDMIOAPICREG *PPDMIOAPICREG;
1777
1778	/** Current PDMAPICREG version number. */
1779	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 7, 0)
1780
1781
1782	/**
1783	* IOAPIC helpers, same in all contexts.
1784	*/
1785	typedef struct PDMIOAPICHLP
1786	{
1787	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1788	uint32_t u32Version;
1789
1790	/**
1791	* Private interface between the IOAPIC and APIC.
1792	*
1793	* @returns status code.
1794	* @param pDevIns Device instance of the IOAPIC.
1795	* @param u8Dest See APIC implementation.
1796	* @param u8DestMode See APIC implementation.
1797	* @param u8DeliveryMode See APIC implementation.
1798	* @param uVector See APIC implementation.
1799	* @param u8Polarity See APIC implementation.
1800	* @param u8TriggerMode See APIC implementation.
1801	* @param uTagSrc The IRQ tag and source (for tracing).
1802	*
1803	* @sa APICBusDeliver()
1804	*/
1805	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1806	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1807
1808	/**
1809	* Acquires the PDM lock.
1810	*
1811	* @returns VINF_SUCCESS on success.
1812	* @returns rc if we failed to acquire the lock.
1813	* @param pDevIns The IOAPIC device instance.
1814	* @param rc What to return if we fail to acquire the lock.
1815	*/
1816	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1817
1818	/**
1819	* Releases the PDM lock.
1820	*
1821	* @param pDevIns The IOAPIC device instance.
1822	*/
1823	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1824
1825	/**
1826	* Private interface between the IOAPIC and IOMMU.
1827	*
1828	* @returns status code.
1829	* @param pDevIns Device instance of the IOAPIC.
1830	* @param uDevId The device ID (bus, device, function) for the source MSI.
1831	* @param pMsiIn The source MSI.
1832	* @param pMsiOut Where to store the remapped MSI.
1833	*
1834	* @sa iommuAmdDeviceMsiRemap().
1835	*/
1836	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevIt, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1837
1838	/** Just a safety precaution. */
1839	uint32_t u32TheEnd;
1840	} PDMIOAPICHLP;
1841	/** Pointer to IOAPIC helpers. */
1842	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1843	/** Pointer to const IOAPIC helpers. */
1844	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1845
1846	/** Current PDMIOAPICHLP version number. */
1847	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 2, 1)
1848
1849
1850	/**
1851	* HPET registration structure.
1852	*/
1853	typedef struct PDMHPETREG
1854	{
1855	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1856	uint32_t u32Version;
1857	} PDMHPETREG;
1858	/** Pointer to an HPET registration structure. */
1859	typedef PDMHPETREG *PPDMHPETREG;
1860
1861	/** Current PDMHPETREG version number. */
1862	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1863
1864	/**
1865	* HPET RC helpers.
1866	*
1867	* @remarks Keep this around in case HPET will need PDM interaction in again RC
1868	* at some later point.
1869	*/
1870	typedef struct PDMHPETHLPRC
1871	{
1872	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
1873	uint32_t u32Version;
1874
1875	/** Just a safety precaution. */
1876	uint32_t u32TheEnd;
1877	} PDMHPETHLPRC;
1878
1879	/** Pointer to HPET RC helpers. */
1880	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
1881	/** Pointer to const HPET RC helpers. */
1882	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
1883
1884	/** Current PDMHPETHLPRC version number. */
1885	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
1886
1887
1888	/**
1889	* HPET R0 helpers.
1890	*
1891	* @remarks Keep this around in case HPET will need PDM interaction in again R0
1892	* at some later point.
1893	*/
1894	typedef struct PDMHPETHLPR0
1895	{
1896	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
1897	uint32_t u32Version;
1898
1899	/** Just a safety precaution. */
1900	uint32_t u32TheEnd;
1901	} PDMHPETHLPR0;
1902
1903	/** Pointer to HPET R0 helpers. */
1904	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
1905	/** Pointer to const HPET R0 helpers. */
1906	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
1907
1908	/** Current PDMHPETHLPR0 version number. */
1909	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
1910
1911	/**
1912	* HPET R3 helpers.
1913	*/
1914	typedef struct PDMHPETHLPR3
1915	{
1916	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
1917	uint32_t u32Version;
1918
1919	/**
1920	* Set legacy mode on PIT and RTC.
1921	*
1922	* @returns VINF_SUCCESS on success.
1923	* @returns rc if we failed to set legacy mode.
1924	* @param pDevIns Device instance of the HPET.
1925	* @param fActivated Whether legacy mode is activated or deactivated.
1926	*/
1927	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
1928
1929
1930	/**
1931	* Set IRQ, bypassing ISA bus override rules.
1932	*
1933	* @returns VINF_SUCCESS on success.
1934	* @returns rc if we failed to set legacy mode.
1935	* @param pDevIns Device instance of the HPET.
1936	* @param iIrq IRQ number to set.
1937	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1938	*/
1939	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
1940
1941	/** Just a safety precaution. */
1942	uint32_t u32TheEnd;
1943	} PDMHPETHLPR3;
1944
1945	/** Pointer to HPET R3 helpers. */
1946	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
1947	/** Pointer to const HPET R3 helpers. */
1948	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
1949
1950	/** Current PDMHPETHLPR3 version number. */
1951	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
1952
1953
1954	/**
1955	* Raw PCI device registration structure.
1956	*/
1957	typedef struct PDMPCIRAWREG
1958	{
1959	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
1960	uint32_t u32Version;
1961	/** Just a safety precaution. */
1962	uint32_t u32TheEnd;
1963	} PDMPCIRAWREG;
1964	/** Pointer to a raw PCI registration structure. */
1965	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
1966
1967	/** Current PDMPCIRAWREG version number. */
1968	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
1969
1970	/**
1971	* Raw PCI device raw-mode context helpers.
1972	*/
1973	typedef struct PDMPCIRAWHLPRC
1974	{
1975	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
1976	uint32_t u32Version;
1977	/** Just a safety precaution. */
1978	uint32_t u32TheEnd;
1979	} PDMPCIRAWHLPRC;
1980	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
1981	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
1982	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
1983	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
1984
1985	/** Current PDMPCIRAWHLPRC version number. */
1986	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
1987
1988	/**
1989	* Raw PCI device ring-0 context helpers.
1990	*/
1991	typedef struct PDMPCIRAWHLPR0
1992	{
1993	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
1994	uint32_t u32Version;
1995	/** Just a safety precaution. */
1996	uint32_t u32TheEnd;
1997	} PDMPCIRAWHLPR0;
1998	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
1999	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2000	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2001	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2002
2003	/** Current PDMPCIRAWHLPR0 version number. */
2004	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2005
2006
2007	/**
2008	* Raw PCI device ring-3 context helpers.
2009	*/
2010	typedef struct PDMPCIRAWHLPR3
2011	{
2012	/** Undefined structure version and magic number. */
2013	uint32_t u32Version;
2014
2015	/**
2016	* Gets the address of the RC raw PCI device helpers.
2017	*
2018	* This should be called at both construction and relocation time to obtain
2019	* the correct address of the RC helpers.
2020	*
2021	* @returns RC pointer to the raw PCI device helpers.
2022	* @param pDevIns Device instance of the raw PCI device.
2023	*/
2024	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2025
2026	/**
2027	* Gets the address of the R0 raw PCI device helpers.
2028	*
2029	* This should be called at both construction and relocation time to obtain
2030	* the correct address of the R0 helpers.
2031	*
2032	* @returns R0 pointer to the raw PCI device helpers.
2033	* @param pDevIns Device instance of the raw PCI device.
2034	*/
2035	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2036
2037	/** Just a safety precaution. */
2038	uint32_t u32TheEnd;
2039	} PDMPCIRAWHLPR3;
2040	/** Pointer to raw PCI R3 helpers. */
2041	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2042	/** Pointer to const raw PCI R3 helpers. */
2043	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2044
2045	/** Current PDMPCIRAWHLPR3 version number. */
2046	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2047
2048
2049	#ifdef IN_RING3
2050
2051	/**
2052	* DMA Transfer Handler.
2053	*
2054	* @returns Number of bytes transferred.
2055	* @param pDevIns Device instance of the DMA.
2056	* @param pvUser User pointer.
2057	* @param uChannel Channel number.
2058	* @param off DMA position.
2059	* @param cb Block size.
2060	* @remarks The device lock is not taken, however, the DMA device lock is held.
2061	*/
2062	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2063	uint32_t off, uint32_t cb));
2064	/** Pointer to a FNDMATRANSFERHANDLER(). */
2065	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2066
2067	/**
2068	* DMA Controller registration structure.
2069	*/
2070	typedef struct PDMDMAREG
2071	{
2072	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2073	uint32_t u32Version;
2074
2075	/**
2076	* Execute pending transfers.
2077	*
2078	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2079	* @param pDevIns Device instance of the DMAC.
2080	* @remarks No locks held, called on EMT(0) as a form of serialization.
2081	*/
2082	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2083
2084	/**
2085	* Register transfer function for DMA channel.
2086	*
2087	* @param pDevIns Device instance of the DMAC.
2088	* @param uChannel Channel number.
2089	* @param pfnTransferHandler Device specific transfer function.
2090	* @param pvUser User pointer to be passed to the callback.
2091	* @remarks No locks held, called on an EMT.
2092	*/
2093	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2094
2095	/**
2096	* Read memory
2097	*
2098	* @returns Number of bytes read.
2099	* @param pDevIns Device instance of the DMAC.
2100	* @param uChannel Channel number.
2101	* @param pvBuffer Pointer to target buffer.
2102	* @param off DMA position.
2103	* @param cbBlock Block size.
2104	* @remarks No locks held, called on an EMT.
2105	*/
2106	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2107
2108	/**
2109	* Write memory
2110	*
2111	* @returns Number of bytes written.
2112	* @param pDevIns Device instance of the DMAC.
2113	* @param uChannel Channel number.
2114	* @param pvBuffer Memory to write.
2115	* @param off DMA position.
2116	* @param cbBlock Block size.
2117	* @remarks No locks held, called on an EMT.
2118	*/
2119	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2120
2121	/**
2122	* Set the DREQ line.
2123	*
2124	* @param pDevIns Device instance of the DMAC.
2125	* @param uChannel Channel number.
2126	* @param uLevel Level of the line.
2127	* @remarks No locks held, called on an EMT.
2128	*/
2129	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2130
2131	/**
2132	* Get channel mode
2133	*
2134	* @returns Channel mode.
2135	* @param pDevIns Device instance of the DMAC.
2136	* @param uChannel Channel number.
2137	* @remarks No locks held, called on an EMT.
2138	*/
2139	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2140
2141	} PDMDMACREG;
2142	/** Pointer to a DMAC registration structure. */
2143	typedef PDMDMACREG *PPDMDMACREG;
2144
2145	/** Current PDMDMACREG version number. */
2146	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 1, 0)
2147
2148
2149	/**
2150	* DMA Controller device helpers.
2151	*/
2152	typedef struct PDMDMACHLP
2153	{
2154	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2155	uint32_t u32Version;
2156
2157	/* to-be-defined */
2158
2159	} PDMDMACHLP;
2160	/** Pointer to DMAC helpers. */
2161	typedef PDMDMACHLP *PPDMDMACHLP;
2162	/** Pointer to const DMAC helpers. */
2163	typedef const PDMDMACHLP *PCPDMDMACHLP;
2164
2165	/** Current PDMDMACHLP version number. */
2166	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2167
2168	#endif /* IN_RING3 */
2169
2170
2171
2172	/**
2173	* RTC registration structure.
2174	*/
2175	typedef struct PDMRTCREG
2176	{
2177	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2178	uint32_t u32Version;
2179	uint32_t u32Alignment; /*< structure size alignment. /
2180
2181	/**
2182	* Write to a CMOS register and update the checksum if necessary.
2183	*
2184	* @returns VBox status code.
2185	* @param pDevIns Device instance of the RTC.
2186	* @param iReg The CMOS register index.
2187	* @param u8Value The CMOS register value.
2188	* @remarks Caller enters the device critical section.
2189	*/
2190	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2191
2192	/**
2193	* Read a CMOS register.
2194	*
2195	* @returns VBox status code.
2196	* @param pDevIns Device instance of the RTC.
2197	* @param iReg The CMOS register index.
2198	* @param pu8Value Where to store the CMOS register value.
2199	* @remarks Caller enters the device critical section.
2200	*/
2201	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2202
2203	} PDMRTCREG;
2204	/** Pointer to a RTC registration structure. */
2205	typedef PDMRTCREG *PPDMRTCREG;
2206	/** Pointer to a const RTC registration structure. */
2207	typedef const PDMRTCREG *PCPDMRTCREG;
2208
2209	/** Current PDMRTCREG version number. */
2210	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2211
2212
2213	/**
2214	* RTC device helpers.
2215	*/
2216	typedef struct PDMRTCHLP
2217	{
2218	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2219	uint32_t u32Version;
2220
2221	/* to-be-defined */
2222
2223	} PDMRTCHLP;
2224	/** Pointer to RTC helpers. */
2225	typedef PDMRTCHLP *PPDMRTCHLP;
2226	/** Pointer to const RTC helpers. */
2227	typedef const PDMRTCHLP *PCPDMRTCHLP;
2228
2229	/** Current PDMRTCHLP version number. */
2230	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2231
2232
2233
2234	/** @name Flags for PCI I/O region registration
2235	* @{ */
2236	/** No handle is passed. */
2237	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2238	/** An I/O port handle is passed. */
2239	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2240	/** An MMIO range handle is passed. */
2241	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2242	/** An MMIO2 handle is passed. */
2243	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2244	/** Handle type mask. */
2245	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2246	/** New-style (mostly wrt callbacks). */
2247	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2248	/** Mask of valid flags. */
2249	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2250	/** @} */
2251
2252
2253	/** @name Flags for the guest physical read/write helpers
2254	* @{ */
2255	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2256	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2257	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2258	* by the device in any way. */
2259	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2260	/** The data is metadata and being processed by the device in some way. */
2261	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2262	/** @} */
2263
2264
2265	#ifdef IN_RING3
2266
2267	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2268	* @{ */
2269	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2270	* This is handy when registering multiple PCI device functions and the device
2271	* number is left up to the PCI bus. In order to facilitate one PDM device
2272	* instance for each PCI function, this searches earlier PDM device
2273	* instances as well. */
2274	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2275	/** Use the first unused device number (all functions must be unused). */
2276	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2277	/** Use the first unused device function. */
2278	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2279
2280	/** The device and function numbers are not mandatory, just suggestions. */
2281	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2282	/** Registering a PCI bridge device. */
2283	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2284	/** Valid flag mask. */
2285	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2286	/** @} */
2287
2288	/** Current PDMDEVHLPR3 version number. */
2289	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 45, 0)
2290
2291	/**
2292	* PDM Device API.
2293	*/
2294	typedef struct PDMDEVHLPR3
2295	{
2296	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2297	uint32_t u32Version;
2298
2299	/** @name I/O ports
2300	* @{ */
2301	/**
2302	* Creates a range of I/O ports for a device.
2303	*
2304	* The I/O port range must be mapped in a separately call. Any ring-0 and
2305	* raw-mode context callback handlers needs to be set up in the respective
2306	* contexts.
2307	*
2308	* @returns VBox status.
2309	* @param pDevIns The device instance to register the ports with.
2310	* @param cPorts Number of ports to register.
2311	* @param fFlags IOM_IOPORT_F_XXX.
2312	* @param pPciDev The PCI device the range is associated with, if
2313	* applicable.
2314	* @param iPciRegion The PCI device region in the high 16-bit word and
2315	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2316	* @param pfnOut Pointer to function which is gonna handle OUT
2317	* operations. Optional.
2318	* @param pfnIn Pointer to function which is gonna handle IN operations.
2319	* Optional.
2320	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2321	* operations. Optional.
2322	* @param pfnInStr Pointer to function which is gonna handle string IN
2323	* operations. Optional.
2324	* @param pvUser User argument to pass to the callbacks.
2325	* @param pszDesc Pointer to description string. This must not be freed.
2326	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2327	* coverage is allowed. This must not be freed.
2328	* @param phIoPorts Where to return the I/O port range handle.
2329	*
2330	* @remarks Caller enters the device critical section prior to invoking the
2331	* registered callback methods.
2332	*
2333	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2334	* PDMDevHlpIoPortUnmap.
2335	*/
2336	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2337	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2338	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2339	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2340
2341	/**
2342	* Maps an I/O port range.
2343	*
2344	* @returns VBox status.
2345	* @param pDevIns The device instance to register the ports with.
2346	* @param hIoPorts The I/O port range handle.
2347	* @param Port Where to map the range.
2348	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2349	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2350	*/
2351	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2352
2353	/**
2354	* Unmaps an I/O port range.
2355	*
2356	* @returns VBox status.
2357	* @param pDevIns The device instance to register the ports with.
2358	* @param hIoPorts The I/O port range handle.
2359	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2360	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2361	*/
2362	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2363
2364	/**
2365	* Gets the mapping address of the I/O port range @a hIoPorts.
2366	*
2367	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2368	* parameters).
2369	* @param pDevIns The device instance to register the ports with.
2370	* @param hIoPorts The I/O port range handle.
2371	*/
2372	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2373	/** @} */
2374
2375	/** @name MMIO
2376	* @{ */
2377	/**
2378	* Creates a memory mapped I/O (MMIO) region for a device.
2379	*
2380	* The MMIO region must be mapped in a separately call. Any ring-0 and
2381	* raw-mode context callback handlers needs to be set up in the respective
2382	* contexts.
2383	*
2384	* @returns VBox status.
2385	* @param pDevIns The device instance to register the ports with.
2386	* @param cbRegion The size of the region in bytes.
2387	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2388	* @param pPciDev The PCI device the range is associated with, if
2389	* applicable.
2390	* @param iPciRegion The PCI device region in the high 16-bit word and
2391	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2392	* @param pfnWrite Pointer to function which is gonna handle Write
2393	* operations.
2394	* @param pfnRead Pointer to function which is gonna handle Read
2395	* operations.
2396	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2397	* operations. (optional)
2398	* @param pvUser User argument to pass to the callbacks.
2399	* @param pszDesc Pointer to description string. This must not be freed.
2400	* @param phRegion Where to return the MMIO region handle.
2401	*
2402	* @remarks Caller enters the device critical section prior to invoking the
2403	* registered callback methods.
2404	*
2405	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2406	*/
2407	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2408	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2409	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2410	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2411
2412	/**
2413	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2414	*
2415	* @returns VBox status.
2416	* @param pDevIns The device instance the region is associated with.
2417	* @param hRegion The MMIO region handle.
2418	* @param GCPhys Where to map the region.
2419	* @note An MMIO range may overlap with base memory if a lot of RAM is
2420	* configured for the VM, in which case we'll drop the base memory
2421	* pages. Presently we will make no attempt to preserve anything that
2422	* happens to be present in the base memory that is replaced, this is
2423	* technically incorrect but it's just not worth the effort to do
2424	* right, at least not at this point.
2425	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2426	* PDMDevHlpMmioSetUpContext
2427	*/
2428	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2429
2430	/**
2431	* Unmaps a memory mapped I/O (MMIO) region.
2432	*
2433	* @returns VBox status.
2434	* @param pDevIns The device instance the region is associated with.
2435	* @param hRegion The MMIO region handle.
2436	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2437	* PDMDevHlpMmioSetUpContext
2438	*/
2439	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2440
2441	/**
2442	* Reduces the length of a MMIO range.
2443	*
2444	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2445	* only work during saved state restore. It will not call the PCI bus code, as
2446	* that is expected to restore the saved resource configuration.
2447	*
2448	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2449	* called it will only map @a cbRegion bytes and not the value set during
2450	* registration.
2451	*
2452	* @return VBox status code.
2453	* @param pDevIns The device owning the range.
2454	* @param hRegion The MMIO region handle.
2455	* @param cbRegion The new size, must be smaller.
2456	*/
2457	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2458
2459	/**
2460	* Gets the mapping address of the MMIO region @a hRegion.
2461	*
2462	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2463	* @param pDevIns The device instance to register the ports with.
2464	* @param hRegion The MMIO region handle.
2465	*/
2466	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2467	/** @} */
2468
2469	/** @name MMIO2
2470	* @{ */
2471	/**
2472	* Creates a MMIO2 region.
2473	*
2474	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2475	* associated with a device. It is also non-shared memory with a permanent
2476	* ring-3 mapping and page backing (presently).
2477	*
2478	* @returns VBox status.
2479	* @param pDevIns The device instance.
2480	* @param pPciDev The PCI device the region is associated with, or
2481	* NULL if no PCI device association.
2482	* @param iPciRegion The region number. Use the PCI region number as
2483	* this must be known to the PCI bus device too. If
2484	* it's not associated with the PCI device, then
2485	* any number up to UINT8_MAX is fine.
2486	* @param cbRegion The size (in bytes) of the region.
2487	* @param fFlags Reserved for future use, must be zero.
2488	* @param pszDesc Pointer to description string. This must not be
2489	* freed.
2490	* @param ppvMapping Where to store the address of the ring-3 mapping
2491	* of the memory.
2492	* @param phRegion Where to return the MMIO2 region handle.
2493	*
2494	* @thread EMT(0)
2495	*/
2496	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2497	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2498
2499	/**
2500	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2501	*
2502	* Any physical access handlers registered for the region must be deregistered
2503	* before calling this function.
2504	*
2505	* @returns VBox status code.
2506	* @param pDevIns The device instance.
2507	* @param hRegion The MMIO2 region handle.
2508	* @thread EMT.
2509	*/
2510	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2511
2512	/**
2513	* Maps a MMIO2 region (into the guest physical address space).
2514	*
2515	* @returns VBox status.
2516	* @param pDevIns The device instance the region is associated with.
2517	* @param hRegion The MMIO2 region handle.
2518	* @param GCPhys Where to map the region.
2519	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2520	* configured for the VM, in which case we'll drop the base memory
2521	* pages. Presently we will make no attempt to preserve anything that
2522	* happens to be present in the base memory that is replaced, this is
2523	* technically incorrect but it's just not worth the effort to do
2524	* right, at least not at this point.
2525	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2526	*/
2527	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2528
2529	/**
2530	* Unmaps a MMIO2 region.
2531	*
2532	* @returns VBox status.
2533	* @param pDevIns The device instance the region is associated with.
2534	* @param hRegion The MMIO2 region handle.
2535	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2536	*/
2537	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2538
2539	/**
2540	* Reduces the length of a MMIO range.
2541	*
2542	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2543	* only work during saved state restore. It will not call the PCI bus code, as
2544	* that is expected to restore the saved resource configuration.
2545	*
2546	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2547	* called it will only map @a cbRegion bytes and not the value set during
2548	* registration.
2549	*
2550	* @return VBox status code.
2551	* @param pDevIns The device owning the range.
2552	* @param hRegion The MMIO2 region handle.
2553	* @param cbRegion The new size, must be smaller.
2554	*/
2555	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2556
2557	/**
2558	* Gets the mapping address of the MMIO region @a hRegion.
2559	*
2560	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2561	* @param pDevIns The device instance to register the ports with.
2562	* @param hRegion The MMIO2 region handle.
2563	*/
2564	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2565
2566	/**
2567	* Changes the number of an MMIO2 or pre-registered MMIO region.
2568	*
2569	* This should only be used to deal with saved state problems, so there is no
2570	* convenience inline wrapper for this method.
2571	*
2572	* @returns VBox status code.
2573	* @param pDevIns The device instance.
2574	* @param hRegion The MMIO2 region handle.
2575	* @param iNewRegion The new region index.
2576	*
2577	* @sa @bugref{9359}
2578	*/
2579	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2580	/** @} */
2581
2582	/**
2583	* Register a ROM (BIOS) region.
2584	*
2585	* It goes without saying that this is read-only memory. The memory region must be
2586	* in unassigned memory. I.e. from the top of the address space or on the PC in
2587	* the 0xa0000-0xfffff range.
2588	*
2589	* @returns VBox status.
2590	* @param pDevIns The device instance owning the ROM region.
2591	* @param GCPhysStart First physical address in the range.
2592	* Must be page aligned!
2593	* @param cbRange The size of the range (in bytes).
2594	* Must be page aligned!
2595	* @param pvBinary Pointer to the binary data backing the ROM image.
2596	* @param cbBinary The size of the binary pointer. This must
2597	* be equal or smaller than @a cbRange.
2598	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2599	* @param pszDesc Pointer to description string. This must not be freed.
2600	*
2601	* @remark There is no way to remove the rom, automatically on device cleanup or
2602	* manually from the device yet. At present I doubt we need such features...
2603	*/
2604	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2605	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2606
2607	/**
2608	* Changes the protection of shadowed ROM mapping.
2609	*
2610	* This is intented for use by the system BIOS, chipset or device in question to
2611	* change the protection of shadowed ROM code after init and on reset.
2612	*
2613	* @param pDevIns The device instance.
2614	* @param GCPhysStart Where the mapping starts.
2615	* @param cbRange The size of the mapping.
2616	* @param enmProt The new protection type.
2617	*/
2618	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2619
2620	/**
2621	* Register a save state data unit.
2622	*
2623	* @returns VBox status.
2624	* @param pDevIns The device instance.
2625	* @param uVersion Data layout version number.
2626	* @param cbGuess The approximate amount of data in the unit.
2627	* Only for progress indicators.
2628	* @param pszBefore Name of data unit which we should be put in
2629	* front of. Optional (NULL).
2630	*
2631	* @param pfnLivePrep Prepare live save callback, optional.
2632	* @param pfnLiveExec Execute live save callback, optional.
2633	* @param pfnLiveVote Vote live save callback, optional.
2634	*
2635	* @param pfnSavePrep Prepare save callback, optional.
2636	* @param pfnSaveExec Execute save callback, optional.
2637	* @param pfnSaveDone Done save callback, optional.
2638	*
2639	* @param pfnLoadPrep Prepare load callback, optional.
2640	* @param pfnLoadExec Execute load callback, optional.
2641	* @param pfnLoadDone Done load callback, optional.
2642	* @remarks Caller enters the device critical section prior to invoking the
2643	* registered callback methods.
2644	*/
2645	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2646	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2647	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2648	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2649
2650	/** @name Exported SSM Functions
2651	* @{ */
2652	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2653	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2654	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2655	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2656	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2657	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2658	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2659	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2660	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2661	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2662	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2663	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2664	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2665	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2666	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2667	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2668	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2669	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2670	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2671	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2672	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2673	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2674	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2675	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2676	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2677	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2678	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2679	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2680	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2681	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2682	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2683	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2684	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2685	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2686	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2687	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2688	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2689	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2690	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2691	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2692	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2693	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2694	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2695	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2696	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2697	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2698	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2699	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2700	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2701	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2702	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2703	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2704	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2705	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2706	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2707	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2708	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2709	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2710	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2711	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2712	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2713	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2714	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2715	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2716	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2717	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2718	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2719	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2720	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2721	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2722	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2723	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2724	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2725	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2726	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2727	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2728	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2729	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2730	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2731	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2732	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2733	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2734	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2735	/** @} */
2736
2737	/**
2738	* Creates a timer.
2739	*
2740	* @returns VBox status.
2741	* @param pDevIns The device instance.
2742	* @param enmClock The clock to use on this timer.
2743	* @param pfnCallback Callback function.
2744	* @param pvUser User argument for the callback.
2745	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2746	* @param pszDesc Pointer to description string which must stay around
2747	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2748	* @param ppTimer Where to store the timer on success.
2749	* @remarks Caller enters the device critical section prior to invoking the
2750	* callback.
2751	*/
2752	DECLR3CALLBACKMEMBER(int, pfnTMTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2753	void pvUser, uint32_t fFlags, const char pszDesc, PPTMTIMERR3 ppTimer));
2754
2755	/**
2756	* Creates a timer w/ a cross context handle.
2757	*
2758	* @returns VBox status.
2759	* @param pDevIns The device instance.
2760	* @param enmClock The clock to use on this timer.
2761	* @param pfnCallback Callback function.
2762	* @param pvUser User argument for the callback.
2763	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2764	* @param pszDesc Pointer to description string which must stay around
2765	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2766	* @param phTimer Where to store the timer handle on success.
2767	* @remarks Caller enters the device critical section prior to invoking the
2768	* callback.
2769	*/
2770	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2771	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
2772
2773	/**
2774	* Translates a timer handle to a pointer.
2775	*
2776	* @returns The time address.
2777	* @param pDevIns The device instance.
2778	* @param hTimer The timer handle.
2779	*/
2780	DECLR3CALLBACKMEMBER(PTMTIMERR3, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2781
2782	/** @name Timer handle method wrappers
2783	* @{ */
2784	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2785	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2786	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2787	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2788	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2789	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2790	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2791	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2792	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2793	/** Takes the clock lock then enters the specified critical section. */
2794	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2795	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2796	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2797	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2798	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2799	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2800	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2801	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2802	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2803	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2804	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2805	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2806	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2807	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2808	/** @sa TMR3TimerSkip */
2809	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2810	/** @} */
2811
2812	/**
2813	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2814	*
2815	* @returns pTime.
2816	* @param pDevIns The device instance.
2817	* @param pTime Where to store the time.
2818	*/
2819	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2820
2821	/** @name Exported CFGM Functions.
2822	* @{ */
2823	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2824	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2825	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
2826	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2827	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2828	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
2829	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
2830	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
2831	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2832	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2833	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
2834	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
2835	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
2836	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
2837	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
2838	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
2839	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
2840	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
2841	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
2842	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
2843	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
2844	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
2845	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
2846	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
2847	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
2848	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
2849	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2850	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2851	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
2852	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
2853	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
2854	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
2855	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
2856	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
2857	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
2858	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
2859	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
2860	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
2861	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
2862	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
2863	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
2864	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
2865	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
2866	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
2867	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
2868	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
2869	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
2870	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
2871	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
2872	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
2873	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
2874	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
2875	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
2876	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
2877	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
2878	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
2879	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
2880	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
2881	const char pszValidValues, const char pszValidNodes,
2882	const char *pszWho, uint32_t uInstance));
2883	/** @} */
2884
2885	/**
2886	* Read physical memory.
2887	*
2888	* @returns VINF_SUCCESS (for now).
2889	* @param pDevIns The device instance.
2890	* @param GCPhys Physical address start reading from.
2891	* @param pvBuf Where to put the read bits.
2892	* @param cbRead How many bytes to read.
2893	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
2894	* @thread Any thread, but the call may involve the emulation thread.
2895	*/
2896	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
2897
2898	/**
2899	* Write to physical memory.
2900	*
2901	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
2902	* @param pDevIns The device instance.
2903	* @param GCPhys Physical address to write to.
2904	* @param pvBuf What to write.
2905	* @param cbWrite How many bytes to write.
2906	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
2907	* @thread Any thread, but the call may involve the emulation thread.
2908	*/
2909	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
2910
2911	/**
2912	* Requests the mapping of a guest page into ring-3.
2913	*
2914	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2915	* release it.
2916	*
2917	* This API will assume your intention is to write to the page, and will
2918	* therefore replace shared and zero pages. If you do not intend to modify the
2919	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
2920	*
2921	* @returns VBox status code.
2922	* @retval VINF_SUCCESS on success.
2923	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2924	* backing or if the page has any active access handlers. The caller
2925	* must fall back on using PGMR3PhysWriteExternal.
2926	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2927	*
2928	* @param pDevIns The device instance.
2929	* @param GCPhys The guest physical address of the page that
2930	* should be mapped.
2931	* @param fFlags Flags reserved for future use, MBZ.
2932	* @param ppv Where to store the address corresponding to
2933	* GCPhys.
2934	* @param pLock Where to store the lock information that
2935	* pfnPhysReleasePageMappingLock needs.
2936	*
2937	* @remark Avoid calling this API from within critical sections (other than the
2938	* PGM one) because of the deadlock risk when we have to delegating the
2939	* task to an EMT.
2940	* @thread Any.
2941	*/
2942	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
2943	PPGMPAGEMAPLOCK pLock));
2944
2945	/**
2946	* Requests the mapping of a guest page into ring-3, external threads.
2947	*
2948	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2949	* release it.
2950	*
2951	* @returns VBox status code.
2952	* @retval VINF_SUCCESS on success.
2953	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2954	* backing or if the page as an active ALL access handler. The caller
2955	* must fall back on using PGMPhysRead.
2956	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2957	*
2958	* @param pDevIns The device instance.
2959	* @param GCPhys The guest physical address of the page that
2960	* should be mapped.
2961	* @param fFlags Flags reserved for future use, MBZ.
2962	* @param ppv Where to store the address corresponding to
2963	* GCPhys.
2964	* @param pLock Where to store the lock information that
2965	* pfnPhysReleasePageMappingLock needs.
2966	*
2967	* @remark Avoid calling this API from within critical sections.
2968	* @thread Any.
2969	*/
2970	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
2971	void const **ppv, PPGMPAGEMAPLOCK pLock));
2972
2973	/**
2974	* Release the mapping of a guest page.
2975	*
2976	* This is the counter part of pfnPhysGCPhys2CCPtr and
2977	* pfnPhysGCPhys2CCPtrReadOnly.
2978	*
2979	* @param pDevIns The device instance.
2980	* @param pLock The lock structure initialized by the mapping
2981	* function.
2982	*/
2983	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
2984
2985	/**
2986	* Read guest physical memory by virtual address.
2987	*
2988	* @param pDevIns The device instance.
2989	* @param pvDst Where to put the read bits.
2990	* @param GCVirtSrc Guest virtual address to start reading from.
2991	* @param cb How many bytes to read.
2992	* @thread The emulation thread.
2993	*/
2994	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
2995
2996	/**
2997	* Write to guest physical memory by virtual address.
2998	*
2999	* @param pDevIns The device instance.
3000	* @param GCVirtDst Guest virtual address to write to.
3001	* @param pvSrc What to write.
3002	* @param cb How many bytes to write.
3003	* @thread The emulation thread.
3004	*/
3005	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3006
3007	/**
3008	* Convert a guest virtual address to a guest physical address.
3009	*
3010	* @returns VBox status code.
3011	* @param pDevIns The device instance.
3012	* @param GCPtr Guest virtual address.
3013	* @param pGCPhys Where to store the GC physical address
3014	* corresponding to GCPtr.
3015	* @thread The emulation thread.
3016	* @remark Careful with page boundaries.
3017	*/
3018	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3019
3020	/**
3021	* Allocate memory which is associated with current VM instance
3022	* and automatically freed on it's destruction.
3023	*
3024	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3025	* @param pDevIns The device instance.
3026	* @param cb Number of bytes to allocate.
3027	*/
3028	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3029
3030	/**
3031	* Allocate memory which is associated with current VM instance
3032	* and automatically freed on it's destruction. The memory is ZEROed.
3033	*
3034	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3035	* @param pDevIns The device instance.
3036	* @param cb Number of bytes to allocate.
3037	*/
3038	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3039
3040	/**
3041	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3042	*
3043	* @param pDevIns The device instance.
3044	* @param pv Pointer to the memory to free.
3045	*/
3046	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3047
3048	/**
3049	* Gets the VM state.
3050	*
3051	* @returns VM state.
3052	* @param pDevIns The device instance.
3053	* @thread Any thread (just keep in mind that it's volatile info).
3054	*/
3055	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3056
3057	/**
3058	* Checks if the VM was teleported and hasn't been fully resumed yet.
3059	*
3060	* @returns true / false.
3061	* @param pDevIns The device instance.
3062	* @thread Any thread.
3063	*/
3064	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3065
3066	/**
3067	* Set the VM error message
3068	*
3069	* @returns rc.
3070	* @param pDevIns The device instance.
3071	* @param rc VBox status code.
3072	* @param SRC_POS Use RT_SRC_POS.
3073	* @param pszFormat Error message format string.
3074	* @param ... Error message arguments.
3075	*/
3076	DECLR3CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3077	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
3078
3079	/**
3080	* Set the VM error message
3081	*
3082	* @returns rc.
3083	* @param pDevIns The device instance.
3084	* @param rc VBox status code.
3085	* @param SRC_POS Use RT_SRC_POS.
3086	* @param pszFormat Error message format string.
3087	* @param va Error message arguments.
3088	*/
3089	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3090	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3091
3092	/**
3093	* Set the VM runtime error message
3094	*
3095	* @returns VBox status code.
3096	* @param pDevIns The device instance.
3097	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3098	* @param pszErrorId Error ID string.
3099	* @param pszFormat Error message format string.
3100	* @param ... Error message arguments.
3101	*/
3102	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3103	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
3104
3105	/**
3106	* Set the VM runtime error message
3107	*
3108	* @returns VBox status code.
3109	* @param pDevIns The device instance.
3110	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3111	* @param pszErrorId Error ID string.
3112	* @param pszFormat Error message format string.
3113	* @param va Error message arguments.
3114	*/
3115	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3116	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3117
3118	/**
3119	* Stops the VM and enters the debugger to look at the guest state.
3120	*
3121	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3122	* invoking this function directly.
3123	*
3124	* @returns VBox status code which must be passed up to the VMM.
3125	* @param pDevIns The device instance.
3126	* @param pszFile Filename of the assertion location.
3127	* @param iLine The linenumber of the assertion location.
3128	* @param pszFunction Function of the assertion location.
3129	* @param pszFormat Message. (optional)
3130	* @param args Message parameters.
3131	*/
3132	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3133	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3134
3135	/**
3136	* Register a info handler with DBGF.
3137	*
3138	* @returns VBox status code.
3139	* @param pDevIns The device instance.
3140	* @param pszName The identifier of the info.
3141	* @param pszDesc The description of the info and any arguments
3142	* the handler may take.
3143	* @param pfnHandler The handler function to be called to display the
3144	* info.
3145	*/
3146	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3147
3148	/**
3149	* Register a info handler with DBGF, argv style.
3150	*
3151	* @returns VBox status code.
3152	* @param pDevIns The device instance.
3153	* @param pszName The identifier of the info.
3154	* @param pszDesc The description of the info and any arguments
3155	* the handler may take.
3156	* @param pfnHandler The handler function to be called to display the
3157	* info.
3158	*/
3159	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3160
3161	/**
3162	* Registers a set of registers for a device.
3163	*
3164	* The @a pvUser argument of the getter and setter callbacks will be
3165	* @a pDevIns. The register names will be prefixed by the device name followed
3166	* immediately by the instance number.
3167	*
3168	* @returns VBox status code.
3169	* @param pDevIns The device instance.
3170	* @param paRegisters The register descriptors.
3171	*
3172	* @remarks The device critical section is NOT entered prior to working the
3173	* callbacks registered via this helper!
3174	*/
3175	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3176
3177	/**
3178	* Gets the trace buffer handle.
3179	*
3180	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3181	* really inteded for direct usage, thus no inline wrapper function.
3182	*
3183	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3184	* @param pDevIns The device instance.
3185	*/
3186	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3187
3188	/**
3189	* Registers a statistics sample.
3190	*
3191	* @param pDevIns Device instance of the DMA.
3192	* @param pvSample Pointer to the sample.
3193	* @param enmType Sample type. This indicates what pvSample is
3194	* pointing at.
3195	* @param pszName Sample name, unix path style. If this does not
3196	* start with a '/', the default prefix will be
3197	* prepended, otherwise it will be used as-is.
3198	* @param enmUnit Sample unit.
3199	* @param pszDesc Sample description.
3200	*/
3201	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3202
3203	/**
3204	* Same as pfnSTAMRegister except that the name is specified in a
3205	* RTStrPrintfV like fashion.
3206	*
3207	* @returns VBox status.
3208	* @param pDevIns Device instance of the DMA.
3209	* @param pvSample Pointer to the sample.
3210	* @param enmType Sample type. This indicates what pvSample is
3211	* pointing at.
3212	* @param enmVisibility Visibility type specifying whether unused
3213	* statistics should be visible or not.
3214	* @param enmUnit Sample unit.
3215	* @param pszDesc Sample description.
3216	* @param pszName Sample name format string, unix path style. If
3217	* this does not start with a '/', the default
3218	* prefix will be prepended, otherwise it will be
3219	* used as-is.
3220	* @param args Arguments to the format string.
3221	*/
3222	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3223	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3224	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3225
3226	/**
3227	* Registers a PCI device with the default PCI bus.
3228	*
3229	* If a PDM device has more than one PCI device, they must be registered in the
3230	* order of PDMDEVINSR3::apPciDevs.
3231	*
3232	* @returns VBox status code.
3233	* @param pDevIns The device instance.
3234	* @param pPciDev The PCI device structure.
3235	* This must be kept in the instance data.
3236	* The PCI configuration must be initialized before registration.
3237	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3238	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3239	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3240	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3241	* device number (0-31). This will be ignored if
3242	* the CFGM configuration contains a PCIDeviceNo
3243	* value.
3244	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3245	* function number (0-7). This will be ignored if
3246	* the CFGM configuration contains a PCIFunctionNo
3247	* value.
3248	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3249	* The pointer is saved, so don't free or changed.
3250	* @note The PCI device configuration is now implicit from the apPciDevs
3251	* index, meaning that the zero'th entry is the primary one and
3252	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3253	*/
3254	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3255	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3256
3257	/**
3258	* Initialize MSI or MSI-X emulation support for the given PCI device.
3259	*
3260	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3261	*
3262	* @returns VBox status code.
3263	* @param pDevIns The device instance.
3264	* @param pPciDev The PCI device. NULL is an alias for the first
3265	* one registered.
3266	* @param pMsiReg MSI emulation registration structure.
3267	*/
3268	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3269
3270	/**
3271	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3272	*
3273	* @returns VBox status code.
3274	* @param pDevIns The device instance.
3275	* @param pPciDev The PCI device structure. If NULL the default
3276	* PCI device for this device instance is used.
3277	* @param iRegion The region number.
3278	* @param cbRegion Size of the region.
3279	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3280	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3281	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3282	* @a fFlags, UINT64_MAX if no handle is passed
3283	* (old style).
3284	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3285	* handle is specified. The callback will be
3286	* invoked holding only the PDM lock. The device
3287	* lock will _not_ be taken (due to lock order).
3288	*/
3289	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3290	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3291	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3292
3293	/**
3294	* Register PCI configuration space read/write callbacks.
3295	*
3296	* @returns VBox status code.
3297	* @param pDevIns The device instance.
3298	* @param pPciDev The PCI device structure. If NULL the default
3299	* PCI device for this device instance is used.
3300	* @param pfnRead Pointer to the user defined PCI config read function.
3301	* to call default PCI config read function. Can be NULL.
3302	* @param pfnWrite Pointer to the user defined PCI config write function.
3303	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3304	* is NOT take because that is very likely be a lock order violation.
3305	* @thread EMT(0)
3306	* @note Only callable during VM creation.
3307	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3308	*/
3309	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3310	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3311
3312	/**
3313	* Perform a PCI configuration space write.
3314	*
3315	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3316	*
3317	* @returns Strict VBox status code (mainly DBGFSTOP).
3318	* @param pDevIns The device instance.
3319	* @param pPciDev The PCI device which config space is being read.
3320	* @param uAddress The config space address.
3321	* @param cb The size of the read: 1, 2 or 4 bytes.
3322	* @param u32Value The value to write.
3323	*/
3324	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3325	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3326
3327	/**
3328	* Perform a PCI configuration space read.
3329	*
3330	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3331	*
3332	* @returns Strict VBox status code (mainly DBGFSTOP).
3333	* @param pDevIns The device instance.
3334	* @param pPciDev The PCI device which config space is being read.
3335	* @param uAddress The config space address.
3336	* @param cb The size of the read: 1, 2 or 4 bytes.
3337	* @param pu32Value Where to return the value.
3338	*/
3339	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3340	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3341
3342	/**
3343	* Bus master physical memory read.
3344	*
3345	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3346	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3347	* @param pDevIns The device instance.
3348	* @param pPciDev The PCI device structure. If NULL the default
3349	* PCI device for this device instance is used.
3350	* @param GCPhys Physical address start reading from.
3351	* @param pvBuf Where to put the read bits.
3352	* @param cbRead How many bytes to read.
3353	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3354	* @thread Any thread, but the call may involve the emulation thread.
3355	*/
3356	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3357
3358	/**
3359	* Bus master physical memory write.
3360	*
3361	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3362	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3363	* @param pDevIns The device instance.
3364	* @param pPciDev The PCI device structure. If NULL the default
3365	* PCI device for this device instance is used.
3366	* @param GCPhys Physical address to write to.
3367	* @param pvBuf What to write.
3368	* @param cbWrite How many bytes to write.
3369	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3370	* @thread Any thread, but the call may involve the emulation thread.
3371	*/
3372	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3373
3374	/**
3375	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3376	* physical memory write operation.
3377	*
3378	* Refer pfnPhysGCPhys2CCPtr() for further details.
3379	*
3380	* @returns VBox status code.
3381	* @param pDevIns The device instance.
3382	* @param pPciDev The PCI device structure. If NULL the default
3383	* PCI device for this device instance is used.
3384	* @param GCPhys The guest physical address of the page that should be
3385	* mapped.
3386	* @param fFlags Flags reserved for future use, MBZ.
3387	* @param ppv Where to store the address corresponding to GCPhys.
3388	* @param pLock Where to store the lock information that
3389	* pfnPhysReleasePageMappingLock needs.
3390	*
3391	* @remarks Avoid calling this API from within critical sections (other than the PGM
3392	* one) because of the deadlock risk when we have to delegating the task to
3393	* an EMT.
3394	* @thread Any.
3395	*/
3396	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3397	void **ppv, PPGMPAGEMAPLOCK pLock));
3398
3399	/**
3400	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3401	* for a bus master physical memory read operation.
3402	*
3403	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3404	*
3405	* @returns VBox status code.
3406	* @param pDevIns The device instance.
3407	* @param pPciDev The PCI device structure. If NULL the default
3408	* PCI device for this device instance is used.
3409	* @param GCPhys The guest physical address of the page that
3410	* should be mapped.
3411	* @param fFlags Flags reserved for future use, MBZ.
3412	* @param ppv Where to store the address corresponding to
3413	* GCPhys.
3414	* @param pLock Where to store the lock information that
3415	* pfnPhysReleasePageMappingLock needs.
3416	*
3417	* @remarks Avoid calling this API from within critical sections.
3418	* @thread Any.
3419	*/
3420	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3421	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3422
3423	/**
3424	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3425	* master physical memory write operation.
3426	*
3427	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3428	* ASAP to release them.
3429	*
3430	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3431	*
3432	* @returns VBox status code.
3433	* @param pDevIns The device instance.
3434	* @param pPciDev The PCI device structure. If NULL the default
3435	* PCI device for this device instance is used.
3436	* @param cPages Number of pages to lock.
3437	* @param paGCPhysPages The guest physical address of the pages that
3438	* should be mapped (@a cPages entries).
3439	* @param fFlags Flags reserved for future use, MBZ.
3440	* @param papvPages Where to store the ring-3 mapping addresses
3441	* corresponding to @a paGCPhysPages.
3442	* @param paLocks Where to store the locking information that
3443	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3444	* in length).
3445	*/
3446	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3447	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3448	PPGMPAGEMAPLOCK paLocks));
3449
3450	/**
3451	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3452	* master physical memory read operation.
3453	*
3454	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3455	* ASAP to release them.
3456	*
3457	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3458	*
3459	* @returns VBox status code.
3460	* @param pDevIns The device instance.
3461	* @param pPciDev The PCI device structure. If NULL the default
3462	* PCI device for this device instance is used.
3463	* @param cPages Number of pages to lock.
3464	* @param paGCPhysPages The guest physical address of the pages that
3465	* should be mapped (@a cPages entries).
3466	* @param fFlags Flags reserved for future use, MBZ.
3467	* @param papvPages Where to store the ring-3 mapping addresses
3468	* corresponding to @a paGCPhysPages.
3469	* @param paLocks Where to store the lock information that
3470	* pfnPhysReleasePageMappingLock needs (@a cPages
3471	* in length).
3472	*/
3473	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3474	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3475	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3476
3477	/**
3478	* Sets the IRQ for the given PCI device.
3479	*
3480	* @param pDevIns The device instance.
3481	* @param pPciDev The PCI device structure. If NULL the default
3482	* PCI device for this device instance is used.
3483	* @param iIrq IRQ number to set.
3484	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3485	* @thread Any thread, but will involve the emulation thread.
3486	*/
3487	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3488
3489	/**
3490	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3491	* the request when not called from EMT.
3492	*
3493	* @param pDevIns The device instance.
3494	* @param pPciDev The PCI device structure. If NULL the default
3495	* PCI device for this device instance is used.
3496	* @param iIrq IRQ number to set.
3497	* @param iLevel IRQ level.
3498	* @thread Any thread, but will involve the emulation thread.
3499	*/
3500	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3501
3502	/**
3503	* Set ISA IRQ for a device.
3504	*
3505	* @param pDevIns The device instance.
3506	* @param iIrq IRQ number to set.
3507	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3508	* @thread Any thread, but will involve the emulation thread.
3509	*/
3510	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3511
3512	/**
3513	* Set the ISA IRQ for a device, but don't wait for EMT to process
3514	* the request when not called from EMT.
3515	*
3516	* @param pDevIns The device instance.
3517	* @param iIrq IRQ number to set.
3518	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3519	* @thread Any thread, but will involve the emulation thread.
3520	*/
3521	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3522
3523	/**
3524	* Attaches a driver (chain) to the device.
3525	*
3526	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3527	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3528	*
3529	* @returns VBox status code.
3530	* @param pDevIns The device instance.
3531	* @param iLun The logical unit to attach.
3532	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3533	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3534	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3535	* for the live of the device instance.
3536	*/
3537	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3538	PPDMIBASE ppBaseInterface, const char pszDesc));
3539
3540	/**
3541	* Detaches an attached driver (chain) from the device again.
3542	*
3543	* @returns VBox status code.
3544	* @param pDevIns The device instance.
3545	* @param pDrvIns The driver instance to detach.
3546	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3547	*/
3548	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3549
3550	/**
3551	* Reconfigures the driver chain for a LUN, detaching any driver currently
3552	* present there.
3553	*
3554	* Caller will have attach it, of course.
3555	*
3556	* @returns VBox status code.
3557	* @param pDevIns The device instance.
3558	* @param iLun The logical unit to reconfigure.
3559	* @param cDepth The depth of the driver chain. Determins the
3560	* size of @a papszDrivers and @a papConfigs.
3561	* @param papszDrivers The names of the drivers to configure in the
3562	* chain, first entry is the one immediately
3563	* below the device/LUN
3564	* @param papConfigs The configurations for each of the drivers
3565	* in @a papszDrivers array. NULL entries
3566	* corresponds to empty 'Config' nodes. This
3567	* function will take ownership of non-NULL
3568	* CFGM sub-trees and set the array member to
3569	* NULL, so the caller can do cleanups on
3570	* failure. This parameter is optional.
3571	* @param fFlags Reserved, MBZ.
3572	*/
3573	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3574	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3575
3576	/** @name Exported PDM Queue Functions
3577	* @{ */
3578	/**
3579	* Create a queue.
3580	*
3581	* @returns VBox status code.
3582	* @param pDevIns The device instance.
3583	* @param cbItem The size of a queue item.
3584	* @param cItems The number of items in the queue.
3585	* @param cMilliesInterval The number of milliseconds between polling the queue.
3586	* If 0 then the emulation thread will be notified whenever an item arrives.
3587	* @param pfnCallback The consumer function.
3588	* @param fRZEnabled Set if the queue should work in RC and R0.
3589	* @param pszName The queue base name. The instance number will be
3590	* appended automatically.
3591	* @param ppQueue Where to store the queue pointer on success.
3592	* @thread The emulation thread.
3593	* @remarks The device critical section will NOT be entered before calling the
3594	* callback. No locks will be held, but for now it's safe to assume
3595	* that only one EMT will do queue callbacks at any one time.
3596	*/
3597	DECLR3CALLBACKMEMBER(int, pfnQueueCreatePtr,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3598	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3599	PPDMQUEUE *ppQueue));
3600
3601	/**
3602	* Create a queue.
3603	*
3604	* @returns VBox status code.
3605	* @param pDevIns The device instance.
3606	* @param cbItem The size of a queue item.
3607	* @param cItems The number of items in the queue.
3608	* @param cMilliesInterval The number of milliseconds between polling the queue.
3609	* If 0 then the emulation thread will be notified whenever an item arrives.
3610	* @param pfnCallback The consumer function.
3611	* @param fRZEnabled Set if the queue should work in RC and R0.
3612	* @param pszName The queue base name. The instance number will be
3613	* appended automatically.
3614	* @param phQueue Where to store the queue handle on success.
3615	* @thread EMT(0)
3616	* @remarks The device critical section will NOT be entered before calling the
3617	* callback. No locks will be held, but for now it's safe to assume
3618	* that only one EMT will do queue callbacks at any one time.
3619	*/
3620	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3621	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3622	PDMQUEUEHANDLE *phQueue));
3623
3624	DECLR3CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3625	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3626	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3627	DECLR3CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
3628	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3629	/** @} */
3630
3631	/** @name PDM Task
3632	* @{ */
3633	/**
3634	* Create an asynchronous ring-3 task.
3635	*
3636	* @returns VBox status code.
3637	* @param pDevIns The device instance.
3638	* @param fFlags PDMTASK_F_XXX
3639	* @param pszName The function name or similar. Used for statistics,
3640	* so no slashes.
3641	* @param pfnCallback The task function.
3642	* @param pvUser User argument for the task function.
3643	* @param phTask Where to return the task handle.
3644	* @thread EMT(0)
3645	*/
3646	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3647	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3648	/**
3649	* Triggers the running the given task.
3650	*
3651	* @returns VBox status code.
3652	* @retval VINF_ALREADY_POSTED is the task is already pending.
3653	* @param pDevIns The device instance.
3654	* @param hTask The task to trigger.
3655	* @thread Any thread.
3656	*/
3657	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3658	/** @} */
3659
3660	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3661	* These semaphores can be signalled from ring-0.
3662	* @{ */
3663	/** @sa SUPSemEventCreate */
3664	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3665	/** @sa SUPSemEventClose */
3666	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3667	/** @sa SUPSemEventSignal */
3668	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3669	/** @sa SUPSemEventWaitNoResume */
3670	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3671	/** @sa SUPSemEventWaitNsAbsIntr */
3672	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3673	/** @sa SUPSemEventWaitNsRelIntr */
3674	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3675	/** @sa SUPSemEventGetResolution */
3676	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3677	/** @} */
3678
3679	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3680	* These semaphores can be signalled from ring-0.
3681	* @{ */
3682	/** @sa SUPSemEventMultiCreate */
3683	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3684	/** @sa SUPSemEventMultiClose */
3685	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3686	/** @sa SUPSemEventMultiSignal */
3687	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3688	/** @sa SUPSemEventMultiReset */
3689	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3690	/** @sa SUPSemEventMultiWaitNoResume */
3691	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3692	/** @sa SUPSemEventMultiWaitNsAbsIntr */
3693	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3694	/** @sa SUPSemEventMultiWaitNsRelIntr */
3695	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3696	/** @sa SUPSemEventMultiGetResolution */
3697	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3698	/** @} */
3699
3700	/**
3701	* Initializes a PDM critical section.
3702	*
3703	* The PDM critical sections are derived from the IPRT critical sections, but
3704	* works in RC and R0 as well.
3705	*
3706	* @returns VBox status code.
3707	* @param pDevIns The device instance.
3708	* @param pCritSect Pointer to the critical section.
3709	* @param SRC_POS Use RT_SRC_POS.
3710	* @param pszNameFmt Format string for naming the critical section.
3711	* For statistics and lock validation.
3712	* @param va Arguments for the format string.
3713	*/
3714	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3715	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3716
3717	/**
3718	* Gets the NOP critical section.
3719	*
3720	* @returns The ring-3 address of the NOP critical section.
3721	* @param pDevIns The device instance.
3722	*/
3723	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3724
3725	/**
3726	* Gets the NOP critical section.
3727	*
3728	* @returns The ring-0 address of the NOP critical section.
3729	* @param pDevIns The device instance.
3730	* @deprecated
3731	*/
3732	DECLR3CALLBACKMEMBER(R0PTRTYPE(PPDMCRITSECT), pfnCritSectGetNopR0,(PPDMDEVINS pDevIns));
3733
3734	/**
3735	* Gets the NOP critical section.
3736	*
3737	* @returns The raw-mode context address of the NOP critical section.
3738	* @param pDevIns The device instance.
3739	* @deprecated
3740	*/
3741	DECLR3CALLBACKMEMBER(RCPTRTYPE(PPDMCRITSECT), pfnCritSectGetNopRC,(PPDMDEVINS pDevIns));
3742
3743	/**
3744	* Changes the device level critical section from the automatically created
3745	* default to one desired by the device constructor.
3746	*
3747	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
3748	* the additional contexts.
3749	*
3750	* @returns VBox status code.
3751	* @param pDevIns The device instance.
3752	* @param pCritSect The critical section to use. NULL is not
3753	* valid, instead use the NOP critical
3754	* section.
3755	*/
3756	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3757
3758	/** @name Exported PDM Critical Section Functions
3759	* @{ */
3760	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3761	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3762	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3763	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3764	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3765	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3766	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3767	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3768	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3769	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3770	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3771	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3772	/** @} */
3773
3774	/**
3775	* Creates a PDM thread.
3776	*
3777	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3778	* resuming, and destroying the thread as the VM state changes.
3779	*
3780	* @returns VBox status code.
3781	* @param pDevIns The device instance.
3782	* @param ppThread Where to store the thread 'handle'.
3783	* @param pvUser The user argument to the thread function.
3784	* @param pfnThread The thread function.
3785	* @param pfnWakeup The wakup callback. This is called on the EMT
3786	* thread when a state change is pending.
3787	* @param cbStack See RTThreadCreate.
3788	* @param enmType See RTThreadCreate.
3789	* @param pszName See RTThreadCreate.
3790	* @remarks The device critical section will NOT be entered prior to invoking
3791	* the function pointers.
3792	*/
3793	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3794	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3795
3796	/** @name Exported PDM Thread Functions
3797	* @{ */
3798	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3799	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3800	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3801	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3802	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3803	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3804	/** @} */
3805
3806	/**
3807	* Set up asynchronous handling of a suspend, reset or power off notification.
3808	*
3809	* This shall only be called when getting the notification. It must be called
3810	* for each one.
3811	*
3812	* @returns VBox status code.
3813	* @param pDevIns The device instance.
3814	* @param pfnAsyncNotify The callback.
3815	* @thread EMT(0)
3816	* @remarks The caller will enter the device critical section prior to invoking
3817	* the callback.
3818	*/
3819	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3820
3821	/**
3822	* Notify EMT(0) that the device has completed the asynchronous notification
3823	* handling.
3824	*
3825	* This can be called at any time, spurious calls will simply be ignored.
3826	*
3827	* @param pDevIns The device instance.
3828	* @thread Any
3829	*/
3830	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
3831
3832	/**
3833	* Register the RTC device.
3834	*
3835	* @returns VBox status code.
3836	* @param pDevIns The device instance.
3837	* @param pRtcReg Pointer to a RTC registration structure.
3838	* @param ppRtcHlp Where to store the pointer to the helper
3839	* functions.
3840	*/
3841	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
3842
3843	/**
3844	* Register a PCI Bus.
3845	*
3846	* @returns VBox status code, but the positive values 0..31 are used to indicate
3847	* bus number rather than informational status codes.
3848	* @param pDevIns The device instance.
3849	* @param pPciBusReg Pointer to PCI bus registration structure.
3850	* @param ppPciHlp Where to store the pointer to the PCI Bus
3851	* helpers.
3852	* @param piBus Where to return the PDM bus number. Optional.
3853	*/
3854	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
3855	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
3856
3857	/**
3858	* Register the IOMMU device.
3859	*
3860	* @returns VBox status code.
3861	* @param pDevIns The device instance.
3862	* @param pIommuReg Pointer to a IOMMU registration structure.
3863	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
3864	* helpers.
3865	* @param pidxIommu Where to return the IOMMU index. Optional.
3866	*/
3867	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
3868	uint32_t *pidxIommu));
3869
3870	/**
3871	* Register the PIC device.
3872	*
3873	* @returns VBox status code.
3874	* @param pDevIns The device instance.
3875	* @param pPicReg Pointer to a PIC registration structure.
3876	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
3877	* helpers.
3878	* @sa PDMDevHlpPICSetUpContext
3879	*/
3880	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
3881
3882	/**
3883	* Register the APIC device.
3884	*
3885	* @returns VBox status code.
3886	* @param pDevIns The device instance.
3887	*/
3888	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
3889
3890	/**
3891	* Register the I/O APIC device.
3892	*
3893	* @returns VBox status code.
3894	* @param pDevIns The device instance.
3895	* @param pIoApicReg Pointer to a I/O APIC registration structure.
3896	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
3897	* helpers.
3898	*/
3899	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
3900
3901	/**
3902	* Register the HPET device.
3903	*
3904	* @returns VBox status code.
3905	* @param pDevIns The device instance.
3906	* @param pHpetReg Pointer to a HPET registration structure.
3907	* @param ppHpetHlpR3 Where to store the pointer to the HPET
3908	* helpers.
3909	*/
3910	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
3911
3912	/**
3913	* Register a raw PCI device.
3914	*
3915	* @returns VBox status code.
3916	* @param pDevIns The device instance.
3917	* @param pPciRawReg Pointer to a raw PCI registration structure.
3918	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
3919	* device helpers.
3920	*/
3921	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
3922
3923	/**
3924	* Register the DMA device.
3925	*
3926	* @returns VBox status code.
3927	* @param pDevIns The device instance.
3928	* @param pDmacReg Pointer to a DMAC registration structure.
3929	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
3930	*/
3931	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
3932
3933	/**
3934	* Register transfer function for DMA channel.
3935	*
3936	* @returns VBox status code.
3937	* @param pDevIns The device instance.
3938	* @param uChannel Channel number.
3939	* @param pfnTransferHandler Device specific transfer callback function.
3940	* @param pvUser User pointer to pass to the callback.
3941	* @thread EMT
3942	*/
3943	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
3944
3945	/**
3946	* Read memory.
3947	*
3948	* @returns VBox status code.
3949	* @param pDevIns The device instance.
3950	* @param uChannel Channel number.
3951	* @param pvBuffer Pointer to target buffer.
3952	* @param off DMA position.
3953	* @param cbBlock Block size.
3954	* @param pcbRead Where to store the number of bytes which was
3955	* read. optional.
3956	* @thread EMT
3957	*/
3958	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
3959
3960	/**
3961	* Write memory.
3962	*
3963	* @returns VBox status code.
3964	* @param pDevIns The device instance.
3965	* @param uChannel Channel number.
3966	* @param pvBuffer Memory to write.
3967	* @param off DMA position.
3968	* @param cbBlock Block size.
3969	* @param pcbWritten Where to store the number of bytes which was
3970	* written. optional.
3971	* @thread EMT
3972	*/
3973	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
3974
3975	/**
3976	* Set the DREQ line.
3977	*
3978	* @returns VBox status code.
3979	* @param pDevIns Device instance.
3980	* @param uChannel Channel number.
3981	* @param uLevel Level of the line.
3982	* @thread EMT
3983	*/
3984	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
3985
3986	/**
3987	* Get channel mode.
3988	*
3989	* @returns Channel mode. See specs.
3990	* @param pDevIns The device instance.
3991	* @param uChannel Channel number.
3992	* @thread EMT
3993	*/
3994	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
3995
3996	/**
3997	* Schedule DMA execution.
3998	*
3999	* @param pDevIns The device instance.
4000	* @thread Any thread.
4001	*/
4002	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4003
4004	/**
4005	* Write CMOS value and update the checksum(s).
4006	*
4007	* @returns VBox status code.
4008	* @param pDevIns The device instance.
4009	* @param iReg The CMOS register index.
4010	* @param u8Value The CMOS register value.
4011	* @thread EMT
4012	*/
4013	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4014
4015	/**
4016	* Read CMOS value.
4017	*
4018	* @returns VBox status code.
4019	* @param pDevIns The device instance.
4020	* @param iReg The CMOS register index.
4021	* @param pu8Value Where to store the CMOS register value.
4022	* @thread EMT
4023	*/
4024	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4025
4026	/**
4027	* Assert that the current thread is the emulation thread.
4028	*
4029	* @returns True if correct.
4030	* @returns False if wrong.
4031	* @param pDevIns The device instance.
4032	* @param pszFile Filename of the assertion location.
4033	* @param iLine The linenumber of the assertion location.
4034	* @param pszFunction Function of the assertion location.
4035	*/
4036	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4037
4038	/**
4039	* Assert that the current thread is NOT the emulation thread.
4040	*
4041	* @returns True if correct.
4042	* @returns False if wrong.
4043	* @param pDevIns The device instance.
4044	* @param pszFile Filename of the assertion location.
4045	* @param iLine The linenumber of the assertion location.
4046	* @param pszFunction Function of the assertion location.
4047	*/
4048	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4049
4050	/**
4051	* Resolves the symbol for a raw-mode context interface.
4052	*
4053	* @returns VBox status code.
4054	* @param pDevIns The device instance.
4055	* @param pvInterface The interface structure.
4056	* @param cbInterface The size of the interface structure.
4057	* @param pszSymPrefix What to prefix the symbols in the list with
4058	* before resolving them. This must start with
4059	* 'dev' and contain the driver name.
4060	* @param pszSymList List of symbols corresponding to the interface.
4061	* There is generally a there is generally a define
4062	* holding this list associated with the interface
4063	* definition (INTERFACE_SYM_LIST). For more
4064	* details see PDMR3LdrGetInterfaceSymbols.
4065	* @thread EMT
4066	*/
4067	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4068	const char pszSymPrefix, const char pszSymList));
4069
4070	/**
4071	* Resolves the symbol for a ring-0 context interface.
4072	*
4073	* @returns VBox status code.
4074	* @param pDevIns The device instance.
4075	* @param pvInterface The interface structure.
4076	* @param cbInterface The size of the interface structure.
4077	* @param pszSymPrefix What to prefix the symbols in the list with
4078	* before resolving them. This must start with
4079	* 'dev' and contain the driver name.
4080	* @param pszSymList List of symbols corresponding to the interface.
4081	* There is generally a there is generally a define
4082	* holding this list associated with the interface
4083	* definition (INTERFACE_SYM_LIST). For more
4084	* details see PDMR3LdrGetInterfaceSymbols.
4085	* @thread EMT
4086	*/
4087	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4088	const char pszSymPrefix, const char pszSymList));
4089
4090	/**
4091	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4092	*
4093	* @returns VBox status code.
4094	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4095	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4096	*
4097	* @param pDevIns The device instance.
4098	* @param uOperation The operation to perform.
4099	* @param u64Arg 64-bit integer argument.
4100	* @thread EMT
4101	*/
4102	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4103
4104	/**
4105	* Gets the reason for the most recent VM suspend.
4106	*
4107	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4108	* suspend has been made or if the pDevIns is invalid.
4109	* @param pDevIns The device instance.
4110	*/
4111	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4112
4113	/**
4114	* Gets the reason for the most recent VM resume.
4115	*
4116	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4117	* resume has been made or if the pDevIns is invalid.
4118	* @param pDevIns The device instance.
4119	*/
4120	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4121
4122	/**
4123	* Requests the mapping of multiple guest page into ring-3.
4124	*
4125	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4126	* ASAP to release them.
4127	*
4128	* This API will assume your intention is to write to the pages, and will
4129	* therefore replace shared and zero pages. If you do not intend to modify the
4130	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4131	*
4132	* @returns VBox status code.
4133	* @retval VINF_SUCCESS on success.
4134	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4135	* backing or if any of the pages the page has any active access
4136	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4137	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4138	* an invalid physical address.
4139	*
4140	* @param pDevIns The device instance.
4141	* @param cPages Number of pages to lock.
4142	* @param paGCPhysPages The guest physical address of the pages that
4143	* should be mapped (@a cPages entries).
4144	* @param fFlags Flags reserved for future use, MBZ.
4145	* @param papvPages Where to store the ring-3 mapping addresses
4146	* corresponding to @a paGCPhysPages.
4147	* @param paLocks Where to store the locking information that
4148	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4149	* in length).
4150	*
4151	* @remark Avoid calling this API from within critical sections (other than the
4152	* PGM one) because of the deadlock risk when we have to delegating the
4153	* task to an EMT.
4154	* @thread Any.
4155	* @since 6.0.6
4156	*/
4157	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4158	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4159
4160	/**
4161	* Requests the mapping of multiple guest page into ring-3, for reading only.
4162	*
4163	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4164	* ASAP to release them.
4165	*
4166	* @returns VBox status code.
4167	* @retval VINF_SUCCESS on success.
4168	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4169	* backing or if any of the pages the page has an active ALL access
4170	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4171	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4172	* an invalid physical address.
4173	*
4174	* @param pDevIns The device instance.
4175	* @param cPages Number of pages to lock.
4176	* @param paGCPhysPages The guest physical address of the pages that
4177	* should be mapped (@a cPages entries).
4178	* @param fFlags Flags reserved for future use, MBZ.
4179	* @param papvPages Where to store the ring-3 mapping addresses
4180	* corresponding to @a paGCPhysPages.
4181	* @param paLocks Where to store the lock information that
4182	* pfnPhysReleasePageMappingLock needs (@a cPages
4183	* in length).
4184	*
4185	* @remark Avoid calling this API from within critical sections.
4186	* @thread Any.
4187	* @since 6.0.6
4188	*/
4189	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4190	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4191
4192	/**
4193	* Release the mappings of multiple guest pages.
4194	*
4195	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4196	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4197	*
4198	* @param pDevIns The device instance.
4199	* @param cPages Number of pages to unlock.
4200	* @param paLocks The lock structures initialized by the mapping
4201	* function (@a cPages in length).
4202	* @thread Any.
4203	* @since 6.0.6
4204	*/
4205	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4206
4207	/**
4208	* Returns the micro architecture used for the guest.
4209	*
4210	* @returns CPU micro architecture enum.
4211	* @param pDevIns The device instance.
4212	*/
4213	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4214
4215	/** Space reserved for future members.
4216	* @{ */
4217	DECLR3CALLBACKMEMBER(void, pfnReserved1,(void));
4218	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4219	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4220	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4221	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4222	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4223	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4224	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4225	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4226	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4227	/** @} */
4228
4229
4230	/** API available to trusted devices only.
4231	*
4232	* These APIs are providing unrestricted access to the guest and the VM,
4233	* or they are interacting intimately with PDM.
4234	*
4235	* @{
4236	*/
4237
4238	/**
4239	* Gets the user mode VM handle. Restricted API.
4240	*
4241	* @returns User mode VM Handle.
4242	* @param pDevIns The device instance.
4243	*/
4244	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4245
4246	/**
4247	* Gets the global VM handle. Restricted API.
4248	*
4249	* @returns VM Handle.
4250	* @param pDevIns The device instance.
4251	*/
4252	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4253
4254	/**
4255	* Gets the VMCPU handle. Restricted API.
4256	*
4257	* @returns VMCPU Handle.
4258	* @param pDevIns The device instance.
4259	*/
4260	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4261
4262	/**
4263	* The the VM CPU ID of the current thread (restricted API).
4264	*
4265	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4266	* @param pDevIns The device instance.
4267	*/
4268	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4269
4270	/**
4271	* Registers the VMM device heap or notifies about mapping/unmapping.
4272	*
4273	* This interface serves three purposes:
4274	*
4275	* -# Register the VMM device heap during device construction
4276	* for the HM to use.
4277	* -# Notify PDM/HM that it's mapped into guest address
4278	* space (i.e. usable).
4279	* -# Notify PDM/HM that it is being unmapped from the guest
4280	* address space (i.e. not usable).
4281	*
4282	* @returns VBox status code.
4283	* @param pDevIns The device instance.
4284	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4285	* not mapped.
4286	* @param pvHeap Ring 3 heap pointer.
4287	* @param cbHeap Size of the heap.
4288	* @thread EMT.
4289	*/
4290	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4291
4292	/**
4293	* Registers the firmware (BIOS, EFI) device with PDM.
4294	*
4295	* The firmware provides a callback table and gets a special PDM helper table.
4296	* There can only be one firmware device for a VM.
4297	*
4298	* @returns VBox status code.
4299	* @param pDevIns The device instance.
4300	* @param pFwReg Firmware registration structure.
4301	* @param ppFwHlp Where to return the firmware helper structure.
4302	* @remarks Only valid during device construction.
4303	* @thread EMT(0)
4304	*/
4305	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4306
4307	/**
4308	* Resets the VM.
4309	*
4310	* @returns The appropriate VBox status code to pass around on reset.
4311	* @param pDevIns The device instance.
4312	* @param fFlags PDMVMRESET_F_XXX flags.
4313	* @thread The emulation thread.
4314	*/
4315	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4316
4317	/**
4318	* Suspends the VM.
4319	*
4320	* @returns The appropriate VBox status code to pass around on suspend.
4321	* @param pDevIns The device instance.
4322	* @thread The emulation thread.
4323	*/
4324	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4325
4326	/**
4327	* Suspends, saves and powers off the VM.
4328	*
4329	* @returns The appropriate VBox status code to pass around.
4330	* @param pDevIns The device instance.
4331	* @thread An emulation thread.
4332	*/
4333	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4334
4335	/**
4336	* Power off the VM.
4337	*
4338	* @returns The appropriate VBox status code to pass around on power off.
4339	* @param pDevIns The device instance.
4340	* @thread The emulation thread.
4341	*/
4342	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4343
4344	/**
4345	* Checks if the Gate A20 is enabled or not.
4346	*
4347	* @returns true if A20 is enabled.
4348	* @returns false if A20 is disabled.
4349	* @param pDevIns The device instance.
4350	* @thread The emulation thread.
4351	*/
4352	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4353
4354	/**
4355	* Enables or disables the Gate A20.
4356	*
4357	* @param pDevIns The device instance.
4358	* @param fEnable Set this flag to enable the Gate A20; clear it
4359	* to disable.
4360	* @thread The emulation thread.
4361	*/
4362	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4363
4364	/**
4365	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4366	* thread.
4367	*
4368	* @param pDevIns The device instance.
4369	* @param iLeaf The CPUID leaf to get.
4370	* @param pEax Where to store the EAX value.
4371	* @param pEbx Where to store the EBX value.
4372	* @param pEcx Where to store the ECX value.
4373	* @param pEdx Where to store the EDX value.
4374	* @thread EMT.
4375	*/
4376	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4377
4378	/**
4379	* Get the current virtual clock time in a VM. The clock frequency must be
4380	* queried separately.
4381	*
4382	* @returns Current clock time.
4383	* @param pDevIns The device instance.
4384	*/
4385	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4386
4387	/**
4388	* Get the frequency of the virtual clock.
4389	*
4390	* @returns The clock frequency (not variable at run-time).
4391	* @param pDevIns The device instance.
4392	*/
4393	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4394
4395	/**
4396	* Get the current virtual clock time in a VM, in nanoseconds.
4397	*
4398	* @returns Current clock time (in ns).
4399	* @param pDevIns The device instance.
4400	*/
4401	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4402
4403	/**
4404	* Gets the support driver session.
4405	*
4406	* This is intended for working with the semaphore API.
4407	*
4408	* @returns Support driver session handle.
4409	* @param pDevIns The device instance.
4410	*/
4411	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4412
4413	/**
4414	* Queries a generic object from the VMM user.
4415	*
4416	* @returns Pointer to the object if found, NULL if not.
4417	* @param pDevIns The device instance.
4418	* @param pUuid The UUID of what's being queried. The UUIDs and
4419	* the usage conventions are defined by the user.
4420	*
4421	* @note It is strictly forbidden to call this internally in VBox! This
4422	* interface is exclusively for hacks in externally developed devices.
4423	*/
4424	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4425
4426	/**
4427	* Register a physical page access handler type.
4428	*
4429	* @returns VBox status code.
4430	* @param pDevIns The device instance.
4431	* @param enmKind The kind of access handler.
4432	* @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4433	* @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4434	* handler should be called.
4435	* @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4436	* ring-3 handler should be called.
4437	* @param pszHandlerRC The name of the raw-mode context handler, NULL if
4438	* the ring-3 handler should be called.
4439	* @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4440	* if the ring-3 handler should be called.
4441	* @param pszDesc The type description.
4442	* @param phType Where to return the type handle (cross context
4443	* safe).
4444	*/
4445	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4446	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4447	const char pszHandlerR0, const char pszPfHandlerR0,
4448	const char pszHandlerRC, const char pszPfHandlerRC,
4449	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4450
4451	/** @} */
4452
4453	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4454	uint32_t u32TheEnd;
4455	} PDMDEVHLPR3;
4456	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4457	/** Pointer to the R3 PDM Device API. */
4458	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4459	/** Pointer to the R3 PDM Device API, const variant. */
4460	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4461
4462
4463	/**
4464	* PDM Device API - RC Variant.
4465	*/
4466	typedef struct PDMDEVHLPRC
4467	{
4468	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4469	uint32_t u32Version;
4470
4471	/**
4472	* Sets up raw-mode context callback handlers for an I/O port range.
4473	*
4474	* The range must have been registered in ring-3 first using
4475	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4476	*
4477	* @returns VBox status.
4478	* @param pDevIns The device instance to register the ports with.
4479	* @param hIoPorts The I/O port range handle.
4480	* @param pfnOut Pointer to function which is gonna handle OUT
4481	* operations. Optional.
4482	* @param pfnIn Pointer to function which is gonna handle IN operations.
4483	* Optional.
4484	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4485	* operations. Optional.
4486	* @param pfnInStr Pointer to function which is gonna handle string IN
4487	* operations. Optional.
4488	* @param pvUser User argument to pass to the callbacks.
4489	*
4490	* @remarks Caller enters the device critical section prior to invoking the
4491	* registered callback methods.
4492	*
4493	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4494	* PDMDevHlpIoPortUnmap.
4495	*/
4496	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4497	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4498	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4499	void *pvUser));
4500
4501	/**
4502	* Sets up raw-mode context callback handlers for an MMIO region.
4503	*
4504	* The region must have been registered in ring-3 first using
4505	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4506	*
4507	* @returns VBox status.
4508	* @param pDevIns The device instance to register the ports with.
4509	* @param hRegion The MMIO region handle.
4510	* @param pfnWrite Pointer to function which is gonna handle Write
4511	* operations.
4512	* @param pfnRead Pointer to function which is gonna handle Read
4513	* operations.
4514	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4515	* operations. (optional)
4516	* @param pvUser User argument to pass to the callbacks.
4517	*
4518	* @remarks Caller enters the device critical section prior to invoking the
4519	* registered callback methods.
4520	*
4521	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4522	* PDMDevHlpMmioUnmap.
4523	*/
4524	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4525	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4526
4527	/**
4528	* Sets up a raw-mode mapping for an MMIO2 region.
4529	*
4530	* The region must have been created in ring-3 first using
4531	* PDMDevHlpMmio2Create().
4532	*
4533	* @returns VBox status.
4534	* @param pDevIns The device instance to register the ports with.
4535	* @param hRegion The MMIO2 region handle.
4536	* @param offSub Start of what to map into raw-mode. Must be page aligned.
4537	* @param cbSub Number of bytes to map into raw-mode. Must be page
4538	* aligned. Zero is an alias for everything.
4539	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4540	* @thread EMT(0)
4541	* @note Only available at VM creation time.
4542	*
4543	* @sa PDMDevHlpMmio2Create().
4544	*/
4545	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4546	size_t offSub, size_t cbSub, void **ppvMapping));
4547
4548	/**
4549	* Bus master physical memory read from the given PCI device.
4550	*
4551	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4552	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4553	* @param pDevIns The device instance.
4554	* @param pPciDev The PCI device structure. If NULL the default
4555	* PCI device for this device instance is used.
4556	* @param GCPhys Physical address start reading from.
4557	* @param pvBuf Where to put the read bits.
4558	* @param cbRead How many bytes to read.
4559	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4560	* @thread Any thread, but the call may involve the emulation thread.
4561	*/
4562	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4563	void *pvBuf, size_t cbRead, uint32_t fFlags));
4564
4565	/**
4566	* Bus master physical memory write from the given PCI device.
4567	*
4568	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4569	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4570	* @param pDevIns The device instance.
4571	* @param pPciDev The PCI device structure. If NULL the default
4572	* PCI device for this device instance is used.
4573	* @param GCPhys Physical address to write to.
4574	* @param pvBuf What to write.
4575	* @param cbWrite How many bytes to write.
4576	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4577	* @thread Any thread, but the call may involve the emulation thread.
4578	*/
4579	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4580	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4581
4582	/**
4583	* Set the IRQ for the given PCI device.
4584	*
4585	* @param pDevIns Device instance.
4586	* @param pPciDev The PCI device structure. If NULL the default
4587	* PCI device for this device instance is used.
4588	* @param iIrq IRQ number to set.
4589	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4590	* @thread Any thread, but will involve the emulation thread.
4591	*/
4592	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4593
4594	/**
4595	* Set ISA IRQ for a device.
4596	*
4597	* @param pDevIns Device instance.
4598	* @param iIrq IRQ number to set.
4599	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4600	* @thread Any thread, but will involve the emulation thread.
4601	*/
4602	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4603
4604	/**
4605	* Read physical memory.
4606	*
4607	* @returns VINF_SUCCESS (for now).
4608	* @param pDevIns Device instance.
4609	* @param GCPhys Physical address start reading from.
4610	* @param pvBuf Where to put the read bits.
4611	* @param cbRead How many bytes to read.
4612	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4613	*/
4614	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
4615
4616	/**
4617	* Write to physical memory.
4618	*
4619	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4620	* @param pDevIns Device instance.
4621	* @param GCPhys Physical address to write to.
4622	* @param pvBuf What to write.
4623	* @param cbWrite How many bytes to write.
4624	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4625	*/
4626	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4627
4628	/**
4629	* Checks if the Gate A20 is enabled or not.
4630	*
4631	* @returns true if A20 is enabled.
4632	* @returns false if A20 is disabled.
4633	* @param pDevIns Device instance.
4634	* @thread The emulation thread.
4635	*/
4636	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4637
4638	/**
4639	* Gets the VM state.
4640	*
4641	* @returns VM state.
4642	* @param pDevIns The device instance.
4643	* @thread Any thread (just keep in mind that it's volatile info).
4644	*/
4645	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4646
4647	/**
4648	* Set the VM error message
4649	*
4650	* @returns rc.
4651	* @param pDevIns Driver instance.
4652	* @param rc VBox status code.
4653	* @param SRC_POS Use RT_SRC_POS.
4654	* @param pszFormat Error message format string.
4655	* @param ... Error message arguments.
4656	*/
4657	DECLRCCALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4658	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4659
4660	/**
4661	* Set the VM error message
4662	*
4663	* @returns rc.
4664	* @param pDevIns Driver instance.
4665	* @param rc VBox status code.
4666	* @param SRC_POS Use RT_SRC_POS.
4667	* @param pszFormat Error message format string.
4668	* @param va Error message arguments.
4669	*/
4670	DECLRCCALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4671	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4672
4673	/**
4674	* Set the VM runtime error message
4675	*
4676	* @returns VBox status code.
4677	* @param pDevIns Device instance.
4678	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4679	* @param pszErrorId Error ID string.
4680	* @param pszFormat Error message format string.
4681	* @param ... Error message arguments.
4682	*/
4683	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4684	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4685
4686	/**
4687	* Set the VM runtime error message
4688	*
4689	* @returns VBox status code.
4690	* @param pDevIns Device instance.
4691	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4692	* @param pszErrorId Error ID string.
4693	* @param pszFormat Error message format string.
4694	* @param va Error message arguments.
4695	*/
4696	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4697	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
4698
4699	/**
4700	* Gets the VM handle. Restricted API.
4701	*
4702	* @returns VM Handle.
4703	* @param pDevIns Device instance.
4704	*/
4705	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4706
4707	/**
4708	* Gets the VMCPU handle. Restricted API.
4709	*
4710	* @returns VMCPU Handle.
4711	* @param pDevIns The device instance.
4712	*/
4713	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4714
4715	/**
4716	* The the VM CPU ID of the current thread (restricted API).
4717	*
4718	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4719	* @param pDevIns The device instance.
4720	*/
4721	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4722
4723	/**
4724	* Get the current virtual clock time in a VM. The clock frequency must be
4725	* queried separately.
4726	*
4727	* @returns Current clock time.
4728	* @param pDevIns The device instance.
4729	*/
4730	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4731
4732	/**
4733	* Get the frequency of the virtual clock.
4734	*
4735	* @returns The clock frequency (not variable at run-time).
4736	* @param pDevIns The device instance.
4737	*/
4738	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4739
4740	/**
4741	* Get the current virtual clock time in a VM, in nanoseconds.
4742	*
4743	* @returns Current clock time (in ns).
4744	* @param pDevIns The device instance.
4745	*/
4746	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4747
4748	/**
4749	* Gets the NOP critical section.
4750	*
4751	* @returns The ring-3 address of the NOP critical section.
4752	* @param pDevIns The device instance.
4753	*/
4754	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4755
4756	/**
4757	* Changes the device level critical section from the automatically created
4758	* default to one desired by the device constructor.
4759	*
4760	* Must first be done in ring-3.
4761	*
4762	* @returns VBox status code.
4763	* @param pDevIns The device instance.
4764	* @param pCritSect The critical section to use. NULL is not
4765	* valid, instead use the NOP critical
4766	* section.
4767	*/
4768	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4769
4770	/** @name Exported PDM Critical Section Functions
4771	* @{ */
4772	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4773	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4774	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4775	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4776	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4777	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4778	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4779	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4780	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4781	/** @} */
4782
4783	/**
4784	* Gets the trace buffer handle.
4785	*
4786	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4787	* really inteded for direct usage, thus no inline wrapper function.
4788	*
4789	* @returns Trace buffer handle or NIL_RTTRACEBUF.
4790	* @param pDevIns The device instance.
4791	*/
4792	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4793
4794	/**
4795	* Sets up the PCI bus for the raw-mode context.
4796	*
4797	* This must be called after ring-3 has registered the PCI bus using
4798	* PDMDevHlpPCIBusRegister().
4799	*
4800	* @returns VBox status code.
4801	* @param pDevIns The device instance.
4802	* @param pPciBusReg The PCI bus registration information for raw-mode,
4803	* considered volatile.
4804	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4805	*/
4806	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4807
4808	/**
4809	* Sets up the IOMMU for the raw-mode context.
4810	*
4811	* This must be called after ring-3 has registered the IOMMU using
4812	* PDMDevHlpIommuRegister().
4813	*
4814	* @returns VBox status code.
4815	* @param pDevIns The device instance.
4816	* @param pIommuReg The IOMMU registration information for raw-mode,
4817	* considered volatile.
4818	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
4819	*/
4820	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
4821
4822	/**
4823	* Sets up the PIC for the ring-0 context.
4824	*
4825	* This must be called after ring-3 has registered the PIC using
4826	* PDMDevHlpPICRegister().
4827	*
4828	* @returns VBox status code.
4829	* @param pDevIns The device instance.
4830	* @param pPicReg The PIC registration information for ring-0,
4831	* considered volatile and copied.
4832	* @param ppPicHlp Where to return the ring-0 PIC helpers.
4833	*/
4834	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4835
4836	/**
4837	* Sets up the APIC for the raw-mode context.
4838	*
4839	* This must be called after ring-3 has registered the APIC using
4840	* PDMDevHlpApicRegister().
4841	*
4842	* @returns VBox status code.
4843	* @param pDevIns The device instance.
4844	*/
4845	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
4846
4847	/**
4848	* Sets up the IOAPIC for the ring-0 context.
4849	*
4850	* This must be called after ring-3 has registered the PIC using
4851	* PDMDevHlpIoApicRegister().
4852	*
4853	* @returns VBox status code.
4854	* @param pDevIns The device instance.
4855	* @param pIoApicReg The PIC registration information for ring-0,
4856	* considered volatile and copied.
4857	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
4858	*/
4859	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4860
4861	/**
4862	* Sets up the HPET for the raw-mode context.
4863	*
4864	* This must be called after ring-3 has registered the PIC using
4865	* PDMDevHlpHpetRegister().
4866	*
4867	* @returns VBox status code.
4868	* @param pDevIns The device instance.
4869	* @param pHpetReg The PIC registration information for raw-mode,
4870	* considered volatile and copied.
4871	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
4872	*/
4873	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
4874
4875	/** Space reserved for future members.
4876	* @{ */
4877	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
4878	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
4879	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
4880	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
4881	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
4882	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
4883	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
4884	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
4885	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
4886	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
4887	/** @} */
4888
4889	/** Just a safety precaution. */
4890	uint32_t u32TheEnd;
4891	} PDMDEVHLPRC;
4892	/** Pointer PDM Device RC API. */
4893	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
4894	/** Pointer PDM Device RC API. */
4895	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
4896
4897	/** Current PDMDEVHLP version number. */
4898	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 16, 0)
4899
4900
4901	/**
4902	* PDM Device API - R0 Variant.
4903	*/
4904	typedef struct PDMDEVHLPR0
4905	{
4906	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
4907	uint32_t u32Version;
4908
4909	/**
4910	* Sets up ring-0 callback handlers for an I/O port range.
4911	*
4912	* The range must have been created in ring-3 first using
4913	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4914	*
4915	* @returns VBox status.
4916	* @param pDevIns The device instance to register the ports with.
4917	* @param hIoPorts The I/O port range handle.
4918	* @param pfnOut Pointer to function which is gonna handle OUT
4919	* operations. Optional.
4920	* @param pfnIn Pointer to function which is gonna handle IN operations.
4921	* Optional.
4922	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4923	* operations. Optional.
4924	* @param pfnInStr Pointer to function which is gonna handle string IN
4925	* operations. Optional.
4926	* @param pvUser User argument to pass to the callbacks.
4927	*
4928	* @remarks Caller enters the device critical section prior to invoking the
4929	* registered callback methods.
4930	*
4931	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
4932	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
4933	*/
4934	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4935	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4936	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4937	void *pvUser));
4938
4939	/**
4940	* Sets up ring-0 callback handlers for an MMIO region.
4941	*
4942	* The region must have been created in ring-3 first using
4943	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
4944	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
4945	*
4946	* @returns VBox status.
4947	* @param pDevIns The device instance to register the ports with.
4948	* @param hRegion The MMIO region handle.
4949	* @param pfnWrite Pointer to function which is gonna handle Write
4950	* operations.
4951	* @param pfnRead Pointer to function which is gonna handle Read
4952	* operations.
4953	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4954	* operations. (optional)
4955	* @param pvUser User argument to pass to the callbacks.
4956	*
4957	* @remarks Caller enters the device critical section prior to invoking the
4958	* registered callback methods.
4959	*
4960	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
4961	* PDMDevHlpMmioUnmap().
4962	*/
4963	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4964	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4965
4966	/**
4967	* Sets up a ring-0 mapping for an MMIO2 region.
4968	*
4969	* The region must have been created in ring-3 first using
4970	* PDMDevHlpMmio2Create().
4971	*
4972	* @returns VBox status.
4973	* @param pDevIns The device instance to register the ports with.
4974	* @param hRegion The MMIO2 region handle.
4975	* @param offSub Start of what to map into ring-0. Must be page aligned.
4976	* @param cbSub Number of bytes to map into ring-0. Must be page
4977	* aligned. Zero is an alias for everything.
4978	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4979	*
4980	* @thread EMT(0)
4981	* @note Only available at VM creation time.
4982	*
4983	* @sa PDMDevHlpMmio2Create().
4984	*/
4985	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
4986	void **ppvMapping));
4987
4988	/**
4989	* Bus master physical memory read from the given PCI device.
4990	*
4991	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
4992	* VERR_EM_MEMORY.
4993	* @param pDevIns The device instance.
4994	* @param pPciDev The PCI device structure. If NULL the default
4995	* PCI device for this device instance is used.
4996	* @param GCPhys Physical address start reading from.
4997	* @param pvBuf Where to put the read bits.
4998	* @param cbRead How many bytes to read.
4999	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5000	* @thread Any thread, but the call may involve the emulation thread.
5001	*/
5002	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5003	void *pvBuf, size_t cbRead, uint32_t fFlags));
5004
5005	/**
5006	* Bus master physical memory write from the given PCI device.
5007	*
5008	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5009	* VERR_EM_MEMORY.
5010	* @param pDevIns The device instance.
5011	* @param pPciDev The PCI device structure. If NULL the default
5012	* PCI device for this device instance is used.
5013	* @param GCPhys Physical address to write to.
5014	* @param pvBuf What to write.
5015	* @param cbWrite How many bytes to write.
5016	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5017	* @thread Any thread, but the call may involve the emulation thread.
5018	*/
5019	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5020	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5021
5022	/**
5023	* Set the IRQ for the given PCI device.
5024	*
5025	* @param pDevIns Device instance.
5026	* @param pPciDev The PCI device structure. If NULL the default
5027	* PCI device for this device instance is used.
5028	* @param iIrq IRQ number to set.
5029	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5030	* @thread Any thread, but will involve the emulation thread.
5031	*/
5032	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5033
5034	/**
5035	* Set ISA IRQ for a device.
5036	*
5037	* @param pDevIns Device instance.
5038	* @param iIrq IRQ number to set.
5039	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5040	* @thread Any thread, but will involve the emulation thread.
5041	*/
5042	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5043
5044	/**
5045	* Read physical memory.
5046	*
5047	* @returns VINF_SUCCESS (for now).
5048	* @param pDevIns Device instance.
5049	* @param GCPhys Physical address start reading from.
5050	* @param pvBuf Where to put the read bits.
5051	* @param cbRead How many bytes to read.
5052	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5053	*/
5054	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5055
5056	/**
5057	* Write to physical memory.
5058	*
5059	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5060	* @param pDevIns Device instance.
5061	* @param GCPhys Physical address to write to.
5062	* @param pvBuf What to write.
5063	* @param cbWrite How many bytes to write.
5064	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5065	*/
5066	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5067
5068	/**
5069	* Checks if the Gate A20 is enabled or not.
5070	*
5071	* @returns true if A20 is enabled.
5072	* @returns false if A20 is disabled.
5073	* @param pDevIns Device instance.
5074	* @thread The emulation thread.
5075	*/
5076	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5077
5078	/**
5079	* Gets the VM state.
5080	*
5081	* @returns VM state.
5082	* @param pDevIns The device instance.
5083	* @thread Any thread (just keep in mind that it's volatile info).
5084	*/
5085	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5086
5087	/**
5088	* Set the VM error message
5089	*
5090	* @returns rc.
5091	* @param pDevIns Driver instance.
5092	* @param rc VBox status code.
5093	* @param SRC_POS Use RT_SRC_POS.
5094	* @param pszFormat Error message format string.
5095	* @param ... Error message arguments.
5096	*/
5097	DECLR0CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5098	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
5099
5100	/**
5101	* Set the VM error message
5102	*
5103	* @returns rc.
5104	* @param pDevIns Driver instance.
5105	* @param rc VBox status code.
5106	* @param SRC_POS Use RT_SRC_POS.
5107	* @param pszFormat Error message format string.
5108	* @param va Error message arguments.
5109	*/
5110	DECLR0CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5111	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
5112
5113	/**
5114	* Set the VM runtime error message
5115	*
5116	* @returns VBox status code.
5117	* @param pDevIns Device instance.
5118	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5119	* @param pszErrorId Error ID string.
5120	* @param pszFormat Error message format string.
5121	* @param ... Error message arguments.
5122	*/
5123	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5124	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
5125
5126	/**
5127	* Set the VM runtime error message
5128	*
5129	* @returns VBox status code.
5130	* @param pDevIns Device instance.
5131	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5132	* @param pszErrorId Error ID string.
5133	* @param pszFormat Error message format string.
5134	* @param va Error message arguments.
5135	*/
5136	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5137	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
5138
5139	/**
5140	* Gets the VM handle. Restricted API.
5141	*
5142	* @returns VM Handle.
5143	* @param pDevIns Device instance.
5144	*/
5145	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5146
5147	/**
5148	* Gets the VMCPU handle. Restricted API.
5149	*
5150	* @returns VMCPU Handle.
5151	* @param pDevIns The device instance.
5152	*/
5153	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5154
5155	/**
5156	* The the VM CPU ID of the current thread (restricted API).
5157	*
5158	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5159	* @param pDevIns The device instance.
5160	*/
5161	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5162
5163	/**
5164	* Translates a timer handle to a pointer.
5165	*
5166	* @returns The time address.
5167	* @param pDevIns The device instance.
5168	* @param hTimer The timer handle.
5169	*/
5170	DECLR0CALLBACKMEMBER(PTMTIMERR0, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5171
5172	/** @name Timer handle method wrappers
5173	* @{ */
5174	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5175	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5176	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5177	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5178	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5179	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5180	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5181	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5182	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5183	/** Takes the clock lock then enters the specified critical section. */
5184	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5185	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5186	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5187	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5188	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5189	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5190	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5191	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5192	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5193	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5194	/** @} */
5195
5196	/**
5197	* Get the current virtual clock time in a VM. The clock frequency must be
5198	* queried separately.
5199	*
5200	* @returns Current clock time.
5201	* @param pDevIns The device instance.
5202	*/
5203	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5204
5205	/**
5206	* Get the frequency of the virtual clock.
5207	*
5208	* @returns The clock frequency (not variable at run-time).
5209	* @param pDevIns The device instance.
5210	*/
5211	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5212
5213	/**
5214	* Get the current virtual clock time in a VM, in nanoseconds.
5215	*
5216	* @returns Current clock time (in ns).
5217	* @param pDevIns The device instance.
5218	*/
5219	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5220
5221	/** @name Exported PDM Queue Functions
5222	* @{ */
5223	DECLR0CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5224	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5225	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5226	DECLR0CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
5227	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5228	/** @} */
5229
5230	/** @name PDM Task
5231	* @{ */
5232	/**
5233	* Triggers the running the given task.
5234	*
5235	* @returns VBox status code.
5236	* @retval VINF_ALREADY_POSTED is the task is already pending.
5237	* @param pDevIns The device instance.
5238	* @param hTask The task to trigger.
5239	* @thread Any thread.
5240	*/
5241	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5242	/** @} */
5243
5244	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5245	* These semaphores can be signalled from ring-0.
5246	* @{ */
5247	/** @sa SUPSemEventSignal */
5248	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5249	/** @sa SUPSemEventWaitNoResume */
5250	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5251	/** @sa SUPSemEventWaitNsAbsIntr */
5252	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5253	/** @sa SUPSemEventWaitNsRelIntr */
5254	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5255	/** @sa SUPSemEventGetResolution */
5256	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5257	/** @} */
5258
5259	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5260	* These semaphores can be signalled from ring-0.
5261	* @{ */
5262	/** @sa SUPSemEventMultiSignal */
5263	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5264	/** @sa SUPSemEventMultiReset */
5265	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5266	/** @sa SUPSemEventMultiWaitNoResume */
5267	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5268	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5269	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5270	/** @sa SUPSemEventMultiWaitNsRelIntr */
5271	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5272	/** @sa SUPSemEventMultiGetResolution */
5273	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5274	/** @} */
5275
5276	/**
5277	* Gets the NOP critical section.
5278	*
5279	* @returns The ring-3 address of the NOP critical section.
5280	* @param pDevIns The device instance.
5281	*/
5282	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5283
5284	/**
5285	* Changes the device level critical section from the automatically created
5286	* default to one desired by the device constructor.
5287	*
5288	* Must first be done in ring-3.
5289	*
5290	* @returns VBox status code.
5291	* @param pDevIns The device instance.
5292	* @param pCritSect The critical section to use. NULL is not
5293	* valid, instead use the NOP critical
5294	* section.
5295	*/
5296	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5297
5298	/** @name Exported PDM Critical Section Functions
5299	* @{ */
5300	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5301	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5302	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5303	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5304	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5305	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5306	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5307	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5308	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5309	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5310	/** @} */
5311
5312	/**
5313	* Gets the trace buffer handle.
5314	*
5315	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5316	* really inteded for direct usage, thus no inline wrapper function.
5317	*
5318	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5319	* @param pDevIns The device instance.
5320	*/
5321	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5322
5323	/**
5324	* Sets up the PCI bus for the ring-0 context.
5325	*
5326	* This must be called after ring-3 has registered the PCI bus using
5327	* PDMDevHlpPCIBusRegister().
5328	*
5329	* @returns VBox status code.
5330	* @param pDevIns The device instance.
5331	* @param pPciBusReg The PCI bus registration information for ring-0,
5332	* considered volatile and copied.
5333	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5334	*/
5335	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5336
5337	/**
5338	* Sets up the IOMMU for the ring-0 context.
5339	*
5340	* This must be called after ring-3 has registered the IOMMU using
5341	* PDMDevHlpIommuRegister().
5342	*
5343	* @returns VBox status code.
5344	* @param pDevIns The device instance.
5345	* @param pIommuReg The IOMMU registration information for ring-0,
5346	* considered volatile and copied.
5347	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5348	*/
5349	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5350
5351	/**
5352	* Sets up the PIC for the ring-0 context.
5353	*
5354	* This must be called after ring-3 has registered the PIC using
5355	* PDMDevHlpPICRegister().
5356	*
5357	* @returns VBox status code.
5358	* @param pDevIns The device instance.
5359	* @param pPicReg The PIC registration information for ring-0,
5360	* considered volatile and copied.
5361	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5362	*/
5363	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5364
5365	/**
5366	* Sets up the APIC for the ring-0 context.
5367	*
5368	* This must be called after ring-3 has registered the APIC using
5369	* PDMDevHlpApicRegister().
5370	*
5371	* @returns VBox status code.
5372	* @param pDevIns The device instance.
5373	*/
5374	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5375
5376	/**
5377	* Sets up the IOAPIC for the ring-0 context.
5378	*
5379	* This must be called after ring-3 has registered the PIC using
5380	* PDMDevHlpIoApicRegister().
5381	*
5382	* @returns VBox status code.
5383	* @param pDevIns The device instance.
5384	* @param pIoApicReg The PIC registration information for ring-0,
5385	* considered volatile and copied.
5386	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5387	*/
5388	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5389
5390	/**
5391	* Sets up the HPET for the ring-0 context.
5392	*
5393	* This must be called after ring-3 has registered the PIC using
5394	* PDMDevHlpHpetRegister().
5395	*
5396	* @returns VBox status code.
5397	* @param pDevIns The device instance.
5398	* @param pHpetReg The PIC registration information for ring-0,
5399	* considered volatile and copied.
5400	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5401	*/
5402	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5403
5404	/** Space reserved for future members.
5405	* @{ */
5406	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5407	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5408	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5409	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5410	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5411	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5412	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5413	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5414	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5415	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5416	/** @} */
5417
5418	/** Just a safety precaution. */
5419	uint32_t u32TheEnd;
5420	} PDMDEVHLPR0;
5421	/** Pointer PDM Device R0 API. */
5422	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5423	/** Pointer PDM Device GC API. */
5424	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5425
5426	/** Current PDMDEVHLP version number. */
5427	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 18, 0)
5428
5429
5430	/**
5431	* PDM Device Instance.
5432	*/
5433	typedef struct PDMDEVINSR3
5434	{
5435	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5436	uint32_t u32Version;
5437	/** Device instance number. */
5438	uint32_t iInstance;
5439	/** Size of the ring-3, raw-mode and shared bits. */
5440	uint32_t cbRing3;
5441	/** Set if ring-0 context is enabled. */
5442	bool fR0Enabled;
5443	/** Set if raw-mode context is enabled. */
5444	bool fRCEnabled;
5445	/** Alignment padding. */
5446	bool afReserved[2];
5447	/** Pointer the HC PDM Device API. */
5448	PCPDMDEVHLPR3 pHlpR3;
5449	/** Pointer to the shared device instance data. */
5450	RTR3PTR pvInstanceDataR3;
5451	/** Pointer to the device instance data for ring-3. */
5452	RTR3PTR pvInstanceDataForR3;
5453	/** The critical section for the device.
5454	*
5455	* TM and IOM will enter this critical section before calling into the device
5456	* code. PDM will when doing power on, power off, reset, suspend and resume
5457	* notifications. SSM will currently not, but this will be changed later on.
5458	*
5459	* The device gets a critical section automatically assigned to it before
5460	* the constructor is called. If the constructor wishes to use a different
5461	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5462	* very early on.
5463	*/
5464	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5465	/** Pointer to device registration structure. */
5466	R3PTRTYPE(PCPDMDEVREG) pReg;
5467	/** Configuration handle. */
5468	R3PTRTYPE(PCFGMNODE) pCfg;
5469	/** The base interface of the device.
5470	*
5471	* The device constructor initializes this if it has any
5472	* device level interfaces to export. To obtain this interface
5473	* call PDMR3QueryDevice(). */
5474	PDMIBASE IBase;
5475
5476	/** Tracing indicator. */
5477	uint32_t fTracing;
5478	/** The tracing ID of this device. */
5479	uint32_t idTracing;
5480
5481	/** Ring-3 pointer to the raw-mode device instance. */
5482	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5483	/** Raw-mode address of the raw-mode device instance. */
5484	RTRGPTR pDevInsForRC;
5485	/** Ring-3 pointer to the raw-mode instance data. */
5486	RTR3PTR pvInstanceDataForRCR3;
5487
5488	/** PCI device structure size. */
5489	uint32_t cbPciDev;
5490	/** Number of PCI devices in apPciDevs. */
5491	uint32_t cPciDevs;
5492	/** Pointer to the PCI devices for this device.
5493	* (Allocated after the shared instance data.)
5494	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5495	* two devices ever needing it can use cbPciDev and do the address
5496	* calculations that for entries 8+. */
5497	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5498
5499	/** Temporarily. */
5500	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5501	/** Temporarily. */
5502	RTR0PTR pvInstanceDataR0;
5503	/** Temporarily. */
5504	RTRCPTR pvInstanceDataRC;
5505	/** Align the internal data more naturally. */
5506	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5507
5508	/** Internal data. */
5509	union
5510	{
5511	#ifdef PDMDEVINSINT_DECLARED
5512	PDMDEVINSINTR3 s;
5513	#endif
5514	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
5515	} Internal;
5516
5517	/** Device instance data for ring-3. The size of this area is defined
5518	* in the PDMDEVREG::cbInstanceR3 field. */
5519	char achInstanceData[8];
5520	} PDMDEVINSR3;
5521
5522	/** Current PDMDEVINSR3 version number. */
5523	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5524
5525	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5526	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5527
5528
5529	/**
5530	* PDM ring-0 device instance.
5531	*/
5532	typedef struct PDMDEVINSR0
5533	{
5534	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5535	uint32_t u32Version;
5536	/** Device instance number. */
5537	uint32_t iInstance;
5538
5539	/** Pointer the HC PDM Device API. */
5540	PCPDMDEVHLPR0 pHlpR0;
5541	/** Pointer to the shared device instance data. */
5542	RTR0PTR pvInstanceDataR0;
5543	/** Pointer to the device instance data for ring-0. */
5544	RTR0PTR pvInstanceDataForR0;
5545	/** The critical section for the device.
5546	*
5547	* TM and IOM will enter this critical section before calling into the device
5548	* code. PDM will when doing power on, power off, reset, suspend and resume
5549	* notifications. SSM will currently not, but this will be changed later on.
5550	*
5551	* The device gets a critical section automatically assigned to it before
5552	* the constructor is called. If the constructor wishes to use a different
5553	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5554	* very early on.
5555	*/
5556	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5557	/** Pointer to the ring-0 device registration structure. */
5558	R0PTRTYPE(PCPDMDEVREGR0) pReg;
5559	/** Ring-3 address of the ring-3 device instance. */
5560	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5561	/** Ring-0 pointer to the ring-3 device instance. */
5562	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5563	/** Ring-0 pointer to the ring-3 instance data. */
5564	RTR0PTR pvInstanceDataForR3R0;
5565	/** Raw-mode address of the raw-mode device instance. */
5566	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5567	/** Ring-0 pointer to the raw-mode device instance. */
5568	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5569	/** Ring-0 pointer to the raw-mode instance data. */
5570	RTR0PTR pvInstanceDataForRCR0;
5571
5572	/** PCI device structure size. */
5573	uint32_t cbPciDev;
5574	/** Number of PCI devices in apPciDevs. */
5575	uint32_t cPciDevs;
5576	/** Pointer to the PCI devices for this device.
5577	* (Allocated after the shared instance data.)
5578	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5579	* two devices ever needing it can use cbPciDev and do the address
5580	* calculations that for entries 8+. */
5581	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5582
5583	/** Align the internal data more naturally. */
5584	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5585
5586	/** Internal data. */
5587	union
5588	{
5589	#ifdef PDMDEVINSINT_DECLARED
5590	PDMDEVINSINTR0 s;
5591	#endif
5592	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
5593	} Internal;
5594
5595	/** Device instance data for ring-0. The size of this area is defined
5596	* in the PDMDEVREG::cbInstanceR0 field. */
5597	char achInstanceData[8];
5598	} PDMDEVINSR0;
5599
5600	/** Current PDMDEVINSR0 version number. */
5601	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5602
5603
5604	/**
5605	* PDM raw-mode device instance.
5606	*/
5607	typedef struct PDMDEVINSRC
5608	{
5609	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5610	uint32_t u32Version;
5611	/** Device instance number. */
5612	uint32_t iInstance;
5613
5614	/** Pointer the HC PDM Device API. */
5615	PCPDMDEVHLPRC pHlpRC;
5616	/** Pointer to the shared device instance data. */
5617	RTRGPTR pvInstanceDataRC;
5618	/** Pointer to the device instance data for raw-mode. */
5619	RTRGPTR pvInstanceDataForRC;
5620	/** The critical section for the device.
5621	*
5622	* TM and IOM will enter this critical section before calling into the device
5623	* code. PDM will when doing power on, power off, reset, suspend and resume
5624	* notifications. SSM will currently not, but this will be changed later on.
5625	*
5626	* The device gets a critical section automatically assigned to it before
5627	* the constructor is called. If the constructor wishes to use a different
5628	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5629	* very early on.
5630	*/
5631	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5632	/** Pointer to the raw-mode device registration structure. */
5633	RGPTRTYPE(PCPDMDEVREGRC) pReg;
5634
5635	/** PCI device structure size. */
5636	uint32_t cbPciDev;
5637	/** Number of PCI devices in apPciDevs. */
5638	uint32_t cPciDevs;
5639	/** Pointer to the PCI devices for this device.
5640	* (Allocated after the shared instance data.) */
5641	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5642
5643	/** Align the internal data more naturally. */
5644	uint32_t au32Padding[14];
5645
5646	/** Internal data. */
5647	union
5648	{
5649	#ifdef PDMDEVINSINT_DECLARED
5650	PDMDEVINSINTRC s;
5651	#endif
5652	uint8_t padding[0x10];
5653	} Internal;
5654
5655	/** Device instance data for ring-0. The size of this area is defined
5656	* in the PDMDEVREG::cbInstanceR0 field. */
5657	char achInstanceData[8];
5658	} PDMDEVINSRC;
5659
5660	/** Current PDMDEVINSR0 version number. */
5661	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5662
5663
5664	/** @def PDM_DEVINS_VERSION
5665	* Current PDMDEVINS version number. */
5666	/** @typedef PDMDEVINS
5667	* The device instance structure for the current context. */
5668	#ifdef IN_RING3
5669	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5670	typedef PDMDEVINSR3 PDMDEVINS;
5671	#elif defined(IN_RING0)
5672	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5673	typedef PDMDEVINSR0 PDMDEVINS;
5674	#elif defined(IN_RC)
5675	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5676	typedef PDMDEVINSRC PDMDEVINS;
5677	#else
5678	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5679	#endif
5680
5681	/**
5682	* Get the pointer to an PCI device.
5683	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5684	*/
5685	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5686	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5687	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5688
5689	/**
5690	* Calc the pointer to of a given PCI device.
5691	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5692	*/
5693	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5694	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5695	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
5696	: (PPDMPCIDEV)NULL )
5697
5698
5699	/**
5700	* Checks the structure versions of the device instance and device helpers,
5701	* returning if they are incompatible.
5702	*
5703	* This is for use in the constructor.
5704	*
5705	* @param pDevIns The device instance pointer.
5706	*/
5707	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5708	do \
5709	{ \
5710	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5711	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5712	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5713	VERR_PDM_DEVINS_VERSION_MISMATCH); \
5714	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5715	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5716	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5717	} while (0)
5718
5719	/**
5720	* Quietly checks the structure versions of the device instance and device
5721	* helpers, returning if they are incompatible.
5722	*
5723	* This is for use in the destructor.
5724	*
5725	* @param pDevIns The device instance pointer.
5726	*/
5727	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5728	do \
5729	{ \
5730	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5731	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5732	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5733	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5734	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5735	} while (0)
5736
5737	/**
5738	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
5739	* constructor - returns on failure.
5740	*
5741	* This should be invoked after having initialized the instance data
5742	* sufficiently for the correct operation of the destructor. The destructor is
5743	* always called!
5744	*
5745	* @param pDevIns Pointer to the PDM device instance.
5746	* @param pszValidValues Patterns describing the valid value names. See
5747	* RTStrSimplePatternMultiMatch for details on the
5748	* pattern syntax.
5749	* @param pszValidNodes Patterns describing the valid node (key) names.
5750	* Pass empty string if no valid nodes.
5751	*/
5752	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5753	do \
5754	{ \
5755	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5756	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5757	if (RT_SUCCESS(rcValCfg)) \
5758	{ /* likely */ } else return rcValCfg; \
5759	} while (0)
5760
5761	/** @def PDMDEV_ASSERT_EMT
5762	* Assert that the current thread is the emulation thread.
5763	*/
5764	#ifdef VBOX_STRICT
5765	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5766	#else
5767	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5768	#endif
5769
5770	/** @def PDMDEV_ASSERT_OTHER
5771	* Assert that the current thread is NOT the emulation thread.
5772	*/
5773	#ifdef VBOX_STRICT
5774	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5775	#else
5776	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5777	#endif
5778
5779	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5780	* Assert that the current thread is owner of the VM lock.
5781	*/
5782	#ifdef VBOX_STRICT
5783	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5784	#else
5785	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5786	#endif
5787
5788	/** @def PDMDEV_SET_ERROR
5789	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5790	*/
5791	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5792	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5793
5794	/** @def PDMDEV_SET_RUNTIME_ERROR
5795	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5796	*/
5797	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5798	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5799
5800	/** @def PDMDEVINS_2_RCPTR
5801	* Converts a PDM Device instance pointer a RC PDM Device instance pointer.
5802	*/
5803	#ifdef IN_RC
5804	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5805	#else
5806	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5807	#endif
5808
5809	/** @def PDMDEVINS_2_R3PTR
5810	* Converts a PDM Device instance pointer a R3 PDM Device instance pointer.
5811	*/
5812	#ifdef IN_RING3
5813	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5814	#else
5815	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5816	#endif
5817
5818	/** @def PDMDEVINS_2_R0PTR
5819	* Converts a PDM Device instance pointer a R0 PDM Device instance pointer.
5820	*/
5821	#ifdef IN_RING0
5822	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5823	#else
5824	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5825	#endif
5826
5827	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5828	* Converts a PDM device instance data pointer to a ring-0 one.
5829	* @deprecated
5830	*/
5831	#ifdef IN_RING0
5832	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5833	#else
5834	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5835	#endif
5836
5837
5838	/** @def PDMDEVINS_2_DATA
5839	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
5840	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5841	*
5842	* @note Do no use this macro in common code working on a core structure which
5843	* device specific code has expanded.
5844	*/
5845	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5846	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5847	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5848	{ \
5849	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5850	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5851	return pLambdaRet; \
5852	}(a_pDevIns))
5853	#else
5854	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5855	#endif
5856
5857	/** @def PDMDEVINS_2_DATA_CC
5858	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5859	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5860	*
5861	* @note Do no use this macro in common code working on a core structure which
5862	* device specific code has expanded.
5863	*/
5864	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5865	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5866	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5867	{ \
5868	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5869	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5870	return pLambdaRet; \
5871	}(a_pDevIns))
5872	#else
5873	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5874	#endif
5875
5876
5877	#ifdef IN_RING3
5878
5879	/**
5880	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
5881	*/
5882	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5883	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
5884	PIOMIOPORTHANDLE phIoPorts)
5885	{
5886	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5887	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5888	if (RT_SUCCESS(rc))
5889	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5890	return rc;
5891	}
5892
5893	/**
5894	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
5895	*/
5896	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5897	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
5898	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5899	{
5900	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5901	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5902	if (RT_SUCCESS(rc))
5903	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5904	return rc;
5905	}
5906
5907	/**
5908	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
5909	*/
5910	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5911	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5912	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5913	{
5914	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5915	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5916	if (RT_SUCCESS(rc))
5917	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5918	return rc;
5919	}
5920
5921	/**
5922	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
5923	*/
5924	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5925	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5926	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5927	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5928	{
5929	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5930	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5931	if (RT_SUCCESS(rc))
5932	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5933	return rc;
5934	}
5935
5936	/**
5937	* @sa PDMDevHlpIoPortCreateEx
5938	*/
5939	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5940	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
5941	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5942	{
5943	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
5944	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5945	}
5946
5947
5948	/**
5949	* @sa PDMDevHlpIoPortCreateEx
5950	*/
5951	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5952	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
5953	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5954	{
5955	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5956	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5957	}
5958
5959	/**
5960	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
5961	*/
5962	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
5963	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5964	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5965	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5966	{
5967	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
5968	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5969	}
5970
5971	/**
5972	* @copydoc PDMDEVHLPR3::pfnIoPortMap
5973	*/
5974	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
5975	{
5976	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
5977	}
5978
5979	/**
5980	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
5981	*/
5982	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5983	{
5984	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
5985	}
5986
5987	/**
5988	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
5989	*/
5990	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5991	{
5992	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
5993	}
5994
5995
5996	#endif /* IN_RING3 */
5997	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
5998
5999	/**
6000	* @sa PDMDevHlpIoPortSetUpContextEx
6001	*/
6002	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6003	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6004	{
6005	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6006	}
6007
6008	/**
6009	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6010	*/
6011	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6012	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6013	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6014	{
6015	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6016	}
6017
6018	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6019	#ifdef IN_RING3
6020
6021	/**
6022	* @sa PDMDevHlpMmioCreateEx
6023	*/
6024	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6025	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6026	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6027	{
6028	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6029	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6030	}
6031
6032	/**
6033	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6034	*/
6035	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6036	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6037	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6038	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6039	{
6040	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6041	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6042	}
6043
6044	/**
6045	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6046	*/
6047	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6048	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6049	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6050	{
6051	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6052	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6053	if (RT_SUCCESS(rc))
6054	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6055	return rc;
6056	}
6057
6058	/**
6059	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6060	*/
6061	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6062	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6063	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6064	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6065	{
6066	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6067	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6068	if (RT_SUCCESS(rc))
6069	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6070	return rc;
6071	}
6072
6073	/**
6074	* @copydoc PDMDEVHLPR3::pfnMmioMap
6075	*/
6076	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6077	{
6078	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6079	}
6080
6081	/**
6082	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6083	*/
6084	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6085	{
6086	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6087	}
6088
6089	/**
6090	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6091	*/
6092	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6093	{
6094	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6095	}
6096
6097	/**
6098	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6099	*/
6100	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6101	{
6102	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6103	}
6104
6105	#endif /* IN_RING3 */
6106	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6107
6108	/**
6109	* @sa PDMDevHlpMmioSetUpContextEx
6110	*/
6111	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6112	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6113	{
6114	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6115	}
6116
6117	/**
6118	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6119	*/
6120	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6121	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6122	{
6123	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6124	}
6125
6126	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6127	#ifdef IN_RING3
6128
6129	/**
6130	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6131	*/
6132	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6133	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6134	{
6135	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6136	}
6137
6138	/**
6139	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6140	*/
6141	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6142	{
6143	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6144	}
6145
6146	/**
6147	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6148	*/
6149	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6150	{
6151	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6152	}
6153
6154	/**
6155	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6156	*/
6157	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6158	{
6159	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6160	}
6161
6162	/**
6163	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6164	*/
6165	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6166	{
6167	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6168	}
6169
6170	#endif /* IN_RING3 */
6171	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6172
6173	/**
6174	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6175	*/
6176	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6177	size_t offSub, size_t cbSub, void **ppvMapping)
6178	{
6179	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6180	}
6181
6182	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6183	#ifdef IN_RING3
6184
6185	/**
6186	* @copydoc PDMDEVHLPR3::pfnROMRegister
6187	*/
6188	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6189	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6190	{
6191	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6192	}
6193
6194	/**
6195	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6196	*/
6197	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6198	{
6199	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6200	}
6201
6202	/**
6203	* Register a save state data unit.
6204	*
6205	* @returns VBox status.
6206	* @param pDevIns The device instance.
6207	* @param uVersion Data layout version number.
6208	* @param cbGuess The approximate amount of data in the unit.
6209	* Only for progress indicators.
6210	* @param pfnSaveExec Execute save callback, optional.
6211	* @param pfnLoadExec Execute load callback, optional.
6212	*/
6213	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6214	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6215	{
6216	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6217	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6218	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6219	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6220	}
6221
6222	/**
6223	* Register a save state data unit with a live save callback as well.
6224	*
6225	* @returns VBox status.
6226	* @param pDevIns The device instance.
6227	* @param uVersion Data layout version number.
6228	* @param cbGuess The approximate amount of data in the unit.
6229	* Only for progress indicators.
6230	* @param pfnLiveExec Execute live callback, optional.
6231	* @param pfnSaveExec Execute save callback, optional.
6232	* @param pfnLoadExec Execute load callback, optional.
6233	*/
6234	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6235	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6236	{
6237	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6238	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6239	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6240	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6241	}
6242
6243	/**
6244	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6245	*/
6246	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6247	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6248	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6249	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6250	{
6251	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6252	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6253	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6254	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6255	}
6256
6257	/**
6258	* @copydoc PDMDEVHLPR3::pfnTMTimerCreate
6259	*/
6260	DECLINLINE(int) PDMDevHlpTMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6261	uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
6262	{
6263	return pDevIns->pHlpR3->pfnTMTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
6264	}
6265
6266	/**
6267	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6268	*/
6269	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6270	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6271	{
6272	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6273	}
6274
6275	#endif /* IN_RING3 */
6276
6277	/**
6278	* @copydoc PDMDEVHLPR3::pfnTimerToPtr
6279	*/
6280	DECLINLINE(PTMTIMER) PDMDevHlpTimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6281	{
6282	return pDevIns->CTX_SUFF(pHlp)->pfnTimerToPtr(pDevIns, hTimer);
6283	}
6284
6285	/**
6286	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6287	*/
6288	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6289	{
6290	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6291	}
6292
6293	/**
6294	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6295	*/
6296	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6297	{
6298	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6299	}
6300
6301	/**
6302	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6303	*/
6304	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6305	{
6306	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6307	}
6308
6309	/**
6310	* @copydoc PDMDEVHLPR3::pfnTimerGet
6311	*/
6312	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6313	{
6314	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6315	}
6316
6317	/**
6318	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6319	*/
6320	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6321	{
6322	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6323	}
6324
6325	/**
6326	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6327	*/
6328	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6329	{
6330	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6331	}
6332
6333	/**
6334	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6335	*/
6336	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6337	{
6338	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6339	}
6340
6341	/**
6342	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6343	*/
6344	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6345	{
6346	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6347	}
6348
6349	/**
6350	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
6351	*/
6352	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6353	{
6354	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6355	}
6356
6357	/**
6358	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6359	*/
6360	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6361	{
6362	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6363	}
6364
6365	/**
6366	* @copydoc PDMDEVHLPR3::pfnTimerSet
6367	*/
6368	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6369	{
6370	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6371	}
6372
6373	/**
6374	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6375	*/
6376	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6377	{
6378	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6379	}
6380
6381	/**
6382	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6383	*/
6384	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6385	{
6386	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6387	}
6388
6389	/**
6390	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6391	*/
6392	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6393	{
6394	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6395	}
6396
6397	/**
6398	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6399	*/
6400	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6401	{
6402	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6403	}
6404
6405	/**
6406	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6407	*/
6408	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6409	{
6410	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6411	}
6412
6413	/**
6414	* @copydoc PDMDEVHLPR3::pfnTimerStop
6415	*/
6416	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6417	{
6418	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6419	}
6420
6421	/**
6422	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6423	*/
6424	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6425	{
6426	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6427	}
6428
6429	/**
6430	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6431	*/
6432	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6433	{
6434	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6435	}
6436
6437	#ifdef IN_RING3
6438
6439	/**
6440	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6441	*/
6442	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6443	{
6444	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6445	}
6446
6447	/**
6448	* @copydoc PDMDEVHLPR3::pfnTimerSave
6449	*/
6450	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6451	{
6452	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6453	}
6454
6455	/**
6456	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6457	*/
6458	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6459	{
6460	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6461	}
6462
6463	/**
6464	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6465	*/
6466	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6467	{
6468	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6469	}
6470
6471	/**
6472	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6473	*/
6474	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6475	{
6476	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6477	}
6478
6479	#endif
6480
6481	/**
6482	* Read physical memory - unknown data usage.
6483	*
6484	* @returns VINF_SUCCESS (for now).
6485	* @param pDevIns The device instance.
6486	* @param GCPhys Physical address start reading from.
6487	* @param pvBuf Where to put the read bits.
6488	* @param cbRead How many bytes to read.
6489	* @thread Any thread, but the call may involve the emulation thread.
6490	*/
6491	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6492	{
6493	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6494	}
6495
6496	/**
6497	* Write to physical memory - unknown data usage.
6498	*
6499	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6500	* @param pDevIns The device instance.
6501	* @param GCPhys Physical address to write to.
6502	* @param pvBuf What to write.
6503	* @param cbWrite How many bytes to write.
6504	* @thread Any thread, but the call may involve the emulation thread.
6505	*/
6506	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6507	{
6508	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6509	}
6510
6511	/**
6512	* Read physical memory - reads meta data processed by the device.
6513	*
6514	* @returns VINF_SUCCESS (for now).
6515	* @param pDevIns The device instance.
6516	* @param GCPhys Physical address start reading from.
6517	* @param pvBuf Where to put the read bits.
6518	* @param cbRead How many bytes to read.
6519	* @thread Any thread, but the call may involve the emulation thread.
6520	*/
6521	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6522	{
6523	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6524	}
6525
6526	/**
6527	* Write to physical memory - written data was created/altered by the device.
6528	*
6529	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6530	* @param pDevIns The device instance.
6531	* @param GCPhys Physical address to write to.
6532	* @param pvBuf What to write.
6533	* @param cbWrite How many bytes to write.
6534	* @thread Any thread, but the call may involve the emulation thread.
6535	*/
6536	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6537	{
6538	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6539	}
6540
6541	/**
6542	* Read physical memory - read data will not be touched by the device.
6543	*
6544	* @returns VINF_SUCCESS (for now).
6545	* @param pDevIns The device instance.
6546	* @param GCPhys Physical address start reading from.
6547	* @param pvBuf Where to put the read bits.
6548	* @param cbRead How many bytes to read.
6549	* @thread Any thread, but the call may involve the emulation thread.
6550	*/
6551	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6552	{
6553	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6554	}
6555
6556	/**
6557	* Write to physical memory - written data was not touched/created by the device.
6558	*
6559	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6560	* @param pDevIns The device instance.
6561	* @param GCPhys Physical address to write to.
6562	* @param pvBuf What to write.
6563	* @param cbWrite How many bytes to write.
6564	* @thread Any thread, but the call may involve the emulation thread.
6565	*/
6566	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6567	{
6568	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6569	}
6570
6571	#ifdef IN_RING3
6572
6573	/**
6574	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6575	*/
6576	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6577	{
6578	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6579	}
6580
6581	/**
6582	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6583	*/
6584	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6585	PPGMPAGEMAPLOCK pLock)
6586	{
6587	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6588	}
6589
6590	/**
6591	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6592	*/
6593	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6594	{
6595	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6596	}
6597
6598	/**
6599	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6600	*/
6601	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6602	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6603	{
6604	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6605	}
6606
6607	/**
6608	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6609	*/
6610	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6611	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6612	{
6613	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6614	}
6615
6616	/**
6617	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6618	*/
6619	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6620	{
6621	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6622	}
6623
6624	/**
6625	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
6626	*/
6627	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
6628	{
6629	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
6630	}
6631
6632	/**
6633	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6634	*/
6635	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6636	{
6637	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6638	}
6639
6640	/**
6641	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6642	*/
6643	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6644	{
6645	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6646	}
6647
6648	/**
6649	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6650	*/
6651	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6652	{
6653	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6654	}
6655
6656	/**
6657	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6658	*/
6659	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6660	{
6661	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6662	}
6663
6664	/**
6665	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6666	*/
6667	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6668	{
6669	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6670	}
6671
6672	/**
6673	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
6674	*/
6675	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6676	{
6677	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6678	}
6679	#endif /* IN_RING3 */
6680
6681	/**
6682	* @copydoc PDMDEVHLPR3::pfnVMState
6683	*/
6684	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6685	{
6686	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6687	}
6688
6689	#ifdef IN_RING3
6690	/**
6691	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6692	*/
6693	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6694	{
6695	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6696	}
6697	#endif /* IN_RING3 */
6698
6699	/**
6700	* @copydoc PDMDEVHLPR3::pfnVMSetError
6701	*/
6702	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6703	const char *pszFormat, ...)
6704	{
6705	va_list va;
6706	va_start(va, pszFormat);
6707	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6708	va_end(va);
6709	return rc;
6710	}
6711
6712	/**
6713	* @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError
6714	*/
6715	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6716	const char *pszFormat, ...)
6717	{
6718	va_list va;
6719	int rc;
6720	va_start(va, pszFormat);
6721	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6722	va_end(va);
6723	return rc;
6724	}
6725
6726	/**
6727	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6728	*
6729	* @returns VBox status code which must be passed up to the VMM. This will be
6730	* VINF_SUCCESS in non-strict builds.
6731	* @param pDevIns The device instance.
6732	* @param SRC_POS Use RT_SRC_POS.
6733	* @param pszFormat Message. (optional)
6734	* @param ... Message parameters.
6735	*/
6736	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6737	{
6738	#ifdef VBOX_STRICT
6739	# ifdef IN_RING3
6740	int rc;
6741	va_list args;
6742	va_start(args, pszFormat);
6743	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6744	va_end(args);
6745	return rc;
6746	# else
6747	NOREF(pDevIns);
6748	NOREF(pszFile);
6749	NOREF(iLine);
6750	NOREF(pszFunction);
6751	NOREF(pszFormat);
6752	return VINF_EM_DBG_STOP;
6753	# endif
6754	#else
6755	NOREF(pDevIns);
6756	NOREF(pszFile);
6757	NOREF(iLine);
6758	NOREF(pszFunction);
6759	NOREF(pszFormat);
6760	return VINF_SUCCESS;
6761	#endif
6762	}
6763
6764	#ifdef IN_RING3
6765
6766	/**
6767	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6768	*/
6769	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6770	{
6771	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6772	}
6773
6774	/**
6775	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6776	*/
6777	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6778	{
6779	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6780	}
6781
6782	/**
6783	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6784	*/
6785	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6786	{
6787	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6788	}
6789
6790	/**
6791	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
6792	*/
6793	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
6794	{
6795	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6796	}
6797
6798	/**
6799	* Same as pfnSTAMRegister except that the name is specified in a
6800	* RTStrPrintf like fashion.
6801	*
6802	* @returns VBox status.
6803	* @param pDevIns Device instance of the DMA.
6804	* @param pvSample Pointer to the sample.
6805	* @param enmType Sample type. This indicates what pvSample is
6806	* pointing at.
6807	* @param enmVisibility Visibility type specifying whether unused
6808	* statistics should be visible or not.
6809	* @param enmUnit Sample unit.
6810	* @param pszDesc Sample description.
6811	* @param pszName Sample name format string, unix path style. If
6812	* this does not start with a '/', the default
6813	* prefix will be prepended, otherwise it will be
6814	* used as-is.
6815	* @param ... Arguments to the format string.
6816	*/
6817	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6818	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6819	const char pszDesc, const char pszName, ...)
6820	{
6821	va_list va;
6822	va_start(va, pszName);
6823	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6824	va_end(va);
6825	}
6826
6827	/**
6828	* Registers the device with the default PCI bus.
6829	*
6830	* @returns VBox status code.
6831	* @param pDevIns The device instance.
6832	* @param pPciDev The PCI device structure.
6833	* This must be kept in the instance data.
6834	* The PCI configuration must be initialized before registration.
6835	*/
6836	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6837	{
6838	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
6839	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6840	}
6841
6842	/**
6843	* @copydoc PDMDEVHLPR3::pfnPCIRegister
6844	*/
6845	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6846	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6847	{
6848	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6849	}
6850
6851	/**
6852	* Initialize MSI emulation support for the first PCI device.
6853	*
6854	* @returns VBox status code.
6855	* @param pDevIns The device instance.
6856	* @param pMsiReg MSI emulation registration structure.
6857	*/
6858	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6859	{
6860	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6861	}
6862
6863	/**
6864	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6865	*/
6866	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6867	{
6868	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6869	}
6870
6871	/**
6872	* Registers a I/O port region for the default PCI device.
6873	*
6874	* @returns VBox status code.
6875	* @param pDevIns The device instance.
6876	* @param iRegion The region number.
6877	* @param cbRegion Size of the region.
6878	* @param hIoPorts Handle to the I/O port region.
6879	*/
6880	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
6881	{
6882	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6883	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
6884	}
6885
6886	/**
6887	* Registers a I/O port region for the default PCI device, custom map/unmap.
6888	*
6889	* @returns VBox status code.
6890	* @param pDevIns The device instance.
6891	* @param iRegion The region number.
6892	* @param cbRegion Size of the region.
6893	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6894	* callback will be invoked holding only the PDM lock.
6895	* The device lock will _not_ be taken (due to lock
6896	* order).
6897	*/
6898	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6899	PFNPCIIOREGIONMAP pfnMapUnmap)
6900	{
6901	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6902	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6903	UINT64_MAX, pfnMapUnmap);
6904	}
6905
6906	/**
6907	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
6908	* and registering an I/O port region for the default PCI device.
6909	*
6910	* @returns VBox status code.
6911	* @param pDevIns The device instance to register the ports with.
6912	* @param cPorts The count of I/O ports in the region (the size).
6913	* @param iPciRegion The PCI device region.
6914	* @param pfnOut Pointer to function which is gonna handle OUT
6915	* operations. Optional.
6916	* @param pfnIn Pointer to function which is gonna handle IN operations.
6917	* Optional.
6918	* @param pvUser User argument to pass to the callbacks.
6919	* @param pszDesc Pointer to description string. This must not be freed.
6920	* @param paExtDescs Extended per-port descriptions, optional. Partial range
6921	* coverage is allowed. This must not be freed.
6922	* @param phIoPorts Where to return the I/O port range handle.
6923	*
6924	*/
6925	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
6926	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6927	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6928
6929	{
6930	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
6931	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6932	if (RT_SUCCESS(rc))
6933	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
6934	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6935	phIoPorts, NULL /pfnMapUnmap*/);
6936	return rc;
6937	}
6938
6939	/**
6940	* Registers an MMIO region for the default PCI device.
6941	*
6942	* @returns VBox status code.
6943	* @param pDevIns The device instance.
6944	* @param iRegion The region number.
6945	* @param cbRegion Size of the region.
6946	* @param enmType PCI_ADDRESS_SPACE_MEM or
6947	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6948	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6949	* @param hMmioRegion Handle to the MMIO region.
6950	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6951	* callback will be invoked holding only the PDM lock.
6952	* The device lock will _not_ be taken (due to lock
6953	* order).
6954	*/
6955	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
6956	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
6957	{
6958	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6959	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6960	hMmioRegion, pfnMapUnmap);
6961	}
6962
6963	/**
6964	* Registers an MMIO region for the default PCI device, extended version.
6965	*
6966	* @returns VBox status code.
6967	* @param pDevIns The device instance.
6968	* @param pPciDev The PCI device structure.
6969	* @param iRegion The region number.
6970	* @param cbRegion Size of the region.
6971	* @param enmType PCI_ADDRESS_SPACE_MEM or
6972	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6973	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6974	* @param hMmioRegion Handle to the MMIO region.
6975	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6976	* callback will be invoked holding only the PDM lock.
6977	* The device lock will _not_ be taken (due to lock
6978	* order).
6979	*/
6980	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
6981	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
6982	PFNPCIIOREGIONMAP pfnMapUnmap)
6983	{
6984	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
6985	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6986	hMmioRegion, pfnMapUnmap);
6987	}
6988
6989	/**
6990	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
6991	* and registering an MMIO region for the default PCI device.
6992	*
6993	* @returns VBox status code.
6994	* @param pDevIns The device instance to register the ports with.
6995	* @param cbRegion The size of the region in bytes.
6996	* @param iPciRegion The PCI device region.
6997	* @param enmType PCI_ADDRESS_SPACE_MEM or
6998	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6999	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7000	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7001	* @param pfnWrite Pointer to function which is gonna handle Write
7002	* operations.
7003	* @param pfnRead Pointer to function which is gonna handle Read
7004	* operations.
7005	* @param pvUser User argument to pass to the callbacks.
7006	* @param pszDesc Pointer to description string. This must not be freed.
7007	* @param phRegion Where to return the MMIO region handle.
7008	*
7009	*/
7010	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7011	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7012	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7013
7014	{
7015	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7016	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7017	if (RT_SUCCESS(rc))
7018	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7019	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7020	phRegion, NULL /pfnMapUnmap*/);
7021	return rc;
7022	}
7023
7024
7025	/**
7026	* Registers an MMIO2 region for the default PCI device.
7027	*
7028	* @returns VBox status code.
7029	* @param pDevIns The device instance.
7030	* @param iRegion The region number.
7031	* @param cbRegion Size of the region.
7032	* @param enmType PCI_ADDRESS_SPACE_MEM or
7033	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7034	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7035	* @param hMmio2Region Handle to the MMIO2 region.
7036	*/
7037	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7038	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7039	{
7040	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7041	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7042	hMmio2Region, NULL);
7043	}
7044
7045	/**
7046	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7047	* and registering an MMIO2 region for the default PCI device, extended edition.
7048	*
7049	* @returns VBox status code.
7050	* @param pDevIns The device instance to register the ports with.
7051	* @param cbRegion The size of the region in bytes.
7052	* @param iPciRegion The PCI device region.
7053	* @param enmType PCI_ADDRESS_SPACE_MEM or
7054	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7055	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7056	* @param pszDesc Pointer to description string. This must not be freed.
7057	* @param ppvMapping Where to store the address of the ring-3 mapping of
7058	* the memory.
7059	* @param phRegion Where to return the MMIO2 region handle.
7060	*
7061	*/
7062	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7063	PCIADDRESSSPACE enmType, const char *pszDesc,
7064	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7065
7066	{
7067	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7068	pszDesc, ppvMapping, phRegion);
7069	if (RT_SUCCESS(rc))
7070	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7071	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7072	phRegion, NULL /pfnCallback*/);
7073	return rc;
7074	}
7075
7076	/**
7077	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7078	* and registering an MMIO2 region for the default PCI device.
7079	*
7080	* @returns VBox status code.
7081	* @param pDevIns The device instance to register the ports with.
7082	* @param cbRegion The size of the region in bytes.
7083	* @param iPciRegion The PCI device region.
7084	* @param enmType PCI_ADDRESS_SPACE_MEM or
7085	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7086	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7087	* @param fMmio2Flags To be defined, must be zero.
7088	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7089	* callback will be invoked holding only the PDM lock.
7090	* The device lock will _not_ be taken (due to lock
7091	* order).
7092	* @param pszDesc Pointer to description string. This must not be freed.
7093	* @param ppvMapping Where to store the address of the ring-3 mapping of
7094	* the memory.
7095	* @param phRegion Where to return the MMIO2 region handle.
7096	*
7097	*/
7098	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7099	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7100	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
7101
7102	{
7103	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7104	pszDesc, ppvMapping, phRegion);
7105	if (RT_SUCCESS(rc))
7106	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7107	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7108	*phRegion, pfnMapUnmap);
7109	return rc;
7110	}
7111
7112	/**
7113	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7114	*/
7115	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7116	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7117	{
7118	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7119	}
7120
7121	/**
7122	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7123	*/
7124	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7125	unsigned cb, uint32_t *pu32Value)
7126	{
7127	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7128	}
7129
7130	/**
7131	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7132	*/
7133	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7134	unsigned cb, uint32_t u32Value)
7135	{
7136	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7137	}
7138
7139	#endif /* IN_RING3 */
7140
7141	/**
7142	* Bus master physical memory read from the default PCI device.
7143	*
7144	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7145	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7146	* @param pDevIns The device instance.
7147	* @param GCPhys Physical address start reading from.
7148	* @param pvBuf Where to put the read bits.
7149	* @param cbRead How many bytes to read.
7150	* @thread Any thread, but the call may involve the emulation thread.
7151	*/
7152	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7153	{
7154	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7155	}
7156
7157	/**
7158	* Bus master physical memory read - unknown data usage.
7159	*
7160	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7161	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7162	* @param pDevIns The device instance.
7163	* @param pPciDev The PCI device structure. If NULL the default
7164	* PCI device for this device instance is used.
7165	* @param GCPhys Physical address start reading from.
7166	* @param pvBuf Where to put the read bits.
7167	* @param cbRead How many bytes to read.
7168	* @thread Any thread, but the call may involve the emulation thread.
7169	*/
7170	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7171	{
7172	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7173	}
7174
7175	/**
7176	* Bus master physical memory read from the default PCI device.
7177	*
7178	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7179	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7180	* @param pDevIns The device instance.
7181	* @param GCPhys Physical address start reading from.
7182	* @param pvBuf Where to put the read bits.
7183	* @param cbRead How many bytes to read.
7184	* @thread Any thread, but the call may involve the emulation thread.
7185	*/
7186	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7187	{
7188	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7189	}
7190
7191	/**
7192	* Bus master physical memory read - reads meta data processed by the device.
7193	*
7194	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7195	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7196	* @param pDevIns The device instance.
7197	* @param pPciDev The PCI device structure. If NULL the default
7198	* PCI device for this device instance is used.
7199	* @param GCPhys Physical address start reading from.
7200	* @param pvBuf Where to put the read bits.
7201	* @param cbRead How many bytes to read.
7202	* @thread Any thread, but the call may involve the emulation thread.
7203	*/
7204	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7205	{
7206	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7207	}
7208
7209	/**
7210	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
7211	*
7212	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7213	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7214	* @param pDevIns The device instance.
7215	* @param GCPhys Physical address start reading from.
7216	* @param pvBuf Where to put the read bits.
7217	* @param cbRead How many bytes to read.
7218	* @thread Any thread, but the call may involve the emulation thread.
7219	*/
7220	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7221	{
7222	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7223	}
7224
7225	/**
7226	* Bus master physical memory read - read data will not be touched by the device.
7227	*
7228	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7229	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7230	* @param pDevIns The device instance.
7231	* @param pPciDev The PCI device structure. If NULL the default
7232	* PCI device for this device instance is used.
7233	* @param GCPhys Physical address start reading from.
7234	* @param pvBuf Where to put the read bits.
7235	* @param cbRead How many bytes to read.
7236	* @thread Any thread, but the call may involve the emulation thread.
7237	*/
7238	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7239	{
7240	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7241	}
7242
7243	/**
7244	* Bus master physical memory write from the default PCI device - unknown data usage.
7245	*
7246	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7247	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7248	* @param pDevIns The device instance.
7249	* @param GCPhys Physical address to write to.
7250	* @param pvBuf What to write.
7251	* @param cbWrite How many bytes to write.
7252	* @thread Any thread, but the call may involve the emulation thread.
7253	*/
7254	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7255	{
7256	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7257	}
7258
7259	/**
7260	* Bus master physical memory write - unknown data usage.
7261	*
7262	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7263	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7264	* @param pDevIns The device instance.
7265	* @param pPciDev The PCI device structure. If NULL the default
7266	* PCI device for this device instance is used.
7267	* @param GCPhys Physical address to write to.
7268	* @param pvBuf What to write.
7269	* @param cbWrite How many bytes to write.
7270	* @thread Any thread, but the call may involve the emulation thread.
7271	*/
7272	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7273	{
7274	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7275	}
7276
7277	/**
7278	* Bus master physical memory write from the default PCI device.
7279	*
7280	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7281	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7282	* @param pDevIns The device instance.
7283	* @param GCPhys Physical address to write to.
7284	* @param pvBuf What to write.
7285	* @param cbWrite How many bytes to write.
7286	* @thread Any thread, but the call may involve the emulation thread.
7287	*/
7288	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7289	{
7290	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7291	}
7292
7293	/**
7294	* Bus master physical memory write - written data was created/altered by the device.
7295	*
7296	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7297	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7298	* @param pDevIns The device instance.
7299	* @param pPciDev The PCI device structure. If NULL the default
7300	* PCI device for this device instance is used.
7301	* @param GCPhys Physical address to write to.
7302	* @param pvBuf What to write.
7303	* @param cbWrite How many bytes to write.
7304	* @thread Any thread, but the call may involve the emulation thread.
7305	*/
7306	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7307	{
7308	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7309	}
7310
7311	/**
7312	* Bus master physical memory write from the default PCI device.
7313	*
7314	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7315	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7316	* @param pDevIns The device instance.
7317	* @param GCPhys Physical address to write to.
7318	* @param pvBuf What to write.
7319	* @param cbWrite How many bytes to write.
7320	* @thread Any thread, but the call may involve the emulation thread.
7321	*/
7322	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7323	{
7324	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7325	}
7326
7327	/**
7328	* Bus master physical memory write - written data was not touched/created by the device.
7329	*
7330	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7331	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7332	* @param pDevIns The device instance.
7333	* @param pPciDev The PCI device structure. If NULL the default
7334	* PCI device for this device instance is used.
7335	* @param GCPhys Physical address to write to.
7336	* @param pvBuf What to write.
7337	* @param cbWrite How many bytes to write.
7338	* @thread Any thread, but the call may involve the emulation thread.
7339	*/
7340	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7341	{
7342	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7343	}
7344
7345	#ifdef IN_RING3
7346	/**
7347	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
7348	*/
7349	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7350	void **ppv, PPGMPAGEMAPLOCK pLock)
7351	{
7352	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7353	}
7354
7355	/**
7356	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
7357	*/
7358	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7359	void const **ppv, PPGMPAGEMAPLOCK pLock)
7360	{
7361	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7362	}
7363
7364	/**
7365	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
7366	*/
7367	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7368	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
7369	PPGMPAGEMAPLOCK paLocks)
7370	{
7371	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
7372	paLocks);
7373	}
7374
7375	/**
7376	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
7377	*/
7378	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7379	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
7380	PPGMPAGEMAPLOCK paLocks)
7381	{
7382	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
7383	papvPages, paLocks);
7384	}
7385	#endif /* IN_RING3 */
7386
7387	/**
7388	* Sets the IRQ for the default PCI device.
7389	*
7390	* @param pDevIns The device instance.
7391	* @param iIrq IRQ number to set.
7392	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7393	* @thread Any thread, but will involve the emulation thread.
7394	*/
7395	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7396	{
7397	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7398	}
7399
7400	/**
7401	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
7402	*/
7403	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7404	{
7405	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7406	}
7407
7408	/**
7409	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7410	* the request when not called from EMT.
7411	*
7412	* @param pDevIns The device instance.
7413	* @param iIrq IRQ number to set.
7414	* @param iLevel IRQ level.
7415	* @thread Any thread, but will involve the emulation thread.
7416	*/
7417	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7418	{
7419	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7420	}
7421
7422	/**
7423	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7424	*/
7425	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7426	{
7427	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7428	}
7429
7430	/**
7431	* @copydoc PDMDEVHLPR3::pfnISASetIrq
7432	*/
7433	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7434	{
7435	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7436	}
7437
7438	/**
7439	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7440	*/
7441	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7442	{
7443	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7444	}
7445
7446	#ifdef IN_RING3
7447
7448	/**
7449	* @copydoc PDMDEVHLPR3::pfnDriverAttach
7450	*/
7451	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
7452	{
7453	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7454	}
7455
7456	/**
7457	* @copydoc PDMDEVHLPR3::pfnDriverDetach
7458	*/
7459	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7460	{
7461	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7462	}
7463
7464	/**
7465	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
7466	*/
7467	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
7468	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
7469	{
7470	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
7471	}
7472
7473	/**
7474	* Reconfigures with a single driver reattachement, no config, noflags.
7475	* @sa PDMDevHlpDriverReconfigure
7476	*/
7477	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
7478	{
7479	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
7480	}
7481
7482	/**
7483	* Reconfigures with a two drivers reattachement, no config, noflags.
7484	* @sa PDMDevHlpDriverReconfigure
7485	*/
7486	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
7487	{
7488	char const * apszDrivers[2];
7489	apszDrivers[0] = pszDriver0;
7490	apszDrivers[1] = pszDriver1;
7491	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
7492	}
7493
7494	/**
7495	* @copydoc PDMDEVHLPR3::pfnQueueCreatePtr
7496	*/
7497	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7498	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PPDMQUEUE ppQueue)
7499	{
7500	return pDevIns->pHlpR3->pfnQueueCreatePtr(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
7501	}
7502
7503	/**
7504	* @copydoc PDMDEVHLPR3::pfnQueueCreate
7505	*/
7506	DECLINLINE(int) PDMDevHlpQueueCreateNew(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7507	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
7508	{
7509	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7510	}
7511
7512	#endif /* IN_RING3 */
7513
7514	/**
7515	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
7516	*/
7517	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7518	{
7519	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7520	}
7521
7522	/**
7523	* @copydoc PDMDEVHLPR3::pfnQueueInsert
7524	*/
7525	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7526	{
7527	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7528	}
7529
7530	/**
7531	* @copydoc PDMDEVHLPR3::pfnQueueInsertEx
7532	*/
7533	DECLINLINE(void) PDMDevHlpQueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay)
7534	{
7535	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsertEx(pDevIns, hQueue, pItem, cNanoMaxDelay);
7536	}
7537
7538	/**
7539	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7540	*/
7541	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7542	{
7543	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7544	}
7545
7546	#ifdef IN_RING3
7547	/**
7548	* @copydoc PDMDEVHLPR3::pfnTaskCreate
7549	*/
7550	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7551	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
7552	{
7553	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7554	}
7555	#endif
7556
7557	/**
7558	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
7559	*/
7560	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7561	{
7562	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7563	}
7564
7565	#ifdef IN_RING3
7566
7567	/**
7568	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7569	*/
7570	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7571	{
7572	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7573	}
7574
7575	/**
7576	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7577	*/
7578	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7579	{
7580	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7581	}
7582
7583	#endif /* IN_RING3 */
7584
7585	/**
7586	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7587	*/
7588	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7589	{
7590	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7591	}
7592
7593	/**
7594	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7595	*/
7596	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7597	{
7598	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7599	}
7600
7601	/**
7602	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7603	*/
7604	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7605	{
7606	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7607	}
7608
7609	/**
7610	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7611	*/
7612	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7613	{
7614	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7615	}
7616
7617	/**
7618	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7619	*/
7620	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7621	{
7622	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7623	}
7624
7625	#ifdef IN_RING3
7626
7627	/**
7628	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7629	*/
7630	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7631	{
7632	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7633	}
7634
7635	/**
7636	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7637	*/
7638	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7639	{
7640	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7641	}
7642
7643	#endif /* IN_RING3 */
7644
7645	/**
7646	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7647	*/
7648	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7649	{
7650	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7651	}
7652
7653	/**
7654	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7655	*/
7656	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7657	{
7658	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7659	}
7660
7661	/**
7662	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7663	*/
7664	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7665	{
7666	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7667	}
7668
7669	/**
7670	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7671	*/
7672	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7673	{
7674	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7675	}
7676
7677	/**
7678	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7679	*/
7680	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7681	{
7682	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7683	}
7684
7685	/**
7686	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7687	*/
7688	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7689	{
7690	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7691	}
7692
7693	#ifdef IN_RING3
7694
7695	/**
7696	* Initializes a PDM critical section.
7697	*
7698	* The PDM critical sections are derived from the IPRT critical sections, but
7699	* works in RC and R0 as well.
7700	*
7701	* @returns VBox status code.
7702	* @param pDevIns The device instance.
7703	* @param pCritSect Pointer to the critical section.
7704	* @param SRC_POS Use RT_SRC_POS.
7705	* @param pszNameFmt Format string for naming the critical section.
7706	* For statistics and lock validation.
7707	* @param ... Arguments for the format string.
7708	*/
7709	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7710	const char *pszNameFmt, ...)
7711	{
7712	int rc;
7713	va_list va;
7714	va_start(va, pszNameFmt);
7715	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7716	va_end(va);
7717	return rc;
7718	}
7719
7720	#endif /* IN_RING3 */
7721
7722	/**
7723	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7724	*/
7725	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7726	{
7727	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7728	}
7729
7730	#ifdef IN_RING3
7731
7732	/**
7733	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopR0
7734	*/
7735	DECLINLINE(R0PTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopR0(PPDMDEVINS pDevIns)
7736	{
7737	return pDevIns->pHlpR3->pfnCritSectGetNopR0(pDevIns);
7738	}
7739
7740	/**
7741	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopRC
7742	*/
7743	DECLINLINE(RCPTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopRC(PPDMDEVINS pDevIns)
7744	{
7745	return pDevIns->pHlpR3->pfnCritSectGetNopRC(pDevIns);
7746	}
7747
7748	#endif /* IN_RING3 */
7749
7750	/**
7751	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7752	*/
7753	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7754	{
7755	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7756	}
7757
7758	/**
7759	* @copydoc PDMCritSectEnter
7760	* @param pDevIns The device instance.
7761	*/
7762	DECLINLINE(int) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7763	{
7764	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7765	}
7766
7767	/**
7768	* @copydoc PDMCritSectEnterDebug
7769	* @param pDevIns The device instance.
7770	*/
7771	DECLINLINE(int) PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7772	{
7773	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7774	}
7775
7776	/**
7777	* @copydoc PDMCritSectTryEnter
7778	* @param pDevIns The device instance.
7779	*/
7780	DECLINLINE(int) PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7781	{
7782	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7783	}
7784
7785	/**
7786	* @copydoc PDMCritSectTryEnterDebug
7787	* @param pDevIns The device instance.
7788	*/
7789	DECLINLINE(int) PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7790	{
7791	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7792	}
7793
7794	/**
7795	* @copydoc PDMCritSectLeave
7796	* @param pDevIns The device instance.
7797	*/
7798	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7799	{
7800	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7801	}
7802
7803	/**
7804	* @copydoc PDMCritSectIsOwner
7805	* @param pDevIns The device instance.
7806	*/
7807	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7808	{
7809	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7810	}
7811
7812	/**
7813	* @copydoc PDMCritSectIsInitialized
7814	* @param pDevIns The device instance.
7815	*/
7816	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7817	{
7818	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
7819	}
7820
7821	/**
7822	* @copydoc PDMCritSectHasWaiters
7823	* @param pDevIns The device instance.
7824	*/
7825	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7826	{
7827	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
7828	}
7829
7830	/**
7831	* @copydoc PDMCritSectGetRecursion
7832	* @param pDevIns The device instance.
7833	*/
7834	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7835	{
7836	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
7837	}
7838
7839	#if defined(IN_RING3) \|\| defined(IN_RING0)
7840	/**
7841	* @copydoc PDMHCCritSectScheduleExitEvent
7842	* @param pDevIns The device instance.
7843	*/
7844	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
7845	{
7846	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
7847	}
7848	#endif
7849
7850	/* Strict build: Remap the two enter calls to the debug versions. */
7851	#ifdef VBOX_STRICT
7852	# ifdef IPRT_INCLUDED_asm_h
7853	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7854	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7855	# else
7856	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
7857	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
7858	# endif
7859	#endif
7860
7861	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
7862
7863	/**
7864	* @copydoc PDMR3CritSectDelete
7865	* @param pDevIns The device instance.
7866	*/
7867	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7868	{
7869	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
7870	}
7871
7872	/**
7873	* @copydoc PDMDEVHLPR3::pfnThreadCreate
7874	*/
7875	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
7876	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
7877	{
7878	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
7879	}
7880
7881	/**
7882	* @copydoc PDMR3ThreadDestroy
7883	* @param pDevIns The device instance.
7884	*/
7885	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
7886	{
7887	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
7888	}
7889
7890	/**
7891	* @copydoc PDMR3ThreadIAmSuspending
7892	* @param pDevIns The device instance.
7893	*/
7894	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7895	{
7896	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
7897	}
7898
7899	/**
7900	* @copydoc PDMR3ThreadIAmRunning
7901	* @param pDevIns The device instance.
7902	*/
7903	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7904	{
7905	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
7906	}
7907
7908	/**
7909	* @copydoc PDMR3ThreadSleep
7910	* @param pDevIns The device instance.
7911	*/
7912	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
7913	{
7914	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
7915	}
7916
7917	/**
7918	* @copydoc PDMR3ThreadSuspend
7919	* @param pDevIns The device instance.
7920	*/
7921	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7922	{
7923	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
7924	}
7925
7926	/**
7927	* @copydoc PDMR3ThreadResume
7928	* @param pDevIns The device instance.
7929	*/
7930	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7931	{
7932	return pDevIns->pHlpR3->pfnThreadResume(pThread);
7933	}
7934
7935	/**
7936	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
7937	*/
7938	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
7939	{
7940	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
7941	}
7942
7943	/**
7944	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
7945	*/
7946	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
7947	{
7948	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
7949	}
7950
7951	/**
7952	* @copydoc PDMDEVHLPR3::pfnA20Set
7953	*/
7954	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
7955	{
7956	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
7957	}
7958
7959	/**
7960	* @copydoc PDMDEVHLPR3::pfnRTCRegister
7961	*/
7962	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
7963	{
7964	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
7965	}
7966
7967	/**
7968	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
7969	*/
7970	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
7971	{
7972	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
7973	}
7974
7975	/**
7976	* @copydoc PDMDEVHLPR3::pfnIommuRegister
7977	*/
7978	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
7979	{
7980	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
7981	}
7982
7983	/**
7984	* @copydoc PDMDEVHLPR3::pfnPICRegister
7985	*/
7986	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
7987	{
7988	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
7989	}
7990
7991	/**
7992	* @copydoc PDMDEVHLPR3::pfnApicRegister
7993	*/
7994	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
7995	{
7996	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
7997	}
7998
7999	/**
8000	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
8001	*/
8002	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8003	{
8004	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
8005	}
8006
8007	/**
8008	* @copydoc PDMDEVHLPR3::pfnHpetRegister
8009	*/
8010	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
8011	{
8012	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
8013	}
8014
8015	/**
8016	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
8017	*/
8018	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
8019	{
8020	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
8021	}
8022
8023	/**
8024	* @copydoc PDMDEVHLPR3::pfnDMACRegister
8025	*/
8026	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
8027	{
8028	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
8029	}
8030
8031	/**
8032	* @copydoc PDMDEVHLPR3::pfnDMARegister
8033	*/
8034	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
8035	{
8036	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
8037	}
8038
8039	/**
8040	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
8041	*/
8042	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
8043	{
8044	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
8045	}
8046
8047	/**
8048	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
8049	*/
8050	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
8051	{
8052	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
8053	}
8054
8055	/**
8056	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
8057	*/
8058	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
8059	{
8060	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
8061	}
8062
8063	/**
8064	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
8065	*/
8066	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
8067	{
8068	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
8069	}
8070
8071	/**
8072	* @copydoc PDMDEVHLPR3::pfnDMASchedule
8073	*/
8074	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
8075	{
8076	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
8077	}
8078
8079	/**
8080	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
8081	*/
8082	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
8083	{
8084	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
8085	}
8086
8087	/**
8088	* @copydoc PDMDEVHLPR3::pfnCMOSRead
8089	*/
8090	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
8091	{
8092	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
8093	}
8094
8095	/**
8096	* @copydoc PDMDEVHLPR3::pfnCallR0
8097	*/
8098	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
8099	{
8100	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
8101	}
8102
8103	/**
8104	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
8105	*/
8106	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
8107	{
8108	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
8109	}
8110
8111	/**
8112	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
8113	*/
8114	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
8115	{
8116	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
8117	}
8118
8119	/**
8120	* @copydoc PDMDEVHLPR3::pfnGetUVM
8121	*/
8122	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
8123	{
8124	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
8125	}
8126
8127	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
8128
8129	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8130
8131	/**
8132	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
8133	*/
8134	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
8135	{
8136	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
8137	}
8138
8139	/**
8140	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
8141	*/
8142	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
8143	{
8144	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
8145	}
8146
8147	/**
8148	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
8149	*/
8150	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8151	{
8152	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
8153	}
8154
8155	/**
8156	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
8157	*/
8158	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
8159	{
8160	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
8161	}
8162
8163	/**
8164	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
8165	*/
8166	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8167	{
8168	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
8169	}
8170
8171	/**
8172	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
8173	*/
8174	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
8175	{
8176	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
8177	}
8178
8179	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
8180
8181	/**
8182	* @copydoc PDMDEVHLPR3::pfnGetVM
8183	*/
8184	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
8185	{
8186	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
8187	}
8188
8189	/**
8190	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
8191	*/
8192	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
8193	{
8194	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
8195	}
8196
8197	/**
8198	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
8199	*/
8200	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
8201	{
8202	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
8203	}
8204
8205	/**
8206	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
8207	*/
8208	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
8209	{
8210	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
8211	}
8212
8213	/**
8214	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8215	*/
8216	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8217	{
8218	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8219	}
8220
8221	/**
8222	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8223	*/
8224	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8225	{
8226	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8227	}
8228
8229	#ifdef IN_RING3
8230
8231	/**
8232	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8233	*/
8234	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8235	{
8236	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
8237	}
8238
8239	/**
8240	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
8241	*/
8242	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
8243	{
8244	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
8245	}
8246
8247	/**
8248	* @copydoc PDMDEVHLPR3::pfnVMReset
8249	*/
8250	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
8251	{
8252	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
8253	}
8254
8255	/**
8256	* @copydoc PDMDEVHLPR3::pfnVMSuspend
8257	*/
8258	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8259	{
8260	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8261	}
8262
8263	/**
8264	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8265	*/
8266	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8267	{
8268	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8269	}
8270
8271	/**
8272	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
8273	*/
8274	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8275	{
8276	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8277	}
8278
8279	#endif /* IN_RING3 */
8280
8281	/**
8282	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8283	*/
8284	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8285	{
8286	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8287	}
8288
8289	#ifdef IN_RING3
8290
8291	/**
8292	* @copydoc PDMDEVHLPR3::pfnGetCpuId
8293	*/
8294	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
8295	{
8296	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8297	}
8298
8299	/**
8300	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8301	*/
8302	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8303	{
8304	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8305	}
8306
8307	/**
8308	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8309	*/
8310	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8311	{
8312	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8313	}
8314
8315	/**
8316	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
8317	*/
8318	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
8319	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
8320	const char pszHandlerR0, const char pszPfHandlerR0,
8321	const char pszHandlerRC, const char pszPfHandlerRC,
8322	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
8323	{
8324	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
8325	pszHandlerR0, pszPfHandlerR0,
8326	pszHandlerRC, pszPfHandlerRC,
8327	pszDesc, phType);
8328	}
8329
8330	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
8331	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8332	do { \
8333	uint32_t u32GetEnumTmp = 0; \
8334	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
8335	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8336	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
8337	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
8338	} while (0)
8339
8340	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
8341	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8342	do { \
8343	uint8_t bGetEnumTmp = 0; \
8344	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
8345	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8346	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
8347	} while (0)
8348
8349	#endif /* IN_RING3 */
8350
8351	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
8352	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
8353
8354	/**
8355	* Callbacks for VBoxDeviceRegister().
8356	*/
8357	typedef struct PDMDEVREGCB
8358	{
8359	/** Interface version.
8360	* This is set to PDM_DEVREG_CB_VERSION. */
8361	uint32_t u32Version;
8362
8363	/**
8364	* Registers a device with the current VM instance.
8365	*
8366	* @returns VBox status code.
8367	* @param pCallbacks Pointer to the callback table.
8368	* @param pReg Pointer to the device registration record.
8369	* This data must be permanent and readonly.
8370	*/
8371	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
8372	} PDMDEVREGCB;
8373
8374	/** Current version of the PDMDEVREGCB structure. */
8375	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
8376
8377
8378	/**
8379	* The VBoxDevicesRegister callback function.
8380	*
8381	* PDM will invoke this function after loading a device module and letting
8382	* the module decide which devices to register and how to handle conflicts.
8383	*
8384	* @returns VBox status code.
8385	* @param pCallbacks Pointer to the callback table.
8386	* @param u32Version VBox version number.
8387	*/
8388	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
8389
8390	/** @} */
8391
8392	RT_C_DECLS_END
8393
8394	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 86661

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