VirtualBox

source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 87542

Last change on this file since 87542 was 87477, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 PDM IOMMU code de-duplication and cleanup.
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1/** @file
2 * PDM - Pluggable Device Manager, Devices.
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27#define VBOX_INCLUDED_vmm_pdmdev_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmqueue.h>
34#include <VBox/vmm/pdmtask.h>
35#ifdef IN_RING3
36# include <VBox/vmm/pdmthread.h>
37#endif
38#include <VBox/vmm/pdmifs.h>
39#include <VBox/vmm/pdmins.h>
40#include <VBox/vmm/pdmcommon.h>
41#include <VBox/vmm/pdmpcidev.h>
42#include <VBox/vmm/iom.h>
43#include <VBox/vmm/tm.h>
44#include <VBox/vmm/ssm.h>
45#include <VBox/vmm/cfgm.h>
46#include <VBox/vmm/cpum.h>
47#include <VBox/vmm/dbgf.h>
48#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
49#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
50#include <VBox/msi.h>
51#include <iprt/stdarg.h>
52#include <iprt/list.h>
53
54
55RT_C_DECLS_BEGIN
56
57/** @defgroup grp_pdm_device The PDM Devices API
58 * @ingroup grp_pdm
59 * @{
60 */
61
62/**
63 * Construct a device instance for a VM.
64 *
65 * @returns VBox status.
66 * @param pDevIns The device instance data. If the registration structure
67 * is needed, it can be accessed thru pDevIns->pReg.
68 * @param iInstance Instance number. Use this to figure out which registers
69 * and such to use. The instance number is also found in
70 * pDevIns->iInstance, but since it's likely to be
71 * frequently used PDM passes it as parameter.
72 * @param pCfg Configuration node handle for the driver. This is
73 * expected to be in high demand in the constructor and is
74 * therefore passed as an argument. When using it at other
75 * times, it can be found in pDevIns->pCfg.
76 */
77typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
78/** Pointer to a FNPDMDEVCONSTRUCT() function. */
79typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
80
81/**
82 * Destruct a device instance.
83 *
84 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
85 * resources can be freed correctly.
86 *
87 * @returns VBox status.
88 * @param pDevIns The device instance data.
89 *
90 * @remarks The device critical section is not entered. The routine may delete
91 * the critical section, so the caller cannot exit it.
92 */
93typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
94/** Pointer to a FNPDMDEVDESTRUCT() function. */
95typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
96
97/**
98 * Device relocation callback.
99 *
100 * This is called when the instance data has been relocated in raw-mode context
101 * (RC). It is also called when the RC hypervisor selects changes. The device
102 * must fixup all necessary pointers and re-query all interfaces to other RC
103 * devices and drivers.
104 *
105 * Before the RC code is executed the first time, this function will be called
106 * with a 0 delta so RC pointer calculations can be one in one place.
107 *
108 * @param pDevIns Pointer to the device instance.
109 * @param offDelta The relocation delta relative to the old location.
110 *
111 * @remarks A relocation CANNOT fail.
112 *
113 * @remarks The device critical section is not entered. The relocations should
114 * not normally require any locking.
115 */
116typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
117/** Pointer to a FNPDMDEVRELOCATE() function. */
118typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
119
120/**
121 * Power On notification.
122 *
123 * @returns VBox status.
124 * @param pDevIns The device instance data.
125 *
126 * @remarks Caller enters the device critical section.
127 */
128typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
129/** Pointer to a FNPDMDEVPOWERON() function. */
130typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
131
132/**
133 * Reset notification.
134 *
135 * @returns VBox status.
136 * @param pDevIns The device instance data.
137 *
138 * @remarks Caller enters the device critical section.
139 */
140typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
141/** Pointer to a FNPDMDEVRESET() function. */
142typedef FNPDMDEVRESET *PFNPDMDEVRESET;
143
144/**
145 * Soft reset notification.
146 *
147 * This is mainly for emulating the 286 style protected mode exits, in which
148 * most devices should remain in their current state.
149 *
150 * @returns VBox status.
151 * @param pDevIns The device instance data.
152 * @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
153 *
154 * @remarks Caller enters the device critical section.
155 */
156typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
157/** Pointer to a FNPDMDEVSOFTRESET() function. */
158typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
159
160/** @name PDMVMRESET_F_XXX - VM reset flags.
161 * These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
162 * reset via PDMDevHlpVMReset.
163 * @{ */
164/** Unknown reason. */
165#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
166/** GIM triggered reset. */
167#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
168/** The last source always causing hard resets. */
169#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
170/** ACPI triggered reset. */
171#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
172/** PS/2 system port A (92h) reset. */
173#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
174/** Keyboard reset. */
175#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
176/** Tripple fault. */
177#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
178/** Reset source mask. */
179#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
180/** @} */
181
182/**
183 * Suspend notification.
184 *
185 * @returns VBox status.
186 * @param pDevIns The device instance data.
187 * @thread EMT(0)
188 *
189 * @remarks Caller enters the device critical section.
190 */
191typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
192/** Pointer to a FNPDMDEVSUSPEND() function. */
193typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
194
195/**
196 * Resume notification.
197 *
198 * @returns VBox status.
199 * @param pDevIns The device instance data.
200 *
201 * @remarks Caller enters the device critical section.
202 */
203typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
204/** Pointer to a FNPDMDEVRESUME() function. */
205typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
206
207/**
208 * Power Off notification.
209 *
210 * This is always called when VMR3PowerOff is called.
211 * There will be no callback when hot plugging devices.
212 *
213 * @param pDevIns The device instance data.
214 * @thread EMT(0)
215 *
216 * @remarks Caller enters the device critical section.
217 */
218typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
219/** Pointer to a FNPDMDEVPOWEROFF() function. */
220typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
221
222/**
223 * Attach command.
224 *
225 * This is called to let the device attach to a driver for a specified LUN
226 * at runtime. This is not called during VM construction, the device
227 * constructor has to attach to all the available drivers.
228 *
229 * This is like plugging in the keyboard or mouse after turning on the PC.
230 *
231 * @returns VBox status code.
232 * @param pDevIns The device instance.
233 * @param iLUN The logical unit which is being attached.
234 * @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
235 *
236 * @remarks Caller enters the device critical section.
237 */
238typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
239/** Pointer to a FNPDMDEVATTACH() function. */
240typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
241
242/**
243 * Detach notification.
244 *
245 * This is called when a driver is detaching itself from a LUN of the device.
246 * The device should adjust its state to reflect this.
247 *
248 * This is like unplugging the network cable to use it for the laptop or
249 * something while the PC is still running.
250 *
251 * @param pDevIns The device instance.
252 * @param iLUN The logical unit which is being detached.
253 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
254 *
255 * @remarks Caller enters the device critical section.
256 */
257typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
258/** Pointer to a FNPDMDEVDETACH() function. */
259typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
260
261/**
262 * Query the base interface of a logical unit.
263 *
264 * @returns VBOX status code.
265 * @param pDevIns The device instance.
266 * @param iLUN The logicial unit to query.
267 * @param ppBase Where to store the pointer to the base interface of the LUN.
268 *
269 * @remarks The device critical section is not entered.
270 */
271typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
272/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
273typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
274
275/**
276 * Init complete notification (after ring-0 & RC init since 5.1).
277 *
278 * This can be done to do communication with other devices and other
279 * initialization which requires everything to be in place.
280 *
281 * @returns VBOX status code.
282 * @param pDevIns The device instance.
283 *
284 * @remarks Caller enters the device critical section.
285 */
286typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
287/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
288typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
289
290
291/**
292 * The context of a pfnMemSetup call.
293 */
294typedef enum PDMDEVMEMSETUPCTX
295{
296 /** Invalid zero value. */
297 PDMDEVMEMSETUPCTX_INVALID = 0,
298 /** After construction. */
299 PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
300 /** After reset. */
301 PDMDEVMEMSETUPCTX_AFTER_RESET,
302 /** Type size hack. */
303 PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
304} PDMDEVMEMSETUPCTX;
305
306
307/**
308 * PDM Device Registration Structure.
309 *
310 * This structure is used when registering a device from VBoxInitDevices() in HC
311 * Ring-3. PDM will continue use till the VM is terminated.
312 *
313 * @note The first part is the same in every context.
314 */
315typedef struct PDMDEVREGR3
316{
317 /** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
318 uint32_t u32Version;
319 /** Reserved, must be zero. */
320 uint32_t uReserved0;
321 /** Device name, must match the ring-3 one. */
322 char szName[32];
323 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
324 uint32_t fFlags;
325 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
326 uint32_t fClass;
327 /** Maximum number of instances (per VM). */
328 uint32_t cMaxInstances;
329 /** The shared data structure version number. */
330 uint32_t uSharedVersion;
331 /** Size of the instance data. */
332 uint32_t cbInstanceShared;
333 /** Size of the ring-0 instance data. */
334 uint32_t cbInstanceCC;
335 /** Size of the raw-mode instance data. */
336 uint32_t cbInstanceRC;
337 /** Max number of PCI devices. */
338 uint16_t cMaxPciDevices;
339 /** Max number of MSI-X vectors in any of the PCI devices. */
340 uint16_t cMaxMsixVectors;
341 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
342 * remain unchanged from registration till VM destruction. */
343 const char *pszDescription;
344
345 /** Name of the raw-mode context module (no path).
346 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
347 const char *pszRCMod;
348 /** Name of the ring-0 module (no path).
349 * Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
350 const char *pszR0Mod;
351
352 /** Construct instance - required. */
353 PFNPDMDEVCONSTRUCT pfnConstruct;
354 /** Destruct instance - optional.
355 * Critical section NOT entered (will be destroyed). */
356 PFNPDMDEVDESTRUCT pfnDestruct;
357 /** Relocation command - optional.
358 * Critical section NOT entered. */
359 PFNPDMDEVRELOCATE pfnRelocate;
360 /**
361 * Memory setup callback.
362 *
363 * @param pDevIns The device instance data.
364 * @param enmCtx Indicates the context of the call.
365 * @remarks The critical section is entered prior to calling this method.
366 */
367 DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
368 /** Power on notification - optional.
369 * Critical section is entered. */
370 PFNPDMDEVPOWERON pfnPowerOn;
371 /** Reset notification - optional.
372 * Critical section is entered. */
373 PFNPDMDEVRESET pfnReset;
374 /** Suspend notification - optional.
375 * Critical section is entered. */
376 PFNPDMDEVSUSPEND pfnSuspend;
377 /** Resume notification - optional.
378 * Critical section is entered. */
379 PFNPDMDEVRESUME pfnResume;
380 /** Attach command - optional.
381 * Critical section is entered. */
382 PFNPDMDEVATTACH pfnAttach;
383 /** Detach notification - optional.
384 * Critical section is entered. */
385 PFNPDMDEVDETACH pfnDetach;
386 /** Query a LUN base interface - optional.
387 * Critical section is NOT entered. */
388 PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
389 /** Init complete notification - optional.
390 * Critical section is entered. */
391 PFNPDMDEVINITCOMPLETE pfnInitComplete;
392 /** Power off notification - optional.
393 * Critical section is entered. */
394 PFNPDMDEVPOWEROFF pfnPowerOff;
395 /** Software system reset notification - optional.
396 * Critical section is entered. */
397 PFNPDMDEVSOFTRESET pfnSoftReset;
398
399 /** @name Reserved for future extensions, must be zero.
400 * @{ */
401 DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
402 DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
403 DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
404 DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
405 DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
406 DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
407 DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
408 DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
409 /** @} */
410
411 /** Initialization safty marker. */
412 uint32_t u32VersionEnd;
413} PDMDEVREGR3;
414/** Pointer to a PDM Device Structure. */
415typedef PDMDEVREGR3 *PPDMDEVREGR3;
416/** Const pointer to a PDM Device Structure. */
417typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
418/** Current DEVREGR3 version number. */
419#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
420
421
422/** PDM Device Flags.
423 * @{ */
424/** This flag is used to indicate that the device has a R0 component. */
425#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
426/** Requires the ring-0 component, ignore configuration values. */
427#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
428/** Requires the ring-0 component, ignore configuration values. */
429#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
430
431/** This flag is used to indicate that the device has a RC component. */
432#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
433/** Requires the raw-mode component, ignore configuration values. */
434#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
435/** Requires the raw-mode component, ignore configuration values. */
436#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
437
438/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
439#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_RC)
440
441/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
442 * The bit count for the current host.
443 * @note Superfluous, but still around for hysterical raisins. */
444#if HC_ARCH_BITS == 32
445# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
446#elif HC_ARCH_BITS == 64
447# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
448#else
449# error Unsupported HC_ARCH_BITS value.
450#endif
451/** The host bit count mask. */
452#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
453
454/** The device support only 32-bit guests. */
455#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
456/** The device support only 64-bit guests. */
457#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
458/** The device support both 32-bit & 64-bit guests. */
459#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
460/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
461 * The guest bit count for the current compilation. */
462#if GC_ARCH_BITS == 32
463# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
464#elif GC_ARCH_BITS == 64
465# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
466#else
467# error Unsupported GC_ARCH_BITS value.
468#endif
469/** The guest bit count mask. */
470#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
471
472/** A convenience. */
473#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
474
475/** Indicates that the device needs to be notified before the drivers when suspending. */
476#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
477/** Indicates that the device needs to be notified before the drivers when powering off. */
478#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
479/** Indicates that the device needs to be notified before the drivers when resetting. */
480#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
481
482/** This flag is used to indicate that the device has been converted to the
483 * new device style. */
484#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
485
486/** @} */
487
488
489/** PDM Device Classes.
490 * The order is important, lower bit earlier instantiation.
491 * @{ */
492/** Architecture device. */
493#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
494/** Architecture BIOS device. */
495#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
496/** PCI bus brigde. */
497#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
498/** PCI built-in device (e.g. PCI root complex devices). */
499#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
500/** Input device (mouse, keyboard, joystick, HID, ...). */
501#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
502/** Interrupt controller (PIC). */
503#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
504/** Interval controoler (PIT). */
505#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
506/** RTC/CMOS. */
507#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
508/** DMA controller. */
509#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
510/** VMM Device. */
511#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
512/** Graphics device, like VGA. */
513#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
514/** Storage controller device. */
515#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
516/** Network interface controller. */
517#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
518/** Audio. */
519#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
520/** USB HIC. */
521#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
522/** ACPI. */
523#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
524/** Serial controller device. */
525#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
526/** Parallel controller device */
527#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
528/** Host PCI pass-through device */
529#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
530/** Misc devices (always last). */
531#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
532/** @} */
533
534
535/**
536 * PDM Device Registration Structure, ring-0.
537 *
538 * This structure is used when registering a device from VBoxInitDevices() in HC
539 * Ring-0. PDM will continue use till the VM is terminated.
540 */
541typedef struct PDMDEVREGR0
542{
543 /** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
544 uint32_t u32Version;
545 /** Reserved, must be zero. */
546 uint32_t uReserved0;
547 /** Device name, must match the ring-3 one. */
548 char szName[32];
549 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
550 uint32_t fFlags;
551 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
552 uint32_t fClass;
553 /** Maximum number of instances (per VM). */
554 uint32_t cMaxInstances;
555 /** The shared data structure version number. */
556 uint32_t uSharedVersion;
557 /** Size of the instance data. */
558 uint32_t cbInstanceShared;
559 /** Size of the ring-0 instance data. */
560 uint32_t cbInstanceCC;
561 /** Size of the raw-mode instance data. */
562 uint32_t cbInstanceRC;
563 /** Max number of PCI devices. */
564 uint16_t cMaxPciDevices;
565 /** Max number of MSI-X vectors in any of the PCI devices. */
566 uint16_t cMaxMsixVectors;
567 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
568 * remain unchanged from registration till VM destruction. */
569 const char *pszDescription;
570
571 /**
572 * Early construction callback (optional).
573 *
574 * This is called right after the device instance structure has been allocated
575 * and before the ring-3 constructor gets called.
576 *
577 * @returns VBox status code.
578 * @param pDevIns The device instance data.
579 * @note The destructure is always called, regardless of the return status.
580 */
581 DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
582
583 /**
584 * Regular construction callback (optional).
585 *
586 * This is called after (or during) the ring-3 constructor.
587 *
588 * @returns VBox status code.
589 * @param pDevIns The device instance data.
590 * @note The destructure is always called, regardless of the return status.
591 */
592 DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
593
594 /**
595 * Destructor (optional).
596 *
597 * This is called after the ring-3 destruction. This is not called if ring-3
598 * fails to trigger it (e.g. process is killed or crashes).
599 *
600 * @param pDevIns The device instance data.
601 */
602 DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
603
604 /**
605 * Final destructor (optional).
606 *
607 * This is called right before the memory is freed, which happens when the
608 * VM/GVM object is destroyed. This is always called.
609 *
610 * @param pDevIns The device instance data.
611 */
612 DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
613
614 /**
615 * Generic request handler (optional).
616 *
617 * @param pDevIns The device instance data.
618 * @param uReq Device specific request.
619 * @param uArg Request argument.
620 */
621 DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
622
623 /** @name Reserved for future extensions, must be zero.
624 * @{ */
625 DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
626 DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
627 DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
628 DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
629 DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
630 DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
631 DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
632 DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
633 /** @} */
634
635 /** Initialization safty marker. */
636 uint32_t u32VersionEnd;
637} PDMDEVREGR0;
638/** Pointer to a ring-0 PDM device registration structure. */
639typedef PDMDEVREGR0 *PPDMDEVREGR0;
640/** Pointer to a const ring-0 PDM device registration structure. */
641typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
642/** Current DEVREGR0 version number. */
643#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
644
645
646/**
647 * PDM Device Registration Structure, raw-mode
648 *
649 * At the moment, this structure is mostly here to match the other two contexts.
650 */
651typedef struct PDMDEVREGRC
652{
653 /** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
654 uint32_t u32Version;
655 /** Reserved, must be zero. */
656 uint32_t uReserved0;
657 /** Device name, must match the ring-3 one. */
658 char szName[32];
659 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
660 uint32_t fFlags;
661 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
662 uint32_t fClass;
663 /** Maximum number of instances (per VM). */
664 uint32_t cMaxInstances;
665 /** The shared data structure version number. */
666 uint32_t uSharedVersion;
667 /** Size of the instance data. */
668 uint32_t cbInstanceShared;
669 /** Size of the ring-0 instance data. */
670 uint32_t cbInstanceCC;
671 /** Size of the raw-mode instance data. */
672 uint32_t cbInstanceRC;
673 /** Max number of PCI devices. */
674 uint16_t cMaxPciDevices;
675 /** Max number of MSI-X vectors in any of the PCI devices. */
676 uint16_t cMaxMsixVectors;
677 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
678 * remain unchanged from registration till VM destruction. */
679 const char *pszDescription;
680
681 /**
682 * Constructor callback.
683 *
684 * This is called much later than both the ring-0 and ring-3 constructors, since
685 * raw-mode v2 require a working VMM to run actual code.
686 *
687 * @returns VBox status code.
688 * @param pDevIns The device instance data.
689 * @note The destructure is always called, regardless of the return status.
690 */
691 DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
692
693 /** @name Reserved for future extensions, must be zero.
694 * @{ */
695 DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
696 DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
697 DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
698 DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
699 DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
700 DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
701 DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
702 DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
703 /** @} */
704
705 /** Initialization safty marker. */
706 uint32_t u32VersionEnd;
707} PDMDEVREGRC;
708/** Pointer to a raw-mode PDM device registration structure. */
709typedef PDMDEVREGRC *PPDMDEVREGRC;
710/** Pointer to a const raw-mode PDM device registration structure. */
711typedef PDMDEVREGRC const *PCPDMDEVREGRC;
712/** Current DEVREGRC version number. */
713#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
714
715
716
717/** @def PDM_DEVREG_VERSION
718 * Current DEVREG version number. */
719/** @typedef PDMDEVREGR3
720 * A current context PDM device registration structure. */
721/** @typedef PPDMDEVREGR3
722 * Pointer to a current context PDM device registration structure. */
723/** @typedef PCPDMDEVREGR3
724 * Pointer to a const current context PDM device registration structure. */
725#if defined(IN_RING3) || defined(DOXYGEN_RUNNING)
726# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
727typedef PDMDEVREGR3 PDMDEVREG;
728typedef PPDMDEVREGR3 PPDMDEVREG;
729typedef PCPDMDEVREGR3 PCPDMDEVREG;
730#elif defined(IN_RING0)
731# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
732typedef PDMDEVREGR0 PDMDEVREG;
733typedef PPDMDEVREGR0 PPDMDEVREG;
734typedef PCPDMDEVREGR0 PCPDMDEVREG;
735#elif defined(IN_RC)
736# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
737typedef PDMDEVREGRC PDMDEVREG;
738typedef PPDMDEVREGRC PPDMDEVREG;
739typedef PCPDMDEVREGRC PCPDMDEVREG;
740#else
741# error "Not IN_RING3, IN_RING0 or IN_RC"
742#endif
743
744
745/**
746 * Device registrations for ring-0 modules.
747 *
748 * This structure is used directly and must therefore reside in persistent
749 * memory (i.e. the data section).
750 */
751typedef struct PDMDEVMODREGR0
752{
753 /** The structure version (PDM_DEVMODREGR0_VERSION). */
754 uint32_t u32Version;
755 /** Number of devices in the array papDevRegs points to. */
756 uint32_t cDevRegs;
757 /** Pointer to device registration structures. */
758 PCPDMDEVREGR0 *papDevRegs;
759 /** The ring-0 module handle - PDM internal, fingers off. */
760 void *hMod;
761 /** List entry - PDM internal, fingers off. */
762 RTLISTNODE ListEntry;
763} PDMDEVMODREGR0;
764/** Pointer to device registriations for a ring-0 module. */
765typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
766/** Current PDMDEVMODREGR0 version number. */
767#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
768
769
770/** @name IRQ Level for use with the *SetIrq APIs.
771 * @{
772 */
773/** Assert the IRQ (can assume value 1). */
774#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
775/** Deassert the IRQ (can assume value 0). */
776#define PDM_IRQ_LEVEL_LOW 0
777/** flip-flop - deassert and then assert the IRQ again immediately. */
778#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) | PDM_IRQ_LEVEL_HIGH)
779/** @} */
780
781/**
782 * Registration record for MSI/MSI-X emulation.
783 */
784typedef struct PDMMSIREG
785{
786 /** Number of MSI interrupt vectors, 0 if MSI not supported */
787 uint16_t cMsiVectors;
788 /** Offset of MSI capability */
789 uint8_t iMsiCapOffset;
790 /** Offset of next capability to MSI */
791 uint8_t iMsiNextOffset;
792 /** If we support 64-bit MSI addressing */
793 bool fMsi64bit;
794 /** If we do not support per-vector masking */
795 bool fMsiNoMasking;
796
797 /** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
798 uint16_t cMsixVectors;
799 /** Offset of MSI-X capability */
800 uint8_t iMsixCapOffset;
801 /** Offset of next capability to MSI-X */
802 uint8_t iMsixNextOffset;
803 /** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
804 uint8_t iMsixBar;
805} PDMMSIREG;
806typedef PDMMSIREG *PPDMMSIREG;
807
808/**
809 * PCI Bus registration structure.
810 * All the callbacks, except the PCIBIOS hack, are working on PCI devices.
811 */
812typedef struct PDMPCIBUSREGR3
813{
814 /** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
815 uint32_t u32Version;
816
817 /**
818 * Registers the device with the default PCI bus.
819 *
820 * @returns VBox status code.
821 * @param pDevIns Device instance of the PCI Bus.
822 * @param pPciDev The PCI device structure.
823 * @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
824 * @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
825 * device number (0-31).
826 * @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
827 * function number (0-7).
828 * @param pszName Device name (static but not unique).
829 *
830 * @remarks Caller enters the PDM critical section.
831 */
832 DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
833 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
834
835 /**
836 * Initialize MSI or MSI-X emulation support in a PCI device.
837 *
838 * This cannot handle all corner cases of the MSI/MSI-X spec, but for the
839 * vast majority of device emulation it covers everything necessary. It's
840 * fully automatic, taking care of all BAR and config space requirements,
841 * and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
842 * When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
843 * the vector number (otherwise it has the usual INTA-D meaning for PCI).
844 *
845 * A device not using this can still offer MSI/MSI-X. In this case it's
846 * completely up to the device (in the MSI-X case) to create/register the
847 * necessary MMIO BAR, handle all config space/BAR updating and take care
848 * of delivering the interrupts appropriately.
849 *
850 * @returns VBox status code.
851 * @param pDevIns Device instance of the PCI Bus.
852 * @param pPciDev The PCI device structure.
853 * @param pMsiReg MSI emulation registration structure
854 * @remarks Caller enters the PDM critical section.
855 */
856 DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
857
858 /**
859 * Registers a I/O region (memory mapped or I/O ports) for a PCI device.
860 *
861 * @returns VBox status code.
862 * @param pDevIns Device instance of the PCI Bus.
863 * @param pPciDev The PCI device structure.
864 * @param iRegion The region number.
865 * @param cbRegion Size of the region.
866 * @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
867 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
868 * PCI_ADDRESS_SPACE_BAR64 or'ed in.
869 * @param fFlags PDMPCIDEV_IORGN_F_XXX.
870 * @param hHandle An I/O port, MMIO or MMIO2 handle according to
871 * @a fFlags, UINT64_MAX if no handle is passed
872 * (old style).
873 * @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
874 * is given.
875 * @remarks Caller enters the PDM critical section.
876 */
877 DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
878 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
879 uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
880
881 /**
882 * Register PCI configuration space read/write intercept callbacks.
883 *
884 * @param pDevIns Device instance of the PCI Bus.
885 * @param pPciDev The PCI device structure.
886 * @param pfnRead Pointer to the user defined PCI config read function.
887 * @param pfnWrite Pointer to the user defined PCI config write function.
888 * to call default PCI config write function. Can be NULL.
889 * @remarks Caller enters the PDM critical section.
890 * @thread EMT
891 */
892 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
893 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
894
895 /**
896 * Perform a PCI configuration space write, bypassing interception.
897 *
898 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
899 *
900 * @returns Strict VBox status code (mainly DBGFSTOP).
901 * @param pDevIns Device instance of the PCI Bus.
902 * @param pPciDev The PCI device which config space is being read.
903 * @param uAddress The config space address.
904 * @param cb The size of the read: 1, 2 or 4 bytes.
905 * @param u32Value The value to write.
906 * @note The caller (PDM) does not enter the PDM critsect, but it is possible
907 * that the (root) bus will have done that already.
908 */
909 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
910 uint32_t uAddress, unsigned cb, uint32_t u32Value));
911
912 /**
913 * Perform a PCI configuration space read, bypassing interception.
914 *
915 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
916 *
917 * @returns Strict VBox status code (mainly DBGFSTOP).
918 * @param pDevIns Device instance of the PCI Bus.
919 * @param pPciDev The PCI device which config space is being read.
920 * @param uAddress The config space address.
921 * @param cb The size of the read: 1, 2 or 4 bytes.
922 * @param pu32Value Where to return the value.
923 * @note The caller (PDM) does not enter the PDM critsect, but it is possible
924 * that the (root) bus will have done that already.
925 */
926 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
927 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
928
929 /**
930 * Set the IRQ for a PCI device.
931 *
932 * @param pDevIns Device instance of the PCI Bus.
933 * @param pPciDev The PCI device structure.
934 * @param iIrq IRQ number to set.
935 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
936 * @param uTagSrc The IRQ tag and source (for tracing).
937 * @remarks Caller enters the PDM critical section.
938 */
939 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
940
941 /** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
942 uint32_t u32EndVersion;
943} PDMPCIBUSREGR3;
944/** Pointer to a PCI bus registration structure. */
945typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
946/** Current PDMPCIBUSREGR3 version number. */
947#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
948
949/**
950 * PCI Bus registration structure for ring-0.
951 */
952typedef struct PDMPCIBUSREGR0
953{
954 /** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
955 uint32_t u32Version;
956 /** The PCI bus number (from ring-3 registration). */
957 uint32_t iBus;
958 /**
959 * Set the IRQ for a PCI device.
960 *
961 * @param pDevIns Device instance of the PCI Bus.
962 * @param pPciDev The PCI device structure.
963 * @param iIrq IRQ number to set.
964 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
965 * @param uTagSrc The IRQ tag and source (for tracing).
966 * @remarks Caller enters the PDM critical section.
967 */
968 DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
969 /** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
970 uint32_t u32EndVersion;
971} PDMPCIBUSREGR0;
972/** Pointer to a PCI bus ring-0 registration structure. */
973typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
974/** Current PDMPCIBUSREGR0 version number. */
975#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
976
977/**
978 * PCI Bus registration structure for raw-mode.
979 */
980typedef struct PDMPCIBUSREGRC
981{
982 /** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
983 uint32_t u32Version;
984 /** The PCI bus number (from ring-3 registration). */
985 uint32_t iBus;
986 /**
987 * Set the IRQ for a PCI device.
988 *
989 * @param pDevIns Device instance of the PCI Bus.
990 * @param pPciDev The PCI device structure.
991 * @param iIrq IRQ number to set.
992 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
993 * @param uTagSrc The IRQ tag and source (for tracing).
994 * @remarks Caller enters the PDM critical section.
995 */
996 DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
997 /** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
998 uint32_t u32EndVersion;
999} PDMPCIBUSREGRC;
1000/** Pointer to a PCI bus raw-mode registration structure. */
1001typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1002/** Current PDMPCIBUSREGRC version number. */
1003#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1004
1005/** PCI bus registration structure for the current context. */
1006typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1007/** Pointer to a PCI bus registration structure for the current context. */
1008typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1009/** PCI bus registration structure version for the current context. */
1010#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1011
1012
1013/**
1014 * PCI Bus RC helpers.
1015 */
1016typedef struct PDMPCIHLPRC
1017{
1018 /** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1019 uint32_t u32Version;
1020
1021 /**
1022 * Set an ISA IRQ.
1023 *
1024 * @param pDevIns PCI device instance.
1025 * @param iIrq IRQ number to set.
1026 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1027 * @param uTagSrc The IRQ tag and source (for tracing).
1028 * @thread EMT only.
1029 */
1030 DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1031
1032 /**
1033 * Set an I/O-APIC IRQ.
1034 *
1035 * @param pDevIns PCI device instance.
1036 * @param uBusDevFn The bus:device:function of the device initiating the
1037 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1038 * interrupt.
1039 * @param iIrq IRQ number to set.
1040 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1041 * @param uTagSrc The IRQ tag and source (for tracing).
1042 * @thread EMT only.
1043 */
1044 DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1045
1046 /**
1047 * Send an MSI.
1048 *
1049 * @param pDevIns PCI device instance.
1050 * @param uBusDevFn The bus:device:function of the device initiating the
1051 * MSI. Cannot be NIL_PCIBDF.
1052 * @param pMsi The MSI to send.
1053 * @param uTagSrc The IRQ tag and source (for tracing).
1054 * @thread EMT only.
1055 */
1056 DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1057
1058
1059 /**
1060 * Acquires the PDM lock.
1061 *
1062 * @returns VINF_SUCCESS on success.
1063 * @returns rc if we failed to acquire the lock.
1064 * @param pDevIns The PCI device instance.
1065 * @param rc What to return if we fail to acquire the lock.
1066 */
1067 DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1068
1069 /**
1070 * Releases the PDM lock.
1071 *
1072 * @param pDevIns The PCI device instance.
1073 */
1074 DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1075
1076 /**
1077 * Gets a bus by it's PDM ordinal (typically the parent bus).
1078 *
1079 * @returns Pointer to the device instance of the bus.
1080 * @param pDevIns The PCI bus device instance.
1081 * @param idxPdmBus The PDM ordinal value of the bus to get.
1082 */
1083 DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1084
1085 /** Just a safety precaution. */
1086 uint32_t u32TheEnd;
1087} PDMPCIHLPRC;
1088/** Pointer to PCI helpers. */
1089typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1090/** Pointer to const PCI helpers. */
1091typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1092
1093/** Current PDMPCIHLPRC version number. */
1094#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1095
1096
1097/**
1098 * PCI Bus R0 helpers.
1099 */
1100typedef struct PDMPCIHLPR0
1101{
1102 /** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1103 uint32_t u32Version;
1104
1105 /**
1106 * Set an ISA IRQ.
1107 *
1108 * @param pDevIns PCI device instance.
1109 * @param iIrq IRQ number to set.
1110 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1111 * @param uTagSrc The IRQ tag and source (for tracing).
1112 * @thread EMT only.
1113 */
1114 DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1115
1116 /**
1117 * Set an I/O-APIC IRQ.
1118 *
1119 * @param pDevIns PCI device instance.
1120 * @param uBusDevFn The bus:device:function of the device initiating the
1121 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1122 * interrupt.
1123 * @param iIrq IRQ number to set.
1124 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1125 * @param uTagSrc The IRQ tag and source (for tracing).
1126 * @thread EMT only.
1127 */
1128 DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1129
1130 /**
1131 * Send an MSI.
1132 *
1133 * @param pDevIns PCI device instance.
1134 * @param uBusDevFn The bus:device:function of the device initiating the
1135 * MSI. Cannot be NIL_PCIBDF.
1136 * @param pMsi The MSI to send.
1137 * @param uTagSrc The IRQ tag and source (for tracing).
1138 * @thread EMT only.
1139 */
1140 DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1141
1142 /**
1143 * Acquires the PDM lock.
1144 *
1145 * @returns VINF_SUCCESS on success.
1146 * @returns rc if we failed to acquire the lock.
1147 * @param pDevIns The PCI device instance.
1148 * @param rc What to return if we fail to acquire the lock.
1149 */
1150 DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1151
1152 /**
1153 * Releases the PDM lock.
1154 *
1155 * @param pDevIns The PCI device instance.
1156 */
1157 DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1158
1159 /**
1160 * Gets a bus by it's PDM ordinal (typically the parent bus).
1161 *
1162 * @returns Pointer to the device instance of the bus.
1163 * @param pDevIns The PCI bus device instance.
1164 * @param idxPdmBus The PDM ordinal value of the bus to get.
1165 */
1166 DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1167
1168 /** Just a safety precaution. */
1169 uint32_t u32TheEnd;
1170} PDMPCIHLPR0;
1171/** Pointer to PCI helpers. */
1172typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1173/** Pointer to const PCI helpers. */
1174typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1175
1176/** Current PDMPCIHLPR0 version number. */
1177#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1178
1179/**
1180 * PCI device helpers.
1181 */
1182typedef struct PDMPCIHLPR3
1183{
1184 /** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1185 uint32_t u32Version;
1186
1187 /**
1188 * Set an ISA IRQ.
1189 *
1190 * @param pDevIns The PCI device instance.
1191 * @param iIrq IRQ number to set.
1192 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1193 * @param uTagSrc The IRQ tag and source (for tracing).
1194 */
1195 DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1196
1197 /**
1198 * Set an I/O-APIC IRQ.
1199 *
1200 * @param pDevIns The PCI device instance.
1201 * @param uBusDevFn The bus:device:function of the device initiating the
1202 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1203 * interrupt.
1204 * @param iIrq IRQ number to set.
1205 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1206 * @param uTagSrc The IRQ tag and source (for tracing).
1207 */
1208 DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1209
1210 /**
1211 * Send an MSI.
1212 *
1213 * @param pDevIns PCI device instance.
1214 * @param uBusDevFn The bus:device:function of the device initiating the
1215 * MSI. Cannot be NIL_PCIBDF.
1216 * @param pMsi The MSI to send.
1217 * @param uTagSrc The IRQ tag and source (for tracing).
1218 */
1219 DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1220
1221 /**
1222 * Acquires the PDM lock.
1223 *
1224 * @returns VINF_SUCCESS on success.
1225 * @returns Fatal error on failure.
1226 * @param pDevIns The PCI device instance.
1227 * @param rc Dummy for making the interface identical to the RC and R0 versions.
1228 */
1229 DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1230
1231 /**
1232 * Releases the PDM lock.
1233 *
1234 * @param pDevIns The PCI device instance.
1235 */
1236 DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1237
1238 /**
1239 * Gets a bus by it's PDM ordinal (typically the parent bus).
1240 *
1241 * @returns Pointer to the device instance of the bus.
1242 * @param pDevIns The PCI bus device instance.
1243 * @param idxPdmBus The PDM ordinal value of the bus to get.
1244 */
1245 DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1246
1247 /** Just a safety precaution. */
1248 uint32_t u32TheEnd;
1249} PDMPCIHLPR3;
1250/** Pointer to PCI helpers. */
1251typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1252/** Pointer to const PCI helpers. */
1253typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1254
1255/** Current PDMPCIHLPR3 version number. */
1256#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1257
1258
1259/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1260 * These flags are used for memory access transactions via the IOMMU interface.
1261 * @{ */
1262/** Memory read. */
1263#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1264/** Memory write. */
1265#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1266/** Valid flag mask. */
1267#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ | PDMIOMMU_MEM_F_WRITE)
1268/** @} */
1269
1270/**
1271 * IOMMU registration structure for ring-0.
1272 */
1273typedef struct PDMIOMMUREGR0
1274{
1275 /** Structure version number. PDM_IOMMUREG_VERSION defines the current
1276 * version. */
1277 uint32_t u32Version;
1278 /** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1279 uint32_t idxIommu;
1280
1281 /**
1282 * Translates the physical address for a memory transaction through the IOMMU.
1283 *
1284 * @returns VBox status code.
1285 * @param pDevIns The IOMMU device instance.
1286 * @param uDevId The device identifier (bus, device, function).
1287 * @param uIova The I/O virtual address being accessed.
1288 * @param cbAccess The number of bytes being accessed.
1289 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1290 * @param pGCPhysSpa Where to store the translated system physical address.
1291 * @param pcbContiguous Where to store the number of contiguous bytes translated
1292 * and permission-checked.
1293 *
1294 * @thread Any.
1295 */
1296 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
1297 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1298
1299 /**
1300 * Translates in bulk physical page addresses for memory transactions through the
1301 * IOMMU.
1302 *
1303 * @returns VBox status code.
1304 * @param pDevIns The IOMMU device instance.
1305 * @param uDevId The device identifier (bus, device, function).
1306 * @param cIovas The number of I/O virtual addresses being accessed.
1307 * @param pauIovas The I/O virtual addresses being accessed.
1308 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1309 * @param paGCPhysSpa Where to store the translated system physical page
1310 * addresses.
1311 *
1312 * @thread Any.
1313 */
1314 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
1315 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1316
1317 /**
1318 * Performs an interrupt remap request through the IOMMU.
1319 *
1320 * @returns VBox status code.
1321 * @param pDevIns The IOMMU device instance.
1322 * @param uDeviceId The device identifier (bus, device, function).
1323 * @param pMsiIn The source MSI.
1324 * @param pMsiOut Where to store the remapped MSI.
1325 *
1326 * @thread Any.
1327 */
1328 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDeviceId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1329
1330 /** Just a safety precaution. */
1331 uint32_t u32TheEnd;
1332} PDMIOMMUREGR0;
1333/** Pointer to a IOMMU registration structure. */
1334typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1335
1336/** Current PDMIOMMUREG version number. */
1337#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1338
1339
1340/**
1341 * IOMMU registration structure for raw-mode.
1342 */
1343typedef struct PDMIOMMUREGRC
1344{
1345 /** Structure version number. PDM_IOMMUREG_VERSION defines the current
1346 * version. */
1347 uint32_t u32Version;
1348 /** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1349 uint32_t idxIommu;
1350
1351 /**
1352 * Translates the physical address for a memory transaction through the IOMMU.
1353 *
1354 * @returns VBox status code.
1355 * @param pDevIns The IOMMU device instance.
1356 * @param uDevId The device identifier (bus, device, function).
1357 * @param uIova The I/O virtual address being accessed.
1358 * @param cbAccess The number of bytes being accessed.
1359 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1360 * @param pGCPhysSpa Where to store the translated system physical address.
1361 * @param pcbContiguous Where to store the number of contiguous bytes translated
1362 * and permission-checked.
1363 *
1364 * @thread Any.
1365 */
1366 DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
1367 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1368
1369 /**
1370 * Translates in bulk physical page addresses for memory transactions through the
1371 * IOMMU.
1372 *
1373 * @returns VBox status code.
1374 * @param pDevIns The IOMMU device instance.
1375 * @param uDevId The device identifier (bus, device, function).
1376 * @param cIovas The number of I/O virtual addresses being accessed.
1377 * @param pauIovas The I/O virtual addresses being accessed.
1378 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1379 * @param paGCPhysSpa Where to store the translated system physical page
1380 * addresses.
1381 *
1382 * @thread Any.
1383 */
1384 DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
1385 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1386
1387 /**
1388 * Performs an interrupt remap request through the IOMMU.
1389 *
1390 * @returns VBox status code.
1391 * @param pDevIns The IOMMU device instance.
1392 * @param uDeviceId The device identifier (bus, device, function).
1393 * @param pMsiIn The source MSI.
1394 * @param pMsiOut Where to store the remapped MSI.
1395 *
1396 * @thread Any.
1397 */
1398 DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDeviceId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1399
1400 /** Just a safety precaution. */
1401 uint32_t u32TheEnd;
1402} PDMIOMMUREGRC;
1403/** Pointer to a IOMMU registration structure. */
1404typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1405
1406/** Current PDMIOMMUREG version number. */
1407#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1408
1409
1410/**
1411 * IOMMU registration structure for ring-3.
1412 */
1413typedef struct PDMIOMMUREGR3
1414{
1415 /** Structure version number. PDM_IOMMUREG_VERSION defines the current
1416 * version. */
1417 uint32_t u32Version;
1418 /** Padding. */
1419 uint32_t uPadding0;
1420
1421 /**
1422 * Translates the physical address for a memory transaction through the IOMMU.
1423 *
1424 * @returns VBox status code.
1425 * @param pDevIns The IOMMU device instance.
1426 * @param uDevId The device identifier (bus, device, function).
1427 * @param uIova The I/O virtual address being accessed.
1428 * @param cbAccess The number of bytes being accessed.
1429 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1430 * @param pGCPhysSpa Where to store the translated system physical address.
1431 * @param pcbContiguous Where to store the number of contiguous bytes translated
1432 * and permission-checked.
1433 *
1434 * @thread Any.
1435 */
1436 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
1437 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1438
1439 /**
1440 * Translates in bulk physical page addresses for memory transactions through the
1441 * IOMMU.
1442 *
1443 * @returns VBox status code.
1444 * @param pDevIns The IOMMU device instance.
1445 * @param uDevId The device identifier (bus, device, function).
1446 * @param cIovas The number of I/O virtual addresses being accessed.
1447 * @param pauIovas The I/O virtual addresses being accessed.
1448 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1449 * @param paGCPhysSpa Where to store the translated system physical page
1450 * addresses.
1451 *
1452 * @thread Any.
1453 */
1454 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
1455 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1456
1457 /**
1458 * Performs an interrupt remap request through the IOMMU.
1459 *
1460 * @returns VBox status code.
1461 * @param pDevIns The IOMMU device instance.
1462 * @param uDeviceId The device identifier (bus, device, function).
1463 * @param pMsiIn The source MSI.
1464 * @param pMsiOut Where to store the remapped MSI.
1465 *
1466 * @thread Any.
1467 */
1468 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDeviceId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1469
1470 /** Just a safety precaution. */
1471 uint32_t u32TheEnd;
1472} PDMIOMMUREGR3;
1473/** Pointer to a IOMMU registration structure. */
1474typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1475
1476/** Current PDMIOMMUREG version number. */
1477#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1478
1479/** IOMMU registration structure for the current context. */
1480typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1481/** Pointer to an IOMMU registration structure for the current context. */
1482typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1483/** IOMMU registration structure version for the current context. */
1484#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1485
1486
1487/**
1488 * IOMMU helpers for ring-0.
1489 */
1490typedef struct PDMIOMMUHLPR0
1491{
1492 /** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1493 uint32_t u32Version;
1494 /** Just a safety precaution. */
1495 uint32_t u32TheEnd;
1496} PDMIOMMUHLPR0;
1497/** Pointer to IOMMU helpers for ring-0. */
1498typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1499/** Pointer to const IOMMU helpers for ring-0. */
1500typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1501
1502/** Current PDMIOMMUHLPR0 version number. */
1503#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 1, 0)
1504
1505
1506/**
1507 * IOMMU helpers for raw-mode.
1508 */
1509typedef struct PDMIOMMUHLPRC
1510{
1511 /** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1512 uint32_t u32Version;
1513 /** Just a safety precaution. */
1514 uint32_t u32TheEnd;
1515} PDMIOMMUHLPRC;
1516/** Pointer to IOMMU helpers for raw-mode. */
1517typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1518/** Pointer to const IOMMU helpers for raw-mode. */
1519typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1520
1521/** Current PDMIOMMUHLPRC version number. */
1522#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 1, 0)
1523
1524
1525/**
1526 * IOMMU helpers for ring-3.
1527 */
1528typedef struct PDMIOMMUHLPR3
1529{
1530 /** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1531 uint32_t u32Version;
1532 /** Just a safety precaution. */
1533 uint32_t u32TheEnd;
1534} PDMIOMMUHLPR3;
1535/** Pointer to IOMMU helpers for raw-mode. */
1536typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1537/** Pointer to const IOMMU helpers for raw-mode. */
1538typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1539
1540/** Current PDMIOMMUHLPR3 version number. */
1541#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 1, 0)
1542
1543
1544/**
1545 * Programmable Interrupt Controller registration structure (all contexts).
1546 */
1547typedef struct PDMPICREG
1548{
1549 /** Structure version number. PDM_PICREG_VERSION defines the current version. */
1550 uint32_t u32Version;
1551
1552 /**
1553 * Set the an IRQ.
1554 *
1555 * @param pDevIns Device instance of the PIC.
1556 * @param iIrq IRQ number to set.
1557 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1558 * @param uTagSrc The IRQ tag and source (for tracing).
1559 * @remarks Caller enters the PDM critical section.
1560 */
1561 DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1562
1563 /**
1564 * Get a pending interrupt.
1565 *
1566 * @returns Pending interrupt number.
1567 * @param pDevIns Device instance of the PIC.
1568 * @param puTagSrc Where to return the IRQ tag and source.
1569 * @remarks Caller enters the PDM critical section.
1570 */
1571 DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1572
1573 /** Just a safety precaution. */
1574 uint32_t u32TheEnd;
1575} PDMPICREG;
1576/** Pointer to a PIC registration structure. */
1577typedef PDMPICREG *PPDMPICREG;
1578
1579/** Current PDMPICREG version number. */
1580#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1581
1582/**
1583 * PIC helpers, same in all contexts.
1584 */
1585typedef struct PDMPICHLP
1586{
1587 /** Structure version. PDM_PICHLP_VERSION defines the current version. */
1588 uint32_t u32Version;
1589
1590 /**
1591 * Set the interrupt force action flag.
1592 *
1593 * @param pDevIns Device instance of the PIC.
1594 */
1595 DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1596
1597 /**
1598 * Clear the interrupt force action flag.
1599 *
1600 * @param pDevIns Device instance of the PIC.
1601 */
1602 DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1603
1604 /**
1605 * Acquires the PDM lock.
1606 *
1607 * @returns VINF_SUCCESS on success.
1608 * @returns rc if we failed to acquire the lock.
1609 * @param pDevIns The PIC device instance.
1610 * @param rc What to return if we fail to acquire the lock.
1611 */
1612 DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1613
1614 /**
1615 * Releases the PDM lock.
1616 *
1617 * @param pDevIns The PIC device instance.
1618 */
1619 DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1620
1621 /** Just a safety precaution. */
1622 uint32_t u32TheEnd;
1623} PDMPICHLP;
1624/** Pointer to PIC helpers. */
1625typedef PDMPICHLP *PPDMPICHLP;
1626/** Pointer to const PIC helpers. */
1627typedef const PDMPICHLP *PCPDMPICHLP;
1628
1629/** Current PDMPICHLP version number. */
1630#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1631
1632
1633/**
1634 * Firmware registration structure.
1635 */
1636typedef struct PDMFWREG
1637{
1638 /** Struct version+magic number (PDM_FWREG_VERSION). */
1639 uint32_t u32Version;
1640
1641 /**
1642 * Checks whether this is a hard or soft reset.
1643 *
1644 * The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1645 * is 5, 9 or 0xA.
1646 *
1647 * @returns true if hard reset, false if soft.
1648 * @param pDevIns Device instance of the firmware.
1649 * @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1650 */
1651 DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1652
1653 /** Just a safety precaution. */
1654 uint32_t u32TheEnd;
1655} PDMFWREG;
1656/** Pointer to a FW registration structure. */
1657typedef PDMFWREG *PPDMFWREG;
1658/** Pointer to a const FW registration structure. */
1659typedef PDMFWREG const *PCPDMFWREG;
1660
1661/** Current PDMFWREG version number. */
1662#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1663
1664/**
1665 * Firmware R3 helpers.
1666 */
1667typedef struct PDMFWHLPR3
1668{
1669 /** Structure version. PDM_FWHLP_VERSION defines the current version. */
1670 uint32_t u32Version;
1671
1672 /** Just a safety precaution. */
1673 uint32_t u32TheEnd;
1674} PDMFWHLPR3;
1675
1676/** Pointer to FW R3 helpers. */
1677typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1678/** Pointer to const FW R3 helpers. */
1679typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1680
1681/** Current PDMFWHLPR3 version number. */
1682#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1683
1684
1685/**
1686 * APIC mode argument for apicR3SetCpuIdFeatureLevel.
1687 *
1688 * Also used in saved-states, CFGM don't change existing values.
1689 */
1690typedef enum PDMAPICMODE
1691{
1692 /** Invalid 0 entry. */
1693 PDMAPICMODE_INVALID = 0,
1694 /** No APIC. */
1695 PDMAPICMODE_NONE,
1696 /** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1697 PDMAPICMODE_APIC,
1698 /** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1699 PDMAPICMODE_X2APIC,
1700 /** The usual 32-bit paranoia. */
1701 PDMAPICMODE_32BIT_HACK = 0x7fffffff
1702} PDMAPICMODE;
1703
1704/**
1705 * APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1706 */
1707typedef enum PDMAPICIRQ
1708{
1709 /** Invalid 0 entry. */
1710 PDMAPICIRQ_INVALID = 0,
1711 /** Normal hardware interrupt. */
1712 PDMAPICIRQ_HARDWARE,
1713 /** NMI. */
1714 PDMAPICIRQ_NMI,
1715 /** SMI. */
1716 PDMAPICIRQ_SMI,
1717 /** ExtINT (HW interrupt via PIC). */
1718 PDMAPICIRQ_EXTINT,
1719 /** Interrupt arrived, needs to be updated to the IRR. */
1720 PDMAPICIRQ_UPDATE_PENDING,
1721 /** The usual 32-bit paranoia. */
1722 PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1723} PDMAPICIRQ;
1724
1725
1726/**
1727 * I/O APIC registration structure (all contexts).
1728 */
1729typedef struct PDMIOAPICREG
1730{
1731 /** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1732 uint32_t u32Version;
1733
1734 /**
1735 * Set an IRQ.
1736 *
1737 * @param pDevIns Device instance of the I/O APIC.
1738 * @param uBusDevFn The bus:device:function of the device initiating the
1739 * IRQ. Can be NIL_PCIBDF.
1740 * @param iIrq IRQ number to set.
1741 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1742 * @param uTagSrc The IRQ tag and source (for tracing).
1743 *
1744 * @remarks Caller enters the PDM critical section
1745 * Actually, as per 2018-07-21 this isn't true (bird).
1746 */
1747 DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1748
1749 /**
1750 * Send a MSI.
1751 *
1752 * @param pDevIns Device instance of the I/O APIC.
1753 * @param uBusDevFn The bus:device:function of the device initiating the
1754 * MSI. Cannot be NIL_PCIBDF.
1755 * @param pMsi The MSI to send.
1756 * @param uTagSrc The IRQ tag and source (for tracing).
1757 *
1758 * @remarks Caller enters the PDM critical section
1759 * Actually, as per 2018-07-21 this isn't true (bird).
1760 */
1761 DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1762
1763 /**
1764 * Set the EOI for an interrupt vector.
1765 *
1766 * @returns Strict VBox status code - only the following informational status codes:
1767 * @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
1768 * @retval VINF_SUCCESS
1769 *
1770 * @param pDevIns Device instance of the I/O APIC.
1771 * @param u8Vector The vector.
1772 *
1773 * @remarks Caller enters the PDM critical section
1774 * Actually, as per 2018-07-21 this isn't true (bird).
1775 */
1776 DECLCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1777
1778 /** Just a safety precaution. */
1779 uint32_t u32TheEnd;
1780} PDMIOAPICREG;
1781/** Pointer to an APIC registration structure. */
1782typedef PDMIOAPICREG *PPDMIOAPICREG;
1783
1784/** Current PDMAPICREG version number. */
1785#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 7, 0)
1786
1787
1788/**
1789 * IOAPIC helpers, same in all contexts.
1790 */
1791typedef struct PDMIOAPICHLP
1792{
1793 /** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1794 uint32_t u32Version;
1795
1796 /**
1797 * Private interface between the IOAPIC and APIC.
1798 *
1799 * @returns status code.
1800 * @param pDevIns Device instance of the IOAPIC.
1801 * @param u8Dest See APIC implementation.
1802 * @param u8DestMode See APIC implementation.
1803 * @param u8DeliveryMode See APIC implementation.
1804 * @param uVector See APIC implementation.
1805 * @param u8Polarity See APIC implementation.
1806 * @param u8TriggerMode See APIC implementation.
1807 * @param uTagSrc The IRQ tag and source (for tracing).
1808 *
1809 * @sa APICBusDeliver()
1810 */
1811 DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1812 uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1813
1814 /**
1815 * Acquires the PDM lock.
1816 *
1817 * @returns VINF_SUCCESS on success.
1818 * @returns rc if we failed to acquire the lock.
1819 * @param pDevIns The IOAPIC device instance.
1820 * @param rc What to return if we fail to acquire the lock.
1821 */
1822 DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1823
1824 /**
1825 * Releases the PDM lock.
1826 *
1827 * @param pDevIns The IOAPIC device instance.
1828 */
1829 DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1830
1831 /**
1832 * Private interface between the IOAPIC and IOMMU.
1833 *
1834 * @returns status code.
1835 * @param pDevIns Device instance of the IOAPIC.
1836 * @param uDeviceId The device identifier (bus, device, function).
1837 * @param pMsiIn The source MSI.
1838 * @param pMsiOut Where to store the remapped MSI.
1839 *
1840 * @sa iommuAmdDeviceMsiRemap().
1841 */
1842 DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDeviceId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1843
1844 /** Just a safety precaution. */
1845 uint32_t u32TheEnd;
1846} PDMIOAPICHLP;
1847/** Pointer to IOAPIC helpers. */
1848typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1849/** Pointer to const IOAPIC helpers. */
1850typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1851
1852/** Current PDMIOAPICHLP version number. */
1853#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 2, 1)
1854
1855
1856/**
1857 * HPET registration structure.
1858 */
1859typedef struct PDMHPETREG
1860{
1861 /** Struct version+magic number (PDM_HPETREG_VERSION). */
1862 uint32_t u32Version;
1863} PDMHPETREG;
1864/** Pointer to an HPET registration structure. */
1865typedef PDMHPETREG *PPDMHPETREG;
1866
1867/** Current PDMHPETREG version number. */
1868#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1869
1870/**
1871 * HPET RC helpers.
1872 *
1873 * @remarks Keep this around in case HPET will need PDM interaction in again RC
1874 * at some later point.
1875 */
1876typedef struct PDMHPETHLPRC
1877{
1878 /** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
1879 uint32_t u32Version;
1880
1881 /** Just a safety precaution. */
1882 uint32_t u32TheEnd;
1883} PDMHPETHLPRC;
1884
1885/** Pointer to HPET RC helpers. */
1886typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
1887/** Pointer to const HPET RC helpers. */
1888typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
1889
1890/** Current PDMHPETHLPRC version number. */
1891#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
1892
1893
1894/**
1895 * HPET R0 helpers.
1896 *
1897 * @remarks Keep this around in case HPET will need PDM interaction in again R0
1898 * at some later point.
1899 */
1900typedef struct PDMHPETHLPR0
1901{
1902 /** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
1903 uint32_t u32Version;
1904
1905 /** Just a safety precaution. */
1906 uint32_t u32TheEnd;
1907} PDMHPETHLPR0;
1908
1909/** Pointer to HPET R0 helpers. */
1910typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
1911/** Pointer to const HPET R0 helpers. */
1912typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
1913
1914/** Current PDMHPETHLPR0 version number. */
1915#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
1916
1917/**
1918 * HPET R3 helpers.
1919 */
1920typedef struct PDMHPETHLPR3
1921{
1922 /** Structure version. PDM_HPETHLP_VERSION defines the current version. */
1923 uint32_t u32Version;
1924
1925 /**
1926 * Set legacy mode on PIT and RTC.
1927 *
1928 * @returns VINF_SUCCESS on success.
1929 * @returns rc if we failed to set legacy mode.
1930 * @param pDevIns Device instance of the HPET.
1931 * @param fActivated Whether legacy mode is activated or deactivated.
1932 */
1933 DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
1934
1935
1936 /**
1937 * Set IRQ, bypassing ISA bus override rules.
1938 *
1939 * @returns VINF_SUCCESS on success.
1940 * @returns rc if we failed to set legacy mode.
1941 * @param pDevIns Device instance of the HPET.
1942 * @param iIrq IRQ number to set.
1943 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1944 */
1945 DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
1946
1947 /** Just a safety precaution. */
1948 uint32_t u32TheEnd;
1949} PDMHPETHLPR3;
1950
1951/** Pointer to HPET R3 helpers. */
1952typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
1953/** Pointer to const HPET R3 helpers. */
1954typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
1955
1956/** Current PDMHPETHLPR3 version number. */
1957#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
1958
1959
1960/**
1961 * Raw PCI device registration structure.
1962 */
1963typedef struct PDMPCIRAWREG
1964{
1965 /** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
1966 uint32_t u32Version;
1967 /** Just a safety precaution. */
1968 uint32_t u32TheEnd;
1969} PDMPCIRAWREG;
1970/** Pointer to a raw PCI registration structure. */
1971typedef PDMPCIRAWREG *PPDMPCIRAWREG;
1972
1973/** Current PDMPCIRAWREG version number. */
1974#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
1975
1976/**
1977 * Raw PCI device raw-mode context helpers.
1978 */
1979typedef struct PDMPCIRAWHLPRC
1980{
1981 /** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
1982 uint32_t u32Version;
1983 /** Just a safety precaution. */
1984 uint32_t u32TheEnd;
1985} PDMPCIRAWHLPRC;
1986/** Pointer to a raw PCI deviec raw-mode context helper structure. */
1987typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
1988/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
1989typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
1990
1991/** Current PDMPCIRAWHLPRC version number. */
1992#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
1993
1994/**
1995 * Raw PCI device ring-0 context helpers.
1996 */
1997typedef struct PDMPCIRAWHLPR0
1998{
1999 /** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2000 uint32_t u32Version;
2001 /** Just a safety precaution. */
2002 uint32_t u32TheEnd;
2003} PDMPCIRAWHLPR0;
2004/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2005typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2006/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2007typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2008
2009/** Current PDMPCIRAWHLPR0 version number. */
2010#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2011
2012
2013/**
2014 * Raw PCI device ring-3 context helpers.
2015 */
2016typedef struct PDMPCIRAWHLPR3
2017{
2018 /** Undefined structure version and magic number. */
2019 uint32_t u32Version;
2020
2021 /**
2022 * Gets the address of the RC raw PCI device helpers.
2023 *
2024 * This should be called at both construction and relocation time to obtain
2025 * the correct address of the RC helpers.
2026 *
2027 * @returns RC pointer to the raw PCI device helpers.
2028 * @param pDevIns Device instance of the raw PCI device.
2029 */
2030 DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2031
2032 /**
2033 * Gets the address of the R0 raw PCI device helpers.
2034 *
2035 * This should be called at both construction and relocation time to obtain
2036 * the correct address of the R0 helpers.
2037 *
2038 * @returns R0 pointer to the raw PCI device helpers.
2039 * @param pDevIns Device instance of the raw PCI device.
2040 */
2041 DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2042
2043 /** Just a safety precaution. */
2044 uint32_t u32TheEnd;
2045} PDMPCIRAWHLPR3;
2046/** Pointer to raw PCI R3 helpers. */
2047typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2048/** Pointer to const raw PCI R3 helpers. */
2049typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2050
2051/** Current PDMPCIRAWHLPR3 version number. */
2052#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2053
2054
2055#ifdef IN_RING3
2056
2057/**
2058 * DMA Transfer Handler.
2059 *
2060 * @returns Number of bytes transferred.
2061 * @param pDevIns The device instance that registered the handler.
2062 * @param pvUser User pointer.
2063 * @param uChannel Channel number.
2064 * @param off DMA position.
2065 * @param cb Block size.
2066 * @remarks The device lock is take before the callback (in fact, the locks of
2067 * DMA devices and the DMA controller itself are taken).
2068 */
2069typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2070 uint32_t off, uint32_t cb));
2071/** Pointer to a FNDMATRANSFERHANDLER(). */
2072typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2073
2074/**
2075 * DMA Controller registration structure.
2076 */
2077typedef struct PDMDMAREG
2078{
2079 /** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2080 uint32_t u32Version;
2081
2082 /**
2083 * Execute pending transfers.
2084 *
2085 * @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2086 * @param pDevIns Device instance of the DMAC.
2087 * @remarks No locks held, called on EMT(0) as a form of serialization.
2088 */
2089 DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2090
2091 /**
2092 * Register transfer function for DMA channel.
2093 *
2094 * @param pDevIns Device instance of the DMAC.
2095 * @param uChannel Channel number.
2096 * @param pDevInsHandler The device instance of the device making the
2097 * regstration (will be passed to the callback).
2098 * @param pfnTransferHandler Device specific transfer function.
2099 * @param pvUser User pointer to be passed to the callback.
2100 * @remarks No locks held, called on an EMT.
2101 */
2102 DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2103 PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2104
2105 /**
2106 * Read memory
2107 *
2108 * @returns Number of bytes read.
2109 * @param pDevIns Device instance of the DMAC.
2110 * @param uChannel Channel number.
2111 * @param pvBuffer Pointer to target buffer.
2112 * @param off DMA position.
2113 * @param cbBlock Block size.
2114 * @remarks No locks held, called on an EMT.
2115 */
2116 DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2117
2118 /**
2119 * Write memory
2120 *
2121 * @returns Number of bytes written.
2122 * @param pDevIns Device instance of the DMAC.
2123 * @param uChannel Channel number.
2124 * @param pvBuffer Memory to write.
2125 * @param off DMA position.
2126 * @param cbBlock Block size.
2127 * @remarks No locks held, called on an EMT.
2128 */
2129 DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2130
2131 /**
2132 * Set the DREQ line.
2133 *
2134 * @param pDevIns Device instance of the DMAC.
2135 * @param uChannel Channel number.
2136 * @param uLevel Level of the line.
2137 * @remarks No locks held, called on an EMT.
2138 */
2139 DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2140
2141 /**
2142 * Get channel mode
2143 *
2144 * @returns Channel mode.
2145 * @param pDevIns Device instance of the DMAC.
2146 * @param uChannel Channel number.
2147 * @remarks No locks held, called on an EMT.
2148 */
2149 DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2150
2151} PDMDMACREG;
2152/** Pointer to a DMAC registration structure. */
2153typedef PDMDMACREG *PPDMDMACREG;
2154
2155/** Current PDMDMACREG version number. */
2156#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2157
2158
2159/**
2160 * DMA Controller device helpers.
2161 */
2162typedef struct PDMDMACHLP
2163{
2164 /** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2165 uint32_t u32Version;
2166
2167 /* to-be-defined */
2168
2169} PDMDMACHLP;
2170/** Pointer to DMAC helpers. */
2171typedef PDMDMACHLP *PPDMDMACHLP;
2172/** Pointer to const DMAC helpers. */
2173typedef const PDMDMACHLP *PCPDMDMACHLP;
2174
2175/** Current PDMDMACHLP version number. */
2176#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2177
2178#endif /* IN_RING3 */
2179
2180
2181
2182/**
2183 * RTC registration structure.
2184 */
2185typedef struct PDMRTCREG
2186{
2187 /** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2188 uint32_t u32Version;
2189 uint32_t u32Alignment; /**< structure size alignment. */
2190
2191 /**
2192 * Write to a CMOS register and update the checksum if necessary.
2193 *
2194 * @returns VBox status code.
2195 * @param pDevIns Device instance of the RTC.
2196 * @param iReg The CMOS register index.
2197 * @param u8Value The CMOS register value.
2198 * @remarks Caller enters the device critical section.
2199 */
2200 DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2201
2202 /**
2203 * Read a CMOS register.
2204 *
2205 * @returns VBox status code.
2206 * @param pDevIns Device instance of the RTC.
2207 * @param iReg The CMOS register index.
2208 * @param pu8Value Where to store the CMOS register value.
2209 * @remarks Caller enters the device critical section.
2210 */
2211 DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2212
2213} PDMRTCREG;
2214/** Pointer to a RTC registration structure. */
2215typedef PDMRTCREG *PPDMRTCREG;
2216/** Pointer to a const RTC registration structure. */
2217typedef const PDMRTCREG *PCPDMRTCREG;
2218
2219/** Current PDMRTCREG version number. */
2220#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2221
2222
2223/**
2224 * RTC device helpers.
2225 */
2226typedef struct PDMRTCHLP
2227{
2228 /** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2229 uint32_t u32Version;
2230
2231 /* to-be-defined */
2232
2233} PDMRTCHLP;
2234/** Pointer to RTC helpers. */
2235typedef PDMRTCHLP *PPDMRTCHLP;
2236/** Pointer to const RTC helpers. */
2237typedef const PDMRTCHLP *PCPDMRTCHLP;
2238
2239/** Current PDMRTCHLP version number. */
2240#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2241
2242
2243
2244/** @name Flags for PCI I/O region registration
2245 * @{ */
2246/** No handle is passed. */
2247#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2248/** An I/O port handle is passed. */
2249#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2250/** An MMIO range handle is passed. */
2251#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2252/** An MMIO2 handle is passed. */
2253#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2254/** Handle type mask. */
2255#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2256/** New-style (mostly wrt callbacks). */
2257#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2258/** Mask of valid flags. */
2259#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2260/** @} */
2261
2262
2263/** @name Flags for the guest physical read/write helpers
2264 * @{ */
2265/** Default flag with no indication whether the data is processed by the device or just passed through. */
2266#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2267/** The data is user data which is just passed through between the guest and the source or destination and not processed
2268 * by the device in any way. */
2269#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2270/** The data is metadata and being processed by the device in some way. */
2271#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2272/** @} */
2273
2274
2275#ifdef IN_RING3
2276
2277/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2278 * @{ */
2279/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2280 * This is handy when registering multiple PCI device functions and the device
2281 * number is left up to the PCI bus. In order to facilitate one PDM device
2282 * instance for each PCI function, this searches earlier PDM device
2283 * instances as well. */
2284# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2285/** Use the first unused device number (all functions must be unused). */
2286# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2287/** Use the first unused device function. */
2288# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2289
2290/** The device and function numbers are not mandatory, just suggestions. */
2291# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2292/** Registering a PCI bridge device. */
2293# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2294/** Valid flag mask. */
2295# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2296/** @} */
2297
2298/** Current PDMDEVHLPR3 version number. */
2299#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 45, 0)
2300
2301/**
2302 * PDM Device API.
2303 */
2304typedef struct PDMDEVHLPR3
2305{
2306 /** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2307 uint32_t u32Version;
2308
2309 /** @name I/O ports
2310 * @{ */
2311 /**
2312 * Creates a range of I/O ports for a device.
2313 *
2314 * The I/O port range must be mapped in a separately call. Any ring-0 and
2315 * raw-mode context callback handlers needs to be set up in the respective
2316 * contexts.
2317 *
2318 * @returns VBox status.
2319 * @param pDevIns The device instance to register the ports with.
2320 * @param cPorts Number of ports to register.
2321 * @param fFlags IOM_IOPORT_F_XXX.
2322 * @param pPciDev The PCI device the range is associated with, if
2323 * applicable.
2324 * @param iPciRegion The PCI device region in the high 16-bit word and
2325 * sub-region in the low 16-bit word. UINT32_MAX if NA.
2326 * @param pfnOut Pointer to function which is gonna handle OUT
2327 * operations. Optional.
2328 * @param pfnIn Pointer to function which is gonna handle IN operations.
2329 * Optional.
2330 * @param pfnOutStr Pointer to function which is gonna handle string OUT
2331 * operations. Optional.
2332 * @param pfnInStr Pointer to function which is gonna handle string IN
2333 * operations. Optional.
2334 * @param pvUser User argument to pass to the callbacks.
2335 * @param pszDesc Pointer to description string. This must not be freed.
2336 * @param paExtDescs Extended per-port descriptions, optional. Partial range
2337 * coverage is allowed. This must not be freed.
2338 * @param phIoPorts Where to return the I/O port range handle.
2339 *
2340 * @remarks Caller enters the device critical section prior to invoking the
2341 * registered callback methods.
2342 *
2343 * @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2344 * PDMDevHlpIoPortUnmap.
2345 */
2346 DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2347 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2348 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2349 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2350
2351 /**
2352 * Maps an I/O port range.
2353 *
2354 * @returns VBox status.
2355 * @param pDevIns The device instance to register the ports with.
2356 * @param hIoPorts The I/O port range handle.
2357 * @param Port Where to map the range.
2358 * @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2359 * PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2360 */
2361 DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2362
2363 /**
2364 * Unmaps an I/O port range.
2365 *
2366 * @returns VBox status.
2367 * @param pDevIns The device instance to register the ports with.
2368 * @param hIoPorts The I/O port range handle.
2369 * @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2370 * PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2371 */
2372 DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2373
2374 /**
2375 * Gets the mapping address of the I/O port range @a hIoPorts.
2376 *
2377 * @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2378 * parameters).
2379 * @param pDevIns The device instance to register the ports with.
2380 * @param hIoPorts The I/O port range handle.
2381 */
2382 DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2383 /** @} */
2384
2385 /** @name MMIO
2386 * @{ */
2387 /**
2388 * Creates a memory mapped I/O (MMIO) region for a device.
2389 *
2390 * The MMIO region must be mapped in a separately call. Any ring-0 and
2391 * raw-mode context callback handlers needs to be set up in the respective
2392 * contexts.
2393 *
2394 * @returns VBox status.
2395 * @param pDevIns The device instance to register the ports with.
2396 * @param cbRegion The size of the region in bytes.
2397 * @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2398 * @param pPciDev The PCI device the range is associated with, if
2399 * applicable.
2400 * @param iPciRegion The PCI device region in the high 16-bit word and
2401 * sub-region in the low 16-bit word. UINT32_MAX if NA.
2402 * @param pfnWrite Pointer to function which is gonna handle Write
2403 * operations.
2404 * @param pfnRead Pointer to function which is gonna handle Read
2405 * operations.
2406 * @param pfnFill Pointer to function which is gonna handle Fill/memset
2407 * operations. (optional)
2408 * @param pvUser User argument to pass to the callbacks.
2409 * @param pszDesc Pointer to description string. This must not be freed.
2410 * @param phRegion Where to return the MMIO region handle.
2411 *
2412 * @remarks Caller enters the device critical section prior to invoking the
2413 * registered callback methods.
2414 *
2415 * @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2416 */
2417 DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2418 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2419 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2420 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion));
2421
2422 /**
2423 * Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2424 *
2425 * @returns VBox status.
2426 * @param pDevIns The device instance the region is associated with.
2427 * @param hRegion The MMIO region handle.
2428 * @param GCPhys Where to map the region.
2429 * @note An MMIO range may overlap with base memory if a lot of RAM is
2430 * configured for the VM, in which case we'll drop the base memory
2431 * pages. Presently we will make no attempt to preserve anything that
2432 * happens to be present in the base memory that is replaced, this is
2433 * technically incorrect but it's just not worth the effort to do
2434 * right, at least not at this point.
2435 * @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2436 * PDMDevHlpMmioSetUpContext
2437 */
2438 DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2439
2440 /**
2441 * Unmaps a memory mapped I/O (MMIO) region.
2442 *
2443 * @returns VBox status.
2444 * @param pDevIns The device instance the region is associated with.
2445 * @param hRegion The MMIO region handle.
2446 * @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2447 * PDMDevHlpMmioSetUpContext
2448 */
2449 DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2450
2451 /**
2452 * Reduces the length of a MMIO range.
2453 *
2454 * This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2455 * only work during saved state restore. It will not call the PCI bus code, as
2456 * that is expected to restore the saved resource configuration.
2457 *
2458 * It just adjusts the mapping length of the region so that when pfnMmioMap is
2459 * called it will only map @a cbRegion bytes and not the value set during
2460 * registration.
2461 *
2462 * @return VBox status code.
2463 * @param pDevIns The device owning the range.
2464 * @param hRegion The MMIO region handle.
2465 * @param cbRegion The new size, must be smaller.
2466 */
2467 DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2468
2469 /**
2470 * Gets the mapping address of the MMIO region @a hRegion.
2471 *
2472 * @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2473 * @param pDevIns The device instance to register the ports with.
2474 * @param hRegion The MMIO region handle.
2475 */
2476 DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2477 /** @} */
2478
2479 /** @name MMIO2
2480 * @{ */
2481 /**
2482 * Creates a MMIO2 region.
2483 *
2484 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2485 * associated with a device. It is also non-shared memory with a permanent
2486 * ring-3 mapping and page backing (presently).
2487 *
2488 * @returns VBox status.
2489 * @param pDevIns The device instance.
2490 * @param pPciDev The PCI device the region is associated with, or
2491 * NULL if no PCI device association.
2492 * @param iPciRegion The region number. Use the PCI region number as
2493 * this must be known to the PCI bus device too. If
2494 * it's not associated with the PCI device, then
2495 * any number up to UINT8_MAX is fine.
2496 * @param cbRegion The size (in bytes) of the region.
2497 * @param fFlags Reserved for future use, must be zero.
2498 * @param pszDesc Pointer to description string. This must not be
2499 * freed.
2500 * @param ppvMapping Where to store the address of the ring-3 mapping
2501 * of the memory.
2502 * @param phRegion Where to return the MMIO2 region handle.
2503 *
2504 * @thread EMT(0)
2505 */
2506 DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2507 uint32_t fFlags, const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion));
2508
2509 /**
2510 * Destroys a MMIO2 region, unmapping it and freeing the memory.
2511 *
2512 * Any physical access handlers registered for the region must be deregistered
2513 * before calling this function.
2514 *
2515 * @returns VBox status code.
2516 * @param pDevIns The device instance.
2517 * @param hRegion The MMIO2 region handle.
2518 * @thread EMT.
2519 */
2520 DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2521
2522 /**
2523 * Maps a MMIO2 region (into the guest physical address space).
2524 *
2525 * @returns VBox status.
2526 * @param pDevIns The device instance the region is associated with.
2527 * @param hRegion The MMIO2 region handle.
2528 * @param GCPhys Where to map the region.
2529 * @note A MMIO2 region overlap with base memory if a lot of RAM is
2530 * configured for the VM, in which case we'll drop the base memory
2531 * pages. Presently we will make no attempt to preserve anything that
2532 * happens to be present in the base memory that is replaced, this is
2533 * technically incorrect but it's just not worth the effort to do
2534 * right, at least not at this point.
2535 * @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2536 */
2537 DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2538
2539 /**
2540 * Unmaps a MMIO2 region.
2541 *
2542 * @returns VBox status.
2543 * @param pDevIns The device instance the region is associated with.
2544 * @param hRegion The MMIO2 region handle.
2545 * @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2546 */
2547 DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2548
2549 /**
2550 * Reduces the length of a MMIO range.
2551 *
2552 * This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2553 * only work during saved state restore. It will not call the PCI bus code, as
2554 * that is expected to restore the saved resource configuration.
2555 *
2556 * It just adjusts the mapping length of the region so that when pfnMmioMap is
2557 * called it will only map @a cbRegion bytes and not the value set during
2558 * registration.
2559 *
2560 * @return VBox status code.
2561 * @param pDevIns The device owning the range.
2562 * @param hRegion The MMIO2 region handle.
2563 * @param cbRegion The new size, must be smaller.
2564 */
2565 DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2566
2567 /**
2568 * Gets the mapping address of the MMIO region @a hRegion.
2569 *
2570 * @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2571 * @param pDevIns The device instance to register the ports with.
2572 * @param hRegion The MMIO2 region handle.
2573 */
2574 DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2575
2576 /**
2577 * Changes the number of an MMIO2 or pre-registered MMIO region.
2578 *
2579 * This should only be used to deal with saved state problems, so there is no
2580 * convenience inline wrapper for this method.
2581 *
2582 * @returns VBox status code.
2583 * @param pDevIns The device instance.
2584 * @param hRegion The MMIO2 region handle.
2585 * @param iNewRegion The new region index.
2586 *
2587 * @sa @bugref{9359}
2588 */
2589 DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2590 /** @} */
2591
2592 /**
2593 * Register a ROM (BIOS) region.
2594 *
2595 * It goes without saying that this is read-only memory. The memory region must be
2596 * in unassigned memory. I.e. from the top of the address space or on the PC in
2597 * the 0xa0000-0xfffff range.
2598 *
2599 * @returns VBox status.
2600 * @param pDevIns The device instance owning the ROM region.
2601 * @param GCPhysStart First physical address in the range.
2602 * Must be page aligned!
2603 * @param cbRange The size of the range (in bytes).
2604 * Must be page aligned!
2605 * @param pvBinary Pointer to the binary data backing the ROM image.
2606 * @param cbBinary The size of the binary pointer. This must
2607 * be equal or smaller than @a cbRange.
2608 * @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2609 * @param pszDesc Pointer to description string. This must not be freed.
2610 *
2611 * @remark There is no way to remove the rom, automatically on device cleanup or
2612 * manually from the device yet. At present I doubt we need such features...
2613 */
2614 DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2615 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc));
2616
2617 /**
2618 * Changes the protection of shadowed ROM mapping.
2619 *
2620 * This is intented for use by the system BIOS, chipset or device in question to
2621 * change the protection of shadowed ROM code after init and on reset.
2622 *
2623 * @param pDevIns The device instance.
2624 * @param GCPhysStart Where the mapping starts.
2625 * @param cbRange The size of the mapping.
2626 * @param enmProt The new protection type.
2627 */
2628 DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2629
2630 /**
2631 * Register a save state data unit.
2632 *
2633 * @returns VBox status.
2634 * @param pDevIns The device instance.
2635 * @param uVersion Data layout version number.
2636 * @param cbGuess The approximate amount of data in the unit.
2637 * Only for progress indicators.
2638 * @param pszBefore Name of data unit which we should be put in
2639 * front of. Optional (NULL).
2640 *
2641 * @param pfnLivePrep Prepare live save callback, optional.
2642 * @param pfnLiveExec Execute live save callback, optional.
2643 * @param pfnLiveVote Vote live save callback, optional.
2644 *
2645 * @param pfnSavePrep Prepare save callback, optional.
2646 * @param pfnSaveExec Execute save callback, optional.
2647 * @param pfnSaveDone Done save callback, optional.
2648 *
2649 * @param pfnLoadPrep Prepare load callback, optional.
2650 * @param pfnLoadExec Execute load callback, optional.
2651 * @param pfnLoadDone Done load callback, optional.
2652 * @remarks Caller enters the device critical section prior to invoking the
2653 * registered callback methods.
2654 */
2655 DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2656 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2657 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2658 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2659
2660 /** @name Exported SSM Functions
2661 * @{ */
2662 DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2663 DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void *pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void *pvUser));
2664 DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2665 DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2666 DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2667 DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2668 DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2669 DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2670 DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2671 DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2672 DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2673 DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2674 DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2675 DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2676 DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2677 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2678 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2679 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2680 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2681 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2682 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2683 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2684 DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2685 DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2686 DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2687 DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2688 DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2689 DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2690 DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void *pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void *pvUser));
2691 DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2692 DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2693 DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2694 DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2695 DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2696 DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2697 DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2698 DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2699 DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2700 DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2701 DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2702 DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2703 DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2704 DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2705 DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2706 DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2707 DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2708 DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2709 DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2710 DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2711 DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2712 DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2713 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2714 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2715 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2716 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2717 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2718 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2719 DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2720 DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2721 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2722 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2723 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2724 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2725 DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2726 DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2727 DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2728 DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2729 DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2730 DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char *psz, size_t cbMax, size_t *pcbStr));
2731 DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2732 DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2733 DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2734 DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2735 DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2736 DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2737 DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2738 DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2739 DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2740 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2741 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2742 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2743 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2744 DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2745 /** @} */
2746
2747 /**
2748 * Creates a timer.
2749 *
2750 * @returns VBox status.
2751 * @param pDevIns The device instance.
2752 * @param enmClock The clock to use on this timer.
2753 * @param pfnCallback Callback function.
2754 * @param pvUser User argument for the callback.
2755 * @param fFlags Flags, see TMTIMER_FLAGS_*.
2756 * @param pszDesc Pointer to description string which must stay around
2757 * until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2758 * @param ppTimer Where to store the timer on success.
2759 * @remarks Caller enters the device critical section prior to invoking the
2760 * callback.
2761 */
2762 DECLR3CALLBACKMEMBER(int, pfnTMTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2763 void *pvUser, uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer));
2764
2765 /**
2766 * Creates a timer w/ a cross context handle.
2767 *
2768 * @returns VBox status.
2769 * @param pDevIns The device instance.
2770 * @param enmClock The clock to use on this timer.
2771 * @param pfnCallback Callback function.
2772 * @param pvUser User argument for the callback.
2773 * @param fFlags Flags, see TMTIMER_FLAGS_*.
2774 * @param pszDesc Pointer to description string which must stay around
2775 * until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2776 * @param phTimer Where to store the timer handle on success.
2777 * @remarks Caller enters the device critical section prior to invoking the
2778 * callback.
2779 */
2780 DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2781 void *pvUser, uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer));
2782
2783 /**
2784 * Translates a timer handle to a pointer.
2785 *
2786 * @returns The time address.
2787 * @param pDevIns The device instance.
2788 * @param hTimer The timer handle.
2789 */
2790 DECLR3CALLBACKMEMBER(PTMTIMERR3, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2791
2792 /** @name Timer handle method wrappers
2793 * @{ */
2794 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2795 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2796 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2797 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2798 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2799 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2800 DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2801 DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2802 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2803 /** Takes the clock lock then enters the specified critical section. */
2804 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2805 DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2806 DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2807 DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2808 DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2809 DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2810 DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2811 DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2812 DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2813 DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2814 DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2815 DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2816 DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2817 DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2818 /** @sa TMR3TimerSkip */
2819 DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2820 /** @} */
2821
2822 /**
2823 * Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2824 *
2825 * @returns pTime.
2826 * @param pDevIns The device instance.
2827 * @param pTime Where to store the time.
2828 */
2829 DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2830
2831 /** @name Exported CFGM Functions.
2832 * @{ */
2833 DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2834 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2835 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char *pszName, size_t *pcb));
2836 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64));
2837 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64, uint64_t u64Def));
2838 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char *pszName, char *pszString, size_t cchString));
2839 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char *pszName, char *pszString, size_t cchString, const char *pszDef));
2840 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char *pszName, void *pvData, size_t cbData));
2841 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64));
2842 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64, uint64_t u64Def));
2843 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char *pszName, int64_t *pi64));
2844 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char *pszName, int64_t *pi64, int64_t i64Def));
2845 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char *pszName, uint32_t *pu32));
2846 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char *pszName, uint32_t *pu32, uint32_t u32Def));
2847 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char *pszName, int32_t *pi32));
2848 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char *pszName, int32_t *pi32, int32_t i32Def));
2849 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char *pszName, uint16_t *pu16));
2850 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char *pszName, uint16_t *pu16, uint16_t u16Def));
2851 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char *pszName, int16_t *pi16));
2852 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char *pszName, int16_t *pi16, int16_t i16Def));
2853 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char *pszName, uint8_t *pu8));
2854 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char *pszName, uint8_t *pu8, uint8_t u8Def));
2855 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char *pszName, int8_t *pi8));
2856 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char *pszName, int8_t *pi8, int8_t i8Def));
2857 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char *pszName, bool *pf));
2858 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char *pszName, bool *pf, bool fDef));
2859 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2860 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2861 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char *pszName, unsigned int *pu));
2862 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char *pszName, unsigned int *pu, unsigned int uDef));
2863 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char *pszName, signed int *pi));
2864 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char *pszName, signed int *pi, signed int iDef));
2865 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char *pszName, void **ppv));
2866 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char *pszName, void **ppv, void *pvDef));
2867 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
2868 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
2869 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
2870 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
2871 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
2872 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
2873 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char *pszName, char **ppszString));
2874 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char *pszName, char **ppszString, const char *pszDef));
2875 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
2876 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
2877 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
2878 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
2879 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
2880 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
2881 DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
2882 DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
2883 DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
2884 DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
2885 DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
2886 DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
2887 DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
2888 DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
2889 DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
2890 DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
2891 const char *pszValidValues, const char *pszValidNodes,
2892 const char *pszWho, uint32_t uInstance));
2893 /** @} */
2894
2895 /**
2896 * Read physical memory.
2897 *
2898 * @returns VINF_SUCCESS (for now).
2899 * @param pDevIns The device instance.
2900 * @param GCPhys Physical address start reading from.
2901 * @param pvBuf Where to put the read bits.
2902 * @param cbRead How many bytes to read.
2903 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
2904 * @thread Any thread, but the call may involve the emulation thread.
2905 */
2906 DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
2907
2908 /**
2909 * Write to physical memory.
2910 *
2911 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
2912 * @param pDevIns The device instance.
2913 * @param GCPhys Physical address to write to.
2914 * @param pvBuf What to write.
2915 * @param cbWrite How many bytes to write.
2916 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
2917 * @thread Any thread, but the call may involve the emulation thread.
2918 */
2919 DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
2920
2921 /**
2922 * Requests the mapping of a guest page into ring-3.
2923 *
2924 * When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2925 * release it.
2926 *
2927 * This API will assume your intention is to write to the page, and will
2928 * therefore replace shared and zero pages. If you do not intend to modify the
2929 * page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
2930 *
2931 * @returns VBox status code.
2932 * @retval VINF_SUCCESS on success.
2933 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2934 * backing or if the page has any active access handlers. The caller
2935 * must fall back on using PGMR3PhysWriteExternal.
2936 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2937 *
2938 * @param pDevIns The device instance.
2939 * @param GCPhys The guest physical address of the page that
2940 * should be mapped.
2941 * @param fFlags Flags reserved for future use, MBZ.
2942 * @param ppv Where to store the address corresponding to
2943 * GCPhys.
2944 * @param pLock Where to store the lock information that
2945 * pfnPhysReleasePageMappingLock needs.
2946 *
2947 * @remark Avoid calling this API from within critical sections (other than the
2948 * PGM one) because of the deadlock risk when we have to delegating the
2949 * task to an EMT.
2950 * @thread Any.
2951 */
2952 DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
2953 PPGMPAGEMAPLOCK pLock));
2954
2955 /**
2956 * Requests the mapping of a guest page into ring-3, external threads.
2957 *
2958 * When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2959 * release it.
2960 *
2961 * @returns VBox status code.
2962 * @retval VINF_SUCCESS on success.
2963 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2964 * backing or if the page as an active ALL access handler. The caller
2965 * must fall back on using PGMPhysRead.
2966 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2967 *
2968 * @param pDevIns The device instance.
2969 * @param GCPhys The guest physical address of the page that
2970 * should be mapped.
2971 * @param fFlags Flags reserved for future use, MBZ.
2972 * @param ppv Where to store the address corresponding to
2973 * GCPhys.
2974 * @param pLock Where to store the lock information that
2975 * pfnPhysReleasePageMappingLock needs.
2976 *
2977 * @remark Avoid calling this API from within critical sections.
2978 * @thread Any.
2979 */
2980 DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
2981 void const **ppv, PPGMPAGEMAPLOCK pLock));
2982
2983 /**
2984 * Release the mapping of a guest page.
2985 *
2986 * This is the counter part of pfnPhysGCPhys2CCPtr and
2987 * pfnPhysGCPhys2CCPtrReadOnly.
2988 *
2989 * @param pDevIns The device instance.
2990 * @param pLock The lock structure initialized by the mapping
2991 * function.
2992 */
2993 DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
2994
2995 /**
2996 * Read guest physical memory by virtual address.
2997 *
2998 * @param pDevIns The device instance.
2999 * @param pvDst Where to put the read bits.
3000 * @param GCVirtSrc Guest virtual address to start reading from.
3001 * @param cb How many bytes to read.
3002 * @thread The emulation thread.
3003 */
3004 DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3005
3006 /**
3007 * Write to guest physical memory by virtual address.
3008 *
3009 * @param pDevIns The device instance.
3010 * @param GCVirtDst Guest virtual address to write to.
3011 * @param pvSrc What to write.
3012 * @param cb How many bytes to write.
3013 * @thread The emulation thread.
3014 */
3015 DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3016
3017 /**
3018 * Convert a guest virtual address to a guest physical address.
3019 *
3020 * @returns VBox status code.
3021 * @param pDevIns The device instance.
3022 * @param GCPtr Guest virtual address.
3023 * @param pGCPhys Where to store the GC physical address
3024 * corresponding to GCPtr.
3025 * @thread The emulation thread.
3026 * @remark Careful with page boundaries.
3027 */
3028 DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3029
3030 /**
3031 * Allocate memory which is associated with current VM instance
3032 * and automatically freed on it's destruction.
3033 *
3034 * @returns Pointer to allocated memory. The memory is *NOT* zero-ed.
3035 * @param pDevIns The device instance.
3036 * @param cb Number of bytes to allocate.
3037 */
3038 DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3039
3040 /**
3041 * Allocate memory which is associated with current VM instance
3042 * and automatically freed on it's destruction. The memory is ZEROed.
3043 *
3044 * @returns Pointer to allocated memory. The memory is *NOT* zero-ed.
3045 * @param pDevIns The device instance.
3046 * @param cb Number of bytes to allocate.
3047 */
3048 DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3049
3050 /**
3051 * Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3052 *
3053 * @param pDevIns The device instance.
3054 * @param pv Pointer to the memory to free.
3055 */
3056 DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3057
3058 /**
3059 * Gets the VM state.
3060 *
3061 * @returns VM state.
3062 * @param pDevIns The device instance.
3063 * @thread Any thread (just keep in mind that it's volatile info).
3064 */
3065 DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3066
3067 /**
3068 * Checks if the VM was teleported and hasn't been fully resumed yet.
3069 *
3070 * @returns true / false.
3071 * @param pDevIns The device instance.
3072 * @thread Any thread.
3073 */
3074 DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3075
3076 /**
3077 * Set the VM error message
3078 *
3079 * @returns rc.
3080 * @param pDevIns The device instance.
3081 * @param rc VBox status code.
3082 * @param SRC_POS Use RT_SRC_POS.
3083 * @param pszFormat Error message format string.
3084 * @param ... Error message arguments.
3085 */
3086 DECLR3CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3087 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
3088
3089 /**
3090 * Set the VM error message
3091 *
3092 * @returns rc.
3093 * @param pDevIns The device instance.
3094 * @param rc VBox status code.
3095 * @param SRC_POS Use RT_SRC_POS.
3096 * @param pszFormat Error message format string.
3097 * @param va Error message arguments.
3098 */
3099 DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3100 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3101
3102 /**
3103 * Set the VM runtime error message
3104 *
3105 * @returns VBox status code.
3106 * @param pDevIns The device instance.
3107 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3108 * @param pszErrorId Error ID string.
3109 * @param pszFormat Error message format string.
3110 * @param ... Error message arguments.
3111 */
3112 DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3113 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
3114
3115 /**
3116 * Set the VM runtime error message
3117 *
3118 * @returns VBox status code.
3119 * @param pDevIns The device instance.
3120 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3121 * @param pszErrorId Error ID string.
3122 * @param pszFormat Error message format string.
3123 * @param va Error message arguments.
3124 */
3125 DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3126 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3127
3128 /**
3129 * Stops the VM and enters the debugger to look at the guest state.
3130 *
3131 * Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3132 * invoking this function directly.
3133 *
3134 * @returns VBox status code which must be passed up to the VMM.
3135 * @param pDevIns The device instance.
3136 * @param pszFile Filename of the assertion location.
3137 * @param iLine The linenumber of the assertion location.
3138 * @param pszFunction Function of the assertion location.
3139 * @param pszFormat Message. (optional)
3140 * @param args Message parameters.
3141 */
3142 DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction,
3143 const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3144
3145 /**
3146 * Register a info handler with DBGF.
3147 *
3148 * @returns VBox status code.
3149 * @param pDevIns The device instance.
3150 * @param pszName The identifier of the info.
3151 * @param pszDesc The description of the info and any arguments
3152 * the handler may take.
3153 * @param pfnHandler The handler function to be called to display the
3154 * info.
3155 */
3156 DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3157
3158 /**
3159 * Register a info handler with DBGF, argv style.
3160 *
3161 * @returns VBox status code.
3162 * @param pDevIns The device instance.
3163 * @param pszName The identifier of the info.
3164 * @param pszDesc The description of the info and any arguments
3165 * the handler may take.
3166 * @param pfnHandler The handler function to be called to display the
3167 * info.
3168 */
3169 DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3170
3171 /**
3172 * Registers a set of registers for a device.
3173 *
3174 * The @a pvUser argument of the getter and setter callbacks will be
3175 * @a pDevIns. The register names will be prefixed by the device name followed
3176 * immediately by the instance number.
3177 *
3178 * @returns VBox status code.
3179 * @param pDevIns The device instance.
3180 * @param paRegisters The register descriptors.
3181 *
3182 * @remarks The device critical section is NOT entered prior to working the
3183 * callbacks registered via this helper!
3184 */
3185 DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3186
3187 /**
3188 * Gets the trace buffer handle.
3189 *
3190 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3191 * really inteded for direct usage, thus no inline wrapper function.
3192 *
3193 * @returns Trace buffer handle or NIL_RTTRACEBUF.
3194 * @param pDevIns The device instance.
3195 */
3196 DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3197
3198 /**
3199 * Registers a statistics sample.
3200 *
3201 * @param pDevIns Device instance of the DMA.
3202 * @param pvSample Pointer to the sample.
3203 * @param enmType Sample type. This indicates what pvSample is
3204 * pointing at.
3205 * @param pszName Sample name, unix path style. If this does not
3206 * start with a '/', the default prefix will be
3207 * prepended, otherwise it will be used as-is.
3208 * @param enmUnit Sample unit.
3209 * @param pszDesc Sample description.
3210 */
3211 DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc));
3212
3213 /**
3214 * Same as pfnSTAMRegister except that the name is specified in a
3215 * RTStrPrintfV like fashion.
3216 *
3217 * @returns VBox status.
3218 * @param pDevIns Device instance of the DMA.
3219 * @param pvSample Pointer to the sample.
3220 * @param enmType Sample type. This indicates what pvSample is
3221 * pointing at.
3222 * @param enmVisibility Visibility type specifying whether unused
3223 * statistics should be visible or not.
3224 * @param enmUnit Sample unit.
3225 * @param pszDesc Sample description.
3226 * @param pszName Sample name format string, unix path style. If
3227 * this does not start with a '/', the default
3228 * prefix will be prepended, otherwise it will be
3229 * used as-is.
3230 * @param args Arguments to the format string.
3231 */
3232 DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3233 STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3234 const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3235
3236 /**
3237 * Registers a PCI device with the default PCI bus.
3238 *
3239 * If a PDM device has more than one PCI device, they must be registered in the
3240 * order of PDMDEVINSR3::apPciDevs.
3241 *
3242 * @returns VBox status code.
3243 * @param pDevIns The device instance.
3244 * @param pPciDev The PCI device structure.
3245 * This must be kept in the instance data.
3246 * The PCI configuration must be initialized before registration.
3247 * @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3248 * PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3249 * @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3250 * PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3251 * device number (0-31). This will be ignored if
3252 * the CFGM configuration contains a PCIDeviceNo
3253 * value.
3254 * @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3255 * function number (0-7). This will be ignored if
3256 * the CFGM configuration contains a PCIFunctionNo
3257 * value.
3258 * @param pszName Device name, if NULL PDMDEVREG::szName is used.
3259 * The pointer is saved, so don't free or changed.
3260 * @note The PCI device configuration is now implicit from the apPciDevs
3261 * index, meaning that the zero'th entry is the primary one and
3262 * subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3263 */
3264 DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3265 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3266
3267 /**
3268 * Initialize MSI or MSI-X emulation support for the given PCI device.
3269 *
3270 * @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3271 *
3272 * @returns VBox status code.
3273 * @param pDevIns The device instance.
3274 * @param pPciDev The PCI device. NULL is an alias for the first
3275 * one registered.
3276 * @param pMsiReg MSI emulation registration structure.
3277 */
3278 DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3279
3280 /**
3281 * Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3282 *
3283 * @returns VBox status code.
3284 * @param pDevIns The device instance.
3285 * @param pPciDev The PCI device structure. If NULL the default
3286 * PCI device for this device instance is used.
3287 * @param iRegion The region number.
3288 * @param cbRegion Size of the region.
3289 * @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3290 * @param fFlags PDMPCIDEV_IORGN_F_XXX.
3291 * @param hHandle An I/O port, MMIO or MMIO2 handle according to
3292 * @a fFlags, UINT64_MAX if no handle is passed
3293 * (old style).
3294 * @param pfnMapUnmap Callback for doing the mapping, optional when a
3295 * handle is specified. The callback will be
3296 * invoked holding only the PDM lock. The device
3297 * lock will _not_ be taken (due to lock order).
3298 */
3299 DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3300 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3301 uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3302
3303 /**
3304 * Register PCI configuration space read/write callbacks.
3305 *
3306 * @returns VBox status code.
3307 * @param pDevIns The device instance.
3308 * @param pPciDev The PCI device structure. If NULL the default
3309 * PCI device for this device instance is used.
3310 * @param pfnRead Pointer to the user defined PCI config read function.
3311 * to call default PCI config read function. Can be NULL.
3312 * @param pfnWrite Pointer to the user defined PCI config write function.
3313 * @remarks The callbacks will be invoked holding the PDM lock. The device lock
3314 * is NOT take because that is very likely be a lock order violation.
3315 * @thread EMT(0)
3316 * @note Only callable during VM creation.
3317 * @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3318 */
3319 DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3320 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3321
3322 /**
3323 * Perform a PCI configuration space write.
3324 *
3325 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3326 *
3327 * @returns Strict VBox status code (mainly DBGFSTOP).
3328 * @param pDevIns The device instance.
3329 * @param pPciDev The PCI device which config space is being read.
3330 * @param uAddress The config space address.
3331 * @param cb The size of the read: 1, 2 or 4 bytes.
3332 * @param u32Value The value to write.
3333 */
3334 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3335 uint32_t uAddress, unsigned cb, uint32_t u32Value));
3336
3337 /**
3338 * Perform a PCI configuration space read.
3339 *
3340 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3341 *
3342 * @returns Strict VBox status code (mainly DBGFSTOP).
3343 * @param pDevIns The device instance.
3344 * @param pPciDev The PCI device which config space is being read.
3345 * @param uAddress The config space address.
3346 * @param cb The size of the read: 1, 2 or 4 bytes.
3347 * @param pu32Value Where to return the value.
3348 */
3349 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3350 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3351
3352 /**
3353 * Bus master physical memory read.
3354 *
3355 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3356 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
3357 * @param pDevIns The device instance.
3358 * @param pPciDev The PCI device structure. If NULL the default
3359 * PCI device for this device instance is used.
3360 * @param GCPhys Physical address start reading from.
3361 * @param pvBuf Where to put the read bits.
3362 * @param cbRead How many bytes to read.
3363 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3364 * @thread Any thread, but the call may involve the emulation thread.
3365 */
3366 DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3367
3368 /**
3369 * Bus master physical memory write.
3370 *
3371 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3372 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
3373 * @param pDevIns The device instance.
3374 * @param pPciDev The PCI device structure. If NULL the default
3375 * PCI device for this device instance is used.
3376 * @param GCPhys Physical address to write to.
3377 * @param pvBuf What to write.
3378 * @param cbWrite How many bytes to write.
3379 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3380 * @thread Any thread, but the call may involve the emulation thread.
3381 */
3382 DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3383
3384 /**
3385 * Requests the mapping of a guest page into ring-3 in preparation for a bus master
3386 * physical memory write operation.
3387 *
3388 * Refer pfnPhysGCPhys2CCPtr() for further details.
3389 *
3390 * @returns VBox status code.
3391 * @param pDevIns The device instance.
3392 * @param pPciDev The PCI device structure. If NULL the default
3393 * PCI device for this device instance is used.
3394 * @param GCPhys The guest physical address of the page that should be
3395 * mapped.
3396 * @param fFlags Flags reserved for future use, MBZ.
3397 * @param ppv Where to store the address corresponding to GCPhys.
3398 * @param pLock Where to store the lock information that
3399 * pfnPhysReleasePageMappingLock needs.
3400 *
3401 * @remarks Avoid calling this API from within critical sections (other than the PGM
3402 * one) because of the deadlock risk when we have to delegating the task to
3403 * an EMT.
3404 * @thread Any.
3405 */
3406 DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3407 void **ppv, PPGMPAGEMAPLOCK pLock));
3408
3409 /**
3410 * Requests the mapping of a guest page into ring-3, external threads, in prepartion
3411 * for a bus master physical memory read operation.
3412 *
3413 * Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3414 *
3415 * @returns VBox status code.
3416 * @param pDevIns The device instance.
3417 * @param pPciDev The PCI device structure. If NULL the default
3418 * PCI device for this device instance is used.
3419 * @param GCPhys The guest physical address of the page that
3420 * should be mapped.
3421 * @param fFlags Flags reserved for future use, MBZ.
3422 * @param ppv Where to store the address corresponding to
3423 * GCPhys.
3424 * @param pLock Where to store the lock information that
3425 * pfnPhysReleasePageMappingLock needs.
3426 *
3427 * @remarks Avoid calling this API from within critical sections.
3428 * @thread Any.
3429 */
3430 DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3431 uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3432
3433 /**
3434 * Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3435 * master physical memory write operation.
3436 *
3437 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3438 * ASAP to release them.
3439 *
3440 * Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3441 *
3442 * @returns VBox status code.
3443 * @param pDevIns The device instance.
3444 * @param pPciDev The PCI device structure. If NULL the default
3445 * PCI device for this device instance is used.
3446 * @param cPages Number of pages to lock.
3447 * @param paGCPhysPages The guest physical address of the pages that
3448 * should be mapped (@a cPages entries).
3449 * @param fFlags Flags reserved for future use, MBZ.
3450 * @param papvPages Where to store the ring-3 mapping addresses
3451 * corresponding to @a paGCPhysPages.
3452 * @param paLocks Where to store the locking information that
3453 * pfnPhysBulkReleasePageMappingLock needs (@a cPages
3454 * in length).
3455 */
3456 DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3457 PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3458 PPGMPAGEMAPLOCK paLocks));
3459
3460 /**
3461 * Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3462 * master physical memory read operation.
3463 *
3464 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3465 * ASAP to release them.
3466 *
3467 * Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3468 *
3469 * @returns VBox status code.
3470 * @param pDevIns The device instance.
3471 * @param pPciDev The PCI device structure. If NULL the default
3472 * PCI device for this device instance is used.
3473 * @param cPages Number of pages to lock.
3474 * @param paGCPhysPages The guest physical address of the pages that
3475 * should be mapped (@a cPages entries).
3476 * @param fFlags Flags reserved for future use, MBZ.
3477 * @param papvPages Where to store the ring-3 mapping addresses
3478 * corresponding to @a paGCPhysPages.
3479 * @param paLocks Where to store the lock information that
3480 * pfnPhysReleasePageMappingLock needs (@a cPages
3481 * in length).
3482 */
3483 DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3484 PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3485 void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3486
3487 /**
3488 * Sets the IRQ for the given PCI device.
3489 *
3490 * @param pDevIns The device instance.
3491 * @param pPciDev The PCI device structure. If NULL the default
3492 * PCI device for this device instance is used.
3493 * @param iIrq IRQ number to set.
3494 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3495 * @thread Any thread, but will involve the emulation thread.
3496 */
3497 DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3498
3499 /**
3500 * Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3501 * the request when not called from EMT.
3502 *
3503 * @param pDevIns The device instance.
3504 * @param pPciDev The PCI device structure. If NULL the default
3505 * PCI device for this device instance is used.
3506 * @param iIrq IRQ number to set.
3507 * @param iLevel IRQ level.
3508 * @thread Any thread, but will involve the emulation thread.
3509 */
3510 DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3511
3512 /**
3513 * Set ISA IRQ for a device.
3514 *
3515 * @param pDevIns The device instance.
3516 * @param iIrq IRQ number to set.
3517 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3518 * @thread Any thread, but will involve the emulation thread.
3519 */
3520 DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3521
3522 /**
3523 * Set the ISA IRQ for a device, but don't wait for EMT to process
3524 * the request when not called from EMT.
3525 *
3526 * @param pDevIns The device instance.
3527 * @param iIrq IRQ number to set.
3528 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3529 * @thread Any thread, but will involve the emulation thread.
3530 */
3531 DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3532
3533 /**
3534 * Attaches a driver (chain) to the device.
3535 *
3536 * The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3537 * the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3538 *
3539 * @returns VBox status code.
3540 * @param pDevIns The device instance.
3541 * @param iLun The logical unit to attach.
3542 * @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3543 * @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3544 * @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3545 * for the live of the device instance.
3546 */
3547 DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3548 PPDMIBASE *ppBaseInterface, const char *pszDesc));
3549
3550 /**
3551 * Detaches an attached driver (chain) from the device again.
3552 *
3553 * @returns VBox status code.
3554 * @param pDevIns The device instance.
3555 * @param pDrvIns The driver instance to detach.
3556 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3557 */
3558 DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3559
3560 /**
3561 * Reconfigures the driver chain for a LUN, detaching any driver currently
3562 * present there.
3563 *
3564 * Caller will have attach it, of course.
3565 *
3566 * @returns VBox status code.
3567 * @param pDevIns The device instance.
3568 * @param iLun The logical unit to reconfigure.
3569 * @param cDepth The depth of the driver chain. Determins the
3570 * size of @a papszDrivers and @a papConfigs.
3571 * @param papszDrivers The names of the drivers to configure in the
3572 * chain, first entry is the one immediately
3573 * below the device/LUN
3574 * @param papConfigs The configurations for each of the drivers
3575 * in @a papszDrivers array. NULL entries
3576 * corresponds to empty 'Config' nodes. This
3577 * function will take ownership of non-NULL
3578 * CFGM sub-trees and set the array member to
3579 * NULL, so the caller can do cleanups on
3580 * failure. This parameter is optional.
3581 * @param fFlags Reserved, MBZ.
3582 */
3583 DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3584 const char * const *papszDrivers, PCFGMNODE *papConfigs, uint32_t fFlags));
3585
3586 /** @name Exported PDM Queue Functions
3587 * @{ */
3588 /**
3589 * Create a queue.
3590 *
3591 * @returns VBox status code.
3592 * @param pDevIns The device instance.
3593 * @param cbItem The size of a queue item.
3594 * @param cItems The number of items in the queue.
3595 * @param cMilliesInterval The number of milliseconds between polling the queue.
3596 * If 0 then the emulation thread will be notified whenever an item arrives.
3597 * @param pfnCallback The consumer function.
3598 * @param fRZEnabled Set if the queue should work in RC and R0.
3599 * @param pszName The queue base name. The instance number will be
3600 * appended automatically.
3601 * @param ppQueue Where to store the queue pointer on success.
3602 * @thread The emulation thread.
3603 * @remarks The device critical section will NOT be entered before calling the
3604 * callback. No locks will be held, but for now it's safe to assume
3605 * that only one EMT will do queue callbacks at any one time.
3606 */
3607 DECLR3CALLBACKMEMBER(int, pfnQueueCreatePtr,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3608 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3609 PPDMQUEUE *ppQueue));
3610
3611 /**
3612 * Create a queue.
3613 *
3614 * @returns VBox status code.
3615 * @param pDevIns The device instance.
3616 * @param cbItem The size of a queue item.
3617 * @param cItems The number of items in the queue.
3618 * @param cMilliesInterval The number of milliseconds between polling the queue.
3619 * If 0 then the emulation thread will be notified whenever an item arrives.
3620 * @param pfnCallback The consumer function.
3621 * @param fRZEnabled Set if the queue should work in RC and R0.
3622 * @param pszName The queue base name. The instance number will be
3623 * appended automatically.
3624 * @param phQueue Where to store the queue handle on success.
3625 * @thread EMT(0)
3626 * @remarks The device critical section will NOT be entered before calling the
3627 * callback. No locks will be held, but for now it's safe to assume
3628 * that only one EMT will do queue callbacks at any one time.
3629 */
3630 DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3631 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3632 PDMQUEUEHANDLE *phQueue));
3633
3634 DECLR3CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3635 DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3636 DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3637 DECLR3CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
3638 DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3639 /** @} */
3640
3641 /** @name PDM Task
3642 * @{ */
3643 /**
3644 * Create an asynchronous ring-3 task.
3645 *
3646 * @returns VBox status code.
3647 * @param pDevIns The device instance.
3648 * @param fFlags PDMTASK_F_XXX
3649 * @param pszName The function name or similar. Used for statistics,
3650 * so no slashes.
3651 * @param pfnCallback The task function.
3652 * @param pvUser User argument for the task function.
3653 * @param phTask Where to return the task handle.
3654 * @thread EMT(0)
3655 */
3656 DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3657 PFNPDMTASKDEV pfnCallback, void *pvUser, PDMTASKHANDLE *phTask));
3658 /**
3659 * Triggers the running the given task.
3660 *
3661 * @returns VBox status code.
3662 * @retval VINF_ALREADY_POSTED is the task is already pending.
3663 * @param pDevIns The device instance.
3664 * @param hTask The task to trigger.
3665 * @thread Any thread.
3666 */
3667 DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3668 /** @} */
3669
3670 /** @name SUP Event Semaphore Wrappers (single release / auto reset)
3671 * These semaphores can be signalled from ring-0.
3672 * @{ */
3673 /** @sa SUPSemEventCreate */
3674 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3675 /** @sa SUPSemEventClose */
3676 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3677 /** @sa SUPSemEventSignal */
3678 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3679 /** @sa SUPSemEventWaitNoResume */
3680 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3681 /** @sa SUPSemEventWaitNsAbsIntr */
3682 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3683 /** @sa SUPSemEventWaitNsRelIntr */
3684 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3685 /** @sa SUPSemEventGetResolution */
3686 DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3687 /** @} */
3688
3689 /** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3690 * These semaphores can be signalled from ring-0.
3691 * @{ */
3692 /** @sa SUPSemEventMultiCreate */
3693 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3694 /** @sa SUPSemEventMultiClose */
3695 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3696 /** @sa SUPSemEventMultiSignal */
3697 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3698 /** @sa SUPSemEventMultiReset */
3699 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3700 /** @sa SUPSemEventMultiWaitNoResume */
3701 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3702 /** @sa SUPSemEventMultiWaitNsAbsIntr */
3703 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3704 /** @sa SUPSemEventMultiWaitNsRelIntr */
3705 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3706 /** @sa SUPSemEventMultiGetResolution */
3707 DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3708 /** @} */
3709
3710 /**
3711 * Initializes a PDM critical section.
3712 *
3713 * The PDM critical sections are derived from the IPRT critical sections, but
3714 * works in RC and R0 as well.
3715 *
3716 * @returns VBox status code.
3717 * @param pDevIns The device instance.
3718 * @param pCritSect Pointer to the critical section.
3719 * @param SRC_POS Use RT_SRC_POS.
3720 * @param pszNameFmt Format string for naming the critical section.
3721 * For statistics and lock validation.
3722 * @param va Arguments for the format string.
3723 */
3724 DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3725 const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3726
3727 /**
3728 * Gets the NOP critical section.
3729 *
3730 * @returns The ring-3 address of the NOP critical section.
3731 * @param pDevIns The device instance.
3732 */
3733 DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3734
3735 /**
3736 * Gets the NOP critical section.
3737 *
3738 * @returns The ring-0 address of the NOP critical section.
3739 * @param pDevIns The device instance.
3740 * @deprecated
3741 */
3742 DECLR3CALLBACKMEMBER(R0PTRTYPE(PPDMCRITSECT), pfnCritSectGetNopR0,(PPDMDEVINS pDevIns));
3743
3744 /**
3745 * Gets the NOP critical section.
3746 *
3747 * @returns The raw-mode context address of the NOP critical section.
3748 * @param pDevIns The device instance.
3749 * @deprecated
3750 */
3751 DECLR3CALLBACKMEMBER(RCPTRTYPE(PPDMCRITSECT), pfnCritSectGetNopRC,(PPDMDEVINS pDevIns));
3752
3753 /**
3754 * Changes the device level critical section from the automatically created
3755 * default to one desired by the device constructor.
3756 *
3757 * For ring-0 and raw-mode capable devices, the call must be repeated in each of
3758 * the additional contexts.
3759 *
3760 * @returns VBox status code.
3761 * @param pDevIns The device instance.
3762 * @param pCritSect The critical section to use. NULL is not
3763 * valid, instead use the NOP critical
3764 * section.
3765 */
3766 DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3767
3768 /** @name Exported PDM Critical Section Functions
3769 * @{ */
3770 DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3771 DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3772 DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3773 DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3774 DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3775 DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3776 DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3777 DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3778 DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3779 DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3780 DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3781 DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3782 /** @} */
3783
3784 /**
3785 * Creates a PDM thread.
3786 *
3787 * This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3788 * resuming, and destroying the thread as the VM state changes.
3789 *
3790 * @returns VBox status code.
3791 * @param pDevIns The device instance.
3792 * @param ppThread Where to store the thread 'handle'.
3793 * @param pvUser The user argument to the thread function.
3794 * @param pfnThread The thread function.
3795 * @param pfnWakeup The wakup callback. This is called on the EMT
3796 * thread when a state change is pending.
3797 * @param cbStack See RTThreadCreate.
3798 * @param enmType See RTThreadCreate.
3799 * @param pszName See RTThreadCreate.
3800 * @remarks The device critical section will NOT be entered prior to invoking
3801 * the function pointers.
3802 */
3803 DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3804 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3805
3806 /** @name Exported PDM Thread Functions
3807 * @{ */
3808 DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3809 DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3810 DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3811 DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3812 DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3813 DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3814 /** @} */
3815
3816 /**
3817 * Set up asynchronous handling of a suspend, reset or power off notification.
3818 *
3819 * This shall only be called when getting the notification. It must be called
3820 * for each one.
3821 *
3822 * @returns VBox status code.
3823 * @param pDevIns The device instance.
3824 * @param pfnAsyncNotify The callback.
3825 * @thread EMT(0)
3826 * @remarks The caller will enter the device critical section prior to invoking
3827 * the callback.
3828 */
3829 DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3830
3831 /**
3832 * Notify EMT(0) that the device has completed the asynchronous notification
3833 * handling.
3834 *
3835 * This can be called at any time, spurious calls will simply be ignored.
3836 *
3837 * @param pDevIns The device instance.
3838 * @thread Any
3839 */
3840 DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
3841
3842 /**
3843 * Register the RTC device.
3844 *
3845 * @returns VBox status code.
3846 * @param pDevIns The device instance.
3847 * @param pRtcReg Pointer to a RTC registration structure.
3848 * @param ppRtcHlp Where to store the pointer to the helper
3849 * functions.
3850 */
3851 DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
3852
3853 /**
3854 * Register a PCI Bus.
3855 *
3856 * @returns VBox status code, but the positive values 0..31 are used to indicate
3857 * bus number rather than informational status codes.
3858 * @param pDevIns The device instance.
3859 * @param pPciBusReg Pointer to PCI bus registration structure.
3860 * @param ppPciHlp Where to store the pointer to the PCI Bus
3861 * helpers.
3862 * @param piBus Where to return the PDM bus number. Optional.
3863 */
3864 DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
3865 PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus));
3866
3867 /**
3868 * Register the IOMMU device.
3869 *
3870 * @returns VBox status code.
3871 * @param pDevIns The device instance.
3872 * @param pIommuReg Pointer to a IOMMU registration structure.
3873 * @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
3874 * helpers.
3875 * @param pidxIommu Where to return the IOMMU index. Optional.
3876 */
3877 DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
3878 uint32_t *pidxIommu));
3879
3880 /**
3881 * Register the PIC device.
3882 *
3883 * @returns VBox status code.
3884 * @param pDevIns The device instance.
3885 * @param pPicReg Pointer to a PIC registration structure.
3886 * @param ppPicHlp Where to store the pointer to the ring-3 PIC
3887 * helpers.
3888 * @sa PDMDevHlpPICSetUpContext
3889 */
3890 DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
3891
3892 /**
3893 * Register the APIC device.
3894 *
3895 * @returns VBox status code.
3896 * @param pDevIns The device instance.
3897 */
3898 DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
3899
3900 /**
3901 * Register the I/O APIC device.
3902 *
3903 * @returns VBox status code.
3904 * @param pDevIns The device instance.
3905 * @param pIoApicReg Pointer to a I/O APIC registration structure.
3906 * @param ppIoApicHlp Where to store the pointer to the IOAPIC
3907 * helpers.
3908 */
3909 DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
3910
3911 /**
3912 * Register the HPET device.
3913 *
3914 * @returns VBox status code.
3915 * @param pDevIns The device instance.
3916 * @param pHpetReg Pointer to a HPET registration structure.
3917 * @param ppHpetHlpR3 Where to store the pointer to the HPET
3918 * helpers.
3919 */
3920 DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
3921
3922 /**
3923 * Register a raw PCI device.
3924 *
3925 * @returns VBox status code.
3926 * @param pDevIns The device instance.
3927 * @param pPciRawReg Pointer to a raw PCI registration structure.
3928 * @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
3929 * device helpers.
3930 */
3931 DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
3932
3933 /**
3934 * Register the DMA device.
3935 *
3936 * @returns VBox status code.
3937 * @param pDevIns The device instance.
3938 * @param pDmacReg Pointer to a DMAC registration structure.
3939 * @param ppDmacHlp Where to store the pointer to the DMA helpers.
3940 */
3941 DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
3942
3943 /**
3944 * Register transfer function for DMA channel.
3945 *
3946 * @returns VBox status code.
3947 * @param pDevIns The device instance.
3948 * @param uChannel Channel number.
3949 * @param pfnTransferHandler Device specific transfer callback function.
3950 * @param pvUser User pointer to pass to the callback.
3951 * @thread EMT
3952 */
3953 DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
3954
3955 /**
3956 * Read memory.
3957 *
3958 * @returns VBox status code.
3959 * @param pDevIns The device instance.
3960 * @param uChannel Channel number.
3961 * @param pvBuffer Pointer to target buffer.
3962 * @param off DMA position.
3963 * @param cbBlock Block size.
3964 * @param pcbRead Where to store the number of bytes which was
3965 * read. optional.
3966 * @thread EMT
3967 */
3968 DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead));
3969
3970 /**
3971 * Write memory.
3972 *
3973 * @returns VBox status code.
3974 * @param pDevIns The device instance.
3975 * @param uChannel Channel number.
3976 * @param pvBuffer Memory to write.
3977 * @param off DMA position.
3978 * @param cbBlock Block size.
3979 * @param pcbWritten Where to store the number of bytes which was
3980 * written. optional.
3981 * @thread EMT
3982 */
3983 DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten));
3984
3985 /**
3986 * Set the DREQ line.
3987 *
3988 * @returns VBox status code.
3989 * @param pDevIns Device instance.
3990 * @param uChannel Channel number.
3991 * @param uLevel Level of the line.
3992 * @thread EMT
3993 */
3994 DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
3995
3996 /**
3997 * Get channel mode.
3998 *
3999 * @returns Channel mode. See specs.
4000 * @param pDevIns The device instance.
4001 * @param uChannel Channel number.
4002 * @thread EMT
4003 */
4004 DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4005
4006 /**
4007 * Schedule DMA execution.
4008 *
4009 * @param pDevIns The device instance.
4010 * @thread Any thread.
4011 */
4012 DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4013
4014 /**
4015 * Write CMOS value and update the checksum(s).
4016 *
4017 * @returns VBox status code.
4018 * @param pDevIns The device instance.
4019 * @param iReg The CMOS register index.
4020 * @param u8Value The CMOS register value.
4021 * @thread EMT
4022 */
4023 DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4024
4025 /**
4026 * Read CMOS value.
4027 *
4028 * @returns VBox status code.
4029 * @param pDevIns The device instance.
4030 * @param iReg The CMOS register index.
4031 * @param pu8Value Where to store the CMOS register value.
4032 * @thread EMT
4033 */
4034 DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4035
4036 /**
4037 * Assert that the current thread is the emulation thread.
4038 *
4039 * @returns True if correct.
4040 * @returns False if wrong.
4041 * @param pDevIns The device instance.
4042 * @param pszFile Filename of the assertion location.
4043 * @param iLine The linenumber of the assertion location.
4044 * @param pszFunction Function of the assertion location.
4045 */
4046 DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction));
4047
4048 /**
4049 * Assert that the current thread is NOT the emulation thread.
4050 *
4051 * @returns True if correct.
4052 * @returns False if wrong.
4053 * @param pDevIns The device instance.
4054 * @param pszFile Filename of the assertion location.
4055 * @param iLine The linenumber of the assertion location.
4056 * @param pszFunction Function of the assertion location.
4057 */
4058 DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction));
4059
4060 /**
4061 * Resolves the symbol for a raw-mode context interface.
4062 *
4063 * @returns VBox status code.
4064 * @param pDevIns The device instance.
4065 * @param pvInterface The interface structure.
4066 * @param cbInterface The size of the interface structure.
4067 * @param pszSymPrefix What to prefix the symbols in the list with
4068 * before resolving them. This must start with
4069 * 'dev' and contain the driver name.
4070 * @param pszSymList List of symbols corresponding to the interface.
4071 * There is generally a there is generally a define
4072 * holding this list associated with the interface
4073 * definition (INTERFACE_SYM_LIST). For more
4074 * details see PDMR3LdrGetInterfaceSymbols.
4075 * @thread EMT
4076 */
4077 DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4078 const char *pszSymPrefix, const char *pszSymList));
4079
4080 /**
4081 * Resolves the symbol for a ring-0 context interface.
4082 *
4083 * @returns VBox status code.
4084 * @param pDevIns The device instance.
4085 * @param pvInterface The interface structure.
4086 * @param cbInterface The size of the interface structure.
4087 * @param pszSymPrefix What to prefix the symbols in the list with
4088 * before resolving them. This must start with
4089 * 'dev' and contain the driver name.
4090 * @param pszSymList List of symbols corresponding to the interface.
4091 * There is generally a there is generally a define
4092 * holding this list associated with the interface
4093 * definition (INTERFACE_SYM_LIST). For more
4094 * details see PDMR3LdrGetInterfaceSymbols.
4095 * @thread EMT
4096 */
4097 DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4098 const char *pszSymPrefix, const char *pszSymList));
4099
4100 /**
4101 * Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4102 *
4103 * @returns VBox status code.
4104 * @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4105 * @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4106 *
4107 * @param pDevIns The device instance.
4108 * @param uOperation The operation to perform.
4109 * @param u64Arg 64-bit integer argument.
4110 * @thread EMT
4111 */
4112 DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4113
4114 /**
4115 * Gets the reason for the most recent VM suspend.
4116 *
4117 * @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4118 * suspend has been made or if the pDevIns is invalid.
4119 * @param pDevIns The device instance.
4120 */
4121 DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4122
4123 /**
4124 * Gets the reason for the most recent VM resume.
4125 *
4126 * @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4127 * resume has been made or if the pDevIns is invalid.
4128 * @param pDevIns The device instance.
4129 */
4130 DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4131
4132 /**
4133 * Requests the mapping of multiple guest page into ring-3.
4134 *
4135 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4136 * ASAP to release them.
4137 *
4138 * This API will assume your intention is to write to the pages, and will
4139 * therefore replace shared and zero pages. If you do not intend to modify the
4140 * pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4141 *
4142 * @returns VBox status code.
4143 * @retval VINF_SUCCESS on success.
4144 * @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4145 * backing or if any of the pages the page has any active access
4146 * handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4147 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4148 * an invalid physical address.
4149 *
4150 * @param pDevIns The device instance.
4151 * @param cPages Number of pages to lock.
4152 * @param paGCPhysPages The guest physical address of the pages that
4153 * should be mapped (@a cPages entries).
4154 * @param fFlags Flags reserved for future use, MBZ.
4155 * @param papvPages Where to store the ring-3 mapping addresses
4156 * corresponding to @a paGCPhysPages.
4157 * @param paLocks Where to store the locking information that
4158 * pfnPhysBulkReleasePageMappingLock needs (@a cPages
4159 * in length).
4160 *
4161 * @remark Avoid calling this API from within critical sections (other than the
4162 * PGM one) because of the deadlock risk when we have to delegating the
4163 * task to an EMT.
4164 * @thread Any.
4165 * @since 6.0.6
4166 */
4167 DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4168 uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4169
4170 /**
4171 * Requests the mapping of multiple guest page into ring-3, for reading only.
4172 *
4173 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4174 * ASAP to release them.
4175 *
4176 * @returns VBox status code.
4177 * @retval VINF_SUCCESS on success.
4178 * @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4179 * backing or if any of the pages the page has an active ALL access
4180 * handler. The caller must fall back on using PGMR3PhysWriteExternal.
4181 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4182 * an invalid physical address.
4183 *
4184 * @param pDevIns The device instance.
4185 * @param cPages Number of pages to lock.
4186 * @param paGCPhysPages The guest physical address of the pages that
4187 * should be mapped (@a cPages entries).
4188 * @param fFlags Flags reserved for future use, MBZ.
4189 * @param papvPages Where to store the ring-3 mapping addresses
4190 * corresponding to @a paGCPhysPages.
4191 * @param paLocks Where to store the lock information that
4192 * pfnPhysReleasePageMappingLock needs (@a cPages
4193 * in length).
4194 *
4195 * @remark Avoid calling this API from within critical sections.
4196 * @thread Any.
4197 * @since 6.0.6
4198 */
4199 DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4200 uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4201
4202 /**
4203 * Release the mappings of multiple guest pages.
4204 *
4205 * This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4206 * pfnPhysBulkGCPhys2CCPtrReadOnly.
4207 *
4208 * @param pDevIns The device instance.
4209 * @param cPages Number of pages to unlock.
4210 * @param paLocks The lock structures initialized by the mapping
4211 * function (@a cPages in length).
4212 * @thread Any.
4213 * @since 6.0.6
4214 */
4215 DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4216
4217 /**
4218 * Returns the micro architecture used for the guest.
4219 *
4220 * @returns CPU micro architecture enum.
4221 * @param pDevIns The device instance.
4222 */
4223 DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4224
4225 /** Space reserved for future members.
4226 * @{ */
4227 DECLR3CALLBACKMEMBER(void, pfnReserved1,(void));
4228 DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4229 DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4230 DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4231 DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4232 DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4233 DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4234 DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4235 DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4236 DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4237 /** @} */
4238
4239
4240 /** API available to trusted devices only.
4241 *
4242 * These APIs are providing unrestricted access to the guest and the VM,
4243 * or they are interacting intimately with PDM.
4244 *
4245 * @{
4246 */
4247
4248 /**
4249 * Gets the user mode VM handle. Restricted API.
4250 *
4251 * @returns User mode VM Handle.
4252 * @param pDevIns The device instance.
4253 */
4254 DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4255
4256 /**
4257 * Gets the global VM handle. Restricted API.
4258 *
4259 * @returns VM Handle.
4260 * @param pDevIns The device instance.
4261 */
4262 DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4263
4264 /**
4265 * Gets the VMCPU handle. Restricted API.
4266 *
4267 * @returns VMCPU Handle.
4268 * @param pDevIns The device instance.
4269 */
4270 DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4271
4272 /**
4273 * The the VM CPU ID of the current thread (restricted API).
4274 *
4275 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4276 * @param pDevIns The device instance.
4277 */
4278 DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4279
4280 /**
4281 * Registers the VMM device heap or notifies about mapping/unmapping.
4282 *
4283 * This interface serves three purposes:
4284 *
4285 * -# Register the VMM device heap during device construction
4286 * for the HM to use.
4287 * -# Notify PDM/HM that it's mapped into guest address
4288 * space (i.e. usable).
4289 * -# Notify PDM/HM that it is being unmapped from the guest
4290 * address space (i.e. not usable).
4291 *
4292 * @returns VBox status code.
4293 * @param pDevIns The device instance.
4294 * @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4295 * not mapped.
4296 * @param pvHeap Ring 3 heap pointer.
4297 * @param cbHeap Size of the heap.
4298 * @thread EMT.
4299 */
4300 DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4301
4302 /**
4303 * Registers the firmware (BIOS, EFI) device with PDM.
4304 *
4305 * The firmware provides a callback table and gets a special PDM helper table.
4306 * There can only be one firmware device for a VM.
4307 *
4308 * @returns VBox status code.
4309 * @param pDevIns The device instance.
4310 * @param pFwReg Firmware registration structure.
4311 * @param ppFwHlp Where to return the firmware helper structure.
4312 * @remarks Only valid during device construction.
4313 * @thread EMT(0)
4314 */
4315 DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4316
4317 /**
4318 * Resets the VM.
4319 *
4320 * @returns The appropriate VBox status code to pass around on reset.
4321 * @param pDevIns The device instance.
4322 * @param fFlags PDMVMRESET_F_XXX flags.
4323 * @thread The emulation thread.
4324 */
4325 DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4326
4327 /**
4328 * Suspends the VM.
4329 *
4330 * @returns The appropriate VBox status code to pass around on suspend.
4331 * @param pDevIns The device instance.
4332 * @thread The emulation thread.
4333 */
4334 DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4335
4336 /**
4337 * Suspends, saves and powers off the VM.
4338 *
4339 * @returns The appropriate VBox status code to pass around.
4340 * @param pDevIns The device instance.
4341 * @thread An emulation thread.
4342 */
4343 DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4344
4345 /**
4346 * Power off the VM.
4347 *
4348 * @returns The appropriate VBox status code to pass around on power off.
4349 * @param pDevIns The device instance.
4350 * @thread The emulation thread.
4351 */
4352 DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4353
4354 /**
4355 * Checks if the Gate A20 is enabled or not.
4356 *
4357 * @returns true if A20 is enabled.
4358 * @returns false if A20 is disabled.
4359 * @param pDevIns The device instance.
4360 * @thread The emulation thread.
4361 */
4362 DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4363
4364 /**
4365 * Enables or disables the Gate A20.
4366 *
4367 * @param pDevIns The device instance.
4368 * @param fEnable Set this flag to enable the Gate A20; clear it
4369 * to disable.
4370 * @thread The emulation thread.
4371 */
4372 DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4373
4374 /**
4375 * Get the specified CPUID leaf for the virtual CPU associated with the calling
4376 * thread.
4377 *
4378 * @param pDevIns The device instance.
4379 * @param iLeaf The CPUID leaf to get.
4380 * @param pEax Where to store the EAX value.
4381 * @param pEbx Where to store the EBX value.
4382 * @param pEcx Where to store the ECX value.
4383 * @param pEdx Where to store the EDX value.
4384 * @thread EMT.
4385 */
4386 DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx));
4387
4388 /**
4389 * Get the current virtual clock time in a VM. The clock frequency must be
4390 * queried separately.
4391 *
4392 * @returns Current clock time.
4393 * @param pDevIns The device instance.
4394 */
4395 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4396
4397 /**
4398 * Get the frequency of the virtual clock.
4399 *
4400 * @returns The clock frequency (not variable at run-time).
4401 * @param pDevIns The device instance.
4402 */
4403 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4404
4405 /**
4406 * Get the current virtual clock time in a VM, in nanoseconds.
4407 *
4408 * @returns Current clock time (in ns).
4409 * @param pDevIns The device instance.
4410 */
4411 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4412
4413 /**
4414 * Gets the support driver session.
4415 *
4416 * This is intended for working with the semaphore API.
4417 *
4418 * @returns Support driver session handle.
4419 * @param pDevIns The device instance.
4420 */
4421 DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4422
4423 /**
4424 * Queries a generic object from the VMM user.
4425 *
4426 * @returns Pointer to the object if found, NULL if not.
4427 * @param pDevIns The device instance.
4428 * @param pUuid The UUID of what's being queried. The UUIDs and
4429 * the usage conventions are defined by the user.
4430 *
4431 * @note It is strictly forbidden to call this internally in VBox! This
4432 * interface is exclusively for hacks in externally developed devices.
4433 */
4434 DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4435
4436 /**
4437 * Register a physical page access handler type.
4438 *
4439 * @returns VBox status code.
4440 * @param pDevIns The device instance.
4441 * @param enmKind The kind of access handler.
4442 * @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4443 * @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4444 * handler should be called.
4445 * @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4446 * ring-3 handler should be called.
4447 * @param pszHandlerRC The name of the raw-mode context handler, NULL if
4448 * the ring-3 handler should be called.
4449 * @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4450 * if the ring-3 handler should be called.
4451 * @param pszDesc The type description.
4452 * @param phType Where to return the type handle (cross context
4453 * safe).
4454 */
4455 DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4456 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4457 const char *pszHandlerR0, const char *pszPfHandlerR0,
4458 const char *pszHandlerRC, const char *pszPfHandlerRC,
4459 const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4460
4461 /** @} */
4462
4463 /** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4464 uint32_t u32TheEnd;
4465} PDMDEVHLPR3;
4466#endif /* !IN_RING3 || DOXYGEN_RUNNING */
4467/** Pointer to the R3 PDM Device API. */
4468typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4469/** Pointer to the R3 PDM Device API, const variant. */
4470typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4471
4472
4473/**
4474 * PDM Device API - RC Variant.
4475 */
4476typedef struct PDMDEVHLPRC
4477{
4478 /** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4479 uint32_t u32Version;
4480
4481 /**
4482 * Sets up raw-mode context callback handlers for an I/O port range.
4483 *
4484 * The range must have been registered in ring-3 first using
4485 * PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4486 *
4487 * @returns VBox status.
4488 * @param pDevIns The device instance to register the ports with.
4489 * @param hIoPorts The I/O port range handle.
4490 * @param pfnOut Pointer to function which is gonna handle OUT
4491 * operations. Optional.
4492 * @param pfnIn Pointer to function which is gonna handle IN operations.
4493 * Optional.
4494 * @param pfnOutStr Pointer to function which is gonna handle string OUT
4495 * operations. Optional.
4496 * @param pfnInStr Pointer to function which is gonna handle string IN
4497 * operations. Optional.
4498 * @param pvUser User argument to pass to the callbacks.
4499 *
4500 * @remarks Caller enters the device critical section prior to invoking the
4501 * registered callback methods.
4502 *
4503 * @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4504 * PDMDevHlpIoPortUnmap.
4505 */
4506 DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4507 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4508 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4509 void *pvUser));
4510
4511 /**
4512 * Sets up raw-mode context callback handlers for an MMIO region.
4513 *
4514 * The region must have been registered in ring-3 first using
4515 * PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4516 *
4517 * @returns VBox status.
4518 * @param pDevIns The device instance to register the ports with.
4519 * @param hRegion The MMIO region handle.
4520 * @param pfnWrite Pointer to function which is gonna handle Write
4521 * operations.
4522 * @param pfnRead Pointer to function which is gonna handle Read
4523 * operations.
4524 * @param pfnFill Pointer to function which is gonna handle Fill/memset
4525 * operations. (optional)
4526 * @param pvUser User argument to pass to the callbacks.
4527 *
4528 * @remarks Caller enters the device critical section prior to invoking the
4529 * registered callback methods.
4530 *
4531 * @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4532 * PDMDevHlpMmioUnmap.
4533 */
4534 DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4535 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4536
4537 /**
4538 * Sets up a raw-mode mapping for an MMIO2 region.
4539 *
4540 * The region must have been created in ring-3 first using
4541 * PDMDevHlpMmio2Create().
4542 *
4543 * @returns VBox status.
4544 * @param pDevIns The device instance to register the ports with.
4545 * @param hRegion The MMIO2 region handle.
4546 * @param offSub Start of what to map into raw-mode. Must be page aligned.
4547 * @param cbSub Number of bytes to map into raw-mode. Must be page
4548 * aligned. Zero is an alias for everything.
4549 * @param ppvMapping Where to return the mapping corresponding to @a offSub.
4550 * @thread EMT(0)
4551 * @note Only available at VM creation time.
4552 *
4553 * @sa PDMDevHlpMmio2Create().
4554 */
4555 DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4556 size_t offSub, size_t cbSub, void **ppvMapping));
4557
4558 /**
4559 * Bus master physical memory read from the given PCI device.
4560 *
4561 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4562 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
4563 * @param pDevIns The device instance.
4564 * @param pPciDev The PCI device structure. If NULL the default
4565 * PCI device for this device instance is used.
4566 * @param GCPhys Physical address start reading from.
4567 * @param pvBuf Where to put the read bits.
4568 * @param cbRead How many bytes to read.
4569 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4570 * @thread Any thread, but the call may involve the emulation thread.
4571 */
4572 DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4573 void *pvBuf, size_t cbRead, uint32_t fFlags));
4574
4575 /**
4576 * Bus master physical memory write from the given PCI device.
4577 *
4578 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4579 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
4580 * @param pDevIns The device instance.
4581 * @param pPciDev The PCI device structure. If NULL the default
4582 * PCI device for this device instance is used.
4583 * @param GCPhys Physical address to write to.
4584 * @param pvBuf What to write.
4585 * @param cbWrite How many bytes to write.
4586 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4587 * @thread Any thread, but the call may involve the emulation thread.
4588 */
4589 DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4590 const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4591
4592 /**
4593 * Set the IRQ for the given PCI device.
4594 *
4595 * @param pDevIns Device instance.
4596 * @param pPciDev The PCI device structure. If NULL the default
4597 * PCI device for this device instance is used.
4598 * @param iIrq IRQ number to set.
4599 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4600 * @thread Any thread, but will involve the emulation thread.
4601 */
4602 DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4603
4604 /**
4605 * Set ISA IRQ for a device.
4606 *
4607 * @param pDevIns Device instance.
4608 * @param iIrq IRQ number to set.
4609 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4610 * @thread Any thread, but will involve the emulation thread.
4611 */
4612 DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4613
4614 /**
4615 * Read physical memory.
4616 *
4617 * @returns VINF_SUCCESS (for now).
4618 * @param pDevIns Device instance.
4619 * @param GCPhys Physical address start reading from.
4620 * @param pvBuf Where to put the read bits.
4621 * @param cbRead How many bytes to read.
4622 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4623 */
4624 DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
4625
4626 /**
4627 * Write to physical memory.
4628 *
4629 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4630 * @param pDevIns Device instance.
4631 * @param GCPhys Physical address to write to.
4632 * @param pvBuf What to write.
4633 * @param cbWrite How many bytes to write.
4634 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4635 */
4636 DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4637
4638 /**
4639 * Checks if the Gate A20 is enabled or not.
4640 *
4641 * @returns true if A20 is enabled.
4642 * @returns false if A20 is disabled.
4643 * @param pDevIns Device instance.
4644 * @thread The emulation thread.
4645 */
4646 DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4647
4648 /**
4649 * Gets the VM state.
4650 *
4651 * @returns VM state.
4652 * @param pDevIns The device instance.
4653 * @thread Any thread (just keep in mind that it's volatile info).
4654 */
4655 DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4656
4657 /**
4658 * Set the VM error message
4659 *
4660 * @returns rc.
4661 * @param pDevIns Driver instance.
4662 * @param rc VBox status code.
4663 * @param SRC_POS Use RT_SRC_POS.
4664 * @param pszFormat Error message format string.
4665 * @param ... Error message arguments.
4666 */
4667 DECLRCCALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4668 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4669
4670 /**
4671 * Set the VM error message
4672 *
4673 * @returns rc.
4674 * @param pDevIns Driver instance.
4675 * @param rc VBox status code.
4676 * @param SRC_POS Use RT_SRC_POS.
4677 * @param pszFormat Error message format string.
4678 * @param va Error message arguments.
4679 */
4680 DECLRCCALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4681 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4682
4683 /**
4684 * Set the VM runtime error message
4685 *
4686 * @returns VBox status code.
4687 * @param pDevIns Device instance.
4688 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4689 * @param pszErrorId Error ID string.
4690 * @param pszFormat Error message format string.
4691 * @param ... Error message arguments.
4692 */
4693 DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4694 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4695
4696 /**
4697 * Set the VM runtime error message
4698 *
4699 * @returns VBox status code.
4700 * @param pDevIns Device instance.
4701 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4702 * @param pszErrorId Error ID string.
4703 * @param pszFormat Error message format string.
4704 * @param va Error message arguments.
4705 */
4706 DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4707 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
4708
4709 /**
4710 * Gets the VM handle. Restricted API.
4711 *
4712 * @returns VM Handle.
4713 * @param pDevIns Device instance.
4714 */
4715 DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4716
4717 /**
4718 * Gets the VMCPU handle. Restricted API.
4719 *
4720 * @returns VMCPU Handle.
4721 * @param pDevIns The device instance.
4722 */
4723 DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4724
4725 /**
4726 * The the VM CPU ID of the current thread (restricted API).
4727 *
4728 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4729 * @param pDevIns The device instance.
4730 */
4731 DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4732
4733 /**
4734 * Get the current virtual clock time in a VM. The clock frequency must be
4735 * queried separately.
4736 *
4737 * @returns Current clock time.
4738 * @param pDevIns The device instance.
4739 */
4740 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4741
4742 /**
4743 * Get the frequency of the virtual clock.
4744 *
4745 * @returns The clock frequency (not variable at run-time).
4746 * @param pDevIns The device instance.
4747 */
4748 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4749
4750 /**
4751 * Get the current virtual clock time in a VM, in nanoseconds.
4752 *
4753 * @returns Current clock time (in ns).
4754 * @param pDevIns The device instance.
4755 */
4756 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4757
4758 /**
4759 * Gets the NOP critical section.
4760 *
4761 * @returns The ring-3 address of the NOP critical section.
4762 * @param pDevIns The device instance.
4763 */
4764 DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4765
4766 /**
4767 * Changes the device level critical section from the automatically created
4768 * default to one desired by the device constructor.
4769 *
4770 * Must first be done in ring-3.
4771 *
4772 * @returns VBox status code.
4773 * @param pDevIns The device instance.
4774 * @param pCritSect The critical section to use. NULL is not
4775 * valid, instead use the NOP critical
4776 * section.
4777 */
4778 DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4779
4780 /** @name Exported PDM Critical Section Functions
4781 * @{ */
4782 DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4783 DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4784 DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4785 DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4786 DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4787 DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4788 DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4789 DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4790 DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4791 /** @} */
4792
4793 /**
4794 * Gets the trace buffer handle.
4795 *
4796 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4797 * really inteded for direct usage, thus no inline wrapper function.
4798 *
4799 * @returns Trace buffer handle or NIL_RTTRACEBUF.
4800 * @param pDevIns The device instance.
4801 */
4802 DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4803
4804 /**
4805 * Sets up the PCI bus for the raw-mode context.
4806 *
4807 * This must be called after ring-3 has registered the PCI bus using
4808 * PDMDevHlpPCIBusRegister().
4809 *
4810 * @returns VBox status code.
4811 * @param pDevIns The device instance.
4812 * @param pPciBusReg The PCI bus registration information for raw-mode,
4813 * considered volatile.
4814 * @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4815 */
4816 DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4817
4818 /**
4819 * Sets up the IOMMU for the raw-mode context.
4820 *
4821 * This must be called after ring-3 has registered the IOMMU using
4822 * PDMDevHlpIommuRegister().
4823 *
4824 * @returns VBox status code.
4825 * @param pDevIns The device instance.
4826 * @param pIommuReg The IOMMU registration information for raw-mode,
4827 * considered volatile.
4828 * @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
4829 */
4830 DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
4831
4832 /**
4833 * Sets up the PIC for the ring-0 context.
4834 *
4835 * This must be called after ring-3 has registered the PIC using
4836 * PDMDevHlpPICRegister().
4837 *
4838 * @returns VBox status code.
4839 * @param pDevIns The device instance.
4840 * @param pPicReg The PIC registration information for ring-0,
4841 * considered volatile and copied.
4842 * @param ppPicHlp Where to return the ring-0 PIC helpers.
4843 */
4844 DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4845
4846 /**
4847 * Sets up the APIC for the raw-mode context.
4848 *
4849 * This must be called after ring-3 has registered the APIC using
4850 * PDMDevHlpApicRegister().
4851 *
4852 * @returns VBox status code.
4853 * @param pDevIns The device instance.
4854 */
4855 DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
4856
4857 /**
4858 * Sets up the IOAPIC for the ring-0 context.
4859 *
4860 * This must be called after ring-3 has registered the PIC using
4861 * PDMDevHlpIoApicRegister().
4862 *
4863 * @returns VBox status code.
4864 * @param pDevIns The device instance.
4865 * @param pIoApicReg The PIC registration information for ring-0,
4866 * considered volatile and copied.
4867 * @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
4868 */
4869 DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4870
4871 /**
4872 * Sets up the HPET for the raw-mode context.
4873 *
4874 * This must be called after ring-3 has registered the PIC using
4875 * PDMDevHlpHpetRegister().
4876 *
4877 * @returns VBox status code.
4878 * @param pDevIns The device instance.
4879 * @param pHpetReg The PIC registration information for raw-mode,
4880 * considered volatile and copied.
4881 * @param ppHpetHlp Where to return the raw-mode HPET helpers.
4882 */
4883 DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
4884
4885 /** Space reserved for future members.
4886 * @{ */
4887 DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
4888 DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
4889 DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
4890 DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
4891 DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
4892 DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
4893 DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
4894 DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
4895 DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
4896 DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
4897 /** @} */
4898
4899 /** Just a safety precaution. */
4900 uint32_t u32TheEnd;
4901} PDMDEVHLPRC;
4902/** Pointer PDM Device RC API. */
4903typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
4904/** Pointer PDM Device RC API. */
4905typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
4906
4907/** Current PDMDEVHLP version number. */
4908#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 16, 0)
4909
4910
4911/**
4912 * PDM Device API - R0 Variant.
4913 */
4914typedef struct PDMDEVHLPR0
4915{
4916 /** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
4917 uint32_t u32Version;
4918
4919 /**
4920 * Sets up ring-0 callback handlers for an I/O port range.
4921 *
4922 * The range must have been created in ring-3 first using
4923 * PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4924 *
4925 * @returns VBox status.
4926 * @param pDevIns The device instance to register the ports with.
4927 * @param hIoPorts The I/O port range handle.
4928 * @param pfnOut Pointer to function which is gonna handle OUT
4929 * operations. Optional.
4930 * @param pfnIn Pointer to function which is gonna handle IN operations.
4931 * Optional.
4932 * @param pfnOutStr Pointer to function which is gonna handle string OUT
4933 * operations. Optional.
4934 * @param pfnInStr Pointer to function which is gonna handle string IN
4935 * operations. Optional.
4936 * @param pvUser User argument to pass to the callbacks.
4937 *
4938 * @remarks Caller enters the device critical section prior to invoking the
4939 * registered callback methods.
4940 *
4941 * @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
4942 * PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
4943 */
4944 DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4945 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4946 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4947 void *pvUser));
4948
4949 /**
4950 * Sets up ring-0 callback handlers for an MMIO region.
4951 *
4952 * The region must have been created in ring-3 first using
4953 * PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
4954 * PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
4955 *
4956 * @returns VBox status.
4957 * @param pDevIns The device instance to register the ports with.
4958 * @param hRegion The MMIO region handle.
4959 * @param pfnWrite Pointer to function which is gonna handle Write
4960 * operations.
4961 * @param pfnRead Pointer to function which is gonna handle Read
4962 * operations.
4963 * @param pfnFill Pointer to function which is gonna handle Fill/memset
4964 * operations. (optional)
4965 * @param pvUser User argument to pass to the callbacks.
4966 *
4967 * @remarks Caller enters the device critical section prior to invoking the
4968 * registered callback methods.
4969 *
4970 * @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
4971 * PDMDevHlpMmioUnmap().
4972 */
4973 DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4974 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4975
4976 /**
4977 * Sets up a ring-0 mapping for an MMIO2 region.
4978 *
4979 * The region must have been created in ring-3 first using
4980 * PDMDevHlpMmio2Create().
4981 *
4982 * @returns VBox status.
4983 * @param pDevIns The device instance to register the ports with.
4984 * @param hRegion The MMIO2 region handle.
4985 * @param offSub Start of what to map into ring-0. Must be page aligned.
4986 * @param cbSub Number of bytes to map into ring-0. Must be page
4987 * aligned. Zero is an alias for everything.
4988 * @param ppvMapping Where to return the mapping corresponding to @a offSub.
4989 *
4990 * @thread EMT(0)
4991 * @note Only available at VM creation time.
4992 *
4993 * @sa PDMDevHlpMmio2Create().
4994 */
4995 DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
4996 void **ppvMapping));
4997
4998 /**
4999 * Bus master physical memory read from the given PCI device.
5000 *
5001 * @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5002 * VERR_EM_MEMORY.
5003 * @param pDevIns The device instance.
5004 * @param pPciDev The PCI device structure. If NULL the default
5005 * PCI device for this device instance is used.
5006 * @param GCPhys Physical address start reading from.
5007 * @param pvBuf Where to put the read bits.
5008 * @param cbRead How many bytes to read.
5009 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5010 * @thread Any thread, but the call may involve the emulation thread.
5011 */
5012 DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5013 void *pvBuf, size_t cbRead, uint32_t fFlags));
5014
5015 /**
5016 * Bus master physical memory write from the given PCI device.
5017 *
5018 * @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5019 * VERR_EM_MEMORY.
5020 * @param pDevIns The device instance.
5021 * @param pPciDev The PCI device structure. If NULL the default
5022 * PCI device for this device instance is used.
5023 * @param GCPhys Physical address to write to.
5024 * @param pvBuf What to write.
5025 * @param cbWrite How many bytes to write.
5026 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5027 * @thread Any thread, but the call may involve the emulation thread.
5028 */
5029 DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5030 const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5031
5032 /**
5033 * Set the IRQ for the given PCI device.
5034 *
5035 * @param pDevIns Device instance.
5036 * @param pPciDev The PCI device structure. If NULL the default
5037 * PCI device for this device instance is used.
5038 * @param iIrq IRQ number to set.
5039 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5040 * @thread Any thread, but will involve the emulation thread.
5041 */
5042 DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5043
5044 /**
5045 * Set ISA IRQ for a device.
5046 *
5047 * @param pDevIns Device instance.
5048 * @param iIrq IRQ number to set.
5049 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5050 * @thread Any thread, but will involve the emulation thread.
5051 */
5052 DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5053
5054 /**
5055 * Read physical memory.
5056 *
5057 * @returns VINF_SUCCESS (for now).
5058 * @param pDevIns Device instance.
5059 * @param GCPhys Physical address start reading from.
5060 * @param pvBuf Where to put the read bits.
5061 * @param cbRead How many bytes to read.
5062 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5063 */
5064 DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5065
5066 /**
5067 * Write to physical memory.
5068 *
5069 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5070 * @param pDevIns Device instance.
5071 * @param GCPhys Physical address to write to.
5072 * @param pvBuf What to write.
5073 * @param cbWrite How many bytes to write.
5074 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5075 */
5076 DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5077
5078 /**
5079 * Checks if the Gate A20 is enabled or not.
5080 *
5081 * @returns true if A20 is enabled.
5082 * @returns false if A20 is disabled.
5083 * @param pDevIns Device instance.
5084 * @thread The emulation thread.
5085 */
5086 DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5087
5088 /**
5089 * Gets the VM state.
5090 *
5091 * @returns VM state.
5092 * @param pDevIns The device instance.
5093 * @thread Any thread (just keep in mind that it's volatile info).
5094 */
5095 DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5096
5097 /**
5098 * Set the VM error message
5099 *
5100 * @returns rc.
5101 * @param pDevIns Driver instance.
5102 * @param rc VBox status code.
5103 * @param SRC_POS Use RT_SRC_POS.
5104 * @param pszFormat Error message format string.
5105 * @param ... Error message arguments.
5106 */
5107 DECLR0CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5108 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
5109
5110 /**
5111 * Set the VM error message
5112 *
5113 * @returns rc.
5114 * @param pDevIns Driver instance.
5115 * @param rc VBox status code.
5116 * @param SRC_POS Use RT_SRC_POS.
5117 * @param pszFormat Error message format string.
5118 * @param va Error message arguments.
5119 */
5120 DECLR0CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5121 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
5122
5123 /**
5124 * Set the VM runtime error message
5125 *
5126 * @returns VBox status code.
5127 * @param pDevIns Device instance.
5128 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5129 * @param pszErrorId Error ID string.
5130 * @param pszFormat Error message format string.
5131 * @param ... Error message arguments.
5132 */
5133 DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5134 const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
5135
5136 /**
5137 * Set the VM runtime error message
5138 *
5139 * @returns VBox status code.
5140 * @param pDevIns Device instance.
5141 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5142 * @param pszErrorId Error ID string.
5143 * @param pszFormat Error message format string.
5144 * @param va Error message arguments.
5145 */
5146 DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5147 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
5148
5149 /**
5150 * Gets the VM handle. Restricted API.
5151 *
5152 * @returns VM Handle.
5153 * @param pDevIns Device instance.
5154 */
5155 DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5156
5157 /**
5158 * Gets the VMCPU handle. Restricted API.
5159 *
5160 * @returns VMCPU Handle.
5161 * @param pDevIns The device instance.
5162 */
5163 DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5164
5165 /**
5166 * The the VM CPU ID of the current thread (restricted API).
5167 *
5168 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5169 * @param pDevIns The device instance.
5170 */
5171 DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5172
5173 /**
5174 * Translates a timer handle to a pointer.
5175 *
5176 * @returns The time address.
5177 * @param pDevIns The device instance.
5178 * @param hTimer The timer handle.
5179 */
5180 DECLR0CALLBACKMEMBER(PTMTIMERR0, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5181
5182 /** @name Timer handle method wrappers
5183 * @{ */
5184 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5185 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5186 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5187 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5188 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5189 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5190 DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5191 DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5192 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5193 /** Takes the clock lock then enters the specified critical section. */
5194 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5195 DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5196 DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5197 DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5198 DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5199 DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5200 DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5201 DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5202 DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5203 DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5204 /** @} */
5205
5206 /**
5207 * Get the current virtual clock time in a VM. The clock frequency must be
5208 * queried separately.
5209 *
5210 * @returns Current clock time.
5211 * @param pDevIns The device instance.
5212 */
5213 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5214
5215 /**
5216 * Get the frequency of the virtual clock.
5217 *
5218 * @returns The clock frequency (not variable at run-time).
5219 * @param pDevIns The device instance.
5220 */
5221 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5222
5223 /**
5224 * Get the current virtual clock time in a VM, in nanoseconds.
5225 *
5226 * @returns Current clock time (in ns).
5227 * @param pDevIns The device instance.
5228 */
5229 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5230
5231 /** @name Exported PDM Queue Functions
5232 * @{ */
5233 DECLR0CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5234 DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5235 DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5236 DECLR0CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
5237 DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5238 /** @} */
5239
5240 /** @name PDM Task
5241 * @{ */
5242 /**
5243 * Triggers the running the given task.
5244 *
5245 * @returns VBox status code.
5246 * @retval VINF_ALREADY_POSTED is the task is already pending.
5247 * @param pDevIns The device instance.
5248 * @param hTask The task to trigger.
5249 * @thread Any thread.
5250 */
5251 DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5252 /** @} */
5253
5254 /** @name SUP Event Semaphore Wrappers (single release / auto reset)
5255 * These semaphores can be signalled from ring-0.
5256 * @{ */
5257 /** @sa SUPSemEventSignal */
5258 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5259 /** @sa SUPSemEventWaitNoResume */
5260 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5261 /** @sa SUPSemEventWaitNsAbsIntr */
5262 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5263 /** @sa SUPSemEventWaitNsRelIntr */
5264 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5265 /** @sa SUPSemEventGetResolution */
5266 DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5267 /** @} */
5268
5269 /** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5270 * These semaphores can be signalled from ring-0.
5271 * @{ */
5272 /** @sa SUPSemEventMultiSignal */
5273 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5274 /** @sa SUPSemEventMultiReset */
5275 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5276 /** @sa SUPSemEventMultiWaitNoResume */
5277 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5278 /** @sa SUPSemEventMultiWaitNsAbsIntr */
5279 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5280 /** @sa SUPSemEventMultiWaitNsRelIntr */
5281 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5282 /** @sa SUPSemEventMultiGetResolution */
5283 DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5284 /** @} */
5285
5286 /**
5287 * Gets the NOP critical section.
5288 *
5289 * @returns The ring-3 address of the NOP critical section.
5290 * @param pDevIns The device instance.
5291 */
5292 DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5293
5294 /**
5295 * Changes the device level critical section from the automatically created
5296 * default to one desired by the device constructor.
5297 *
5298 * Must first be done in ring-3.
5299 *
5300 * @returns VBox status code.
5301 * @param pDevIns The device instance.
5302 * @param pCritSect The critical section to use. NULL is not
5303 * valid, instead use the NOP critical
5304 * section.
5305 */
5306 DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5307
5308 /** @name Exported PDM Critical Section Functions
5309 * @{ */
5310 DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5311 DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5312 DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5313 DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5314 DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5315 DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5316 DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5317 DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5318 DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5319 DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5320 /** @} */
5321
5322 /**
5323 * Gets the trace buffer handle.
5324 *
5325 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5326 * really inteded for direct usage, thus no inline wrapper function.
5327 *
5328 * @returns Trace buffer handle or NIL_RTTRACEBUF.
5329 * @param pDevIns The device instance.
5330 */
5331 DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5332
5333 /**
5334 * Sets up the PCI bus for the ring-0 context.
5335 *
5336 * This must be called after ring-3 has registered the PCI bus using
5337 * PDMDevHlpPCIBusRegister().
5338 *
5339 * @returns VBox status code.
5340 * @param pDevIns The device instance.
5341 * @param pPciBusReg The PCI bus registration information for ring-0,
5342 * considered volatile and copied.
5343 * @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5344 */
5345 DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5346
5347 /**
5348 * Sets up the IOMMU for the ring-0 context.
5349 *
5350 * This must be called after ring-3 has registered the IOMMU using
5351 * PDMDevHlpIommuRegister().
5352 *
5353 * @returns VBox status code.
5354 * @param pDevIns The device instance.
5355 * @param pIommuReg The IOMMU registration information for ring-0,
5356 * considered volatile and copied.
5357 * @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5358 */
5359 DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5360
5361 /**
5362 * Sets up the PIC for the ring-0 context.
5363 *
5364 * This must be called after ring-3 has registered the PIC using
5365 * PDMDevHlpPICRegister().
5366 *
5367 * @returns VBox status code.
5368 * @param pDevIns The device instance.
5369 * @param pPicReg The PIC registration information for ring-0,
5370 * considered volatile and copied.
5371 * @param ppPicHlp Where to return the ring-0 PIC helpers.
5372 */
5373 DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5374
5375 /**
5376 * Sets up the APIC for the ring-0 context.
5377 *
5378 * This must be called after ring-3 has registered the APIC using
5379 * PDMDevHlpApicRegister().
5380 *
5381 * @returns VBox status code.
5382 * @param pDevIns The device instance.
5383 */
5384 DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5385
5386 /**
5387 * Sets up the IOAPIC for the ring-0 context.
5388 *
5389 * This must be called after ring-3 has registered the PIC using
5390 * PDMDevHlpIoApicRegister().
5391 *
5392 * @returns VBox status code.
5393 * @param pDevIns The device instance.
5394 * @param pIoApicReg The PIC registration information for ring-0,
5395 * considered volatile and copied.
5396 * @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5397 */
5398 DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5399
5400 /**
5401 * Sets up the HPET for the ring-0 context.
5402 *
5403 * This must be called after ring-3 has registered the PIC using
5404 * PDMDevHlpHpetRegister().
5405 *
5406 * @returns VBox status code.
5407 * @param pDevIns The device instance.
5408 * @param pHpetReg The PIC registration information for ring-0,
5409 * considered volatile and copied.
5410 * @param ppHpetHlp Where to return the ring-0 HPET helpers.
5411 */
5412 DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5413
5414 /** Space reserved for future members.
5415 * @{ */
5416 DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5417 DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5418 DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5419 DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5420 DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5421 DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5422 DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5423 DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5424 DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5425 DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5426 /** @} */
5427
5428 /** Just a safety precaution. */
5429 uint32_t u32TheEnd;
5430} PDMDEVHLPR0;
5431/** Pointer PDM Device R0 API. */
5432typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5433/** Pointer PDM Device GC API. */
5434typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5435
5436/** Current PDMDEVHLP version number. */
5437#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 18, 0)
5438
5439
5440/**
5441 * PDM Device Instance.
5442 */
5443typedef struct PDMDEVINSR3
5444{
5445 /** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5446 uint32_t u32Version;
5447 /** Device instance number. */
5448 uint32_t iInstance;
5449 /** Size of the ring-3, raw-mode and shared bits. */
5450 uint32_t cbRing3;
5451 /** Set if ring-0 context is enabled. */
5452 bool fR0Enabled;
5453 /** Set if raw-mode context is enabled. */
5454 bool fRCEnabled;
5455 /** Alignment padding. */
5456 bool afReserved[2];
5457 /** Pointer the HC PDM Device API. */
5458 PCPDMDEVHLPR3 pHlpR3;
5459 /** Pointer to the shared device instance data. */
5460 RTR3PTR pvInstanceDataR3;
5461 /** Pointer to the device instance data for ring-3. */
5462 RTR3PTR pvInstanceDataForR3;
5463 /** The critical section for the device.
5464 *
5465 * TM and IOM will enter this critical section before calling into the device
5466 * code. PDM will when doing power on, power off, reset, suspend and resume
5467 * notifications. SSM will currently not, but this will be changed later on.
5468 *
5469 * The device gets a critical section automatically assigned to it before
5470 * the constructor is called. If the constructor wishes to use a different
5471 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5472 * very early on.
5473 */
5474 R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5475 /** Pointer to device registration structure. */
5476 R3PTRTYPE(PCPDMDEVREG) pReg;
5477 /** Configuration handle. */
5478 R3PTRTYPE(PCFGMNODE) pCfg;
5479 /** The base interface of the device.
5480 *
5481 * The device constructor initializes this if it has any
5482 * device level interfaces to export. To obtain this interface
5483 * call PDMR3QueryDevice(). */
5484 PDMIBASE IBase;
5485
5486 /** Tracing indicator. */
5487 uint32_t fTracing;
5488 /** The tracing ID of this device. */
5489 uint32_t idTracing;
5490
5491 /** Ring-3 pointer to the raw-mode device instance. */
5492 R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5493 /** Raw-mode address of the raw-mode device instance. */
5494 RTRGPTR pDevInsForRC;
5495 /** Ring-3 pointer to the raw-mode instance data. */
5496 RTR3PTR pvInstanceDataForRCR3;
5497
5498 /** PCI device structure size. */
5499 uint32_t cbPciDev;
5500 /** Number of PCI devices in apPciDevs. */
5501 uint32_t cPciDevs;
5502 /** Pointer to the PCI devices for this device.
5503 * (Allocated after the shared instance data.)
5504 * @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5505 * two devices ever needing it can use cbPciDev and do the address
5506 * calculations that for entries 8+. */
5507 R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5508
5509 /** Temporarily. */
5510 R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5511 /** Temporarily. */
5512 RTR0PTR pvInstanceDataR0;
5513 /** Temporarily. */
5514 RTRCPTR pvInstanceDataRC;
5515 /** Align the internal data more naturally. */
5516 uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5517
5518 /** Internal data. */
5519 union
5520 {
5521#ifdef PDMDEVINSINT_DECLARED
5522 PDMDEVINSINTR3 s;
5523#endif
5524 uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
5525 } Internal;
5526
5527 /** Device instance data for ring-3. The size of this area is defined
5528 * in the PDMDEVREG::cbInstanceR3 field. */
5529 char achInstanceData[8];
5530} PDMDEVINSR3;
5531
5532/** Current PDMDEVINSR3 version number. */
5533#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5534
5535/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5536#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5537
5538
5539/**
5540 * PDM ring-0 device instance.
5541 */
5542typedef struct PDMDEVINSR0
5543{
5544 /** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5545 uint32_t u32Version;
5546 /** Device instance number. */
5547 uint32_t iInstance;
5548
5549 /** Pointer the HC PDM Device API. */
5550 PCPDMDEVHLPR0 pHlpR0;
5551 /** Pointer to the shared device instance data. */
5552 RTR0PTR pvInstanceDataR0;
5553 /** Pointer to the device instance data for ring-0. */
5554 RTR0PTR pvInstanceDataForR0;
5555 /** The critical section for the device.
5556 *
5557 * TM and IOM will enter this critical section before calling into the device
5558 * code. PDM will when doing power on, power off, reset, suspend and resume
5559 * notifications. SSM will currently not, but this will be changed later on.
5560 *
5561 * The device gets a critical section automatically assigned to it before
5562 * the constructor is called. If the constructor wishes to use a different
5563 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5564 * very early on.
5565 */
5566 R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5567 /** Pointer to the ring-0 device registration structure. */
5568 R0PTRTYPE(PCPDMDEVREGR0) pReg;
5569 /** Ring-3 address of the ring-3 device instance. */
5570 R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5571 /** Ring-0 pointer to the ring-3 device instance. */
5572 R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5573 /** Ring-0 pointer to the ring-3 instance data. */
5574 RTR0PTR pvInstanceDataForR3R0;
5575 /** Raw-mode address of the raw-mode device instance. */
5576 RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5577 /** Ring-0 pointer to the raw-mode device instance. */
5578 R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5579 /** Ring-0 pointer to the raw-mode instance data. */
5580 RTR0PTR pvInstanceDataForRCR0;
5581
5582 /** PCI device structure size. */
5583 uint32_t cbPciDev;
5584 /** Number of PCI devices in apPciDevs. */
5585 uint32_t cPciDevs;
5586 /** Pointer to the PCI devices for this device.
5587 * (Allocated after the shared instance data.)
5588 * @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5589 * two devices ever needing it can use cbPciDev and do the address
5590 * calculations that for entries 8+. */
5591 R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5592
5593 /** Align the internal data more naturally. */
5594 uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5595
5596 /** Internal data. */
5597 union
5598 {
5599#ifdef PDMDEVINSINT_DECLARED
5600 PDMDEVINSINTR0 s;
5601#endif
5602 uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
5603 } Internal;
5604
5605 /** Device instance data for ring-0. The size of this area is defined
5606 * in the PDMDEVREG::cbInstanceR0 field. */
5607 char achInstanceData[8];
5608} PDMDEVINSR0;
5609
5610/** Current PDMDEVINSR0 version number. */
5611#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5612
5613
5614/**
5615 * PDM raw-mode device instance.
5616 */
5617typedef struct PDMDEVINSRC
5618{
5619 /** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5620 uint32_t u32Version;
5621 /** Device instance number. */
5622 uint32_t iInstance;
5623
5624 /** Pointer the HC PDM Device API. */
5625 PCPDMDEVHLPRC pHlpRC;
5626 /** Pointer to the shared device instance data. */
5627 RTRGPTR pvInstanceDataRC;
5628 /** Pointer to the device instance data for raw-mode. */
5629 RTRGPTR pvInstanceDataForRC;
5630 /** The critical section for the device.
5631 *
5632 * TM and IOM will enter this critical section before calling into the device
5633 * code. PDM will when doing power on, power off, reset, suspend and resume
5634 * notifications. SSM will currently not, but this will be changed later on.
5635 *
5636 * The device gets a critical section automatically assigned to it before
5637 * the constructor is called. If the constructor wishes to use a different
5638 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5639 * very early on.
5640 */
5641 RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5642 /** Pointer to the raw-mode device registration structure. */
5643 RGPTRTYPE(PCPDMDEVREGRC) pReg;
5644
5645 /** PCI device structure size. */
5646 uint32_t cbPciDev;
5647 /** Number of PCI devices in apPciDevs. */
5648 uint32_t cPciDevs;
5649 /** Pointer to the PCI devices for this device.
5650 * (Allocated after the shared instance data.) */
5651 RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5652
5653 /** Align the internal data more naturally. */
5654 uint32_t au32Padding[14];
5655
5656 /** Internal data. */
5657 union
5658 {
5659#ifdef PDMDEVINSINT_DECLARED
5660 PDMDEVINSINTRC s;
5661#endif
5662 uint8_t padding[0x10];
5663 } Internal;
5664
5665 /** Device instance data for ring-0. The size of this area is defined
5666 * in the PDMDEVREG::cbInstanceR0 field. */
5667 char achInstanceData[8];
5668} PDMDEVINSRC;
5669
5670/** Current PDMDEVINSR0 version number. */
5671#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5672
5673
5674/** @def PDM_DEVINS_VERSION
5675 * Current PDMDEVINS version number. */
5676/** @typedef PDMDEVINS
5677 * The device instance structure for the current context. */
5678#ifdef IN_RING3
5679# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5680typedef PDMDEVINSR3 PDMDEVINS;
5681#elif defined(IN_RING0)
5682# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5683typedef PDMDEVINSR0 PDMDEVINS;
5684#elif defined(IN_RC)
5685# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5686typedef PDMDEVINSRC PDMDEVINS;
5687#else
5688# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5689#endif
5690
5691/**
5692 * Get the pointer to an PCI device.
5693 * @note Returns NULL if @a a_idxPciDev is out of bounds.
5694 */
5695#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5696 ( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5697 : PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5698
5699/**
5700 * Calc the pointer to of a given PCI device.
5701 * @note Returns NULL if @a a_idxPciDev is out of bounds.
5702 */
5703#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5704 ( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5705 ? (PPDMPCIDEV)((uint8_t *)((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) * (uintptr_t)(a_idxPciDev)) \
5706 : (PPDMPCIDEV)NULL )
5707
5708
5709/**
5710 * Checks the structure versions of the device instance and device helpers,
5711 * returning if they are incompatible.
5712 *
5713 * This is for use in the constructor.
5714 *
5715 * @param pDevIns The device instance pointer.
5716 */
5717#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5718 do \
5719 { \
5720 PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5721 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5722 ("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5723 VERR_PDM_DEVINS_VERSION_MISMATCH); \
5724 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5725 ("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5726 VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5727 } while (0)
5728
5729/**
5730 * Quietly checks the structure versions of the device instance and device
5731 * helpers, returning if they are incompatible.
5732 *
5733 * This is for use in the destructor.
5734 *
5735 * @param pDevIns The device instance pointer.
5736 */
5737#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5738 do \
5739 { \
5740 PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5741 if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5742 { /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5743 if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5744 { /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5745 } while (0)
5746
5747/**
5748 * Wrapper around CFGMR3ValidateConfig for the root config for use in the
5749 * constructor - returns on failure.
5750 *
5751 * This should be invoked after having initialized the instance data
5752 * sufficiently for the correct operation of the destructor. The destructor is
5753 * always called!
5754 *
5755 * @param pDevIns Pointer to the PDM device instance.
5756 * @param pszValidValues Patterns describing the valid value names. See
5757 * RTStrSimplePatternMultiMatch for details on the
5758 * pattern syntax.
5759 * @param pszValidNodes Patterns describing the valid node (key) names.
5760 * Pass empty string if no valid nodes.
5761 */
5762#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5763 do \
5764 { \
5765 int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5766 (pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5767 if (RT_SUCCESS(rcValCfg)) \
5768 { /* likely */ } else return rcValCfg; \
5769 } while (0)
5770
5771/** @def PDMDEV_ASSERT_EMT
5772 * Assert that the current thread is the emulation thread.
5773 */
5774#ifdef VBOX_STRICT
5775# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5776#else
5777# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5778#endif
5779
5780/** @def PDMDEV_ASSERT_OTHER
5781 * Assert that the current thread is NOT the emulation thread.
5782 */
5783#ifdef VBOX_STRICT
5784# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5785#else
5786# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5787#endif
5788
5789/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5790 * Assert that the current thread is owner of the VM lock.
5791 */
5792#ifdef VBOX_STRICT
5793# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5794#else
5795# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5796#endif
5797
5798/** @def PDMDEV_SET_ERROR
5799 * Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5800 */
5801#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5802 PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5803
5804/** @def PDMDEV_SET_RUNTIME_ERROR
5805 * Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5806 */
5807#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5808 PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5809
5810/** @def PDMDEVINS_2_RCPTR
5811 * Converts a PDM Device instance pointer a RC PDM Device instance pointer.
5812 */
5813#ifdef IN_RC
5814# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5815#else
5816# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5817#endif
5818
5819/** @def PDMDEVINS_2_R3PTR
5820 * Converts a PDM Device instance pointer a R3 PDM Device instance pointer.
5821 */
5822#ifdef IN_RING3
5823# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5824#else
5825# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5826#endif
5827
5828/** @def PDMDEVINS_2_R0PTR
5829 * Converts a PDM Device instance pointer a R0 PDM Device instance pointer.
5830 */
5831#ifdef IN_RING0
5832# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5833#else
5834# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5835#endif
5836
5837/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5838 * Converts a PDM device instance data pointer to a ring-0 one.
5839 * @deprecated
5840 */
5841#ifdef IN_RING0
5842# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5843#else
5844# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5845#endif
5846
5847
5848/** @def PDMDEVINS_2_DATA
5849 * This is a safer edition of PDMINS_2_DATA that checks that the size of the
5850 * target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5851 *
5852 * @note Do no use this macro in common code working on a core structure which
5853 * device specific code has expanded.
5854 */
5855#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5856# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5857 ([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5858 { \
5859 a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5860 Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5861 return pLambdaRet; \
5862 }(a_pDevIns))
5863#else
5864# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5865#endif
5866
5867/** @def PDMDEVINS_2_DATA_CC
5868 * This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5869 * target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5870 *
5871 * @note Do no use this macro in common code working on a core structure which
5872 * device specific code has expanded.
5873 */
5874#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5875# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5876 ([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5877 { \
5878 a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5879 Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5880 return pLambdaRet; \
5881 }(a_pDevIns))
5882#else
5883# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5884#endif
5885
5886
5887#ifdef IN_RING3
5888
5889/**
5890 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
5891 */
5892DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5893 PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
5894 PIOMIOPORTHANDLE phIoPorts)
5895{
5896 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5897 pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5898 if (RT_SUCCESS(rc))
5899 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5900 return rc;
5901}
5902
5903/**
5904 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
5905 */
5906DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5907 PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
5908 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5909{
5910 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5911 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5912 if (RT_SUCCESS(rc))
5913 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5914 return rc;
5915}
5916
5917/**
5918 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
5919 */
5920DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5921 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5922 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5923{
5924 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5925 pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5926 if (RT_SUCCESS(rc))
5927 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5928 return rc;
5929}
5930
5931/**
5932 * Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
5933 */
5934DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5935 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5936 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5937 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5938{
5939 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5940 pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5941 if (RT_SUCCESS(rc))
5942 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5943 return rc;
5944}
5945
5946/**
5947 * @sa PDMDevHlpIoPortCreateEx
5948 */
5949DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5950 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser, const char *pszDesc,
5951 PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5952{
5953 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
5954 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5955}
5956
5957
5958/**
5959 * @sa PDMDevHlpIoPortCreateEx
5960 */
5961DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5962 PFNIOMIOPORTNEWIN pfnIn, void *pvUser, const char *pszDesc,
5963 PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5964{
5965 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5966 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5967}
5968
5969/**
5970 * @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
5971 */
5972DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
5973 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5974 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5975 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5976{
5977 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
5978 pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5979}
5980
5981/**
5982 * @copydoc PDMDEVHLPR3::pfnIoPortMap
5983 */
5984DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
5985{
5986 return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
5987}
5988
5989/**
5990 * @copydoc PDMDEVHLPR3::pfnIoPortUnmap
5991 */
5992DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5993{
5994 return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
5995}
5996
5997/**
5998 * @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
5999 */
6000DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6001{
6002 return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6003}
6004
6005
6006#endif /* IN_RING3 */
6007#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
6008
6009/**
6010 * @sa PDMDevHlpIoPortSetUpContextEx
6011 */
6012DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6013 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6014{
6015 return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6016}
6017
6018/**
6019 * @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6020 */
6021DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6022 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6023 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6024{
6025 return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6026}
6027
6028#endif /* !IN_RING3 || DOXYGEN_RUNNING */
6029#ifdef IN_RING3
6030
6031/**
6032 * @sa PDMDevHlpMmioCreateEx
6033 */
6034DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6035 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6036 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6037{
6038 return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6039 pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6040}
6041
6042/**
6043 * @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6044 */
6045DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6046 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6047 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6048 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6049{
6050 return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6051 pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6052}
6053
6054/**
6055 * @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6056 */
6057DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6058 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6059 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6060{
6061 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /*pPciDev*/, UINT32_MAX /*iPciRegion*/,
6062 pfnWrite, pfnRead, NULL /*pfnFill*/, NULL /*pvUser*/, pszDesc, phRegion);
6063 if (RT_SUCCESS(rc))
6064 rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6065 return rc;
6066}
6067
6068/**
6069 * @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6070 */
6071DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6072 PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6073 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6074 const char *pszDesc, PIOMMMIOHANDLE phRegion)
6075{
6076 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6077 pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6078 if (RT_SUCCESS(rc))
6079 rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6080 return rc;
6081}
6082
6083/**
6084 * @copydoc PDMDEVHLPR3::pfnMmioMap
6085 */
6086DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6087{
6088 return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6089}
6090
6091/**
6092 * @copydoc PDMDEVHLPR3::pfnMmioUnmap
6093 */
6094DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6095{
6096 return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6097}
6098
6099/**
6100 * @copydoc PDMDEVHLPR3::pfnMmioReduce
6101 */
6102DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6103{
6104 return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6105}
6106
6107/**
6108 * @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6109 */
6110DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6111{
6112 return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6113}
6114
6115#endif /* IN_RING3 */
6116#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
6117
6118/**
6119 * @sa PDMDevHlpMmioSetUpContextEx
6120 */
6121DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6122 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6123{
6124 return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6125}
6126
6127/**
6128 * @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6129 */
6130DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6131 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6132{
6133 return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6134}
6135
6136#endif /* !IN_RING3 || DOXYGEN_RUNNING */
6137#ifdef IN_RING3
6138
6139/**
6140 * @copydoc PDMDEVHLPR3::pfnMmio2Create
6141 */
6142DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6143 uint32_t fFlags, const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion)
6144{
6145 return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6146}
6147
6148/**
6149 * @copydoc PDMDEVHLPR3::pfnMmio2Map
6150 */
6151DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6152{
6153 return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6154}
6155
6156/**
6157 * @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6158 */
6159DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6160{
6161 return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6162}
6163
6164/**
6165 * @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6166 */
6167DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6168{
6169 return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6170}
6171
6172/**
6173 * @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6174 */
6175DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6176{
6177 return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6178}
6179
6180#endif /* IN_RING3 */
6181#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
6182
6183/**
6184 * @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6185 */
6186DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6187 size_t offSub, size_t cbSub, void **ppvMapping)
6188{
6189 return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6190}
6191
6192#endif /* !IN_RING3 || DOXYGEN_RUNNING */
6193#ifdef IN_RING3
6194
6195/**
6196 * @copydoc PDMDEVHLPR3::pfnROMRegister
6197 */
6198DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6199 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc)
6200{
6201 return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6202}
6203
6204/**
6205 * @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6206 */
6207DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6208{
6209 return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6210}
6211
6212/**
6213 * Register a save state data unit.
6214 *
6215 * @returns VBox status.
6216 * @param pDevIns The device instance.
6217 * @param uVersion Data layout version number.
6218 * @param cbGuess The approximate amount of data in the unit.
6219 * Only for progress indicators.
6220 * @param pfnSaveExec Execute save callback, optional.
6221 * @param pfnLoadExec Execute load callback, optional.
6222 */
6223DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6224 PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6225{
6226 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /*pszBefore*/,
6227 NULL /*pfnLivePrep*/, NULL /*pfnLiveExec*/, NULL /*pfnLiveDone*/,
6228 NULL /*pfnSavePrep*/, pfnSaveExec, NULL /*pfnSaveDone*/,
6229 NULL /*pfnLoadPrep*/, pfnLoadExec, NULL /*pfnLoadDone*/);
6230}
6231
6232/**
6233 * Register a save state data unit with a live save callback as well.
6234 *
6235 * @returns VBox status.
6236 * @param pDevIns The device instance.
6237 * @param uVersion Data layout version number.
6238 * @param cbGuess The approximate amount of data in the unit.
6239 * Only for progress indicators.
6240 * @param pfnLiveExec Execute live callback, optional.
6241 * @param pfnSaveExec Execute save callback, optional.
6242 * @param pfnLoadExec Execute load callback, optional.
6243 */
6244DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6245 PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6246{
6247 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /*pszBefore*/,
6248 NULL /*pfnLivePrep*/, pfnLiveExec, NULL /*pfnLiveDone*/,
6249 NULL /*pfnSavePrep*/, pfnSaveExec, NULL /*pfnSaveDone*/,
6250 NULL /*pfnLoadPrep*/, pfnLoadExec, NULL /*pfnLoadDone*/);
6251}
6252
6253/**
6254 * @copydoc PDMDEVHLPR3::pfnSSMRegister
6255 */
6256DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6257 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6258 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6259 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6260{
6261 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6262 pfnLivePrep, pfnLiveExec, pfnLiveVote,
6263 pfnSavePrep, pfnSaveExec, pfnSaveDone,
6264 pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6265}
6266
6267/**
6268 * @copydoc PDMDEVHLPR3::pfnTMTimerCreate
6269 */
6270DECLINLINE(int) PDMDevHlpTMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6271 uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
6272{
6273 return pDevIns->pHlpR3->pfnTMTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
6274}
6275
6276/**
6277 * @copydoc PDMDEVHLPR3::pfnTimerCreate
6278 */
6279DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6280 uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6281{
6282 return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6283}
6284
6285#endif /* IN_RING3 */
6286
6287/**
6288 * @copydoc PDMDEVHLPR3::pfnTimerToPtr
6289 */
6290DECLINLINE(PTMTIMER) PDMDevHlpTimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6291{
6292 return pDevIns->CTX_SUFF(pHlp)->pfnTimerToPtr(pDevIns, hTimer);
6293}
6294
6295/**
6296 * @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6297 */
6298DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6299{
6300 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6301}
6302
6303/**
6304 * @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6305 */
6306DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6307{
6308 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6309}
6310
6311/**
6312 * @copydoc PDMDEVHLPR3::pfnTimerFromNano
6313 */
6314DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6315{
6316 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6317}
6318
6319/**
6320 * @copydoc PDMDEVHLPR3::pfnTimerGet
6321 */
6322DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6323{
6324 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6325}
6326
6327/**
6328 * @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6329 */
6330DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6331{
6332 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6333}
6334
6335/**
6336 * @copydoc PDMDEVHLPR3::pfnTimerGetNano
6337 */
6338DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6339{
6340 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6341}
6342
6343/**
6344 * @copydoc PDMDEVHLPR3::pfnTimerIsActive
6345 */
6346DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6347{
6348 return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6349}
6350
6351/**
6352 * @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6353 */
6354DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6355{
6356 return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6357}
6358
6359/**
6360 * @copydoc PDMDEVHLPR3::pfnTimerLockClock
6361 */
6362DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6363{
6364 return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6365}
6366
6367/**
6368 * @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6369 */
6370DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6371{
6372 return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6373}
6374
6375/**
6376 * @copydoc PDMDEVHLPR3::pfnTimerSet
6377 */
6378DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6379{
6380 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6381}
6382
6383/**
6384 * @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6385 */
6386DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6387{
6388 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6389}
6390
6391/**
6392 * @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6393 */
6394DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6395{
6396 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6397}
6398
6399/**
6400 * @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6401 */
6402DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6403{
6404 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6405}
6406
6407/**
6408 * @copydoc PDMDEVHLPR3::pfnTimerSetNano
6409 */
6410DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6411{
6412 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6413}
6414
6415/**
6416 * @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6417 */
6418DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6419{
6420 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6421}
6422
6423/**
6424 * @copydoc PDMDEVHLPR3::pfnTimerStop
6425 */
6426DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6427{
6428 return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6429}
6430
6431/**
6432 * @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6433 */
6434DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6435{
6436 pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6437}
6438
6439/**
6440 * @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6441 */
6442DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6443{
6444 pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6445}
6446
6447#ifdef IN_RING3
6448
6449/**
6450 * @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6451 */
6452DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6453{
6454 return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6455}
6456
6457/**
6458 * @copydoc PDMDEVHLPR3::pfnTimerSave
6459 */
6460DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6461{
6462 return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6463}
6464
6465/**
6466 * @copydoc PDMDEVHLPR3::pfnTimerLoad
6467 */
6468DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6469{
6470 return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6471}
6472
6473/**
6474 * @copydoc PDMDEVHLPR3::pfnTimerDestroy
6475 */
6476DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6477{
6478 return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6479}
6480
6481/**
6482 * @copydoc PDMDEVHLPR3::pfnTMUtcNow
6483 */
6484DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6485{
6486 return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6487}
6488
6489#endif
6490
6491/**
6492 * Read physical memory - unknown data usage.
6493 *
6494 * @returns VINF_SUCCESS (for now).
6495 * @param pDevIns The device instance.
6496 * @param GCPhys Physical address start reading from.
6497 * @param pvBuf Where to put the read bits.
6498 * @param cbRead How many bytes to read.
6499 * @thread Any thread, but the call may involve the emulation thread.
6500 */
6501DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6502{
6503 return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6504}
6505
6506/**
6507 * Write to physical memory - unknown data usage.
6508 *
6509 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6510 * @param pDevIns The device instance.
6511 * @param GCPhys Physical address to write to.
6512 * @param pvBuf What to write.
6513 * @param cbWrite How many bytes to write.
6514 * @thread Any thread, but the call may involve the emulation thread.
6515 */
6516DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6517{
6518 return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6519}
6520
6521/**
6522 * Read physical memory - reads meta data processed by the device.
6523 *
6524 * @returns VINF_SUCCESS (for now).
6525 * @param pDevIns The device instance.
6526 * @param GCPhys Physical address start reading from.
6527 * @param pvBuf Where to put the read bits.
6528 * @param cbRead How many bytes to read.
6529 * @thread Any thread, but the call may involve the emulation thread.
6530 */
6531DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6532{
6533 return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6534}
6535
6536/**
6537 * Write to physical memory - written data was created/altered by the device.
6538 *
6539 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6540 * @param pDevIns The device instance.
6541 * @param GCPhys Physical address to write to.
6542 * @param pvBuf What to write.
6543 * @param cbWrite How many bytes to write.
6544 * @thread Any thread, but the call may involve the emulation thread.
6545 */
6546DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6547{
6548 return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6549}
6550
6551/**
6552 * Read physical memory - read data will not be touched by the device.
6553 *
6554 * @returns VINF_SUCCESS (for now).
6555 * @param pDevIns The device instance.
6556 * @param GCPhys Physical address start reading from.
6557 * @param pvBuf Where to put the read bits.
6558 * @param cbRead How many bytes to read.
6559 * @thread Any thread, but the call may involve the emulation thread.
6560 */
6561DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6562{
6563 return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6564}
6565
6566/**
6567 * Write to physical memory - written data was not touched/created by the device.
6568 *
6569 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6570 * @param pDevIns The device instance.
6571 * @param GCPhys Physical address to write to.
6572 * @param pvBuf What to write.
6573 * @param cbWrite How many bytes to write.
6574 * @thread Any thread, but the call may involve the emulation thread.
6575 */
6576DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6577{
6578 return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6579}
6580
6581#ifdef IN_RING3
6582
6583/**
6584 * @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6585 */
6586DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6587{
6588 return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6589}
6590
6591/**
6592 * @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6593 */
6594DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6595 PPGMPAGEMAPLOCK pLock)
6596{
6597 return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6598}
6599
6600/**
6601 * @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6602 */
6603DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6604{
6605 pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6606}
6607
6608/**
6609 * @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6610 */
6611DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6612 uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6613{
6614 return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6615}
6616
6617/**
6618 * @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6619 */
6620DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6621 uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6622{
6623 return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6624}
6625
6626/**
6627 * @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6628 */
6629DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6630{
6631 pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6632}
6633
6634/**
6635 * @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
6636 */
6637DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
6638{
6639 return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
6640}
6641
6642/**
6643 * @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6644 */
6645DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6646{
6647 return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6648}
6649
6650/**
6651 * @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6652 */
6653DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6654{
6655 return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6656}
6657
6658/**
6659 * @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6660 */
6661DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6662{
6663 return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6664}
6665
6666/**
6667 * @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6668 */
6669DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6670{
6671 return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6672}
6673
6674/**
6675 * @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6676 */
6677DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6678{
6679 return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6680}
6681
6682/**
6683 * @copydoc PDMDEVHLPR3::pfnMMHeapFree
6684 */
6685DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6686{
6687 pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6688}
6689#endif /* IN_RING3 */
6690
6691/**
6692 * @copydoc PDMDEVHLPR3::pfnVMState
6693 */
6694DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6695{
6696 return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6697}
6698
6699#ifdef IN_RING3
6700/**
6701 * @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6702 */
6703DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6704{
6705 return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6706}
6707#endif /* IN_RING3 */
6708
6709/**
6710 * @copydoc PDMDEVHLPR3::pfnVMSetError
6711 */
6712DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6713 const char *pszFormat, ...)
6714{
6715 va_list va;
6716 va_start(va, pszFormat);
6717 pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6718 va_end(va);
6719 return rc;
6720}
6721
6722/**
6723 * @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError
6724 */
6725DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6726 const char *pszFormat, ...)
6727{
6728 va_list va;
6729 int rc;
6730 va_start(va, pszFormat);
6731 rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6732 va_end(va);
6733 return rc;
6734}
6735
6736/**
6737 * VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6738 *
6739 * @returns VBox status code which must be passed up to the VMM. This will be
6740 * VINF_SUCCESS in non-strict builds.
6741 * @param pDevIns The device instance.
6742 * @param SRC_POS Use RT_SRC_POS.
6743 * @param pszFormat Message. (optional)
6744 * @param ... Message parameters.
6745 */
6746DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6747{
6748#ifdef VBOX_STRICT
6749# ifdef IN_RING3
6750 int rc;
6751 va_list args;
6752 va_start(args, pszFormat);
6753 rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6754 va_end(args);
6755 return rc;
6756# else
6757 NOREF(pDevIns);
6758 NOREF(pszFile);
6759 NOREF(iLine);
6760 NOREF(pszFunction);
6761 NOREF(pszFormat);
6762 return VINF_EM_DBG_STOP;
6763# endif
6764#else
6765 NOREF(pDevIns);
6766 NOREF(pszFile);
6767 NOREF(iLine);
6768 NOREF(pszFunction);
6769 NOREF(pszFormat);
6770 return VINF_SUCCESS;
6771#endif
6772}
6773
6774#ifdef IN_RING3
6775
6776/**
6777 * @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6778 */
6779DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6780{
6781 return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6782}
6783
6784/**
6785 * @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6786 */
6787DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6788{
6789 return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6790}
6791
6792/**
6793 * @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6794 */
6795DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6796{
6797 return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6798}
6799
6800/**
6801 * @copydoc PDMDEVHLPR3::pfnSTAMRegister
6802 */
6803DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc)
6804{
6805 pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6806}
6807
6808/**
6809 * Same as pfnSTAMRegister except that the name is specified in a
6810 * RTStrPrintf like fashion.
6811 *
6812 * @returns VBox status.
6813 * @param pDevIns Device instance of the DMA.
6814 * @param pvSample Pointer to the sample.
6815 * @param enmType Sample type. This indicates what pvSample is
6816 * pointing at.
6817 * @param enmVisibility Visibility type specifying whether unused
6818 * statistics should be visible or not.
6819 * @param enmUnit Sample unit.
6820 * @param pszDesc Sample description.
6821 * @param pszName Sample name format string, unix path style. If
6822 * this does not start with a '/', the default
6823 * prefix will be prepended, otherwise it will be
6824 * used as-is.
6825 * @param ... Arguments to the format string.
6826 */
6827DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6828 STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6829 const char *pszDesc, const char *pszName, ...)
6830{
6831 va_list va;
6832 va_start(va, pszName);
6833 pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6834 va_end(va);
6835}
6836
6837/**
6838 * Registers the device with the default PCI bus.
6839 *
6840 * @returns VBox status code.
6841 * @param pDevIns The device instance.
6842 * @param pPciDev The PCI device structure.
6843 * This must be kept in the instance data.
6844 * The PCI configuration must be initialized before registration.
6845 */
6846DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6847{
6848 return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /*fFlags*/,
6849 PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6850}
6851
6852/**
6853 * @copydoc PDMDEVHLPR3::pfnPCIRegister
6854 */
6855DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6856 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6857{
6858 return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6859}
6860
6861/**
6862 * Initialize MSI emulation support for the first PCI device.
6863 *
6864 * @returns VBox status code.
6865 * @param pDevIns The device instance.
6866 * @param pMsiReg MSI emulation registration structure.
6867 */
6868DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6869{
6870 return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6871}
6872
6873/**
6874 * @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6875 */
6876DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6877{
6878 return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6879}
6880
6881/**
6882 * Registers a I/O port region for the default PCI device.
6883 *
6884 * @returns VBox status code.
6885 * @param pDevIns The device instance.
6886 * @param iRegion The region number.
6887 * @param cbRegion Size of the region.
6888 * @param hIoPorts Handle to the I/O port region.
6889 */
6890DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
6891{
6892 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6893 PDMPCIDEV_IORGN_F_IOPORT_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
6894}
6895
6896/**
6897 * Registers a I/O port region for the default PCI device, custom map/unmap.
6898 *
6899 * @returns VBox status code.
6900 * @param pDevIns The device instance.
6901 * @param iRegion The region number.
6902 * @param cbRegion Size of the region.
6903 * @param pfnMapUnmap Callback for doing the mapping, optional. The
6904 * callback will be invoked holding only the PDM lock.
6905 * The device lock will _not_ be taken (due to lock
6906 * order).
6907 */
6908DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6909 PFNPCIIOREGIONMAP pfnMapUnmap)
6910{
6911 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6912 PDMPCIDEV_IORGN_F_NO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6913 UINT64_MAX, pfnMapUnmap);
6914}
6915
6916/**
6917 * Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
6918 * and registering an I/O port region for the default PCI device.
6919 *
6920 * @returns VBox status code.
6921 * @param pDevIns The device instance to register the ports with.
6922 * @param cPorts The count of I/O ports in the region (the size).
6923 * @param iPciRegion The PCI device region.
6924 * @param pfnOut Pointer to function which is gonna handle OUT
6925 * operations. Optional.
6926 * @param pfnIn Pointer to function which is gonna handle IN operations.
6927 * Optional.
6928 * @param pvUser User argument to pass to the callbacks.
6929 * @param pszDesc Pointer to description string. This must not be freed.
6930 * @param paExtDescs Extended per-port descriptions, optional. Partial range
6931 * coverage is allowed. This must not be freed.
6932 * @param phIoPorts Where to return the I/O port range handle.
6933 *
6934 */
6935DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
6936 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6937 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6938
6939{
6940 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /*fFlags*/, pDevIns->apPciDevs[0], iPciRegion << 16,
6941 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6942 if (RT_SUCCESS(rc))
6943 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
6944 PDMPCIDEV_IORGN_F_IOPORT_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6945 *phIoPorts, NULL /*pfnMapUnmap*/);
6946 return rc;
6947}
6948
6949/**
6950 * Registers an MMIO region for the default PCI device.
6951 *
6952 * @returns VBox status code.
6953 * @param pDevIns The device instance.
6954 * @param iRegion The region number.
6955 * @param cbRegion Size of the region.
6956 * @param enmType PCI_ADDRESS_SPACE_MEM or
6957 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6958 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6959 * @param hMmioRegion Handle to the MMIO region.
6960 * @param pfnMapUnmap Callback for doing the mapping, optional. The
6961 * callback will be invoked holding only the PDM lock.
6962 * The device lock will _not_ be taken (due to lock
6963 * order).
6964 */
6965DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
6966 IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
6967{
6968 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6969 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6970 hMmioRegion, pfnMapUnmap);
6971}
6972
6973/**
6974 * Registers an MMIO region for the default PCI device, extended version.
6975 *
6976 * @returns VBox status code.
6977 * @param pDevIns The device instance.
6978 * @param pPciDev The PCI device structure.
6979 * @param iRegion The region number.
6980 * @param cbRegion Size of the region.
6981 * @param enmType PCI_ADDRESS_SPACE_MEM or
6982 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6983 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6984 * @param hMmioRegion Handle to the MMIO region.
6985 * @param pfnMapUnmap Callback for doing the mapping, optional. The
6986 * callback will be invoked holding only the PDM lock.
6987 * The device lock will _not_ be taken (due to lock
6988 * order).
6989 */
6990DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
6991 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
6992 PFNPCIIOREGIONMAP pfnMapUnmap)
6993{
6994 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
6995 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
6996 hMmioRegion, pfnMapUnmap);
6997}
6998
6999/**
7000 * Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7001 * and registering an MMIO region for the default PCI device.
7002 *
7003 * @returns VBox status code.
7004 * @param pDevIns The device instance to register the ports with.
7005 * @param cbRegion The size of the region in bytes.
7006 * @param iPciRegion The PCI device region.
7007 * @param enmType PCI_ADDRESS_SPACE_MEM or
7008 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7009 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7010 * @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7011 * @param pfnWrite Pointer to function which is gonna handle Write
7012 * operations.
7013 * @param pfnRead Pointer to function which is gonna handle Read
7014 * operations.
7015 * @param pvUser User argument to pass to the callbacks.
7016 * @param pszDesc Pointer to description string. This must not be freed.
7017 * @param phRegion Where to return the MMIO region handle.
7018 *
7019 */
7020DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7021 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7022 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7023
7024{
7025 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7026 pfnWrite, pfnRead, NULL /*pfnFill*/, pvUser, pszDesc, phRegion);
7027 if (RT_SUCCESS(rc))
7028 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7029 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7030 *phRegion, NULL /*pfnMapUnmap*/);
7031 return rc;
7032}
7033
7034
7035/**
7036 * Registers an MMIO2 region for the default PCI device.
7037 *
7038 * @returns VBox status code.
7039 * @param pDevIns The device instance.
7040 * @param iRegion The region number.
7041 * @param cbRegion Size of the region.
7042 * @param enmType PCI_ADDRESS_SPACE_MEM or
7043 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7044 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7045 * @param hMmio2Region Handle to the MMIO2 region.
7046 */
7047DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7048 PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7049{
7050 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7051 PDMPCIDEV_IORGN_F_MMIO2_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7052 hMmio2Region, NULL);
7053}
7054
7055/**
7056 * Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7057 * and registering an MMIO2 region for the default PCI device, extended edition.
7058 *
7059 * @returns VBox status code.
7060 * @param pDevIns The device instance to register the ports with.
7061 * @param cbRegion The size of the region in bytes.
7062 * @param iPciRegion The PCI device region.
7063 * @param enmType PCI_ADDRESS_SPACE_MEM or
7064 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7065 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7066 * @param pszDesc Pointer to description string. This must not be freed.
7067 * @param ppvMapping Where to store the address of the ring-3 mapping of
7068 * the memory.
7069 * @param phRegion Where to return the MMIO2 region handle.
7070 *
7071 */
7072DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7073 PCIADDRESSSPACE enmType, const char *pszDesc,
7074 void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7075
7076{
7077 int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /*fFlags*/,
7078 pszDesc, ppvMapping, phRegion);
7079 if (RT_SUCCESS(rc))
7080 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7081 PDMPCIDEV_IORGN_F_MMIO2_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7082 *phRegion, NULL /*pfnCallback*/);
7083 return rc;
7084}
7085
7086/**
7087 * Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7088 * and registering an MMIO2 region for the default PCI device.
7089 *
7090 * @returns VBox status code.
7091 * @param pDevIns The device instance to register the ports with.
7092 * @param cbRegion The size of the region in bytes.
7093 * @param iPciRegion The PCI device region.
7094 * @param enmType PCI_ADDRESS_SPACE_MEM or
7095 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7096 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7097 * @param fMmio2Flags To be defined, must be zero.
7098 * @param pfnMapUnmap Callback for doing the mapping, optional. The
7099 * callback will be invoked holding only the PDM lock.
7100 * The device lock will _not_ be taken (due to lock
7101 * order).
7102 * @param pszDesc Pointer to description string. This must not be freed.
7103 * @param ppvMapping Where to store the address of the ring-3 mapping of
7104 * the memory.
7105 * @param phRegion Where to return the MMIO2 region handle.
7106 *
7107 */
7108DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7109 PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7110 const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7111
7112{
7113 int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7114 pszDesc, ppvMapping, phRegion);
7115 if (RT_SUCCESS(rc))
7116 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7117 PDMPCIDEV_IORGN_F_MMIO2_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7118 *phRegion, pfnMapUnmap);
7119 return rc;
7120}
7121
7122/**
7123 * @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7124 */
7125DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7126 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7127{
7128 return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7129}
7130
7131/**
7132 * @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7133 */
7134DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7135 unsigned cb, uint32_t *pu32Value)
7136{
7137 return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7138}
7139
7140/**
7141 * @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7142 */
7143DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7144 unsigned cb, uint32_t u32Value)
7145{
7146 return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7147}
7148
7149#endif /* IN_RING3 */
7150
7151/**
7152 * Bus master physical memory read from the default PCI device.
7153 *
7154 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7155 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7156 * @param pDevIns The device instance.
7157 * @param GCPhys Physical address start reading from.
7158 * @param pvBuf Where to put the read bits.
7159 * @param cbRead How many bytes to read.
7160 * @thread Any thread, but the call may involve the emulation thread.
7161 */
7162DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7163{
7164 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7165}
7166
7167/**
7168 * Bus master physical memory read - unknown data usage.
7169 *
7170 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7171 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7172 * @param pDevIns The device instance.
7173 * @param pPciDev The PCI device structure. If NULL the default
7174 * PCI device for this device instance is used.
7175 * @param GCPhys Physical address start reading from.
7176 * @param pvBuf Where to put the read bits.
7177 * @param cbRead How many bytes to read.
7178 * @thread Any thread, but the call may involve the emulation thread.
7179 */
7180DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7181{
7182 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7183}
7184
7185/**
7186 * Bus master physical memory read from the default PCI device.
7187 *
7188 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7189 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7190 * @param pDevIns The device instance.
7191 * @param GCPhys Physical address start reading from.
7192 * @param pvBuf Where to put the read bits.
7193 * @param cbRead How many bytes to read.
7194 * @thread Any thread, but the call may involve the emulation thread.
7195 */
7196DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7197{
7198 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7199}
7200
7201/**
7202 * Bus master physical memory read - reads meta data processed by the device.
7203 *
7204 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7205 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7206 * @param pDevIns The device instance.
7207 * @param pPciDev The PCI device structure. If NULL the default
7208 * PCI device for this device instance is used.
7209 * @param GCPhys Physical address start reading from.
7210 * @param pvBuf Where to put the read bits.
7211 * @param cbRead How many bytes to read.
7212 * @thread Any thread, but the call may involve the emulation thread.
7213 */
7214DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7215{
7216 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7217}
7218
7219/**
7220 * Bus master physical memory read from the default PCI device - read data will not be touched by the device.
7221 *
7222 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7223 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7224 * @param pDevIns The device instance.
7225 * @param GCPhys Physical address start reading from.
7226 * @param pvBuf Where to put the read bits.
7227 * @param cbRead How many bytes to read.
7228 * @thread Any thread, but the call may involve the emulation thread.
7229 */
7230DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7231{
7232 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7233}
7234
7235/**
7236 * Bus master physical memory read - read data will not be touched by the device.
7237 *
7238 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7239 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7240 * @param pDevIns The device instance.
7241 * @param pPciDev The PCI device structure. If NULL the default
7242 * PCI device for this device instance is used.
7243 * @param GCPhys Physical address start reading from.
7244 * @param pvBuf Where to put the read bits.
7245 * @param cbRead How many bytes to read.
7246 * @thread Any thread, but the call may involve the emulation thread.
7247 */
7248DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7249{
7250 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7251}
7252
7253/**
7254 * Bus master physical memory write from the default PCI device - unknown data usage.
7255 *
7256 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7257 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7258 * @param pDevIns The device instance.
7259 * @param GCPhys Physical address to write to.
7260 * @param pvBuf What to write.
7261 * @param cbWrite How many bytes to write.
7262 * @thread Any thread, but the call may involve the emulation thread.
7263 */
7264DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7265{
7266 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7267}
7268
7269/**
7270 * Bus master physical memory write - unknown data usage.
7271 *
7272 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7273 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7274 * @param pDevIns The device instance.
7275 * @param pPciDev The PCI device structure. If NULL the default
7276 * PCI device for this device instance is used.
7277 * @param GCPhys Physical address to write to.
7278 * @param pvBuf What to write.
7279 * @param cbWrite How many bytes to write.
7280 * @thread Any thread, but the call may involve the emulation thread.
7281 */
7282DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7283{
7284 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7285}
7286
7287/**
7288 * Bus master physical memory write from the default PCI device.
7289 *
7290 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7291 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7292 * @param pDevIns The device instance.
7293 * @param GCPhys Physical address to write to.
7294 * @param pvBuf What to write.
7295 * @param cbWrite How many bytes to write.
7296 * @thread Any thread, but the call may involve the emulation thread.
7297 */
7298DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7299{
7300 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7301}
7302
7303/**
7304 * Bus master physical memory write - written data was created/altered by the device.
7305 *
7306 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7307 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7308 * @param pDevIns The device instance.
7309 * @param pPciDev The PCI device structure. If NULL the default
7310 * PCI device for this device instance is used.
7311 * @param GCPhys Physical address to write to.
7312 * @param pvBuf What to write.
7313 * @param cbWrite How many bytes to write.
7314 * @thread Any thread, but the call may involve the emulation thread.
7315 */
7316DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7317{
7318 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7319}
7320
7321/**
7322 * Bus master physical memory write from the default PCI device.
7323 *
7324 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7325 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7326 * @param pDevIns The device instance.
7327 * @param GCPhys Physical address to write to.
7328 * @param pvBuf What to write.
7329 * @param cbWrite How many bytes to write.
7330 * @thread Any thread, but the call may involve the emulation thread.
7331 */
7332DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7333{
7334 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7335}
7336
7337/**
7338 * Bus master physical memory write - written data was not touched/created by the device.
7339 *
7340 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7341 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7342 * @param pDevIns The device instance.
7343 * @param pPciDev The PCI device structure. If NULL the default
7344 * PCI device for this device instance is used.
7345 * @param GCPhys Physical address to write to.
7346 * @param pvBuf What to write.
7347 * @param cbWrite How many bytes to write.
7348 * @thread Any thread, but the call may involve the emulation thread.
7349 */
7350DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7351{
7352 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7353}
7354
7355#ifdef IN_RING3
7356/**
7357 * @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
7358 */
7359DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7360 void **ppv, PPGMPAGEMAPLOCK pLock)
7361{
7362 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7363}
7364
7365/**
7366 * @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
7367 */
7368DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7369 void const **ppv, PPGMPAGEMAPLOCK pLock)
7370{
7371 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7372}
7373
7374/**
7375 * @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
7376 */
7377DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7378 PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
7379 PPGMPAGEMAPLOCK paLocks)
7380{
7381 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
7382 paLocks);
7383}
7384
7385/**
7386 * @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
7387 */
7388DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7389 PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
7390 PPGMPAGEMAPLOCK paLocks)
7391{
7392 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
7393 papvPages, paLocks);
7394}
7395#endif /* IN_RING3 */
7396
7397/**
7398 * Sets the IRQ for the default PCI device.
7399 *
7400 * @param pDevIns The device instance.
7401 * @param iIrq IRQ number to set.
7402 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7403 * @thread Any thread, but will involve the emulation thread.
7404 */
7405DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7406{
7407 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7408}
7409
7410/**
7411 * @copydoc PDMDEVHLPR3::pfnPCISetIrq
7412 */
7413DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7414{
7415 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7416}
7417
7418/**
7419 * Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7420 * the request when not called from EMT.
7421 *
7422 * @param pDevIns The device instance.
7423 * @param iIrq IRQ number to set.
7424 * @param iLevel IRQ level.
7425 * @thread Any thread, but will involve the emulation thread.
7426 */
7427DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7428{
7429 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7430}
7431
7432/**
7433 * @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7434 */
7435DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7436{
7437 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7438}
7439
7440/**
7441 * @copydoc PDMDEVHLPR3::pfnISASetIrq
7442 */
7443DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7444{
7445 pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7446}
7447
7448/**
7449 * @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7450 */
7451DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7452{
7453 pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7454}
7455
7456#ifdef IN_RING3
7457
7458/**
7459 * @copydoc PDMDEVHLPR3::pfnDriverAttach
7460 */
7461DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE *ppBaseInterface, const char *pszDesc)
7462{
7463 return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7464}
7465
7466/**
7467 * @copydoc PDMDEVHLPR3::pfnDriverDetach
7468 */
7469DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7470{
7471 return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7472}
7473
7474/**
7475 * @copydoc PDMDEVHLPR3::pfnDriverReconfigure
7476 */
7477DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
7478 const char * const *papszDrivers, PCFGMNODE *papConfigs, uint32_t fFlags)
7479{
7480 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
7481}
7482
7483/**
7484 * Reconfigures with a single driver reattachement, no config, noflags.
7485 * @sa PDMDevHlpDriverReconfigure
7486 */
7487DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
7488{
7489 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
7490}
7491
7492/**
7493 * Reconfigures with a two drivers reattachement, no config, noflags.
7494 * @sa PDMDevHlpDriverReconfigure
7495 */
7496DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0, const char *pszDriver1)
7497{
7498 char const * apszDrivers[2];
7499 apszDrivers[0] = pszDriver0;
7500 apszDrivers[1] = pszDriver1;
7501 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
7502}
7503
7504/**
7505 * @copydoc PDMDEVHLPR3::pfnQueueCreatePtr
7506 */
7507DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7508 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName, PPDMQUEUE *ppQueue)
7509{
7510 return pDevIns->pHlpR3->pfnQueueCreatePtr(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
7511}
7512
7513/**
7514 * @copydoc PDMDEVHLPR3::pfnQueueCreate
7515 */
7516DECLINLINE(int) PDMDevHlpQueueCreateNew(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7517 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName, PDMQUEUEHANDLE *phQueue)
7518{
7519 return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7520}
7521
7522#endif /* IN_RING3 */
7523
7524/**
7525 * @copydoc PDMDEVHLPR3::pfnQueueAlloc
7526 */
7527DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7528{
7529 return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7530}
7531
7532/**
7533 * @copydoc PDMDEVHLPR3::pfnQueueInsert
7534 */
7535DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7536{
7537 pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7538}
7539
7540/**
7541 * @copydoc PDMDEVHLPR3::pfnQueueInsertEx
7542 */
7543DECLINLINE(void) PDMDevHlpQueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay)
7544{
7545 pDevIns->CTX_SUFF(pHlp)->pfnQueueInsertEx(pDevIns, hQueue, pItem, cNanoMaxDelay);
7546}
7547
7548/**
7549 * @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7550 */
7551DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7552{
7553 return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7554}
7555
7556#ifdef IN_RING3
7557/**
7558 * @copydoc PDMDEVHLPR3::pfnTaskCreate
7559 */
7560DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7561 PFNPDMTASKDEV pfnCallback, void *pvUser, PDMTASKHANDLE *phTask)
7562{
7563 return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7564}
7565#endif
7566
7567/**
7568 * @copydoc PDMDEVHLPR3::pfnTaskTrigger
7569 */
7570DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7571{
7572 return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7573}
7574
7575#ifdef IN_RING3
7576
7577/**
7578 * @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7579 */
7580DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7581{
7582 return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7583}
7584
7585/**
7586 * @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7587 */
7588DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7589{
7590 return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7591}
7592
7593#endif /* IN_RING3 */
7594
7595/**
7596 * @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7597 */
7598DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7599{
7600 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7601}
7602
7603/**
7604 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7605 */
7606DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7607{
7608 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7609}
7610
7611/**
7612 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7613 */
7614DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7615{
7616 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7617}
7618
7619/**
7620 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7621 */
7622DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7623{
7624 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7625}
7626
7627/**
7628 * @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7629 */
7630DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7631{
7632 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7633}
7634
7635#ifdef IN_RING3
7636
7637/**
7638 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7639 */
7640DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7641{
7642 return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7643}
7644
7645/**
7646 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7647 */
7648DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7649{
7650 return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7651}
7652
7653#endif /* IN_RING3 */
7654
7655/**
7656 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7657 */
7658DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7659{
7660 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7661}
7662
7663/**
7664 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7665 */
7666DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7667{
7668 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7669}
7670
7671/**
7672 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7673 */
7674DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7675{
7676 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7677}
7678
7679/**
7680 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7681 */
7682DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7683{
7684 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7685}
7686
7687/**
7688 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7689 */
7690DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7691{
7692 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7693}
7694
7695/**
7696 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7697 */
7698DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7699{
7700 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7701}
7702
7703#ifdef IN_RING3
7704
7705/**
7706 * Initializes a PDM critical section.
7707 *
7708 * The PDM critical sections are derived from the IPRT critical sections, but
7709 * works in RC and R0 as well.
7710 *
7711 * @returns VBox status code.
7712 * @param pDevIns The device instance.
7713 * @param pCritSect Pointer to the critical section.
7714 * @param SRC_POS Use RT_SRC_POS.
7715 * @param pszNameFmt Format string for naming the critical section.
7716 * For statistics and lock validation.
7717 * @param ... Arguments for the format string.
7718 */
7719DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7720 const char *pszNameFmt, ...)
7721{
7722 int rc;
7723 va_list va;
7724 va_start(va, pszNameFmt);
7725 rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7726 va_end(va);
7727 return rc;
7728}
7729
7730#endif /* IN_RING3 */
7731
7732/**
7733 * @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7734 */
7735DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7736{
7737 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7738}
7739
7740#ifdef IN_RING3
7741
7742/**
7743 * @copydoc PDMDEVHLPR3::pfnCritSectGetNopR0
7744 */
7745DECLINLINE(R0PTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopR0(PPDMDEVINS pDevIns)
7746{
7747 return pDevIns->pHlpR3->pfnCritSectGetNopR0(pDevIns);
7748}
7749
7750/**
7751 * @copydoc PDMDEVHLPR3::pfnCritSectGetNopRC
7752 */
7753DECLINLINE(RCPTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopRC(PPDMDEVINS pDevIns)
7754{
7755 return pDevIns->pHlpR3->pfnCritSectGetNopRC(pDevIns);
7756}
7757
7758#endif /* IN_RING3 */
7759
7760/**
7761 * @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7762 */
7763DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7764{
7765 return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7766}
7767
7768/**
7769 * @copydoc PDMCritSectEnter
7770 * @param pDevIns The device instance.
7771 */
7772DECLINLINE(int) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7773{
7774 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7775}
7776
7777/**
7778 * @copydoc PDMCritSectEnterDebug
7779 * @param pDevIns The device instance.
7780 */
7781DECLINLINE(int) PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7782{
7783 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7784}
7785
7786/**
7787 * @copydoc PDMCritSectTryEnter
7788 * @param pDevIns The device instance.
7789 */
7790DECLINLINE(int) PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7791{
7792 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7793}
7794
7795/**
7796 * @copydoc PDMCritSectTryEnterDebug
7797 * @param pDevIns The device instance.
7798 */
7799DECLINLINE(int) PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7800{
7801 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7802}
7803
7804/**
7805 * @copydoc PDMCritSectLeave
7806 * @param pDevIns The device instance.
7807 */
7808DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7809{
7810 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7811}
7812
7813/**
7814 * @copydoc PDMCritSectIsOwner
7815 * @param pDevIns The device instance.
7816 */
7817DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7818{
7819 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7820}
7821
7822/**
7823 * @copydoc PDMCritSectIsInitialized
7824 * @param pDevIns The device instance.
7825 */
7826DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7827{
7828 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
7829}
7830
7831/**
7832 * @copydoc PDMCritSectHasWaiters
7833 * @param pDevIns The device instance.
7834 */
7835DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7836{
7837 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
7838}
7839
7840/**
7841 * @copydoc PDMCritSectGetRecursion
7842 * @param pDevIns The device instance.
7843 */
7844DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7845{
7846 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
7847}
7848
7849#if defined(IN_RING3) || defined(IN_RING0)
7850/**
7851 * @copydoc PDMHCCritSectScheduleExitEvent
7852 * @param pDevIns The device instance.
7853 */
7854DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
7855{
7856 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
7857}
7858#endif
7859
7860/* Strict build: Remap the two enter calls to the debug versions. */
7861#ifdef VBOX_STRICT
7862# ifdef IPRT_INCLUDED_asm_h
7863# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7864# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7865# else
7866# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
7867# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
7868# endif
7869#endif
7870
7871#if defined(IN_RING3) || defined(DOXYGEN_RUNNING)
7872
7873/**
7874 * @copydoc PDMR3CritSectDelete
7875 * @param pDevIns The device instance.
7876 */
7877DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7878{
7879 return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
7880}
7881
7882/**
7883 * @copydoc PDMDEVHLPR3::pfnThreadCreate
7884 */
7885DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
7886 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
7887{
7888 return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
7889}
7890
7891/**
7892 * @copydoc PDMR3ThreadDestroy
7893 * @param pDevIns The device instance.
7894 */
7895DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
7896{
7897 return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
7898}
7899
7900/**
7901 * @copydoc PDMR3ThreadIAmSuspending
7902 * @param pDevIns The device instance.
7903 */
7904DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7905{
7906 return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
7907}
7908
7909/**
7910 * @copydoc PDMR3ThreadIAmRunning
7911 * @param pDevIns The device instance.
7912 */
7913DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7914{
7915 return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
7916}
7917
7918/**
7919 * @copydoc PDMR3ThreadSleep
7920 * @param pDevIns The device instance.
7921 */
7922DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
7923{
7924 return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
7925}
7926
7927/**
7928 * @copydoc PDMR3ThreadSuspend
7929 * @param pDevIns The device instance.
7930 */
7931DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7932{
7933 return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
7934}
7935
7936/**
7937 * @copydoc PDMR3ThreadResume
7938 * @param pDevIns The device instance.
7939 */
7940DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7941{
7942 return pDevIns->pHlpR3->pfnThreadResume(pThread);
7943}
7944
7945/**
7946 * @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
7947 */
7948DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
7949{
7950 return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
7951}
7952
7953/**
7954 * @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
7955 */
7956DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
7957{
7958 pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
7959}
7960
7961/**
7962 * @copydoc PDMDEVHLPR3::pfnA20Set
7963 */
7964DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
7965{
7966 pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
7967}
7968
7969/**
7970 * @copydoc PDMDEVHLPR3::pfnRTCRegister
7971 */
7972DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
7973{
7974 return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
7975}
7976
7977/**
7978 * @copydoc PDMDEVHLPR3::pfnPCIBusRegister
7979 */
7980DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus)
7981{
7982 return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
7983}
7984
7985/**
7986 * @copydoc PDMDEVHLPR3::pfnIommuRegister
7987 */
7988DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp, uint32_t *pidxIommu)
7989{
7990 return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
7991}
7992
7993/**
7994 * @copydoc PDMDEVHLPR3::pfnPICRegister
7995 */
7996DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
7997{
7998 return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
7999}
8000
8001/**
8002 * @copydoc PDMDEVHLPR3::pfnApicRegister
8003 */
8004DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
8005{
8006 return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
8007}
8008
8009/**
8010 * @copydoc PDMDEVHLPR3::pfnIoApicRegister
8011 */
8012DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8013{
8014 return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
8015}
8016
8017/**
8018 * @copydoc PDMDEVHLPR3::pfnHpetRegister
8019 */
8020DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
8021{
8022 return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
8023}
8024
8025/**
8026 * @copydoc PDMDEVHLPR3::pfnPciRawRegister
8027 */
8028DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
8029{
8030 return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
8031}
8032
8033/**
8034 * @copydoc PDMDEVHLPR3::pfnDMACRegister
8035 */
8036DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
8037{
8038 return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
8039}
8040
8041/**
8042 * @copydoc PDMDEVHLPR3::pfnDMARegister
8043 */
8044DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
8045{
8046 return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
8047}
8048
8049/**
8050 * @copydoc PDMDEVHLPR3::pfnDMAReadMemory
8051 */
8052DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead)
8053{
8054 return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
8055}
8056
8057/**
8058 * @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
8059 */
8060DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten)
8061{
8062 return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
8063}
8064
8065/**
8066 * @copydoc PDMDEVHLPR3::pfnDMASetDREQ
8067 */
8068DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
8069{
8070 return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
8071}
8072
8073/**
8074 * @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
8075 */
8076DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
8077{
8078 return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
8079}
8080
8081/**
8082 * @copydoc PDMDEVHLPR3::pfnDMASchedule
8083 */
8084DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
8085{
8086 pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
8087}
8088
8089/**
8090 * @copydoc PDMDEVHLPR3::pfnCMOSWrite
8091 */
8092DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
8093{
8094 return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
8095}
8096
8097/**
8098 * @copydoc PDMDEVHLPR3::pfnCMOSRead
8099 */
8100DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
8101{
8102 return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
8103}
8104
8105/**
8106 * @copydoc PDMDEVHLPR3::pfnCallR0
8107 */
8108DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
8109{
8110 return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
8111}
8112
8113/**
8114 * @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
8115 */
8116DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
8117{
8118 return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
8119}
8120
8121/**
8122 * @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
8123 */
8124DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
8125{
8126 return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
8127}
8128
8129/**
8130 * @copydoc PDMDEVHLPR3::pfnGetUVM
8131 */
8132DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
8133{
8134 return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
8135}
8136
8137#endif /* IN_RING3 || DOXYGEN_RUNNING */
8138
8139#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
8140
8141/**
8142 * @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
8143 */
8144DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
8145{
8146 return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
8147}
8148
8149/**
8150 * @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
8151 */
8152DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
8153{
8154 return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
8155}
8156
8157/**
8158 * @copydoc PDMDEVHLPR0::pfnPICSetUpContext
8159 */
8160DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8161{
8162 return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
8163}
8164
8165/**
8166 * @copydoc PDMDEVHLPR0::pfnApicSetUpContext
8167 */
8168DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
8169{
8170 return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
8171}
8172
8173/**
8174 * @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
8175 */
8176DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8177{
8178 return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
8179}
8180
8181/**
8182 * @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
8183 */
8184DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
8185{
8186 return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
8187}
8188
8189#endif /* !IN_RING3 || DOXYGEN_RUNNING */
8190
8191/**
8192 * @copydoc PDMDEVHLPR3::pfnGetVM
8193 */
8194DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
8195{
8196 return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
8197}
8198
8199/**
8200 * @copydoc PDMDEVHLPR3::pfnGetVMCPU
8201 */
8202DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
8203{
8204 return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
8205}
8206
8207/**
8208 * @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
8209 */
8210DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
8211{
8212 return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
8213}
8214
8215/**
8216 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
8217 */
8218DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
8219{
8220 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
8221}
8222
8223/**
8224 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8225 */
8226DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8227{
8228 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8229}
8230
8231/**
8232 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8233 */
8234DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8235{
8236 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8237}
8238
8239#ifdef IN_RING3
8240
8241/**
8242 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8243 */
8244DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8245{
8246 return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
8247}
8248
8249/**
8250 * @copydoc PDMDEVHLPR3::pfnFirmwareRegister
8251 */
8252DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
8253{
8254 return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
8255}
8256
8257/**
8258 * @copydoc PDMDEVHLPR3::pfnVMReset
8259 */
8260DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
8261{
8262 return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
8263}
8264
8265/**
8266 * @copydoc PDMDEVHLPR3::pfnVMSuspend
8267 */
8268DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8269{
8270 return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8271}
8272
8273/**
8274 * @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8275 */
8276DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8277{
8278 return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8279}
8280
8281/**
8282 * @copydoc PDMDEVHLPR3::pfnVMPowerOff
8283 */
8284DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8285{
8286 return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8287}
8288
8289#endif /* IN_RING3 */
8290
8291/**
8292 * @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8293 */
8294DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8295{
8296 return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8297}
8298
8299#ifdef IN_RING3
8300
8301/**
8302 * @copydoc PDMDEVHLPR3::pfnGetCpuId
8303 */
8304DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
8305{
8306 pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8307}
8308
8309/**
8310 * @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8311 */
8312DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8313{
8314 return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8315}
8316
8317/**
8318 * @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8319 */
8320DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8321{
8322 return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8323}
8324
8325/**
8326 * @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
8327 */
8328DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
8329 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
8330 const char *pszHandlerR0, const char *pszPfHandlerR0,
8331 const char *pszHandlerRC, const char *pszPfHandlerRC,
8332 const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
8333{
8334 return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
8335 pszHandlerR0, pszPfHandlerR0,
8336 pszHandlerRC, pszPfHandlerRC,
8337 pszDesc, phType);
8338}
8339
8340/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
8341# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8342 do { \
8343 uint32_t u32GetEnumTmp = 0; \
8344 int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
8345 AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8346 (a_enmDst) = (a_EnumType)u32GetEnumTmp; \
8347 AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
8348 } while (0)
8349
8350/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
8351# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8352 do { \
8353 uint8_t bGetEnumTmp = 0; \
8354 int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
8355 AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8356 (a_enmDst) = (a_EnumType)bGetEnumTmp; \
8357 } while (0)
8358
8359#endif /* IN_RING3 */
8360
8361/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
8362typedef struct PDMDEVREGCB *PPDMDEVREGCB;
8363
8364/**
8365 * Callbacks for VBoxDeviceRegister().
8366 */
8367typedef struct PDMDEVREGCB
8368{
8369 /** Interface version.
8370 * This is set to PDM_DEVREG_CB_VERSION. */
8371 uint32_t u32Version;
8372
8373 /**
8374 * Registers a device with the current VM instance.
8375 *
8376 * @returns VBox status code.
8377 * @param pCallbacks Pointer to the callback table.
8378 * @param pReg Pointer to the device registration record.
8379 * This data must be permanent and readonly.
8380 */
8381 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
8382} PDMDEVREGCB;
8383
8384/** Current version of the PDMDEVREGCB structure. */
8385#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
8386
8387
8388/**
8389 * The VBoxDevicesRegister callback function.
8390 *
8391 * PDM will invoke this function after loading a device module and letting
8392 * the module decide which devices to register and how to handle conflicts.
8393 *
8394 * @returns VBox status code.
8395 * @param pCallbacks Pointer to the callback table.
8396 * @param u32Version VBox version number.
8397 */
8398typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
8399
8400/** @} */
8401
8402RT_C_DECLS_END
8403
8404#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */
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