pdmdev.h@ 90433

Last change on this file since 90433 was 90433, checked in by vboxsync, 3 years ago
VMM/PDMCritSectEnter: Added macros for correctly asserting on successfull PDMCritSectEnter calls when rcBusy is VINF_SUCCESS or the caller can't return an error. Makes it easier to spot these compared to generic AssertReleaseRC. bugref:6695
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File size: 358.2 KB

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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmqueue.h>
34	#include <VBox/vmm/pdmtask.h>
35	#ifdef IN_RING3
36	# include <VBox/vmm/pdmthread.h>
37	#endif
38	#include <VBox/vmm/pdmifs.h>
39	#include <VBox/vmm/pdmins.h>
40	#include <VBox/vmm/pdmcommon.h>
41	#include <VBox/vmm/pdmpcidev.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/tm.h>
44	#include <VBox/vmm/ssm.h>
45	#include <VBox/vmm/cfgm.h>
46	#include <VBox/vmm/cpum.h>
47	#include <VBox/vmm/dbgf.h>
48	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
49	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
50	#include <VBox/msi.h>
51	#include <iprt/stdarg.h>
52	#include <iprt/list.h>
53
54
55	RT_C_DECLS_BEGIN
56
57	/** @defgroup grp_pdm_device The PDM Devices API
58	* @ingroup grp_pdm
59	* @{
60	*/
61
62	/**
63	* Construct a device instance for a VM.
64	*
65	* @returns VBox status.
66	* @param pDevIns The device instance data. If the registration structure
67	* is needed, it can be accessed thru pDevIns->pReg.
68	* @param iInstance Instance number. Use this to figure out which registers
69	* and such to use. The instance number is also found in
70	* pDevIns->iInstance, but since it's likely to be
71	* frequently used PDM passes it as parameter.
72	* @param pCfg Configuration node handle for the driver. This is
73	* expected to be in high demand in the constructor and is
74	* therefore passed as an argument. When using it at other
75	* times, it can be found in pDevIns->pCfg.
76	*/
77	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
78	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
79	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
80
81	/**
82	* Destruct a device instance.
83	*
84	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
85	* resources can be freed correctly.
86	*
87	* @returns VBox status.
88	* @param pDevIns The device instance data.
89	*
90	* @remarks The device critical section is not entered. The routine may delete
91	* the critical section, so the caller cannot exit it.
92	*/
93	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
94	/** Pointer to a FNPDMDEVDESTRUCT() function. */
95	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
96
97	/**
98	* Device relocation callback.
99	*
100	* This is called when the instance data has been relocated in raw-mode context
101	* (RC). It is also called when the RC hypervisor selects changes. The device
102	* must fixup all necessary pointers and re-query all interfaces to other RC
103	* devices and drivers.
104	*
105	* Before the RC code is executed the first time, this function will be called
106	* with a 0 delta so RC pointer calculations can be one in one place.
107	*
108	* @param pDevIns Pointer to the device instance.
109	* @param offDelta The relocation delta relative to the old location.
110	*
111	* @remarks A relocation CANNOT fail.
112	*
113	* @remarks The device critical section is not entered. The relocations should
114	* not normally require any locking.
115	*/
116	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
117	/** Pointer to a FNPDMDEVRELOCATE() function. */
118	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
119
120	/**
121	* Power On notification.
122	*
123	* @returns VBox status.
124	* @param pDevIns The device instance data.
125	*
126	* @remarks Caller enters the device critical section.
127	*/
128	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
129	/** Pointer to a FNPDMDEVPOWERON() function. */
130	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
131
132	/**
133	* Reset notification.
134	*
135	* @returns VBox status.
136	* @param pDevIns The device instance data.
137	*
138	* @remarks Caller enters the device critical section.
139	*/
140	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
141	/** Pointer to a FNPDMDEVRESET() function. */
142	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
143
144	/**
145	* Soft reset notification.
146	*
147	* This is mainly for emulating the 286 style protected mode exits, in which
148	* most devices should remain in their current state.
149	*
150	* @returns VBox status.
151	* @param pDevIns The device instance data.
152	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
153	*
154	* @remarks Caller enters the device critical section.
155	*/
156	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
157	/** Pointer to a FNPDMDEVSOFTRESET() function. */
158	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
159
160	/** @name PDMVMRESET_F_XXX - VM reset flags.
161	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
162	* reset via PDMDevHlpVMReset.
163	* @{ */
164	/** Unknown reason. */
165	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
166	/** GIM triggered reset. */
167	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
168	/** The last source always causing hard resets. */
169	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
170	/** ACPI triggered reset. */
171	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
172	/** PS/2 system port A (92h) reset. */
173	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
174	/** Keyboard reset. */
175	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
176	/** Tripple fault. */
177	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
178	/** Reset source mask. */
179	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
180	/** @} */
181
182	/**
183	* Suspend notification.
184	*
185	* @returns VBox status.
186	* @param pDevIns The device instance data.
187	* @thread EMT(0)
188	*
189	* @remarks Caller enters the device critical section.
190	*/
191	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
192	/** Pointer to a FNPDMDEVSUSPEND() function. */
193	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
194
195	/**
196	* Resume notification.
197	*
198	* @returns VBox status.
199	* @param pDevIns The device instance data.
200	*
201	* @remarks Caller enters the device critical section.
202	*/
203	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
204	/** Pointer to a FNPDMDEVRESUME() function. */
205	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
206
207	/**
208	* Power Off notification.
209	*
210	* This is always called when VMR3PowerOff is called.
211	* There will be no callback when hot plugging devices.
212	*
213	* @param pDevIns The device instance data.
214	* @thread EMT(0)
215	*
216	* @remarks Caller enters the device critical section.
217	*/
218	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
219	/** Pointer to a FNPDMDEVPOWEROFF() function. */
220	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
221
222	/**
223	* Attach command.
224	*
225	* This is called to let the device attach to a driver for a specified LUN
226	* at runtime. This is not called during VM construction, the device
227	* constructor has to attach to all the available drivers.
228	*
229	* This is like plugging in the keyboard or mouse after turning on the PC.
230	*
231	* @returns VBox status code.
232	* @param pDevIns The device instance.
233	* @param iLUN The logical unit which is being attached.
234	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
235	*
236	* @remarks Caller enters the device critical section.
237	*/
238	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
239	/** Pointer to a FNPDMDEVATTACH() function. */
240	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
241
242	/**
243	* Detach notification.
244	*
245	* This is called when a driver is detaching itself from a LUN of the device.
246	* The device should adjust its state to reflect this.
247	*
248	* This is like unplugging the network cable to use it for the laptop or
249	* something while the PC is still running.
250	*
251	* @param pDevIns The device instance.
252	* @param iLUN The logical unit which is being detached.
253	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
254	*
255	* @remarks Caller enters the device critical section.
256	*/
257	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
258	/** Pointer to a FNPDMDEVDETACH() function. */
259	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
260
261	/**
262	* Query the base interface of a logical unit.
263	*
264	* @returns VBOX status code.
265	* @param pDevIns The device instance.
266	* @param iLUN The logicial unit to query.
267	* @param ppBase Where to store the pointer to the base interface of the LUN.
268	*
269	* @remarks The device critical section is not entered.
270	*/
271	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
272	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
273	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
274
275	/**
276	* Init complete notification (after ring-0 & RC init since 5.1).
277	*
278	* This can be done to do communication with other devices and other
279	* initialization which requires everything to be in place.
280	*
281	* @returns VBOX status code.
282	* @param pDevIns The device instance.
283	*
284	* @remarks Caller enters the device critical section.
285	*/
286	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
287	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
288	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
289
290
291	/**
292	* The context of a pfnMemSetup call.
293	*/
294	typedef enum PDMDEVMEMSETUPCTX
295	{
296	/** Invalid zero value. */
297	PDMDEVMEMSETUPCTX_INVALID = 0,
298	/** After construction. */
299	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
300	/** After reset. */
301	PDMDEVMEMSETUPCTX_AFTER_RESET,
302	/** Type size hack. */
303	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
304	} PDMDEVMEMSETUPCTX;
305
306
307	/**
308	* PDM Device Registration Structure.
309	*
310	* This structure is used when registering a device from VBoxInitDevices() in HC
311	* Ring-3. PDM will continue use till the VM is terminated.
312	*
313	* @note The first part is the same in every context.
314	*/
315	typedef struct PDMDEVREGR3
316	{
317	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
318	uint32_t u32Version;
319	/** Reserved, must be zero. */
320	uint32_t uReserved0;
321	/** Device name, must match the ring-3 one. */
322	char szName[32];
323	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
324	uint32_t fFlags;
325	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
326	uint32_t fClass;
327	/** Maximum number of instances (per VM). */
328	uint32_t cMaxInstances;
329	/** The shared data structure version number. */
330	uint32_t uSharedVersion;
331	/** Size of the instance data. */
332	uint32_t cbInstanceShared;
333	/** Size of the ring-0 instance data. */
334	uint32_t cbInstanceCC;
335	/** Size of the raw-mode instance data. */
336	uint32_t cbInstanceRC;
337	/** Max number of PCI devices. */
338	uint16_t cMaxPciDevices;
339	/** Max number of MSI-X vectors in any of the PCI devices. */
340	uint16_t cMaxMsixVectors;
341	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
342	* remain unchanged from registration till VM destruction. */
343	const char *pszDescription;
344
345	/** Name of the raw-mode context module (no path).
346	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
347	const char *pszRCMod;
348	/** Name of the ring-0 module (no path).
349	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
350	const char *pszR0Mod;
351
352	/** Construct instance - required. */
353	PFNPDMDEVCONSTRUCT pfnConstruct;
354	/** Destruct instance - optional.
355	* Critical section NOT entered (will be destroyed). */
356	PFNPDMDEVDESTRUCT pfnDestruct;
357	/** Relocation command - optional.
358	* Critical section NOT entered. */
359	PFNPDMDEVRELOCATE pfnRelocate;
360	/**
361	* Memory setup callback.
362	*
363	* @param pDevIns The device instance data.
364	* @param enmCtx Indicates the context of the call.
365	* @remarks The critical section is entered prior to calling this method.
366	*/
367	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
368	/** Power on notification - optional.
369	* Critical section is entered. */
370	PFNPDMDEVPOWERON pfnPowerOn;
371	/** Reset notification - optional.
372	* Critical section is entered. */
373	PFNPDMDEVRESET pfnReset;
374	/** Suspend notification - optional.
375	* Critical section is entered. */
376	PFNPDMDEVSUSPEND pfnSuspend;
377	/** Resume notification - optional.
378	* Critical section is entered. */
379	PFNPDMDEVRESUME pfnResume;
380	/** Attach command - optional.
381	* Critical section is entered. */
382	PFNPDMDEVATTACH pfnAttach;
383	/** Detach notification - optional.
384	* Critical section is entered. */
385	PFNPDMDEVDETACH pfnDetach;
386	/** Query a LUN base interface - optional.
387	* Critical section is NOT entered. */
388	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
389	/** Init complete notification - optional.
390	* Critical section is entered. */
391	PFNPDMDEVINITCOMPLETE pfnInitComplete;
392	/** Power off notification - optional.
393	* Critical section is entered. */
394	PFNPDMDEVPOWEROFF pfnPowerOff;
395	/** Software system reset notification - optional.
396	* Critical section is entered. */
397	PFNPDMDEVSOFTRESET pfnSoftReset;
398
399	/** @name Reserved for future extensions, must be zero.
400	* @{ */
401	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
402	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
403	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
406	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
407	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
408	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
409	/** @} */
410
411	/** Initialization safty marker. */
412	uint32_t u32VersionEnd;
413	} PDMDEVREGR3;
414	/** Pointer to a PDM Device Structure. */
415	typedef PDMDEVREGR3 *PPDMDEVREGR3;
416	/** Const pointer to a PDM Device Structure. */
417	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
418	/** Current DEVREGR3 version number. */
419	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
420
421
422	/** PDM Device Flags.
423	* @{ */
424	/** This flag is used to indicate that the device has a R0 component. */
425	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
426	/** Requires the ring-0 component, ignore configuration values. */
427	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
428	/** Requires the ring-0 component, ignore configuration values. */
429	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
430
431	/** This flag is used to indicate that the device has a RC component. */
432	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
433	/** Requires the raw-mode component, ignore configuration values. */
434	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
435	/** Requires the raw-mode component, ignore configuration values. */
436	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
437
438	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
439	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
440
441	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
442	* The bit count for the current host.
443	* @note Superfluous, but still around for hysterical raisins. */
444	#if HC_ARCH_BITS == 32
445	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
446	#elif HC_ARCH_BITS == 64
447	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
448	#else
449	# error Unsupported HC_ARCH_BITS value.
450	#endif
451	/** The host bit count mask. */
452	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
453
454	/** The device support only 32-bit guests. */
455	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
456	/** The device support only 64-bit guests. */
457	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
458	/** The device support both 32-bit & 64-bit guests. */
459	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
460	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
461	* The guest bit count for the current compilation. */
462	#if GC_ARCH_BITS == 32
463	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
464	#elif GC_ARCH_BITS == 64
465	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
466	#else
467	# error Unsupported GC_ARCH_BITS value.
468	#endif
469	/** The guest bit count mask. */
470	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
471
472	/** A convenience. */
473	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
474
475	/** Indicates that the device needs to be notified before the drivers when suspending. */
476	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
477	/** Indicates that the device needs to be notified before the drivers when powering off. */
478	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
479	/** Indicates that the device needs to be notified before the drivers when resetting. */
480	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
481
482	/** This flag is used to indicate that the device has been converted to the
483	* new device style. */
484	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
485
486	/** @} */
487
488
489	/** PDM Device Classes.
490	* The order is important, lower bit earlier instantiation.
491	* @{ */
492	/** Architecture device. */
493	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
494	/** Architecture BIOS device. */
495	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
496	/** PCI bus brigde. */
497	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
498	/** PCI built-in device (e.g. PCI root complex devices). */
499	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
500	/** Input device (mouse, keyboard, joystick, HID, ...). */
501	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
502	/** Interrupt controller (PIC). */
503	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
504	/** Interval controoler (PIT). */
505	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
506	/** RTC/CMOS. */
507	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
508	/** DMA controller. */
509	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
510	/** VMM Device. */
511	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
512	/** Graphics device, like VGA. */
513	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
514	/** Storage controller device. */
515	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
516	/** Network interface controller. */
517	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
518	/** Audio. */
519	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
520	/** USB HIC. */
521	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
522	/** ACPI. */
523	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
524	/** Serial controller device. */
525	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
526	/** Parallel controller device */
527	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
528	/** Host PCI pass-through device */
529	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
530	/** Misc devices (always last). */
531	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
532	/** @} */
533
534
535	/**
536	* PDM Device Registration Structure, ring-0.
537	*
538	* This structure is used when registering a device from VBoxInitDevices() in HC
539	* Ring-0. PDM will continue use till the VM is terminated.
540	*/
541	typedef struct PDMDEVREGR0
542	{
543	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
544	uint32_t u32Version;
545	/** Reserved, must be zero. */
546	uint32_t uReserved0;
547	/** Device name, must match the ring-3 one. */
548	char szName[32];
549	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
550	uint32_t fFlags;
551	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
552	uint32_t fClass;
553	/** Maximum number of instances (per VM). */
554	uint32_t cMaxInstances;
555	/** The shared data structure version number. */
556	uint32_t uSharedVersion;
557	/** Size of the instance data. */
558	uint32_t cbInstanceShared;
559	/** Size of the ring-0 instance data. */
560	uint32_t cbInstanceCC;
561	/** Size of the raw-mode instance data. */
562	uint32_t cbInstanceRC;
563	/** Max number of PCI devices. */
564	uint16_t cMaxPciDevices;
565	/** Max number of MSI-X vectors in any of the PCI devices. */
566	uint16_t cMaxMsixVectors;
567	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
568	* remain unchanged from registration till VM destruction. */
569	const char *pszDescription;
570
571	/**
572	* Early construction callback (optional).
573	*
574	* This is called right after the device instance structure has been allocated
575	* and before the ring-3 constructor gets called.
576	*
577	* @returns VBox status code.
578	* @param pDevIns The device instance data.
579	* @note The destructure is always called, regardless of the return status.
580	*/
581	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
582
583	/**
584	* Regular construction callback (optional).
585	*
586	* This is called after (or during) the ring-3 constructor.
587	*
588	* @returns VBox status code.
589	* @param pDevIns The device instance data.
590	* @note The destructure is always called, regardless of the return status.
591	*/
592	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
593
594	/**
595	* Destructor (optional).
596	*
597	* This is called after the ring-3 destruction. This is not called if ring-3
598	* fails to trigger it (e.g. process is killed or crashes).
599	*
600	* @param pDevIns The device instance data.
601	*/
602	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
603
604	/**
605	* Final destructor (optional).
606	*
607	* This is called right before the memory is freed, which happens when the
608	* VM/GVM object is destroyed. This is always called.
609	*
610	* @param pDevIns The device instance data.
611	*/
612	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
613
614	/**
615	* Generic request handler (optional).
616	*
617	* @param pDevIns The device instance data.
618	* @param uReq Device specific request.
619	* @param uArg Request argument.
620	*/
621	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
622
623	/** @name Reserved for future extensions, must be zero.
624	* @{ */
625	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
626	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
627	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
630	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
631	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
632	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
633	/** @} */
634
635	/** Initialization safty marker. */
636	uint32_t u32VersionEnd;
637	} PDMDEVREGR0;
638	/** Pointer to a ring-0 PDM device registration structure. */
639	typedef PDMDEVREGR0 *PPDMDEVREGR0;
640	/** Pointer to a const ring-0 PDM device registration structure. */
641	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
642	/** Current DEVREGR0 version number. */
643	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
644
645
646	/**
647	* PDM Device Registration Structure, raw-mode
648	*
649	* At the moment, this structure is mostly here to match the other two contexts.
650	*/
651	typedef struct PDMDEVREGRC
652	{
653	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
654	uint32_t u32Version;
655	/** Reserved, must be zero. */
656	uint32_t uReserved0;
657	/** Device name, must match the ring-3 one. */
658	char szName[32];
659	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
660	uint32_t fFlags;
661	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
662	uint32_t fClass;
663	/** Maximum number of instances (per VM). */
664	uint32_t cMaxInstances;
665	/** The shared data structure version number. */
666	uint32_t uSharedVersion;
667	/** Size of the instance data. */
668	uint32_t cbInstanceShared;
669	/** Size of the ring-0 instance data. */
670	uint32_t cbInstanceCC;
671	/** Size of the raw-mode instance data. */
672	uint32_t cbInstanceRC;
673	/** Max number of PCI devices. */
674	uint16_t cMaxPciDevices;
675	/** Max number of MSI-X vectors in any of the PCI devices. */
676	uint16_t cMaxMsixVectors;
677	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
678	* remain unchanged from registration till VM destruction. */
679	const char *pszDescription;
680
681	/**
682	* Constructor callback.
683	*
684	* This is called much later than both the ring-0 and ring-3 constructors, since
685	* raw-mode v2 require a working VMM to run actual code.
686	*
687	* @returns VBox status code.
688	* @param pDevIns The device instance data.
689	* @note The destructure is always called, regardless of the return status.
690	*/
691	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
692
693	/** @name Reserved for future extensions, must be zero.
694	* @{ */
695	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
696	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
697	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
700	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
701	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
702	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
703	/** @} */
704
705	/** Initialization safty marker. */
706	uint32_t u32VersionEnd;
707	} PDMDEVREGRC;
708	/** Pointer to a raw-mode PDM device registration structure. */
709	typedef PDMDEVREGRC *PPDMDEVREGRC;
710	/** Pointer to a const raw-mode PDM device registration structure. */
711	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
712	/** Current DEVREGRC version number. */
713	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
714
715
716
717	/** @def PDM_DEVREG_VERSION
718	* Current DEVREG version number. */
719	/** @typedef PDMDEVREGR3
720	* A current context PDM device registration structure. */
721	/** @typedef PPDMDEVREGR3
722	* Pointer to a current context PDM device registration structure. */
723	/** @typedef PCPDMDEVREGR3
724	* Pointer to a const current context PDM device registration structure. */
725	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
726	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
727	typedef PDMDEVREGR3 PDMDEVREG;
728	typedef PPDMDEVREGR3 PPDMDEVREG;
729	typedef PCPDMDEVREGR3 PCPDMDEVREG;
730	#elif defined(IN_RING0)
731	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
732	typedef PDMDEVREGR0 PDMDEVREG;
733	typedef PPDMDEVREGR0 PPDMDEVREG;
734	typedef PCPDMDEVREGR0 PCPDMDEVREG;
735	#elif defined(IN_RC)
736	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
737	typedef PDMDEVREGRC PDMDEVREG;
738	typedef PPDMDEVREGRC PPDMDEVREG;
739	typedef PCPDMDEVREGRC PCPDMDEVREG;
740	#else
741	# error "Not IN_RING3, IN_RING0 or IN_RC"
742	#endif
743
744
745	/**
746	* Device registrations for ring-0 modules.
747	*
748	* This structure is used directly and must therefore reside in persistent
749	* memory (i.e. the data section).
750	*/
751	typedef struct PDMDEVMODREGR0
752	{
753	/** The structure version (PDM_DEVMODREGR0_VERSION). */
754	uint32_t u32Version;
755	/** Number of devices in the array papDevRegs points to. */
756	uint32_t cDevRegs;
757	/** Pointer to device registration structures. */
758	PCPDMDEVREGR0 *papDevRegs;
759	/** The ring-0 module handle - PDM internal, fingers off. */
760	void *hMod;
761	/** List entry - PDM internal, fingers off. */
762	RTLISTNODE ListEntry;
763	} PDMDEVMODREGR0;
764	/** Pointer to device registriations for a ring-0 module. */
765	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
766	/** Current PDMDEVMODREGR0 version number. */
767	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
768
769
770	/** @name IRQ Level for use with the *SetIrq APIs.
771	* @{
772	*/
773	/** Assert the IRQ (can assume value 1). */
774	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
775	/** Deassert the IRQ (can assume value 0). */
776	#define PDM_IRQ_LEVEL_LOW 0
777	/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
778	* automatically deasserts it after delivery to the APIC (IOAPIC).
779	* @note Only suitable for edge trigger interrupts. */
780	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
781	/** @} */
782
783	/**
784	* Registration record for MSI/MSI-X emulation.
785	*/
786	typedef struct PDMMSIREG
787	{
788	/** Number of MSI interrupt vectors, 0 if MSI not supported */
789	uint16_t cMsiVectors;
790	/** Offset of MSI capability */
791	uint8_t iMsiCapOffset;
792	/** Offset of next capability to MSI */
793	uint8_t iMsiNextOffset;
794	/** If we support 64-bit MSI addressing */
795	bool fMsi64bit;
796	/** If we do not support per-vector masking */
797	bool fMsiNoMasking;
798
799	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
800	uint16_t cMsixVectors;
801	/** Offset of MSI-X capability */
802	uint8_t iMsixCapOffset;
803	/** Offset of next capability to MSI-X */
804	uint8_t iMsixNextOffset;
805	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
806	uint8_t iMsixBar;
807	} PDMMSIREG;
808	typedef PDMMSIREG *PPDMMSIREG;
809
810	/**
811	* PCI Bus registration structure.
812	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
813	*/
814	typedef struct PDMPCIBUSREGR3
815	{
816	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
817	uint32_t u32Version;
818
819	/**
820	* Registers the device with the default PCI bus.
821	*
822	* @returns VBox status code.
823	* @param pDevIns Device instance of the PCI Bus.
824	* @param pPciDev The PCI device structure.
825	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
826	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
827	* device number (0-31).
828	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
829	* function number (0-7).
830	* @param pszName Device name (static but not unique).
831	*
832	* @remarks Caller enters the PDM critical section.
833	*/
834	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
835	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
836
837	/**
838	* Initialize MSI or MSI-X emulation support in a PCI device.
839	*
840	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
841	* vast majority of device emulation it covers everything necessary. It's
842	* fully automatic, taking care of all BAR and config space requirements,
843	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
844	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
845	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
846	*
847	* A device not using this can still offer MSI/MSI-X. In this case it's
848	* completely up to the device (in the MSI-X case) to create/register the
849	* necessary MMIO BAR, handle all config space/BAR updating and take care
850	* of delivering the interrupts appropriately.
851	*
852	* @returns VBox status code.
853	* @param pDevIns Device instance of the PCI Bus.
854	* @param pPciDev The PCI device structure.
855	* @param pMsiReg MSI emulation registration structure
856	* @remarks Caller enters the PDM critical section.
857	*/
858	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
859
860	/**
861	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
862	*
863	* @returns VBox status code.
864	* @param pDevIns Device instance of the PCI Bus.
865	* @param pPciDev The PCI device structure.
866	* @param iRegion The region number.
867	* @param cbRegion Size of the region.
868	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
869	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
870	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
871	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
872	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
873	* @a fFlags, UINT64_MAX if no handle is passed
874	* (old style).
875	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
876	* is given.
877	* @remarks Caller enters the PDM critical section.
878	*/
879	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
880	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
881	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
882
883	/**
884	* Register PCI configuration space read/write intercept callbacks.
885	*
886	* @param pDevIns Device instance of the PCI Bus.
887	* @param pPciDev The PCI device structure.
888	* @param pfnRead Pointer to the user defined PCI config read function.
889	* @param pfnWrite Pointer to the user defined PCI config write function.
890	* to call default PCI config write function. Can be NULL.
891	* @remarks Caller enters the PDM critical section.
892	* @thread EMT
893	*/
894	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
895	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
896
897	/**
898	* Perform a PCI configuration space write, bypassing interception.
899	*
900	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
901	*
902	* @returns Strict VBox status code (mainly DBGFSTOP).
903	* @param pDevIns Device instance of the PCI Bus.
904	* @param pPciDev The PCI device which config space is being read.
905	* @param uAddress The config space address.
906	* @param cb The size of the read: 1, 2 or 4 bytes.
907	* @param u32Value The value to write.
908	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
909	* that the (root) bus will have done that already.
910	*/
911	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
912	uint32_t uAddress, unsigned cb, uint32_t u32Value));
913
914	/**
915	* Perform a PCI configuration space read, bypassing interception.
916	*
917	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
918	*
919	* @returns Strict VBox status code (mainly DBGFSTOP).
920	* @param pDevIns Device instance of the PCI Bus.
921	* @param pPciDev The PCI device which config space is being read.
922	* @param uAddress The config space address.
923	* @param cb The size of the read: 1, 2 or 4 bytes.
924	* @param pu32Value Where to return the value.
925	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
926	* that the (root) bus will have done that already.
927	*/
928	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
929	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
930
931	/**
932	* Set the IRQ for a PCI device.
933	*
934	* @param pDevIns Device instance of the PCI Bus.
935	* @param pPciDev The PCI device structure.
936	* @param iIrq IRQ number to set.
937	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
938	* @param uTagSrc The IRQ tag and source (for tracing).
939	* @remarks Caller enters the PDM critical section.
940	*/
941	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
942
943	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
944	uint32_t u32EndVersion;
945	} PDMPCIBUSREGR3;
946	/** Pointer to a PCI bus registration structure. */
947	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
948	/** Current PDMPCIBUSREGR3 version number. */
949	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
950
951	/**
952	* PCI Bus registration structure for ring-0.
953	*/
954	typedef struct PDMPCIBUSREGR0
955	{
956	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
957	uint32_t u32Version;
958	/** The PCI bus number (from ring-3 registration). */
959	uint32_t iBus;
960	/**
961	* Set the IRQ for a PCI device.
962	*
963	* @param pDevIns Device instance of the PCI Bus.
964	* @param pPciDev The PCI device structure.
965	* @param iIrq IRQ number to set.
966	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
967	* @param uTagSrc The IRQ tag and source (for tracing).
968	* @remarks Caller enters the PDM critical section.
969	*/
970	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
971	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
972	uint32_t u32EndVersion;
973	} PDMPCIBUSREGR0;
974	/** Pointer to a PCI bus ring-0 registration structure. */
975	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
976	/** Current PDMPCIBUSREGR0 version number. */
977	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
978
979	/**
980	* PCI Bus registration structure for raw-mode.
981	*/
982	typedef struct PDMPCIBUSREGRC
983	{
984	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
985	uint32_t u32Version;
986	/** The PCI bus number (from ring-3 registration). */
987	uint32_t iBus;
988	/**
989	* Set the IRQ for a PCI device.
990	*
991	* @param pDevIns Device instance of the PCI Bus.
992	* @param pPciDev The PCI device structure.
993	* @param iIrq IRQ number to set.
994	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
995	* @param uTagSrc The IRQ tag and source (for tracing).
996	* @remarks Caller enters the PDM critical section.
997	*/
998	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
999	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1000	uint32_t u32EndVersion;
1001	} PDMPCIBUSREGRC;
1002	/** Pointer to a PCI bus raw-mode registration structure. */
1003	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1004	/** Current PDMPCIBUSREGRC version number. */
1005	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1006
1007	/** PCI bus registration structure for the current context. */
1008	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1009	/** Pointer to a PCI bus registration structure for the current context. */
1010	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1011	/** PCI bus registration structure version for the current context. */
1012	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1013
1014
1015	/**
1016	* PCI Bus RC helpers.
1017	*/
1018	typedef struct PDMPCIHLPRC
1019	{
1020	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1021	uint32_t u32Version;
1022
1023	/**
1024	* Set an ISA IRQ.
1025	*
1026	* @param pDevIns PCI device instance.
1027	* @param iIrq IRQ number to set.
1028	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1029	* @param uTagSrc The IRQ tag and source (for tracing).
1030	* @thread EMT only.
1031	*/
1032	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1033
1034	/**
1035	* Set an I/O-APIC IRQ.
1036	*
1037	* @param pDevIns PCI device instance.
1038	* @param uBusDevFn The bus:device:function of the device initiating the
1039	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1040	* interrupt.
1041	* @param iIrq IRQ number to set.
1042	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1043	* @param uTagSrc The IRQ tag and source (for tracing).
1044	* @thread EMT only.
1045	*/
1046	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1047
1048	/**
1049	* Send an MSI.
1050	*
1051	* @param pDevIns PCI device instance.
1052	* @param uBusDevFn The bus:device:function of the device initiating the
1053	* MSI. Cannot be NIL_PCIBDF.
1054	* @param pMsi The MSI to send.
1055	* @param uTagSrc The IRQ tag and source (for tracing).
1056	* @thread EMT only.
1057	*/
1058	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1059
1060
1061	/**
1062	* Acquires the PDM lock.
1063	*
1064	* @returns VINF_SUCCESS on success.
1065	* @returns rc if we failed to acquire the lock.
1066	* @param pDevIns The PCI device instance.
1067	* @param rc What to return if we fail to acquire the lock.
1068	*
1069	* @sa PDMCritSectEnter
1070	*/
1071	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1072
1073	/**
1074	* Releases the PDM lock.
1075	*
1076	* @param pDevIns The PCI device instance.
1077	*/
1078	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1079
1080	/**
1081	* Gets a bus by it's PDM ordinal (typically the parent bus).
1082	*
1083	* @returns Pointer to the device instance of the bus.
1084	* @param pDevIns The PCI bus device instance.
1085	* @param idxPdmBus The PDM ordinal value of the bus to get.
1086	*/
1087	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1088
1089	/** Just a safety precaution. */
1090	uint32_t u32TheEnd;
1091	} PDMPCIHLPRC;
1092	/** Pointer to PCI helpers. */
1093	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1094	/** Pointer to const PCI helpers. */
1095	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1096
1097	/** Current PDMPCIHLPRC version number. */
1098	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1099
1100
1101	/**
1102	* PCI Bus R0 helpers.
1103	*/
1104	typedef struct PDMPCIHLPR0
1105	{
1106	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1107	uint32_t u32Version;
1108
1109	/**
1110	* Set an ISA IRQ.
1111	*
1112	* @param pDevIns PCI device instance.
1113	* @param iIrq IRQ number to set.
1114	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1115	* @param uTagSrc The IRQ tag and source (for tracing).
1116	* @thread EMT only.
1117	*/
1118	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1119
1120	/**
1121	* Set an I/O-APIC IRQ.
1122	*
1123	* @param pDevIns PCI device instance.
1124	* @param uBusDevFn The bus:device:function of the device initiating the
1125	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1126	* interrupt.
1127	* @param iIrq IRQ number to set.
1128	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1129	* @param uTagSrc The IRQ tag and source (for tracing).
1130	* @thread EMT only.
1131	*/
1132	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1133
1134	/**
1135	* Send an MSI.
1136	*
1137	* @param pDevIns PCI device instance.
1138	* @param uBusDevFn The bus:device:function of the device initiating the
1139	* MSI. Cannot be NIL_PCIBDF.
1140	* @param pMsi The MSI to send.
1141	* @param uTagSrc The IRQ tag and source (for tracing).
1142	* @thread EMT only.
1143	*/
1144	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1145
1146	/**
1147	* Acquires the PDM lock.
1148	*
1149	* @returns VINF_SUCCESS on success.
1150	* @returns rc if we failed to acquire the lock.
1151	* @param pDevIns The PCI device instance.
1152	* @param rc What to return if we fail to acquire the lock.
1153	*
1154	* @sa PDMCritSectEnter
1155	*/
1156	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1157
1158	/**
1159	* Releases the PDM lock.
1160	*
1161	* @param pDevIns The PCI device instance.
1162	*/
1163	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1164
1165	/**
1166	* Gets a bus by it's PDM ordinal (typically the parent bus).
1167	*
1168	* @returns Pointer to the device instance of the bus.
1169	* @param pDevIns The PCI bus device instance.
1170	* @param idxPdmBus The PDM ordinal value of the bus to get.
1171	*/
1172	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1173
1174	/** Just a safety precaution. */
1175	uint32_t u32TheEnd;
1176	} PDMPCIHLPR0;
1177	/** Pointer to PCI helpers. */
1178	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1179	/** Pointer to const PCI helpers. */
1180	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1181
1182	/** Current PDMPCIHLPR0 version number. */
1183	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1184
1185	/**
1186	* PCI device helpers.
1187	*/
1188	typedef struct PDMPCIHLPR3
1189	{
1190	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1191	uint32_t u32Version;
1192
1193	/**
1194	* Set an ISA IRQ.
1195	*
1196	* @param pDevIns The PCI device instance.
1197	* @param iIrq IRQ number to set.
1198	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1199	* @param uTagSrc The IRQ tag and source (for tracing).
1200	*/
1201	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1202
1203	/**
1204	* Set an I/O-APIC IRQ.
1205	*
1206	* @param pDevIns The PCI device instance.
1207	* @param uBusDevFn The bus:device:function of the device initiating the
1208	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1209	* interrupt.
1210	* @param iIrq IRQ number to set.
1211	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1212	* @param uTagSrc The IRQ tag and source (for tracing).
1213	*/
1214	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1215
1216	/**
1217	* Send an MSI.
1218	*
1219	* @param pDevIns PCI device instance.
1220	* @param uBusDevFn The bus:device:function of the device initiating the
1221	* MSI. Cannot be NIL_PCIBDF.
1222	* @param pMsi The MSI to send.
1223	* @param uTagSrc The IRQ tag and source (for tracing).
1224	*/
1225	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1226
1227	/**
1228	* Acquires the PDM lock.
1229	*
1230	* @returns VINF_SUCCESS on success.
1231	* @returns Fatal error on failure.
1232	* @param pDevIns The PCI device instance.
1233	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1234	*
1235	* @sa PDMCritSectEnter
1236	*/
1237	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1238
1239	/**
1240	* Releases the PDM lock.
1241	*
1242	* @param pDevIns The PCI device instance.
1243	*/
1244	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1245
1246	/**
1247	* Gets a bus by it's PDM ordinal (typically the parent bus).
1248	*
1249	* @returns Pointer to the device instance of the bus.
1250	* @param pDevIns The PCI bus device instance.
1251	* @param idxPdmBus The PDM ordinal value of the bus to get.
1252	*/
1253	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1254
1255	/** Just a safety precaution. */
1256	uint32_t u32TheEnd;
1257	} PDMPCIHLPR3;
1258	/** Pointer to PCI helpers. */
1259	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1260	/** Pointer to const PCI helpers. */
1261	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1262
1263	/** Current PDMPCIHLPR3 version number. */
1264	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1265
1266
1267	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1268	* These flags are used for memory access transactions via the IOMMU interface.
1269	* @{ */
1270	/** Memory read. */
1271	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1272	/** Memory write. */
1273	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1274	/** Valid flag mask. */
1275	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1276	/** @} */
1277
1278	/**
1279	* IOMMU registration structure for ring-0.
1280	*/
1281	typedef struct PDMIOMMUREGR0
1282	{
1283	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1284	* version. */
1285	uint32_t u32Version;
1286	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1287	uint32_t idxIommu;
1288
1289	/**
1290	* Translates the physical address for a memory transaction through the IOMMU.
1291	*
1292	* @returns VBox status code.
1293	* @param pDevIns The IOMMU device instance.
1294	* @param idDevice The device identifier (bus, device, function).
1295	* @param uIova The I/O virtual address being accessed.
1296	* @param cbIova The size of the access.
1297	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1298	* @param pGCPhysSpa Where to store the translated system physical address.
1299	* @param pcbContiguous Where to store the number of contiguous bytes translated
1300	* and permission-checked.
1301	*
1302	* @thread Any.
1303	*/
1304	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1305	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1306
1307	/**
1308	* Translates in bulk physical page addresses for memory transactions through the
1309	* IOMMU.
1310	*
1311	* @returns VBox status code.
1312	* @param pDevIns The IOMMU device instance.
1313	* @param idDevice The device identifier (bus, device, function).
1314	* @param cIovas The number of I/O virtual addresses being accessed.
1315	* @param pauIovas The I/O virtual addresses being accessed.
1316	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1317	* @param paGCPhysSpa Where to store the translated system physical page
1318	* addresses.
1319	*
1320	* @thread Any.
1321	*/
1322	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1323	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1324
1325	/**
1326	* Performs an interrupt remap request through the IOMMU.
1327	*
1328	* @returns VBox status code.
1329	* @param pDevIns The IOMMU device instance.
1330	* @param idDevice The device identifier (bus, device, function).
1331	* @param pMsiIn The source MSI.
1332	* @param pMsiOut Where to store the remapped MSI.
1333	*
1334	* @thread Any.
1335	*/
1336	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1337
1338	/** Just a safety precaution. */
1339	uint32_t u32TheEnd;
1340	} PDMIOMMUREGR0;
1341	/** Pointer to a IOMMU registration structure. */
1342	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1343
1344	/** Current PDMIOMMUREG version number. */
1345	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1346
1347
1348	/**
1349	* IOMMU registration structure for raw-mode.
1350	*/
1351	typedef struct PDMIOMMUREGRC
1352	{
1353	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1354	* version. */
1355	uint32_t u32Version;
1356	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1357	uint32_t idxIommu;
1358
1359	/**
1360	* Translates the physical address for a memory transaction through the IOMMU.
1361	*
1362	* @returns VBox status code.
1363	* @param pDevIns The IOMMU device instance.
1364	* @param idDevice The device identifier (bus, device, function).
1365	* @param uIova The I/O virtual address being accessed.
1366	* @param cbIova The size of the access.
1367	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1368	* @param pGCPhysSpa Where to store the translated system physical address.
1369	* @param pcbContiguous Where to store the number of contiguous bytes translated
1370	* and permission-checked.
1371	*
1372	* @thread Any.
1373	*/
1374	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1375	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1376
1377	/**
1378	* Translates in bulk physical page addresses for memory transactions through the
1379	* IOMMU.
1380	*
1381	* @returns VBox status code.
1382	* @param pDevIns The IOMMU device instance.
1383	* @param idDevice The device identifier (bus, device, function).
1384	* @param cIovas The number of I/O virtual addresses being accessed.
1385	* @param pauIovas The I/O virtual addresses being accessed.
1386	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1387	* @param paGCPhysSpa Where to store the translated system physical page
1388	* addresses.
1389	*
1390	* @thread Any.
1391	*/
1392	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1393	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1394
1395	/**
1396	* Performs an interrupt remap request through the IOMMU.
1397	*
1398	* @returns VBox status code.
1399	* @param pDevIns The IOMMU device instance.
1400	* @param idDevice The device identifier (bus, device, function).
1401	* @param pMsiIn The source MSI.
1402	* @param pMsiOut Where to store the remapped MSI.
1403	*
1404	* @thread Any.
1405	*/
1406	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1407
1408	/** Just a safety precaution. */
1409	uint32_t u32TheEnd;
1410	} PDMIOMMUREGRC;
1411	/** Pointer to a IOMMU registration structure. */
1412	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1413
1414	/** Current PDMIOMMUREG version number. */
1415	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1416
1417
1418	/**
1419	* IOMMU registration structure for ring-3.
1420	*/
1421	typedef struct PDMIOMMUREGR3
1422	{
1423	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1424	* version. */
1425	uint32_t u32Version;
1426	/** Padding. */
1427	uint32_t uPadding0;
1428
1429	/**
1430	* Translates the physical address for a memory transaction through the IOMMU.
1431	*
1432	* @returns VBox status code.
1433	* @param pDevIns The IOMMU device instance.
1434	* @param idDevice The device identifier (bus, device, function).
1435	* @param uIova The I/O virtual address being accessed.
1436	* @param cbIova The size of the access.
1437	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1438	* @param pGCPhysSpa Where to store the translated system physical address.
1439	* @param pcbContiguous Where to store the number of contiguous bytes translated
1440	* and permission-checked.
1441	*
1442	* @thread Any.
1443	*/
1444	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1445	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1446
1447	/**
1448	* Translates in bulk physical page addresses for memory transactions through the
1449	* IOMMU.
1450	*
1451	* @returns VBox status code.
1452	* @param pDevIns The IOMMU device instance.
1453	* @param idDevice The device identifier (bus, device, function).
1454	* @param cIovas The number of I/O virtual addresses being accessed.
1455	* @param pauIovas The I/O virtual addresses being accessed.
1456	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1457	* @param paGCPhysSpa Where to store the translated system physical page
1458	* addresses.
1459	*
1460	* @thread Any.
1461	*/
1462	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1463	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1464
1465	/**
1466	* Performs an interrupt remap request through the IOMMU.
1467	*
1468	* @returns VBox status code.
1469	* @param pDevIns The IOMMU device instance.
1470	* @param idDevice The device identifier (bus, device, function).
1471	* @param pMsiIn The source MSI.
1472	* @param pMsiOut Where to store the remapped MSI.
1473	*
1474	* @thread Any.
1475	*/
1476	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1477
1478	/** Just a safety precaution. */
1479	uint32_t u32TheEnd;
1480	} PDMIOMMUREGR3;
1481	/** Pointer to a IOMMU registration structure. */
1482	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1483
1484	/** Current PDMIOMMUREG version number. */
1485	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1486
1487	/** IOMMU registration structure for the current context. */
1488	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1489	/** Pointer to an IOMMU registration structure for the current context. */
1490	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1491	/** IOMMU registration structure version for the current context. */
1492	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1493
1494
1495	/**
1496	* IOMMU helpers for ring-0.
1497	*/
1498	typedef struct PDMIOMMUHLPR0
1499	{
1500	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1501	uint32_t u32Version;
1502
1503	/**
1504	* Acquires the PDM lock.
1505	*
1506	* @returns VINF_SUCCESS on success.
1507	* @returns rc if we failed to acquire the lock.
1508	* @param pDevIns The PCI device instance.
1509	* @param rc What to return if we fail to acquire the lock.
1510	*
1511	* @sa PDMCritSectEnter
1512	*/
1513	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1514
1515	/**
1516	* Releases the PDM lock.
1517	*
1518	* @param pDevIns The PCI device instance.
1519	*/
1520	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1521
1522	/**
1523	* Check whether the calling thread owns the PDM lock.
1524	*
1525	* @returns @c true if the PDM lock is owned, @c false otherwise.
1526	* @param pDevIns The PCI device instance.
1527	*/
1528	DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1529
1530	/**
1531	* Send an MSI (when generated by the IOMMU device itself).
1532	*
1533	* @param pDevIns PCI device instance.
1534	* @param pMsi The MSI to send.
1535	* @param uTagSrc The IRQ tag and source (for tracing).
1536	*/
1537	DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1538
1539	/** Just a safety precaution. */
1540	uint32_t u32TheEnd;
1541	} PDMIOMMUHLPR0;
1542	/** Pointer to IOMMU helpers for ring-0. */
1543	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1544	/** Pointer to const IOMMU helpers for ring-0. */
1545	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1546
1547	/** Current PDMIOMMUHLPR0 version number. */
1548	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1549
1550
1551	/**
1552	* IOMMU helpers for raw-mode.
1553	*/
1554	typedef struct PDMIOMMUHLPRC
1555	{
1556	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1557	uint32_t u32Version;
1558
1559	/**
1560	* Acquires the PDM lock.
1561	*
1562	* @returns VINF_SUCCESS on success.
1563	* @returns rc if we failed to acquire the lock.
1564	* @param pDevIns The PCI device instance.
1565	* @param rc What to return if we fail to acquire the lock.
1566	*
1567	* @sa PDMCritSectEnter
1568	*/
1569	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1570
1571	/**
1572	* Releases the PDM lock.
1573	*
1574	* @param pDevIns The PCI device instance.
1575	*/
1576	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1577
1578	/**
1579	* Check whether the threads owns the PDM lock.
1580	*
1581	* @returns @c true if the PDM lock is owned, @c false otherwise.
1582	* @param pDevIns The PCI device instance.
1583	*/
1584	DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1585
1586	/**
1587	* Send an MSI (when generated by the IOMMU device itself).
1588	*
1589	* @param pDevIns PCI device instance.
1590	* @param pMsi The MSI to send.
1591	* @param uTagSrc The IRQ tag and source (for tracing).
1592	*/
1593	DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1594
1595	/** Just a safety precaution. */
1596	uint32_t u32TheEnd;
1597	} PDMIOMMUHLPRC;
1598	/** Pointer to IOMMU helpers for raw-mode. */
1599	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1600	/** Pointer to const IOMMU helpers for raw-mode. */
1601	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1602
1603	/** Current PDMIOMMUHLPRC version number. */
1604	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1605
1606
1607	/**
1608	* IOMMU helpers for ring-3.
1609	*/
1610	typedef struct PDMIOMMUHLPR3
1611	{
1612	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1613	uint32_t u32Version;
1614
1615	/**
1616	* Acquires the PDM lock.
1617	*
1618	* @returns VINF_SUCCESS on success.
1619	* @returns rc if we failed to acquire the lock.
1620	* @param pDevIns The PCI device instance.
1621	* @param rc What to return if we fail to acquire the lock.
1622	*
1623	* @sa PDMCritSectEnter
1624	*/
1625	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1626
1627	/**
1628	* Releases the PDM lock.
1629	*
1630	* @param pDevIns The PCI device instance.
1631	*/
1632	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1633
1634	/**
1635	* Check whether the threads owns the PDM lock.
1636	*
1637	* @returns @c true if the PDM lock is owned, @c false otherwise.
1638	* @param pDevIns The PCI device instance.
1639	*/
1640	DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1641
1642	/**
1643	* Send an MSI (when generated by the IOMMU device itself).
1644	*
1645	* @param pDevIns PCI device instance.
1646	* @param pMsi The MSI to send.
1647	* @param uTagSrc The IRQ tag and source (for tracing).
1648	*/
1649	DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1650
1651	/** Just a safety precaution. */
1652	uint32_t u32TheEnd;
1653	} PDMIOMMUHLPR3;
1654	/** Pointer to IOMMU helpers for raw-mode. */
1655	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1656	/** Pointer to const IOMMU helpers for raw-mode. */
1657	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1658
1659	/** Current PDMIOMMUHLPR3 version number. */
1660	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1661
1662
1663	/**
1664	* Programmable Interrupt Controller registration structure (all contexts).
1665	*/
1666	typedef struct PDMPICREG
1667	{
1668	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1669	uint32_t u32Version;
1670
1671	/**
1672	* Set the an IRQ.
1673	*
1674	* @param pDevIns Device instance of the PIC.
1675	* @param iIrq IRQ number to set.
1676	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1677	* @param uTagSrc The IRQ tag and source (for tracing).
1678	* @remarks Caller enters the PDM critical section.
1679	*/
1680	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1681
1682	/**
1683	* Get a pending interrupt.
1684	*
1685	* @returns Pending interrupt number.
1686	* @param pDevIns Device instance of the PIC.
1687	* @param puTagSrc Where to return the IRQ tag and source.
1688	* @remarks Caller enters the PDM critical section.
1689	*/
1690	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1691
1692	/** Just a safety precaution. */
1693	uint32_t u32TheEnd;
1694	} PDMPICREG;
1695	/** Pointer to a PIC registration structure. */
1696	typedef PDMPICREG *PPDMPICREG;
1697
1698	/** Current PDMPICREG version number. */
1699	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1700
1701	/**
1702	* PIC helpers, same in all contexts.
1703	*/
1704	typedef struct PDMPICHLP
1705	{
1706	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1707	uint32_t u32Version;
1708
1709	/**
1710	* Set the interrupt force action flag.
1711	*
1712	* @param pDevIns Device instance of the PIC.
1713	*/
1714	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1715
1716	/**
1717	* Clear the interrupt force action flag.
1718	*
1719	* @param pDevIns Device instance of the PIC.
1720	*/
1721	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1722
1723	/**
1724	* Acquires the PDM lock.
1725	*
1726	* @returns VINF_SUCCESS on success.
1727	* @returns rc if we failed to acquire the lock.
1728	* @param pDevIns The PIC device instance.
1729	* @param rc What to return if we fail to acquire the lock.
1730	*
1731	* @sa PDMCritSectEnter
1732	*/
1733	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1734
1735	/**
1736	* Releases the PDM lock.
1737	*
1738	* @param pDevIns The PIC device instance.
1739	*/
1740	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1741
1742	/** Just a safety precaution. */
1743	uint32_t u32TheEnd;
1744	} PDMPICHLP;
1745	/** Pointer to PIC helpers. */
1746	typedef PDMPICHLP *PPDMPICHLP;
1747	/** Pointer to const PIC helpers. */
1748	typedef const PDMPICHLP *PCPDMPICHLP;
1749
1750	/** Current PDMPICHLP version number. */
1751	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1752
1753
1754	/**
1755	* Firmware registration structure.
1756	*/
1757	typedef struct PDMFWREG
1758	{
1759	/** Struct version+magic number (PDM_FWREG_VERSION). */
1760	uint32_t u32Version;
1761
1762	/**
1763	* Checks whether this is a hard or soft reset.
1764	*
1765	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1766	* is 5, 9 or 0xA.
1767	*
1768	* @returns true if hard reset, false if soft.
1769	* @param pDevIns Device instance of the firmware.
1770	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1771	*/
1772	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1773
1774	/** Just a safety precaution. */
1775	uint32_t u32TheEnd;
1776	} PDMFWREG;
1777	/** Pointer to a FW registration structure. */
1778	typedef PDMFWREG *PPDMFWREG;
1779	/** Pointer to a const FW registration structure. */
1780	typedef PDMFWREG const *PCPDMFWREG;
1781
1782	/** Current PDMFWREG version number. */
1783	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1784
1785	/**
1786	* Firmware R3 helpers.
1787	*/
1788	typedef struct PDMFWHLPR3
1789	{
1790	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1791	uint32_t u32Version;
1792
1793	/** Just a safety precaution. */
1794	uint32_t u32TheEnd;
1795	} PDMFWHLPR3;
1796
1797	/** Pointer to FW R3 helpers. */
1798	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1799	/** Pointer to const FW R3 helpers. */
1800	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1801
1802	/** Current PDMFWHLPR3 version number. */
1803	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1804
1805
1806	/**
1807	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1808	*
1809	* Also used in saved-states, CFGM don't change existing values.
1810	*/
1811	typedef enum PDMAPICMODE
1812	{
1813	/** Invalid 0 entry. */
1814	PDMAPICMODE_INVALID = 0,
1815	/** No APIC. */
1816	PDMAPICMODE_NONE,
1817	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1818	PDMAPICMODE_APIC,
1819	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1820	PDMAPICMODE_X2APIC,
1821	/** The usual 32-bit paranoia. */
1822	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1823	} PDMAPICMODE;
1824
1825	/**
1826	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1827	*/
1828	typedef enum PDMAPICIRQ
1829	{
1830	/** Invalid 0 entry. */
1831	PDMAPICIRQ_INVALID = 0,
1832	/** Normal hardware interrupt. */
1833	PDMAPICIRQ_HARDWARE,
1834	/** NMI. */
1835	PDMAPICIRQ_NMI,
1836	/** SMI. */
1837	PDMAPICIRQ_SMI,
1838	/** ExtINT (HW interrupt via PIC). */
1839	PDMAPICIRQ_EXTINT,
1840	/** Interrupt arrived, needs to be updated to the IRR. */
1841	PDMAPICIRQ_UPDATE_PENDING,
1842	/** The usual 32-bit paranoia. */
1843	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1844	} PDMAPICIRQ;
1845
1846
1847	/**
1848	* I/O APIC registration structure (all contexts).
1849	*/
1850	typedef struct PDMIOAPICREG
1851	{
1852	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1853	uint32_t u32Version;
1854
1855	/**
1856	* Set an IRQ.
1857	*
1858	* @param pDevIns Device instance of the I/O APIC.
1859	* @param uBusDevFn The bus:device:function of the device initiating the
1860	* IRQ. Can be NIL_PCIBDF.
1861	* @param iIrq IRQ number to set.
1862	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1863	* @param uTagSrc The IRQ tag and source (for tracing).
1864	*
1865	* @remarks Caller enters the PDM critical section
1866	* Actually, as per 2018-07-21 this isn't true (bird).
1867	*/
1868	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1869
1870	/**
1871	* Send a MSI.
1872	*
1873	* @param pDevIns Device instance of the I/O APIC.
1874	* @param uBusDevFn The bus:device:function of the device initiating the
1875	* MSI. Cannot be NIL_PCIBDF.
1876	* @param pMsi The MSI to send.
1877	* @param uTagSrc The IRQ tag and source (for tracing).
1878	*
1879	* @remarks Caller enters the PDM critical section
1880	* Actually, as per 2018-07-21 this isn't true (bird).
1881	*/
1882	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1883
1884	/**
1885	* Set the EOI for an interrupt vector.
1886	*
1887	* @param pDevIns Device instance of the I/O APIC.
1888	* @param u8Vector The vector.
1889	*
1890	* @remarks Caller enters the PDM critical section
1891	* Actually, as per 2018-07-21 this isn't true (bird).
1892	*/
1893	DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1894
1895	/** Just a safety precaution. */
1896	uint32_t u32TheEnd;
1897	} PDMIOAPICREG;
1898	/** Pointer to an APIC registration structure. */
1899	typedef PDMIOAPICREG *PPDMIOAPICREG;
1900
1901	/** Current PDMAPICREG version number. */
1902	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1903
1904
1905	/**
1906	* IOAPIC helpers, same in all contexts.
1907	*/
1908	typedef struct PDMIOAPICHLP
1909	{
1910	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1911	uint32_t u32Version;
1912
1913	/**
1914	* Private interface between the IOAPIC and APIC.
1915	*
1916	* @returns status code.
1917	* @param pDevIns Device instance of the IOAPIC.
1918	* @param u8Dest See APIC implementation.
1919	* @param u8DestMode See APIC implementation.
1920	* @param u8DeliveryMode See APIC implementation.
1921	* @param uVector See APIC implementation.
1922	* @param u8Polarity See APIC implementation.
1923	* @param u8TriggerMode See APIC implementation.
1924	* @param uTagSrc The IRQ tag and source (for tracing).
1925	*
1926	* @sa APICBusDeliver()
1927	*/
1928	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1929	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1930
1931	/**
1932	* Acquires the PDM lock.
1933	*
1934	* @returns VINF_SUCCESS on success.
1935	* @returns rc if we failed to acquire the lock.
1936	* @param pDevIns The IOAPIC device instance.
1937	* @param rc What to return if we fail to acquire the lock.
1938	*
1939	* @sa PDMCritSectEnter
1940	*/
1941	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1942
1943	/**
1944	* Releases the PDM lock.
1945	*
1946	* @param pDevIns The IOAPIC device instance.
1947	*/
1948	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1949
1950	/**
1951	* Checks if the calling thread owns the PDM lock.
1952	*
1953	* @param pDevIns The IOAPIC device instance.
1954	*/
1955	DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1956
1957	/**
1958	* Private interface between the IOAPIC and IOMMU.
1959	*
1960	* @returns status code.
1961	* @param pDevIns Device instance of the IOAPIC.
1962	* @param idDevice The device identifier (bus, device, function).
1963	* @param pMsiIn The source MSI.
1964	* @param pMsiOut Where to store the remapped MSI (only updated when
1965	* VINF_SUCCESS is returned).
1966	*/
1967	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1968
1969	/** Just a safety precaution. */
1970	uint32_t u32TheEnd;
1971	} PDMIOAPICHLP;
1972	/** Pointer to IOAPIC helpers. */
1973	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1974	/** Pointer to const IOAPIC helpers. */
1975	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1976
1977	/** Current PDMIOAPICHLP version number. */
1978	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1979
1980
1981	/**
1982	* HPET registration structure.
1983	*/
1984	typedef struct PDMHPETREG
1985	{
1986	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1987	uint32_t u32Version;
1988	} PDMHPETREG;
1989	/** Pointer to an HPET registration structure. */
1990	typedef PDMHPETREG *PPDMHPETREG;
1991
1992	/** Current PDMHPETREG version number. */
1993	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1994
1995	/**
1996	* HPET RC helpers.
1997	*
1998	* @remarks Keep this around in case HPET will need PDM interaction in again RC
1999	* at some later point.
2000	*/
2001	typedef struct PDMHPETHLPRC
2002	{
2003	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
2004	uint32_t u32Version;
2005
2006	/** Just a safety precaution. */
2007	uint32_t u32TheEnd;
2008	} PDMHPETHLPRC;
2009
2010	/** Pointer to HPET RC helpers. */
2011	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
2012	/** Pointer to const HPET RC helpers. */
2013	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
2014
2015	/** Current PDMHPETHLPRC version number. */
2016	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
2017
2018
2019	/**
2020	* HPET R0 helpers.
2021	*
2022	* @remarks Keep this around in case HPET will need PDM interaction in again R0
2023	* at some later point.
2024	*/
2025	typedef struct PDMHPETHLPR0
2026	{
2027	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2028	uint32_t u32Version;
2029
2030	/** Just a safety precaution. */
2031	uint32_t u32TheEnd;
2032	} PDMHPETHLPR0;
2033
2034	/** Pointer to HPET R0 helpers. */
2035	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2036	/** Pointer to const HPET R0 helpers. */
2037	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2038
2039	/** Current PDMHPETHLPR0 version number. */
2040	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2041
2042	/**
2043	* HPET R3 helpers.
2044	*/
2045	typedef struct PDMHPETHLPR3
2046	{
2047	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2048	uint32_t u32Version;
2049
2050	/**
2051	* Set legacy mode on PIT and RTC.
2052	*
2053	* @returns VINF_SUCCESS on success.
2054	* @returns rc if we failed to set legacy mode.
2055	* @param pDevIns Device instance of the HPET.
2056	* @param fActivated Whether legacy mode is activated or deactivated.
2057	*/
2058	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2059
2060
2061	/**
2062	* Set IRQ, bypassing ISA bus override rules.
2063	*
2064	* @returns VINF_SUCCESS on success.
2065	* @returns rc if we failed to set legacy mode.
2066	* @param pDevIns Device instance of the HPET.
2067	* @param iIrq IRQ number to set.
2068	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2069	*/
2070	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2071
2072	/** Just a safety precaution. */
2073	uint32_t u32TheEnd;
2074	} PDMHPETHLPR3;
2075
2076	/** Pointer to HPET R3 helpers. */
2077	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2078	/** Pointer to const HPET R3 helpers. */
2079	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2080
2081	/** Current PDMHPETHLPR3 version number. */
2082	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2083
2084
2085	/**
2086	* Raw PCI device registration structure.
2087	*/
2088	typedef struct PDMPCIRAWREG
2089	{
2090	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2091	uint32_t u32Version;
2092	/** Just a safety precaution. */
2093	uint32_t u32TheEnd;
2094	} PDMPCIRAWREG;
2095	/** Pointer to a raw PCI registration structure. */
2096	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2097
2098	/** Current PDMPCIRAWREG version number. */
2099	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2100
2101	/**
2102	* Raw PCI device raw-mode context helpers.
2103	*/
2104	typedef struct PDMPCIRAWHLPRC
2105	{
2106	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2107	uint32_t u32Version;
2108	/** Just a safety precaution. */
2109	uint32_t u32TheEnd;
2110	} PDMPCIRAWHLPRC;
2111	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2112	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2113	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2114	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2115
2116	/** Current PDMPCIRAWHLPRC version number. */
2117	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2118
2119	/**
2120	* Raw PCI device ring-0 context helpers.
2121	*/
2122	typedef struct PDMPCIRAWHLPR0
2123	{
2124	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2125	uint32_t u32Version;
2126	/** Just a safety precaution. */
2127	uint32_t u32TheEnd;
2128	} PDMPCIRAWHLPR0;
2129	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2130	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2131	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2132	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2133
2134	/** Current PDMPCIRAWHLPR0 version number. */
2135	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2136
2137
2138	/**
2139	* Raw PCI device ring-3 context helpers.
2140	*/
2141	typedef struct PDMPCIRAWHLPR3
2142	{
2143	/** Undefined structure version and magic number. */
2144	uint32_t u32Version;
2145
2146	/**
2147	* Gets the address of the RC raw PCI device helpers.
2148	*
2149	* This should be called at both construction and relocation time to obtain
2150	* the correct address of the RC helpers.
2151	*
2152	* @returns RC pointer to the raw PCI device helpers.
2153	* @param pDevIns Device instance of the raw PCI device.
2154	*/
2155	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2156
2157	/**
2158	* Gets the address of the R0 raw PCI device helpers.
2159	*
2160	* This should be called at both construction and relocation time to obtain
2161	* the correct address of the R0 helpers.
2162	*
2163	* @returns R0 pointer to the raw PCI device helpers.
2164	* @param pDevIns Device instance of the raw PCI device.
2165	*/
2166	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2167
2168	/** Just a safety precaution. */
2169	uint32_t u32TheEnd;
2170	} PDMPCIRAWHLPR3;
2171	/** Pointer to raw PCI R3 helpers. */
2172	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2173	/** Pointer to const raw PCI R3 helpers. */
2174	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2175
2176	/** Current PDMPCIRAWHLPR3 version number. */
2177	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2178
2179
2180	#ifdef IN_RING3
2181
2182	/**
2183	* DMA Transfer Handler.
2184	*
2185	* @returns Number of bytes transferred.
2186	* @param pDevIns The device instance that registered the handler.
2187	* @param pvUser User pointer.
2188	* @param uChannel Channel number.
2189	* @param off DMA position.
2190	* @param cb Block size.
2191	* @remarks The device lock is take before the callback (in fact, the locks of
2192	* DMA devices and the DMA controller itself are taken).
2193	*/
2194	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2195	uint32_t off, uint32_t cb));
2196	/** Pointer to a FNDMATRANSFERHANDLER(). */
2197	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2198
2199	/**
2200	* DMA Controller registration structure.
2201	*/
2202	typedef struct PDMDMAREG
2203	{
2204	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2205	uint32_t u32Version;
2206
2207	/**
2208	* Execute pending transfers.
2209	*
2210	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2211	* @param pDevIns Device instance of the DMAC.
2212	* @remarks No locks held, called on EMT(0) as a form of serialization.
2213	*/
2214	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2215
2216	/**
2217	* Register transfer function for DMA channel.
2218	*
2219	* @param pDevIns Device instance of the DMAC.
2220	* @param uChannel Channel number.
2221	* @param pDevInsHandler The device instance of the device making the
2222	* regstration (will be passed to the callback).
2223	* @param pfnTransferHandler Device specific transfer function.
2224	* @param pvUser User pointer to be passed to the callback.
2225	* @remarks No locks held, called on an EMT.
2226	*/
2227	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2228	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2229
2230	/**
2231	* Read memory
2232	*
2233	* @returns Number of bytes read.
2234	* @param pDevIns Device instance of the DMAC.
2235	* @param uChannel Channel number.
2236	* @param pvBuffer Pointer to target buffer.
2237	* @param off DMA position.
2238	* @param cbBlock Block size.
2239	* @remarks No locks held, called on an EMT.
2240	*/
2241	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2242
2243	/**
2244	* Write memory
2245	*
2246	* @returns Number of bytes written.
2247	* @param pDevIns Device instance of the DMAC.
2248	* @param uChannel Channel number.
2249	* @param pvBuffer Memory to write.
2250	* @param off DMA position.
2251	* @param cbBlock Block size.
2252	* @remarks No locks held, called on an EMT.
2253	*/
2254	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2255
2256	/**
2257	* Set the DREQ line.
2258	*
2259	* @param pDevIns Device instance of the DMAC.
2260	* @param uChannel Channel number.
2261	* @param uLevel Level of the line.
2262	* @remarks No locks held, called on an EMT.
2263	*/
2264	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2265
2266	/**
2267	* Get channel mode
2268	*
2269	* @returns Channel mode.
2270	* @param pDevIns Device instance of the DMAC.
2271	* @param uChannel Channel number.
2272	* @remarks No locks held, called on an EMT.
2273	*/
2274	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2275
2276	} PDMDMACREG;
2277	/** Pointer to a DMAC registration structure. */
2278	typedef PDMDMACREG *PPDMDMACREG;
2279
2280	/** Current PDMDMACREG version number. */
2281	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2282
2283
2284	/**
2285	* DMA Controller device helpers.
2286	*/
2287	typedef struct PDMDMACHLP
2288	{
2289	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2290	uint32_t u32Version;
2291
2292	/* to-be-defined */
2293
2294	} PDMDMACHLP;
2295	/** Pointer to DMAC helpers. */
2296	typedef PDMDMACHLP *PPDMDMACHLP;
2297	/** Pointer to const DMAC helpers. */
2298	typedef const PDMDMACHLP *PCPDMDMACHLP;
2299
2300	/** Current PDMDMACHLP version number. */
2301	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2302
2303	#endif /* IN_RING3 */
2304
2305
2306
2307	/**
2308	* RTC registration structure.
2309	*/
2310	typedef struct PDMRTCREG
2311	{
2312	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2313	uint32_t u32Version;
2314	uint32_t u32Alignment; /*< structure size alignment. /
2315
2316	/**
2317	* Write to a CMOS register and update the checksum if necessary.
2318	*
2319	* @returns VBox status code.
2320	* @param pDevIns Device instance of the RTC.
2321	* @param iReg The CMOS register index.
2322	* @param u8Value The CMOS register value.
2323	* @remarks Caller enters the device critical section.
2324	*/
2325	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2326
2327	/**
2328	* Read a CMOS register.
2329	*
2330	* @returns VBox status code.
2331	* @param pDevIns Device instance of the RTC.
2332	* @param iReg The CMOS register index.
2333	* @param pu8Value Where to store the CMOS register value.
2334	* @remarks Caller enters the device critical section.
2335	*/
2336	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2337
2338	} PDMRTCREG;
2339	/** Pointer to a RTC registration structure. */
2340	typedef PDMRTCREG *PPDMRTCREG;
2341	/** Pointer to a const RTC registration structure. */
2342	typedef const PDMRTCREG *PCPDMRTCREG;
2343
2344	/** Current PDMRTCREG version number. */
2345	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2346
2347
2348	/**
2349	* RTC device helpers.
2350	*/
2351	typedef struct PDMRTCHLP
2352	{
2353	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2354	uint32_t u32Version;
2355
2356	/* to-be-defined */
2357
2358	} PDMRTCHLP;
2359	/** Pointer to RTC helpers. */
2360	typedef PDMRTCHLP *PPDMRTCHLP;
2361	/** Pointer to const RTC helpers. */
2362	typedef const PDMRTCHLP *PCPDMRTCHLP;
2363
2364	/** Current PDMRTCHLP version number. */
2365	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2366
2367
2368
2369	/** @name Flags for PCI I/O region registration
2370	* @{ */
2371	/** No handle is passed. */
2372	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2373	/** An I/O port handle is passed. */
2374	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2375	/** An MMIO range handle is passed. */
2376	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2377	/** An MMIO2 handle is passed. */
2378	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2379	/** Handle type mask. */
2380	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2381	/** New-style (mostly wrt callbacks). */
2382	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2383	/** Mask of valid flags. */
2384	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2385	/** @} */
2386
2387
2388	/** @name Flags for the guest physical read/write helpers
2389	* @{ */
2390	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2391	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2392	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2393	* by the device in any way. */
2394	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2395	/** The data is metadata and being processed by the device in some way. */
2396	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2397	/** @} */
2398
2399
2400	#ifdef IN_RING3
2401
2402	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2403	* @{ */
2404	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2405	* This is handy when registering multiple PCI device functions and the device
2406	* number is left up to the PCI bus. In order to facilitate one PDM device
2407	* instance for each PCI function, this searches earlier PDM device
2408	* instances as well. */
2409	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2410	/** Use the first unused device number (all functions must be unused). */
2411	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2412	/** Use the first unused device function. */
2413	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2414
2415	/** The device and function numbers are not mandatory, just suggestions. */
2416	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2417	/** Registering a PCI bridge device. */
2418	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2419	/** Valid flag mask. */
2420	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2421	/** @} */
2422
2423	/** Current PDMDEVHLPR3 version number. */
2424	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 47, 1)
2425
2426	/**
2427	* PDM Device API.
2428	*/
2429	typedef struct PDMDEVHLPR3
2430	{
2431	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2432	uint32_t u32Version;
2433
2434	/** @name I/O ports
2435	* @{ */
2436	/**
2437	* Creates a range of I/O ports for a device.
2438	*
2439	* The I/O port range must be mapped in a separately call. Any ring-0 and
2440	* raw-mode context callback handlers needs to be set up in the respective
2441	* contexts.
2442	*
2443	* @returns VBox status.
2444	* @param pDevIns The device instance to register the ports with.
2445	* @param cPorts Number of ports to register.
2446	* @param fFlags IOM_IOPORT_F_XXX.
2447	* @param pPciDev The PCI device the range is associated with, if
2448	* applicable.
2449	* @param iPciRegion The PCI device region in the high 16-bit word and
2450	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2451	* @param pfnOut Pointer to function which is gonna handle OUT
2452	* operations. Optional.
2453	* @param pfnIn Pointer to function which is gonna handle IN operations.
2454	* Optional.
2455	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2456	* operations. Optional.
2457	* @param pfnInStr Pointer to function which is gonna handle string IN
2458	* operations. Optional.
2459	* @param pvUser User argument to pass to the callbacks.
2460	* @param pszDesc Pointer to description string. This must not be freed.
2461	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2462	* coverage is allowed. This must not be freed.
2463	* @param phIoPorts Where to return the I/O port range handle.
2464	*
2465	* @remarks Caller enters the device critical section prior to invoking the
2466	* registered callback methods.
2467	*
2468	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2469	* PDMDevHlpIoPortUnmap.
2470	*/
2471	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2472	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2473	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2474	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2475
2476	/**
2477	* Maps an I/O port range.
2478	*
2479	* @returns VBox status.
2480	* @param pDevIns The device instance to register the ports with.
2481	* @param hIoPorts The I/O port range handle.
2482	* @param Port Where to map the range.
2483	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2484	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2485	*/
2486	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2487
2488	/**
2489	* Unmaps an I/O port range.
2490	*
2491	* @returns VBox status.
2492	* @param pDevIns The device instance to register the ports with.
2493	* @param hIoPorts The I/O port range handle.
2494	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2495	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2496	*/
2497	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2498
2499	/**
2500	* Gets the mapping address of the I/O port range @a hIoPorts.
2501	*
2502	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2503	* parameters).
2504	* @param pDevIns The device instance to register the ports with.
2505	* @param hIoPorts The I/O port range handle.
2506	*/
2507	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2508	/** @} */
2509
2510	/** @name MMIO
2511	* @{ */
2512	/**
2513	* Creates a memory mapped I/O (MMIO) region for a device.
2514	*
2515	* The MMIO region must be mapped in a separately call. Any ring-0 and
2516	* raw-mode context callback handlers needs to be set up in the respective
2517	* contexts.
2518	*
2519	* @returns VBox status.
2520	* @param pDevIns The device instance to register the ports with.
2521	* @param cbRegion The size of the region in bytes.
2522	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2523	* @param pPciDev The PCI device the range is associated with, if
2524	* applicable.
2525	* @param iPciRegion The PCI device region in the high 16-bit word and
2526	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2527	* @param pfnWrite Pointer to function which is gonna handle Write
2528	* operations.
2529	* @param pfnRead Pointer to function which is gonna handle Read
2530	* operations.
2531	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2532	* operations. (optional)
2533	* @param pvUser User argument to pass to the callbacks.
2534	* @param pszDesc Pointer to description string. This must not be freed.
2535	* @param phRegion Where to return the MMIO region handle.
2536	*
2537	* @remarks Caller enters the device critical section prior to invoking the
2538	* registered callback methods.
2539	*
2540	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2541	*/
2542	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2543	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2544	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2545	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2546
2547	/**
2548	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2549	*
2550	* @returns VBox status.
2551	* @param pDevIns The device instance the region is associated with.
2552	* @param hRegion The MMIO region handle.
2553	* @param GCPhys Where to map the region.
2554	* @note An MMIO range may overlap with base memory if a lot of RAM is
2555	* configured for the VM, in which case we'll drop the base memory
2556	* pages. Presently we will make no attempt to preserve anything that
2557	* happens to be present in the base memory that is replaced, this is
2558	* technically incorrect but it's just not worth the effort to do
2559	* right, at least not at this point.
2560	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2561	* PDMDevHlpMmioSetUpContext
2562	*/
2563	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2564
2565	/**
2566	* Unmaps a memory mapped I/O (MMIO) region.
2567	*
2568	* @returns VBox status.
2569	* @param pDevIns The device instance the region is associated with.
2570	* @param hRegion The MMIO region handle.
2571	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2572	* PDMDevHlpMmioSetUpContext
2573	*/
2574	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2575
2576	/**
2577	* Reduces the length of a MMIO range.
2578	*
2579	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2580	* only work during saved state restore. It will not call the PCI bus code, as
2581	* that is expected to restore the saved resource configuration.
2582	*
2583	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2584	* called it will only map @a cbRegion bytes and not the value set during
2585	* registration.
2586	*
2587	* @return VBox status code.
2588	* @param pDevIns The device owning the range.
2589	* @param hRegion The MMIO region handle.
2590	* @param cbRegion The new size, must be smaller.
2591	*/
2592	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2593
2594	/**
2595	* Gets the mapping address of the MMIO region @a hRegion.
2596	*
2597	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2598	* @param pDevIns The device instance to register the ports with.
2599	* @param hRegion The MMIO region handle.
2600	*/
2601	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2602	/** @} */
2603
2604	/** @name MMIO2
2605	* @{ */
2606	/**
2607	* Creates a MMIO2 region.
2608	*
2609	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2610	* associated with a device. It is also non-shared memory with a permanent
2611	* ring-3 mapping and page backing (presently).
2612	*
2613	* @returns VBox status.
2614	* @param pDevIns The device instance.
2615	* @param pPciDev The PCI device the region is associated with, or
2616	* NULL if no PCI device association.
2617	* @param iPciRegion The region number. Use the PCI region number as
2618	* this must be known to the PCI bus device too. If
2619	* it's not associated with the PCI device, then
2620	* any number up to UINT8_MAX is fine.
2621	* @param cbRegion The size (in bytes) of the region.
2622	* @param fFlags Reserved for future use, must be zero.
2623	* @param pszDesc Pointer to description string. This must not be
2624	* freed.
2625	* @param ppvMapping Where to store the address of the ring-3 mapping
2626	* of the memory.
2627	* @param phRegion Where to return the MMIO2 region handle.
2628	*
2629	* @thread EMT(0)
2630	*/
2631	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2632	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2633
2634	/**
2635	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2636	*
2637	* Any physical access handlers registered for the region must be deregistered
2638	* before calling this function.
2639	*
2640	* @returns VBox status code.
2641	* @param pDevIns The device instance.
2642	* @param hRegion The MMIO2 region handle.
2643	* @thread EMT.
2644	*/
2645	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2646
2647	/**
2648	* Maps a MMIO2 region (into the guest physical address space).
2649	*
2650	* @returns VBox status.
2651	* @param pDevIns The device instance the region is associated with.
2652	* @param hRegion The MMIO2 region handle.
2653	* @param GCPhys Where to map the region.
2654	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2655	* configured for the VM, in which case we'll drop the base memory
2656	* pages. Presently we will make no attempt to preserve anything that
2657	* happens to be present in the base memory that is replaced, this is
2658	* technically incorrect but it's just not worth the effort to do
2659	* right, at least not at this point.
2660	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2661	*/
2662	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2663
2664	/**
2665	* Unmaps a MMIO2 region.
2666	*
2667	* @returns VBox status.
2668	* @param pDevIns The device instance the region is associated with.
2669	* @param hRegion The MMIO2 region handle.
2670	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2671	*/
2672	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2673
2674	/**
2675	* Reduces the length of a MMIO range.
2676	*
2677	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2678	* only work during saved state restore. It will not call the PCI bus code, as
2679	* that is expected to restore the saved resource configuration.
2680	*
2681	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2682	* called it will only map @a cbRegion bytes and not the value set during
2683	* registration.
2684	*
2685	* @return VBox status code.
2686	* @param pDevIns The device owning the range.
2687	* @param hRegion The MMIO2 region handle.
2688	* @param cbRegion The new size, must be smaller.
2689	*/
2690	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2691
2692	/**
2693	* Gets the mapping address of the MMIO region @a hRegion.
2694	*
2695	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2696	* @param pDevIns The device instance to register the ports with.
2697	* @param hRegion The MMIO2 region handle.
2698	*/
2699	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2700
2701	/**
2702	* Changes the number of an MMIO2 or pre-registered MMIO region.
2703	*
2704	* This should only be used to deal with saved state problems, so there is no
2705	* convenience inline wrapper for this method.
2706	*
2707	* @returns VBox status code.
2708	* @param pDevIns The device instance.
2709	* @param hRegion The MMIO2 region handle.
2710	* @param iNewRegion The new region index.
2711	*
2712	* @sa @bugref{9359}
2713	*/
2714	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2715	/** @} */
2716
2717	/**
2718	* Register a ROM (BIOS) region.
2719	*
2720	* It goes without saying that this is read-only memory. The memory region must be
2721	* in unassigned memory. I.e. from the top of the address space or on the PC in
2722	* the 0xa0000-0xfffff range.
2723	*
2724	* @returns VBox status.
2725	* @param pDevIns The device instance owning the ROM region.
2726	* @param GCPhysStart First physical address in the range.
2727	* Must be page aligned!
2728	* @param cbRange The size of the range (in bytes).
2729	* Must be page aligned!
2730	* @param pvBinary Pointer to the binary data backing the ROM image.
2731	* @param cbBinary The size of the binary pointer. This must
2732	* be equal or smaller than @a cbRange.
2733	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2734	* @param pszDesc Pointer to description string. This must not be freed.
2735	*
2736	* @remark There is no way to remove the rom, automatically on device cleanup or
2737	* manually from the device yet. At present I doubt we need such features...
2738	*/
2739	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2740	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2741
2742	/**
2743	* Changes the protection of shadowed ROM mapping.
2744	*
2745	* This is intented for use by the system BIOS, chipset or device in question to
2746	* change the protection of shadowed ROM code after init and on reset.
2747	*
2748	* @param pDevIns The device instance.
2749	* @param GCPhysStart Where the mapping starts.
2750	* @param cbRange The size of the mapping.
2751	* @param enmProt The new protection type.
2752	*/
2753	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2754
2755	/**
2756	* Register a save state data unit.
2757	*
2758	* @returns VBox status.
2759	* @param pDevIns The device instance.
2760	* @param uVersion Data layout version number.
2761	* @param cbGuess The approximate amount of data in the unit.
2762	* Only for progress indicators.
2763	* @param pszBefore Name of data unit which we should be put in
2764	* front of. Optional (NULL).
2765	*
2766	* @param pfnLivePrep Prepare live save callback, optional.
2767	* @param pfnLiveExec Execute live save callback, optional.
2768	* @param pfnLiveVote Vote live save callback, optional.
2769	*
2770	* @param pfnSavePrep Prepare save callback, optional.
2771	* @param pfnSaveExec Execute save callback, optional.
2772	* @param pfnSaveDone Done save callback, optional.
2773	*
2774	* @param pfnLoadPrep Prepare load callback, optional.
2775	* @param pfnLoadExec Execute load callback, optional.
2776	* @param pfnLoadDone Done load callback, optional.
2777	* @remarks Caller enters the device critical section prior to invoking the
2778	* registered callback methods.
2779	*/
2780	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2781	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2782	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2783	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2784
2785	/** @name Exported SSM Functions
2786	* @{ */
2787	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2788	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2789	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2790	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2791	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2792	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2793	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2794	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2795	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2796	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2797	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2798	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2799	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2800	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2801	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2802	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2803	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2804	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2805	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2806	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2807	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2808	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2809	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2810	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2811	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2812	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2813	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2814	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2815	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2816	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2817	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2818	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2819	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2820	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2821	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2822	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2823	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2824	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2825	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2826	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2827	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2828	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2829	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2830	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2831	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2832	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2833	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2834	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2835	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2836	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2837	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2838	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2839	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2840	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2841	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2842	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2843	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2844	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2845	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2846	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2847	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2848	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2849	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2850	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2851	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2852	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2853	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2854	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2855	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2856	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2857	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2858	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2859	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2860	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2861	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2862	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2863	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2864	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2865	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2866	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2867	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2868	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2869	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2870	/** @} */
2871
2872	/**
2873	* Creates a timer w/ a cross context handle.
2874	*
2875	* @returns VBox status.
2876	* @param pDevIns The device instance.
2877	* @param enmClock The clock to use on this timer.
2878	* @param pfnCallback Callback function.
2879	* @param pvUser User argument for the callback.
2880	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2881	* @param pszDesc Pointer to description string which must stay around
2882	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2883	* @param phTimer Where to store the timer handle on success.
2884	* @remarks Caller enters the device critical section prior to invoking the
2885	* callback.
2886	*/
2887	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2888	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
2889
2890	/** @name Timer handle method wrappers
2891	* @{ */
2892	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2893	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2894	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2895	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2896	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2897	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2898	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2899	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2900	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2901	/** Takes the clock lock then enters the specified critical section. */
2902	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2903	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2904	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2905	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2906	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2907	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2908	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2909	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2910	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2911	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2912	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2913	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2914	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2915	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2916	/** @sa TMR3TimerSkip */
2917	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2918	/** @} */
2919
2920	/**
2921	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2922	*
2923	* @returns pTime.
2924	* @param pDevIns The device instance.
2925	* @param pTime Where to store the time.
2926	*/
2927	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2928
2929	/** @name Exported CFGM Functions.
2930	* @{ */
2931	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2932	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2933	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
2934	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2935	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2936	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
2937	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
2938	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
2939	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2940	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2941	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
2942	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
2943	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
2944	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
2945	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
2946	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
2947	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
2948	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
2949	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
2950	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
2951	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
2952	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
2953	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
2954	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
2955	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
2956	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
2957	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2958	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2959	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
2960	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
2961	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
2962	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
2963	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
2964	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
2965	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
2966	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
2967	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
2968	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
2969	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
2970	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
2971	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
2972	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
2973	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
2974	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
2975	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
2976	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
2977	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
2978	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
2979	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
2980	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
2981	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
2982	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
2983	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
2984	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
2985	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
2986	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
2987	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
2988	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
2989	const char pszValidValues, const char pszValidNodes,
2990	const char *pszWho, uint32_t uInstance));
2991	/** @} */
2992
2993	/**
2994	* Read physical memory.
2995	*
2996	* @returns VINF_SUCCESS (for now).
2997	* @param pDevIns The device instance.
2998	* @param GCPhys Physical address start reading from.
2999	* @param pvBuf Where to put the read bits.
3000	* @param cbRead How many bytes to read.
3001	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3002	* @thread Any thread, but the call may involve the emulation thread.
3003	*/
3004	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3005
3006	/**
3007	* Write to physical memory.
3008	*
3009	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3010	* @param pDevIns The device instance.
3011	* @param GCPhys Physical address to write to.
3012	* @param pvBuf What to write.
3013	* @param cbWrite How many bytes to write.
3014	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3015	* @thread Any thread, but the call may involve the emulation thread.
3016	*/
3017	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3018
3019	/**
3020	* Requests the mapping of a guest page into ring-3.
3021	*
3022	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3023	* release it.
3024	*
3025	* This API will assume your intention is to write to the page, and will
3026	* therefore replace shared and zero pages. If you do not intend to modify the
3027	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3028	*
3029	* @returns VBox status code.
3030	* @retval VINF_SUCCESS on success.
3031	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3032	* backing or if the page has any active access handlers. The caller
3033	* must fall back on using PGMR3PhysWriteExternal.
3034	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3035	*
3036	* @param pDevIns The device instance.
3037	* @param GCPhys The guest physical address of the page that
3038	* should be mapped.
3039	* @param fFlags Flags reserved for future use, MBZ.
3040	* @param ppv Where to store the address corresponding to
3041	* GCPhys.
3042	* @param pLock Where to store the lock information that
3043	* pfnPhysReleasePageMappingLock needs.
3044	*
3045	* @remark Avoid calling this API from within critical sections (other than the
3046	* PGM one) because of the deadlock risk when we have to delegating the
3047	* task to an EMT.
3048	* @thread Any.
3049	*/
3050	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3051	PPGMPAGEMAPLOCK pLock));
3052
3053	/**
3054	* Requests the mapping of a guest page into ring-3, external threads.
3055	*
3056	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3057	* release it.
3058	*
3059	* @returns VBox status code.
3060	* @retval VINF_SUCCESS on success.
3061	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3062	* backing or if the page as an active ALL access handler. The caller
3063	* must fall back on using PGMPhysRead.
3064	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3065	*
3066	* @param pDevIns The device instance.
3067	* @param GCPhys The guest physical address of the page that
3068	* should be mapped.
3069	* @param fFlags Flags reserved for future use, MBZ.
3070	* @param ppv Where to store the address corresponding to
3071	* GCPhys.
3072	* @param pLock Where to store the lock information that
3073	* pfnPhysReleasePageMappingLock needs.
3074	*
3075	* @remark Avoid calling this API from within critical sections.
3076	* @thread Any.
3077	*/
3078	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3079	void const **ppv, PPGMPAGEMAPLOCK pLock));
3080
3081	/**
3082	* Release the mapping of a guest page.
3083	*
3084	* This is the counter part of pfnPhysGCPhys2CCPtr and
3085	* pfnPhysGCPhys2CCPtrReadOnly.
3086	*
3087	* @param pDevIns The device instance.
3088	* @param pLock The lock structure initialized by the mapping
3089	* function.
3090	*/
3091	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3092
3093	/**
3094	* Read guest physical memory by virtual address.
3095	*
3096	* @param pDevIns The device instance.
3097	* @param pvDst Where to put the read bits.
3098	* @param GCVirtSrc Guest virtual address to start reading from.
3099	* @param cb How many bytes to read.
3100	* @thread The emulation thread.
3101	*/
3102	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3103
3104	/**
3105	* Write to guest physical memory by virtual address.
3106	*
3107	* @param pDevIns The device instance.
3108	* @param GCVirtDst Guest virtual address to write to.
3109	* @param pvSrc What to write.
3110	* @param cb How many bytes to write.
3111	* @thread The emulation thread.
3112	*/
3113	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3114
3115	/**
3116	* Convert a guest virtual address to a guest physical address.
3117	*
3118	* @returns VBox status code.
3119	* @param pDevIns The device instance.
3120	* @param GCPtr Guest virtual address.
3121	* @param pGCPhys Where to store the GC physical address
3122	* corresponding to GCPtr.
3123	* @thread The emulation thread.
3124	* @remark Careful with page boundaries.
3125	*/
3126	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3127
3128	/**
3129	* Allocate memory which is associated with current VM instance
3130	* and automatically freed on it's destruction.
3131	*
3132	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3133	* @param pDevIns The device instance.
3134	* @param cb Number of bytes to allocate.
3135	*/
3136	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3137
3138	/**
3139	* Allocate memory which is associated with current VM instance
3140	* and automatically freed on it's destruction. The memory is ZEROed.
3141	*
3142	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3143	* @param pDevIns The device instance.
3144	* @param cb Number of bytes to allocate.
3145	*/
3146	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3147
3148	/**
3149	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3150	*
3151	* @param pDevIns The device instance.
3152	* @param pv Pointer to the memory to free.
3153	*/
3154	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3155
3156	/**
3157	* Gets the VM state.
3158	*
3159	* @returns VM state.
3160	* @param pDevIns The device instance.
3161	* @thread Any thread (just keep in mind that it's volatile info).
3162	*/
3163	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3164
3165	/**
3166	* Checks if the VM was teleported and hasn't been fully resumed yet.
3167	*
3168	* @returns true / false.
3169	* @param pDevIns The device instance.
3170	* @thread Any thread.
3171	*/
3172	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3173
3174	/**
3175	* Set the VM error message
3176	*
3177	* @returns rc.
3178	* @param pDevIns The device instance.
3179	* @param rc VBox status code.
3180	* @param SRC_POS Use RT_SRC_POS.
3181	* @param pszFormat Error message format string.
3182	* @param ... Error message arguments.
3183	*/
3184	DECLR3CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3185	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
3186
3187	/**
3188	* Set the VM error message
3189	*
3190	* @returns rc.
3191	* @param pDevIns The device instance.
3192	* @param rc VBox status code.
3193	* @param SRC_POS Use RT_SRC_POS.
3194	* @param pszFormat Error message format string.
3195	* @param va Error message arguments.
3196	*/
3197	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3198	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3199
3200	/**
3201	* Set the VM runtime error message
3202	*
3203	* @returns VBox status code.
3204	* @param pDevIns The device instance.
3205	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3206	* @param pszErrorId Error ID string.
3207	* @param pszFormat Error message format string.
3208	* @param ... Error message arguments.
3209	*/
3210	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3211	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
3212
3213	/**
3214	* Set the VM runtime error message
3215	*
3216	* @returns VBox status code.
3217	* @param pDevIns The device instance.
3218	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3219	* @param pszErrorId Error ID string.
3220	* @param pszFormat Error message format string.
3221	* @param va Error message arguments.
3222	*/
3223	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3224	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3225
3226	/**
3227	* Stops the VM and enters the debugger to look at the guest state.
3228	*
3229	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3230	* invoking this function directly.
3231	*
3232	* @returns VBox status code which must be passed up to the VMM.
3233	* @param pDevIns The device instance.
3234	* @param pszFile Filename of the assertion location.
3235	* @param iLine The linenumber of the assertion location.
3236	* @param pszFunction Function of the assertion location.
3237	* @param pszFormat Message. (optional)
3238	* @param args Message parameters.
3239	*/
3240	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3241	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3242
3243	/**
3244	* Register a info handler with DBGF.
3245	*
3246	* @returns VBox status code.
3247	* @param pDevIns The device instance.
3248	* @param pszName The identifier of the info.
3249	* @param pszDesc The description of the info and any arguments
3250	* the handler may take.
3251	* @param pfnHandler The handler function to be called to display the
3252	* info.
3253	*/
3254	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3255
3256	/**
3257	* Register a info handler with DBGF, argv style.
3258	*
3259	* @returns VBox status code.
3260	* @param pDevIns The device instance.
3261	* @param pszName The identifier of the info.
3262	* @param pszDesc The description of the info and any arguments
3263	* the handler may take.
3264	* @param pfnHandler The handler function to be called to display the
3265	* info.
3266	*/
3267	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3268
3269	/**
3270	* Registers a set of registers for a device.
3271	*
3272	* The @a pvUser argument of the getter and setter callbacks will be
3273	* @a pDevIns. The register names will be prefixed by the device name followed
3274	* immediately by the instance number.
3275	*
3276	* @returns VBox status code.
3277	* @param pDevIns The device instance.
3278	* @param paRegisters The register descriptors.
3279	*
3280	* @remarks The device critical section is NOT entered prior to working the
3281	* callbacks registered via this helper!
3282	*/
3283	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3284
3285	/**
3286	* Gets the trace buffer handle.
3287	*
3288	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3289	* really inteded for direct usage, thus no inline wrapper function.
3290	*
3291	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3292	* @param pDevIns The device instance.
3293	*/
3294	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3295
3296	/**
3297	* Registers a statistics sample.
3298	*
3299	* @param pDevIns Device instance of the DMA.
3300	* @param pvSample Pointer to the sample.
3301	* @param enmType Sample type. This indicates what pvSample is
3302	* pointing at.
3303	* @param pszName Sample name, unix path style. If this does not
3304	* start with a '/', the default prefix will be
3305	* prepended, otherwise it will be used as-is.
3306	* @param enmUnit Sample unit.
3307	* @param pszDesc Sample description.
3308	*/
3309	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3310
3311	/**
3312	* Same as pfnSTAMRegister except that the name is specified in a
3313	* RTStrPrintfV like fashion.
3314	*
3315	* @returns VBox status.
3316	* @param pDevIns Device instance of the DMA.
3317	* @param pvSample Pointer to the sample.
3318	* @param enmType Sample type. This indicates what pvSample is
3319	* pointing at.
3320	* @param enmVisibility Visibility type specifying whether unused
3321	* statistics should be visible or not.
3322	* @param enmUnit Sample unit.
3323	* @param pszDesc Sample description.
3324	* @param pszName Sample name format string, unix path style. If
3325	* this does not start with a '/', the default
3326	* prefix will be prepended, otherwise it will be
3327	* used as-is.
3328	* @param args Arguments to the format string.
3329	*/
3330	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3331	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3332	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3333
3334	/**
3335	* Registers a PCI device with the default PCI bus.
3336	*
3337	* If a PDM device has more than one PCI device, they must be registered in the
3338	* order of PDMDEVINSR3::apPciDevs.
3339	*
3340	* @returns VBox status code.
3341	* @param pDevIns The device instance.
3342	* @param pPciDev The PCI device structure.
3343	* This must be kept in the instance data.
3344	* The PCI configuration must be initialized before registration.
3345	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3346	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3347	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3348	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3349	* device number (0-31). This will be ignored if
3350	* the CFGM configuration contains a PCIDeviceNo
3351	* value.
3352	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3353	* function number (0-7). This will be ignored if
3354	* the CFGM configuration contains a PCIFunctionNo
3355	* value.
3356	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3357	* The pointer is saved, so don't free or changed.
3358	* @note The PCI device configuration is now implicit from the apPciDevs
3359	* index, meaning that the zero'th entry is the primary one and
3360	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3361	*/
3362	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3363	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3364
3365	/**
3366	* Initialize MSI or MSI-X emulation support for the given PCI device.
3367	*
3368	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3369	*
3370	* @returns VBox status code.
3371	* @param pDevIns The device instance.
3372	* @param pPciDev The PCI device. NULL is an alias for the first
3373	* one registered.
3374	* @param pMsiReg MSI emulation registration structure.
3375	*/
3376	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3377
3378	/**
3379	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3380	*
3381	* @returns VBox status code.
3382	* @param pDevIns The device instance.
3383	* @param pPciDev The PCI device structure. If NULL the default
3384	* PCI device for this device instance is used.
3385	* @param iRegion The region number.
3386	* @param cbRegion Size of the region.
3387	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3388	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3389	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3390	* @a fFlags, UINT64_MAX if no handle is passed
3391	* (old style).
3392	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3393	* handle is specified. The callback will be
3394	* invoked holding only the PDM lock. The device
3395	* lock will _not_ be taken (due to lock order).
3396	*/
3397	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3398	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3399	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3400
3401	/**
3402	* Register PCI configuration space read/write callbacks.
3403	*
3404	* @returns VBox status code.
3405	* @param pDevIns The device instance.
3406	* @param pPciDev The PCI device structure. If NULL the default
3407	* PCI device for this device instance is used.
3408	* @param pfnRead Pointer to the user defined PCI config read function.
3409	* to call default PCI config read function. Can be NULL.
3410	* @param pfnWrite Pointer to the user defined PCI config write function.
3411	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3412	* is NOT take because that is very likely be a lock order violation.
3413	* @thread EMT(0)
3414	* @note Only callable during VM creation.
3415	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3416	*/
3417	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3418	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3419
3420	/**
3421	* Perform a PCI configuration space write.
3422	*
3423	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3424	*
3425	* @returns Strict VBox status code (mainly DBGFSTOP).
3426	* @param pDevIns The device instance.
3427	* @param pPciDev The PCI device which config space is being read.
3428	* @param uAddress The config space address.
3429	* @param cb The size of the read: 1, 2 or 4 bytes.
3430	* @param u32Value The value to write.
3431	*/
3432	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3433	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3434
3435	/**
3436	* Perform a PCI configuration space read.
3437	*
3438	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3439	*
3440	* @returns Strict VBox status code (mainly DBGFSTOP).
3441	* @param pDevIns The device instance.
3442	* @param pPciDev The PCI device which config space is being read.
3443	* @param uAddress The config space address.
3444	* @param cb The size of the read: 1, 2 or 4 bytes.
3445	* @param pu32Value Where to return the value.
3446	*/
3447	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3448	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3449
3450	/**
3451	* Bus master physical memory read.
3452	*
3453	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3454	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3455	* @param pDevIns The device instance.
3456	* @param pPciDev The PCI device structure. If NULL the default
3457	* PCI device for this device instance is used.
3458	* @param GCPhys Physical address start reading from.
3459	* @param pvBuf Where to put the read bits.
3460	* @param cbRead How many bytes to read.
3461	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3462	* @thread Any thread, but the call may involve the emulation thread.
3463	*/
3464	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3465
3466	/**
3467	* Bus master physical memory write.
3468	*
3469	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3470	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3471	* @param pDevIns The device instance.
3472	* @param pPciDev The PCI device structure. If NULL the default
3473	* PCI device for this device instance is used.
3474	* @param GCPhys Physical address to write to.
3475	* @param pvBuf What to write.
3476	* @param cbWrite How many bytes to write.
3477	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3478	* @thread Any thread, but the call may involve the emulation thread.
3479	*/
3480	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3481
3482	/**
3483	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3484	* physical memory write operation.
3485	*
3486	* Refer pfnPhysGCPhys2CCPtr() for further details.
3487	*
3488	* @returns VBox status code.
3489	* @param pDevIns The device instance.
3490	* @param pPciDev The PCI device structure. If NULL the default
3491	* PCI device for this device instance is used.
3492	* @param GCPhys The guest physical address of the page that should be
3493	* mapped.
3494	* @param fFlags Flags reserved for future use, MBZ.
3495	* @param ppv Where to store the address corresponding to GCPhys.
3496	* @param pLock Where to store the lock information that
3497	* pfnPhysReleasePageMappingLock needs.
3498	*
3499	* @remarks Avoid calling this API from within critical sections (other than the PGM
3500	* one) because of the deadlock risk when we have to delegating the task to
3501	* an EMT.
3502	* @thread Any.
3503	*/
3504	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3505	void **ppv, PPGMPAGEMAPLOCK pLock));
3506
3507	/**
3508	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3509	* for a bus master physical memory read operation.
3510	*
3511	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3512	*
3513	* @returns VBox status code.
3514	* @param pDevIns The device instance.
3515	* @param pPciDev The PCI device structure. If NULL the default
3516	* PCI device for this device instance is used.
3517	* @param GCPhys The guest physical address of the page that
3518	* should be mapped.
3519	* @param fFlags Flags reserved for future use, MBZ.
3520	* @param ppv Where to store the address corresponding to
3521	* GCPhys.
3522	* @param pLock Where to store the lock information that
3523	* pfnPhysReleasePageMappingLock needs.
3524	*
3525	* @remarks Avoid calling this API from within critical sections.
3526	* @thread Any.
3527	*/
3528	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3529	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3530
3531	/**
3532	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3533	* master physical memory write operation.
3534	*
3535	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3536	* ASAP to release them.
3537	*
3538	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3539	*
3540	* @returns VBox status code.
3541	* @param pDevIns The device instance.
3542	* @param pPciDev The PCI device structure. If NULL the default
3543	* PCI device for this device instance is used.
3544	* @param cPages Number of pages to lock.
3545	* @param paGCPhysPages The guest physical address of the pages that
3546	* should be mapped (@a cPages entries).
3547	* @param fFlags Flags reserved for future use, MBZ.
3548	* @param papvPages Where to store the ring-3 mapping addresses
3549	* corresponding to @a paGCPhysPages.
3550	* @param paLocks Where to store the locking information that
3551	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3552	* in length).
3553	*/
3554	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3555	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3556	PPGMPAGEMAPLOCK paLocks));
3557
3558	/**
3559	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3560	* master physical memory read operation.
3561	*
3562	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3563	* ASAP to release them.
3564	*
3565	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3566	*
3567	* @returns VBox status code.
3568	* @param pDevIns The device instance.
3569	* @param pPciDev The PCI device structure. If NULL the default
3570	* PCI device for this device instance is used.
3571	* @param cPages Number of pages to lock.
3572	* @param paGCPhysPages The guest physical address of the pages that
3573	* should be mapped (@a cPages entries).
3574	* @param fFlags Flags reserved for future use, MBZ.
3575	* @param papvPages Where to store the ring-3 mapping addresses
3576	* corresponding to @a paGCPhysPages.
3577	* @param paLocks Where to store the lock information that
3578	* pfnPhysReleasePageMappingLock needs (@a cPages
3579	* in length).
3580	*/
3581	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3582	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3583	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3584
3585	/**
3586	* Sets the IRQ for the given PCI device.
3587	*
3588	* @param pDevIns The device instance.
3589	* @param pPciDev The PCI device structure. If NULL the default
3590	* PCI device for this device instance is used.
3591	* @param iIrq IRQ number to set.
3592	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3593	* @thread Any thread, but will involve the emulation thread.
3594	*/
3595	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3596
3597	/**
3598	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3599	* the request when not called from EMT.
3600	*
3601	* @param pDevIns The device instance.
3602	* @param pPciDev The PCI device structure. If NULL the default
3603	* PCI device for this device instance is used.
3604	* @param iIrq IRQ number to set.
3605	* @param iLevel IRQ level.
3606	* @thread Any thread, but will involve the emulation thread.
3607	*/
3608	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3609
3610	/**
3611	* Set ISA IRQ for a device.
3612	*
3613	* @param pDevIns The device instance.
3614	* @param iIrq IRQ number to set.
3615	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3616	* @thread Any thread, but will involve the emulation thread.
3617	*/
3618	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3619
3620	/**
3621	* Set the ISA IRQ for a device, but don't wait for EMT to process
3622	* the request when not called from EMT.
3623	*
3624	* @param pDevIns The device instance.
3625	* @param iIrq IRQ number to set.
3626	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3627	* @thread Any thread, but will involve the emulation thread.
3628	*/
3629	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3630
3631	/**
3632	* Attaches a driver (chain) to the device.
3633	*
3634	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3635	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3636	*
3637	* @returns VBox status code.
3638	* @param pDevIns The device instance.
3639	* @param iLun The logical unit to attach.
3640	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3641	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3642	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3643	* for the live of the device instance.
3644	*/
3645	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3646	PPDMIBASE ppBaseInterface, const char pszDesc));
3647
3648	/**
3649	* Detaches an attached driver (chain) from the device again.
3650	*
3651	* @returns VBox status code.
3652	* @param pDevIns The device instance.
3653	* @param pDrvIns The driver instance to detach.
3654	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3655	*/
3656	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3657
3658	/**
3659	* Reconfigures the driver chain for a LUN, detaching any driver currently
3660	* present there.
3661	*
3662	* Caller will have attach it, of course.
3663	*
3664	* @returns VBox status code.
3665	* @param pDevIns The device instance.
3666	* @param iLun The logical unit to reconfigure.
3667	* @param cDepth The depth of the driver chain. Determins the
3668	* size of @a papszDrivers and @a papConfigs.
3669	* @param papszDrivers The names of the drivers to configure in the
3670	* chain, first entry is the one immediately
3671	* below the device/LUN
3672	* @param papConfigs The configurations for each of the drivers
3673	* in @a papszDrivers array. NULL entries
3674	* corresponds to empty 'Config' nodes. This
3675	* function will take ownership of non-NULL
3676	* CFGM sub-trees and set the array member to
3677	* NULL, so the caller can do cleanups on
3678	* failure. This parameter is optional.
3679	* @param fFlags Reserved, MBZ.
3680	*/
3681	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3682	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3683
3684	/** @name Exported PDM Queue Functions
3685	* @{ */
3686	/**
3687	* Create a queue.
3688	*
3689	* @returns VBox status code.
3690	* @param pDevIns The device instance.
3691	* @param cbItem The size of a queue item.
3692	* @param cItems The number of items in the queue.
3693	* @param cMilliesInterval The number of milliseconds between polling the queue.
3694	* If 0 then the emulation thread will be notified whenever an item arrives.
3695	* @param pfnCallback The consumer function.
3696	* @param fRZEnabled Set if the queue should work in RC and R0.
3697	* @param pszName The queue base name. The instance number will be
3698	* appended automatically.
3699	* @param ppQueue Where to store the queue pointer on success.
3700	* @thread The emulation thread.
3701	* @remarks The device critical section will NOT be entered before calling the
3702	* callback. No locks will be held, but for now it's safe to assume
3703	* that only one EMT will do queue callbacks at any one time.
3704	*/
3705	DECLR3CALLBACKMEMBER(int, pfnQueueCreatePtr,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3706	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3707	PPDMQUEUE *ppQueue));
3708
3709	/**
3710	* Create a queue.
3711	*
3712	* @returns VBox status code.
3713	* @param pDevIns The device instance.
3714	* @param cbItem The size of a queue item.
3715	* @param cItems The number of items in the queue.
3716	* @param cMilliesInterval The number of milliseconds between polling the queue.
3717	* If 0 then the emulation thread will be notified whenever an item arrives.
3718	* @param pfnCallback The consumer function.
3719	* @param fRZEnabled Set if the queue should work in RC and R0.
3720	* @param pszName The queue base name. The instance number will be
3721	* appended automatically.
3722	* @param phQueue Where to store the queue handle on success.
3723	* @thread EMT(0)
3724	* @remarks The device critical section will NOT be entered before calling the
3725	* callback. No locks will be held, but for now it's safe to assume
3726	* that only one EMT will do queue callbacks at any one time.
3727	*/
3728	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3729	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3730	PDMQUEUEHANDLE *phQueue));
3731
3732	DECLR3CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3733	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3734	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3735	DECLR3CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
3736	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3737	/** @} */
3738
3739	/** @name PDM Task
3740	* @{ */
3741	/**
3742	* Create an asynchronous ring-3 task.
3743	*
3744	* @returns VBox status code.
3745	* @param pDevIns The device instance.
3746	* @param fFlags PDMTASK_F_XXX
3747	* @param pszName The function name or similar. Used for statistics,
3748	* so no slashes.
3749	* @param pfnCallback The task function.
3750	* @param pvUser User argument for the task function.
3751	* @param phTask Where to return the task handle.
3752	* @thread EMT(0)
3753	*/
3754	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3755	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3756	/**
3757	* Triggers the running the given task.
3758	*
3759	* @returns VBox status code.
3760	* @retval VINF_ALREADY_POSTED is the task is already pending.
3761	* @param pDevIns The device instance.
3762	* @param hTask The task to trigger.
3763	* @thread Any thread.
3764	*/
3765	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3766	/** @} */
3767
3768	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3769	* These semaphores can be signalled from ring-0.
3770	* @{ */
3771	/** @sa SUPSemEventCreate */
3772	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3773	/** @sa SUPSemEventClose */
3774	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3775	/** @sa SUPSemEventSignal */
3776	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3777	/** @sa SUPSemEventWaitNoResume */
3778	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3779	/** @sa SUPSemEventWaitNsAbsIntr */
3780	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3781	/** @sa SUPSemEventWaitNsRelIntr */
3782	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3783	/** @sa SUPSemEventGetResolution */
3784	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3785	/** @} */
3786
3787	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3788	* These semaphores can be signalled from ring-0.
3789	* @{ */
3790	/** @sa SUPSemEventMultiCreate */
3791	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3792	/** @sa SUPSemEventMultiClose */
3793	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3794	/** @sa SUPSemEventMultiSignal */
3795	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3796	/** @sa SUPSemEventMultiReset */
3797	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3798	/** @sa SUPSemEventMultiWaitNoResume */
3799	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3800	/** @sa SUPSemEventMultiWaitNsAbsIntr */
3801	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3802	/** @sa SUPSemEventMultiWaitNsRelIntr */
3803	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3804	/** @sa SUPSemEventMultiGetResolution */
3805	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3806	/** @} */
3807
3808	/**
3809	* Initializes a PDM critical section.
3810	*
3811	* The PDM critical sections are derived from the IPRT critical sections, but
3812	* works in RC and R0 as well.
3813	*
3814	* @returns VBox status code.
3815	* @param pDevIns The device instance.
3816	* @param pCritSect Pointer to the critical section.
3817	* @param SRC_POS Use RT_SRC_POS.
3818	* @param pszNameFmt Format string for naming the critical section.
3819	* For statistics and lock validation.
3820	* @param va Arguments for the format string.
3821	*/
3822	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3823	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3824
3825	/**
3826	* Gets the NOP critical section.
3827	*
3828	* @returns The ring-3 address of the NOP critical section.
3829	* @param pDevIns The device instance.
3830	*/
3831	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3832
3833	/**
3834	* Gets the NOP critical section.
3835	*
3836	* @returns The ring-0 address of the NOP critical section.
3837	* @param pDevIns The device instance.
3838	* @deprecated
3839	*/
3840	DECLR3CALLBACKMEMBER(R0PTRTYPE(PPDMCRITSECT), pfnCritSectGetNopR0,(PPDMDEVINS pDevIns));
3841
3842	/**
3843	* Gets the NOP critical section.
3844	*
3845	* @returns The raw-mode context address of the NOP critical section.
3846	* @param pDevIns The device instance.
3847	* @deprecated
3848	*/
3849	DECLR3CALLBACKMEMBER(RCPTRTYPE(PPDMCRITSECT), pfnCritSectGetNopRC,(PPDMDEVINS pDevIns));
3850
3851	/**
3852	* Changes the device level critical section from the automatically created
3853	* default to one desired by the device constructor.
3854	*
3855	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
3856	* the additional contexts.
3857	*
3858	* @returns VBox status code.
3859	* @param pDevIns The device instance.
3860	* @param pCritSect The critical section to use. NULL is not
3861	* valid, instead use the NOP critical
3862	* section.
3863	*/
3864	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3865
3866	/** @name Exported PDM Critical Section Functions
3867	* @{ */
3868	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3869	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3870	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3871	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3872	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3873	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3874	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3875	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3876	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3877	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3878	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3879	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3880	/** @} */
3881
3882	/**
3883	* Creates a PDM thread.
3884	*
3885	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3886	* resuming, and destroying the thread as the VM state changes.
3887	*
3888	* @returns VBox status code.
3889	* @param pDevIns The device instance.
3890	* @param ppThread Where to store the thread 'handle'.
3891	* @param pvUser The user argument to the thread function.
3892	* @param pfnThread The thread function.
3893	* @param pfnWakeup The wakup callback. This is called on the EMT
3894	* thread when a state change is pending.
3895	* @param cbStack See RTThreadCreate.
3896	* @param enmType See RTThreadCreate.
3897	* @param pszName See RTThreadCreate.
3898	* @remarks The device critical section will NOT be entered prior to invoking
3899	* the function pointers.
3900	*/
3901	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3902	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3903
3904	/** @name Exported PDM Thread Functions
3905	* @{ */
3906	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3907	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3908	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3909	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3910	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3911	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3912	/** @} */
3913
3914	/**
3915	* Set up asynchronous handling of a suspend, reset or power off notification.
3916	*
3917	* This shall only be called when getting the notification. It must be called
3918	* for each one.
3919	*
3920	* @returns VBox status code.
3921	* @param pDevIns The device instance.
3922	* @param pfnAsyncNotify The callback.
3923	* @thread EMT(0)
3924	* @remarks The caller will enter the device critical section prior to invoking
3925	* the callback.
3926	*/
3927	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3928
3929	/**
3930	* Notify EMT(0) that the device has completed the asynchronous notification
3931	* handling.
3932	*
3933	* This can be called at any time, spurious calls will simply be ignored.
3934	*
3935	* @param pDevIns The device instance.
3936	* @thread Any
3937	*/
3938	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
3939
3940	/**
3941	* Register the RTC device.
3942	*
3943	* @returns VBox status code.
3944	* @param pDevIns The device instance.
3945	* @param pRtcReg Pointer to a RTC registration structure.
3946	* @param ppRtcHlp Where to store the pointer to the helper
3947	* functions.
3948	*/
3949	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
3950
3951	/**
3952	* Register a PCI Bus.
3953	*
3954	* @returns VBox status code, but the positive values 0..31 are used to indicate
3955	* bus number rather than informational status codes.
3956	* @param pDevIns The device instance.
3957	* @param pPciBusReg Pointer to PCI bus registration structure.
3958	* @param ppPciHlp Where to store the pointer to the PCI Bus
3959	* helpers.
3960	* @param piBus Where to return the PDM bus number. Optional.
3961	*/
3962	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
3963	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
3964
3965	/**
3966	* Register the IOMMU device.
3967	*
3968	* @returns VBox status code.
3969	* @param pDevIns The device instance.
3970	* @param pIommuReg Pointer to a IOMMU registration structure.
3971	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
3972	* helpers.
3973	* @param pidxIommu Where to return the IOMMU index. Optional.
3974	*/
3975	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
3976	uint32_t *pidxIommu));
3977
3978	/**
3979	* Register the PIC device.
3980	*
3981	* @returns VBox status code.
3982	* @param pDevIns The device instance.
3983	* @param pPicReg Pointer to a PIC registration structure.
3984	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
3985	* helpers.
3986	* @sa PDMDevHlpPICSetUpContext
3987	*/
3988	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
3989
3990	/**
3991	* Register the APIC device.
3992	*
3993	* @returns VBox status code.
3994	* @param pDevIns The device instance.
3995	*/
3996	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
3997
3998	/**
3999	* Register the I/O APIC device.
4000	*
4001	* @returns VBox status code.
4002	* @param pDevIns The device instance.
4003	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4004	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
4005	* helpers.
4006	*/
4007	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4008
4009	/**
4010	* Register the HPET device.
4011	*
4012	* @returns VBox status code.
4013	* @param pDevIns The device instance.
4014	* @param pHpetReg Pointer to a HPET registration structure.
4015	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4016	* helpers.
4017	*/
4018	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4019
4020	/**
4021	* Register a raw PCI device.
4022	*
4023	* @returns VBox status code.
4024	* @param pDevIns The device instance.
4025	* @param pPciRawReg Pointer to a raw PCI registration structure.
4026	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4027	* device helpers.
4028	*/
4029	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4030
4031	/**
4032	* Register the DMA device.
4033	*
4034	* @returns VBox status code.
4035	* @param pDevIns The device instance.
4036	* @param pDmacReg Pointer to a DMAC registration structure.
4037	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4038	*/
4039	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4040
4041	/**
4042	* Register transfer function for DMA channel.
4043	*
4044	* @returns VBox status code.
4045	* @param pDevIns The device instance.
4046	* @param uChannel Channel number.
4047	* @param pfnTransferHandler Device specific transfer callback function.
4048	* @param pvUser User pointer to pass to the callback.
4049	* @thread EMT
4050	*/
4051	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4052
4053	/**
4054	* Read memory.
4055	*
4056	* @returns VBox status code.
4057	* @param pDevIns The device instance.
4058	* @param uChannel Channel number.
4059	* @param pvBuffer Pointer to target buffer.
4060	* @param off DMA position.
4061	* @param cbBlock Block size.
4062	* @param pcbRead Where to store the number of bytes which was
4063	* read. optional.
4064	* @thread EMT
4065	*/
4066	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4067
4068	/**
4069	* Write memory.
4070	*
4071	* @returns VBox status code.
4072	* @param pDevIns The device instance.
4073	* @param uChannel Channel number.
4074	* @param pvBuffer Memory to write.
4075	* @param off DMA position.
4076	* @param cbBlock Block size.
4077	* @param pcbWritten Where to store the number of bytes which was
4078	* written. optional.
4079	* @thread EMT
4080	*/
4081	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4082
4083	/**
4084	* Set the DREQ line.
4085	*
4086	* @returns VBox status code.
4087	* @param pDevIns Device instance.
4088	* @param uChannel Channel number.
4089	* @param uLevel Level of the line.
4090	* @thread EMT
4091	*/
4092	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4093
4094	/**
4095	* Get channel mode.
4096	*
4097	* @returns Channel mode. See specs.
4098	* @param pDevIns The device instance.
4099	* @param uChannel Channel number.
4100	* @thread EMT
4101	*/
4102	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4103
4104	/**
4105	* Schedule DMA execution.
4106	*
4107	* @param pDevIns The device instance.
4108	* @thread Any thread.
4109	*/
4110	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4111
4112	/**
4113	* Write CMOS value and update the checksum(s).
4114	*
4115	* @returns VBox status code.
4116	* @param pDevIns The device instance.
4117	* @param iReg The CMOS register index.
4118	* @param u8Value The CMOS register value.
4119	* @thread EMT
4120	*/
4121	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4122
4123	/**
4124	* Read CMOS value.
4125	*
4126	* @returns VBox status code.
4127	* @param pDevIns The device instance.
4128	* @param iReg The CMOS register index.
4129	* @param pu8Value Where to store the CMOS register value.
4130	* @thread EMT
4131	*/
4132	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4133
4134	/**
4135	* Assert that the current thread is the emulation thread.
4136	*
4137	* @returns True if correct.
4138	* @returns False if wrong.
4139	* @param pDevIns The device instance.
4140	* @param pszFile Filename of the assertion location.
4141	* @param iLine The linenumber of the assertion location.
4142	* @param pszFunction Function of the assertion location.
4143	*/
4144	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4145
4146	/**
4147	* Assert that the current thread is NOT the emulation thread.
4148	*
4149	* @returns True if correct.
4150	* @returns False if wrong.
4151	* @param pDevIns The device instance.
4152	* @param pszFile Filename of the assertion location.
4153	* @param iLine The linenumber of the assertion location.
4154	* @param pszFunction Function of the assertion location.
4155	*/
4156	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4157
4158	/**
4159	* Resolves the symbol for a raw-mode context interface.
4160	*
4161	* @returns VBox status code.
4162	* @param pDevIns The device instance.
4163	* @param pvInterface The interface structure.
4164	* @param cbInterface The size of the interface structure.
4165	* @param pszSymPrefix What to prefix the symbols in the list with
4166	* before resolving them. This must start with
4167	* 'dev' and contain the driver name.
4168	* @param pszSymList List of symbols corresponding to the interface.
4169	* There is generally a there is generally a define
4170	* holding this list associated with the interface
4171	* definition (INTERFACE_SYM_LIST). For more
4172	* details see PDMR3LdrGetInterfaceSymbols.
4173	* @thread EMT
4174	*/
4175	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4176	const char pszSymPrefix, const char pszSymList));
4177
4178	/**
4179	* Resolves the symbol for a ring-0 context interface.
4180	*
4181	* @returns VBox status code.
4182	* @param pDevIns The device instance.
4183	* @param pvInterface The interface structure.
4184	* @param cbInterface The size of the interface structure.
4185	* @param pszSymPrefix What to prefix the symbols in the list with
4186	* before resolving them. This must start with
4187	* 'dev' and contain the driver name.
4188	* @param pszSymList List of symbols corresponding to the interface.
4189	* There is generally a there is generally a define
4190	* holding this list associated with the interface
4191	* definition (INTERFACE_SYM_LIST). For more
4192	* details see PDMR3LdrGetInterfaceSymbols.
4193	* @thread EMT
4194	*/
4195	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4196	const char pszSymPrefix, const char pszSymList));
4197
4198	/**
4199	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4200	*
4201	* @returns VBox status code.
4202	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4203	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4204	*
4205	* @param pDevIns The device instance.
4206	* @param uOperation The operation to perform.
4207	* @param u64Arg 64-bit integer argument.
4208	* @thread EMT
4209	*/
4210	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4211
4212	/**
4213	* Gets the reason for the most recent VM suspend.
4214	*
4215	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4216	* suspend has been made or if the pDevIns is invalid.
4217	* @param pDevIns The device instance.
4218	*/
4219	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4220
4221	/**
4222	* Gets the reason for the most recent VM resume.
4223	*
4224	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4225	* resume has been made or if the pDevIns is invalid.
4226	* @param pDevIns The device instance.
4227	*/
4228	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4229
4230	/**
4231	* Requests the mapping of multiple guest page into ring-3.
4232	*
4233	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4234	* ASAP to release them.
4235	*
4236	* This API will assume your intention is to write to the pages, and will
4237	* therefore replace shared and zero pages. If you do not intend to modify the
4238	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4239	*
4240	* @returns VBox status code.
4241	* @retval VINF_SUCCESS on success.
4242	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4243	* backing or if any of the pages the page has any active access
4244	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4245	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4246	* an invalid physical address.
4247	*
4248	* @param pDevIns The device instance.
4249	* @param cPages Number of pages to lock.
4250	* @param paGCPhysPages The guest physical address of the pages that
4251	* should be mapped (@a cPages entries).
4252	* @param fFlags Flags reserved for future use, MBZ.
4253	* @param papvPages Where to store the ring-3 mapping addresses
4254	* corresponding to @a paGCPhysPages.
4255	* @param paLocks Where to store the locking information that
4256	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4257	* in length).
4258	*
4259	* @remark Avoid calling this API from within critical sections (other than the
4260	* PGM one) because of the deadlock risk when we have to delegating the
4261	* task to an EMT.
4262	* @thread Any.
4263	* @since 6.0.6
4264	*/
4265	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4266	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4267
4268	/**
4269	* Requests the mapping of multiple guest page into ring-3, for reading only.
4270	*
4271	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4272	* ASAP to release them.
4273	*
4274	* @returns VBox status code.
4275	* @retval VINF_SUCCESS on success.
4276	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4277	* backing or if any of the pages the page has an active ALL access
4278	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4279	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4280	* an invalid physical address.
4281	*
4282	* @param pDevIns The device instance.
4283	* @param cPages Number of pages to lock.
4284	* @param paGCPhysPages The guest physical address of the pages that
4285	* should be mapped (@a cPages entries).
4286	* @param fFlags Flags reserved for future use, MBZ.
4287	* @param papvPages Where to store the ring-3 mapping addresses
4288	* corresponding to @a paGCPhysPages.
4289	* @param paLocks Where to store the lock information that
4290	* pfnPhysReleasePageMappingLock needs (@a cPages
4291	* in length).
4292	*
4293	* @remark Avoid calling this API from within critical sections.
4294	* @thread Any.
4295	* @since 6.0.6
4296	*/
4297	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4298	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4299
4300	/**
4301	* Release the mappings of multiple guest pages.
4302	*
4303	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4304	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4305	*
4306	* @param pDevIns The device instance.
4307	* @param cPages Number of pages to unlock.
4308	* @param paLocks The lock structures initialized by the mapping
4309	* function (@a cPages in length).
4310	* @thread Any.
4311	* @since 6.0.6
4312	*/
4313	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4314
4315	/**
4316	* Returns the micro architecture used for the guest.
4317	*
4318	* @returns CPU micro architecture enum.
4319	* @param pDevIns The device instance.
4320	*/
4321	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4322
4323	/**
4324	* Get the number of physical and linear address bits supported by the guest.
4325	*
4326	* @param pDevIns The device instance.
4327	* @param pcPhysAddrWidth Where to store the number of physical address bits
4328	* supported by the guest.
4329	* @param pcLinearAddrWidth Where to store the number of linear address bits
4330	* supported by the guest.
4331	*/
4332	DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4333	uint8_t *pcLinearAddrWidth));
4334
4335	/** Space reserved for future members.
4336	* @{ */
4337	/**
4338	* Deregister zero or more samples given their name prefix.
4339	*
4340	* @returns VBox status code.
4341	* @param pDevIns The device instance.
4342	* @param pszPrefix The name prefix of the samples to remove. If this does
4343	* not start with a '/', the default prefix will be
4344	* prepended, otherwise it will be used as-is.
4345	*/
4346	DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4347	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4348	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4349	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4350	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4351	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4352	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4353	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4354	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4355	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4356	/** @} */
4357
4358
4359	/** API available to trusted devices only.
4360	*
4361	* These APIs are providing unrestricted access to the guest and the VM,
4362	* or they are interacting intimately with PDM.
4363	*
4364	* @{
4365	*/
4366
4367	/**
4368	* Gets the user mode VM handle. Restricted API.
4369	*
4370	* @returns User mode VM Handle.
4371	* @param pDevIns The device instance.
4372	*/
4373	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4374
4375	/**
4376	* Gets the global VM handle. Restricted API.
4377	*
4378	* @returns VM Handle.
4379	* @param pDevIns The device instance.
4380	*/
4381	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4382
4383	/**
4384	* Gets the VMCPU handle. Restricted API.
4385	*
4386	* @returns VMCPU Handle.
4387	* @param pDevIns The device instance.
4388	*/
4389	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4390
4391	/**
4392	* The the VM CPU ID of the current thread (restricted API).
4393	*
4394	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4395	* @param pDevIns The device instance.
4396	*/
4397	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4398
4399	/**
4400	* Registers the VMM device heap or notifies about mapping/unmapping.
4401	*
4402	* This interface serves three purposes:
4403	*
4404	* -# Register the VMM device heap during device construction
4405	* for the HM to use.
4406	* -# Notify PDM/HM that it's mapped into guest address
4407	* space (i.e. usable).
4408	* -# Notify PDM/HM that it is being unmapped from the guest
4409	* address space (i.e. not usable).
4410	*
4411	* @returns VBox status code.
4412	* @param pDevIns The device instance.
4413	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4414	* not mapped.
4415	* @param pvHeap Ring 3 heap pointer.
4416	* @param cbHeap Size of the heap.
4417	* @thread EMT.
4418	*/
4419	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4420
4421	/**
4422	* Registers the firmware (BIOS, EFI) device with PDM.
4423	*
4424	* The firmware provides a callback table and gets a special PDM helper table.
4425	* There can only be one firmware device for a VM.
4426	*
4427	* @returns VBox status code.
4428	* @param pDevIns The device instance.
4429	* @param pFwReg Firmware registration structure.
4430	* @param ppFwHlp Where to return the firmware helper structure.
4431	* @remarks Only valid during device construction.
4432	* @thread EMT(0)
4433	*/
4434	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4435
4436	/**
4437	* Resets the VM.
4438	*
4439	* @returns The appropriate VBox status code to pass around on reset.
4440	* @param pDevIns The device instance.
4441	* @param fFlags PDMVMRESET_F_XXX flags.
4442	* @thread The emulation thread.
4443	*/
4444	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4445
4446	/**
4447	* Suspends the VM.
4448	*
4449	* @returns The appropriate VBox status code to pass around on suspend.
4450	* @param pDevIns The device instance.
4451	* @thread The emulation thread.
4452	*/
4453	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4454
4455	/**
4456	* Suspends, saves and powers off the VM.
4457	*
4458	* @returns The appropriate VBox status code to pass around.
4459	* @param pDevIns The device instance.
4460	* @thread An emulation thread.
4461	*/
4462	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4463
4464	/**
4465	* Power off the VM.
4466	*
4467	* @returns The appropriate VBox status code to pass around on power off.
4468	* @param pDevIns The device instance.
4469	* @thread The emulation thread.
4470	*/
4471	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4472
4473	/**
4474	* Checks if the Gate A20 is enabled or not.
4475	*
4476	* @returns true if A20 is enabled.
4477	* @returns false if A20 is disabled.
4478	* @param pDevIns The device instance.
4479	* @thread The emulation thread.
4480	*/
4481	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4482
4483	/**
4484	* Enables or disables the Gate A20.
4485	*
4486	* @param pDevIns The device instance.
4487	* @param fEnable Set this flag to enable the Gate A20; clear it
4488	* to disable.
4489	* @thread The emulation thread.
4490	*/
4491	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4492
4493	/**
4494	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4495	* thread.
4496	*
4497	* @param pDevIns The device instance.
4498	* @param iLeaf The CPUID leaf to get.
4499	* @param pEax Where to store the EAX value.
4500	* @param pEbx Where to store the EBX value.
4501	* @param pEcx Where to store the ECX value.
4502	* @param pEdx Where to store the EDX value.
4503	* @thread EMT.
4504	*/
4505	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4506
4507	/**
4508	* Get the current virtual clock time in a VM. The clock frequency must be
4509	* queried separately.
4510	*
4511	* @returns Current clock time.
4512	* @param pDevIns The device instance.
4513	*/
4514	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4515
4516	/**
4517	* Get the frequency of the virtual clock.
4518	*
4519	* @returns The clock frequency (not variable at run-time).
4520	* @param pDevIns The device instance.
4521	*/
4522	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4523
4524	/**
4525	* Get the current virtual clock time in a VM, in nanoseconds.
4526	*
4527	* @returns Current clock time (in ns).
4528	* @param pDevIns The device instance.
4529	*/
4530	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4531
4532	/**
4533	* Gets the support driver session.
4534	*
4535	* This is intended for working with the semaphore API.
4536	*
4537	* @returns Support driver session handle.
4538	* @param pDevIns The device instance.
4539	*/
4540	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4541
4542	/**
4543	* Queries a generic object from the VMM user.
4544	*
4545	* @returns Pointer to the object if found, NULL if not.
4546	* @param pDevIns The device instance.
4547	* @param pUuid The UUID of what's being queried. The UUIDs and
4548	* the usage conventions are defined by the user.
4549	*
4550	* @note It is strictly forbidden to call this internally in VBox! This
4551	* interface is exclusively for hacks in externally developed devices.
4552	*/
4553	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4554
4555	/**
4556	* Register a physical page access handler type.
4557	*
4558	* @returns VBox status code.
4559	* @param pDevIns The device instance.
4560	* @param enmKind The kind of access handler.
4561	* @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4562	* @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4563	* handler should be called.
4564	* @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4565	* ring-3 handler should be called.
4566	* @param pszHandlerRC The name of the raw-mode context handler, NULL if
4567	* the ring-3 handler should be called.
4568	* @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4569	* if the ring-3 handler should be called.
4570	* @param pszDesc The type description.
4571	* @param phType Where to return the type handle (cross context
4572	* safe).
4573	*/
4574	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4575	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4576	const char pszHandlerR0, const char pszPfHandlerR0,
4577	const char pszHandlerRC, const char pszPfHandlerRC,
4578	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4579
4580	/** @} */
4581
4582	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4583	uint32_t u32TheEnd;
4584	} PDMDEVHLPR3;
4585	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4586	/** Pointer to the R3 PDM Device API. */
4587	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4588	/** Pointer to the R3 PDM Device API, const variant. */
4589	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4590
4591
4592	/**
4593	* PDM Device API - RC Variant.
4594	*/
4595	typedef struct PDMDEVHLPRC
4596	{
4597	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4598	uint32_t u32Version;
4599
4600	/**
4601	* Sets up raw-mode context callback handlers for an I/O port range.
4602	*
4603	* The range must have been registered in ring-3 first using
4604	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4605	*
4606	* @returns VBox status.
4607	* @param pDevIns The device instance to register the ports with.
4608	* @param hIoPorts The I/O port range handle.
4609	* @param pfnOut Pointer to function which is gonna handle OUT
4610	* operations. Optional.
4611	* @param pfnIn Pointer to function which is gonna handle IN operations.
4612	* Optional.
4613	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4614	* operations. Optional.
4615	* @param pfnInStr Pointer to function which is gonna handle string IN
4616	* operations. Optional.
4617	* @param pvUser User argument to pass to the callbacks.
4618	*
4619	* @remarks Caller enters the device critical section prior to invoking the
4620	* registered callback methods.
4621	*
4622	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4623	* PDMDevHlpIoPortUnmap.
4624	*/
4625	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4626	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4627	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4628	void *pvUser));
4629
4630	/**
4631	* Sets up raw-mode context callback handlers for an MMIO region.
4632	*
4633	* The region must have been registered in ring-3 first using
4634	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4635	*
4636	* @returns VBox status.
4637	* @param pDevIns The device instance to register the ports with.
4638	* @param hRegion The MMIO region handle.
4639	* @param pfnWrite Pointer to function which is gonna handle Write
4640	* operations.
4641	* @param pfnRead Pointer to function which is gonna handle Read
4642	* operations.
4643	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4644	* operations. (optional)
4645	* @param pvUser User argument to pass to the callbacks.
4646	*
4647	* @remarks Caller enters the device critical section prior to invoking the
4648	* registered callback methods.
4649	*
4650	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4651	* PDMDevHlpMmioUnmap.
4652	*/
4653	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4654	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4655
4656	/**
4657	* Sets up a raw-mode mapping for an MMIO2 region.
4658	*
4659	* The region must have been created in ring-3 first using
4660	* PDMDevHlpMmio2Create().
4661	*
4662	* @returns VBox status.
4663	* @param pDevIns The device instance to register the ports with.
4664	* @param hRegion The MMIO2 region handle.
4665	* @param offSub Start of what to map into raw-mode. Must be page aligned.
4666	* @param cbSub Number of bytes to map into raw-mode. Must be page
4667	* aligned. Zero is an alias for everything.
4668	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4669	* @thread EMT(0)
4670	* @note Only available at VM creation time.
4671	*
4672	* @sa PDMDevHlpMmio2Create().
4673	*/
4674	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4675	size_t offSub, size_t cbSub, void **ppvMapping));
4676
4677	/**
4678	* Bus master physical memory read from the given PCI device.
4679	*
4680	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4681	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4682	* @param pDevIns The device instance.
4683	* @param pPciDev The PCI device structure. If NULL the default
4684	* PCI device for this device instance is used.
4685	* @param GCPhys Physical address start reading from.
4686	* @param pvBuf Where to put the read bits.
4687	* @param cbRead How many bytes to read.
4688	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4689	* @thread Any thread, but the call may involve the emulation thread.
4690	*/
4691	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4692	void *pvBuf, size_t cbRead, uint32_t fFlags));
4693
4694	/**
4695	* Bus master physical memory write from the given PCI device.
4696	*
4697	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4698	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4699	* @param pDevIns The device instance.
4700	* @param pPciDev The PCI device structure. If NULL the default
4701	* PCI device for this device instance is used.
4702	* @param GCPhys Physical address to write to.
4703	* @param pvBuf What to write.
4704	* @param cbWrite How many bytes to write.
4705	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4706	* @thread Any thread, but the call may involve the emulation thread.
4707	*/
4708	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4709	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4710
4711	/**
4712	* Set the IRQ for the given PCI device.
4713	*
4714	* @param pDevIns Device instance.
4715	* @param pPciDev The PCI device structure. If NULL the default
4716	* PCI device for this device instance is used.
4717	* @param iIrq IRQ number to set.
4718	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4719	* @thread Any thread, but will involve the emulation thread.
4720	*/
4721	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4722
4723	/**
4724	* Set ISA IRQ for a device.
4725	*
4726	* @param pDevIns Device instance.
4727	* @param iIrq IRQ number to set.
4728	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4729	* @thread Any thread, but will involve the emulation thread.
4730	*/
4731	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4732
4733	/**
4734	* Read physical memory.
4735	*
4736	* @returns VINF_SUCCESS (for now).
4737	* @param pDevIns Device instance.
4738	* @param GCPhys Physical address start reading from.
4739	* @param pvBuf Where to put the read bits.
4740	* @param cbRead How many bytes to read.
4741	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4742	*/
4743	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
4744
4745	/**
4746	* Write to physical memory.
4747	*
4748	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4749	* @param pDevIns Device instance.
4750	* @param GCPhys Physical address to write to.
4751	* @param pvBuf What to write.
4752	* @param cbWrite How many bytes to write.
4753	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4754	*/
4755	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4756
4757	/**
4758	* Checks if the Gate A20 is enabled or not.
4759	*
4760	* @returns true if A20 is enabled.
4761	* @returns false if A20 is disabled.
4762	* @param pDevIns Device instance.
4763	* @thread The emulation thread.
4764	*/
4765	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4766
4767	/**
4768	* Gets the VM state.
4769	*
4770	* @returns VM state.
4771	* @param pDevIns The device instance.
4772	* @thread Any thread (just keep in mind that it's volatile info).
4773	*/
4774	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4775
4776	/**
4777	* Set the VM error message
4778	*
4779	* @returns rc.
4780	* @param pDevIns Driver instance.
4781	* @param rc VBox status code.
4782	* @param SRC_POS Use RT_SRC_POS.
4783	* @param pszFormat Error message format string.
4784	* @param ... Error message arguments.
4785	*/
4786	DECLRCCALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4787	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4788
4789	/**
4790	* Set the VM error message
4791	*
4792	* @returns rc.
4793	* @param pDevIns Driver instance.
4794	* @param rc VBox status code.
4795	* @param SRC_POS Use RT_SRC_POS.
4796	* @param pszFormat Error message format string.
4797	* @param va Error message arguments.
4798	*/
4799	DECLRCCALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4800	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4801
4802	/**
4803	* Set the VM runtime error message
4804	*
4805	* @returns VBox status code.
4806	* @param pDevIns Device instance.
4807	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4808	* @param pszErrorId Error ID string.
4809	* @param pszFormat Error message format string.
4810	* @param ... Error message arguments.
4811	*/
4812	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4813	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4814
4815	/**
4816	* Set the VM runtime error message
4817	*
4818	* @returns VBox status code.
4819	* @param pDevIns Device instance.
4820	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4821	* @param pszErrorId Error ID string.
4822	* @param pszFormat Error message format string.
4823	* @param va Error message arguments.
4824	*/
4825	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4826	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
4827
4828	/**
4829	* Gets the VM handle. Restricted API.
4830	*
4831	* @returns VM Handle.
4832	* @param pDevIns Device instance.
4833	*/
4834	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4835
4836	/**
4837	* Gets the VMCPU handle. Restricted API.
4838	*
4839	* @returns VMCPU Handle.
4840	* @param pDevIns The device instance.
4841	*/
4842	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4843
4844	/**
4845	* The the VM CPU ID of the current thread (restricted API).
4846	*
4847	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4848	* @param pDevIns The device instance.
4849	*/
4850	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4851
4852	/**
4853	* Get the current virtual clock time in a VM. The clock frequency must be
4854	* queried separately.
4855	*
4856	* @returns Current clock time.
4857	* @param pDevIns The device instance.
4858	*/
4859	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4860
4861	/**
4862	* Get the frequency of the virtual clock.
4863	*
4864	* @returns The clock frequency (not variable at run-time).
4865	* @param pDevIns The device instance.
4866	*/
4867	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4868
4869	/**
4870	* Get the current virtual clock time in a VM, in nanoseconds.
4871	*
4872	* @returns Current clock time (in ns).
4873	* @param pDevIns The device instance.
4874	*/
4875	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4876
4877	/**
4878	* Gets the NOP critical section.
4879	*
4880	* @returns The ring-3 address of the NOP critical section.
4881	* @param pDevIns The device instance.
4882	*/
4883	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4884
4885	/**
4886	* Changes the device level critical section from the automatically created
4887	* default to one desired by the device constructor.
4888	*
4889	* Must first be done in ring-3.
4890	*
4891	* @returns VBox status code.
4892	* @param pDevIns The device instance.
4893	* @param pCritSect The critical section to use. NULL is not
4894	* valid, instead use the NOP critical
4895	* section.
4896	*/
4897	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4898
4899	/** @name Exported PDM Critical Section Functions
4900	* @{ */
4901	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4902	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4903	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4904	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4905	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4906	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4907	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4908	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4909	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4910	/** @} */
4911
4912	/**
4913	* Gets the trace buffer handle.
4914	*
4915	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4916	* really inteded for direct usage, thus no inline wrapper function.
4917	*
4918	* @returns Trace buffer handle or NIL_RTTRACEBUF.
4919	* @param pDevIns The device instance.
4920	*/
4921	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4922
4923	/**
4924	* Sets up the PCI bus for the raw-mode context.
4925	*
4926	* This must be called after ring-3 has registered the PCI bus using
4927	* PDMDevHlpPCIBusRegister().
4928	*
4929	* @returns VBox status code.
4930	* @param pDevIns The device instance.
4931	* @param pPciBusReg The PCI bus registration information for raw-mode,
4932	* considered volatile.
4933	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4934	*/
4935	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4936
4937	/**
4938	* Sets up the IOMMU for the raw-mode context.
4939	*
4940	* This must be called after ring-3 has registered the IOMMU using
4941	* PDMDevHlpIommuRegister().
4942	*
4943	* @returns VBox status code.
4944	* @param pDevIns The device instance.
4945	* @param pIommuReg The IOMMU registration information for raw-mode,
4946	* considered volatile.
4947	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
4948	*/
4949	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
4950
4951	/**
4952	* Sets up the PIC for the ring-0 context.
4953	*
4954	* This must be called after ring-3 has registered the PIC using
4955	* PDMDevHlpPICRegister().
4956	*
4957	* @returns VBox status code.
4958	* @param pDevIns The device instance.
4959	* @param pPicReg The PIC registration information for ring-0,
4960	* considered volatile and copied.
4961	* @param ppPicHlp Where to return the ring-0 PIC helpers.
4962	*/
4963	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4964
4965	/**
4966	* Sets up the APIC for the raw-mode context.
4967	*
4968	* This must be called after ring-3 has registered the APIC using
4969	* PDMDevHlpApicRegister().
4970	*
4971	* @returns VBox status code.
4972	* @param pDevIns The device instance.
4973	*/
4974	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
4975
4976	/**
4977	* Sets up the IOAPIC for the ring-0 context.
4978	*
4979	* This must be called after ring-3 has registered the PIC using
4980	* PDMDevHlpIoApicRegister().
4981	*
4982	* @returns VBox status code.
4983	* @param pDevIns The device instance.
4984	* @param pIoApicReg The PIC registration information for ring-0,
4985	* considered volatile and copied.
4986	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
4987	*/
4988	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4989
4990	/**
4991	* Sets up the HPET for the raw-mode context.
4992	*
4993	* This must be called after ring-3 has registered the PIC using
4994	* PDMDevHlpHpetRegister().
4995	*
4996	* @returns VBox status code.
4997	* @param pDevIns The device instance.
4998	* @param pHpetReg The PIC registration information for raw-mode,
4999	* considered volatile and copied.
5000	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
5001	*/
5002	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
5003
5004	/** Space reserved for future members.
5005	* @{ */
5006	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
5007	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
5008	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
5009	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
5010	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
5011	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
5012	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
5013	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
5014	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
5015	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
5016	/** @} */
5017
5018	/** Just a safety precaution. */
5019	uint32_t u32TheEnd;
5020	} PDMDEVHLPRC;
5021	/** Pointer PDM Device RC API. */
5022	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
5023	/** Pointer PDM Device RC API. */
5024	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
5025
5026	/** Current PDMDEVHLP version number. */
5027	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 16, 0)
5028
5029
5030	/**
5031	* PDM Device API - R0 Variant.
5032	*/
5033	typedef struct PDMDEVHLPR0
5034	{
5035	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5036	uint32_t u32Version;
5037
5038	/**
5039	* Sets up ring-0 callback handlers for an I/O port range.
5040	*
5041	* The range must have been created in ring-3 first using
5042	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5043	*
5044	* @returns VBox status.
5045	* @param pDevIns The device instance to register the ports with.
5046	* @param hIoPorts The I/O port range handle.
5047	* @param pfnOut Pointer to function which is gonna handle OUT
5048	* operations. Optional.
5049	* @param pfnIn Pointer to function which is gonna handle IN operations.
5050	* Optional.
5051	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5052	* operations. Optional.
5053	* @param pfnInStr Pointer to function which is gonna handle string IN
5054	* operations. Optional.
5055	* @param pvUser User argument to pass to the callbacks.
5056	*
5057	* @remarks Caller enters the device critical section prior to invoking the
5058	* registered callback methods.
5059	*
5060	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5061	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5062	*/
5063	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5064	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5065	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5066	void *pvUser));
5067
5068	/**
5069	* Sets up ring-0 callback handlers for an MMIO region.
5070	*
5071	* The region must have been created in ring-3 first using
5072	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5073	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5074	*
5075	* @returns VBox status.
5076	* @param pDevIns The device instance to register the ports with.
5077	* @param hRegion The MMIO region handle.
5078	* @param pfnWrite Pointer to function which is gonna handle Write
5079	* operations.
5080	* @param pfnRead Pointer to function which is gonna handle Read
5081	* operations.
5082	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5083	* operations. (optional)
5084	* @param pvUser User argument to pass to the callbacks.
5085	*
5086	* @remarks Caller enters the device critical section prior to invoking the
5087	* registered callback methods.
5088	*
5089	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5090	* PDMDevHlpMmioUnmap().
5091	*/
5092	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5093	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5094
5095	/**
5096	* Sets up a ring-0 mapping for an MMIO2 region.
5097	*
5098	* The region must have been created in ring-3 first using
5099	* PDMDevHlpMmio2Create().
5100	*
5101	* @returns VBox status.
5102	* @param pDevIns The device instance to register the ports with.
5103	* @param hRegion The MMIO2 region handle.
5104	* @param offSub Start of what to map into ring-0. Must be page aligned.
5105	* @param cbSub Number of bytes to map into ring-0. Must be page
5106	* aligned. Zero is an alias for everything.
5107	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5108	*
5109	* @thread EMT(0)
5110	* @note Only available at VM creation time.
5111	*
5112	* @sa PDMDevHlpMmio2Create().
5113	*/
5114	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5115	void **ppvMapping));
5116
5117	/**
5118	* Bus master physical memory read from the given PCI device.
5119	*
5120	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5121	* VERR_EM_MEMORY.
5122	* @param pDevIns The device instance.
5123	* @param pPciDev The PCI device structure. If NULL the default
5124	* PCI device for this device instance is used.
5125	* @param GCPhys Physical address start reading from.
5126	* @param pvBuf Where to put the read bits.
5127	* @param cbRead How many bytes to read.
5128	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5129	* @thread Any thread, but the call may involve the emulation thread.
5130	*/
5131	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5132	void *pvBuf, size_t cbRead, uint32_t fFlags));
5133
5134	/**
5135	* Bus master physical memory write from the given PCI device.
5136	*
5137	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5138	* VERR_EM_MEMORY.
5139	* @param pDevIns The device instance.
5140	* @param pPciDev The PCI device structure. If NULL the default
5141	* PCI device for this device instance is used.
5142	* @param GCPhys Physical address to write to.
5143	* @param pvBuf What to write.
5144	* @param cbWrite How many bytes to write.
5145	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5146	* @thread Any thread, but the call may involve the emulation thread.
5147	*/
5148	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5149	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5150
5151	/**
5152	* Set the IRQ for the given PCI device.
5153	*
5154	* @param pDevIns Device instance.
5155	* @param pPciDev The PCI device structure. If NULL the default
5156	* PCI device for this device instance is used.
5157	* @param iIrq IRQ number to set.
5158	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5159	* @thread Any thread, but will involve the emulation thread.
5160	*/
5161	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5162
5163	/**
5164	* Set ISA IRQ for a device.
5165	*
5166	* @param pDevIns Device instance.
5167	* @param iIrq IRQ number to set.
5168	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5169	* @thread Any thread, but will involve the emulation thread.
5170	*/
5171	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5172
5173	/**
5174	* Read physical memory.
5175	*
5176	* @returns VINF_SUCCESS (for now).
5177	* @param pDevIns Device instance.
5178	* @param GCPhys Physical address start reading from.
5179	* @param pvBuf Where to put the read bits.
5180	* @param cbRead How many bytes to read.
5181	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5182	*/
5183	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5184
5185	/**
5186	* Write to physical memory.
5187	*
5188	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5189	* @param pDevIns Device instance.
5190	* @param GCPhys Physical address to write to.
5191	* @param pvBuf What to write.
5192	* @param cbWrite How many bytes to write.
5193	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5194	*/
5195	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5196
5197	/**
5198	* Checks if the Gate A20 is enabled or not.
5199	*
5200	* @returns true if A20 is enabled.
5201	* @returns false if A20 is disabled.
5202	* @param pDevIns Device instance.
5203	* @thread The emulation thread.
5204	*/
5205	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5206
5207	/**
5208	* Gets the VM state.
5209	*
5210	* @returns VM state.
5211	* @param pDevIns The device instance.
5212	* @thread Any thread (just keep in mind that it's volatile info).
5213	*/
5214	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5215
5216	/**
5217	* Set the VM error message
5218	*
5219	* @returns rc.
5220	* @param pDevIns Driver instance.
5221	* @param rc VBox status code.
5222	* @param SRC_POS Use RT_SRC_POS.
5223	* @param pszFormat Error message format string.
5224	* @param ... Error message arguments.
5225	*/
5226	DECLR0CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5227	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
5228
5229	/**
5230	* Set the VM error message
5231	*
5232	* @returns rc.
5233	* @param pDevIns Driver instance.
5234	* @param rc VBox status code.
5235	* @param SRC_POS Use RT_SRC_POS.
5236	* @param pszFormat Error message format string.
5237	* @param va Error message arguments.
5238	*/
5239	DECLR0CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5240	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
5241
5242	/**
5243	* Set the VM runtime error message
5244	*
5245	* @returns VBox status code.
5246	* @param pDevIns Device instance.
5247	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5248	* @param pszErrorId Error ID string.
5249	* @param pszFormat Error message format string.
5250	* @param ... Error message arguments.
5251	*/
5252	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5253	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
5254
5255	/**
5256	* Set the VM runtime error message
5257	*
5258	* @returns VBox status code.
5259	* @param pDevIns Device instance.
5260	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5261	* @param pszErrorId Error ID string.
5262	* @param pszFormat Error message format string.
5263	* @param va Error message arguments.
5264	*/
5265	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5266	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
5267
5268	/**
5269	* Gets the VM handle. Restricted API.
5270	*
5271	* @returns VM Handle.
5272	* @param pDevIns Device instance.
5273	*/
5274	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5275
5276	/**
5277	* Gets the VMCPU handle. Restricted API.
5278	*
5279	* @returns VMCPU Handle.
5280	* @param pDevIns The device instance.
5281	*/
5282	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5283
5284	/**
5285	* The the VM CPU ID of the current thread (restricted API).
5286	*
5287	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5288	* @param pDevIns The device instance.
5289	*/
5290	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5291
5292	/** @name Timer handle method wrappers
5293	* @{ */
5294	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5295	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5296	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5297	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5298	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5299	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5300	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5301	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5302	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5303	/** Takes the clock lock then enters the specified critical section. */
5304	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5305	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5306	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5307	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5308	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5309	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5310	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5311	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5312	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5313	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5314	/** @} */
5315
5316	/**
5317	* Get the current virtual clock time in a VM. The clock frequency must be
5318	* queried separately.
5319	*
5320	* @returns Current clock time.
5321	* @param pDevIns The device instance.
5322	*/
5323	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5324
5325	/**
5326	* Get the frequency of the virtual clock.
5327	*
5328	* @returns The clock frequency (not variable at run-time).
5329	* @param pDevIns The device instance.
5330	*/
5331	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5332
5333	/**
5334	* Get the current virtual clock time in a VM, in nanoseconds.
5335	*
5336	* @returns Current clock time (in ns).
5337	* @param pDevIns The device instance.
5338	*/
5339	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5340
5341	/** @name Exported PDM Queue Functions
5342	* @{ */
5343	DECLR0CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5344	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5345	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5346	DECLR0CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
5347	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5348	/** @} */
5349
5350	/** @name PDM Task
5351	* @{ */
5352	/**
5353	* Triggers the running the given task.
5354	*
5355	* @returns VBox status code.
5356	* @retval VINF_ALREADY_POSTED is the task is already pending.
5357	* @param pDevIns The device instance.
5358	* @param hTask The task to trigger.
5359	* @thread Any thread.
5360	*/
5361	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5362	/** @} */
5363
5364	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5365	* These semaphores can be signalled from ring-0.
5366	* @{ */
5367	/** @sa SUPSemEventSignal */
5368	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5369	/** @sa SUPSemEventWaitNoResume */
5370	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5371	/** @sa SUPSemEventWaitNsAbsIntr */
5372	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5373	/** @sa SUPSemEventWaitNsRelIntr */
5374	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5375	/** @sa SUPSemEventGetResolution */
5376	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5377	/** @} */
5378
5379	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5380	* These semaphores can be signalled from ring-0.
5381	* @{ */
5382	/** @sa SUPSemEventMultiSignal */
5383	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5384	/** @sa SUPSemEventMultiReset */
5385	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5386	/** @sa SUPSemEventMultiWaitNoResume */
5387	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5388	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5389	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5390	/** @sa SUPSemEventMultiWaitNsRelIntr */
5391	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5392	/** @sa SUPSemEventMultiGetResolution */
5393	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5394	/** @} */
5395
5396	/**
5397	* Gets the NOP critical section.
5398	*
5399	* @returns The ring-3 address of the NOP critical section.
5400	* @param pDevIns The device instance.
5401	*/
5402	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5403
5404	/**
5405	* Changes the device level critical section from the automatically created
5406	* default to one desired by the device constructor.
5407	*
5408	* Must first be done in ring-3.
5409	*
5410	* @returns VBox status code.
5411	* @param pDevIns The device instance.
5412	* @param pCritSect The critical section to use. NULL is not
5413	* valid, instead use the NOP critical
5414	* section.
5415	*/
5416	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5417
5418	/** @name Exported PDM Critical Section Functions
5419	* @{ */
5420	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5421	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5422	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5423	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5424	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5425	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5426	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5427	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5428	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5429	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5430	/** @} */
5431
5432	/**
5433	* Gets the trace buffer handle.
5434	*
5435	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5436	* really inteded for direct usage, thus no inline wrapper function.
5437	*
5438	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5439	* @param pDevIns The device instance.
5440	*/
5441	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5442
5443	/**
5444	* Sets up the PCI bus for the ring-0 context.
5445	*
5446	* This must be called after ring-3 has registered the PCI bus using
5447	* PDMDevHlpPCIBusRegister().
5448	*
5449	* @returns VBox status code.
5450	* @param pDevIns The device instance.
5451	* @param pPciBusReg The PCI bus registration information for ring-0,
5452	* considered volatile and copied.
5453	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5454	*/
5455	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5456
5457	/**
5458	* Sets up the IOMMU for the ring-0 context.
5459	*
5460	* This must be called after ring-3 has registered the IOMMU using
5461	* PDMDevHlpIommuRegister().
5462	*
5463	* @returns VBox status code.
5464	* @param pDevIns The device instance.
5465	* @param pIommuReg The IOMMU registration information for ring-0,
5466	* considered volatile and copied.
5467	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5468	*/
5469	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5470
5471	/**
5472	* Sets up the PIC for the ring-0 context.
5473	*
5474	* This must be called after ring-3 has registered the PIC using
5475	* PDMDevHlpPICRegister().
5476	*
5477	* @returns VBox status code.
5478	* @param pDevIns The device instance.
5479	* @param pPicReg The PIC registration information for ring-0,
5480	* considered volatile and copied.
5481	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5482	*/
5483	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5484
5485	/**
5486	* Sets up the APIC for the ring-0 context.
5487	*
5488	* This must be called after ring-3 has registered the APIC using
5489	* PDMDevHlpApicRegister().
5490	*
5491	* @returns VBox status code.
5492	* @param pDevIns The device instance.
5493	*/
5494	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5495
5496	/**
5497	* Sets up the IOAPIC for the ring-0 context.
5498	*
5499	* This must be called after ring-3 has registered the PIC using
5500	* PDMDevHlpIoApicRegister().
5501	*
5502	* @returns VBox status code.
5503	* @param pDevIns The device instance.
5504	* @param pIoApicReg The PIC registration information for ring-0,
5505	* considered volatile and copied.
5506	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5507	*/
5508	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5509
5510	/**
5511	* Sets up the HPET for the ring-0 context.
5512	*
5513	* This must be called after ring-3 has registered the PIC using
5514	* PDMDevHlpHpetRegister().
5515	*
5516	* @returns VBox status code.
5517	* @param pDevIns The device instance.
5518	* @param pHpetReg The PIC registration information for ring-0,
5519	* considered volatile and copied.
5520	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5521	*/
5522	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5523
5524	/** Space reserved for future members.
5525	* @{ */
5526	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5527	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5528	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5529	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5530	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5531	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5532	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5533	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5534	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5535	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5536	/** @} */
5537
5538	/** Just a safety precaution. */
5539	uint32_t u32TheEnd;
5540	} PDMDEVHLPR0;
5541	/** Pointer PDM Device R0 API. */
5542	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5543	/** Pointer PDM Device GC API. */
5544	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5545
5546	/** Current PDMDEVHLP version number. */
5547	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 19, 0)
5548
5549
5550	/**
5551	* PDM Device Instance.
5552	*/
5553	typedef struct PDMDEVINSR3
5554	{
5555	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5556	uint32_t u32Version;
5557	/** Device instance number. */
5558	uint32_t iInstance;
5559	/** Size of the ring-3, raw-mode and shared bits. */
5560	uint32_t cbRing3;
5561	/** Set if ring-0 context is enabled. */
5562	bool fR0Enabled;
5563	/** Set if raw-mode context is enabled. */
5564	bool fRCEnabled;
5565	/** Alignment padding. */
5566	bool afReserved[2];
5567	/** Pointer the HC PDM Device API. */
5568	PCPDMDEVHLPR3 pHlpR3;
5569	/** Pointer to the shared device instance data. */
5570	RTR3PTR pvInstanceDataR3;
5571	/** Pointer to the device instance data for ring-3. */
5572	RTR3PTR pvInstanceDataForR3;
5573	/** The critical section for the device.
5574	*
5575	* TM and IOM will enter this critical section before calling into the device
5576	* code. PDM will when doing power on, power off, reset, suspend and resume
5577	* notifications. SSM will currently not, but this will be changed later on.
5578	*
5579	* The device gets a critical section automatically assigned to it before
5580	* the constructor is called. If the constructor wishes to use a different
5581	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5582	* very early on.
5583	*/
5584	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5585	/** Pointer to device registration structure. */
5586	R3PTRTYPE(PCPDMDEVREG) pReg;
5587	/** Configuration handle. */
5588	R3PTRTYPE(PCFGMNODE) pCfg;
5589	/** The base interface of the device.
5590	*
5591	* The device constructor initializes this if it has any
5592	* device level interfaces to export. To obtain this interface
5593	* call PDMR3QueryDevice(). */
5594	PDMIBASE IBase;
5595
5596	/** Tracing indicator. */
5597	uint32_t fTracing;
5598	/** The tracing ID of this device. */
5599	uint32_t idTracing;
5600
5601	/** Ring-3 pointer to the raw-mode device instance. */
5602	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5603	/** Raw-mode address of the raw-mode device instance. */
5604	RTRGPTR pDevInsForRC;
5605	/** Ring-3 pointer to the raw-mode instance data. */
5606	RTR3PTR pvInstanceDataForRCR3;
5607
5608	/** PCI device structure size. */
5609	uint32_t cbPciDev;
5610	/** Number of PCI devices in apPciDevs. */
5611	uint32_t cPciDevs;
5612	/** Pointer to the PCI devices for this device.
5613	* (Allocated after the shared instance data.)
5614	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5615	* two devices ever needing it can use cbPciDev and do the address
5616	* calculations that for entries 8+. */
5617	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5618
5619	/** Temporarily. */
5620	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5621	/** Temporarily. */
5622	RTR0PTR pvInstanceDataR0;
5623	/** Temporarily. */
5624	RTRCPTR pvInstanceDataRC;
5625	/** Align the internal data more naturally. */
5626	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5627
5628	/** Internal data. */
5629	union
5630	{
5631	#ifdef PDMDEVINSINT_DECLARED
5632	PDMDEVINSINTR3 s;
5633	#endif
5634	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
5635	} Internal;
5636
5637	/** Device instance data for ring-3. The size of this area is defined
5638	* in the PDMDEVREG::cbInstanceR3 field. */
5639	char achInstanceData[8];
5640	} PDMDEVINSR3;
5641
5642	/** Current PDMDEVINSR3 version number. */
5643	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5644
5645	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5646	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5647
5648
5649	/**
5650	* PDM ring-0 device instance.
5651	*/
5652	typedef struct PDMDEVINSR0
5653	{
5654	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5655	uint32_t u32Version;
5656	/** Device instance number. */
5657	uint32_t iInstance;
5658
5659	/** Pointer the HC PDM Device API. */
5660	PCPDMDEVHLPR0 pHlpR0;
5661	/** Pointer to the shared device instance data. */
5662	RTR0PTR pvInstanceDataR0;
5663	/** Pointer to the device instance data for ring-0. */
5664	RTR0PTR pvInstanceDataForR0;
5665	/** The critical section for the device.
5666	*
5667	* TM and IOM will enter this critical section before calling into the device
5668	* code. PDM will when doing power on, power off, reset, suspend and resume
5669	* notifications. SSM will currently not, but this will be changed later on.
5670	*
5671	* The device gets a critical section automatically assigned to it before
5672	* the constructor is called. If the constructor wishes to use a different
5673	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5674	* very early on.
5675	*/
5676	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5677	/** Pointer to the ring-0 device registration structure. */
5678	R0PTRTYPE(PCPDMDEVREGR0) pReg;
5679	/** Ring-3 address of the ring-3 device instance. */
5680	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5681	/** Ring-0 pointer to the ring-3 device instance. */
5682	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5683	/** Ring-0 pointer to the ring-3 instance data. */
5684	RTR0PTR pvInstanceDataForR3R0;
5685	/** Raw-mode address of the raw-mode device instance. */
5686	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5687	/** Ring-0 pointer to the raw-mode device instance. */
5688	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5689	/** Ring-0 pointer to the raw-mode instance data. */
5690	RTR0PTR pvInstanceDataForRCR0;
5691
5692	/** PCI device structure size. */
5693	uint32_t cbPciDev;
5694	/** Number of PCI devices in apPciDevs. */
5695	uint32_t cPciDevs;
5696	/** Pointer to the PCI devices for this device.
5697	* (Allocated after the shared instance data.)
5698	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5699	* two devices ever needing it can use cbPciDev and do the address
5700	* calculations that for entries 8+. */
5701	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5702
5703	/** Align the internal data more naturally. */
5704	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5705
5706	/** Internal data. */
5707	union
5708	{
5709	#ifdef PDMDEVINSINT_DECLARED
5710	PDMDEVINSINTR0 s;
5711	#endif
5712	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
5713	} Internal;
5714
5715	/** Device instance data for ring-0. The size of this area is defined
5716	* in the PDMDEVREG::cbInstanceR0 field. */
5717	char achInstanceData[8];
5718	} PDMDEVINSR0;
5719
5720	/** Current PDMDEVINSR0 version number. */
5721	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5722
5723
5724	/**
5725	* PDM raw-mode device instance.
5726	*/
5727	typedef struct PDMDEVINSRC
5728	{
5729	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5730	uint32_t u32Version;
5731	/** Device instance number. */
5732	uint32_t iInstance;
5733
5734	/** Pointer the HC PDM Device API. */
5735	PCPDMDEVHLPRC pHlpRC;
5736	/** Pointer to the shared device instance data. */
5737	RTRGPTR pvInstanceDataRC;
5738	/** Pointer to the device instance data for raw-mode. */
5739	RTRGPTR pvInstanceDataForRC;
5740	/** The critical section for the device.
5741	*
5742	* TM and IOM will enter this critical section before calling into the device
5743	* code. PDM will when doing power on, power off, reset, suspend and resume
5744	* notifications. SSM will currently not, but this will be changed later on.
5745	*
5746	* The device gets a critical section automatically assigned to it before
5747	* the constructor is called. If the constructor wishes to use a different
5748	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5749	* very early on.
5750	*/
5751	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5752	/** Pointer to the raw-mode device registration structure. */
5753	RGPTRTYPE(PCPDMDEVREGRC) pReg;
5754
5755	/** PCI device structure size. */
5756	uint32_t cbPciDev;
5757	/** Number of PCI devices in apPciDevs. */
5758	uint32_t cPciDevs;
5759	/** Pointer to the PCI devices for this device.
5760	* (Allocated after the shared instance data.) */
5761	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5762
5763	/** Align the internal data more naturally. */
5764	uint32_t au32Padding[14];
5765
5766	/** Internal data. */
5767	union
5768	{
5769	#ifdef PDMDEVINSINT_DECLARED
5770	PDMDEVINSINTRC s;
5771	#endif
5772	uint8_t padding[0x10];
5773	} Internal;
5774
5775	/** Device instance data for ring-0. The size of this area is defined
5776	* in the PDMDEVREG::cbInstanceR0 field. */
5777	char achInstanceData[8];
5778	} PDMDEVINSRC;
5779
5780	/** Current PDMDEVINSR0 version number. */
5781	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5782
5783
5784	/** @def PDM_DEVINS_VERSION
5785	* Current PDMDEVINS version number. */
5786	/** @typedef PDMDEVINS
5787	* The device instance structure for the current context. */
5788	#ifdef IN_RING3
5789	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5790	typedef PDMDEVINSR3 PDMDEVINS;
5791	#elif defined(IN_RING0)
5792	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5793	typedef PDMDEVINSR0 PDMDEVINS;
5794	#elif defined(IN_RC)
5795	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5796	typedef PDMDEVINSRC PDMDEVINS;
5797	#else
5798	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5799	#endif
5800
5801	/**
5802	* Get the pointer to an PCI device.
5803	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5804	*/
5805	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5806	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5807	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5808
5809	/**
5810	* Calc the pointer to of a given PCI device.
5811	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5812	*/
5813	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5814	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5815	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
5816	: (PPDMPCIDEV)NULL )
5817
5818
5819	/**
5820	* Checks the structure versions of the device instance and device helpers,
5821	* returning if they are incompatible.
5822	*
5823	* This is for use in the constructor.
5824	*
5825	* @param pDevIns The device instance pointer.
5826	*/
5827	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5828	do \
5829	{ \
5830	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5831	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5832	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5833	VERR_PDM_DEVINS_VERSION_MISMATCH); \
5834	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5835	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5836	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5837	} while (0)
5838
5839	/**
5840	* Quietly checks the structure versions of the device instance and device
5841	* helpers, returning if they are incompatible.
5842	*
5843	* This is for use in the destructor.
5844	*
5845	* @param pDevIns The device instance pointer.
5846	*/
5847	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5848	do \
5849	{ \
5850	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5851	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5852	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5853	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5854	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5855	} while (0)
5856
5857	/**
5858	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
5859	* constructor - returns on failure.
5860	*
5861	* This should be invoked after having initialized the instance data
5862	* sufficiently for the correct operation of the destructor. The destructor is
5863	* always called!
5864	*
5865	* @param pDevIns Pointer to the PDM device instance.
5866	* @param pszValidValues Patterns describing the valid value names. See
5867	* RTStrSimplePatternMultiMatch for details on the
5868	* pattern syntax.
5869	* @param pszValidNodes Patterns describing the valid node (key) names.
5870	* Pass empty string if no valid nodes.
5871	*/
5872	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5873	do \
5874	{ \
5875	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5876	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5877	if (RT_SUCCESS(rcValCfg)) \
5878	{ /* likely */ } else return rcValCfg; \
5879	} while (0)
5880
5881	/** @def PDMDEV_ASSERT_EMT
5882	* Assert that the current thread is the emulation thread.
5883	*/
5884	#ifdef VBOX_STRICT
5885	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5886	#else
5887	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5888	#endif
5889
5890	/** @def PDMDEV_ASSERT_OTHER
5891	* Assert that the current thread is NOT the emulation thread.
5892	*/
5893	#ifdef VBOX_STRICT
5894	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5895	#else
5896	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5897	#endif
5898
5899	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5900	* Assert that the current thread is owner of the VM lock.
5901	*/
5902	#ifdef VBOX_STRICT
5903	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5904	#else
5905	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5906	#endif
5907
5908	/** @def PDMDEV_SET_ERROR
5909	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5910	*/
5911	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5912	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5913
5914	/** @def PDMDEV_SET_RUNTIME_ERROR
5915	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5916	*/
5917	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5918	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5919
5920	/** @def PDMDEVINS_2_RCPTR
5921	* Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
5922	*/
5923	#ifdef IN_RC
5924	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5925	#else
5926	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5927	#endif
5928
5929	/** @def PDMDEVINS_2_R3PTR
5930	* Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
5931	*/
5932	#ifdef IN_RING3
5933	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5934	#else
5935	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5936	#endif
5937
5938	/** @def PDMDEVINS_2_R0PTR
5939	* Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
5940	*/
5941	#ifdef IN_RING0
5942	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5943	#else
5944	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5945	#endif
5946
5947	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5948	* Converts a PDM device instance data pointer to a ring-0 one.
5949	* @deprecated
5950	*/
5951	#ifdef IN_RING0
5952	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5953	#else
5954	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5955	#endif
5956
5957
5958	/** @def PDMDEVINS_2_DATA
5959	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
5960	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5961	*
5962	* @note Do no use this macro in common code working on a core structure which
5963	* device specific code has expanded.
5964	*/
5965	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5966	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5967	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5968	{ \
5969	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5970	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5971	return pLambdaRet; \
5972	}(a_pDevIns))
5973	#else
5974	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5975	#endif
5976
5977	/** @def PDMDEVINS_2_DATA_CC
5978	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5979	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5980	*
5981	* @note Do no use this macro in common code working on a core structure which
5982	* device specific code has expanded.
5983	*/
5984	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5985	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5986	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5987	{ \
5988	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5989	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5990	return pLambdaRet; \
5991	}(a_pDevIns))
5992	#else
5993	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5994	#endif
5995
5996
5997	#ifdef IN_RING3
5998
5999	/**
6000	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
6001	*/
6002	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6003	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
6004	PIOMIOPORTHANDLE phIoPorts)
6005	{
6006	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6007	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6008	if (RT_SUCCESS(rc))
6009	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6010	return rc;
6011	}
6012
6013	/**
6014	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
6015	*/
6016	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6017	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6018	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6019	{
6020	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6021	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6022	if (RT_SUCCESS(rc))
6023	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6024	return rc;
6025	}
6026
6027	/**
6028	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
6029	*/
6030	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6031	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6032	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6033	{
6034	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6035	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6036	if (RT_SUCCESS(rc))
6037	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6038	return rc;
6039	}
6040
6041	/**
6042	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
6043	*/
6044	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6045	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6046	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6047	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6048	{
6049	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6050	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6051	if (RT_SUCCESS(rc))
6052	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6053	return rc;
6054	}
6055
6056	/**
6057	* @sa PDMDevHlpIoPortCreateEx
6058	*/
6059	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6060	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6061	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6062	{
6063	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
6064	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6065	}
6066
6067
6068	/**
6069	* @sa PDMDevHlpIoPortCreateEx
6070	*/
6071	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6072	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6073	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6074	{
6075	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6076	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6077	}
6078
6079	/**
6080	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6081	*/
6082	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6083	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6084	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6085	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6086	{
6087	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6088	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6089	}
6090
6091	/**
6092	* @copydoc PDMDEVHLPR3::pfnIoPortMap
6093	*/
6094	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6095	{
6096	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6097	}
6098
6099	/**
6100	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6101	*/
6102	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6103	{
6104	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6105	}
6106
6107	/**
6108	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6109	*/
6110	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6111	{
6112	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6113	}
6114
6115
6116	#endif /* IN_RING3 */
6117	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6118
6119	/**
6120	* @sa PDMDevHlpIoPortSetUpContextEx
6121	*/
6122	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6123	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6124	{
6125	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6126	}
6127
6128	/**
6129	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6130	*/
6131	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6132	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6133	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6134	{
6135	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6136	}
6137
6138	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6139	#ifdef IN_RING3
6140
6141	/**
6142	* @sa PDMDevHlpMmioCreateEx
6143	*/
6144	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6145	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6146	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6147	{
6148	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6149	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6150	}
6151
6152	/**
6153	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6154	*/
6155	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6156	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6157	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6158	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6159	{
6160	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6161	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6162	}
6163
6164	/**
6165	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6166	*/
6167	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6168	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6169	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6170	{
6171	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6172	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6173	if (RT_SUCCESS(rc))
6174	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6175	return rc;
6176	}
6177
6178	/**
6179	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6180	*/
6181	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6182	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6183	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6184	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6185	{
6186	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6187	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6188	if (RT_SUCCESS(rc))
6189	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6190	return rc;
6191	}
6192
6193	/**
6194	* @copydoc PDMDEVHLPR3::pfnMmioMap
6195	*/
6196	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6197	{
6198	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6199	}
6200
6201	/**
6202	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6203	*/
6204	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6205	{
6206	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6207	}
6208
6209	/**
6210	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6211	*/
6212	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6213	{
6214	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6215	}
6216
6217	/**
6218	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6219	*/
6220	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6221	{
6222	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6223	}
6224
6225	#endif /* IN_RING3 */
6226	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6227
6228	/**
6229	* @sa PDMDevHlpMmioSetUpContextEx
6230	*/
6231	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6232	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6233	{
6234	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6235	}
6236
6237	/**
6238	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6239	*/
6240	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6241	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6242	{
6243	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6244	}
6245
6246	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6247	#ifdef IN_RING3
6248
6249	/**
6250	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6251	*/
6252	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6253	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6254	{
6255	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6256	}
6257
6258	/**
6259	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6260	*/
6261	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6262	{
6263	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6264	}
6265
6266	/**
6267	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6268	*/
6269	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6270	{
6271	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6272	}
6273
6274	/**
6275	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6276	*/
6277	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6278	{
6279	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6280	}
6281
6282	/**
6283	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6284	*/
6285	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6286	{
6287	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6288	}
6289
6290	#endif /* IN_RING3 */
6291	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6292
6293	/**
6294	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6295	*/
6296	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6297	size_t offSub, size_t cbSub, void **ppvMapping)
6298	{
6299	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6300	}
6301
6302	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6303	#ifdef IN_RING3
6304
6305	/**
6306	* @copydoc PDMDEVHLPR3::pfnROMRegister
6307	*/
6308	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6309	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6310	{
6311	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6312	}
6313
6314	/**
6315	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6316	*/
6317	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6318	{
6319	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6320	}
6321
6322	/**
6323	* Register a save state data unit.
6324	*
6325	* @returns VBox status.
6326	* @param pDevIns The device instance.
6327	* @param uVersion Data layout version number.
6328	* @param cbGuess The approximate amount of data in the unit.
6329	* Only for progress indicators.
6330	* @param pfnSaveExec Execute save callback, optional.
6331	* @param pfnLoadExec Execute load callback, optional.
6332	*/
6333	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6334	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6335	{
6336	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6337	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6338	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6339	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6340	}
6341
6342	/**
6343	* Register a save state data unit with a live save callback as well.
6344	*
6345	* @returns VBox status.
6346	* @param pDevIns The device instance.
6347	* @param uVersion Data layout version number.
6348	* @param cbGuess The approximate amount of data in the unit.
6349	* Only for progress indicators.
6350	* @param pfnLiveExec Execute live callback, optional.
6351	* @param pfnSaveExec Execute save callback, optional.
6352	* @param pfnLoadExec Execute load callback, optional.
6353	*/
6354	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6355	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6356	{
6357	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6358	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6359	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6360	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6361	}
6362
6363	/**
6364	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6365	*/
6366	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6367	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6368	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6369	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6370	{
6371	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6372	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6373	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6374	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6375	}
6376
6377	/**
6378	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6379	*/
6380	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6381	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6382	{
6383	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6384	}
6385
6386	#endif /* IN_RING3 */
6387
6388	/**
6389	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6390	*/
6391	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6392	{
6393	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6394	}
6395
6396	/**
6397	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6398	*/
6399	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6400	{
6401	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6402	}
6403
6404	/**
6405	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6406	*/
6407	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6408	{
6409	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6410	}
6411
6412	/**
6413	* @copydoc PDMDEVHLPR3::pfnTimerGet
6414	*/
6415	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6416	{
6417	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6418	}
6419
6420	/**
6421	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6422	*/
6423	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6424	{
6425	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6426	}
6427
6428	/**
6429	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6430	*/
6431	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6432	{
6433	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6434	}
6435
6436	/**
6437	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6438	*/
6439	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6440	{
6441	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6442	}
6443
6444	/**
6445	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6446	*/
6447	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6448	{
6449	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6450	}
6451
6452	/**
6453	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
6454	*/
6455	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6456	{
6457	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6458	}
6459
6460	/**
6461	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6462	*/
6463	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6464	{
6465	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6466	}
6467
6468	/**
6469	* @copydoc PDMDEVHLPR3::pfnTimerSet
6470	*/
6471	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6472	{
6473	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6474	}
6475
6476	/**
6477	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6478	*/
6479	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6480	{
6481	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6482	}
6483
6484	/**
6485	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6486	*/
6487	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6488	{
6489	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6490	}
6491
6492	/**
6493	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6494	*/
6495	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6496	{
6497	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6498	}
6499
6500	/**
6501	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6502	*/
6503	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6504	{
6505	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6506	}
6507
6508	/**
6509	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6510	*/
6511	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6512	{
6513	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6514	}
6515
6516	/**
6517	* @copydoc PDMDEVHLPR3::pfnTimerStop
6518	*/
6519	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6520	{
6521	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6522	}
6523
6524	/**
6525	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6526	*/
6527	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6528	{
6529	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6530	}
6531
6532	/**
6533	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6534	*/
6535	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6536	{
6537	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6538	}
6539
6540	#ifdef IN_RING3
6541
6542	/**
6543	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6544	*/
6545	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6546	{
6547	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6548	}
6549
6550	/**
6551	* @copydoc PDMDEVHLPR3::pfnTimerSave
6552	*/
6553	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6554	{
6555	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6556	}
6557
6558	/**
6559	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6560	*/
6561	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6562	{
6563	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6564	}
6565
6566	/**
6567	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6568	*/
6569	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6570	{
6571	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6572	}
6573
6574	/**
6575	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6576	*/
6577	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6578	{
6579	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6580	}
6581
6582	#endif
6583
6584	/**
6585	* Read physical memory - unknown data usage.
6586	*
6587	* @returns VINF_SUCCESS (for now).
6588	* @param pDevIns The device instance.
6589	* @param GCPhys Physical address start reading from.
6590	* @param pvBuf Where to put the read bits.
6591	* @param cbRead How many bytes to read.
6592	* @thread Any thread, but the call may involve the emulation thread.
6593	*/
6594	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6595	{
6596	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6597	}
6598
6599	/**
6600	* Write to physical memory - unknown data usage.
6601	*
6602	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6603	* @param pDevIns The device instance.
6604	* @param GCPhys Physical address to write to.
6605	* @param pvBuf What to write.
6606	* @param cbWrite How many bytes to write.
6607	* @thread Any thread, but the call may involve the emulation thread.
6608	*/
6609	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6610	{
6611	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6612	}
6613
6614	/**
6615	* Read physical memory - reads meta data processed by the device.
6616	*
6617	* @returns VINF_SUCCESS (for now).
6618	* @param pDevIns The device instance.
6619	* @param GCPhys Physical address start reading from.
6620	* @param pvBuf Where to put the read bits.
6621	* @param cbRead How many bytes to read.
6622	* @thread Any thread, but the call may involve the emulation thread.
6623	*/
6624	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6625	{
6626	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6627	}
6628
6629	/**
6630	* Write to physical memory - written data was created/altered by the device.
6631	*
6632	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6633	* @param pDevIns The device instance.
6634	* @param GCPhys Physical address to write to.
6635	* @param pvBuf What to write.
6636	* @param cbWrite How many bytes to write.
6637	* @thread Any thread, but the call may involve the emulation thread.
6638	*/
6639	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6640	{
6641	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6642	}
6643
6644	/**
6645	* Read physical memory - read data will not be touched by the device.
6646	*
6647	* @returns VINF_SUCCESS (for now).
6648	* @param pDevIns The device instance.
6649	* @param GCPhys Physical address start reading from.
6650	* @param pvBuf Where to put the read bits.
6651	* @param cbRead How many bytes to read.
6652	* @thread Any thread, but the call may involve the emulation thread.
6653	*/
6654	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6655	{
6656	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6657	}
6658
6659	/**
6660	* Write to physical memory - written data was not touched/created by the device.
6661	*
6662	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6663	* @param pDevIns The device instance.
6664	* @param GCPhys Physical address to write to.
6665	* @param pvBuf What to write.
6666	* @param cbWrite How many bytes to write.
6667	* @thread Any thread, but the call may involve the emulation thread.
6668	*/
6669	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6670	{
6671	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6672	}
6673
6674	#ifdef IN_RING3
6675
6676	/**
6677	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6678	*/
6679	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6680	{
6681	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6682	}
6683
6684	/**
6685	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6686	*/
6687	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6688	PPGMPAGEMAPLOCK pLock)
6689	{
6690	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6691	}
6692
6693	/**
6694	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6695	*/
6696	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6697	{
6698	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6699	}
6700
6701	/**
6702	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6703	*/
6704	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6705	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6706	{
6707	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6708	}
6709
6710	/**
6711	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6712	*/
6713	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6714	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6715	{
6716	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6717	}
6718
6719	/**
6720	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6721	*/
6722	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6723	{
6724	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6725	}
6726
6727	/**
6728	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
6729	*/
6730	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
6731	{
6732	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
6733	}
6734
6735	/**
6736	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
6737	*/
6738	DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth)
6739	{
6740	pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
6741	}
6742
6743	/**
6744	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6745	*/
6746	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6747	{
6748	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6749	}
6750
6751	/**
6752	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6753	*/
6754	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6755	{
6756	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6757	}
6758
6759	/**
6760	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6761	*/
6762	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6763	{
6764	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6765	}
6766
6767	/**
6768	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6769	*/
6770	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6771	{
6772	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6773	}
6774
6775	/**
6776	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6777	*/
6778	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6779	{
6780	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6781	}
6782
6783	/**
6784	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
6785	*/
6786	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6787	{
6788	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6789	}
6790	#endif /* IN_RING3 */
6791
6792	/**
6793	* @copydoc PDMDEVHLPR3::pfnVMState
6794	*/
6795	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6796	{
6797	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6798	}
6799
6800	#ifdef IN_RING3
6801	/**
6802	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6803	*/
6804	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6805	{
6806	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6807	}
6808	#endif /* IN_RING3 */
6809
6810	/**
6811	* @copydoc PDMDEVHLPR3::pfnVMSetError
6812	*/
6813	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6814	const char *pszFormat, ...)
6815	{
6816	va_list va;
6817	va_start(va, pszFormat);
6818	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6819	va_end(va);
6820	return rc;
6821	}
6822
6823	/**
6824	* @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError
6825	*/
6826	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6827	const char *pszFormat, ...)
6828	{
6829	va_list va;
6830	int rc;
6831	va_start(va, pszFormat);
6832	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6833	va_end(va);
6834	return rc;
6835	}
6836
6837	/**
6838	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6839	*
6840	* @returns VBox status code which must be passed up to the VMM. This will be
6841	* VINF_SUCCESS in non-strict builds.
6842	* @param pDevIns The device instance.
6843	* @param SRC_POS Use RT_SRC_POS.
6844	* @param pszFormat Message. (optional)
6845	* @param ... Message parameters.
6846	*/
6847	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6848	{
6849	#ifdef VBOX_STRICT
6850	# ifdef IN_RING3
6851	int rc;
6852	va_list args;
6853	va_start(args, pszFormat);
6854	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6855	va_end(args);
6856	return rc;
6857	# else
6858	NOREF(pDevIns);
6859	NOREF(pszFile);
6860	NOREF(iLine);
6861	NOREF(pszFunction);
6862	NOREF(pszFormat);
6863	return VINF_EM_DBG_STOP;
6864	# endif
6865	#else
6866	NOREF(pDevIns);
6867	NOREF(pszFile);
6868	NOREF(iLine);
6869	NOREF(pszFunction);
6870	NOREF(pszFormat);
6871	return VINF_SUCCESS;
6872	#endif
6873	}
6874
6875	#ifdef IN_RING3
6876
6877	/**
6878	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6879	*/
6880	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6881	{
6882	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6883	}
6884
6885	/**
6886	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6887	*/
6888	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6889	{
6890	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6891	}
6892
6893	/**
6894	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6895	*/
6896	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6897	{
6898	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6899	}
6900
6901	/**
6902	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
6903	*/
6904	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
6905	{
6906	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6907	}
6908
6909	/**
6910	* Same as pfnSTAMRegister except that the name is specified in a
6911	* RTStrPrintf like fashion.
6912	*
6913	* @returns VBox status.
6914	* @param pDevIns Device instance of the DMA.
6915	* @param pvSample Pointer to the sample.
6916	* @param enmType Sample type. This indicates what pvSample is
6917	* pointing at.
6918	* @param enmVisibility Visibility type specifying whether unused
6919	* statistics should be visible or not.
6920	* @param enmUnit Sample unit.
6921	* @param pszDesc Sample description.
6922	* @param pszName Sample name format string, unix path style. If
6923	* this does not start with a '/', the default
6924	* prefix will be prepended, otherwise it will be
6925	* used as-is.
6926	* @param ... Arguments to the format string.
6927	*/
6928	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6929	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6930	const char pszDesc, const char pszName, ...)
6931	{
6932	va_list va;
6933	va_start(va, pszName);
6934	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6935	va_end(va);
6936	}
6937
6938	/**
6939	* @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
6940	*/
6941	DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
6942	{
6943	return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
6944	}
6945
6946	/**
6947	* Registers the device with the default PCI bus.
6948	*
6949	* @returns VBox status code.
6950	* @param pDevIns The device instance.
6951	* @param pPciDev The PCI device structure.
6952	* This must be kept in the instance data.
6953	* The PCI configuration must be initialized before registration.
6954	*/
6955	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6956	{
6957	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
6958	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6959	}
6960
6961	/**
6962	* @copydoc PDMDEVHLPR3::pfnPCIRegister
6963	*/
6964	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6965	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6966	{
6967	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6968	}
6969
6970	/**
6971	* Initialize MSI emulation support for the first PCI device.
6972	*
6973	* @returns VBox status code.
6974	* @param pDevIns The device instance.
6975	* @param pMsiReg MSI emulation registration structure.
6976	*/
6977	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6978	{
6979	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6980	}
6981
6982	/**
6983	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6984	*/
6985	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6986	{
6987	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6988	}
6989
6990	/**
6991	* Registers a I/O port region for the default PCI device.
6992	*
6993	* @returns VBox status code.
6994	* @param pDevIns The device instance.
6995	* @param iRegion The region number.
6996	* @param cbRegion Size of the region.
6997	* @param hIoPorts Handle to the I/O port region.
6998	*/
6999	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
7000	{
7001	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7002	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
7003	}
7004
7005	/**
7006	* Registers a I/O port region for the default PCI device, custom map/unmap.
7007	*
7008	* @returns VBox status code.
7009	* @param pDevIns The device instance.
7010	* @param iRegion The region number.
7011	* @param cbRegion Size of the region.
7012	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7013	* callback will be invoked holding only the PDM lock.
7014	* The device lock will _not_ be taken (due to lock
7015	* order).
7016	*/
7017	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7018	PFNPCIIOREGIONMAP pfnMapUnmap)
7019	{
7020	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7021	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7022	UINT64_MAX, pfnMapUnmap);
7023	}
7024
7025	/**
7026	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7027	* and registering an I/O port region for the default PCI device.
7028	*
7029	* @returns VBox status code.
7030	* @param pDevIns The device instance to register the ports with.
7031	* @param cPorts The count of I/O ports in the region (the size).
7032	* @param iPciRegion The PCI device region.
7033	* @param pfnOut Pointer to function which is gonna handle OUT
7034	* operations. Optional.
7035	* @param pfnIn Pointer to function which is gonna handle IN operations.
7036	* Optional.
7037	* @param pvUser User argument to pass to the callbacks.
7038	* @param pszDesc Pointer to description string. This must not be freed.
7039	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7040	* coverage is allowed. This must not be freed.
7041	* @param phIoPorts Where to return the I/O port range handle.
7042	*
7043	*/
7044	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7045	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7046	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7047
7048	{
7049	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7050	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7051	if (RT_SUCCESS(rc))
7052	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7053	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7054	phIoPorts, NULL /pfnMapUnmap*/);
7055	return rc;
7056	}
7057
7058	/**
7059	* Registers an MMIO region for the default PCI device.
7060	*
7061	* @returns VBox status code.
7062	* @param pDevIns The device instance.
7063	* @param iRegion The region number.
7064	* @param cbRegion Size of the region.
7065	* @param enmType PCI_ADDRESS_SPACE_MEM or
7066	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7067	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7068	* @param hMmioRegion Handle to the MMIO region.
7069	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7070	* callback will be invoked holding only the PDM lock.
7071	* The device lock will _not_ be taken (due to lock
7072	* order).
7073	*/
7074	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7075	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7076	{
7077	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7078	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7079	hMmioRegion, pfnMapUnmap);
7080	}
7081
7082	/**
7083	* Registers an MMIO region for the default PCI device, extended version.
7084	*
7085	* @returns VBox status code.
7086	* @param pDevIns The device instance.
7087	* @param pPciDev The PCI device structure.
7088	* @param iRegion The region number.
7089	* @param cbRegion Size of the region.
7090	* @param enmType PCI_ADDRESS_SPACE_MEM or
7091	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7092	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7093	* @param hMmioRegion Handle to the MMIO region.
7094	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7095	* callback will be invoked holding only the PDM lock.
7096	* The device lock will _not_ be taken (due to lock
7097	* order).
7098	*/
7099	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7100	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7101	PFNPCIIOREGIONMAP pfnMapUnmap)
7102	{
7103	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7104	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7105	hMmioRegion, pfnMapUnmap);
7106	}
7107
7108	/**
7109	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7110	* and registering an MMIO region for the default PCI device.
7111	*
7112	* @returns VBox status code.
7113	* @param pDevIns The device instance to register the ports with.
7114	* @param cbRegion The size of the region in bytes.
7115	* @param iPciRegion The PCI device region.
7116	* @param enmType PCI_ADDRESS_SPACE_MEM or
7117	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7118	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7119	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7120	* @param pfnWrite Pointer to function which is gonna handle Write
7121	* operations.
7122	* @param pfnRead Pointer to function which is gonna handle Read
7123	* operations.
7124	* @param pvUser User argument to pass to the callbacks.
7125	* @param pszDesc Pointer to description string. This must not be freed.
7126	* @param phRegion Where to return the MMIO region handle.
7127	*
7128	*/
7129	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7130	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7131	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7132
7133	{
7134	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7135	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7136	if (RT_SUCCESS(rc))
7137	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7138	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7139	phRegion, NULL /pfnMapUnmap*/);
7140	return rc;
7141	}
7142
7143
7144	/**
7145	* Registers an MMIO2 region for the default PCI device.
7146	*
7147	* @returns VBox status code.
7148	* @param pDevIns The device instance.
7149	* @param iRegion The region number.
7150	* @param cbRegion Size of the region.
7151	* @param enmType PCI_ADDRESS_SPACE_MEM or
7152	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7153	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7154	* @param hMmio2Region Handle to the MMIO2 region.
7155	*/
7156	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7157	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7158	{
7159	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7160	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7161	hMmio2Region, NULL);
7162	}
7163
7164	/**
7165	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7166	* and registering an MMIO2 region for the default PCI device, extended edition.
7167	*
7168	* @returns VBox status code.
7169	* @param pDevIns The device instance to register the ports with.
7170	* @param cbRegion The size of the region in bytes.
7171	* @param iPciRegion The PCI device region.
7172	* @param enmType PCI_ADDRESS_SPACE_MEM or
7173	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7174	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7175	* @param pszDesc Pointer to description string. This must not be freed.
7176	* @param ppvMapping Where to store the address of the ring-3 mapping of
7177	* the memory.
7178	* @param phRegion Where to return the MMIO2 region handle.
7179	*
7180	*/
7181	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7182	PCIADDRESSSPACE enmType, const char *pszDesc,
7183	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7184
7185	{
7186	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7187	pszDesc, ppvMapping, phRegion);
7188	if (RT_SUCCESS(rc))
7189	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7190	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7191	phRegion, NULL /pfnCallback*/);
7192	return rc;
7193	}
7194
7195	/**
7196	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7197	* and registering an MMIO2 region for the default PCI device.
7198	*
7199	* @returns VBox status code.
7200	* @param pDevIns The device instance to register the ports with.
7201	* @param cbRegion The size of the region in bytes.
7202	* @param iPciRegion The PCI device region.
7203	* @param enmType PCI_ADDRESS_SPACE_MEM or
7204	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7205	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7206	* @param fMmio2Flags To be defined, must be zero.
7207	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7208	* callback will be invoked holding only the PDM lock.
7209	* The device lock will _not_ be taken (due to lock
7210	* order).
7211	* @param pszDesc Pointer to description string. This must not be freed.
7212	* @param ppvMapping Where to store the address of the ring-3 mapping of
7213	* the memory.
7214	* @param phRegion Where to return the MMIO2 region handle.
7215	*
7216	*/
7217	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7218	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7219	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
7220
7221	{
7222	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7223	pszDesc, ppvMapping, phRegion);
7224	if (RT_SUCCESS(rc))
7225	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7226	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7227	*phRegion, pfnMapUnmap);
7228	return rc;
7229	}
7230
7231	/**
7232	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7233	*/
7234	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7235	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7236	{
7237	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7238	}
7239
7240	/**
7241	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7242	*/
7243	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7244	unsigned cb, uint32_t *pu32Value)
7245	{
7246	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7247	}
7248
7249	/**
7250	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7251	*/
7252	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7253	unsigned cb, uint32_t u32Value)
7254	{
7255	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7256	}
7257
7258	#endif /* IN_RING3 */
7259
7260	/**
7261	* Bus master physical memory read from the default PCI device.
7262	*
7263	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7264	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7265	* @param pDevIns The device instance.
7266	* @param GCPhys Physical address start reading from.
7267	* @param pvBuf Where to put the read bits.
7268	* @param cbRead How many bytes to read.
7269	* @thread Any thread, but the call may involve the emulation thread.
7270	*/
7271	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7272	{
7273	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7274	}
7275
7276	/**
7277	* Bus master physical memory read - unknown data usage.
7278	*
7279	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7280	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7281	* @param pDevIns The device instance.
7282	* @param pPciDev The PCI device structure. If NULL the default
7283	* PCI device for this device instance is used.
7284	* @param GCPhys Physical address start reading from.
7285	* @param pvBuf Where to put the read bits.
7286	* @param cbRead How many bytes to read.
7287	* @thread Any thread, but the call may involve the emulation thread.
7288	*/
7289	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7290	{
7291	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7292	}
7293
7294	/**
7295	* Bus master physical memory read from the default PCI device.
7296	*
7297	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7298	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7299	* @param pDevIns The device instance.
7300	* @param GCPhys Physical address start reading from.
7301	* @param pvBuf Where to put the read bits.
7302	* @param cbRead How many bytes to read.
7303	* @thread Any thread, but the call may involve the emulation thread.
7304	*/
7305	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7306	{
7307	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7308	}
7309
7310	/**
7311	* Bus master physical memory read - reads meta data processed by the device.
7312	*
7313	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7314	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7315	* @param pDevIns The device instance.
7316	* @param pPciDev The PCI device structure. If NULL the default
7317	* PCI device for this device instance is used.
7318	* @param GCPhys Physical address start reading from.
7319	* @param pvBuf Where to put the read bits.
7320	* @param cbRead How many bytes to read.
7321	* @thread Any thread, but the call may involve the emulation thread.
7322	*/
7323	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7324	{
7325	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7326	}
7327
7328	/**
7329	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
7330	*
7331	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7332	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7333	* @param pDevIns The device instance.
7334	* @param GCPhys Physical address start reading from.
7335	* @param pvBuf Where to put the read bits.
7336	* @param cbRead How many bytes to read.
7337	* @thread Any thread, but the call may involve the emulation thread.
7338	*/
7339	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7340	{
7341	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7342	}
7343
7344	/**
7345	* Bus master physical memory read - read data will not be touched by the device.
7346	*
7347	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7348	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7349	* @param pDevIns The device instance.
7350	* @param pPciDev The PCI device structure. If NULL the default
7351	* PCI device for this device instance is used.
7352	* @param GCPhys Physical address start reading from.
7353	* @param pvBuf Where to put the read bits.
7354	* @param cbRead How many bytes to read.
7355	* @thread Any thread, but the call may involve the emulation thread.
7356	*/
7357	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7358	{
7359	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7360	}
7361
7362	/**
7363	* Bus master physical memory write from the default PCI device - unknown data usage.
7364	*
7365	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7366	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7367	* @param pDevIns The device instance.
7368	* @param GCPhys Physical address to write to.
7369	* @param pvBuf What to write.
7370	* @param cbWrite How many bytes to write.
7371	* @thread Any thread, but the call may involve the emulation thread.
7372	*/
7373	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7374	{
7375	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7376	}
7377
7378	/**
7379	* Bus master physical memory write - unknown data usage.
7380	*
7381	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7382	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7383	* @param pDevIns The device instance.
7384	* @param pPciDev The PCI device structure. If NULL the default
7385	* PCI device for this device instance is used.
7386	* @param GCPhys Physical address to write to.
7387	* @param pvBuf What to write.
7388	* @param cbWrite How many bytes to write.
7389	* @thread Any thread, but the call may involve the emulation thread.
7390	*/
7391	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7392	{
7393	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7394	}
7395
7396	/**
7397	* Bus master physical memory write from the default PCI device.
7398	*
7399	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7400	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7401	* @param pDevIns The device instance.
7402	* @param GCPhys Physical address to write to.
7403	* @param pvBuf What to write.
7404	* @param cbWrite How many bytes to write.
7405	* @thread Any thread, but the call may involve the emulation thread.
7406	*/
7407	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7408	{
7409	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7410	}
7411
7412	/**
7413	* Bus master physical memory write - written data was created/altered by the device.
7414	*
7415	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7416	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7417	* @param pDevIns The device instance.
7418	* @param pPciDev The PCI device structure. If NULL the default
7419	* PCI device for this device instance is used.
7420	* @param GCPhys Physical address to write to.
7421	* @param pvBuf What to write.
7422	* @param cbWrite How many bytes to write.
7423	* @thread Any thread, but the call may involve the emulation thread.
7424	*/
7425	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7426	{
7427	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7428	}
7429
7430	/**
7431	* Bus master physical memory write from the default PCI device.
7432	*
7433	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7434	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7435	* @param pDevIns The device instance.
7436	* @param GCPhys Physical address to write to.
7437	* @param pvBuf What to write.
7438	* @param cbWrite How many bytes to write.
7439	* @thread Any thread, but the call may involve the emulation thread.
7440	*/
7441	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7442	{
7443	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7444	}
7445
7446	/**
7447	* Bus master physical memory write - written data was not touched/created by the device.
7448	*
7449	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7450	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7451	* @param pDevIns The device instance.
7452	* @param pPciDev The PCI device structure. If NULL the default
7453	* PCI device for this device instance is used.
7454	* @param GCPhys Physical address to write to.
7455	* @param pvBuf What to write.
7456	* @param cbWrite How many bytes to write.
7457	* @thread Any thread, but the call may involve the emulation thread.
7458	*/
7459	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7460	{
7461	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7462	}
7463
7464	#ifdef IN_RING3
7465	/**
7466	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
7467	*/
7468	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7469	void **ppv, PPGMPAGEMAPLOCK pLock)
7470	{
7471	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7472	}
7473
7474	/**
7475	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
7476	*/
7477	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7478	void const **ppv, PPGMPAGEMAPLOCK pLock)
7479	{
7480	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7481	}
7482
7483	/**
7484	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
7485	*/
7486	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7487	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
7488	PPGMPAGEMAPLOCK paLocks)
7489	{
7490	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
7491	paLocks);
7492	}
7493
7494	/**
7495	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
7496	*/
7497	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7498	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
7499	PPGMPAGEMAPLOCK paLocks)
7500	{
7501	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
7502	papvPages, paLocks);
7503	}
7504	#endif /* IN_RING3 */
7505
7506	/**
7507	* Sets the IRQ for the default PCI device.
7508	*
7509	* @param pDevIns The device instance.
7510	* @param iIrq IRQ number to set.
7511	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7512	* @thread Any thread, but will involve the emulation thread.
7513	*/
7514	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7515	{
7516	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7517	}
7518
7519	/**
7520	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
7521	*/
7522	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7523	{
7524	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7525	}
7526
7527	/**
7528	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7529	* the request when not called from EMT.
7530	*
7531	* @param pDevIns The device instance.
7532	* @param iIrq IRQ number to set.
7533	* @param iLevel IRQ level.
7534	* @thread Any thread, but will involve the emulation thread.
7535	*/
7536	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7537	{
7538	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7539	}
7540
7541	/**
7542	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7543	*/
7544	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7545	{
7546	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7547	}
7548
7549	/**
7550	* @copydoc PDMDEVHLPR3::pfnISASetIrq
7551	*/
7552	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7553	{
7554	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7555	}
7556
7557	/**
7558	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7559	*/
7560	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7561	{
7562	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7563	}
7564
7565	#ifdef IN_RING3
7566
7567	/**
7568	* @copydoc PDMDEVHLPR3::pfnDriverAttach
7569	*/
7570	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
7571	{
7572	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7573	}
7574
7575	/**
7576	* @copydoc PDMDEVHLPR3::pfnDriverDetach
7577	*/
7578	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7579	{
7580	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7581	}
7582
7583	/**
7584	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
7585	*/
7586	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
7587	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
7588	{
7589	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
7590	}
7591
7592	/**
7593	* Reconfigures with a single driver reattachement, no config, noflags.
7594	* @sa PDMDevHlpDriverReconfigure
7595	*/
7596	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
7597	{
7598	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
7599	}
7600
7601	/**
7602	* Reconfigures with a two drivers reattachement, no config, noflags.
7603	* @sa PDMDevHlpDriverReconfigure
7604	*/
7605	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
7606	{
7607	char const * apszDrivers[2];
7608	apszDrivers[0] = pszDriver0;
7609	apszDrivers[1] = pszDriver1;
7610	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
7611	}
7612
7613	/**
7614	* @copydoc PDMDEVHLPR3::pfnQueueCreatePtr
7615	*/
7616	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7617	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PPDMQUEUE ppQueue)
7618	{
7619	return pDevIns->pHlpR3->pfnQueueCreatePtr(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
7620	}
7621
7622	/**
7623	* @copydoc PDMDEVHLPR3::pfnQueueCreate
7624	*/
7625	DECLINLINE(int) PDMDevHlpQueueCreateNew(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7626	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
7627	{
7628	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7629	}
7630
7631	#endif /* IN_RING3 */
7632
7633	/**
7634	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
7635	*/
7636	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7637	{
7638	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7639	}
7640
7641	/**
7642	* @copydoc PDMDEVHLPR3::pfnQueueInsert
7643	*/
7644	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7645	{
7646	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7647	}
7648
7649	/**
7650	* @copydoc PDMDEVHLPR3::pfnQueueInsertEx
7651	*/
7652	DECLINLINE(void) PDMDevHlpQueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay)
7653	{
7654	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsertEx(pDevIns, hQueue, pItem, cNanoMaxDelay);
7655	}
7656
7657	/**
7658	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7659	*/
7660	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7661	{
7662	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7663	}
7664
7665	#ifdef IN_RING3
7666	/**
7667	* @copydoc PDMDEVHLPR3::pfnTaskCreate
7668	*/
7669	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7670	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
7671	{
7672	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7673	}
7674	#endif
7675
7676	/**
7677	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
7678	*/
7679	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7680	{
7681	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7682	}
7683
7684	#ifdef IN_RING3
7685
7686	/**
7687	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7688	*/
7689	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7690	{
7691	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7692	}
7693
7694	/**
7695	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7696	*/
7697	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7698	{
7699	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7700	}
7701
7702	#endif /* IN_RING3 */
7703
7704	/**
7705	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7706	*/
7707	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7708	{
7709	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7710	}
7711
7712	/**
7713	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7714	*/
7715	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7716	{
7717	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7718	}
7719
7720	/**
7721	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7722	*/
7723	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7724	{
7725	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7726	}
7727
7728	/**
7729	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7730	*/
7731	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7732	{
7733	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7734	}
7735
7736	/**
7737	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7738	*/
7739	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7740	{
7741	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7742	}
7743
7744	#ifdef IN_RING3
7745
7746	/**
7747	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7748	*/
7749	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7750	{
7751	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7752	}
7753
7754	/**
7755	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7756	*/
7757	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7758	{
7759	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7760	}
7761
7762	#endif /* IN_RING3 */
7763
7764	/**
7765	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7766	*/
7767	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7768	{
7769	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7770	}
7771
7772	/**
7773	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7774	*/
7775	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7776	{
7777	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7778	}
7779
7780	/**
7781	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7782	*/
7783	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7784	{
7785	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7786	}
7787
7788	/**
7789	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7790	*/
7791	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7792	{
7793	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7794	}
7795
7796	/**
7797	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7798	*/
7799	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7800	{
7801	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7802	}
7803
7804	/**
7805	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7806	*/
7807	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7808	{
7809	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7810	}
7811
7812	#ifdef IN_RING3
7813
7814	/**
7815	* Initializes a PDM critical section.
7816	*
7817	* The PDM critical sections are derived from the IPRT critical sections, but
7818	* works in RC and R0 as well.
7819	*
7820	* @returns VBox status code.
7821	* @param pDevIns The device instance.
7822	* @param pCritSect Pointer to the critical section.
7823	* @param SRC_POS Use RT_SRC_POS.
7824	* @param pszNameFmt Format string for naming the critical section.
7825	* For statistics and lock validation.
7826	* @param ... Arguments for the format string.
7827	*/
7828	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7829	const char *pszNameFmt, ...)
7830	{
7831	int rc;
7832	va_list va;
7833	va_start(va, pszNameFmt);
7834	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7835	va_end(va);
7836	return rc;
7837	}
7838
7839	#endif /* IN_RING3 */
7840
7841	/**
7842	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7843	*/
7844	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7845	{
7846	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7847	}
7848
7849	#ifdef IN_RING3
7850
7851	/**
7852	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopR0
7853	*/
7854	DECLINLINE(R0PTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopR0(PPDMDEVINS pDevIns)
7855	{
7856	return pDevIns->pHlpR3->pfnCritSectGetNopR0(pDevIns);
7857	}
7858
7859	/**
7860	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopRC
7861	*/
7862	DECLINLINE(RCPTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopRC(PPDMDEVINS pDevIns)
7863	{
7864	return pDevIns->pHlpR3->pfnCritSectGetNopRC(pDevIns);
7865	}
7866
7867	#endif /* IN_RING3 */
7868
7869	/**
7870	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7871	*/
7872	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7873	{
7874	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7875	}
7876
7877	/**
7878	* Enters a PDM critical section.
7879	*
7880	* @returns VINF_SUCCESS if entered successfully.
7881	* @returns rcBusy when encountering a busy critical section in RC/R0.
7882	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7883	* during the operation.
7884	*
7885	* @param pDevIns The device instance.
7886	* @param pCritSect The PDM critical section to enter.
7887	* @param rcBusy The status code to return when we're in RC or R0
7888	* and the section is busy. Pass VINF_SUCCESS to
7889	* acquired the critical section thru a ring-3
7890	* call if necessary.
7891	*
7892	* @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
7893	* possible failures in ring-0 or at least apply
7894	* PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
7895	* function.
7896	*
7897	* @sa PDMCritSectEnter
7898	*/
7899	DECLINLINE(int) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7900	{
7901	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7902	}
7903
7904	/**
7905	* Enters a PDM critical section, with location information for debugging.
7906	*
7907	* @returns VINF_SUCCESS if entered successfully.
7908	* @returns rcBusy when encountering a busy critical section in RC/R0.
7909	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7910	* during the operation.
7911	*
7912	* @param pDevIns The device instance.
7913	* @param pCritSect The PDM critical section to enter.
7914	* @param rcBusy The status code to return when we're in RC or R0
7915	* and the section is busy. Pass VINF_SUCCESS to
7916	* acquired the critical section thru a ring-3
7917	* call if necessary.
7918	* @param uId Some kind of locking location ID. Typically a
7919	* return address up the stack. Optional (0).
7920	* @param SRC_POS The source position where to lock is being
7921	* acquired from. Optional.
7922	* @sa PDMCritSectEnterDebug
7923	*/
7924	DECLINLINE(int) PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7925	{
7926	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7927	}
7928
7929	/**
7930	* Try enter a critical section.
7931	*
7932	* @retval VINF_SUCCESS on success.
7933	* @retval VERR_SEM_BUSY if the critsect was owned.
7934	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
7935	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7936	* during the operation.
7937	*
7938	* @param pDevIns The device instance.
7939	* @param pCritSect The critical section.
7940	* @sa PDMCritSectTryEnter
7941	*/
7942	DECLINLINE(int) PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7943	{
7944	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7945	}
7946
7947	/**
7948	* Try enter a critical section, with location information for debugging.
7949	*
7950	* @retval VINF_SUCCESS on success.
7951	* @retval VERR_SEM_BUSY if the critsect was owned.
7952	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
7953	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7954	* during the operation.
7955	*
7956	* @param pDevIns The device instance.
7957	* @param pCritSect The critical section.
7958	* @param uId Some kind of locking location ID. Typically a
7959	* return address up the stack. Optional (0).
7960	* @param SRC_POS The source position where to lock is being
7961	* acquired from. Optional.
7962	* @sa PDMCritSectTryEnterDebug
7963	*/
7964	DECLINLINE(int) PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7965	{
7966	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7967	}
7968
7969	/**
7970	* Leaves a critical section entered with PDMCritSectEnter().
7971	*
7972	* @returns Indication whether we really exited the critical section.
7973	* @retval VINF_SUCCESS if we really exited.
7974	* @retval VINF_SEM_NESTED if we only reduced the nesting count.
7975	* @retval VERR_NOT_OWNER if you somehow ignore release assertions.
7976	*
7977	* @param pDevIns The device instance.
7978	* @param pCritSect The PDM critical section to leave.
7979	* @sa PDMCritSectLeave
7980	*/
7981	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7982	{
7983	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7984	}
7985
7986	/**
7987	* @see PDMCritSectIsOwner
7988	*/
7989	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7990	{
7991	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7992	}
7993
7994	/**
7995	* @see PDMCritSectIsInitialized
7996	*/
7997	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7998	{
7999	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
8000	}
8001
8002	/**
8003	* @see PDMCritSectHasWaiters
8004	*/
8005	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8006	{
8007	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
8008	}
8009
8010	/**
8011	* @see PDMCritSectGetRecursion
8012	*/
8013	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8014	{
8015	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
8016	}
8017
8018	#if defined(IN_RING3) \|\| defined(IN_RING0)
8019	/**
8020	* @see PDMHCCritSectScheduleExitEvent
8021	*/
8022	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
8023	{
8024	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
8025	}
8026	#endif
8027
8028	/* Strict build: Remap the two enter calls to the debug versions. */
8029	#ifdef VBOX_STRICT
8030	# ifdef IPRT_INCLUDED_asm_h
8031	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8032	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8033	# else
8034	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8035	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8036	# endif
8037	#endif
8038
8039	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8040
8041	/**
8042	* Deletes the critical section.
8043	*
8044	* @returns VBox status code.
8045	* @param pDevIns The device instance.
8046	* @param pCritSect The PDM critical section to destroy.
8047	* @sa PDMR3CritSectDelete
8048	*/
8049	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8050	{
8051	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8052	}
8053
8054	/**
8055	* @copydoc PDMDEVHLPR3::pfnThreadCreate
8056	*/
8057	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
8058	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
8059	{
8060	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
8061	}
8062
8063	/**
8064	* @copydoc PDMR3ThreadDestroy
8065	* @param pDevIns The device instance.
8066	*/
8067	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
8068	{
8069	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
8070	}
8071
8072	/**
8073	* @copydoc PDMR3ThreadIAmSuspending
8074	* @param pDevIns The device instance.
8075	*/
8076	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8077	{
8078	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
8079	}
8080
8081	/**
8082	* @copydoc PDMR3ThreadIAmRunning
8083	* @param pDevIns The device instance.
8084	*/
8085	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8086	{
8087	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
8088	}
8089
8090	/**
8091	* @copydoc PDMR3ThreadSleep
8092	* @param pDevIns The device instance.
8093	*/
8094	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
8095	{
8096	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
8097	}
8098
8099	/**
8100	* @copydoc PDMR3ThreadSuspend
8101	* @param pDevIns The device instance.
8102	*/
8103	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8104	{
8105	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
8106	}
8107
8108	/**
8109	* @copydoc PDMR3ThreadResume
8110	* @param pDevIns The device instance.
8111	*/
8112	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8113	{
8114	return pDevIns->pHlpR3->pfnThreadResume(pThread);
8115	}
8116
8117	/**
8118	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
8119	*/
8120	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
8121	{
8122	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
8123	}
8124
8125	/**
8126	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
8127	*/
8128	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
8129	{
8130	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
8131	}
8132
8133	/**
8134	* @copydoc PDMDEVHLPR3::pfnA20Set
8135	*/
8136	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
8137	{
8138	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
8139	}
8140
8141	/**
8142	* @copydoc PDMDEVHLPR3::pfnRTCRegister
8143	*/
8144	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
8145	{
8146	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
8147	}
8148
8149	/**
8150	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
8151	*/
8152	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
8153	{
8154	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
8155	}
8156
8157	/**
8158	* @copydoc PDMDEVHLPR3::pfnIommuRegister
8159	*/
8160	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
8161	{
8162	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
8163	}
8164
8165	/**
8166	* @copydoc PDMDEVHLPR3::pfnPICRegister
8167	*/
8168	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8169	{
8170	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
8171	}
8172
8173	/**
8174	* @copydoc PDMDEVHLPR3::pfnApicRegister
8175	*/
8176	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
8177	{
8178	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
8179	}
8180
8181	/**
8182	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
8183	*/
8184	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8185	{
8186	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
8187	}
8188
8189	/**
8190	* @copydoc PDMDEVHLPR3::pfnHpetRegister
8191	*/
8192	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
8193	{
8194	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
8195	}
8196
8197	/**
8198	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
8199	*/
8200	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
8201	{
8202	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
8203	}
8204
8205	/**
8206	* @copydoc PDMDEVHLPR3::pfnDMACRegister
8207	*/
8208	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
8209	{
8210	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
8211	}
8212
8213	/**
8214	* @copydoc PDMDEVHLPR3::pfnDMARegister
8215	*/
8216	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
8217	{
8218	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
8219	}
8220
8221	/**
8222	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
8223	*/
8224	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
8225	{
8226	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
8227	}
8228
8229	/**
8230	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
8231	*/
8232	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
8233	{
8234	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
8235	}
8236
8237	/**
8238	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
8239	*/
8240	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
8241	{
8242	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
8243	}
8244
8245	/**
8246	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
8247	*/
8248	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
8249	{
8250	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
8251	}
8252
8253	/**
8254	* @copydoc PDMDEVHLPR3::pfnDMASchedule
8255	*/
8256	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
8257	{
8258	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
8259	}
8260
8261	/**
8262	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
8263	*/
8264	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
8265	{
8266	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
8267	}
8268
8269	/**
8270	* @copydoc PDMDEVHLPR3::pfnCMOSRead
8271	*/
8272	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
8273	{
8274	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
8275	}
8276
8277	/**
8278	* @copydoc PDMDEVHLPR3::pfnCallR0
8279	*/
8280	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
8281	{
8282	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
8283	}
8284
8285	/**
8286	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
8287	*/
8288	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
8289	{
8290	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
8291	}
8292
8293	/**
8294	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
8295	*/
8296	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
8297	{
8298	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
8299	}
8300
8301	/**
8302	* @copydoc PDMDEVHLPR3::pfnGetUVM
8303	*/
8304	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
8305	{
8306	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
8307	}
8308
8309	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
8310
8311	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8312
8313	/**
8314	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
8315	*/
8316	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
8317	{
8318	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
8319	}
8320
8321	/**
8322	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
8323	*/
8324	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
8325	{
8326	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
8327	}
8328
8329	/**
8330	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
8331	*/
8332	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8333	{
8334	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
8335	}
8336
8337	/**
8338	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
8339	*/
8340	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
8341	{
8342	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
8343	}
8344
8345	/**
8346	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
8347	*/
8348	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8349	{
8350	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
8351	}
8352
8353	/**
8354	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
8355	*/
8356	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
8357	{
8358	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
8359	}
8360
8361	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
8362
8363	/**
8364	* @copydoc PDMDEVHLPR3::pfnGetVM
8365	*/
8366	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
8367	{
8368	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
8369	}
8370
8371	/**
8372	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
8373	*/
8374	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
8375	{
8376	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
8377	}
8378
8379	/**
8380	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
8381	*/
8382	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
8383	{
8384	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
8385	}
8386
8387	/**
8388	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
8389	*/
8390	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
8391	{
8392	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
8393	}
8394
8395	/**
8396	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8397	*/
8398	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8399	{
8400	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8401	}
8402
8403	/**
8404	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8405	*/
8406	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8407	{
8408	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8409	}
8410
8411	#ifdef IN_RING3
8412
8413	/**
8414	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8415	*/
8416	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8417	{
8418	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
8419	}
8420
8421	/**
8422	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
8423	*/
8424	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
8425	{
8426	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
8427	}
8428
8429	/**
8430	* @copydoc PDMDEVHLPR3::pfnVMReset
8431	*/
8432	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
8433	{
8434	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
8435	}
8436
8437	/**
8438	* @copydoc PDMDEVHLPR3::pfnVMSuspend
8439	*/
8440	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8441	{
8442	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8443	}
8444
8445	/**
8446	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8447	*/
8448	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8449	{
8450	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8451	}
8452
8453	/**
8454	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
8455	*/
8456	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8457	{
8458	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8459	}
8460
8461	#endif /* IN_RING3 */
8462
8463	/**
8464	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8465	*/
8466	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8467	{
8468	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8469	}
8470
8471	#ifdef IN_RING3
8472
8473	/**
8474	* @copydoc PDMDEVHLPR3::pfnGetCpuId
8475	*/
8476	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
8477	{
8478	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8479	}
8480
8481	/**
8482	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8483	*/
8484	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8485	{
8486	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8487	}
8488
8489	/**
8490	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8491	*/
8492	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8493	{
8494	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8495	}
8496
8497	/**
8498	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
8499	*/
8500	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
8501	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
8502	const char pszHandlerR0, const char pszPfHandlerR0,
8503	const char pszHandlerRC, const char pszPfHandlerRC,
8504	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
8505	{
8506	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
8507	pszHandlerR0, pszPfHandlerR0,
8508	pszHandlerRC, pszPfHandlerRC,
8509	pszDesc, phType);
8510	}
8511
8512	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
8513	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8514	do { \
8515	uint32_t u32GetEnumTmp = 0; \
8516	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
8517	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8518	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
8519	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
8520	} while (0)
8521
8522	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
8523	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8524	do { \
8525	uint8_t bGetEnumTmp = 0; \
8526	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
8527	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8528	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
8529	} while (0)
8530
8531	#endif /* IN_RING3 */
8532
8533	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
8534	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
8535
8536	/**
8537	* Callbacks for VBoxDeviceRegister().
8538	*/
8539	typedef struct PDMDEVREGCB
8540	{
8541	/** Interface version.
8542	* This is set to PDM_DEVREG_CB_VERSION. */
8543	uint32_t u32Version;
8544
8545	/**
8546	* Registers a device with the current VM instance.
8547	*
8548	* @returns VBox status code.
8549	* @param pCallbacks Pointer to the callback table.
8550	* @param pReg Pointer to the device registration record.
8551	* This data must be permanent and readonly.
8552	*/
8553	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
8554	} PDMDEVREGCB;
8555
8556	/** Current version of the PDMDEVREGCB structure. */
8557	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
8558
8559
8560	/**
8561	* The VBoxDevicesRegister callback function.
8562	*
8563	* PDM will invoke this function after loading a device module and letting
8564	* the module decide which devices to register and how to handle conflicts.
8565	*
8566	* @returns VBox status code.
8567	* @param pCallbacks Pointer to the callback table.
8568	* @param u32Version VBox version number.
8569	*/
8570	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
8571
8572	/** @} */
8573
8574	RT_C_DECLS_END
8575
8576	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 90433

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