pdmdev.h@ 91909

Last change on this file since 91909 was 91909, checked in by vboxsync, 3 years ago
VMM,PDM: Eliminated PDMDevHlpCritSectGetNopR0 and PDMDevHlpCritSectGetNopRC as they are no longer used. bugref:9218
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 365.6 KB

Line
1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmcritsectrw.h>
34	#include <VBox/vmm/pdmqueue.h>
35	#include <VBox/vmm/pdmtask.h>
36	#ifdef IN_RING3
37	# include <VBox/vmm/pdmthread.h>
38	#endif
39	#include <VBox/vmm/pdmifs.h>
40	#include <VBox/vmm/pdmins.h>
41	#include <VBox/vmm/pdmcommon.h>
42	#include <VBox/vmm/pdmpcidev.h>
43	#include <VBox/vmm/iom.h>
44	#include <VBox/vmm/mm.h>
45	#include <VBox/vmm/tm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/cfgm.h>
48	#include <VBox/vmm/cpum.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
51	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
52	#include <VBox/msi.h>
53	#include <iprt/stdarg.h>
54	#include <iprt/list.h>
55
56
57	RT_C_DECLS_BEGIN
58
59	/** @defgroup grp_pdm_device The PDM Devices API
60	* @ingroup grp_pdm
61	* @{
62	*/
63
64	/**
65	* Construct a device instance for a VM.
66	*
67	* @returns VBox status.
68	* @param pDevIns The device instance data. If the registration structure
69	* is needed, it can be accessed thru pDevIns->pReg.
70	* @param iInstance Instance number. Use this to figure out which registers
71	* and such to use. The instance number is also found in
72	* pDevIns->iInstance, but since it's likely to be
73	* frequently used PDM passes it as parameter.
74	* @param pCfg Configuration node handle for the driver. This is
75	* expected to be in high demand in the constructor and is
76	* therefore passed as an argument. When using it at other
77	* times, it can be found in pDevIns->pCfg.
78	*/
79	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
80	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
81	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
82
83	/**
84	* Destruct a device instance.
85	*
86	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
87	* resources can be freed correctly.
88	*
89	* @returns VBox status.
90	* @param pDevIns The device instance data.
91	*
92	* @remarks The device critical section is not entered. The routine may delete
93	* the critical section, so the caller cannot exit it.
94	*/
95	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
96	/** Pointer to a FNPDMDEVDESTRUCT() function. */
97	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
98
99	/**
100	* Device relocation callback.
101	*
102	* This is called when the instance data has been relocated in raw-mode context
103	* (RC). It is also called when the RC hypervisor selects changes. The device
104	* must fixup all necessary pointers and re-query all interfaces to other RC
105	* devices and drivers.
106	*
107	* Before the RC code is executed the first time, this function will be called
108	* with a 0 delta so RC pointer calculations can be one in one place.
109	*
110	* @param pDevIns Pointer to the device instance.
111	* @param offDelta The relocation delta relative to the old location.
112	*
113	* @remarks A relocation CANNOT fail.
114	*
115	* @remarks The device critical section is not entered. The relocations should
116	* not normally require any locking.
117	*/
118	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
119	/** Pointer to a FNPDMDEVRELOCATE() function. */
120	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
121
122	/**
123	* Power On notification.
124	*
125	* @returns VBox status.
126	* @param pDevIns The device instance data.
127	*
128	* @remarks Caller enters the device critical section.
129	*/
130	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
131	/** Pointer to a FNPDMDEVPOWERON() function. */
132	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
133
134	/**
135	* Reset notification.
136	*
137	* @returns VBox status.
138	* @param pDevIns The device instance data.
139	*
140	* @remarks Caller enters the device critical section.
141	*/
142	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
143	/** Pointer to a FNPDMDEVRESET() function. */
144	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
145
146	/**
147	* Soft reset notification.
148	*
149	* This is mainly for emulating the 286 style protected mode exits, in which
150	* most devices should remain in their current state.
151	*
152	* @returns VBox status.
153	* @param pDevIns The device instance data.
154	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
155	*
156	* @remarks Caller enters the device critical section.
157	*/
158	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
159	/** Pointer to a FNPDMDEVSOFTRESET() function. */
160	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
161
162	/** @name PDMVMRESET_F_XXX - VM reset flags.
163	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
164	* reset via PDMDevHlpVMReset.
165	* @{ */
166	/** Unknown reason. */
167	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
168	/** GIM triggered reset. */
169	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
170	/** The last source always causing hard resets. */
171	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
172	/** ACPI triggered reset. */
173	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
174	/** PS/2 system port A (92h) reset. */
175	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
176	/** Keyboard reset. */
177	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
178	/** Tripple fault. */
179	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
180	/** Reset source mask. */
181	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
182	/** @} */
183
184	/**
185	* Suspend notification.
186	*
187	* @returns VBox status.
188	* @param pDevIns The device instance data.
189	* @thread EMT(0)
190	*
191	* @remarks Caller enters the device critical section.
192	*/
193	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
194	/** Pointer to a FNPDMDEVSUSPEND() function. */
195	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
196
197	/**
198	* Resume notification.
199	*
200	* @returns VBox status.
201	* @param pDevIns The device instance data.
202	*
203	* @remarks Caller enters the device critical section.
204	*/
205	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
206	/** Pointer to a FNPDMDEVRESUME() function. */
207	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
208
209	/**
210	* Power Off notification.
211	*
212	* This is always called when VMR3PowerOff is called.
213	* There will be no callback when hot plugging devices.
214	*
215	* @param pDevIns The device instance data.
216	* @thread EMT(0)
217	*
218	* @remarks Caller enters the device critical section.
219	*/
220	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
221	/** Pointer to a FNPDMDEVPOWEROFF() function. */
222	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
223
224	/**
225	* Attach command.
226	*
227	* This is called to let the device attach to a driver for a specified LUN
228	* at runtime. This is not called during VM construction, the device
229	* constructor has to attach to all the available drivers.
230	*
231	* This is like plugging in the keyboard or mouse after turning on the PC.
232	*
233	* @returns VBox status code.
234	* @param pDevIns The device instance.
235	* @param iLUN The logical unit which is being attached.
236	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
237	*
238	* @remarks Caller enters the device critical section.
239	*/
240	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
241	/** Pointer to a FNPDMDEVATTACH() function. */
242	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
243
244	/**
245	* Detach notification.
246	*
247	* This is called when a driver is detaching itself from a LUN of the device.
248	* The device should adjust its state to reflect this.
249	*
250	* This is like unplugging the network cable to use it for the laptop or
251	* something while the PC is still running.
252	*
253	* @param pDevIns The device instance.
254	* @param iLUN The logical unit which is being detached.
255	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
256	*
257	* @remarks Caller enters the device critical section.
258	*/
259	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
260	/** Pointer to a FNPDMDEVDETACH() function. */
261	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
262
263	/**
264	* Query the base interface of a logical unit.
265	*
266	* @returns VBOX status code.
267	* @param pDevIns The device instance.
268	* @param iLUN The logicial unit to query.
269	* @param ppBase Where to store the pointer to the base interface of the LUN.
270	*
271	* @remarks The device critical section is not entered.
272	*/
273	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
274	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
275	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
276
277	/**
278	* Init complete notification (after ring-0 & RC init since 5.1).
279	*
280	* This can be done to do communication with other devices and other
281	* initialization which requires everything to be in place.
282	*
283	* @returns VBOX status code.
284	* @param pDevIns The device instance.
285	*
286	* @remarks Caller enters the device critical section.
287	*/
288	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
289	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
290	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
291
292
293	/**
294	* The context of a pfnMemSetup call.
295	*/
296	typedef enum PDMDEVMEMSETUPCTX
297	{
298	/** Invalid zero value. */
299	PDMDEVMEMSETUPCTX_INVALID = 0,
300	/** After construction. */
301	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
302	/** After reset. */
303	PDMDEVMEMSETUPCTX_AFTER_RESET,
304	/** Type size hack. */
305	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
306	} PDMDEVMEMSETUPCTX;
307
308
309	/**
310	* PDM Device Registration Structure.
311	*
312	* This structure is used when registering a device from VBoxInitDevices() in HC
313	* Ring-3. PDM will continue use till the VM is terminated.
314	*
315	* @note The first part is the same in every context.
316	*/
317	typedef struct PDMDEVREGR3
318	{
319	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
320	uint32_t u32Version;
321	/** Reserved, must be zero. */
322	uint32_t uReserved0;
323	/** Device name, must match the ring-3 one. */
324	char szName[32];
325	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
326	uint32_t fFlags;
327	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
328	uint32_t fClass;
329	/** Maximum number of instances (per VM). */
330	uint32_t cMaxInstances;
331	/** The shared data structure version number. */
332	uint32_t uSharedVersion;
333	/** Size of the instance data. */
334	uint32_t cbInstanceShared;
335	/** Size of the ring-0 instance data. */
336	uint32_t cbInstanceCC;
337	/** Size of the raw-mode instance data. */
338	uint32_t cbInstanceRC;
339	/** Max number of PCI devices. */
340	uint16_t cMaxPciDevices;
341	/** Max number of MSI-X vectors in any of the PCI devices. */
342	uint16_t cMaxMsixVectors;
343	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
344	* remain unchanged from registration till VM destruction. */
345	const char *pszDescription;
346
347	/** Name of the raw-mode context module (no path).
348	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
349	const char *pszRCMod;
350	/** Name of the ring-0 module (no path).
351	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
352	const char *pszR0Mod;
353
354	/** Construct instance - required. */
355	PFNPDMDEVCONSTRUCT pfnConstruct;
356	/** Destruct instance - optional.
357	* Critical section NOT entered (will be destroyed). */
358	PFNPDMDEVDESTRUCT pfnDestruct;
359	/** Relocation command - optional.
360	* Critical section NOT entered. */
361	PFNPDMDEVRELOCATE pfnRelocate;
362	/**
363	* Memory setup callback.
364	*
365	* @param pDevIns The device instance data.
366	* @param enmCtx Indicates the context of the call.
367	* @remarks The critical section is entered prior to calling this method.
368	*/
369	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
370	/** Power on notification - optional.
371	* Critical section is entered. */
372	PFNPDMDEVPOWERON pfnPowerOn;
373	/** Reset notification - optional.
374	* Critical section is entered. */
375	PFNPDMDEVRESET pfnReset;
376	/** Suspend notification - optional.
377	* Critical section is entered. */
378	PFNPDMDEVSUSPEND pfnSuspend;
379	/** Resume notification - optional.
380	* Critical section is entered. */
381	PFNPDMDEVRESUME pfnResume;
382	/** Attach command - optional.
383	* Critical section is entered. */
384	PFNPDMDEVATTACH pfnAttach;
385	/** Detach notification - optional.
386	* Critical section is entered. */
387	PFNPDMDEVDETACH pfnDetach;
388	/** Query a LUN base interface - optional.
389	* Critical section is NOT entered. */
390	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
391	/** Init complete notification - optional.
392	* Critical section is entered. */
393	PFNPDMDEVINITCOMPLETE pfnInitComplete;
394	/** Power off notification - optional.
395	* Critical section is entered. */
396	PFNPDMDEVPOWEROFF pfnPowerOff;
397	/** Software system reset notification - optional.
398	* Critical section is entered. */
399	PFNPDMDEVSOFTRESET pfnSoftReset;
400
401	/** @name Reserved for future extensions, must be zero.
402	* @{ */
403	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
406	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
407	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
408	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
409	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
410	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
411	/** @} */
412
413	/** Initialization safty marker. */
414	uint32_t u32VersionEnd;
415	} PDMDEVREGR3;
416	/** Pointer to a PDM Device Structure. */
417	typedef PDMDEVREGR3 *PPDMDEVREGR3;
418	/** Const pointer to a PDM Device Structure. */
419	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
420	/** Current DEVREGR3 version number. */
421	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
422
423
424	/** PDM Device Flags.
425	* @{ */
426	/** This flag is used to indicate that the device has a R0 component. */
427	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
428	/** Requires the ring-0 component, ignore configuration values. */
429	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
430	/** Requires the ring-0 component, ignore configuration values. */
431	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
432
433	/** This flag is used to indicate that the device has a RC component. */
434	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
435	/** Requires the raw-mode component, ignore configuration values. */
436	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
437	/** Requires the raw-mode component, ignore configuration values. */
438	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
439
440	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
441	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
442
443	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
444	* The bit count for the current host.
445	* @note Superfluous, but still around for hysterical raisins. */
446	#if HC_ARCH_BITS == 32
447	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
448	#elif HC_ARCH_BITS == 64
449	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
450	#else
451	# error Unsupported HC_ARCH_BITS value.
452	#endif
453	/** The host bit count mask. */
454	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
455
456	/** The device support only 32-bit guests. */
457	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
458	/** The device support only 64-bit guests. */
459	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
460	/** The device support both 32-bit & 64-bit guests. */
461	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
462	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
463	* The guest bit count for the current compilation. */
464	#if GC_ARCH_BITS == 32
465	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
466	#elif GC_ARCH_BITS == 64
467	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
468	#else
469	# error Unsupported GC_ARCH_BITS value.
470	#endif
471	/** The guest bit count mask. */
472	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
473
474	/** A convenience. */
475	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
476
477	/** Indicates that the device needs to be notified before the drivers when suspending. */
478	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
479	/** Indicates that the device needs to be notified before the drivers when powering off. */
480	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
481	/** Indicates that the device needs to be notified before the drivers when resetting. */
482	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
483
484	/** This flag is used to indicate that the device has been converted to the
485	* new device style. */
486	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
487
488	/** @} */
489
490
491	/** PDM Device Classes.
492	* The order is important, lower bit earlier instantiation.
493	* @{ */
494	/** Architecture device. */
495	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
496	/** Architecture BIOS device. */
497	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
498	/** PCI bus brigde. */
499	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
500	/** PCI built-in device (e.g. PCI root complex devices). */
501	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
502	/** Input device (mouse, keyboard, joystick, HID, ...). */
503	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
504	/** Interrupt controller (PIC). */
505	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
506	/** Interval controoler (PIT). */
507	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
508	/** RTC/CMOS. */
509	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
510	/** DMA controller. */
511	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
512	/** VMM Device. */
513	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
514	/** Graphics device, like VGA. */
515	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
516	/** Storage controller device. */
517	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
518	/** Network interface controller. */
519	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
520	/** Audio. */
521	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
522	/** USB HIC. */
523	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
524	/** ACPI. */
525	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
526	/** Serial controller device. */
527	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
528	/** Parallel controller device */
529	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
530	/** Host PCI pass-through device */
531	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
532	/** Misc devices (always last). */
533	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
534	/** @} */
535
536
537	/**
538	* PDM Device Registration Structure, ring-0.
539	*
540	* This structure is used when registering a device from VBoxInitDevices() in HC
541	* Ring-0. PDM will continue use till the VM is terminated.
542	*/
543	typedef struct PDMDEVREGR0
544	{
545	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
546	uint32_t u32Version;
547	/** Reserved, must be zero. */
548	uint32_t uReserved0;
549	/** Device name, must match the ring-3 one. */
550	char szName[32];
551	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
552	uint32_t fFlags;
553	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
554	uint32_t fClass;
555	/** Maximum number of instances (per VM). */
556	uint32_t cMaxInstances;
557	/** The shared data structure version number. */
558	uint32_t uSharedVersion;
559	/** Size of the instance data. */
560	uint32_t cbInstanceShared;
561	/** Size of the ring-0 instance data. */
562	uint32_t cbInstanceCC;
563	/** Size of the raw-mode instance data. */
564	uint32_t cbInstanceRC;
565	/** Max number of PCI devices. */
566	uint16_t cMaxPciDevices;
567	/** Max number of MSI-X vectors in any of the PCI devices. */
568	uint16_t cMaxMsixVectors;
569	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
570	* remain unchanged from registration till VM destruction. */
571	const char *pszDescription;
572
573	/**
574	* Early construction callback (optional).
575	*
576	* This is called right after the device instance structure has been allocated
577	* and before the ring-3 constructor gets called.
578	*
579	* @returns VBox status code.
580	* @param pDevIns The device instance data.
581	* @note The destructure is always called, regardless of the return status.
582	*/
583	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
584
585	/**
586	* Regular construction callback (optional).
587	*
588	* This is called after (or during) the ring-3 constructor.
589	*
590	* @returns VBox status code.
591	* @param pDevIns The device instance data.
592	* @note The destructure is always called, regardless of the return status.
593	*/
594	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
595
596	/**
597	* Destructor (optional).
598	*
599	* This is called after the ring-3 destruction. This is not called if ring-3
600	* fails to trigger it (e.g. process is killed or crashes).
601	*
602	* @param pDevIns The device instance data.
603	*/
604	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
605
606	/**
607	* Final destructor (optional).
608	*
609	* This is called right before the memory is freed, which happens when the
610	* VM/GVM object is destroyed. This is always called.
611	*
612	* @param pDevIns The device instance data.
613	*/
614	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
615
616	/**
617	* Generic request handler (optional).
618	*
619	* @param pDevIns The device instance data.
620	* @param uReq Device specific request.
621	* @param uArg Request argument.
622	*/
623	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
624
625	/** @name Reserved for future extensions, must be zero.
626	* @{ */
627	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
630	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
631	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
632	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
633	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
634	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
635	/** @} */
636
637	/** Initialization safty marker. */
638	uint32_t u32VersionEnd;
639	} PDMDEVREGR0;
640	/** Pointer to a ring-0 PDM device registration structure. */
641	typedef PDMDEVREGR0 *PPDMDEVREGR0;
642	/** Pointer to a const ring-0 PDM device registration structure. */
643	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
644	/** Current DEVREGR0 version number. */
645	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
646
647
648	/**
649	* PDM Device Registration Structure, raw-mode
650	*
651	* At the moment, this structure is mostly here to match the other two contexts.
652	*/
653	typedef struct PDMDEVREGRC
654	{
655	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
656	uint32_t u32Version;
657	/** Reserved, must be zero. */
658	uint32_t uReserved0;
659	/** Device name, must match the ring-3 one. */
660	char szName[32];
661	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
662	uint32_t fFlags;
663	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
664	uint32_t fClass;
665	/** Maximum number of instances (per VM). */
666	uint32_t cMaxInstances;
667	/** The shared data structure version number. */
668	uint32_t uSharedVersion;
669	/** Size of the instance data. */
670	uint32_t cbInstanceShared;
671	/** Size of the ring-0 instance data. */
672	uint32_t cbInstanceCC;
673	/** Size of the raw-mode instance data. */
674	uint32_t cbInstanceRC;
675	/** Max number of PCI devices. */
676	uint16_t cMaxPciDevices;
677	/** Max number of MSI-X vectors in any of the PCI devices. */
678	uint16_t cMaxMsixVectors;
679	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
680	* remain unchanged from registration till VM destruction. */
681	const char *pszDescription;
682
683	/**
684	* Constructor callback.
685	*
686	* This is called much later than both the ring-0 and ring-3 constructors, since
687	* raw-mode v2 require a working VMM to run actual code.
688	*
689	* @returns VBox status code.
690	* @param pDevIns The device instance data.
691	* @note The destructure is always called, regardless of the return status.
692	*/
693	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
694
695	/** @name Reserved for future extensions, must be zero.
696	* @{ */
697	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
700	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
701	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
702	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
703	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
704	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
705	/** @} */
706
707	/** Initialization safty marker. */
708	uint32_t u32VersionEnd;
709	} PDMDEVREGRC;
710	/** Pointer to a raw-mode PDM device registration structure. */
711	typedef PDMDEVREGRC *PPDMDEVREGRC;
712	/** Pointer to a const raw-mode PDM device registration structure. */
713	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
714	/** Current DEVREGRC version number. */
715	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
716
717
718
719	/** @def PDM_DEVREG_VERSION
720	* Current DEVREG version number. */
721	/** @typedef PDMDEVREGR3
722	* A current context PDM device registration structure. */
723	/** @typedef PPDMDEVREGR3
724	* Pointer to a current context PDM device registration structure. */
725	/** @typedef PCPDMDEVREGR3
726	* Pointer to a const current context PDM device registration structure. */
727	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
728	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
729	typedef PDMDEVREGR3 PDMDEVREG;
730	typedef PPDMDEVREGR3 PPDMDEVREG;
731	typedef PCPDMDEVREGR3 PCPDMDEVREG;
732	#elif defined(IN_RING0)
733	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
734	typedef PDMDEVREGR0 PDMDEVREG;
735	typedef PPDMDEVREGR0 PPDMDEVREG;
736	typedef PCPDMDEVREGR0 PCPDMDEVREG;
737	#elif defined(IN_RC)
738	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
739	typedef PDMDEVREGRC PDMDEVREG;
740	typedef PPDMDEVREGRC PPDMDEVREG;
741	typedef PCPDMDEVREGRC PCPDMDEVREG;
742	#else
743	# error "Not IN_RING3, IN_RING0 or IN_RC"
744	#endif
745
746
747	/**
748	* Device registrations for ring-0 modules.
749	*
750	* This structure is used directly and must therefore reside in persistent
751	* memory (i.e. the data section).
752	*/
753	typedef struct PDMDEVMODREGR0
754	{
755	/** The structure version (PDM_DEVMODREGR0_VERSION). */
756	uint32_t u32Version;
757	/** Number of devices in the array papDevRegs points to. */
758	uint32_t cDevRegs;
759	/** Pointer to device registration structures. */
760	PCPDMDEVREGR0 *papDevRegs;
761	/** The ring-0 module handle - PDM internal, fingers off. */
762	void *hMod;
763	/** List entry - PDM internal, fingers off. */
764	RTLISTNODE ListEntry;
765	} PDMDEVMODREGR0;
766	/** Pointer to device registriations for a ring-0 module. */
767	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
768	/** Current PDMDEVMODREGR0 version number. */
769	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
770
771
772	/** @name IRQ Level for use with the *SetIrq APIs.
773	* @{
774	*/
775	/** Assert the IRQ (can assume value 1). */
776	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
777	/** Deassert the IRQ (can assume value 0). */
778	#define PDM_IRQ_LEVEL_LOW 0
779	/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
780	* automatically deasserts it after delivery to the APIC (IOAPIC).
781	* @note Only suitable for edge trigger interrupts. */
782	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
783	/** @} */
784
785	/**
786	* Registration record for MSI/MSI-X emulation.
787	*/
788	typedef struct PDMMSIREG
789	{
790	/** Number of MSI interrupt vectors, 0 if MSI not supported */
791	uint16_t cMsiVectors;
792	/** Offset of MSI capability */
793	uint8_t iMsiCapOffset;
794	/** Offset of next capability to MSI */
795	uint8_t iMsiNextOffset;
796	/** If we support 64-bit MSI addressing */
797	bool fMsi64bit;
798	/** If we do not support per-vector masking */
799	bool fMsiNoMasking;
800
801	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
802	uint16_t cMsixVectors;
803	/** Offset of MSI-X capability */
804	uint8_t iMsixCapOffset;
805	/** Offset of next capability to MSI-X */
806	uint8_t iMsixNextOffset;
807	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
808	uint8_t iMsixBar;
809	} PDMMSIREG;
810	typedef PDMMSIREG *PPDMMSIREG;
811
812	/**
813	* PCI Bus registration structure.
814	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
815	*/
816	typedef struct PDMPCIBUSREGR3
817	{
818	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
819	uint32_t u32Version;
820
821	/**
822	* Registers the device with the default PCI bus.
823	*
824	* @returns VBox status code.
825	* @param pDevIns Device instance of the PCI Bus.
826	* @param pPciDev The PCI device structure.
827	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
828	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
829	* device number (0-31).
830	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
831	* function number (0-7).
832	* @param pszName Device name (static but not unique).
833	*
834	* @remarks Caller enters the PDM critical section.
835	*/
836	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
837	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
838
839	/**
840	* Initialize MSI or MSI-X emulation support in a PCI device.
841	*
842	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
843	* vast majority of device emulation it covers everything necessary. It's
844	* fully automatic, taking care of all BAR and config space requirements,
845	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
846	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
847	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
848	*
849	* A device not using this can still offer MSI/MSI-X. In this case it's
850	* completely up to the device (in the MSI-X case) to create/register the
851	* necessary MMIO BAR, handle all config space/BAR updating and take care
852	* of delivering the interrupts appropriately.
853	*
854	* @returns VBox status code.
855	* @param pDevIns Device instance of the PCI Bus.
856	* @param pPciDev The PCI device structure.
857	* @param pMsiReg MSI emulation registration structure
858	* @remarks Caller enters the PDM critical section.
859	*/
860	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
861
862	/**
863	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
864	*
865	* @returns VBox status code.
866	* @param pDevIns Device instance of the PCI Bus.
867	* @param pPciDev The PCI device structure.
868	* @param iRegion The region number.
869	* @param cbRegion Size of the region.
870	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
871	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
872	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
873	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
874	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
875	* @a fFlags, UINT64_MAX if no handle is passed
876	* (old style).
877	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
878	* is given.
879	* @remarks Caller enters the PDM critical section.
880	*/
881	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
882	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
883	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
884
885	/**
886	* Register PCI configuration space read/write intercept callbacks.
887	*
888	* @param pDevIns Device instance of the PCI Bus.
889	* @param pPciDev The PCI device structure.
890	* @param pfnRead Pointer to the user defined PCI config read function.
891	* @param pfnWrite Pointer to the user defined PCI config write function.
892	* to call default PCI config write function. Can be NULL.
893	* @remarks Caller enters the PDM critical section.
894	* @thread EMT
895	*/
896	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
897	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
898
899	/**
900	* Perform a PCI configuration space write, bypassing interception.
901	*
902	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
903	*
904	* @returns Strict VBox status code (mainly DBGFSTOP).
905	* @param pDevIns Device instance of the PCI Bus.
906	* @param pPciDev The PCI device which config space is being read.
907	* @param uAddress The config space address.
908	* @param cb The size of the read: 1, 2 or 4 bytes.
909	* @param u32Value The value to write.
910	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
911	* that the (root) bus will have done that already.
912	*/
913	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
914	uint32_t uAddress, unsigned cb, uint32_t u32Value));
915
916	/**
917	* Perform a PCI configuration space read, bypassing interception.
918	*
919	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
920	*
921	* @returns Strict VBox status code (mainly DBGFSTOP).
922	* @param pDevIns Device instance of the PCI Bus.
923	* @param pPciDev The PCI device which config space is being read.
924	* @param uAddress The config space address.
925	* @param cb The size of the read: 1, 2 or 4 bytes.
926	* @param pu32Value Where to return the value.
927	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
928	* that the (root) bus will have done that already.
929	*/
930	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
931	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
932
933	/**
934	* Set the IRQ for a PCI device.
935	*
936	* @param pDevIns Device instance of the PCI Bus.
937	* @param pPciDev The PCI device structure.
938	* @param iIrq IRQ number to set.
939	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
940	* @param uTagSrc The IRQ tag and source (for tracing).
941	* @remarks Caller enters the PDM critical section.
942	*/
943	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
944
945	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
946	uint32_t u32EndVersion;
947	} PDMPCIBUSREGR3;
948	/** Pointer to a PCI bus registration structure. */
949	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
950	/** Current PDMPCIBUSREGR3 version number. */
951	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
952
953	/**
954	* PCI Bus registration structure for ring-0.
955	*/
956	typedef struct PDMPCIBUSREGR0
957	{
958	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
959	uint32_t u32Version;
960	/** The PCI bus number (from ring-3 registration). */
961	uint32_t iBus;
962	/**
963	* Set the IRQ for a PCI device.
964	*
965	* @param pDevIns Device instance of the PCI Bus.
966	* @param pPciDev The PCI device structure.
967	* @param iIrq IRQ number to set.
968	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
969	* @param uTagSrc The IRQ tag and source (for tracing).
970	* @remarks Caller enters the PDM critical section.
971	*/
972	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
973	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
974	uint32_t u32EndVersion;
975	} PDMPCIBUSREGR0;
976	/** Pointer to a PCI bus ring-0 registration structure. */
977	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
978	/** Current PDMPCIBUSREGR0 version number. */
979	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
980
981	/**
982	* PCI Bus registration structure for raw-mode.
983	*/
984	typedef struct PDMPCIBUSREGRC
985	{
986	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
987	uint32_t u32Version;
988	/** The PCI bus number (from ring-3 registration). */
989	uint32_t iBus;
990	/**
991	* Set the IRQ for a PCI device.
992	*
993	* @param pDevIns Device instance of the PCI Bus.
994	* @param pPciDev The PCI device structure.
995	* @param iIrq IRQ number to set.
996	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
997	* @param uTagSrc The IRQ tag and source (for tracing).
998	* @remarks Caller enters the PDM critical section.
999	*/
1000	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
1001	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1002	uint32_t u32EndVersion;
1003	} PDMPCIBUSREGRC;
1004	/** Pointer to a PCI bus raw-mode registration structure. */
1005	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1006	/** Current PDMPCIBUSREGRC version number. */
1007	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1008
1009	/** PCI bus registration structure for the current context. */
1010	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1011	/** Pointer to a PCI bus registration structure for the current context. */
1012	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1013	/** PCI bus registration structure version for the current context. */
1014	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1015
1016
1017	/**
1018	* PCI Bus RC helpers.
1019	*/
1020	typedef struct PDMPCIHLPRC
1021	{
1022	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1023	uint32_t u32Version;
1024
1025	/**
1026	* Set an ISA IRQ.
1027	*
1028	* @param pDevIns PCI device instance.
1029	* @param iIrq IRQ number to set.
1030	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1031	* @param uTagSrc The IRQ tag and source (for tracing).
1032	* @thread EMT only.
1033	*/
1034	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1035
1036	/**
1037	* Set an I/O-APIC IRQ.
1038	*
1039	* @param pDevIns PCI device instance.
1040	* @param uBusDevFn The bus:device:function of the device initiating the
1041	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1042	* interrupt.
1043	* @param iIrq IRQ number to set.
1044	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1045	* @param uTagSrc The IRQ tag and source (for tracing).
1046	* @thread EMT only.
1047	*/
1048	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1049
1050	/**
1051	* Send an MSI.
1052	*
1053	* @param pDevIns PCI device instance.
1054	* @param uBusDevFn The bus:device:function of the device initiating the
1055	* MSI. Cannot be NIL_PCIBDF.
1056	* @param pMsi The MSI to send.
1057	* @param uTagSrc The IRQ tag and source (for tracing).
1058	* @thread EMT only.
1059	*/
1060	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1061
1062
1063	/**
1064	* Acquires the PDM lock.
1065	*
1066	* @returns VINF_SUCCESS on success.
1067	* @returns rc if we failed to acquire the lock.
1068	* @param pDevIns The PCI device instance.
1069	* @param rc What to return if we fail to acquire the lock.
1070	*
1071	* @sa PDMCritSectEnter
1072	*/
1073	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1074
1075	/**
1076	* Releases the PDM lock.
1077	*
1078	* @param pDevIns The PCI device instance.
1079	*/
1080	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1081
1082	/**
1083	* Gets a bus by it's PDM ordinal (typically the parent bus).
1084	*
1085	* @returns Pointer to the device instance of the bus.
1086	* @param pDevIns The PCI bus device instance.
1087	* @param idxPdmBus The PDM ordinal value of the bus to get.
1088	*/
1089	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1090
1091	/** Just a safety precaution. */
1092	uint32_t u32TheEnd;
1093	} PDMPCIHLPRC;
1094	/** Pointer to PCI helpers. */
1095	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1096	/** Pointer to const PCI helpers. */
1097	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1098
1099	/** Current PDMPCIHLPRC version number. */
1100	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1101
1102
1103	/**
1104	* PCI Bus R0 helpers.
1105	*/
1106	typedef struct PDMPCIHLPR0
1107	{
1108	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1109	uint32_t u32Version;
1110
1111	/**
1112	* Set an ISA IRQ.
1113	*
1114	* @param pDevIns PCI device instance.
1115	* @param iIrq IRQ number to set.
1116	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1117	* @param uTagSrc The IRQ tag and source (for tracing).
1118	* @thread EMT only.
1119	*/
1120	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1121
1122	/**
1123	* Set an I/O-APIC IRQ.
1124	*
1125	* @param pDevIns PCI device instance.
1126	* @param uBusDevFn The bus:device:function of the device initiating the
1127	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1128	* interrupt.
1129	* @param iIrq IRQ number to set.
1130	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1131	* @param uTagSrc The IRQ tag and source (for tracing).
1132	* @thread EMT only.
1133	*/
1134	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1135
1136	/**
1137	* Send an MSI.
1138	*
1139	* @param pDevIns PCI device instance.
1140	* @param uBusDevFn The bus:device:function of the device initiating the
1141	* MSI. Cannot be NIL_PCIBDF.
1142	* @param pMsi The MSI to send.
1143	* @param uTagSrc The IRQ tag and source (for tracing).
1144	* @thread EMT only.
1145	*/
1146	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1147
1148	/**
1149	* Acquires the PDM lock.
1150	*
1151	* @returns VINF_SUCCESS on success.
1152	* @returns rc if we failed to acquire the lock.
1153	* @param pDevIns The PCI device instance.
1154	* @param rc What to return if we fail to acquire the lock.
1155	*
1156	* @sa PDMCritSectEnter
1157	*/
1158	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1159
1160	/**
1161	* Releases the PDM lock.
1162	*
1163	* @param pDevIns The PCI device instance.
1164	*/
1165	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1166
1167	/**
1168	* Gets a bus by it's PDM ordinal (typically the parent bus).
1169	*
1170	* @returns Pointer to the device instance of the bus.
1171	* @param pDevIns The PCI bus device instance.
1172	* @param idxPdmBus The PDM ordinal value of the bus to get.
1173	*/
1174	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1175
1176	/** Just a safety precaution. */
1177	uint32_t u32TheEnd;
1178	} PDMPCIHLPR0;
1179	/** Pointer to PCI helpers. */
1180	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1181	/** Pointer to const PCI helpers. */
1182	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1183
1184	/** Current PDMPCIHLPR0 version number. */
1185	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1186
1187	/**
1188	* PCI device helpers.
1189	*/
1190	typedef struct PDMPCIHLPR3
1191	{
1192	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1193	uint32_t u32Version;
1194
1195	/**
1196	* Set an ISA IRQ.
1197	*
1198	* @param pDevIns The PCI device instance.
1199	* @param iIrq IRQ number to set.
1200	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1201	* @param uTagSrc The IRQ tag and source (for tracing).
1202	*/
1203	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1204
1205	/**
1206	* Set an I/O-APIC IRQ.
1207	*
1208	* @param pDevIns The PCI device instance.
1209	* @param uBusDevFn The bus:device:function of the device initiating the
1210	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1211	* interrupt.
1212	* @param iIrq IRQ number to set.
1213	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1214	* @param uTagSrc The IRQ tag and source (for tracing).
1215	*/
1216	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1217
1218	/**
1219	* Send an MSI.
1220	*
1221	* @param pDevIns PCI device instance.
1222	* @param uBusDevFn The bus:device:function of the device initiating the
1223	* MSI. Cannot be NIL_PCIBDF.
1224	* @param pMsi The MSI to send.
1225	* @param uTagSrc The IRQ tag and source (for tracing).
1226	*/
1227	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1228
1229	/**
1230	* Acquires the PDM lock.
1231	*
1232	* @returns VINF_SUCCESS on success.
1233	* @returns Fatal error on failure.
1234	* @param pDevIns The PCI device instance.
1235	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1236	*
1237	* @sa PDMCritSectEnter
1238	*/
1239	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1240
1241	/**
1242	* Releases the PDM lock.
1243	*
1244	* @param pDevIns The PCI device instance.
1245	*/
1246	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1247
1248	/**
1249	* Gets a bus by it's PDM ordinal (typically the parent bus).
1250	*
1251	* @returns Pointer to the device instance of the bus.
1252	* @param pDevIns The PCI bus device instance.
1253	* @param idxPdmBus The PDM ordinal value of the bus to get.
1254	*/
1255	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1256
1257	/** Just a safety precaution. */
1258	uint32_t u32TheEnd;
1259	} PDMPCIHLPR3;
1260	/** Pointer to PCI helpers. */
1261	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1262	/** Pointer to const PCI helpers. */
1263	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1264
1265	/** Current PDMPCIHLPR3 version number. */
1266	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1267
1268
1269	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1270	* These flags are used for memory access transactions via the IOMMU interface.
1271	* @{ */
1272	/** Memory read. */
1273	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1274	/** Memory write. */
1275	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1276	/** Valid flag mask. */
1277	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1278	/** @} */
1279
1280	/**
1281	* IOMMU registration structure for ring-0.
1282	*/
1283	typedef struct PDMIOMMUREGR0
1284	{
1285	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1286	* version. */
1287	uint32_t u32Version;
1288	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1289	uint32_t idxIommu;
1290
1291	/**
1292	* Translates the physical address for a memory transaction through the IOMMU.
1293	*
1294	* @returns VBox status code.
1295	* @param pDevIns The IOMMU device instance.
1296	* @param idDevice The device identifier (bus, device, function).
1297	* @param uIova The I/O virtual address being accessed.
1298	* @param cbIova The size of the access.
1299	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1300	* @param pGCPhysSpa Where to store the translated system physical address.
1301	* @param pcbContiguous Where to store the number of contiguous bytes translated
1302	* and permission-checked.
1303	*
1304	* @thread Any.
1305	*/
1306	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1307	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1308
1309	/**
1310	* Translates in bulk physical page addresses for memory transactions through the
1311	* IOMMU.
1312	*
1313	* @returns VBox status code.
1314	* @param pDevIns The IOMMU device instance.
1315	* @param idDevice The device identifier (bus, device, function).
1316	* @param cIovas The number of I/O virtual addresses being accessed.
1317	* @param pauIovas The I/O virtual addresses being accessed.
1318	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1319	* @param paGCPhysSpa Where to store the translated system physical page
1320	* addresses.
1321	*
1322	* @thread Any.
1323	*/
1324	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1325	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1326
1327	/**
1328	* Performs an interrupt remap request through the IOMMU.
1329	*
1330	* @returns VBox status code.
1331	* @param pDevIns The IOMMU device instance.
1332	* @param idDevice The device identifier (bus, device, function).
1333	* @param pMsiIn The source MSI.
1334	* @param pMsiOut Where to store the remapped MSI.
1335	*
1336	* @thread Any.
1337	*/
1338	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1339
1340	/** Just a safety precaution. */
1341	uint32_t u32TheEnd;
1342	} PDMIOMMUREGR0;
1343	/** Pointer to a IOMMU registration structure. */
1344	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1345
1346	/** Current PDMIOMMUREG version number. */
1347	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1348
1349
1350	/**
1351	* IOMMU registration structure for raw-mode.
1352	*/
1353	typedef struct PDMIOMMUREGRC
1354	{
1355	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1356	* version. */
1357	uint32_t u32Version;
1358	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1359	uint32_t idxIommu;
1360
1361	/**
1362	* Translates the physical address for a memory transaction through the IOMMU.
1363	*
1364	* @returns VBox status code.
1365	* @param pDevIns The IOMMU device instance.
1366	* @param idDevice The device identifier (bus, device, function).
1367	* @param uIova The I/O virtual address being accessed.
1368	* @param cbIova The size of the access.
1369	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1370	* @param pGCPhysSpa Where to store the translated system physical address.
1371	* @param pcbContiguous Where to store the number of contiguous bytes translated
1372	* and permission-checked.
1373	*
1374	* @thread Any.
1375	*/
1376	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1377	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1378
1379	/**
1380	* Translates in bulk physical page addresses for memory transactions through the
1381	* IOMMU.
1382	*
1383	* @returns VBox status code.
1384	* @param pDevIns The IOMMU device instance.
1385	* @param idDevice The device identifier (bus, device, function).
1386	* @param cIovas The number of I/O virtual addresses being accessed.
1387	* @param pauIovas The I/O virtual addresses being accessed.
1388	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1389	* @param paGCPhysSpa Where to store the translated system physical page
1390	* addresses.
1391	*
1392	* @thread Any.
1393	*/
1394	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1395	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1396
1397	/**
1398	* Performs an interrupt remap request through the IOMMU.
1399	*
1400	* @returns VBox status code.
1401	* @param pDevIns The IOMMU device instance.
1402	* @param idDevice The device identifier (bus, device, function).
1403	* @param pMsiIn The source MSI.
1404	* @param pMsiOut Where to store the remapped MSI.
1405	*
1406	* @thread Any.
1407	*/
1408	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1409
1410	/** Just a safety precaution. */
1411	uint32_t u32TheEnd;
1412	} PDMIOMMUREGRC;
1413	/** Pointer to a IOMMU registration structure. */
1414	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1415
1416	/** Current PDMIOMMUREG version number. */
1417	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1418
1419
1420	/**
1421	* IOMMU registration structure for ring-3.
1422	*/
1423	typedef struct PDMIOMMUREGR3
1424	{
1425	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1426	* version. */
1427	uint32_t u32Version;
1428	/** Padding. */
1429	uint32_t uPadding0;
1430
1431	/**
1432	* Translates the physical address for a memory transaction through the IOMMU.
1433	*
1434	* @returns VBox status code.
1435	* @param pDevIns The IOMMU device instance.
1436	* @param idDevice The device identifier (bus, device, function).
1437	* @param uIova The I/O virtual address being accessed.
1438	* @param cbIova The size of the access.
1439	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1440	* @param pGCPhysSpa Where to store the translated system physical address.
1441	* @param pcbContiguous Where to store the number of contiguous bytes translated
1442	* and permission-checked.
1443	*
1444	* @thread Any.
1445	*/
1446	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1447	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1448
1449	/**
1450	* Translates in bulk physical page addresses for memory transactions through the
1451	* IOMMU.
1452	*
1453	* @returns VBox status code.
1454	* @param pDevIns The IOMMU device instance.
1455	* @param idDevice The device identifier (bus, device, function).
1456	* @param cIovas The number of I/O virtual addresses being accessed.
1457	* @param pauIovas The I/O virtual addresses being accessed.
1458	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1459	* @param paGCPhysSpa Where to store the translated system physical page
1460	* addresses.
1461	*
1462	* @thread Any.
1463	*/
1464	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1465	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1466
1467	/**
1468	* Performs an interrupt remap request through the IOMMU.
1469	*
1470	* @returns VBox status code.
1471	* @param pDevIns The IOMMU device instance.
1472	* @param idDevice The device identifier (bus, device, function).
1473	* @param pMsiIn The source MSI.
1474	* @param pMsiOut Where to store the remapped MSI.
1475	*
1476	* @thread Any.
1477	*/
1478	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1479
1480	/** Just a safety precaution. */
1481	uint32_t u32TheEnd;
1482	} PDMIOMMUREGR3;
1483	/** Pointer to a IOMMU registration structure. */
1484	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1485
1486	/** Current PDMIOMMUREG version number. */
1487	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1488
1489	/** IOMMU registration structure for the current context. */
1490	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1491	/** Pointer to an IOMMU registration structure for the current context. */
1492	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1493	/** IOMMU registration structure version for the current context. */
1494	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1495
1496
1497	/**
1498	* IOMMU helpers for ring-0.
1499	*/
1500	typedef struct PDMIOMMUHLPR0
1501	{
1502	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1503	uint32_t u32Version;
1504
1505	/**
1506	* Acquires the PDM lock.
1507	*
1508	* @returns VINF_SUCCESS on success.
1509	* @returns rc if we failed to acquire the lock.
1510	* @param pDevIns The PCI device instance.
1511	* @param rc What to return if we fail to acquire the lock.
1512	*
1513	* @sa PDMCritSectEnter
1514	*/
1515	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1516
1517	/**
1518	* Releases the PDM lock.
1519	*
1520	* @param pDevIns The PCI device instance.
1521	*/
1522	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1523
1524	/**
1525	* Check whether the calling thread owns the PDM lock.
1526	*
1527	* @returns @c true if the PDM lock is owned, @c false otherwise.
1528	* @param pDevIns The PCI device instance.
1529	*/
1530	DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1531
1532	/**
1533	* Send an MSI (when generated by the IOMMU device itself).
1534	*
1535	* @param pDevIns PCI device instance.
1536	* @param pMsi The MSI to send.
1537	* @param uTagSrc The IRQ tag and source (for tracing).
1538	*/
1539	DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1540
1541	/** Just a safety precaution. */
1542	uint32_t u32TheEnd;
1543	} PDMIOMMUHLPR0;
1544	/** Pointer to IOMMU helpers for ring-0. */
1545	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1546	/** Pointer to const IOMMU helpers for ring-0. */
1547	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1548
1549	/** Current PDMIOMMUHLPR0 version number. */
1550	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1551
1552
1553	/**
1554	* IOMMU helpers for raw-mode.
1555	*/
1556	typedef struct PDMIOMMUHLPRC
1557	{
1558	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1559	uint32_t u32Version;
1560
1561	/**
1562	* Acquires the PDM lock.
1563	*
1564	* @returns VINF_SUCCESS on success.
1565	* @returns rc if we failed to acquire the lock.
1566	* @param pDevIns The PCI device instance.
1567	* @param rc What to return if we fail to acquire the lock.
1568	*
1569	* @sa PDMCritSectEnter
1570	*/
1571	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1572
1573	/**
1574	* Releases the PDM lock.
1575	*
1576	* @param pDevIns The PCI device instance.
1577	*/
1578	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1579
1580	/**
1581	* Check whether the threads owns the PDM lock.
1582	*
1583	* @returns @c true if the PDM lock is owned, @c false otherwise.
1584	* @param pDevIns The PCI device instance.
1585	*/
1586	DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1587
1588	/**
1589	* Send an MSI (when generated by the IOMMU device itself).
1590	*
1591	* @param pDevIns PCI device instance.
1592	* @param pMsi The MSI to send.
1593	* @param uTagSrc The IRQ tag and source (for tracing).
1594	*/
1595	DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1596
1597	/** Just a safety precaution. */
1598	uint32_t u32TheEnd;
1599	} PDMIOMMUHLPRC;
1600	/** Pointer to IOMMU helpers for raw-mode. */
1601	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1602	/** Pointer to const IOMMU helpers for raw-mode. */
1603	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1604
1605	/** Current PDMIOMMUHLPRC version number. */
1606	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1607
1608
1609	/**
1610	* IOMMU helpers for ring-3.
1611	*/
1612	typedef struct PDMIOMMUHLPR3
1613	{
1614	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1615	uint32_t u32Version;
1616
1617	/**
1618	* Acquires the PDM lock.
1619	*
1620	* @returns VINF_SUCCESS on success.
1621	* @returns rc if we failed to acquire the lock.
1622	* @param pDevIns The PCI device instance.
1623	* @param rc What to return if we fail to acquire the lock.
1624	*
1625	* @sa PDMCritSectEnter
1626	*/
1627	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1628
1629	/**
1630	* Releases the PDM lock.
1631	*
1632	* @param pDevIns The PCI device instance.
1633	*/
1634	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1635
1636	/**
1637	* Check whether the threads owns the PDM lock.
1638	*
1639	* @returns @c true if the PDM lock is owned, @c false otherwise.
1640	* @param pDevIns The PCI device instance.
1641	*/
1642	DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1643
1644	/**
1645	* Send an MSI (when generated by the IOMMU device itself).
1646	*
1647	* @param pDevIns PCI device instance.
1648	* @param pMsi The MSI to send.
1649	* @param uTagSrc The IRQ tag and source (for tracing).
1650	*/
1651	DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1652
1653	/** Just a safety precaution. */
1654	uint32_t u32TheEnd;
1655	} PDMIOMMUHLPR3;
1656	/** Pointer to IOMMU helpers for raw-mode. */
1657	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1658	/** Pointer to const IOMMU helpers for raw-mode. */
1659	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1660
1661	/** Current PDMIOMMUHLPR3 version number. */
1662	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1663
1664
1665	/**
1666	* Programmable Interrupt Controller registration structure (all contexts).
1667	*/
1668	typedef struct PDMPICREG
1669	{
1670	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1671	uint32_t u32Version;
1672
1673	/**
1674	* Set the an IRQ.
1675	*
1676	* @param pDevIns Device instance of the PIC.
1677	* @param iIrq IRQ number to set.
1678	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1679	* @param uTagSrc The IRQ tag and source (for tracing).
1680	* @remarks Caller enters the PDM critical section.
1681	*/
1682	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1683
1684	/**
1685	* Get a pending interrupt.
1686	*
1687	* @returns Pending interrupt number.
1688	* @param pDevIns Device instance of the PIC.
1689	* @param puTagSrc Where to return the IRQ tag and source.
1690	* @remarks Caller enters the PDM critical section.
1691	*/
1692	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1693
1694	/** Just a safety precaution. */
1695	uint32_t u32TheEnd;
1696	} PDMPICREG;
1697	/** Pointer to a PIC registration structure. */
1698	typedef PDMPICREG *PPDMPICREG;
1699
1700	/** Current PDMPICREG version number. */
1701	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1702
1703	/**
1704	* PIC helpers, same in all contexts.
1705	*/
1706	typedef struct PDMPICHLP
1707	{
1708	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1709	uint32_t u32Version;
1710
1711	/**
1712	* Set the interrupt force action flag.
1713	*
1714	* @param pDevIns Device instance of the PIC.
1715	*/
1716	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1717
1718	/**
1719	* Clear the interrupt force action flag.
1720	*
1721	* @param pDevIns Device instance of the PIC.
1722	*/
1723	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1724
1725	/**
1726	* Acquires the PDM lock.
1727	*
1728	* @returns VINF_SUCCESS on success.
1729	* @returns rc if we failed to acquire the lock.
1730	* @param pDevIns The PIC device instance.
1731	* @param rc What to return if we fail to acquire the lock.
1732	*
1733	* @sa PDMCritSectEnter
1734	*/
1735	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1736
1737	/**
1738	* Releases the PDM lock.
1739	*
1740	* @param pDevIns The PIC device instance.
1741	*/
1742	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1743
1744	/** Just a safety precaution. */
1745	uint32_t u32TheEnd;
1746	} PDMPICHLP;
1747	/** Pointer to PIC helpers. */
1748	typedef PDMPICHLP *PPDMPICHLP;
1749	/** Pointer to const PIC helpers. */
1750	typedef const PDMPICHLP *PCPDMPICHLP;
1751
1752	/** Current PDMPICHLP version number. */
1753	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1754
1755
1756	/**
1757	* Firmware registration structure.
1758	*/
1759	typedef struct PDMFWREG
1760	{
1761	/** Struct version+magic number (PDM_FWREG_VERSION). */
1762	uint32_t u32Version;
1763
1764	/**
1765	* Checks whether this is a hard or soft reset.
1766	*
1767	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1768	* is 5, 9 or 0xA.
1769	*
1770	* @returns true if hard reset, false if soft.
1771	* @param pDevIns Device instance of the firmware.
1772	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1773	*/
1774	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1775
1776	/** Just a safety precaution. */
1777	uint32_t u32TheEnd;
1778	} PDMFWREG;
1779	/** Pointer to a FW registration structure. */
1780	typedef PDMFWREG *PPDMFWREG;
1781	/** Pointer to a const FW registration structure. */
1782	typedef PDMFWREG const *PCPDMFWREG;
1783
1784	/** Current PDMFWREG version number. */
1785	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1786
1787	/**
1788	* Firmware R3 helpers.
1789	*/
1790	typedef struct PDMFWHLPR3
1791	{
1792	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1793	uint32_t u32Version;
1794
1795	/** Just a safety precaution. */
1796	uint32_t u32TheEnd;
1797	} PDMFWHLPR3;
1798
1799	/** Pointer to FW R3 helpers. */
1800	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1801	/** Pointer to const FW R3 helpers. */
1802	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1803
1804	/** Current PDMFWHLPR3 version number. */
1805	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1806
1807
1808	/**
1809	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1810	*
1811	* Also used in saved-states, CFGM don't change existing values.
1812	*/
1813	typedef enum PDMAPICMODE
1814	{
1815	/** Invalid 0 entry. */
1816	PDMAPICMODE_INVALID = 0,
1817	/** No APIC. */
1818	PDMAPICMODE_NONE,
1819	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1820	PDMAPICMODE_APIC,
1821	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1822	PDMAPICMODE_X2APIC,
1823	/** The usual 32-bit paranoia. */
1824	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1825	} PDMAPICMODE;
1826
1827	/**
1828	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1829	*/
1830	typedef enum PDMAPICIRQ
1831	{
1832	/** Invalid 0 entry. */
1833	PDMAPICIRQ_INVALID = 0,
1834	/** Normal hardware interrupt. */
1835	PDMAPICIRQ_HARDWARE,
1836	/** NMI. */
1837	PDMAPICIRQ_NMI,
1838	/** SMI. */
1839	PDMAPICIRQ_SMI,
1840	/** ExtINT (HW interrupt via PIC). */
1841	PDMAPICIRQ_EXTINT,
1842	/** Interrupt arrived, needs to be updated to the IRR. */
1843	PDMAPICIRQ_UPDATE_PENDING,
1844	/** The usual 32-bit paranoia. */
1845	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1846	} PDMAPICIRQ;
1847
1848
1849	/**
1850	* I/O APIC registration structure (all contexts).
1851	*/
1852	typedef struct PDMIOAPICREG
1853	{
1854	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1855	uint32_t u32Version;
1856
1857	/**
1858	* Set an IRQ.
1859	*
1860	* @param pDevIns Device instance of the I/O APIC.
1861	* @param uBusDevFn The bus:device:function of the device initiating the
1862	* IRQ. Can be NIL_PCIBDF.
1863	* @param iIrq IRQ number to set.
1864	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1865	* @param uTagSrc The IRQ tag and source (for tracing).
1866	*
1867	* @remarks Caller enters the PDM critical section
1868	* Actually, as per 2018-07-21 this isn't true (bird).
1869	*/
1870	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1871
1872	/**
1873	* Send a MSI.
1874	*
1875	* @param pDevIns Device instance of the I/O APIC.
1876	* @param uBusDevFn The bus:device:function of the device initiating the
1877	* MSI. Cannot be NIL_PCIBDF.
1878	* @param pMsi The MSI to send.
1879	* @param uTagSrc The IRQ tag and source (for tracing).
1880	*
1881	* @remarks Caller enters the PDM critical section
1882	* Actually, as per 2018-07-21 this isn't true (bird).
1883	*/
1884	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1885
1886	/**
1887	* Set the EOI for an interrupt vector.
1888	*
1889	* @param pDevIns Device instance of the I/O APIC.
1890	* @param u8Vector The vector.
1891	*
1892	* @remarks Caller enters the PDM critical section
1893	* Actually, as per 2018-07-21 this isn't true (bird).
1894	*/
1895	DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1896
1897	/** Just a safety precaution. */
1898	uint32_t u32TheEnd;
1899	} PDMIOAPICREG;
1900	/** Pointer to an APIC registration structure. */
1901	typedef PDMIOAPICREG *PPDMIOAPICREG;
1902
1903	/** Current PDMAPICREG version number. */
1904	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1905
1906
1907	/**
1908	* IOAPIC helpers, same in all contexts.
1909	*/
1910	typedef struct PDMIOAPICHLP
1911	{
1912	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1913	uint32_t u32Version;
1914
1915	/**
1916	* Private interface between the IOAPIC and APIC.
1917	*
1918	* @returns status code.
1919	* @param pDevIns Device instance of the IOAPIC.
1920	* @param u8Dest See APIC implementation.
1921	* @param u8DestMode See APIC implementation.
1922	* @param u8DeliveryMode See APIC implementation.
1923	* @param uVector See APIC implementation.
1924	* @param u8Polarity See APIC implementation.
1925	* @param u8TriggerMode See APIC implementation.
1926	* @param uTagSrc The IRQ tag and source (for tracing).
1927	*
1928	* @sa APICBusDeliver()
1929	*/
1930	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1931	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1932
1933	/**
1934	* Acquires the PDM lock.
1935	*
1936	* @returns VINF_SUCCESS on success.
1937	* @returns rc if we failed to acquire the lock.
1938	* @param pDevIns The IOAPIC device instance.
1939	* @param rc What to return if we fail to acquire the lock.
1940	*
1941	* @sa PDMCritSectEnter
1942	*/
1943	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1944
1945	/**
1946	* Releases the PDM lock.
1947	*
1948	* @param pDevIns The IOAPIC device instance.
1949	*/
1950	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1951
1952	/**
1953	* Checks if the calling thread owns the PDM lock.
1954	*
1955	* @param pDevIns The IOAPIC device instance.
1956	*/
1957	DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1958
1959	/**
1960	* Private interface between the IOAPIC and IOMMU.
1961	*
1962	* @returns status code.
1963	* @param pDevIns Device instance of the IOAPIC.
1964	* @param idDevice The device identifier (bus, device, function).
1965	* @param pMsiIn The source MSI.
1966	* @param pMsiOut Where to store the remapped MSI (only updated when
1967	* VINF_SUCCESS is returned).
1968	*/
1969	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1970
1971	/** Just a safety precaution. */
1972	uint32_t u32TheEnd;
1973	} PDMIOAPICHLP;
1974	/** Pointer to IOAPIC helpers. */
1975	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1976	/** Pointer to const IOAPIC helpers. */
1977	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1978
1979	/** Current PDMIOAPICHLP version number. */
1980	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1981
1982
1983	/**
1984	* HPET registration structure.
1985	*/
1986	typedef struct PDMHPETREG
1987	{
1988	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1989	uint32_t u32Version;
1990	} PDMHPETREG;
1991	/** Pointer to an HPET registration structure. */
1992	typedef PDMHPETREG *PPDMHPETREG;
1993
1994	/** Current PDMHPETREG version number. */
1995	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1996
1997	/**
1998	* HPET RC helpers.
1999	*
2000	* @remarks Keep this around in case HPET will need PDM interaction in again RC
2001	* at some later point.
2002	*/
2003	typedef struct PDMHPETHLPRC
2004	{
2005	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
2006	uint32_t u32Version;
2007
2008	/** Just a safety precaution. */
2009	uint32_t u32TheEnd;
2010	} PDMHPETHLPRC;
2011
2012	/** Pointer to HPET RC helpers. */
2013	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
2014	/** Pointer to const HPET RC helpers. */
2015	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
2016
2017	/** Current PDMHPETHLPRC version number. */
2018	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
2019
2020
2021	/**
2022	* HPET R0 helpers.
2023	*
2024	* @remarks Keep this around in case HPET will need PDM interaction in again R0
2025	* at some later point.
2026	*/
2027	typedef struct PDMHPETHLPR0
2028	{
2029	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2030	uint32_t u32Version;
2031
2032	/** Just a safety precaution. */
2033	uint32_t u32TheEnd;
2034	} PDMHPETHLPR0;
2035
2036	/** Pointer to HPET R0 helpers. */
2037	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2038	/** Pointer to const HPET R0 helpers. */
2039	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2040
2041	/** Current PDMHPETHLPR0 version number. */
2042	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2043
2044	/**
2045	* HPET R3 helpers.
2046	*/
2047	typedef struct PDMHPETHLPR3
2048	{
2049	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2050	uint32_t u32Version;
2051
2052	/**
2053	* Set legacy mode on PIT and RTC.
2054	*
2055	* @returns VINF_SUCCESS on success.
2056	* @returns rc if we failed to set legacy mode.
2057	* @param pDevIns Device instance of the HPET.
2058	* @param fActivated Whether legacy mode is activated or deactivated.
2059	*/
2060	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2061
2062
2063	/**
2064	* Set IRQ, bypassing ISA bus override rules.
2065	*
2066	* @returns VINF_SUCCESS on success.
2067	* @returns rc if we failed to set legacy mode.
2068	* @param pDevIns Device instance of the HPET.
2069	* @param iIrq IRQ number to set.
2070	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2071	*/
2072	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2073
2074	/** Just a safety precaution. */
2075	uint32_t u32TheEnd;
2076	} PDMHPETHLPR3;
2077
2078	/** Pointer to HPET R3 helpers. */
2079	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2080	/** Pointer to const HPET R3 helpers. */
2081	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2082
2083	/** Current PDMHPETHLPR3 version number. */
2084	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2085
2086
2087	/**
2088	* Raw PCI device registration structure.
2089	*/
2090	typedef struct PDMPCIRAWREG
2091	{
2092	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2093	uint32_t u32Version;
2094	/** Just a safety precaution. */
2095	uint32_t u32TheEnd;
2096	} PDMPCIRAWREG;
2097	/** Pointer to a raw PCI registration structure. */
2098	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2099
2100	/** Current PDMPCIRAWREG version number. */
2101	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2102
2103	/**
2104	* Raw PCI device raw-mode context helpers.
2105	*/
2106	typedef struct PDMPCIRAWHLPRC
2107	{
2108	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2109	uint32_t u32Version;
2110	/** Just a safety precaution. */
2111	uint32_t u32TheEnd;
2112	} PDMPCIRAWHLPRC;
2113	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2114	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2115	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2116	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2117
2118	/** Current PDMPCIRAWHLPRC version number. */
2119	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2120
2121	/**
2122	* Raw PCI device ring-0 context helpers.
2123	*/
2124	typedef struct PDMPCIRAWHLPR0
2125	{
2126	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2127	uint32_t u32Version;
2128	/** Just a safety precaution. */
2129	uint32_t u32TheEnd;
2130	} PDMPCIRAWHLPR0;
2131	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2132	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2133	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2134	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2135
2136	/** Current PDMPCIRAWHLPR0 version number. */
2137	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2138
2139
2140	/**
2141	* Raw PCI device ring-3 context helpers.
2142	*/
2143	typedef struct PDMPCIRAWHLPR3
2144	{
2145	/** Undefined structure version and magic number. */
2146	uint32_t u32Version;
2147
2148	/**
2149	* Gets the address of the RC raw PCI device helpers.
2150	*
2151	* This should be called at both construction and relocation time to obtain
2152	* the correct address of the RC helpers.
2153	*
2154	* @returns RC pointer to the raw PCI device helpers.
2155	* @param pDevIns Device instance of the raw PCI device.
2156	*/
2157	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2158
2159	/**
2160	* Gets the address of the R0 raw PCI device helpers.
2161	*
2162	* This should be called at both construction and relocation time to obtain
2163	* the correct address of the R0 helpers.
2164	*
2165	* @returns R0 pointer to the raw PCI device helpers.
2166	* @param pDevIns Device instance of the raw PCI device.
2167	*/
2168	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2169
2170	/** Just a safety precaution. */
2171	uint32_t u32TheEnd;
2172	} PDMPCIRAWHLPR3;
2173	/** Pointer to raw PCI R3 helpers. */
2174	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2175	/** Pointer to const raw PCI R3 helpers. */
2176	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2177
2178	/** Current PDMPCIRAWHLPR3 version number. */
2179	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2180
2181
2182	#ifdef IN_RING3
2183
2184	/**
2185	* DMA Transfer Handler.
2186	*
2187	* @returns Number of bytes transferred.
2188	* @param pDevIns The device instance that registered the handler.
2189	* @param pvUser User pointer.
2190	* @param uChannel Channel number.
2191	* @param off DMA position.
2192	* @param cb Block size.
2193	* @remarks The device lock is take before the callback (in fact, the locks of
2194	* DMA devices and the DMA controller itself are taken).
2195	*/
2196	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2197	uint32_t off, uint32_t cb));
2198	/** Pointer to a FNDMATRANSFERHANDLER(). */
2199	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2200
2201	/**
2202	* DMA Controller registration structure.
2203	*/
2204	typedef struct PDMDMAREG
2205	{
2206	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2207	uint32_t u32Version;
2208
2209	/**
2210	* Execute pending transfers.
2211	*
2212	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2213	* @param pDevIns Device instance of the DMAC.
2214	* @remarks No locks held, called on EMT(0) as a form of serialization.
2215	*/
2216	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2217
2218	/**
2219	* Register transfer function for DMA channel.
2220	*
2221	* @param pDevIns Device instance of the DMAC.
2222	* @param uChannel Channel number.
2223	* @param pDevInsHandler The device instance of the device making the
2224	* regstration (will be passed to the callback).
2225	* @param pfnTransferHandler Device specific transfer function.
2226	* @param pvUser User pointer to be passed to the callback.
2227	* @remarks No locks held, called on an EMT.
2228	*/
2229	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2230	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2231
2232	/**
2233	* Read memory
2234	*
2235	* @returns Number of bytes read.
2236	* @param pDevIns Device instance of the DMAC.
2237	* @param uChannel Channel number.
2238	* @param pvBuffer Pointer to target buffer.
2239	* @param off DMA position.
2240	* @param cbBlock Block size.
2241	* @remarks No locks held, called on an EMT.
2242	*/
2243	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2244
2245	/**
2246	* Write memory
2247	*
2248	* @returns Number of bytes written.
2249	* @param pDevIns Device instance of the DMAC.
2250	* @param uChannel Channel number.
2251	* @param pvBuffer Memory to write.
2252	* @param off DMA position.
2253	* @param cbBlock Block size.
2254	* @remarks No locks held, called on an EMT.
2255	*/
2256	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2257
2258	/**
2259	* Set the DREQ line.
2260	*
2261	* @param pDevIns Device instance of the DMAC.
2262	* @param uChannel Channel number.
2263	* @param uLevel Level of the line.
2264	* @remarks No locks held, called on an EMT.
2265	*/
2266	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2267
2268	/**
2269	* Get channel mode
2270	*
2271	* @returns Channel mode.
2272	* @param pDevIns Device instance of the DMAC.
2273	* @param uChannel Channel number.
2274	* @remarks No locks held, called on an EMT.
2275	*/
2276	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2277
2278	} PDMDMACREG;
2279	/** Pointer to a DMAC registration structure. */
2280	typedef PDMDMACREG *PPDMDMACREG;
2281
2282	/** Current PDMDMACREG version number. */
2283	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2284
2285
2286	/**
2287	* DMA Controller device helpers.
2288	*/
2289	typedef struct PDMDMACHLP
2290	{
2291	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2292	uint32_t u32Version;
2293
2294	/* to-be-defined */
2295
2296	} PDMDMACHLP;
2297	/** Pointer to DMAC helpers. */
2298	typedef PDMDMACHLP *PPDMDMACHLP;
2299	/** Pointer to const DMAC helpers. */
2300	typedef const PDMDMACHLP *PCPDMDMACHLP;
2301
2302	/** Current PDMDMACHLP version number. */
2303	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2304
2305	#endif /* IN_RING3 */
2306
2307
2308
2309	/**
2310	* RTC registration structure.
2311	*/
2312	typedef struct PDMRTCREG
2313	{
2314	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2315	uint32_t u32Version;
2316	uint32_t u32Alignment; /*< structure size alignment. /
2317
2318	/**
2319	* Write to a CMOS register and update the checksum if necessary.
2320	*
2321	* @returns VBox status code.
2322	* @param pDevIns Device instance of the RTC.
2323	* @param iReg The CMOS register index.
2324	* @param u8Value The CMOS register value.
2325	* @remarks Caller enters the device critical section.
2326	*/
2327	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2328
2329	/**
2330	* Read a CMOS register.
2331	*
2332	* @returns VBox status code.
2333	* @param pDevIns Device instance of the RTC.
2334	* @param iReg The CMOS register index.
2335	* @param pu8Value Where to store the CMOS register value.
2336	* @remarks Caller enters the device critical section.
2337	*/
2338	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2339
2340	} PDMRTCREG;
2341	/** Pointer to a RTC registration structure. */
2342	typedef PDMRTCREG *PPDMRTCREG;
2343	/** Pointer to a const RTC registration structure. */
2344	typedef const PDMRTCREG *PCPDMRTCREG;
2345
2346	/** Current PDMRTCREG version number. */
2347	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2348
2349
2350	/**
2351	* RTC device helpers.
2352	*/
2353	typedef struct PDMRTCHLP
2354	{
2355	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2356	uint32_t u32Version;
2357
2358	/* to-be-defined */
2359
2360	} PDMRTCHLP;
2361	/** Pointer to RTC helpers. */
2362	typedef PDMRTCHLP *PPDMRTCHLP;
2363	/** Pointer to const RTC helpers. */
2364	typedef const PDMRTCHLP *PCPDMRTCHLP;
2365
2366	/** Current PDMRTCHLP version number. */
2367	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2368
2369
2370
2371	/** @name Flags for PCI I/O region registration
2372	* @{ */
2373	/** No handle is passed. */
2374	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2375	/** An I/O port handle is passed. */
2376	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2377	/** An MMIO range handle is passed. */
2378	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2379	/** An MMIO2 handle is passed. */
2380	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2381	/** Handle type mask. */
2382	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2383	/** New-style (mostly wrt callbacks). */
2384	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2385	/** Mask of valid flags. */
2386	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2387	/** @} */
2388
2389
2390	/** @name Flags for the guest physical read/write helpers
2391	* @{ */
2392	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2393	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2394	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2395	* by the device in any way. */
2396	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2397	/** The data is metadata and being processed by the device in some way. */
2398	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2399	/** @} */
2400
2401
2402	#ifdef IN_RING3
2403
2404	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2405	* @{ */
2406	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2407	* This is handy when registering multiple PCI device functions and the device
2408	* number is left up to the PCI bus. In order to facilitate one PDM device
2409	* instance for each PCI function, this searches earlier PDM device
2410	* instances as well. */
2411	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2412	/** Use the first unused device number (all functions must be unused). */
2413	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2414	/** Use the first unused device function. */
2415	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2416
2417	/** The device and function numbers are not mandatory, just suggestions. */
2418	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2419	/** Registering a PCI bridge device. */
2420	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2421	/** Valid flag mask. */
2422	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2423	/** @} */
2424
2425	/** Current PDMDEVHLPR3 version number. */
2426	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 52, 0)
2427
2428	/**
2429	* PDM Device API.
2430	*/
2431	typedef struct PDMDEVHLPR3
2432	{
2433	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2434	uint32_t u32Version;
2435
2436	/** @name I/O ports
2437	* @{ */
2438	/**
2439	* Creates a range of I/O ports for a device.
2440	*
2441	* The I/O port range must be mapped in a separately call. Any ring-0 and
2442	* raw-mode context callback handlers needs to be set up in the respective
2443	* contexts.
2444	*
2445	* @returns VBox status.
2446	* @param pDevIns The device instance to register the ports with.
2447	* @param cPorts Number of ports to register.
2448	* @param fFlags IOM_IOPORT_F_XXX.
2449	* @param pPciDev The PCI device the range is associated with, if
2450	* applicable.
2451	* @param iPciRegion The PCI device region in the high 16-bit word and
2452	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2453	* @param pfnOut Pointer to function which is gonna handle OUT
2454	* operations. Optional.
2455	* @param pfnIn Pointer to function which is gonna handle IN operations.
2456	* Optional.
2457	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2458	* operations. Optional.
2459	* @param pfnInStr Pointer to function which is gonna handle string IN
2460	* operations. Optional.
2461	* @param pvUser User argument to pass to the callbacks.
2462	* @param pszDesc Pointer to description string. This must not be freed.
2463	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2464	* coverage is allowed. This must not be freed.
2465	* @param phIoPorts Where to return the I/O port range handle.
2466	*
2467	* @remarks Caller enters the device critical section prior to invoking the
2468	* registered callback methods.
2469	*
2470	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2471	* PDMDevHlpIoPortUnmap.
2472	*/
2473	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2474	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2475	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2476	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2477
2478	/**
2479	* Maps an I/O port range.
2480	*
2481	* @returns VBox status.
2482	* @param pDevIns The device instance to register the ports with.
2483	* @param hIoPorts The I/O port range handle.
2484	* @param Port Where to map the range.
2485	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2486	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2487	*/
2488	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2489
2490	/**
2491	* Unmaps an I/O port range.
2492	*
2493	* @returns VBox status.
2494	* @param pDevIns The device instance to register the ports with.
2495	* @param hIoPorts The I/O port range handle.
2496	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2497	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2498	*/
2499	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2500
2501	/**
2502	* Gets the mapping address of the I/O port range @a hIoPorts.
2503	*
2504	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2505	* parameters).
2506	* @param pDevIns The device instance to register the ports with.
2507	* @param hIoPorts The I/O port range handle.
2508	*/
2509	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2510	/** @} */
2511
2512	/** @name MMIO
2513	* @{ */
2514	/**
2515	* Creates a memory mapped I/O (MMIO) region for a device.
2516	*
2517	* The MMIO region must be mapped in a separately call. Any ring-0 and
2518	* raw-mode context callback handlers needs to be set up in the respective
2519	* contexts.
2520	*
2521	* @returns VBox status.
2522	* @param pDevIns The device instance to register the ports with.
2523	* @param cbRegion The size of the region in bytes.
2524	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2525	* @param pPciDev The PCI device the range is associated with, if
2526	* applicable.
2527	* @param iPciRegion The PCI device region in the high 16-bit word and
2528	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2529	* @param pfnWrite Pointer to function which is gonna handle Write
2530	* operations.
2531	* @param pfnRead Pointer to function which is gonna handle Read
2532	* operations.
2533	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2534	* operations. (optional)
2535	* @param pvUser User argument to pass to the callbacks.
2536	* @param pszDesc Pointer to description string. This must not be freed.
2537	* @param phRegion Where to return the MMIO region handle.
2538	*
2539	* @remarks Caller enters the device critical section prior to invoking the
2540	* registered callback methods.
2541	*
2542	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2543	*/
2544	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2545	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2546	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2547	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2548
2549	/**
2550	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2551	*
2552	* @returns VBox status.
2553	* @param pDevIns The device instance the region is associated with.
2554	* @param hRegion The MMIO region handle.
2555	* @param GCPhys Where to map the region.
2556	* @note An MMIO range may overlap with base memory if a lot of RAM is
2557	* configured for the VM, in which case we'll drop the base memory
2558	* pages. Presently we will make no attempt to preserve anything that
2559	* happens to be present in the base memory that is replaced, this is
2560	* technically incorrect but it's just not worth the effort to do
2561	* right, at least not at this point.
2562	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2563	* PDMDevHlpMmioSetUpContext
2564	*/
2565	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2566
2567	/**
2568	* Unmaps a memory mapped I/O (MMIO) region.
2569	*
2570	* @returns VBox status.
2571	* @param pDevIns The device instance the region is associated with.
2572	* @param hRegion The MMIO region handle.
2573	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2574	* PDMDevHlpMmioSetUpContext
2575	*/
2576	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2577
2578	/**
2579	* Reduces the length of a MMIO range.
2580	*
2581	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2582	* only work during saved state restore. It will not call the PCI bus code, as
2583	* that is expected to restore the saved resource configuration.
2584	*
2585	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2586	* called it will only map @a cbRegion bytes and not the value set during
2587	* registration.
2588	*
2589	* @return VBox status code.
2590	* @param pDevIns The device owning the range.
2591	* @param hRegion The MMIO region handle.
2592	* @param cbRegion The new size, must be smaller.
2593	*/
2594	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2595
2596	/**
2597	* Gets the mapping address of the MMIO region @a hRegion.
2598	*
2599	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2600	* @param pDevIns The device instance to register the ports with.
2601	* @param hRegion The MMIO region handle.
2602	*/
2603	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2604	/** @} */
2605
2606	/** @name MMIO2
2607	* @{ */
2608	/**
2609	* Creates a MMIO2 region.
2610	*
2611	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2612	* associated with a device. It is also non-shared memory with a permanent
2613	* ring-3 mapping and page backing (presently).
2614	*
2615	* @returns VBox status.
2616	* @param pDevIns The device instance.
2617	* @param pPciDev The PCI device the region is associated with, or
2618	* NULL if no PCI device association.
2619	* @param iPciRegion The region number. Use the PCI region number as
2620	* this must be known to the PCI bus device too. If
2621	* it's not associated with the PCI device, then
2622	* any number up to UINT8_MAX is fine.
2623	* @param cbRegion The size (in bytes) of the region.
2624	* @param fFlags Reserved for future use, must be zero.
2625	* @param pszDesc Pointer to description string. This must not be
2626	* freed.
2627	* @param ppvMapping Where to store the address of the ring-3 mapping
2628	* of the memory.
2629	* @param phRegion Where to return the MMIO2 region handle.
2630	*
2631	* @thread EMT(0)
2632	*/
2633	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2634	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2635
2636	/**
2637	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2638	*
2639	* Any physical access handlers registered for the region must be deregistered
2640	* before calling this function.
2641	*
2642	* @returns VBox status code.
2643	* @param pDevIns The device instance.
2644	* @param hRegion The MMIO2 region handle.
2645	* @thread EMT.
2646	*/
2647	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2648
2649	/**
2650	* Maps a MMIO2 region (into the guest physical address space).
2651	*
2652	* @returns VBox status.
2653	* @param pDevIns The device instance the region is associated with.
2654	* @param hRegion The MMIO2 region handle.
2655	* @param GCPhys Where to map the region.
2656	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2657	* configured for the VM, in which case we'll drop the base memory
2658	* pages. Presently we will make no attempt to preserve anything that
2659	* happens to be present in the base memory that is replaced, this is
2660	* technically incorrect but it's just not worth the effort to do
2661	* right, at least not at this point.
2662	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2663	*/
2664	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2665
2666	/**
2667	* Unmaps a MMIO2 region.
2668	*
2669	* @returns VBox status.
2670	* @param pDevIns The device instance the region is associated with.
2671	* @param hRegion The MMIO2 region handle.
2672	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2673	*/
2674	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2675
2676	/**
2677	* Reduces the length of a MMIO range.
2678	*
2679	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2680	* only work during saved state restore. It will not call the PCI bus code, as
2681	* that is expected to restore the saved resource configuration.
2682	*
2683	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2684	* called it will only map @a cbRegion bytes and not the value set during
2685	* registration.
2686	*
2687	* @return VBox status code.
2688	* @param pDevIns The device owning the range.
2689	* @param hRegion The MMIO2 region handle.
2690	* @param cbRegion The new size, must be smaller.
2691	*/
2692	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2693
2694	/**
2695	* Gets the mapping address of the MMIO region @a hRegion.
2696	*
2697	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2698	* @param pDevIns The device instance to register the ports with.
2699	* @param hRegion The MMIO2 region handle.
2700	*/
2701	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2702
2703	/**
2704	* Changes the number of an MMIO2 or pre-registered MMIO region.
2705	*
2706	* This should only be used to deal with saved state problems, so there is no
2707	* convenience inline wrapper for this method.
2708	*
2709	* @returns VBox status code.
2710	* @param pDevIns The device instance.
2711	* @param hRegion The MMIO2 region handle.
2712	* @param iNewRegion The new region index.
2713	*
2714	* @sa @bugref{9359}
2715	*/
2716	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2717	/** @} */
2718
2719	/**
2720	* Register a ROM (BIOS) region.
2721	*
2722	* It goes without saying that this is read-only memory. The memory region must be
2723	* in unassigned memory. I.e. from the top of the address space or on the PC in
2724	* the 0xa0000-0xfffff range.
2725	*
2726	* @returns VBox status.
2727	* @param pDevIns The device instance owning the ROM region.
2728	* @param GCPhysStart First physical address in the range.
2729	* Must be page aligned!
2730	* @param cbRange The size of the range (in bytes).
2731	* Must be page aligned!
2732	* @param pvBinary Pointer to the binary data backing the ROM image.
2733	* @param cbBinary The size of the binary pointer. This must
2734	* be equal or smaller than @a cbRange.
2735	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2736	* @param pszDesc Pointer to description string. This must not be freed.
2737	*
2738	* @remark There is no way to remove the rom, automatically on device cleanup or
2739	* manually from the device yet. At present I doubt we need such features...
2740	*/
2741	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2742	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2743
2744	/**
2745	* Changes the protection of shadowed ROM mapping.
2746	*
2747	* This is intented for use by the system BIOS, chipset or device in question to
2748	* change the protection of shadowed ROM code after init and on reset.
2749	*
2750	* @param pDevIns The device instance.
2751	* @param GCPhysStart Where the mapping starts.
2752	* @param cbRange The size of the mapping.
2753	* @param enmProt The new protection type.
2754	*/
2755	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2756
2757	/**
2758	* Register a save state data unit.
2759	*
2760	* @returns VBox status.
2761	* @param pDevIns The device instance.
2762	* @param uVersion Data layout version number.
2763	* @param cbGuess The approximate amount of data in the unit.
2764	* Only for progress indicators.
2765	* @param pszBefore Name of data unit which we should be put in
2766	* front of. Optional (NULL).
2767	*
2768	* @param pfnLivePrep Prepare live save callback, optional.
2769	* @param pfnLiveExec Execute live save callback, optional.
2770	* @param pfnLiveVote Vote live save callback, optional.
2771	*
2772	* @param pfnSavePrep Prepare save callback, optional.
2773	* @param pfnSaveExec Execute save callback, optional.
2774	* @param pfnSaveDone Done save callback, optional.
2775	*
2776	* @param pfnLoadPrep Prepare load callback, optional.
2777	* @param pfnLoadExec Execute load callback, optional.
2778	* @param pfnLoadDone Done load callback, optional.
2779	* @remarks Caller enters the device critical section prior to invoking the
2780	* registered callback methods.
2781	*/
2782	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2783	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2784	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2785	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2786
2787	/** @name Exported SSM Functions
2788	* @{ */
2789	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2790	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2791	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2792	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2793	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2794	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2795	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2796	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2797	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2798	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2799	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2800	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2801	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2802	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2803	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2804	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2805	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2806	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2807	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2808	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2809	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2810	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2811	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2812	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2813	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2814	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2815	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2816	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2817	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2818	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2819	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2820	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2821	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2822	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2823	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2824	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2825	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2826	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2827	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2828	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2829	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2830	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2831	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2832	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2833	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2834	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2835	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2836	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2837	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2838	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2839	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2840	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2841	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2842	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2843	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2844	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2845	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2846	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2847	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2848	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2849	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2850	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2851	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2852	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2853	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2854	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2855	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2856	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2857	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2858	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2859	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2860	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2861	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2862	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2863	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2864	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2865	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2866	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2867	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2868	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2869	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2870	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2871	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2872	/** @} */
2873
2874	/**
2875	* Creates a timer w/ a cross context handle.
2876	*
2877	* @returns VBox status.
2878	* @param pDevIns The device instance.
2879	* @param enmClock The clock to use on this timer.
2880	* @param pfnCallback Callback function.
2881	* @param pvUser User argument for the callback.
2882	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2883	* @param pszDesc Pointer to description string which must stay around
2884	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2885	* @param phTimer Where to store the timer handle on success.
2886	* @remarks Caller enters the device critical section prior to invoking the
2887	* callback.
2888	*/
2889	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2890	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
2891
2892	/** @name Timer handle method wrappers
2893	* @{ */
2894	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2895	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2896	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2897	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2898	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2899	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2900	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2901	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2902	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2903	/** Takes the clock lock then enters the specified critical section. */
2904	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2905	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2906	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2907	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2908	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2909	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2910	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2911	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2912	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2913	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2914	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2915	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2916	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2917	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2918	/** @sa TMR3TimerSkip */
2919	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2920	/** @} */
2921
2922	/**
2923	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2924	*
2925	* @returns pTime.
2926	* @param pDevIns The device instance.
2927	* @param pTime Where to store the time.
2928	*/
2929	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2930
2931	/** @name Exported CFGM Functions.
2932	* @{ */
2933	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2934	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2935	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
2936	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2937	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2938	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
2939	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
2940	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
2941	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2942	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2943	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
2944	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
2945	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
2946	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
2947	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
2948	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
2949	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
2950	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
2951	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
2952	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
2953	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
2954	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
2955	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
2956	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
2957	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
2958	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
2959	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2960	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2961	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
2962	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
2963	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
2964	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
2965	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
2966	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
2967	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
2968	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
2969	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
2970	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
2971	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
2972	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
2973	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
2974	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
2975	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
2976	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
2977	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
2978	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
2979	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
2980	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
2981	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
2982	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
2983	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
2984	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
2985	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
2986	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
2987	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
2988	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
2989	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
2990	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
2991	const char pszValidValues, const char pszValidNodes,
2992	const char *pszWho, uint32_t uInstance));
2993	/** @} */
2994
2995	/**
2996	* Read physical memory.
2997	*
2998	* @returns VINF_SUCCESS (for now).
2999	* @param pDevIns The device instance.
3000	* @param GCPhys Physical address start reading from.
3001	* @param pvBuf Where to put the read bits.
3002	* @param cbRead How many bytes to read.
3003	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3004	* @thread Any thread, but the call may involve the emulation thread.
3005	*/
3006	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3007
3008	/**
3009	* Write to physical memory.
3010	*
3011	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3012	* @param pDevIns The device instance.
3013	* @param GCPhys Physical address to write to.
3014	* @param pvBuf What to write.
3015	* @param cbWrite How many bytes to write.
3016	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3017	* @thread Any thread, but the call may involve the emulation thread.
3018	*/
3019	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3020
3021	/**
3022	* Requests the mapping of a guest page into ring-3.
3023	*
3024	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3025	* release it.
3026	*
3027	* This API will assume your intention is to write to the page, and will
3028	* therefore replace shared and zero pages. If you do not intend to modify the
3029	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3030	*
3031	* @returns VBox status code.
3032	* @retval VINF_SUCCESS on success.
3033	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3034	* backing or if the page has any active access handlers. The caller
3035	* must fall back on using PGMR3PhysWriteExternal.
3036	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3037	*
3038	* @param pDevIns The device instance.
3039	* @param GCPhys The guest physical address of the page that
3040	* should be mapped.
3041	* @param fFlags Flags reserved for future use, MBZ.
3042	* @param ppv Where to store the address corresponding to
3043	* GCPhys.
3044	* @param pLock Where to store the lock information that
3045	* pfnPhysReleasePageMappingLock needs.
3046	*
3047	* @remark Avoid calling this API from within critical sections (other than the
3048	* PGM one) because of the deadlock risk when we have to delegating the
3049	* task to an EMT.
3050	* @thread Any.
3051	*/
3052	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3053	PPGMPAGEMAPLOCK pLock));
3054
3055	/**
3056	* Requests the mapping of a guest page into ring-3, external threads.
3057	*
3058	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3059	* release it.
3060	*
3061	* @returns VBox status code.
3062	* @retval VINF_SUCCESS on success.
3063	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3064	* backing or if the page as an active ALL access handler. The caller
3065	* must fall back on using PGMPhysRead.
3066	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3067	*
3068	* @param pDevIns The device instance.
3069	* @param GCPhys The guest physical address of the page that
3070	* should be mapped.
3071	* @param fFlags Flags reserved for future use, MBZ.
3072	* @param ppv Where to store the address corresponding to
3073	* GCPhys.
3074	* @param pLock Where to store the lock information that
3075	* pfnPhysReleasePageMappingLock needs.
3076	*
3077	* @remark Avoid calling this API from within critical sections.
3078	* @thread Any.
3079	*/
3080	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3081	void const **ppv, PPGMPAGEMAPLOCK pLock));
3082
3083	/**
3084	* Release the mapping of a guest page.
3085	*
3086	* This is the counter part of pfnPhysGCPhys2CCPtr and
3087	* pfnPhysGCPhys2CCPtrReadOnly.
3088	*
3089	* @param pDevIns The device instance.
3090	* @param pLock The lock structure initialized by the mapping
3091	* function.
3092	*/
3093	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3094
3095	/**
3096	* Read guest physical memory by virtual address.
3097	*
3098	* @param pDevIns The device instance.
3099	* @param pvDst Where to put the read bits.
3100	* @param GCVirtSrc Guest virtual address to start reading from.
3101	* @param cb How many bytes to read.
3102	* @thread The emulation thread.
3103	*/
3104	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3105
3106	/**
3107	* Write to guest physical memory by virtual address.
3108	*
3109	* @param pDevIns The device instance.
3110	* @param GCVirtDst Guest virtual address to write to.
3111	* @param pvSrc What to write.
3112	* @param cb How many bytes to write.
3113	* @thread The emulation thread.
3114	*/
3115	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3116
3117	/**
3118	* Convert a guest virtual address to a guest physical address.
3119	*
3120	* @returns VBox status code.
3121	* @param pDevIns The device instance.
3122	* @param GCPtr Guest virtual address.
3123	* @param pGCPhys Where to store the GC physical address
3124	* corresponding to GCPtr.
3125	* @thread The emulation thread.
3126	* @remark Careful with page boundaries.
3127	*/
3128	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3129
3130	/**
3131	* Allocate memory which is associated with current VM instance
3132	* and automatically freed on it's destruction.
3133	*
3134	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3135	* @param pDevIns The device instance.
3136	* @param cb Number of bytes to allocate.
3137	*/
3138	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3139
3140	/**
3141	* Allocate memory which is associated with current VM instance
3142	* and automatically freed on it's destruction. The memory is ZEROed.
3143	*
3144	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3145	* @param pDevIns The device instance.
3146	* @param cb Number of bytes to allocate.
3147	*/
3148	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3149
3150	/**
3151	* Allocating string printf.
3152	*
3153	* @returns Pointer to the string.
3154	* @param pDevIns The device instance.
3155	* @param enmTag The statistics tag.
3156	* @param pszFormat The format string.
3157	* @param va Format arguments.
3158	*/
3159	DECLR3CALLBACKMEMBER(char , pfnMMHeapAPrintfV,(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, va_list va));
3160
3161	/**
3162	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3163	*
3164	* @param pDevIns The device instance.
3165	* @param pv Pointer to the memory to free.
3166	*/
3167	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3168
3169	/**
3170	* Returns the physical RAM size of the VM.
3171	*
3172	* @returns RAM size in bytes.
3173	* @param pDevIns The device instance.
3174	*/
3175	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSize,(PPDMDEVINS pDevIns));
3176
3177	/**
3178	* Returns the physical RAM size of the VM below the 4GB boundary.
3179	*
3180	* @returns RAM size in bytes.
3181	* @param pDevIns The device instance.
3182	*/
3183	DECLR3CALLBACKMEMBER(uint32_t, pfnMMPhysGetRamSizeBelow4GB,(PPDMDEVINS pDevIns));
3184
3185	/**
3186	* Returns the physical RAM size of the VM above the 4GB boundary.
3187	*
3188	* @returns RAM size in bytes.
3189	* @param pDevIns The device instance.
3190	*/
3191	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSizeAbove4GB,(PPDMDEVINS pDevIns));
3192
3193	/**
3194	* Gets the VM state.
3195	*
3196	* @returns VM state.
3197	* @param pDevIns The device instance.
3198	* @thread Any thread (just keep in mind that it's volatile info).
3199	*/
3200	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3201
3202	/**
3203	* Checks if the VM was teleported and hasn't been fully resumed yet.
3204	*
3205	* @returns true / false.
3206	* @param pDevIns The device instance.
3207	* @thread Any thread.
3208	*/
3209	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3210
3211	/**
3212	* Set the VM error message
3213	*
3214	* @returns rc.
3215	* @param pDevIns The device instance.
3216	* @param rc VBox status code.
3217	* @param SRC_POS Use RT_SRC_POS.
3218	* @param pszFormat Error message format string.
3219	* @param va Error message arguments.
3220	*/
3221	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3222	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3223
3224	/**
3225	* Set the VM runtime error message
3226	*
3227	* @returns VBox status code.
3228	* @param pDevIns The device instance.
3229	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3230	* @param pszErrorId Error ID string.
3231	* @param pszFormat Error message format string.
3232	* @param va Error message arguments.
3233	*/
3234	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3235	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3236
3237	/**
3238	* Stops the VM and enters the debugger to look at the guest state.
3239	*
3240	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3241	* invoking this function directly.
3242	*
3243	* @returns VBox status code which must be passed up to the VMM.
3244	* @param pDevIns The device instance.
3245	* @param pszFile Filename of the assertion location.
3246	* @param iLine The linenumber of the assertion location.
3247	* @param pszFunction Function of the assertion location.
3248	* @param pszFormat Message. (optional)
3249	* @param args Message parameters.
3250	*/
3251	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3252	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3253
3254	/**
3255	* Register a info handler with DBGF.
3256	*
3257	* @returns VBox status code.
3258	* @param pDevIns The device instance.
3259	* @param pszName The identifier of the info.
3260	* @param pszDesc The description of the info and any arguments
3261	* the handler may take.
3262	* @param pfnHandler The handler function to be called to display the
3263	* info.
3264	*/
3265	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3266
3267	/**
3268	* Register a info handler with DBGF, argv style.
3269	*
3270	* @returns VBox status code.
3271	* @param pDevIns The device instance.
3272	* @param pszName The identifier of the info.
3273	* @param pszDesc The description of the info and any arguments
3274	* the handler may take.
3275	* @param pfnHandler The handler function to be called to display the
3276	* info.
3277	*/
3278	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3279
3280	/**
3281	* Registers a set of registers for a device.
3282	*
3283	* The @a pvUser argument of the getter and setter callbacks will be
3284	* @a pDevIns. The register names will be prefixed by the device name followed
3285	* immediately by the instance number.
3286	*
3287	* @returns VBox status code.
3288	* @param pDevIns The device instance.
3289	* @param paRegisters The register descriptors.
3290	*
3291	* @remarks The device critical section is NOT entered prior to working the
3292	* callbacks registered via this helper!
3293	*/
3294	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3295
3296	/**
3297	* Gets the trace buffer handle.
3298	*
3299	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3300	* really inteded for direct usage, thus no inline wrapper function.
3301	*
3302	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3303	* @param pDevIns The device instance.
3304	*/
3305	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3306
3307	/**
3308	* Registers a statistics sample.
3309	*
3310	* @param pDevIns Device instance of the DMA.
3311	* @param pvSample Pointer to the sample.
3312	* @param enmType Sample type. This indicates what pvSample is
3313	* pointing at.
3314	* @param pszName Sample name, unix path style. If this does not
3315	* start with a '/', the default prefix will be
3316	* prepended, otherwise it will be used as-is.
3317	* @param enmUnit Sample unit.
3318	* @param pszDesc Sample description.
3319	*/
3320	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3321
3322	/**
3323	* Same as pfnSTAMRegister except that the name is specified in a
3324	* RTStrPrintfV like fashion.
3325	*
3326	* @returns VBox status.
3327	* @param pDevIns Device instance of the DMA.
3328	* @param pvSample Pointer to the sample.
3329	* @param enmType Sample type. This indicates what pvSample is
3330	* pointing at.
3331	* @param enmVisibility Visibility type specifying whether unused
3332	* statistics should be visible or not.
3333	* @param enmUnit Sample unit.
3334	* @param pszDesc Sample description.
3335	* @param pszName Sample name format string, unix path style. If
3336	* this does not start with a '/', the default
3337	* prefix will be prepended, otherwise it will be
3338	* used as-is.
3339	* @param args Arguments to the format string.
3340	*/
3341	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3342	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3343	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3344
3345	/**
3346	* Registers a PCI device with the default PCI bus.
3347	*
3348	* If a PDM device has more than one PCI device, they must be registered in the
3349	* order of PDMDEVINSR3::apPciDevs.
3350	*
3351	* @returns VBox status code.
3352	* @param pDevIns The device instance.
3353	* @param pPciDev The PCI device structure.
3354	* This must be kept in the instance data.
3355	* The PCI configuration must be initialized before registration.
3356	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3357	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3358	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3359	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3360	* device number (0-31). This will be ignored if
3361	* the CFGM configuration contains a PCIDeviceNo
3362	* value.
3363	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3364	* function number (0-7). This will be ignored if
3365	* the CFGM configuration contains a PCIFunctionNo
3366	* value.
3367	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3368	* The pointer is saved, so don't free or changed.
3369	* @note The PCI device configuration is now implicit from the apPciDevs
3370	* index, meaning that the zero'th entry is the primary one and
3371	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3372	*/
3373	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3374	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3375
3376	/**
3377	* Initialize MSI or MSI-X emulation support for the given PCI device.
3378	*
3379	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3380	*
3381	* @returns VBox status code.
3382	* @param pDevIns The device instance.
3383	* @param pPciDev The PCI device. NULL is an alias for the first
3384	* one registered.
3385	* @param pMsiReg MSI emulation registration structure.
3386	*/
3387	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3388
3389	/**
3390	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3391	*
3392	* @returns VBox status code.
3393	* @param pDevIns The device instance.
3394	* @param pPciDev The PCI device structure. If NULL the default
3395	* PCI device for this device instance is used.
3396	* @param iRegion The region number.
3397	* @param cbRegion Size of the region.
3398	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3399	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3400	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3401	* @a fFlags, UINT64_MAX if no handle is passed
3402	* (old style).
3403	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3404	* handle is specified. The callback will be
3405	* invoked holding only the PDM lock. The device
3406	* lock will _not_ be taken (due to lock order).
3407	*/
3408	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3409	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3410	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3411
3412	/**
3413	* Register PCI configuration space read/write callbacks.
3414	*
3415	* @returns VBox status code.
3416	* @param pDevIns The device instance.
3417	* @param pPciDev The PCI device structure. If NULL the default
3418	* PCI device for this device instance is used.
3419	* @param pfnRead Pointer to the user defined PCI config read function.
3420	* to call default PCI config read function. Can be NULL.
3421	* @param pfnWrite Pointer to the user defined PCI config write function.
3422	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3423	* is NOT take because that is very likely be a lock order violation.
3424	* @thread EMT(0)
3425	* @note Only callable during VM creation.
3426	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3427	*/
3428	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3429	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3430
3431	/**
3432	* Perform a PCI configuration space write.
3433	*
3434	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3435	*
3436	* @returns Strict VBox status code (mainly DBGFSTOP).
3437	* @param pDevIns The device instance.
3438	* @param pPciDev The PCI device which config space is being read.
3439	* @param uAddress The config space address.
3440	* @param cb The size of the read: 1, 2 or 4 bytes.
3441	* @param u32Value The value to write.
3442	*/
3443	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3444	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3445
3446	/**
3447	* Perform a PCI configuration space read.
3448	*
3449	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3450	*
3451	* @returns Strict VBox status code (mainly DBGFSTOP).
3452	* @param pDevIns The device instance.
3453	* @param pPciDev The PCI device which config space is being read.
3454	* @param uAddress The config space address.
3455	* @param cb The size of the read: 1, 2 or 4 bytes.
3456	* @param pu32Value Where to return the value.
3457	*/
3458	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3459	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3460
3461	/**
3462	* Bus master physical memory read.
3463	*
3464	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3465	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3466	* @param pDevIns The device instance.
3467	* @param pPciDev The PCI device structure. If NULL the default
3468	* PCI device for this device instance is used.
3469	* @param GCPhys Physical address start reading from.
3470	* @param pvBuf Where to put the read bits.
3471	* @param cbRead How many bytes to read.
3472	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3473	* @thread Any thread, but the call may involve the emulation thread.
3474	*/
3475	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3476
3477	/**
3478	* Bus master physical memory write.
3479	*
3480	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3481	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3482	* @param pDevIns The device instance.
3483	* @param pPciDev The PCI device structure. If NULL the default
3484	* PCI device for this device instance is used.
3485	* @param GCPhys Physical address to write to.
3486	* @param pvBuf What to write.
3487	* @param cbWrite How many bytes to write.
3488	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3489	* @thread Any thread, but the call may involve the emulation thread.
3490	*/
3491	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3492
3493	/**
3494	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3495	* physical memory write operation.
3496	*
3497	* Refer pfnPhysGCPhys2CCPtr() for further details.
3498	*
3499	* @returns VBox status code.
3500	* @param pDevIns The device instance.
3501	* @param pPciDev The PCI device structure. If NULL the default
3502	* PCI device for this device instance is used.
3503	* @param GCPhys The guest physical address of the page that should be
3504	* mapped.
3505	* @param fFlags Flags reserved for future use, MBZ.
3506	* @param ppv Where to store the address corresponding to GCPhys.
3507	* @param pLock Where to store the lock information that
3508	* pfnPhysReleasePageMappingLock needs.
3509	*
3510	* @remarks Avoid calling this API from within critical sections (other than the PGM
3511	* one) because of the deadlock risk when we have to delegating the task to
3512	* an EMT.
3513	* @thread Any.
3514	*/
3515	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3516	void **ppv, PPGMPAGEMAPLOCK pLock));
3517
3518	/**
3519	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3520	* for a bus master physical memory read operation.
3521	*
3522	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3523	*
3524	* @returns VBox status code.
3525	* @param pDevIns The device instance.
3526	* @param pPciDev The PCI device structure. If NULL the default
3527	* PCI device for this device instance is used.
3528	* @param GCPhys The guest physical address of the page that
3529	* should be mapped.
3530	* @param fFlags Flags reserved for future use, MBZ.
3531	* @param ppv Where to store the address corresponding to
3532	* GCPhys.
3533	* @param pLock Where to store the lock information that
3534	* pfnPhysReleasePageMappingLock needs.
3535	*
3536	* @remarks Avoid calling this API from within critical sections.
3537	* @thread Any.
3538	*/
3539	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3540	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3541
3542	/**
3543	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3544	* master physical memory write operation.
3545	*
3546	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3547	* ASAP to release them.
3548	*
3549	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3550	*
3551	* @returns VBox status code.
3552	* @param pDevIns The device instance.
3553	* @param pPciDev The PCI device structure. If NULL the default
3554	* PCI device for this device instance is used.
3555	* @param cPages Number of pages to lock.
3556	* @param paGCPhysPages The guest physical address of the pages that
3557	* should be mapped (@a cPages entries).
3558	* @param fFlags Flags reserved for future use, MBZ.
3559	* @param papvPages Where to store the ring-3 mapping addresses
3560	* corresponding to @a paGCPhysPages.
3561	* @param paLocks Where to store the locking information that
3562	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3563	* in length).
3564	*/
3565	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3566	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3567	PPGMPAGEMAPLOCK paLocks));
3568
3569	/**
3570	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3571	* master physical memory read operation.
3572	*
3573	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3574	* ASAP to release them.
3575	*
3576	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3577	*
3578	* @returns VBox status code.
3579	* @param pDevIns The device instance.
3580	* @param pPciDev The PCI device structure. If NULL the default
3581	* PCI device for this device instance is used.
3582	* @param cPages Number of pages to lock.
3583	* @param paGCPhysPages The guest physical address of the pages that
3584	* should be mapped (@a cPages entries).
3585	* @param fFlags Flags reserved for future use, MBZ.
3586	* @param papvPages Where to store the ring-3 mapping addresses
3587	* corresponding to @a paGCPhysPages.
3588	* @param paLocks Where to store the lock information that
3589	* pfnPhysReleasePageMappingLock needs (@a cPages
3590	* in length).
3591	*/
3592	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3593	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3594	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3595
3596	/**
3597	* Sets the IRQ for the given PCI device.
3598	*
3599	* @param pDevIns The device instance.
3600	* @param pPciDev The PCI device structure. If NULL the default
3601	* PCI device for this device instance is used.
3602	* @param iIrq IRQ number to set.
3603	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3604	* @thread Any thread, but will involve the emulation thread.
3605	*/
3606	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3607
3608	/**
3609	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3610	* the request when not called from EMT.
3611	*
3612	* @param pDevIns The device instance.
3613	* @param pPciDev The PCI device structure. If NULL the default
3614	* PCI device for this device instance is used.
3615	* @param iIrq IRQ number to set.
3616	* @param iLevel IRQ level.
3617	* @thread Any thread, but will involve the emulation thread.
3618	*/
3619	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3620
3621	/**
3622	* Set ISA IRQ for a device.
3623	*
3624	* @param pDevIns The device instance.
3625	* @param iIrq IRQ number to set.
3626	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3627	* @thread Any thread, but will involve the emulation thread.
3628	*/
3629	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3630
3631	/**
3632	* Set the ISA IRQ for a device, but don't wait for EMT to process
3633	* the request when not called from EMT.
3634	*
3635	* @param pDevIns The device instance.
3636	* @param iIrq IRQ number to set.
3637	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3638	* @thread Any thread, but will involve the emulation thread.
3639	*/
3640	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3641
3642	/**
3643	* Attaches a driver (chain) to the device.
3644	*
3645	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3646	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3647	*
3648	* @returns VBox status code.
3649	* @param pDevIns The device instance.
3650	* @param iLun The logical unit to attach.
3651	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3652	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3653	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3654	* for the live of the device instance.
3655	*/
3656	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3657	PPDMIBASE ppBaseInterface, const char pszDesc));
3658
3659	/**
3660	* Detaches an attached driver (chain) from the device again.
3661	*
3662	* @returns VBox status code.
3663	* @param pDevIns The device instance.
3664	* @param pDrvIns The driver instance to detach.
3665	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3666	*/
3667	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3668
3669	/**
3670	* Reconfigures the driver chain for a LUN, detaching any driver currently
3671	* present there.
3672	*
3673	* Caller will have attach it, of course.
3674	*
3675	* @returns VBox status code.
3676	* @param pDevIns The device instance.
3677	* @param iLun The logical unit to reconfigure.
3678	* @param cDepth The depth of the driver chain. Determins the
3679	* size of @a papszDrivers and @a papConfigs.
3680	* @param papszDrivers The names of the drivers to configure in the
3681	* chain, first entry is the one immediately
3682	* below the device/LUN
3683	* @param papConfigs The configurations for each of the drivers
3684	* in @a papszDrivers array. NULL entries
3685	* corresponds to empty 'Config' nodes. This
3686	* function will take ownership of non-NULL
3687	* CFGM sub-trees and set the array member to
3688	* NULL, so the caller can do cleanups on
3689	* failure. This parameter is optional.
3690	* @param fFlags Reserved, MBZ.
3691	*/
3692	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3693	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3694
3695	/** @name Exported PDM Queue Functions
3696	* @{ */
3697	/**
3698	* Create a queue.
3699	*
3700	* @returns VBox status code.
3701	* @param pDevIns The device instance.
3702	* @param cbItem The size of a queue item.
3703	* @param cItems The number of items in the queue.
3704	* @param cMilliesInterval The number of milliseconds between polling the queue.
3705	* If 0 then the emulation thread will be notified whenever an item arrives.
3706	* @param pfnCallback The consumer function.
3707	* @param fRZEnabled Set if the queue should work in RC and R0.
3708	* @param pszName The queue base name. The instance number will be
3709	* appended automatically.
3710	* @param phQueue Where to store the queue handle on success.
3711	* @thread EMT(0)
3712	* @remarks The device critical section will NOT be entered before calling the
3713	* callback. No locks will be held, but for now it's safe to assume
3714	* that only one EMT will do queue callbacks at any one time.
3715	*/
3716	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3717	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3718	PDMQUEUEHANDLE *phQueue));
3719
3720	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3721	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3722	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3723	/** @} */
3724
3725	/** @name PDM Task
3726	* @{ */
3727	/**
3728	* Create an asynchronous ring-3 task.
3729	*
3730	* @returns VBox status code.
3731	* @param pDevIns The device instance.
3732	* @param fFlags PDMTASK_F_XXX
3733	* @param pszName The function name or similar. Used for statistics,
3734	* so no slashes.
3735	* @param pfnCallback The task function.
3736	* @param pvUser User argument for the task function.
3737	* @param phTask Where to return the task handle.
3738	* @thread EMT(0)
3739	*/
3740	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3741	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3742	/**
3743	* Triggers the running the given task.
3744	*
3745	* @returns VBox status code.
3746	* @retval VINF_ALREADY_POSTED is the task is already pending.
3747	* @param pDevIns The device instance.
3748	* @param hTask The task to trigger.
3749	* @thread Any thread.
3750	*/
3751	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3752	/** @} */
3753
3754	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3755	* These semaphores can be signalled from ring-0.
3756	* @{ */
3757	/** @sa SUPSemEventCreate */
3758	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3759	/** @sa SUPSemEventClose */
3760	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3761	/** @sa SUPSemEventSignal */
3762	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3763	/** @sa SUPSemEventWaitNoResume */
3764	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3765	/** @sa SUPSemEventWaitNsAbsIntr */
3766	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3767	/** @sa SUPSemEventWaitNsRelIntr */
3768	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3769	/** @sa SUPSemEventGetResolution */
3770	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3771	/** @} */
3772
3773	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3774	* These semaphores can be signalled from ring-0.
3775	* @{ */
3776	/** @sa SUPSemEventMultiCreate */
3777	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3778	/** @sa SUPSemEventMultiClose */
3779	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3780	/** @sa SUPSemEventMultiSignal */
3781	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3782	/** @sa SUPSemEventMultiReset */
3783	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3784	/** @sa SUPSemEventMultiWaitNoResume */
3785	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3786	/** @sa SUPSemEventMultiWaitNsAbsIntr */
3787	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3788	/** @sa SUPSemEventMultiWaitNsRelIntr */
3789	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3790	/** @sa SUPSemEventMultiGetResolution */
3791	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3792	/** @} */
3793
3794	/**
3795	* Initializes a PDM critical section.
3796	*
3797	* The PDM critical sections are derived from the IPRT critical sections, but
3798	* works in RC and R0 as well.
3799	*
3800	* @returns VBox status code.
3801	* @param pDevIns The device instance.
3802	* @param pCritSect Pointer to the critical section.
3803	* @param SRC_POS Use RT_SRC_POS.
3804	* @param pszNameFmt Format string for naming the critical section.
3805	* For statistics and lock validation.
3806	* @param va Arguments for the format string.
3807	*/
3808	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3809	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3810
3811	/**
3812	* Gets the NOP critical section.
3813	*
3814	* @returns The ring-3 address of the NOP critical section.
3815	* @param pDevIns The device instance.
3816	*/
3817	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3818
3819	/**
3820	* Changes the device level critical section from the automatically created
3821	* default to one desired by the device constructor.
3822	*
3823	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
3824	* the additional contexts.
3825	*
3826	* @returns VBox status code.
3827	* @param pDevIns The device instance.
3828	* @param pCritSect The critical section to use. NULL is not
3829	* valid, instead use the NOP critical
3830	* section.
3831	*/
3832	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3833
3834	/** @name Exported PDM Critical Section Functions
3835	* @{ */
3836	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3837	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3838	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3839	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3840	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3841	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3842	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3843	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3844	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3845	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3846	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3847	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3848	/** @} */
3849
3850	/** @name Exported PDM Read/Write Critical Section Functions
3851	* @{ */
3852	DECLR3CALLBACKMEMBER(int, pfnCritSectRwInit,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
3853	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3854	DECLR3CALLBACKMEMBER(int, pfnCritSectRwDelete,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3855
3856	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
3857	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3858	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3859	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3860	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3861
3862	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
3863	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3864	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3865	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3866	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3867
3868	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3869	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
3870	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3871	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3872	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3873	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3874	/** @} */
3875
3876	/**
3877	* Creates a PDM thread.
3878	*
3879	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3880	* resuming, and destroying the thread as the VM state changes.
3881	*
3882	* @returns VBox status code.
3883	* @param pDevIns The device instance.
3884	* @param ppThread Where to store the thread 'handle'.
3885	* @param pvUser The user argument to the thread function.
3886	* @param pfnThread The thread function.
3887	* @param pfnWakeup The wakup callback. This is called on the EMT
3888	* thread when a state change is pending.
3889	* @param cbStack See RTThreadCreate.
3890	* @param enmType See RTThreadCreate.
3891	* @param pszName See RTThreadCreate.
3892	* @remarks The device critical section will NOT be entered prior to invoking
3893	* the function pointers.
3894	*/
3895	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3896	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3897
3898	/** @name Exported PDM Thread Functions
3899	* @{ */
3900	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3901	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3902	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3903	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3904	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3905	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3906	/** @} */
3907
3908	/**
3909	* Set up asynchronous handling of a suspend, reset or power off notification.
3910	*
3911	* This shall only be called when getting the notification. It must be called
3912	* for each one.
3913	*
3914	* @returns VBox status code.
3915	* @param pDevIns The device instance.
3916	* @param pfnAsyncNotify The callback.
3917	* @thread EMT(0)
3918	* @remarks The caller will enter the device critical section prior to invoking
3919	* the callback.
3920	*/
3921	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3922
3923	/**
3924	* Notify EMT(0) that the device has completed the asynchronous notification
3925	* handling.
3926	*
3927	* This can be called at any time, spurious calls will simply be ignored.
3928	*
3929	* @param pDevIns The device instance.
3930	* @thread Any
3931	*/
3932	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
3933
3934	/**
3935	* Register the RTC device.
3936	*
3937	* @returns VBox status code.
3938	* @param pDevIns The device instance.
3939	* @param pRtcReg Pointer to a RTC registration structure.
3940	* @param ppRtcHlp Where to store the pointer to the helper
3941	* functions.
3942	*/
3943	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
3944
3945	/**
3946	* Register a PCI Bus.
3947	*
3948	* @returns VBox status code, but the positive values 0..31 are used to indicate
3949	* bus number rather than informational status codes.
3950	* @param pDevIns The device instance.
3951	* @param pPciBusReg Pointer to PCI bus registration structure.
3952	* @param ppPciHlp Where to store the pointer to the PCI Bus
3953	* helpers.
3954	* @param piBus Where to return the PDM bus number. Optional.
3955	*/
3956	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
3957	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
3958
3959	/**
3960	* Register the IOMMU device.
3961	*
3962	* @returns VBox status code.
3963	* @param pDevIns The device instance.
3964	* @param pIommuReg Pointer to a IOMMU registration structure.
3965	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
3966	* helpers.
3967	* @param pidxIommu Where to return the IOMMU index. Optional.
3968	*/
3969	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
3970	uint32_t *pidxIommu));
3971
3972	/**
3973	* Register the PIC device.
3974	*
3975	* @returns VBox status code.
3976	* @param pDevIns The device instance.
3977	* @param pPicReg Pointer to a PIC registration structure.
3978	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
3979	* helpers.
3980	* @sa PDMDevHlpPICSetUpContext
3981	*/
3982	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
3983
3984	/**
3985	* Register the APIC device.
3986	*
3987	* @returns VBox status code.
3988	* @param pDevIns The device instance.
3989	*/
3990	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
3991
3992	/**
3993	* Register the I/O APIC device.
3994	*
3995	* @returns VBox status code.
3996	* @param pDevIns The device instance.
3997	* @param pIoApicReg Pointer to a I/O APIC registration structure.
3998	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
3999	* helpers.
4000	*/
4001	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4002
4003	/**
4004	* Register the HPET device.
4005	*
4006	* @returns VBox status code.
4007	* @param pDevIns The device instance.
4008	* @param pHpetReg Pointer to a HPET registration structure.
4009	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4010	* helpers.
4011	*/
4012	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4013
4014	/**
4015	* Register a raw PCI device.
4016	*
4017	* @returns VBox status code.
4018	* @param pDevIns The device instance.
4019	* @param pPciRawReg Pointer to a raw PCI registration structure.
4020	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4021	* device helpers.
4022	*/
4023	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4024
4025	/**
4026	* Register the DMA device.
4027	*
4028	* @returns VBox status code.
4029	* @param pDevIns The device instance.
4030	* @param pDmacReg Pointer to a DMAC registration structure.
4031	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4032	*/
4033	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4034
4035	/**
4036	* Register transfer function for DMA channel.
4037	*
4038	* @returns VBox status code.
4039	* @param pDevIns The device instance.
4040	* @param uChannel Channel number.
4041	* @param pfnTransferHandler Device specific transfer callback function.
4042	* @param pvUser User pointer to pass to the callback.
4043	* @thread EMT
4044	*/
4045	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4046
4047	/**
4048	* Read memory.
4049	*
4050	* @returns VBox status code.
4051	* @param pDevIns The device instance.
4052	* @param uChannel Channel number.
4053	* @param pvBuffer Pointer to target buffer.
4054	* @param off DMA position.
4055	* @param cbBlock Block size.
4056	* @param pcbRead Where to store the number of bytes which was
4057	* read. optional.
4058	* @thread EMT
4059	*/
4060	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4061
4062	/**
4063	* Write memory.
4064	*
4065	* @returns VBox status code.
4066	* @param pDevIns The device instance.
4067	* @param uChannel Channel number.
4068	* @param pvBuffer Memory to write.
4069	* @param off DMA position.
4070	* @param cbBlock Block size.
4071	* @param pcbWritten Where to store the number of bytes which was
4072	* written. optional.
4073	* @thread EMT
4074	*/
4075	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4076
4077	/**
4078	* Set the DREQ line.
4079	*
4080	* @returns VBox status code.
4081	* @param pDevIns Device instance.
4082	* @param uChannel Channel number.
4083	* @param uLevel Level of the line.
4084	* @thread EMT
4085	*/
4086	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4087
4088	/**
4089	* Get channel mode.
4090	*
4091	* @returns Channel mode. See specs.
4092	* @param pDevIns The device instance.
4093	* @param uChannel Channel number.
4094	* @thread EMT
4095	*/
4096	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4097
4098	/**
4099	* Schedule DMA execution.
4100	*
4101	* @param pDevIns The device instance.
4102	* @thread Any thread.
4103	*/
4104	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4105
4106	/**
4107	* Write CMOS value and update the checksum(s).
4108	*
4109	* @returns VBox status code.
4110	* @param pDevIns The device instance.
4111	* @param iReg The CMOS register index.
4112	* @param u8Value The CMOS register value.
4113	* @thread EMT
4114	*/
4115	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4116
4117	/**
4118	* Read CMOS value.
4119	*
4120	* @returns VBox status code.
4121	* @param pDevIns The device instance.
4122	* @param iReg The CMOS register index.
4123	* @param pu8Value Where to store the CMOS register value.
4124	* @thread EMT
4125	*/
4126	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4127
4128	/**
4129	* Assert that the current thread is the emulation thread.
4130	*
4131	* @returns True if correct.
4132	* @returns False if wrong.
4133	* @param pDevIns The device instance.
4134	* @param pszFile Filename of the assertion location.
4135	* @param iLine The linenumber of the assertion location.
4136	* @param pszFunction Function of the assertion location.
4137	*/
4138	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4139
4140	/**
4141	* Assert that the current thread is NOT the emulation thread.
4142	*
4143	* @returns True if correct.
4144	* @returns False if wrong.
4145	* @param pDevIns The device instance.
4146	* @param pszFile Filename of the assertion location.
4147	* @param iLine The linenumber of the assertion location.
4148	* @param pszFunction Function of the assertion location.
4149	*/
4150	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4151
4152	/**
4153	* Resolves the symbol for a raw-mode context interface.
4154	*
4155	* @returns VBox status code.
4156	* @param pDevIns The device instance.
4157	* @param pvInterface The interface structure.
4158	* @param cbInterface The size of the interface structure.
4159	* @param pszSymPrefix What to prefix the symbols in the list with
4160	* before resolving them. This must start with
4161	* 'dev' and contain the driver name.
4162	* @param pszSymList List of symbols corresponding to the interface.
4163	* There is generally a there is generally a define
4164	* holding this list associated with the interface
4165	* definition (INTERFACE_SYM_LIST). For more
4166	* details see PDMR3LdrGetInterfaceSymbols.
4167	* @thread EMT
4168	*/
4169	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4170	const char pszSymPrefix, const char pszSymList));
4171
4172	/**
4173	* Resolves the symbol for a ring-0 context interface.
4174	*
4175	* @returns VBox status code.
4176	* @param pDevIns The device instance.
4177	* @param pvInterface The interface structure.
4178	* @param cbInterface The size of the interface structure.
4179	* @param pszSymPrefix What to prefix the symbols in the list with
4180	* before resolving them. This must start with
4181	* 'dev' and contain the driver name.
4182	* @param pszSymList List of symbols corresponding to the interface.
4183	* There is generally a there is generally a define
4184	* holding this list associated with the interface
4185	* definition (INTERFACE_SYM_LIST). For more
4186	* details see PDMR3LdrGetInterfaceSymbols.
4187	* @thread EMT
4188	*/
4189	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4190	const char pszSymPrefix, const char pszSymList));
4191
4192	/**
4193	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4194	*
4195	* @returns VBox status code.
4196	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4197	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4198	*
4199	* @param pDevIns The device instance.
4200	* @param uOperation The operation to perform.
4201	* @param u64Arg 64-bit integer argument.
4202	* @thread EMT
4203	*/
4204	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4205
4206	/**
4207	* Gets the reason for the most recent VM suspend.
4208	*
4209	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4210	* suspend has been made or if the pDevIns is invalid.
4211	* @param pDevIns The device instance.
4212	*/
4213	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4214
4215	/**
4216	* Gets the reason for the most recent VM resume.
4217	*
4218	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4219	* resume has been made or if the pDevIns is invalid.
4220	* @param pDevIns The device instance.
4221	*/
4222	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4223
4224	/**
4225	* Requests the mapping of multiple guest page into ring-3.
4226	*
4227	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4228	* ASAP to release them.
4229	*
4230	* This API will assume your intention is to write to the pages, and will
4231	* therefore replace shared and zero pages. If you do not intend to modify the
4232	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4233	*
4234	* @returns VBox status code.
4235	* @retval VINF_SUCCESS on success.
4236	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4237	* backing or if any of the pages the page has any active access
4238	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4239	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4240	* an invalid physical address.
4241	*
4242	* @param pDevIns The device instance.
4243	* @param cPages Number of pages to lock.
4244	* @param paGCPhysPages The guest physical address of the pages that
4245	* should be mapped (@a cPages entries).
4246	* @param fFlags Flags reserved for future use, MBZ.
4247	* @param papvPages Where to store the ring-3 mapping addresses
4248	* corresponding to @a paGCPhysPages.
4249	* @param paLocks Where to store the locking information that
4250	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4251	* in length).
4252	*
4253	* @remark Avoid calling this API from within critical sections (other than the
4254	* PGM one) because of the deadlock risk when we have to delegating the
4255	* task to an EMT.
4256	* @thread Any.
4257	* @since 6.0.6
4258	*/
4259	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4260	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4261
4262	/**
4263	* Requests the mapping of multiple guest page into ring-3, for reading only.
4264	*
4265	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4266	* ASAP to release them.
4267	*
4268	* @returns VBox status code.
4269	* @retval VINF_SUCCESS on success.
4270	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4271	* backing or if any of the pages the page has an active ALL access
4272	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4273	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4274	* an invalid physical address.
4275	*
4276	* @param pDevIns The device instance.
4277	* @param cPages Number of pages to lock.
4278	* @param paGCPhysPages The guest physical address of the pages that
4279	* should be mapped (@a cPages entries).
4280	* @param fFlags Flags reserved for future use, MBZ.
4281	* @param papvPages Where to store the ring-3 mapping addresses
4282	* corresponding to @a paGCPhysPages.
4283	* @param paLocks Where to store the lock information that
4284	* pfnPhysReleasePageMappingLock needs (@a cPages
4285	* in length).
4286	*
4287	* @remark Avoid calling this API from within critical sections.
4288	* @thread Any.
4289	* @since 6.0.6
4290	*/
4291	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4292	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4293
4294	/**
4295	* Release the mappings of multiple guest pages.
4296	*
4297	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4298	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4299	*
4300	* @param pDevIns The device instance.
4301	* @param cPages Number of pages to unlock.
4302	* @param paLocks The lock structures initialized by the mapping
4303	* function (@a cPages in length).
4304	* @thread Any.
4305	* @since 6.0.6
4306	*/
4307	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4308
4309	/**
4310	* Returns the micro architecture used for the guest.
4311	*
4312	* @returns CPU micro architecture enum.
4313	* @param pDevIns The device instance.
4314	*/
4315	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4316
4317	/**
4318	* Get the number of physical and linear address bits supported by the guest.
4319	*
4320	* @param pDevIns The device instance.
4321	* @param pcPhysAddrWidth Where to store the number of physical address bits
4322	* supported by the guest.
4323	* @param pcLinearAddrWidth Where to store the number of linear address bits
4324	* supported by the guest.
4325	*/
4326	DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4327	uint8_t *pcLinearAddrWidth));
4328
4329	/** Space reserved for future members.
4330	* @{ */
4331	/**
4332	* Deregister zero or more samples given their name prefix.
4333	*
4334	* @returns VBox status code.
4335	* @param pDevIns The device instance.
4336	* @param pszPrefix The name prefix of the samples to remove. If this does
4337	* not start with a '/', the default prefix will be
4338	* prepended, otherwise it will be used as-is.
4339	*/
4340	DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4341	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4342	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4343	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4344	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4345	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4346	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4347	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4348	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4349	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4350	/** @} */
4351
4352
4353	/** API available to trusted devices only.
4354	*
4355	* These APIs are providing unrestricted access to the guest and the VM,
4356	* or they are interacting intimately with PDM.
4357	*
4358	* @{
4359	*/
4360
4361	/**
4362	* Gets the user mode VM handle. Restricted API.
4363	*
4364	* @returns User mode VM Handle.
4365	* @param pDevIns The device instance.
4366	*/
4367	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4368
4369	/**
4370	* Gets the global VM handle. Restricted API.
4371	*
4372	* @returns VM Handle.
4373	* @param pDevIns The device instance.
4374	*/
4375	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4376
4377	/**
4378	* Gets the VMCPU handle. Restricted API.
4379	*
4380	* @returns VMCPU Handle.
4381	* @param pDevIns The device instance.
4382	*/
4383	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4384
4385	/**
4386	* The the VM CPU ID of the current thread (restricted API).
4387	*
4388	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4389	* @param pDevIns The device instance.
4390	*/
4391	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4392
4393	/**
4394	* Registers the VMM device heap or notifies about mapping/unmapping.
4395	*
4396	* This interface serves three purposes:
4397	*
4398	* -# Register the VMM device heap during device construction
4399	* for the HM to use.
4400	* -# Notify PDM/HM that it's mapped into guest address
4401	* space (i.e. usable).
4402	* -# Notify PDM/HM that it is being unmapped from the guest
4403	* address space (i.e. not usable).
4404	*
4405	* @returns VBox status code.
4406	* @param pDevIns The device instance.
4407	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4408	* not mapped.
4409	* @param pvHeap Ring 3 heap pointer.
4410	* @param cbHeap Size of the heap.
4411	* @thread EMT.
4412	*/
4413	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4414
4415	/**
4416	* Registers the firmware (BIOS, EFI) device with PDM.
4417	*
4418	* The firmware provides a callback table and gets a special PDM helper table.
4419	* There can only be one firmware device for a VM.
4420	*
4421	* @returns VBox status code.
4422	* @param pDevIns The device instance.
4423	* @param pFwReg Firmware registration structure.
4424	* @param ppFwHlp Where to return the firmware helper structure.
4425	* @remarks Only valid during device construction.
4426	* @thread EMT(0)
4427	*/
4428	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4429
4430	/**
4431	* Resets the VM.
4432	*
4433	* @returns The appropriate VBox status code to pass around on reset.
4434	* @param pDevIns The device instance.
4435	* @param fFlags PDMVMRESET_F_XXX flags.
4436	* @thread The emulation thread.
4437	*/
4438	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4439
4440	/**
4441	* Suspends the VM.
4442	*
4443	* @returns The appropriate VBox status code to pass around on suspend.
4444	* @param pDevIns The device instance.
4445	* @thread The emulation thread.
4446	*/
4447	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4448
4449	/**
4450	* Suspends, saves and powers off the VM.
4451	*
4452	* @returns The appropriate VBox status code to pass around.
4453	* @param pDevIns The device instance.
4454	* @thread An emulation thread.
4455	*/
4456	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4457
4458	/**
4459	* Power off the VM.
4460	*
4461	* @returns The appropriate VBox status code to pass around on power off.
4462	* @param pDevIns The device instance.
4463	* @thread The emulation thread.
4464	*/
4465	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4466
4467	/**
4468	* Checks if the Gate A20 is enabled or not.
4469	*
4470	* @returns true if A20 is enabled.
4471	* @returns false if A20 is disabled.
4472	* @param pDevIns The device instance.
4473	* @thread The emulation thread.
4474	*/
4475	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4476
4477	/**
4478	* Enables or disables the Gate A20.
4479	*
4480	* @param pDevIns The device instance.
4481	* @param fEnable Set this flag to enable the Gate A20; clear it
4482	* to disable.
4483	* @thread The emulation thread.
4484	*/
4485	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4486
4487	/**
4488	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4489	* thread.
4490	*
4491	* @param pDevIns The device instance.
4492	* @param iLeaf The CPUID leaf to get.
4493	* @param pEax Where to store the EAX value.
4494	* @param pEbx Where to store the EBX value.
4495	* @param pEcx Where to store the ECX value.
4496	* @param pEdx Where to store the EDX value.
4497	* @thread EMT.
4498	*/
4499	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4500
4501	/**
4502	* Get the current virtual clock time in a VM. The clock frequency must be
4503	* queried separately.
4504	*
4505	* @returns Current clock time.
4506	* @param pDevIns The device instance.
4507	*/
4508	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4509
4510	/**
4511	* Get the frequency of the virtual clock.
4512	*
4513	* @returns The clock frequency (not variable at run-time).
4514	* @param pDevIns The device instance.
4515	*/
4516	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4517
4518	/**
4519	* Get the current virtual clock time in a VM, in nanoseconds.
4520	*
4521	* @returns Current clock time (in ns).
4522	* @param pDevIns The device instance.
4523	*/
4524	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4525
4526	/**
4527	* Gets the support driver session.
4528	*
4529	* This is intended for working with the semaphore API.
4530	*
4531	* @returns Support driver session handle.
4532	* @param pDevIns The device instance.
4533	*/
4534	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4535
4536	/**
4537	* Queries a generic object from the VMM user.
4538	*
4539	* @returns Pointer to the object if found, NULL if not.
4540	* @param pDevIns The device instance.
4541	* @param pUuid The UUID of what's being queried. The UUIDs and
4542	* the usage conventions are defined by the user.
4543	*
4544	* @note It is strictly forbidden to call this internally in VBox! This
4545	* interface is exclusively for hacks in externally developed devices.
4546	*/
4547	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4548
4549	/**
4550	* Register a physical page access handler type.
4551	*
4552	* @returns VBox status code.
4553	* @param pDevIns The device instance.
4554	* @param enmKind The kind of access handler.
4555	* @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4556	* @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4557	* handler should be called.
4558	* @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4559	* ring-3 handler should be called.
4560	* @param pszHandlerRC The name of the raw-mode context handler, NULL if
4561	* the ring-3 handler should be called.
4562	* @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4563	* if the ring-3 handler should be called.
4564	* @param pszDesc The type description.
4565	* @param phType Where to return the type handle (cross context
4566	* safe).
4567	*/
4568	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4569	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4570	const char pszHandlerR0, const char pszPfHandlerR0,
4571	const char pszHandlerRC, const char pszPfHandlerRC,
4572	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4573
4574	/** @} */
4575
4576	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4577	uint32_t u32TheEnd;
4578	} PDMDEVHLPR3;
4579	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4580	/** Pointer to the R3 PDM Device API. */
4581	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4582	/** Pointer to the R3 PDM Device API, const variant. */
4583	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4584
4585
4586	/**
4587	* PDM Device API - RC Variant.
4588	*/
4589	typedef struct PDMDEVHLPRC
4590	{
4591	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4592	uint32_t u32Version;
4593
4594	/**
4595	* Sets up raw-mode context callback handlers for an I/O port range.
4596	*
4597	* The range must have been registered in ring-3 first using
4598	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4599	*
4600	* @returns VBox status.
4601	* @param pDevIns The device instance to register the ports with.
4602	* @param hIoPorts The I/O port range handle.
4603	* @param pfnOut Pointer to function which is gonna handle OUT
4604	* operations. Optional.
4605	* @param pfnIn Pointer to function which is gonna handle IN operations.
4606	* Optional.
4607	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4608	* operations. Optional.
4609	* @param pfnInStr Pointer to function which is gonna handle string IN
4610	* operations. Optional.
4611	* @param pvUser User argument to pass to the callbacks.
4612	*
4613	* @remarks Caller enters the device critical section prior to invoking the
4614	* registered callback methods.
4615	*
4616	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4617	* PDMDevHlpIoPortUnmap.
4618	*/
4619	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4620	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4621	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4622	void *pvUser));
4623
4624	/**
4625	* Sets up raw-mode context callback handlers for an MMIO region.
4626	*
4627	* The region must have been registered in ring-3 first using
4628	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4629	*
4630	* @returns VBox status.
4631	* @param pDevIns The device instance to register the ports with.
4632	* @param hRegion The MMIO region handle.
4633	* @param pfnWrite Pointer to function which is gonna handle Write
4634	* operations.
4635	* @param pfnRead Pointer to function which is gonna handle Read
4636	* operations.
4637	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4638	* operations. (optional)
4639	* @param pvUser User argument to pass to the callbacks.
4640	*
4641	* @remarks Caller enters the device critical section prior to invoking the
4642	* registered callback methods.
4643	*
4644	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4645	* PDMDevHlpMmioUnmap.
4646	*/
4647	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4648	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4649
4650	/**
4651	* Sets up a raw-mode mapping for an MMIO2 region.
4652	*
4653	* The region must have been created in ring-3 first using
4654	* PDMDevHlpMmio2Create().
4655	*
4656	* @returns VBox status.
4657	* @param pDevIns The device instance to register the ports with.
4658	* @param hRegion The MMIO2 region handle.
4659	* @param offSub Start of what to map into raw-mode. Must be page aligned.
4660	* @param cbSub Number of bytes to map into raw-mode. Must be page
4661	* aligned. Zero is an alias for everything.
4662	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4663	* @thread EMT(0)
4664	* @note Only available at VM creation time.
4665	*
4666	* @sa PDMDevHlpMmio2Create().
4667	*/
4668	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4669	size_t offSub, size_t cbSub, void **ppvMapping));
4670
4671	/**
4672	* Bus master physical memory read from the given PCI device.
4673	*
4674	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4675	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4676	* @param pDevIns The device instance.
4677	* @param pPciDev The PCI device structure. If NULL the default
4678	* PCI device for this device instance is used.
4679	* @param GCPhys Physical address start reading from.
4680	* @param pvBuf Where to put the read bits.
4681	* @param cbRead How many bytes to read.
4682	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4683	* @thread Any thread, but the call may involve the emulation thread.
4684	*/
4685	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4686	void *pvBuf, size_t cbRead, uint32_t fFlags));
4687
4688	/**
4689	* Bus master physical memory write from the given PCI device.
4690	*
4691	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4692	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4693	* @param pDevIns The device instance.
4694	* @param pPciDev The PCI device structure. If NULL the default
4695	* PCI device for this device instance is used.
4696	* @param GCPhys Physical address to write to.
4697	* @param pvBuf What to write.
4698	* @param cbWrite How many bytes to write.
4699	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4700	* @thread Any thread, but the call may involve the emulation thread.
4701	*/
4702	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4703	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4704
4705	/**
4706	* Set the IRQ for the given PCI device.
4707	*
4708	* @param pDevIns Device instance.
4709	* @param pPciDev The PCI device structure. If NULL the default
4710	* PCI device for this device instance is used.
4711	* @param iIrq IRQ number to set.
4712	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4713	* @thread Any thread, but will involve the emulation thread.
4714	*/
4715	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4716
4717	/**
4718	* Set ISA IRQ for a device.
4719	*
4720	* @param pDevIns Device instance.
4721	* @param iIrq IRQ number to set.
4722	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4723	* @thread Any thread, but will involve the emulation thread.
4724	*/
4725	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4726
4727	/**
4728	* Read physical memory.
4729	*
4730	* @returns VINF_SUCCESS (for now).
4731	* @param pDevIns Device instance.
4732	* @param GCPhys Physical address start reading from.
4733	* @param pvBuf Where to put the read bits.
4734	* @param cbRead How many bytes to read.
4735	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4736	*/
4737	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
4738
4739	/**
4740	* Write to physical memory.
4741	*
4742	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4743	* @param pDevIns Device instance.
4744	* @param GCPhys Physical address to write to.
4745	* @param pvBuf What to write.
4746	* @param cbWrite How many bytes to write.
4747	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4748	*/
4749	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4750
4751	/**
4752	* Checks if the Gate A20 is enabled or not.
4753	*
4754	* @returns true if A20 is enabled.
4755	* @returns false if A20 is disabled.
4756	* @param pDevIns Device instance.
4757	* @thread The emulation thread.
4758	*/
4759	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4760
4761	/**
4762	* Gets the VM state.
4763	*
4764	* @returns VM state.
4765	* @param pDevIns The device instance.
4766	* @thread Any thread (just keep in mind that it's volatile info).
4767	*/
4768	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4769
4770	/**
4771	* Gets the VM handle. Restricted API.
4772	*
4773	* @returns VM Handle.
4774	* @param pDevIns Device instance.
4775	*/
4776	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4777
4778	/**
4779	* Gets the VMCPU handle. Restricted API.
4780	*
4781	* @returns VMCPU Handle.
4782	* @param pDevIns The device instance.
4783	*/
4784	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4785
4786	/**
4787	* The the VM CPU ID of the current thread (restricted API).
4788	*
4789	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4790	* @param pDevIns The device instance.
4791	*/
4792	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4793
4794	/**
4795	* Get the current virtual clock time in a VM. The clock frequency must be
4796	* queried separately.
4797	*
4798	* @returns Current clock time.
4799	* @param pDevIns The device instance.
4800	*/
4801	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4802
4803	/**
4804	* Get the frequency of the virtual clock.
4805	*
4806	* @returns The clock frequency (not variable at run-time).
4807	* @param pDevIns The device instance.
4808	*/
4809	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4810
4811	/**
4812	* Get the current virtual clock time in a VM, in nanoseconds.
4813	*
4814	* @returns Current clock time (in ns).
4815	* @param pDevIns The device instance.
4816	*/
4817	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4818
4819	/**
4820	* Gets the NOP critical section.
4821	*
4822	* @returns The ring-3 address of the NOP critical section.
4823	* @param pDevIns The device instance.
4824	*/
4825	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4826
4827	/**
4828	* Changes the device level critical section from the automatically created
4829	* default to one desired by the device constructor.
4830	*
4831	* Must first be done in ring-3.
4832	*
4833	* @returns VBox status code.
4834	* @param pDevIns The device instance.
4835	* @param pCritSect The critical section to use. NULL is not
4836	* valid, instead use the NOP critical
4837	* section.
4838	*/
4839	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4840
4841	/** @name Exported PDM Critical Section Functions
4842	* @{ */
4843	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4844	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4845	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4846	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4847	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4848	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4849	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4850	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4851	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4852	/** @} */
4853
4854	/** @name Exported PDM Read/Write Critical Section Functions
4855	* @{ */
4856	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4857	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4858	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4859	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4860	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4861
4862	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4863	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4864	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4865	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4866	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4867
4868	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4869	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
4870	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4871	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4872	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4873	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4874	/** @} */
4875
4876	/**
4877	* Gets the trace buffer handle.
4878	*
4879	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4880	* really inteded for direct usage, thus no inline wrapper function.
4881	*
4882	* @returns Trace buffer handle or NIL_RTTRACEBUF.
4883	* @param pDevIns The device instance.
4884	*/
4885	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4886
4887	/**
4888	* Sets up the PCI bus for the raw-mode context.
4889	*
4890	* This must be called after ring-3 has registered the PCI bus using
4891	* PDMDevHlpPCIBusRegister().
4892	*
4893	* @returns VBox status code.
4894	* @param pDevIns The device instance.
4895	* @param pPciBusReg The PCI bus registration information for raw-mode,
4896	* considered volatile.
4897	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4898	*/
4899	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4900
4901	/**
4902	* Sets up the IOMMU for the raw-mode context.
4903	*
4904	* This must be called after ring-3 has registered the IOMMU using
4905	* PDMDevHlpIommuRegister().
4906	*
4907	* @returns VBox status code.
4908	* @param pDevIns The device instance.
4909	* @param pIommuReg The IOMMU registration information for raw-mode,
4910	* considered volatile.
4911	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
4912	*/
4913	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
4914
4915	/**
4916	* Sets up the PIC for the ring-0 context.
4917	*
4918	* This must be called after ring-3 has registered the PIC using
4919	* PDMDevHlpPICRegister().
4920	*
4921	* @returns VBox status code.
4922	* @param pDevIns The device instance.
4923	* @param pPicReg The PIC registration information for ring-0,
4924	* considered volatile and copied.
4925	* @param ppPicHlp Where to return the ring-0 PIC helpers.
4926	*/
4927	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4928
4929	/**
4930	* Sets up the APIC for the raw-mode context.
4931	*
4932	* This must be called after ring-3 has registered the APIC using
4933	* PDMDevHlpApicRegister().
4934	*
4935	* @returns VBox status code.
4936	* @param pDevIns The device instance.
4937	*/
4938	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
4939
4940	/**
4941	* Sets up the IOAPIC for the ring-0 context.
4942	*
4943	* This must be called after ring-3 has registered the PIC using
4944	* PDMDevHlpIoApicRegister().
4945	*
4946	* @returns VBox status code.
4947	* @param pDevIns The device instance.
4948	* @param pIoApicReg The PIC registration information for ring-0,
4949	* considered volatile and copied.
4950	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
4951	*/
4952	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4953
4954	/**
4955	* Sets up the HPET for the raw-mode context.
4956	*
4957	* This must be called after ring-3 has registered the PIC using
4958	* PDMDevHlpHpetRegister().
4959	*
4960	* @returns VBox status code.
4961	* @param pDevIns The device instance.
4962	* @param pHpetReg The PIC registration information for raw-mode,
4963	* considered volatile and copied.
4964	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
4965	*/
4966	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
4967
4968	/** Space reserved for future members.
4969	* @{ */
4970	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
4971	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
4972	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
4973	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
4974	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
4975	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
4976	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
4977	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
4978	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
4979	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
4980	/** @} */
4981
4982	/** Just a safety precaution. */
4983	uint32_t u32TheEnd;
4984	} PDMDEVHLPRC;
4985	/** Pointer PDM Device RC API. */
4986	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
4987	/** Pointer PDM Device RC API. */
4988	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
4989
4990	/** Current PDMDEVHLP version number. */
4991	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 18, 0)
4992
4993
4994	/**
4995	* PDM Device API - R0 Variant.
4996	*/
4997	typedef struct PDMDEVHLPR0
4998	{
4999	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5000	uint32_t u32Version;
5001
5002	/**
5003	* Sets up ring-0 callback handlers for an I/O port range.
5004	*
5005	* The range must have been created in ring-3 first using
5006	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5007	*
5008	* @returns VBox status.
5009	* @param pDevIns The device instance to register the ports with.
5010	* @param hIoPorts The I/O port range handle.
5011	* @param pfnOut Pointer to function which is gonna handle OUT
5012	* operations. Optional.
5013	* @param pfnIn Pointer to function which is gonna handle IN operations.
5014	* Optional.
5015	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5016	* operations. Optional.
5017	* @param pfnInStr Pointer to function which is gonna handle string IN
5018	* operations. Optional.
5019	* @param pvUser User argument to pass to the callbacks.
5020	*
5021	* @remarks Caller enters the device critical section prior to invoking the
5022	* registered callback methods.
5023	*
5024	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5025	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5026	*/
5027	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5028	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5029	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5030	void *pvUser));
5031
5032	/**
5033	* Sets up ring-0 callback handlers for an MMIO region.
5034	*
5035	* The region must have been created in ring-3 first using
5036	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5037	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5038	*
5039	* @returns VBox status.
5040	* @param pDevIns The device instance to register the ports with.
5041	* @param hRegion The MMIO region handle.
5042	* @param pfnWrite Pointer to function which is gonna handle Write
5043	* operations.
5044	* @param pfnRead Pointer to function which is gonna handle Read
5045	* operations.
5046	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5047	* operations. (optional)
5048	* @param pvUser User argument to pass to the callbacks.
5049	*
5050	* @remarks Caller enters the device critical section prior to invoking the
5051	* registered callback methods.
5052	*
5053	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5054	* PDMDevHlpMmioUnmap().
5055	*/
5056	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5057	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5058
5059	/**
5060	* Sets up a ring-0 mapping for an MMIO2 region.
5061	*
5062	* The region must have been created in ring-3 first using
5063	* PDMDevHlpMmio2Create().
5064	*
5065	* @returns VBox status.
5066	* @param pDevIns The device instance to register the ports with.
5067	* @param hRegion The MMIO2 region handle.
5068	* @param offSub Start of what to map into ring-0. Must be page aligned.
5069	* @param cbSub Number of bytes to map into ring-0. Must be page
5070	* aligned. Zero is an alias for everything.
5071	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5072	*
5073	* @thread EMT(0)
5074	* @note Only available at VM creation time.
5075	*
5076	* @sa PDMDevHlpMmio2Create().
5077	*/
5078	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5079	void **ppvMapping));
5080
5081	/**
5082	* Bus master physical memory read from the given PCI device.
5083	*
5084	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5085	* VERR_EM_MEMORY.
5086	* @param pDevIns The device instance.
5087	* @param pPciDev The PCI device structure. If NULL the default
5088	* PCI device for this device instance is used.
5089	* @param GCPhys Physical address start reading from.
5090	* @param pvBuf Where to put the read bits.
5091	* @param cbRead How many bytes to read.
5092	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5093	* @thread Any thread, but the call may involve the emulation thread.
5094	*/
5095	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5096	void *pvBuf, size_t cbRead, uint32_t fFlags));
5097
5098	/**
5099	* Bus master physical memory write from the given PCI device.
5100	*
5101	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5102	* VERR_EM_MEMORY.
5103	* @param pDevIns The device instance.
5104	* @param pPciDev The PCI device structure. If NULL the default
5105	* PCI device for this device instance is used.
5106	* @param GCPhys Physical address to write to.
5107	* @param pvBuf What to write.
5108	* @param cbWrite How many bytes to write.
5109	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5110	* @thread Any thread, but the call may involve the emulation thread.
5111	*/
5112	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5113	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5114
5115	/**
5116	* Set the IRQ for the given PCI device.
5117	*
5118	* @param pDevIns Device instance.
5119	* @param pPciDev The PCI device structure. If NULL the default
5120	* PCI device for this device instance is used.
5121	* @param iIrq IRQ number to set.
5122	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5123	* @thread Any thread, but will involve the emulation thread.
5124	*/
5125	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5126
5127	/**
5128	* Set ISA IRQ for a device.
5129	*
5130	* @param pDevIns Device instance.
5131	* @param iIrq IRQ number to set.
5132	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5133	* @thread Any thread, but will involve the emulation thread.
5134	*/
5135	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5136
5137	/**
5138	* Read physical memory.
5139	*
5140	* @returns VINF_SUCCESS (for now).
5141	* @param pDevIns Device instance.
5142	* @param GCPhys Physical address start reading from.
5143	* @param pvBuf Where to put the read bits.
5144	* @param cbRead How many bytes to read.
5145	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5146	*/
5147	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5148
5149	/**
5150	* Write to physical memory.
5151	*
5152	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5153	* @param pDevIns Device instance.
5154	* @param GCPhys Physical address to write to.
5155	* @param pvBuf What to write.
5156	* @param cbWrite How many bytes to write.
5157	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5158	*/
5159	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5160
5161	/**
5162	* Checks if the Gate A20 is enabled or not.
5163	*
5164	* @returns true if A20 is enabled.
5165	* @returns false if A20 is disabled.
5166	* @param pDevIns Device instance.
5167	* @thread The emulation thread.
5168	*/
5169	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5170
5171	/**
5172	* Gets the VM state.
5173	*
5174	* @returns VM state.
5175	* @param pDevIns The device instance.
5176	* @thread Any thread (just keep in mind that it's volatile info).
5177	*/
5178	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5179
5180	/**
5181	* Gets the VM handle. Restricted API.
5182	*
5183	* @returns VM Handle.
5184	* @param pDevIns Device instance.
5185	*/
5186	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5187
5188	/**
5189	* Gets the VMCPU handle. Restricted API.
5190	*
5191	* @returns VMCPU Handle.
5192	* @param pDevIns The device instance.
5193	*/
5194	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5195
5196	/**
5197	* The the VM CPU ID of the current thread (restricted API).
5198	*
5199	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5200	* @param pDevIns The device instance.
5201	*/
5202	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5203
5204	/** @name Timer handle method wrappers
5205	* @{ */
5206	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5207	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5208	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5209	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5210	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5211	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5212	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5213	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5214	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5215	/** Takes the clock lock then enters the specified critical section. */
5216	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5217	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5218	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5219	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5220	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5221	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5222	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5223	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5224	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5225	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5226	/** @} */
5227
5228	/**
5229	* Get the current virtual clock time in a VM. The clock frequency must be
5230	* queried separately.
5231	*
5232	* @returns Current clock time.
5233	* @param pDevIns The device instance.
5234	*/
5235	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5236
5237	/**
5238	* Get the frequency of the virtual clock.
5239	*
5240	* @returns The clock frequency (not variable at run-time).
5241	* @param pDevIns The device instance.
5242	*/
5243	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5244
5245	/**
5246	* Get the current virtual clock time in a VM, in nanoseconds.
5247	*
5248	* @returns Current clock time (in ns).
5249	* @param pDevIns The device instance.
5250	*/
5251	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5252
5253	/** @name Exported PDM Queue Functions
5254	* @{ */
5255	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5256	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5257	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5258	/** @} */
5259
5260	/** @name PDM Task
5261	* @{ */
5262	/**
5263	* Triggers the running the given task.
5264	*
5265	* @returns VBox status code.
5266	* @retval VINF_ALREADY_POSTED is the task is already pending.
5267	* @param pDevIns The device instance.
5268	* @param hTask The task to trigger.
5269	* @thread Any thread.
5270	*/
5271	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5272	/** @} */
5273
5274	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5275	* These semaphores can be signalled from ring-0.
5276	* @{ */
5277	/** @sa SUPSemEventSignal */
5278	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5279	/** @sa SUPSemEventWaitNoResume */
5280	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5281	/** @sa SUPSemEventWaitNsAbsIntr */
5282	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5283	/** @sa SUPSemEventWaitNsRelIntr */
5284	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5285	/** @sa SUPSemEventGetResolution */
5286	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5287	/** @} */
5288
5289	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5290	* These semaphores can be signalled from ring-0.
5291	* @{ */
5292	/** @sa SUPSemEventMultiSignal */
5293	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5294	/** @sa SUPSemEventMultiReset */
5295	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5296	/** @sa SUPSemEventMultiWaitNoResume */
5297	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5298	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5299	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5300	/** @sa SUPSemEventMultiWaitNsRelIntr */
5301	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5302	/** @sa SUPSemEventMultiGetResolution */
5303	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5304	/** @} */
5305
5306	/**
5307	* Gets the NOP critical section.
5308	*
5309	* @returns The ring-3 address of the NOP critical section.
5310	* @param pDevIns The device instance.
5311	*/
5312	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5313
5314	/**
5315	* Changes the device level critical section from the automatically created
5316	* default to one desired by the device constructor.
5317	*
5318	* Must first be done in ring-3.
5319	*
5320	* @returns VBox status code.
5321	* @param pDevIns The device instance.
5322	* @param pCritSect The critical section to use. NULL is not
5323	* valid, instead use the NOP critical
5324	* section.
5325	*/
5326	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5327
5328	/** @name Exported PDM Critical Section Functions
5329	* @{ */
5330	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5331	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5332	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5333	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5334	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5335	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5336	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5337	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5338	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5339	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5340	/** @} */
5341
5342	/** @name Exported PDM Read/Write Critical Section Functions
5343	* @{ */
5344	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5345	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5346	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5347	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5348	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5349
5350	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5351	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5352	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5353	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5354	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5355
5356	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5357	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5358	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5359	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5360	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5361	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5362	/** @} */
5363
5364	/**
5365	* Gets the trace buffer handle.
5366	*
5367	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5368	* really inteded for direct usage, thus no inline wrapper function.
5369	*
5370	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5371	* @param pDevIns The device instance.
5372	*/
5373	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5374
5375	/**
5376	* Sets up the PCI bus for the ring-0 context.
5377	*
5378	* This must be called after ring-3 has registered the PCI bus using
5379	* PDMDevHlpPCIBusRegister().
5380	*
5381	* @returns VBox status code.
5382	* @param pDevIns The device instance.
5383	* @param pPciBusReg The PCI bus registration information for ring-0,
5384	* considered volatile and copied.
5385	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5386	*/
5387	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5388
5389	/**
5390	* Sets up the IOMMU for the ring-0 context.
5391	*
5392	* This must be called after ring-3 has registered the IOMMU using
5393	* PDMDevHlpIommuRegister().
5394	*
5395	* @returns VBox status code.
5396	* @param pDevIns The device instance.
5397	* @param pIommuReg The IOMMU registration information for ring-0,
5398	* considered volatile and copied.
5399	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5400	*/
5401	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5402
5403	/**
5404	* Sets up the PIC for the ring-0 context.
5405	*
5406	* This must be called after ring-3 has registered the PIC using
5407	* PDMDevHlpPICRegister().
5408	*
5409	* @returns VBox status code.
5410	* @param pDevIns The device instance.
5411	* @param pPicReg The PIC registration information for ring-0,
5412	* considered volatile and copied.
5413	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5414	*/
5415	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5416
5417	/**
5418	* Sets up the APIC for the ring-0 context.
5419	*
5420	* This must be called after ring-3 has registered the APIC using
5421	* PDMDevHlpApicRegister().
5422	*
5423	* @returns VBox status code.
5424	* @param pDevIns The device instance.
5425	*/
5426	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5427
5428	/**
5429	* Sets up the IOAPIC for the ring-0 context.
5430	*
5431	* This must be called after ring-3 has registered the PIC using
5432	* PDMDevHlpIoApicRegister().
5433	*
5434	* @returns VBox status code.
5435	* @param pDevIns The device instance.
5436	* @param pIoApicReg The PIC registration information for ring-0,
5437	* considered volatile and copied.
5438	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5439	*/
5440	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5441
5442	/**
5443	* Sets up the HPET for the ring-0 context.
5444	*
5445	* This must be called after ring-3 has registered the PIC using
5446	* PDMDevHlpHpetRegister().
5447	*
5448	* @returns VBox status code.
5449	* @param pDevIns The device instance.
5450	* @param pHpetReg The PIC registration information for ring-0,
5451	* considered volatile and copied.
5452	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5453	*/
5454	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5455
5456	/** Space reserved for future members.
5457	* @{ */
5458	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5459	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5460	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5461	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5462	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5463	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5464	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5465	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5466	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5467	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5468	/** @} */
5469
5470	/** Just a safety precaution. */
5471	uint32_t u32TheEnd;
5472	} PDMDEVHLPR0;
5473	/** Pointer PDM Device R0 API. */
5474	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5475	/** Pointer PDM Device GC API. */
5476	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5477
5478	/** Current PDMDEVHLP version number. */
5479	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 22, 0)
5480
5481
5482	/**
5483	* PDM Device Instance.
5484	*/
5485	typedef struct PDMDEVINSR3
5486	{
5487	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5488	uint32_t u32Version;
5489	/** Device instance number. */
5490	uint32_t iInstance;
5491	/** Size of the ring-3, raw-mode and shared bits. */
5492	uint32_t cbRing3;
5493	/** Set if ring-0 context is enabled. */
5494	bool fR0Enabled;
5495	/** Set if raw-mode context is enabled. */
5496	bool fRCEnabled;
5497	/** Alignment padding. */
5498	bool afReserved[2];
5499	/** Pointer the HC PDM Device API. */
5500	PCPDMDEVHLPR3 pHlpR3;
5501	/** Pointer to the shared device instance data. */
5502	RTR3PTR pvInstanceDataR3;
5503	/** Pointer to the device instance data for ring-3. */
5504	RTR3PTR pvInstanceDataForR3;
5505	/** The critical section for the device.
5506	*
5507	* TM and IOM will enter this critical section before calling into the device
5508	* code. PDM will when doing power on, power off, reset, suspend and resume
5509	* notifications. SSM will currently not, but this will be changed later on.
5510	*
5511	* The device gets a critical section automatically assigned to it before
5512	* the constructor is called. If the constructor wishes to use a different
5513	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5514	* very early on.
5515	*/
5516	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5517	/** Pointer to device registration structure. */
5518	R3PTRTYPE(PCPDMDEVREG) pReg;
5519	/** Configuration handle. */
5520	R3PTRTYPE(PCFGMNODE) pCfg;
5521	/** The base interface of the device.
5522	*
5523	* The device constructor initializes this if it has any
5524	* device level interfaces to export. To obtain this interface
5525	* call PDMR3QueryDevice(). */
5526	PDMIBASE IBase;
5527
5528	/** Tracing indicator. */
5529	uint32_t fTracing;
5530	/** The tracing ID of this device. */
5531	uint32_t idTracing;
5532
5533	/** Ring-3 pointer to the raw-mode device instance. */
5534	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5535	/** Raw-mode address of the raw-mode device instance. */
5536	RTRGPTR pDevInsForRC;
5537	/** Ring-3 pointer to the raw-mode instance data. */
5538	RTR3PTR pvInstanceDataForRCR3;
5539
5540	/** PCI device structure size. */
5541	uint32_t cbPciDev;
5542	/** Number of PCI devices in apPciDevs. */
5543	uint32_t cPciDevs;
5544	/** Pointer to the PCI devices for this device.
5545	* (Allocated after the shared instance data.)
5546	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5547	* two devices ever needing it can use cbPciDev and do the address
5548	* calculations that for entries 8+. */
5549	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5550
5551	/** Temporarily. */
5552	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5553	/** Temporarily. */
5554	RTR0PTR pvInstanceDataR0;
5555	/** Temporarily. */
5556	RTRCPTR pvInstanceDataRC;
5557	/** Align the internal data more naturally. */
5558	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5559
5560	/** Internal data. */
5561	union
5562	{
5563	#ifdef PDMDEVINSINT_DECLARED
5564	PDMDEVINSINTR3 s;
5565	#endif
5566	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
5567	} Internal;
5568
5569	/** Device instance data for ring-3. The size of this area is defined
5570	* in the PDMDEVREG::cbInstanceR3 field. */
5571	char achInstanceData[8];
5572	} PDMDEVINSR3;
5573
5574	/** Current PDMDEVINSR3 version number. */
5575	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5576
5577	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5578	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5579
5580
5581	/**
5582	* PDM ring-0 device instance.
5583	*/
5584	typedef struct PDMDEVINSR0
5585	{
5586	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5587	uint32_t u32Version;
5588	/** Device instance number. */
5589	uint32_t iInstance;
5590
5591	/** Pointer the HC PDM Device API. */
5592	PCPDMDEVHLPR0 pHlpR0;
5593	/** Pointer to the shared device instance data. */
5594	RTR0PTR pvInstanceDataR0;
5595	/** Pointer to the device instance data for ring-0. */
5596	RTR0PTR pvInstanceDataForR0;
5597	/** The critical section for the device.
5598	*
5599	* TM and IOM will enter this critical section before calling into the device
5600	* code. PDM will when doing power on, power off, reset, suspend and resume
5601	* notifications. SSM will currently not, but this will be changed later on.
5602	*
5603	* The device gets a critical section automatically assigned to it before
5604	* the constructor is called. If the constructor wishes to use a different
5605	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5606	* very early on.
5607	*/
5608	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5609	/** Pointer to the ring-0 device registration structure. */
5610	R0PTRTYPE(PCPDMDEVREGR0) pReg;
5611	/** Ring-3 address of the ring-3 device instance. */
5612	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5613	/** Ring-0 pointer to the ring-3 device instance. */
5614	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5615	/** Ring-0 pointer to the ring-3 instance data. */
5616	RTR0PTR pvInstanceDataForR3R0;
5617	/** Raw-mode address of the raw-mode device instance. */
5618	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5619	/** Ring-0 pointer to the raw-mode device instance. */
5620	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5621	/** Ring-0 pointer to the raw-mode instance data. */
5622	RTR0PTR pvInstanceDataForRCR0;
5623
5624	/** PCI device structure size. */
5625	uint32_t cbPciDev;
5626	/** Number of PCI devices in apPciDevs. */
5627	uint32_t cPciDevs;
5628	/** Pointer to the PCI devices for this device.
5629	* (Allocated after the shared instance data.)
5630	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5631	* two devices ever needing it can use cbPciDev and do the address
5632	* calculations that for entries 8+. */
5633	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5634
5635	/** Align the internal data more naturally. */
5636	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5637
5638	/** Internal data. */
5639	union
5640	{
5641	#ifdef PDMDEVINSINT_DECLARED
5642	PDMDEVINSINTR0 s;
5643	#endif
5644	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
5645	} Internal;
5646
5647	/** Device instance data for ring-0. The size of this area is defined
5648	* in the PDMDEVREG::cbInstanceR0 field. */
5649	char achInstanceData[8];
5650	} PDMDEVINSR0;
5651
5652	/** Current PDMDEVINSR0 version number. */
5653	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5654
5655
5656	/**
5657	* PDM raw-mode device instance.
5658	*/
5659	typedef struct PDMDEVINSRC
5660	{
5661	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5662	uint32_t u32Version;
5663	/** Device instance number. */
5664	uint32_t iInstance;
5665
5666	/** Pointer the HC PDM Device API. */
5667	PCPDMDEVHLPRC pHlpRC;
5668	/** Pointer to the shared device instance data. */
5669	RTRGPTR pvInstanceDataRC;
5670	/** Pointer to the device instance data for raw-mode. */
5671	RTRGPTR pvInstanceDataForRC;
5672	/** The critical section for the device.
5673	*
5674	* TM and IOM will enter this critical section before calling into the device
5675	* code. PDM will when doing power on, power off, reset, suspend and resume
5676	* notifications. SSM will currently not, but this will be changed later on.
5677	*
5678	* The device gets a critical section automatically assigned to it before
5679	* the constructor is called. If the constructor wishes to use a different
5680	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5681	* very early on.
5682	*/
5683	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5684	/** Pointer to the raw-mode device registration structure. */
5685	RGPTRTYPE(PCPDMDEVREGRC) pReg;
5686
5687	/** PCI device structure size. */
5688	uint32_t cbPciDev;
5689	/** Number of PCI devices in apPciDevs. */
5690	uint32_t cPciDevs;
5691	/** Pointer to the PCI devices for this device.
5692	* (Allocated after the shared instance data.) */
5693	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5694
5695	/** Align the internal data more naturally. */
5696	uint32_t au32Padding[14];
5697
5698	/** Internal data. */
5699	union
5700	{
5701	#ifdef PDMDEVINSINT_DECLARED
5702	PDMDEVINSINTRC s;
5703	#endif
5704	uint8_t padding[0x10];
5705	} Internal;
5706
5707	/** Device instance data for ring-0. The size of this area is defined
5708	* in the PDMDEVREG::cbInstanceR0 field. */
5709	char achInstanceData[8];
5710	} PDMDEVINSRC;
5711
5712	/** Current PDMDEVINSR0 version number. */
5713	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5714
5715
5716	/** @def PDM_DEVINS_VERSION
5717	* Current PDMDEVINS version number. */
5718	/** @typedef PDMDEVINS
5719	* The device instance structure for the current context. */
5720	#ifdef IN_RING3
5721	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5722	typedef PDMDEVINSR3 PDMDEVINS;
5723	#elif defined(IN_RING0)
5724	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5725	typedef PDMDEVINSR0 PDMDEVINS;
5726	#elif defined(IN_RC)
5727	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5728	typedef PDMDEVINSRC PDMDEVINS;
5729	#else
5730	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5731	#endif
5732
5733	/**
5734	* Get the pointer to an PCI device.
5735	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5736	*/
5737	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5738	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5739	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5740
5741	/**
5742	* Calc the pointer to of a given PCI device.
5743	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5744	*/
5745	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5746	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5747	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
5748	: (PPDMPCIDEV)NULL )
5749
5750
5751	/**
5752	* Checks the structure versions of the device instance and device helpers,
5753	* returning if they are incompatible.
5754	*
5755	* This is for use in the constructor.
5756	*
5757	* @param pDevIns The device instance pointer.
5758	*/
5759	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5760	do \
5761	{ \
5762	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5763	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5764	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5765	VERR_PDM_DEVINS_VERSION_MISMATCH); \
5766	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5767	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5768	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5769	} while (0)
5770
5771	/**
5772	* Quietly checks the structure versions of the device instance and device
5773	* helpers, returning if they are incompatible.
5774	*
5775	* This is for use in the destructor.
5776	*
5777	* @param pDevIns The device instance pointer.
5778	*/
5779	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5780	do \
5781	{ \
5782	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5783	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5784	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5785	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5786	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5787	} while (0)
5788
5789	/**
5790	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
5791	* constructor - returns on failure.
5792	*
5793	* This should be invoked after having initialized the instance data
5794	* sufficiently for the correct operation of the destructor. The destructor is
5795	* always called!
5796	*
5797	* @param pDevIns Pointer to the PDM device instance.
5798	* @param pszValidValues Patterns describing the valid value names. See
5799	* RTStrSimplePatternMultiMatch for details on the
5800	* pattern syntax.
5801	* @param pszValidNodes Patterns describing the valid node (key) names.
5802	* Pass empty string if no valid nodes.
5803	*/
5804	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5805	do \
5806	{ \
5807	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5808	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5809	if (RT_SUCCESS(rcValCfg)) \
5810	{ /* likely */ } else return rcValCfg; \
5811	} while (0)
5812
5813	/** @def PDMDEV_ASSERT_EMT
5814	* Assert that the current thread is the emulation thread.
5815	*/
5816	#ifdef VBOX_STRICT
5817	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5818	#else
5819	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5820	#endif
5821
5822	/** @def PDMDEV_ASSERT_OTHER
5823	* Assert that the current thread is NOT the emulation thread.
5824	*/
5825	#ifdef VBOX_STRICT
5826	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5827	#else
5828	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5829	#endif
5830
5831	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5832	* Assert that the current thread is owner of the VM lock.
5833	*/
5834	#ifdef VBOX_STRICT
5835	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5836	#else
5837	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5838	#endif
5839
5840	/** @def PDMDEV_SET_ERROR
5841	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5842	*/
5843	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5844	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5845
5846	/** @def PDMDEV_SET_RUNTIME_ERROR
5847	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5848	*/
5849	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5850	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5851
5852	/** @def PDMDEVINS_2_RCPTR
5853	* Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
5854	*/
5855	#ifdef IN_RC
5856	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5857	#else
5858	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5859	#endif
5860
5861	/** @def PDMDEVINS_2_R3PTR
5862	* Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
5863	*/
5864	#ifdef IN_RING3
5865	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5866	#else
5867	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5868	#endif
5869
5870	/** @def PDMDEVINS_2_R0PTR
5871	* Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
5872	*/
5873	#ifdef IN_RING0
5874	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5875	#else
5876	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5877	#endif
5878
5879	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5880	* Converts a PDM device instance data pointer to a ring-0 one.
5881	* @deprecated
5882	*/
5883	#ifdef IN_RING0
5884	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5885	#else
5886	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5887	#endif
5888
5889
5890	/** @def PDMDEVINS_2_DATA
5891	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
5892	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5893	*
5894	* @note Do no use this macro in common code working on a core structure which
5895	* device specific code has expanded.
5896	*/
5897	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5898	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5899	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5900	{ \
5901	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5902	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5903	return pLambdaRet; \
5904	}(a_pDevIns))
5905	#else
5906	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5907	#endif
5908
5909	/** @def PDMDEVINS_2_DATA_CC
5910	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5911	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5912	*
5913	* @note Do no use this macro in common code working on a core structure which
5914	* device specific code has expanded.
5915	*/
5916	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5917	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5918	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5919	{ \
5920	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5921	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5922	return pLambdaRet; \
5923	}(a_pDevIns))
5924	#else
5925	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5926	#endif
5927
5928
5929	#ifdef IN_RING3
5930
5931	/**
5932	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
5933	*/
5934	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5935	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
5936	PIOMIOPORTHANDLE phIoPorts)
5937	{
5938	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5939	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5940	if (RT_SUCCESS(rc))
5941	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5942	return rc;
5943	}
5944
5945	/**
5946	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
5947	*/
5948	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5949	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
5950	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5951	{
5952	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5953	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5954	if (RT_SUCCESS(rc))
5955	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5956	return rc;
5957	}
5958
5959	/**
5960	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
5961	*/
5962	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5963	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5964	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5965	{
5966	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5967	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5968	if (RT_SUCCESS(rc))
5969	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5970	return rc;
5971	}
5972
5973	/**
5974	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
5975	*/
5976	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5977	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5978	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5979	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5980	{
5981	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5982	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5983	if (RT_SUCCESS(rc))
5984	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5985	return rc;
5986	}
5987
5988	/**
5989	* @sa PDMDevHlpIoPortCreateEx
5990	*/
5991	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5992	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
5993	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5994	{
5995	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
5996	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5997	}
5998
5999
6000	/**
6001	* @sa PDMDevHlpIoPortCreateEx
6002	*/
6003	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6004	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6005	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6006	{
6007	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6008	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6009	}
6010
6011	/**
6012	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6013	*/
6014	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6015	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6016	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6017	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6018	{
6019	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6020	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6021	}
6022
6023	/**
6024	* @copydoc PDMDEVHLPR3::pfnIoPortMap
6025	*/
6026	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6027	{
6028	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6029	}
6030
6031	/**
6032	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6033	*/
6034	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6035	{
6036	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6037	}
6038
6039	/**
6040	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6041	*/
6042	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6043	{
6044	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6045	}
6046
6047
6048	#endif /* IN_RING3 */
6049	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6050
6051	/**
6052	* @sa PDMDevHlpIoPortSetUpContextEx
6053	*/
6054	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6055	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6056	{
6057	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6058	}
6059
6060	/**
6061	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6062	*/
6063	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6064	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6065	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6066	{
6067	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6068	}
6069
6070	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6071	#ifdef IN_RING3
6072
6073	/**
6074	* @sa PDMDevHlpMmioCreateEx
6075	*/
6076	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6077	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6078	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6079	{
6080	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6081	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6082	}
6083
6084	/**
6085	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6086	*/
6087	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6088	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6089	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6090	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6091	{
6092	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6093	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6094	}
6095
6096	/**
6097	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6098	*/
6099	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6100	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6101	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6102	{
6103	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6104	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6105	if (RT_SUCCESS(rc))
6106	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6107	return rc;
6108	}
6109
6110	/**
6111	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6112	*/
6113	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6114	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6115	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6116	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6117	{
6118	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6119	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6120	if (RT_SUCCESS(rc))
6121	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6122	return rc;
6123	}
6124
6125	/**
6126	* @copydoc PDMDEVHLPR3::pfnMmioMap
6127	*/
6128	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6129	{
6130	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6131	}
6132
6133	/**
6134	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6135	*/
6136	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6137	{
6138	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6139	}
6140
6141	/**
6142	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6143	*/
6144	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6145	{
6146	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6147	}
6148
6149	/**
6150	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6151	*/
6152	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6153	{
6154	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6155	}
6156
6157	#endif /* IN_RING3 */
6158	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6159
6160	/**
6161	* @sa PDMDevHlpMmioSetUpContextEx
6162	*/
6163	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6164	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6165	{
6166	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6167	}
6168
6169	/**
6170	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6171	*/
6172	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6173	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6174	{
6175	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6176	}
6177
6178	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6179	#ifdef IN_RING3
6180
6181	/**
6182	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6183	*/
6184	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6185	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6186	{
6187	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6188	}
6189
6190	/**
6191	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6192	*/
6193	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6194	{
6195	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6196	}
6197
6198	/**
6199	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6200	*/
6201	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6202	{
6203	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6204	}
6205
6206	/**
6207	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6208	*/
6209	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6210	{
6211	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6212	}
6213
6214	/**
6215	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6216	*/
6217	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6218	{
6219	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6220	}
6221
6222	#endif /* IN_RING3 */
6223	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6224
6225	/**
6226	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6227	*/
6228	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6229	size_t offSub, size_t cbSub, void **ppvMapping)
6230	{
6231	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6232	}
6233
6234	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6235	#ifdef IN_RING3
6236
6237	/**
6238	* @copydoc PDMDEVHLPR3::pfnROMRegister
6239	*/
6240	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6241	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6242	{
6243	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6244	}
6245
6246	/**
6247	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6248	*/
6249	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6250	{
6251	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6252	}
6253
6254	/**
6255	* Register a save state data unit.
6256	*
6257	* @returns VBox status.
6258	* @param pDevIns The device instance.
6259	* @param uVersion Data layout version number.
6260	* @param cbGuess The approximate amount of data in the unit.
6261	* Only for progress indicators.
6262	* @param pfnSaveExec Execute save callback, optional.
6263	* @param pfnLoadExec Execute load callback, optional.
6264	*/
6265	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6266	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6267	{
6268	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6269	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6270	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6271	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6272	}
6273
6274	/**
6275	* Register a save state data unit with a live save callback as well.
6276	*
6277	* @returns VBox status.
6278	* @param pDevIns The device instance.
6279	* @param uVersion Data layout version number.
6280	* @param cbGuess The approximate amount of data in the unit.
6281	* Only for progress indicators.
6282	* @param pfnLiveExec Execute live callback, optional.
6283	* @param pfnSaveExec Execute save callback, optional.
6284	* @param pfnLoadExec Execute load callback, optional.
6285	*/
6286	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6287	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6288	{
6289	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6290	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6291	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6292	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6293	}
6294
6295	/**
6296	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6297	*/
6298	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6299	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6300	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6301	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6302	{
6303	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6304	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6305	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6306	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6307	}
6308
6309	/**
6310	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6311	*/
6312	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6313	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6314	{
6315	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6316	}
6317
6318	#endif /* IN_RING3 */
6319
6320	/**
6321	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6322	*/
6323	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6324	{
6325	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6326	}
6327
6328	/**
6329	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6330	*/
6331	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6332	{
6333	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6334	}
6335
6336	/**
6337	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6338	*/
6339	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6340	{
6341	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6342	}
6343
6344	/**
6345	* @copydoc PDMDEVHLPR3::pfnTimerGet
6346	*/
6347	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6348	{
6349	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6350	}
6351
6352	/**
6353	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6354	*/
6355	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6356	{
6357	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6358	}
6359
6360	/**
6361	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6362	*/
6363	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6364	{
6365	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6366	}
6367
6368	/**
6369	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6370	*/
6371	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6372	{
6373	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6374	}
6375
6376	/**
6377	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6378	*/
6379	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6380	{
6381	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6382	}
6383
6384	/**
6385	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
6386	*/
6387	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6388	{
6389	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6390	}
6391
6392	/**
6393	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6394	*/
6395	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6396	{
6397	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6398	}
6399
6400	/**
6401	* @copydoc PDMDEVHLPR3::pfnTimerSet
6402	*/
6403	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6404	{
6405	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6406	}
6407
6408	/**
6409	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6410	*/
6411	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6412	{
6413	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6414	}
6415
6416	/**
6417	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6418	*/
6419	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6420	{
6421	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6422	}
6423
6424	/**
6425	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6426	*/
6427	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6428	{
6429	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6430	}
6431
6432	/**
6433	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6434	*/
6435	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6436	{
6437	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6438	}
6439
6440	/**
6441	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6442	*/
6443	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6444	{
6445	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6446	}
6447
6448	/**
6449	* @copydoc PDMDEVHLPR3::pfnTimerStop
6450	*/
6451	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6452	{
6453	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6454	}
6455
6456	/**
6457	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6458	*/
6459	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6460	{
6461	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6462	}
6463
6464	/**
6465	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6466	*/
6467	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6468	{
6469	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6470	}
6471
6472	#ifdef IN_RING3
6473
6474	/**
6475	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6476	*/
6477	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6478	{
6479	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6480	}
6481
6482	/**
6483	* @copydoc PDMDEVHLPR3::pfnTimerSave
6484	*/
6485	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6486	{
6487	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6488	}
6489
6490	/**
6491	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6492	*/
6493	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6494	{
6495	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6496	}
6497
6498	/**
6499	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6500	*/
6501	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6502	{
6503	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6504	}
6505
6506	/**
6507	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6508	*/
6509	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6510	{
6511	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6512	}
6513
6514	#endif
6515
6516	/**
6517	* Read physical memory - unknown data usage.
6518	*
6519	* @returns VINF_SUCCESS (for now).
6520	* @param pDevIns The device instance.
6521	* @param GCPhys Physical address start reading from.
6522	* @param pvBuf Where to put the read bits.
6523	* @param cbRead How many bytes to read.
6524	* @thread Any thread, but the call may involve the emulation thread.
6525	*/
6526	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6527	{
6528	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6529	}
6530
6531	/**
6532	* Write to physical memory - unknown data usage.
6533	*
6534	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6535	* @param pDevIns The device instance.
6536	* @param GCPhys Physical address to write to.
6537	* @param pvBuf What to write.
6538	* @param cbWrite How many bytes to write.
6539	* @thread Any thread, but the call may involve the emulation thread.
6540	*/
6541	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6542	{
6543	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6544	}
6545
6546	/**
6547	* Read physical memory - reads meta data processed by the device.
6548	*
6549	* @returns VINF_SUCCESS (for now).
6550	* @param pDevIns The device instance.
6551	* @param GCPhys Physical address start reading from.
6552	* @param pvBuf Where to put the read bits.
6553	* @param cbRead How many bytes to read.
6554	* @thread Any thread, but the call may involve the emulation thread.
6555	*/
6556	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6557	{
6558	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6559	}
6560
6561	/**
6562	* Write to physical memory - written data was created/altered by the device.
6563	*
6564	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6565	* @param pDevIns The device instance.
6566	* @param GCPhys Physical address to write to.
6567	* @param pvBuf What to write.
6568	* @param cbWrite How many bytes to write.
6569	* @thread Any thread, but the call may involve the emulation thread.
6570	*/
6571	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6572	{
6573	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6574	}
6575
6576	/**
6577	* Read physical memory - read data will not be touched by the device.
6578	*
6579	* @returns VINF_SUCCESS (for now).
6580	* @param pDevIns The device instance.
6581	* @param GCPhys Physical address start reading from.
6582	* @param pvBuf Where to put the read bits.
6583	* @param cbRead How many bytes to read.
6584	* @thread Any thread, but the call may involve the emulation thread.
6585	*/
6586	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6587	{
6588	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6589	}
6590
6591	/**
6592	* Write to physical memory - written data was not touched/created by the device.
6593	*
6594	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6595	* @param pDevIns The device instance.
6596	* @param GCPhys Physical address to write to.
6597	* @param pvBuf What to write.
6598	* @param cbWrite How many bytes to write.
6599	* @thread Any thread, but the call may involve the emulation thread.
6600	*/
6601	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6602	{
6603	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6604	}
6605
6606	#ifdef IN_RING3
6607
6608	/**
6609	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6610	*/
6611	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6612	{
6613	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6614	}
6615
6616	/**
6617	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6618	*/
6619	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6620	PPGMPAGEMAPLOCK pLock)
6621	{
6622	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6623	}
6624
6625	/**
6626	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6627	*/
6628	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6629	{
6630	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6631	}
6632
6633	/**
6634	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6635	*/
6636	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6637	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6638	{
6639	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6640	}
6641
6642	/**
6643	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6644	*/
6645	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6646	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6647	{
6648	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6649	}
6650
6651	/**
6652	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6653	*/
6654	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6655	{
6656	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6657	}
6658
6659	/**
6660	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
6661	*/
6662	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
6663	{
6664	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
6665	}
6666
6667	/**
6668	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
6669	*/
6670	DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth)
6671	{
6672	pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
6673	}
6674
6675	/**
6676	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6677	*/
6678	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6679	{
6680	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6681	}
6682
6683	/**
6684	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6685	*/
6686	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6687	{
6688	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6689	}
6690
6691	/**
6692	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6693	*/
6694	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6695	{
6696	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6697	}
6698
6699	/**
6700	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6701	*/
6702	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6703	{
6704	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6705	}
6706
6707	/**
6708	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6709	*/
6710	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6711	{
6712	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6713	}
6714
6715	/**
6716	* Allocating string printf.
6717	*
6718	* @returns Pointer to the string.
6719	* @param pDevIns The device instance.
6720	* @param enmTag The statistics tag.
6721	* @param pszFormat The format string.
6722	* @param ... Format arguments.
6723	*/
6724	DECLINLINE(char ) RT_IPRT_FORMAT_ATTR(2, 3) PDMDevHlpMMHeapAPrintf(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, ...)
6725	{
6726	va_list va;
6727	va_start(va, pszFormat);
6728	char *psz = pDevIns->pHlpR3->pfnMMHeapAPrintfV(pDevIns, enmTag, pszFormat, va);
6729	va_end(va);
6730
6731	return psz;
6732	}
6733
6734	/**
6735	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
6736	*/
6737	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6738	{
6739	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6740	}
6741
6742	/**
6743	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSize
6744	*/
6745	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSize(PPDMDEVINS pDevIns)
6746	{
6747	return pDevIns->pHlpR3->pfnMMPhysGetRamSize(pDevIns);
6748	}
6749
6750	/**
6751	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeBelow4GB
6752	*/
6753	DECLINLINE(uint32_t) PDMDevHlpMMPhysGetRamSizeBelow4GB(PPDMDEVINS pDevIns)
6754	{
6755	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeBelow4GB(pDevIns);
6756	}
6757
6758	/**
6759	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeAbove4GB
6760	*/
6761	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSizeAbove4GB(PPDMDEVINS pDevIns)
6762	{
6763	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeAbove4GB(pDevIns);
6764	}
6765	#endif /* IN_RING3 */
6766
6767	/**
6768	* @copydoc PDMDEVHLPR3::pfnVMState
6769	*/
6770	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6771	{
6772	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6773	}
6774
6775	#ifdef IN_RING3
6776
6777	/**
6778	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6779	*/
6780	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6781	{
6782	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6783	}
6784
6785	/**
6786	* Set the VM error message
6787	*
6788	* @returns rc.
6789	* @param pDevIns The device instance.
6790	* @param rc VBox status code.
6791	* @param SRC_POS Use RT_SRC_POS.
6792	* @param pszFormat Error message format string.
6793	* @param ... Error message arguments.
6794	* @sa VMSetError
6795	*/
6796	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6797	const char *pszFormat, ...)
6798	{
6799	va_list va;
6800	va_start(va, pszFormat);
6801	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6802	va_end(va);
6803	return rc;
6804	}
6805
6806	/**
6807	* Set the VM runtime error message
6808	*
6809	* @returns VBox status code.
6810	* @param pDevIns The device instance.
6811	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
6812	* @param pszErrorId Error ID string.
6813	* @param pszFormat Error message format string.
6814	* @param ... Error message arguments.
6815	* @sa VMSetRuntimeError
6816	*/
6817	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6818	const char *pszFormat, ...)
6819	{
6820	va_list va;
6821	int rc;
6822	va_start(va, pszFormat);
6823	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6824	va_end(va);
6825	return rc;
6826	}
6827
6828	#endif /* IN_RING3 */
6829
6830	/**
6831	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6832	*
6833	* @returns VBox status code which must be passed up to the VMM. This will be
6834	* VINF_SUCCESS in non-strict builds.
6835	* @param pDevIns The device instance.
6836	* @param SRC_POS Use RT_SRC_POS.
6837	* @param pszFormat Message. (optional)
6838	* @param ... Message parameters.
6839	*/
6840	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6841	{
6842	#ifdef VBOX_STRICT
6843	# ifdef IN_RING3
6844	int rc;
6845	va_list args;
6846	va_start(args, pszFormat);
6847	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6848	va_end(args);
6849	return rc;
6850	# else
6851	NOREF(pDevIns);
6852	NOREF(pszFile);
6853	NOREF(iLine);
6854	NOREF(pszFunction);
6855	NOREF(pszFormat);
6856	return VINF_EM_DBG_STOP;
6857	# endif
6858	#else
6859	NOREF(pDevIns);
6860	NOREF(pszFile);
6861	NOREF(iLine);
6862	NOREF(pszFunction);
6863	NOREF(pszFormat);
6864	return VINF_SUCCESS;
6865	#endif
6866	}
6867
6868	#ifdef IN_RING3
6869
6870	/**
6871	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6872	*/
6873	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6874	{
6875	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6876	}
6877
6878	/**
6879	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6880	*/
6881	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6882	{
6883	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6884	}
6885
6886	/**
6887	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6888	*/
6889	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6890	{
6891	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6892	}
6893
6894	/**
6895	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
6896	*/
6897	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
6898	{
6899	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6900	}
6901
6902	/**
6903	* Same as pfnSTAMRegister except that the name is specified in a
6904	* RTStrPrintf like fashion.
6905	*
6906	* @returns VBox status.
6907	* @param pDevIns Device instance of the DMA.
6908	* @param pvSample Pointer to the sample.
6909	* @param enmType Sample type. This indicates what pvSample is
6910	* pointing at.
6911	* @param enmVisibility Visibility type specifying whether unused
6912	* statistics should be visible or not.
6913	* @param enmUnit Sample unit.
6914	* @param pszDesc Sample description.
6915	* @param pszName Sample name format string, unix path style. If
6916	* this does not start with a '/', the default
6917	* prefix will be prepended, otherwise it will be
6918	* used as-is.
6919	* @param ... Arguments to the format string.
6920	*/
6921	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6922	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6923	const char pszDesc, const char pszName, ...)
6924	{
6925	va_list va;
6926	va_start(va, pszName);
6927	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6928	va_end(va);
6929	}
6930
6931	/**
6932	* @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
6933	*/
6934	DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
6935	{
6936	return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
6937	}
6938
6939	/**
6940	* Registers the device with the default PCI bus.
6941	*
6942	* @returns VBox status code.
6943	* @param pDevIns The device instance.
6944	* @param pPciDev The PCI device structure.
6945	* This must be kept in the instance data.
6946	* The PCI configuration must be initialized before registration.
6947	*/
6948	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6949	{
6950	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
6951	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6952	}
6953
6954	/**
6955	* @copydoc PDMDEVHLPR3::pfnPCIRegister
6956	*/
6957	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6958	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6959	{
6960	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6961	}
6962
6963	/**
6964	* Initialize MSI emulation support for the first PCI device.
6965	*
6966	* @returns VBox status code.
6967	* @param pDevIns The device instance.
6968	* @param pMsiReg MSI emulation registration structure.
6969	*/
6970	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6971	{
6972	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6973	}
6974
6975	/**
6976	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6977	*/
6978	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6979	{
6980	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6981	}
6982
6983	/**
6984	* Registers a I/O port region for the default PCI device.
6985	*
6986	* @returns VBox status code.
6987	* @param pDevIns The device instance.
6988	* @param iRegion The region number.
6989	* @param cbRegion Size of the region.
6990	* @param hIoPorts Handle to the I/O port region.
6991	*/
6992	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
6993	{
6994	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6995	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
6996	}
6997
6998	/**
6999	* Registers a I/O port region for the default PCI device, custom map/unmap.
7000	*
7001	* @returns VBox status code.
7002	* @param pDevIns The device instance.
7003	* @param iRegion The region number.
7004	* @param cbRegion Size of the region.
7005	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7006	* callback will be invoked holding only the PDM lock.
7007	* The device lock will _not_ be taken (due to lock
7008	* order).
7009	*/
7010	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7011	PFNPCIIOREGIONMAP pfnMapUnmap)
7012	{
7013	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7014	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7015	UINT64_MAX, pfnMapUnmap);
7016	}
7017
7018	/**
7019	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7020	* and registering an I/O port region for the default PCI device.
7021	*
7022	* @returns VBox status code.
7023	* @param pDevIns The device instance to register the ports with.
7024	* @param cPorts The count of I/O ports in the region (the size).
7025	* @param iPciRegion The PCI device region.
7026	* @param pfnOut Pointer to function which is gonna handle OUT
7027	* operations. Optional.
7028	* @param pfnIn Pointer to function which is gonna handle IN operations.
7029	* Optional.
7030	* @param pvUser User argument to pass to the callbacks.
7031	* @param pszDesc Pointer to description string. This must not be freed.
7032	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7033	* coverage is allowed. This must not be freed.
7034	* @param phIoPorts Where to return the I/O port range handle.
7035	*
7036	*/
7037	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7038	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7039	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7040
7041	{
7042	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7043	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7044	if (RT_SUCCESS(rc))
7045	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7046	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7047	phIoPorts, NULL /pfnMapUnmap*/);
7048	return rc;
7049	}
7050
7051	/**
7052	* Registers an MMIO region for the default PCI device.
7053	*
7054	* @returns VBox status code.
7055	* @param pDevIns The device instance.
7056	* @param iRegion The region number.
7057	* @param cbRegion Size of the region.
7058	* @param enmType PCI_ADDRESS_SPACE_MEM or
7059	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7060	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7061	* @param hMmioRegion Handle to the MMIO region.
7062	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7063	* callback will be invoked holding only the PDM lock.
7064	* The device lock will _not_ be taken (due to lock
7065	* order).
7066	*/
7067	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7068	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7069	{
7070	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7071	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7072	hMmioRegion, pfnMapUnmap);
7073	}
7074
7075	/**
7076	* Registers an MMIO region for the default PCI device, extended version.
7077	*
7078	* @returns VBox status code.
7079	* @param pDevIns The device instance.
7080	* @param pPciDev The PCI device structure.
7081	* @param iRegion The region number.
7082	* @param cbRegion Size of the region.
7083	* @param enmType PCI_ADDRESS_SPACE_MEM or
7084	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7085	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7086	* @param hMmioRegion Handle to the MMIO region.
7087	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7088	* callback will be invoked holding only the PDM lock.
7089	* The device lock will _not_ be taken (due to lock
7090	* order).
7091	*/
7092	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7093	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7094	PFNPCIIOREGIONMAP pfnMapUnmap)
7095	{
7096	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7097	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7098	hMmioRegion, pfnMapUnmap);
7099	}
7100
7101	/**
7102	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7103	* and registering an MMIO region for the default PCI device.
7104	*
7105	* @returns VBox status code.
7106	* @param pDevIns The device instance to register the ports with.
7107	* @param cbRegion The size of the region in bytes.
7108	* @param iPciRegion The PCI device region.
7109	* @param enmType PCI_ADDRESS_SPACE_MEM or
7110	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7111	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7112	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7113	* @param pfnWrite Pointer to function which is gonna handle Write
7114	* operations.
7115	* @param pfnRead Pointer to function which is gonna handle Read
7116	* operations.
7117	* @param pvUser User argument to pass to the callbacks.
7118	* @param pszDesc Pointer to description string. This must not be freed.
7119	* @param phRegion Where to return the MMIO region handle.
7120	*
7121	*/
7122	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7123	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7124	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7125
7126	{
7127	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7128	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7129	if (RT_SUCCESS(rc))
7130	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7131	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7132	phRegion, NULL /pfnMapUnmap*/);
7133	return rc;
7134	}
7135
7136
7137	/**
7138	* Registers an MMIO2 region for the default PCI device.
7139	*
7140	* @returns VBox status code.
7141	* @param pDevIns The device instance.
7142	* @param iRegion The region number.
7143	* @param cbRegion Size of the region.
7144	* @param enmType PCI_ADDRESS_SPACE_MEM or
7145	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7146	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7147	* @param hMmio2Region Handle to the MMIO2 region.
7148	*/
7149	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7150	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7151	{
7152	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7153	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7154	hMmio2Region, NULL);
7155	}
7156
7157	/**
7158	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7159	* and registering an MMIO2 region for the default PCI device, extended edition.
7160	*
7161	* @returns VBox status code.
7162	* @param pDevIns The device instance to register the ports with.
7163	* @param cbRegion The size of the region in bytes.
7164	* @param iPciRegion The PCI device region.
7165	* @param enmType PCI_ADDRESS_SPACE_MEM or
7166	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7167	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7168	* @param pszDesc Pointer to description string. This must not be freed.
7169	* @param ppvMapping Where to store the address of the ring-3 mapping of
7170	* the memory.
7171	* @param phRegion Where to return the MMIO2 region handle.
7172	*
7173	*/
7174	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7175	PCIADDRESSSPACE enmType, const char *pszDesc,
7176	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7177
7178	{
7179	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7180	pszDesc, ppvMapping, phRegion);
7181	if (RT_SUCCESS(rc))
7182	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7183	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7184	phRegion, NULL /pfnCallback*/);
7185	return rc;
7186	}
7187
7188	/**
7189	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7190	* and registering an MMIO2 region for the default PCI device.
7191	*
7192	* @returns VBox status code.
7193	* @param pDevIns The device instance to register the ports with.
7194	* @param cbRegion The size of the region in bytes.
7195	* @param iPciRegion The PCI device region.
7196	* @param enmType PCI_ADDRESS_SPACE_MEM or
7197	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7198	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7199	* @param fMmio2Flags To be defined, must be zero.
7200	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7201	* callback will be invoked holding only the PDM lock.
7202	* The device lock will _not_ be taken (due to lock
7203	* order).
7204	* @param pszDesc Pointer to description string. This must not be freed.
7205	* @param ppvMapping Where to store the address of the ring-3 mapping of
7206	* the memory.
7207	* @param phRegion Where to return the MMIO2 region handle.
7208	*
7209	*/
7210	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7211	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7212	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
7213
7214	{
7215	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7216	pszDesc, ppvMapping, phRegion);
7217	if (RT_SUCCESS(rc))
7218	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7219	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7220	*phRegion, pfnMapUnmap);
7221	return rc;
7222	}
7223
7224	/**
7225	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7226	*/
7227	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7228	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7229	{
7230	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7231	}
7232
7233	/**
7234	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7235	*/
7236	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7237	unsigned cb, uint32_t *pu32Value)
7238	{
7239	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7240	}
7241
7242	/**
7243	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7244	*/
7245	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7246	unsigned cb, uint32_t u32Value)
7247	{
7248	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7249	}
7250
7251	#endif /* IN_RING3 */
7252
7253	/**
7254	* Bus master physical memory read from the default PCI device.
7255	*
7256	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7257	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7258	* @param pDevIns The device instance.
7259	* @param GCPhys Physical address start reading from.
7260	* @param pvBuf Where to put the read bits.
7261	* @param cbRead How many bytes to read.
7262	* @thread Any thread, but the call may involve the emulation thread.
7263	*/
7264	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7265	{
7266	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7267	}
7268
7269	/**
7270	* Bus master physical memory read - unknown data usage.
7271	*
7272	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7273	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7274	* @param pDevIns The device instance.
7275	* @param pPciDev The PCI device structure. If NULL the default
7276	* PCI device for this device instance is used.
7277	* @param GCPhys Physical address start reading from.
7278	* @param pvBuf Where to put the read bits.
7279	* @param cbRead How many bytes to read.
7280	* @thread Any thread, but the call may involve the emulation thread.
7281	*/
7282	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7283	{
7284	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7285	}
7286
7287	/**
7288	* Bus master physical memory read from the default PCI device.
7289	*
7290	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7291	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7292	* @param pDevIns The device instance.
7293	* @param GCPhys Physical address start reading from.
7294	* @param pvBuf Where to put the read bits.
7295	* @param cbRead How many bytes to read.
7296	* @thread Any thread, but the call may involve the emulation thread.
7297	*/
7298	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7299	{
7300	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7301	}
7302
7303	/**
7304	* Bus master physical memory read - reads meta data processed by the device.
7305	*
7306	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7307	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7308	* @param pDevIns The device instance.
7309	* @param pPciDev The PCI device structure. If NULL the default
7310	* PCI device for this device instance is used.
7311	* @param GCPhys Physical address start reading from.
7312	* @param pvBuf Where to put the read bits.
7313	* @param cbRead How many bytes to read.
7314	* @thread Any thread, but the call may involve the emulation thread.
7315	*/
7316	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7317	{
7318	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7319	}
7320
7321	/**
7322	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
7323	*
7324	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7325	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7326	* @param pDevIns The device instance.
7327	* @param GCPhys Physical address start reading from.
7328	* @param pvBuf Where to put the read bits.
7329	* @param cbRead How many bytes to read.
7330	* @thread Any thread, but the call may involve the emulation thread.
7331	*/
7332	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7333	{
7334	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7335	}
7336
7337	/**
7338	* Bus master physical memory read - read data will not be touched by the device.
7339	*
7340	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7341	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7342	* @param pDevIns The device instance.
7343	* @param pPciDev The PCI device structure. If NULL the default
7344	* PCI device for this device instance is used.
7345	* @param GCPhys Physical address start reading from.
7346	* @param pvBuf Where to put the read bits.
7347	* @param cbRead How many bytes to read.
7348	* @thread Any thread, but the call may involve the emulation thread.
7349	*/
7350	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7351	{
7352	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7353	}
7354
7355	/**
7356	* Bus master physical memory write from the default PCI device - unknown data usage.
7357	*
7358	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7359	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7360	* @param pDevIns The device instance.
7361	* @param GCPhys Physical address to write to.
7362	* @param pvBuf What to write.
7363	* @param cbWrite How many bytes to write.
7364	* @thread Any thread, but the call may involve the emulation thread.
7365	*/
7366	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7367	{
7368	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7369	}
7370
7371	/**
7372	* Bus master physical memory write - unknown data usage.
7373	*
7374	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7375	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7376	* @param pDevIns The device instance.
7377	* @param pPciDev The PCI device structure. If NULL the default
7378	* PCI device for this device instance is used.
7379	* @param GCPhys Physical address to write to.
7380	* @param pvBuf What to write.
7381	* @param cbWrite How many bytes to write.
7382	* @thread Any thread, but the call may involve the emulation thread.
7383	*/
7384	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7385	{
7386	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7387	}
7388
7389	/**
7390	* Bus master physical memory write from the default PCI device.
7391	*
7392	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7393	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7394	* @param pDevIns The device instance.
7395	* @param GCPhys Physical address to write to.
7396	* @param pvBuf What to write.
7397	* @param cbWrite How many bytes to write.
7398	* @thread Any thread, but the call may involve the emulation thread.
7399	*/
7400	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7401	{
7402	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7403	}
7404
7405	/**
7406	* Bus master physical memory write - written data was created/altered by the device.
7407	*
7408	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7409	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7410	* @param pDevIns The device instance.
7411	* @param pPciDev The PCI device structure. If NULL the default
7412	* PCI device for this device instance is used.
7413	* @param GCPhys Physical address to write to.
7414	* @param pvBuf What to write.
7415	* @param cbWrite How many bytes to write.
7416	* @thread Any thread, but the call may involve the emulation thread.
7417	*/
7418	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7419	{
7420	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7421	}
7422
7423	/**
7424	* Bus master physical memory write from the default PCI device.
7425	*
7426	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7427	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7428	* @param pDevIns The device instance.
7429	* @param GCPhys Physical address to write to.
7430	* @param pvBuf What to write.
7431	* @param cbWrite How many bytes to write.
7432	* @thread Any thread, but the call may involve the emulation thread.
7433	*/
7434	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7435	{
7436	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7437	}
7438
7439	/**
7440	* Bus master physical memory write - written data was not touched/created by the device.
7441	*
7442	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7443	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7444	* @param pDevIns The device instance.
7445	* @param pPciDev The PCI device structure. If NULL the default
7446	* PCI device for this device instance is used.
7447	* @param GCPhys Physical address to write to.
7448	* @param pvBuf What to write.
7449	* @param cbWrite How many bytes to write.
7450	* @thread Any thread, but the call may involve the emulation thread.
7451	*/
7452	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7453	{
7454	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7455	}
7456
7457	#ifdef IN_RING3
7458	/**
7459	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
7460	*/
7461	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7462	void **ppv, PPGMPAGEMAPLOCK pLock)
7463	{
7464	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7465	}
7466
7467	/**
7468	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
7469	*/
7470	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7471	void const **ppv, PPGMPAGEMAPLOCK pLock)
7472	{
7473	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7474	}
7475
7476	/**
7477	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
7478	*/
7479	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7480	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
7481	PPGMPAGEMAPLOCK paLocks)
7482	{
7483	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
7484	paLocks);
7485	}
7486
7487	/**
7488	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
7489	*/
7490	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7491	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
7492	PPGMPAGEMAPLOCK paLocks)
7493	{
7494	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
7495	papvPages, paLocks);
7496	}
7497	#endif /* IN_RING3 */
7498
7499	/**
7500	* Sets the IRQ for the default PCI device.
7501	*
7502	* @param pDevIns The device instance.
7503	* @param iIrq IRQ number to set.
7504	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7505	* @thread Any thread, but will involve the emulation thread.
7506	*/
7507	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7508	{
7509	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7510	}
7511
7512	/**
7513	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
7514	*/
7515	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7516	{
7517	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7518	}
7519
7520	/**
7521	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7522	* the request when not called from EMT.
7523	*
7524	* @param pDevIns The device instance.
7525	* @param iIrq IRQ number to set.
7526	* @param iLevel IRQ level.
7527	* @thread Any thread, but will involve the emulation thread.
7528	*/
7529	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7530	{
7531	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7532	}
7533
7534	/**
7535	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7536	*/
7537	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7538	{
7539	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7540	}
7541
7542	/**
7543	* @copydoc PDMDEVHLPR3::pfnISASetIrq
7544	*/
7545	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7546	{
7547	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7548	}
7549
7550	/**
7551	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7552	*/
7553	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7554	{
7555	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7556	}
7557
7558	#ifdef IN_RING3
7559
7560	/**
7561	* @copydoc PDMDEVHLPR3::pfnDriverAttach
7562	*/
7563	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
7564	{
7565	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7566	}
7567
7568	/**
7569	* @copydoc PDMDEVHLPR3::pfnDriverDetach
7570	*/
7571	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7572	{
7573	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7574	}
7575
7576	/**
7577	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
7578	*/
7579	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
7580	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
7581	{
7582	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
7583	}
7584
7585	/**
7586	* Reconfigures with a single driver reattachement, no config, noflags.
7587	* @sa PDMDevHlpDriverReconfigure
7588	*/
7589	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
7590	{
7591	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
7592	}
7593
7594	/**
7595	* Reconfigures with a two drivers reattachement, no config, noflags.
7596	* @sa PDMDevHlpDriverReconfigure
7597	*/
7598	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
7599	{
7600	char const * apszDrivers[2];
7601	apszDrivers[0] = pszDriver0;
7602	apszDrivers[1] = pszDriver1;
7603	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
7604	}
7605
7606	/**
7607	* @copydoc PDMDEVHLPR3::pfnQueueCreate
7608	*/
7609	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7610	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
7611	{
7612	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7613	}
7614
7615	#endif /* IN_RING3 */
7616
7617	/**
7618	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
7619	*/
7620	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7621	{
7622	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7623	}
7624
7625	/**
7626	* @copydoc PDMDEVHLPR3::pfnQueueInsert
7627	*/
7628	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7629	{
7630	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7631	}
7632
7633	/**
7634	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7635	*/
7636	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7637	{
7638	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7639	}
7640
7641	#ifdef IN_RING3
7642	/**
7643	* @copydoc PDMDEVHLPR3::pfnTaskCreate
7644	*/
7645	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7646	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
7647	{
7648	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7649	}
7650	#endif
7651
7652	/**
7653	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
7654	*/
7655	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7656	{
7657	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7658	}
7659
7660	#ifdef IN_RING3
7661
7662	/**
7663	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7664	*/
7665	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7666	{
7667	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7668	}
7669
7670	/**
7671	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7672	*/
7673	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7674	{
7675	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7676	}
7677
7678	#endif /* IN_RING3 */
7679
7680	/**
7681	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7682	*/
7683	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7684	{
7685	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7686	}
7687
7688	/**
7689	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7690	*/
7691	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7692	{
7693	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7694	}
7695
7696	/**
7697	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7698	*/
7699	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7700	{
7701	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7702	}
7703
7704	/**
7705	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7706	*/
7707	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7708	{
7709	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7710	}
7711
7712	/**
7713	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7714	*/
7715	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7716	{
7717	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7718	}
7719
7720	#ifdef IN_RING3
7721
7722	/**
7723	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7724	*/
7725	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7726	{
7727	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7728	}
7729
7730	/**
7731	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7732	*/
7733	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7734	{
7735	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7736	}
7737
7738	#endif /* IN_RING3 */
7739
7740	/**
7741	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7742	*/
7743	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7744	{
7745	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7746	}
7747
7748	/**
7749	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7750	*/
7751	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7752	{
7753	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7754	}
7755
7756	/**
7757	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7758	*/
7759	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7760	{
7761	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7762	}
7763
7764	/**
7765	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7766	*/
7767	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7768	{
7769	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7770	}
7771
7772	/**
7773	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7774	*/
7775	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7776	{
7777	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7778	}
7779
7780	/**
7781	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7782	*/
7783	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7784	{
7785	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7786	}
7787
7788	#ifdef IN_RING3
7789
7790	/**
7791	* Initializes a PDM critical section.
7792	*
7793	* The PDM critical sections are derived from the IPRT critical sections, but
7794	* works in RC and R0 as well.
7795	*
7796	* @returns VBox status code.
7797	* @param pDevIns The device instance.
7798	* @param pCritSect Pointer to the critical section.
7799	* @param SRC_POS Use RT_SRC_POS.
7800	* @param pszNameFmt Format string for naming the critical section.
7801	* For statistics and lock validation.
7802	* @param ... Arguments for the format string.
7803	*/
7804	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7805	const char *pszNameFmt, ...)
7806	{
7807	int rc;
7808	va_list va;
7809	va_start(va, pszNameFmt);
7810	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7811	va_end(va);
7812	return rc;
7813	}
7814
7815	#endif /* IN_RING3 */
7816
7817	/**
7818	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7819	*/
7820	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7821	{
7822	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7823	}
7824
7825	/**
7826	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7827	*/
7828	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7829	{
7830	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7831	}
7832
7833	/**
7834	* Enters a PDM critical section.
7835	*
7836	* @returns VINF_SUCCESS if entered successfully.
7837	* @returns rcBusy when encountering a busy critical section in RC/R0.
7838	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7839	* during the operation.
7840	*
7841	* @param pDevIns The device instance.
7842	* @param pCritSect The PDM critical section to enter.
7843	* @param rcBusy The status code to return when we're in RC or R0
7844	* and the section is busy. Pass VINF_SUCCESS to
7845	* acquired the critical section thru a ring-3
7846	* call if necessary.
7847	*
7848	* @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
7849	* possible failures in ring-0 or at least apply
7850	* PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
7851	* function.
7852	*
7853	* @sa PDMCritSectEnter
7854	*/
7855	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7856	{
7857	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7858	}
7859
7860	/**
7861	* Enters a PDM critical section, with location information for debugging.
7862	*
7863	* @returns VINF_SUCCESS if entered successfully.
7864	* @returns rcBusy when encountering a busy critical section in RC/R0.
7865	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7866	* during the operation.
7867	*
7868	* @param pDevIns The device instance.
7869	* @param pCritSect The PDM critical section to enter.
7870	* @param rcBusy The status code to return when we're in RC or R0
7871	* and the section is busy. Pass VINF_SUCCESS to
7872	* acquired the critical section thru a ring-3
7873	* call if necessary.
7874	* @param uId Some kind of locking location ID. Typically a
7875	* return address up the stack. Optional (0).
7876	* @param SRC_POS The source position where to lock is being
7877	* acquired from. Optional.
7878	* @sa PDMCritSectEnterDebug
7879	*/
7880	DECLINLINE(DECL_CHECK_RETURN(int))
7881	PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7882	{
7883	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7884	}
7885
7886	/**
7887	* Try enter a critical section.
7888	*
7889	* @retval VINF_SUCCESS on success.
7890	* @retval VERR_SEM_BUSY if the critsect was owned.
7891	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
7892	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7893	* during the operation.
7894	*
7895	* @param pDevIns The device instance.
7896	* @param pCritSect The critical section.
7897	* @sa PDMCritSectTryEnter
7898	*/
7899	DECLINLINE(DECL_CHECK_RETURN(int))
7900	PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7901	{
7902	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7903	}
7904
7905	/**
7906	* Try enter a critical section, with location information for debugging.
7907	*
7908	* @retval VINF_SUCCESS on success.
7909	* @retval VERR_SEM_BUSY if the critsect was owned.
7910	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
7911	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7912	* during the operation.
7913	*
7914	* @param pDevIns The device instance.
7915	* @param pCritSect The critical section.
7916	* @param uId Some kind of locking location ID. Typically a
7917	* return address up the stack. Optional (0).
7918	* @param SRC_POS The source position where to lock is being
7919	* acquired from. Optional.
7920	* @sa PDMCritSectTryEnterDebug
7921	*/
7922	DECLINLINE(DECL_CHECK_RETURN(int))
7923	PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7924	{
7925	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7926	}
7927
7928	/**
7929	* Leaves a critical section entered with PDMCritSectEnter().
7930	*
7931	* @returns Indication whether we really exited the critical section.
7932	* @retval VINF_SUCCESS if we really exited.
7933	* @retval VINF_SEM_NESTED if we only reduced the nesting count.
7934	* @retval VERR_NOT_OWNER if you somehow ignore release assertions.
7935	*
7936	* @param pDevIns The device instance.
7937	* @param pCritSect The PDM critical section to leave.
7938	* @sa PDMCritSectLeave
7939	*/
7940	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7941	{
7942	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7943	}
7944
7945	/**
7946	* @see PDMCritSectIsOwner
7947	*/
7948	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7949	{
7950	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7951	}
7952
7953	/**
7954	* @see PDMCritSectIsInitialized
7955	*/
7956	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7957	{
7958	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
7959	}
7960
7961	/**
7962	* @see PDMCritSectHasWaiters
7963	*/
7964	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7965	{
7966	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
7967	}
7968
7969	/**
7970	* @see PDMCritSectGetRecursion
7971	*/
7972	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7973	{
7974	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
7975	}
7976
7977	#if defined(IN_RING3) \|\| defined(IN_RING0)
7978	/**
7979	* @see PDMHCCritSectScheduleExitEvent
7980	*/
7981	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
7982	{
7983	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
7984	}
7985	#endif
7986
7987	/* Strict build: Remap the two enter calls to the debug versions. */
7988	#ifdef VBOX_STRICT
7989	# ifdef IPRT_INCLUDED_asm_h
7990	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7991	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7992	# else
7993	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
7994	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
7995	# endif
7996	#endif
7997
7998	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
7999
8000	/**
8001	* Deletes the critical section.
8002	*
8003	* @returns VBox status code.
8004	* @param pDevIns The device instance.
8005	* @param pCritSect The PDM critical section to destroy.
8006	* @sa PDMR3CritSectDelete
8007	*/
8008	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8009	{
8010	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8011	}
8012
8013	/**
8014	* Initializes a PDM read/write critical section.
8015	*
8016	* The PDM read/write critical sections are derived from the IPRT critical
8017	* sections, but works in RC and R0 as well.
8018	*
8019	* @returns VBox status code.
8020	* @param pDevIns The device instance.
8021	* @param pCritSect Pointer to the read/write critical section.
8022	* @param SRC_POS Use RT_SRC_POS.
8023	* @param pszNameFmt Format string for naming the critical section.
8024	* For statistics and lock validation.
8025	* @param ... Arguments for the format string.
8026	*/
8027	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
8028	const char *pszNameFmt, ...)
8029	{
8030	int rc;
8031	va_list va;
8032	va_start(va, pszNameFmt);
8033	rc = pDevIns->pHlpR3->pfnCritSectRwInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8034	va_end(va);
8035	return rc;
8036	}
8037
8038	/**
8039	* Deletes the read/write critical section.
8040	*
8041	* @returns VBox status code.
8042	* @param pDevIns The device instance.
8043	* @param pCritSect The PDM read/write critical section to destroy.
8044	* @sa PDMR3CritSectRwDelete
8045	*/
8046	DECLINLINE(int) PDMDevHlpCritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8047	{
8048	return pDevIns->pHlpR3->pfnCritSectRwDelete(pDevIns, pCritSect);
8049	}
8050
8051	#endif /* IN_RING3 */
8052
8053	/**
8054	* @sa PDMCritSectRwEnterShared, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8055	*/
8056	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8057	{
8058	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterShared(pDevIns, pCritSect, rcBusy);
8059	}
8060
8061	/**
8062	* @sa PDMCritSectRwEnterSharedDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8063	*/
8064	DECLINLINE(DECL_CHECK_RETURN(int))
8065	PDMDevHlpCritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8066	{
8067	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterSharedDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8068	}
8069
8070	/**
8071	* @sa PDMCritSectRwTryEnterShared
8072	*/
8073	DECLINLINE(DECL_CHECK_RETURN(int))
8074	PDMDevHlpCritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8075	{
8076	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterShared(pDevIns, pCritSect);
8077	}
8078
8079	/**
8080	* @sa PDMCritSectRwTryEnterSharedDebug
8081	*/
8082	DECLINLINE(DECL_CHECK_RETURN(int))
8083	PDMDevHlpCritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8084	{
8085	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterSharedDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8086	}
8087
8088	/**
8089	* @sa PDMCritSectRwLeaveShared
8090	*/
8091	DECLINLINE(int) PDMDevHlpCritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8092	{
8093	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveShared(pDevIns, pCritSect);
8094	}
8095
8096	/**
8097	* @sa PDMCritSectRwEnterExcl, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8098	*/
8099	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8100	{
8101	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy);
8102	}
8103
8104	/**
8105	* @sa PDMCritSectRwEnterExclDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8106	*/
8107	DECLINLINE(DECL_CHECK_RETURN(int))
8108	PDMDevHlpCritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8109	{
8110	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExclDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8111	}
8112
8113	/**
8114	* @sa PDMCritSectRwTryEnterExcl
8115	*/
8116	DECLINLINE(DECL_CHECK_RETURN(int))
8117	PDMDevHlpCritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8118	{
8119	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExcl(pDevIns, pCritSect);
8120	}
8121
8122	/**
8123	* @sa PDMCritSectRwTryEnterExclDebug
8124	*/
8125	DECLINLINE(DECL_CHECK_RETURN(int))
8126	PDMDevHlpCritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8127	{
8128	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExclDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8129	}
8130
8131	/**
8132	* @sa PDMCritSectRwLeaveExcl
8133	*/
8134	DECLINLINE(int) PDMDevHlpCritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8135	{
8136	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveExcl(pDevIns, pCritSect);
8137	}
8138
8139	/**
8140	* @see PDMCritSectRwIsWriteOwner
8141	*/
8142	DECLINLINE(bool) PDMDevHlpCritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8143	{
8144	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsWriteOwner(pDevIns, pCritSect);
8145	}
8146
8147	/**
8148	* @see PDMCritSectRwIsReadOwner
8149	*/
8150	DECLINLINE(bool) PDMDevHlpCritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
8151	{
8152	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsReadOwner(pDevIns, pCritSect, fWannaHear);
8153	}
8154
8155	/**
8156	* @see PDMCritSectRwGetWriteRecursion
8157	*/
8158	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8159	{
8160	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriteRecursion(pDevIns, pCritSect);
8161	}
8162
8163	/**
8164	* @see PDMCritSectRwGetWriterReadRecursion
8165	*/
8166	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8167	{
8168	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriterReadRecursion(pDevIns, pCritSect);
8169	}
8170
8171	/**
8172	* @see PDMCritSectRwGetReadCount
8173	*/
8174	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8175	{
8176	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetReadCount(pDevIns, pCritSect);
8177	}
8178
8179	/**
8180	* @see PDMCritSectRwIsInitialized
8181	*/
8182	DECLINLINE(bool) PDMDevHlpCritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8183	{
8184	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsInitialized(pDevIns, pCritSect);
8185	}
8186
8187	/* Strict build: Remap the two enter calls to the debug versions. */
8188	#ifdef VBOX_STRICT
8189	# ifdef IPRT_INCLUDED_asm_h
8190	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8191	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8192	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8193	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8194	# else
8195	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8196	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8197	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8198	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8199	# endif
8200	#endif
8201
8202	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8203
8204	/**
8205	* @copydoc PDMDEVHLPR3::pfnThreadCreate
8206	*/
8207	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
8208	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
8209	{
8210	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
8211	}
8212
8213	/**
8214	* @copydoc PDMR3ThreadDestroy
8215	* @param pDevIns The device instance.
8216	*/
8217	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
8218	{
8219	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
8220	}
8221
8222	/**
8223	* @copydoc PDMR3ThreadIAmSuspending
8224	* @param pDevIns The device instance.
8225	*/
8226	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8227	{
8228	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
8229	}
8230
8231	/**
8232	* @copydoc PDMR3ThreadIAmRunning
8233	* @param pDevIns The device instance.
8234	*/
8235	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8236	{
8237	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
8238	}
8239
8240	/**
8241	* @copydoc PDMR3ThreadSleep
8242	* @param pDevIns The device instance.
8243	*/
8244	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
8245	{
8246	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
8247	}
8248
8249	/**
8250	* @copydoc PDMR3ThreadSuspend
8251	* @param pDevIns The device instance.
8252	*/
8253	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8254	{
8255	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
8256	}
8257
8258	/**
8259	* @copydoc PDMR3ThreadResume
8260	* @param pDevIns The device instance.
8261	*/
8262	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8263	{
8264	return pDevIns->pHlpR3->pfnThreadResume(pThread);
8265	}
8266
8267	/**
8268	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
8269	*/
8270	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
8271	{
8272	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
8273	}
8274
8275	/**
8276	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
8277	*/
8278	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
8279	{
8280	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
8281	}
8282
8283	/**
8284	* @copydoc PDMDEVHLPR3::pfnA20Set
8285	*/
8286	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
8287	{
8288	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
8289	}
8290
8291	/**
8292	* @copydoc PDMDEVHLPR3::pfnRTCRegister
8293	*/
8294	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
8295	{
8296	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
8297	}
8298
8299	/**
8300	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
8301	*/
8302	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
8303	{
8304	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
8305	}
8306
8307	/**
8308	* @copydoc PDMDEVHLPR3::pfnIommuRegister
8309	*/
8310	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
8311	{
8312	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
8313	}
8314
8315	/**
8316	* @copydoc PDMDEVHLPR3::pfnPICRegister
8317	*/
8318	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8319	{
8320	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
8321	}
8322
8323	/**
8324	* @copydoc PDMDEVHLPR3::pfnApicRegister
8325	*/
8326	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
8327	{
8328	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
8329	}
8330
8331	/**
8332	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
8333	*/
8334	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8335	{
8336	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
8337	}
8338
8339	/**
8340	* @copydoc PDMDEVHLPR3::pfnHpetRegister
8341	*/
8342	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
8343	{
8344	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
8345	}
8346
8347	/**
8348	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
8349	*/
8350	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
8351	{
8352	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
8353	}
8354
8355	/**
8356	* @copydoc PDMDEVHLPR3::pfnDMACRegister
8357	*/
8358	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
8359	{
8360	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
8361	}
8362
8363	/**
8364	* @copydoc PDMDEVHLPR3::pfnDMARegister
8365	*/
8366	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
8367	{
8368	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
8369	}
8370
8371	/**
8372	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
8373	*/
8374	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
8375	{
8376	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
8377	}
8378
8379	/**
8380	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
8381	*/
8382	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
8383	{
8384	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
8385	}
8386
8387	/**
8388	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
8389	*/
8390	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
8391	{
8392	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
8393	}
8394
8395	/**
8396	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
8397	*/
8398	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
8399	{
8400	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
8401	}
8402
8403	/**
8404	* @copydoc PDMDEVHLPR3::pfnDMASchedule
8405	*/
8406	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
8407	{
8408	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
8409	}
8410
8411	/**
8412	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
8413	*/
8414	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
8415	{
8416	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
8417	}
8418
8419	/**
8420	* @copydoc PDMDEVHLPR3::pfnCMOSRead
8421	*/
8422	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
8423	{
8424	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
8425	}
8426
8427	/**
8428	* @copydoc PDMDEVHLPR3::pfnCallR0
8429	*/
8430	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
8431	{
8432	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
8433	}
8434
8435	/**
8436	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
8437	*/
8438	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
8439	{
8440	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
8441	}
8442
8443	/**
8444	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
8445	*/
8446	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
8447	{
8448	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
8449	}
8450
8451	/**
8452	* @copydoc PDMDEVHLPR3::pfnGetUVM
8453	*/
8454	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
8455	{
8456	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
8457	}
8458
8459	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
8460
8461	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8462
8463	/**
8464	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
8465	*/
8466	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
8467	{
8468	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
8469	}
8470
8471	/**
8472	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
8473	*/
8474	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
8475	{
8476	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
8477	}
8478
8479	/**
8480	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
8481	*/
8482	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8483	{
8484	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
8485	}
8486
8487	/**
8488	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
8489	*/
8490	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
8491	{
8492	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
8493	}
8494
8495	/**
8496	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
8497	*/
8498	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8499	{
8500	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
8501	}
8502
8503	/**
8504	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
8505	*/
8506	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
8507	{
8508	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
8509	}
8510
8511	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
8512
8513	/**
8514	* @copydoc PDMDEVHLPR3::pfnGetVM
8515	*/
8516	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
8517	{
8518	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
8519	}
8520
8521	/**
8522	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
8523	*/
8524	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
8525	{
8526	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
8527	}
8528
8529	/**
8530	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
8531	*/
8532	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
8533	{
8534	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
8535	}
8536
8537	/**
8538	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
8539	*/
8540	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
8541	{
8542	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
8543	}
8544
8545	/**
8546	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8547	*/
8548	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8549	{
8550	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8551	}
8552
8553	/**
8554	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8555	*/
8556	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8557	{
8558	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8559	}
8560
8561	#ifdef IN_RING3
8562
8563	/**
8564	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8565	*/
8566	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8567	{
8568	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
8569	}
8570
8571	/**
8572	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
8573	*/
8574	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
8575	{
8576	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
8577	}
8578
8579	/**
8580	* @copydoc PDMDEVHLPR3::pfnVMReset
8581	*/
8582	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
8583	{
8584	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
8585	}
8586
8587	/**
8588	* @copydoc PDMDEVHLPR3::pfnVMSuspend
8589	*/
8590	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8591	{
8592	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8593	}
8594
8595	/**
8596	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8597	*/
8598	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8599	{
8600	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8601	}
8602
8603	/**
8604	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
8605	*/
8606	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8607	{
8608	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8609	}
8610
8611	#endif /* IN_RING3 */
8612
8613	/**
8614	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8615	*/
8616	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8617	{
8618	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8619	}
8620
8621	#ifdef IN_RING3
8622
8623	/**
8624	* @copydoc PDMDEVHLPR3::pfnGetCpuId
8625	*/
8626	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
8627	{
8628	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8629	}
8630
8631	/**
8632	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8633	*/
8634	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8635	{
8636	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8637	}
8638
8639	/**
8640	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8641	*/
8642	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8643	{
8644	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8645	}
8646
8647	/**
8648	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
8649	*/
8650	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
8651	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
8652	const char pszHandlerR0, const char pszPfHandlerR0,
8653	const char pszHandlerRC, const char pszPfHandlerRC,
8654	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
8655	{
8656	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
8657	pszHandlerR0, pszPfHandlerR0,
8658	pszHandlerRC, pszPfHandlerRC,
8659	pszDesc, phType);
8660	}
8661
8662	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
8663	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8664	do { \
8665	uint32_t u32GetEnumTmp = 0; \
8666	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
8667	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8668	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
8669	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
8670	} while (0)
8671
8672	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
8673	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8674	do { \
8675	uint8_t bGetEnumTmp = 0; \
8676	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
8677	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8678	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
8679	} while (0)
8680
8681	#endif /* IN_RING3 */
8682
8683	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
8684	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
8685
8686	/**
8687	* Callbacks for VBoxDeviceRegister().
8688	*/
8689	typedef struct PDMDEVREGCB
8690	{
8691	/** Interface version.
8692	* This is set to PDM_DEVREG_CB_VERSION. */
8693	uint32_t u32Version;
8694
8695	/**
8696	* Registers a device with the current VM instance.
8697	*
8698	* @returns VBox status code.
8699	* @param pCallbacks Pointer to the callback table.
8700	* @param pReg Pointer to the device registration record.
8701	* This data must be permanent and readonly.
8702	*/
8703	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
8704	} PDMDEVREGCB;
8705
8706	/** Current version of the PDMDEVREGCB structure. */
8707	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
8708
8709
8710	/**
8711	* The VBoxDevicesRegister callback function.
8712	*
8713	* PDM will invoke this function after loading a device module and letting
8714	* the module decide which devices to register and how to handle conflicts.
8715	*
8716	* @returns VBox status code.
8717	* @param pCallbacks Pointer to the callback table.
8718	* @param u32Version VBox version number.
8719	*/
8720	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
8721
8722	/** @} */
8723
8724	RT_C_DECLS_END
8725
8726	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 91909

Download in other formats: