pdmdev.h@ 91928

Last change on this file since 91928 was 91928, checked in by vboxsync, 3 years ago
VMM,Devices: Eliminate direct calls to PGMHandlerPhysical* APIs and introduce callbacks in the device helper callback table, bugref:10074
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File size: 383.9 KB

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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmcritsectrw.h>
34	#include <VBox/vmm/pdmqueue.h>
35	#include <VBox/vmm/pdmtask.h>
36	#ifdef IN_RING3
37	# include <VBox/vmm/pdmthread.h>
38	#endif
39	#include <VBox/vmm/pdmifs.h>
40	#include <VBox/vmm/pdmins.h>
41	#include <VBox/vmm/pdmcommon.h>
42	#include <VBox/vmm/pdmpcidev.h>
43	#include <VBox/vmm/iom.h>
44	#include <VBox/vmm/mm.h>
45	#include <VBox/vmm/tm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/cfgm.h>
48	#include <VBox/vmm/cpum.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
51	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
52	#include <VBox/msi.h>
53	#include <iprt/stdarg.h>
54	#include <iprt/list.h>
55
56
57	RT_C_DECLS_BEGIN
58
59	/** @defgroup grp_pdm_device The PDM Devices API
60	* @ingroup grp_pdm
61	* @{
62	*/
63
64	/**
65	* Construct a device instance for a VM.
66	*
67	* @returns VBox status.
68	* @param pDevIns The device instance data. If the registration structure
69	* is needed, it can be accessed thru pDevIns->pReg.
70	* @param iInstance Instance number. Use this to figure out which registers
71	* and such to use. The instance number is also found in
72	* pDevIns->iInstance, but since it's likely to be
73	* frequently used PDM passes it as parameter.
74	* @param pCfg Configuration node handle for the driver. This is
75	* expected to be in high demand in the constructor and is
76	* therefore passed as an argument. When using it at other
77	* times, it can be found in pDevIns->pCfg.
78	*/
79	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
80	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
81	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
82
83	/**
84	* Destruct a device instance.
85	*
86	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
87	* resources can be freed correctly.
88	*
89	* @returns VBox status.
90	* @param pDevIns The device instance data.
91	*
92	* @remarks The device critical section is not entered. The routine may delete
93	* the critical section, so the caller cannot exit it.
94	*/
95	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
96	/** Pointer to a FNPDMDEVDESTRUCT() function. */
97	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
98
99	/**
100	* Device relocation callback.
101	*
102	* This is called when the instance data has been relocated in raw-mode context
103	* (RC). It is also called when the RC hypervisor selects changes. The device
104	* must fixup all necessary pointers and re-query all interfaces to other RC
105	* devices and drivers.
106	*
107	* Before the RC code is executed the first time, this function will be called
108	* with a 0 delta so RC pointer calculations can be one in one place.
109	*
110	* @param pDevIns Pointer to the device instance.
111	* @param offDelta The relocation delta relative to the old location.
112	*
113	* @remarks A relocation CANNOT fail.
114	*
115	* @remarks The device critical section is not entered. The relocations should
116	* not normally require any locking.
117	*/
118	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
119	/** Pointer to a FNPDMDEVRELOCATE() function. */
120	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
121
122	/**
123	* Power On notification.
124	*
125	* @returns VBox status.
126	* @param pDevIns The device instance data.
127	*
128	* @remarks Caller enters the device critical section.
129	*/
130	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
131	/** Pointer to a FNPDMDEVPOWERON() function. */
132	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
133
134	/**
135	* Reset notification.
136	*
137	* @returns VBox status.
138	* @param pDevIns The device instance data.
139	*
140	* @remarks Caller enters the device critical section.
141	*/
142	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
143	/** Pointer to a FNPDMDEVRESET() function. */
144	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
145
146	/**
147	* Soft reset notification.
148	*
149	* This is mainly for emulating the 286 style protected mode exits, in which
150	* most devices should remain in their current state.
151	*
152	* @returns VBox status.
153	* @param pDevIns The device instance data.
154	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
155	*
156	* @remarks Caller enters the device critical section.
157	*/
158	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
159	/** Pointer to a FNPDMDEVSOFTRESET() function. */
160	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
161
162	/** @name PDMVMRESET_F_XXX - VM reset flags.
163	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
164	* reset via PDMDevHlpVMReset.
165	* @{ */
166	/** Unknown reason. */
167	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
168	/** GIM triggered reset. */
169	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
170	/** The last source always causing hard resets. */
171	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
172	/** ACPI triggered reset. */
173	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
174	/** PS/2 system port A (92h) reset. */
175	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
176	/** Keyboard reset. */
177	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
178	/** Tripple fault. */
179	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
180	/** Reset source mask. */
181	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
182	/** @} */
183
184	/**
185	* Suspend notification.
186	*
187	* @returns VBox status.
188	* @param pDevIns The device instance data.
189	* @thread EMT(0)
190	*
191	* @remarks Caller enters the device critical section.
192	*/
193	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
194	/** Pointer to a FNPDMDEVSUSPEND() function. */
195	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
196
197	/**
198	* Resume notification.
199	*
200	* @returns VBox status.
201	* @param pDevIns The device instance data.
202	*
203	* @remarks Caller enters the device critical section.
204	*/
205	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
206	/** Pointer to a FNPDMDEVRESUME() function. */
207	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
208
209	/**
210	* Power Off notification.
211	*
212	* This is always called when VMR3PowerOff is called.
213	* There will be no callback when hot plugging devices.
214	*
215	* @param pDevIns The device instance data.
216	* @thread EMT(0)
217	*
218	* @remarks Caller enters the device critical section.
219	*/
220	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
221	/** Pointer to a FNPDMDEVPOWEROFF() function. */
222	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
223
224	/**
225	* Attach command.
226	*
227	* This is called to let the device attach to a driver for a specified LUN
228	* at runtime. This is not called during VM construction, the device
229	* constructor has to attach to all the available drivers.
230	*
231	* This is like plugging in the keyboard or mouse after turning on the PC.
232	*
233	* @returns VBox status code.
234	* @param pDevIns The device instance.
235	* @param iLUN The logical unit which is being attached.
236	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
237	*
238	* @remarks Caller enters the device critical section.
239	*/
240	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
241	/** Pointer to a FNPDMDEVATTACH() function. */
242	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
243
244	/**
245	* Detach notification.
246	*
247	* This is called when a driver is detaching itself from a LUN of the device.
248	* The device should adjust its state to reflect this.
249	*
250	* This is like unplugging the network cable to use it for the laptop or
251	* something while the PC is still running.
252	*
253	* @param pDevIns The device instance.
254	* @param iLUN The logical unit which is being detached.
255	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
256	*
257	* @remarks Caller enters the device critical section.
258	*/
259	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
260	/** Pointer to a FNPDMDEVDETACH() function. */
261	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
262
263	/**
264	* Query the base interface of a logical unit.
265	*
266	* @returns VBOX status code.
267	* @param pDevIns The device instance.
268	* @param iLUN The logicial unit to query.
269	* @param ppBase Where to store the pointer to the base interface of the LUN.
270	*
271	* @remarks The device critical section is not entered.
272	*/
273	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
274	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
275	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
276
277	/**
278	* Init complete notification (after ring-0 & RC init since 5.1).
279	*
280	* This can be done to do communication with other devices and other
281	* initialization which requires everything to be in place.
282	*
283	* @returns VBOX status code.
284	* @param pDevIns The device instance.
285	*
286	* @remarks Caller enters the device critical section.
287	*/
288	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
289	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
290	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
291
292
293	/**
294	* The context of a pfnMemSetup call.
295	*/
296	typedef enum PDMDEVMEMSETUPCTX
297	{
298	/** Invalid zero value. */
299	PDMDEVMEMSETUPCTX_INVALID = 0,
300	/** After construction. */
301	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
302	/** After reset. */
303	PDMDEVMEMSETUPCTX_AFTER_RESET,
304	/** Type size hack. */
305	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
306	} PDMDEVMEMSETUPCTX;
307
308
309	/**
310	* PDM Device Registration Structure.
311	*
312	* This structure is used when registering a device from VBoxInitDevices() in HC
313	* Ring-3. PDM will continue use till the VM is terminated.
314	*
315	* @note The first part is the same in every context.
316	*/
317	typedef struct PDMDEVREGR3
318	{
319	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
320	uint32_t u32Version;
321	/** Reserved, must be zero. */
322	uint32_t uReserved0;
323	/** Device name, must match the ring-3 one. */
324	char szName[32];
325	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
326	uint32_t fFlags;
327	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
328	uint32_t fClass;
329	/** Maximum number of instances (per VM). */
330	uint32_t cMaxInstances;
331	/** The shared data structure version number. */
332	uint32_t uSharedVersion;
333	/** Size of the instance data. */
334	uint32_t cbInstanceShared;
335	/** Size of the ring-0 instance data. */
336	uint32_t cbInstanceCC;
337	/** Size of the raw-mode instance data. */
338	uint32_t cbInstanceRC;
339	/** Max number of PCI devices. */
340	uint16_t cMaxPciDevices;
341	/** Max number of MSI-X vectors in any of the PCI devices. */
342	uint16_t cMaxMsixVectors;
343	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
344	* remain unchanged from registration till VM destruction. */
345	const char *pszDescription;
346
347	/** Name of the raw-mode context module (no path).
348	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
349	const char *pszRCMod;
350	/** Name of the ring-0 module (no path).
351	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
352	const char *pszR0Mod;
353
354	/** Construct instance - required. */
355	PFNPDMDEVCONSTRUCT pfnConstruct;
356	/** Destruct instance - optional.
357	* Critical section NOT entered (will be destroyed). */
358	PFNPDMDEVDESTRUCT pfnDestruct;
359	/** Relocation command - optional.
360	* Critical section NOT entered. */
361	PFNPDMDEVRELOCATE pfnRelocate;
362	/**
363	* Memory setup callback.
364	*
365	* @param pDevIns The device instance data.
366	* @param enmCtx Indicates the context of the call.
367	* @remarks The critical section is entered prior to calling this method.
368	*/
369	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
370	/** Power on notification - optional.
371	* Critical section is entered. */
372	PFNPDMDEVPOWERON pfnPowerOn;
373	/** Reset notification - optional.
374	* Critical section is entered. */
375	PFNPDMDEVRESET pfnReset;
376	/** Suspend notification - optional.
377	* Critical section is entered. */
378	PFNPDMDEVSUSPEND pfnSuspend;
379	/** Resume notification - optional.
380	* Critical section is entered. */
381	PFNPDMDEVRESUME pfnResume;
382	/** Attach command - optional.
383	* Critical section is entered. */
384	PFNPDMDEVATTACH pfnAttach;
385	/** Detach notification - optional.
386	* Critical section is entered. */
387	PFNPDMDEVDETACH pfnDetach;
388	/** Query a LUN base interface - optional.
389	* Critical section is NOT entered. */
390	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
391	/** Init complete notification - optional.
392	* Critical section is entered. */
393	PFNPDMDEVINITCOMPLETE pfnInitComplete;
394	/** Power off notification - optional.
395	* Critical section is entered. */
396	PFNPDMDEVPOWEROFF pfnPowerOff;
397	/** Software system reset notification - optional.
398	* Critical section is entered. */
399	PFNPDMDEVSOFTRESET pfnSoftReset;
400
401	/** @name Reserved for future extensions, must be zero.
402	* @{ */
403	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
406	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
407	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
408	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
409	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
410	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
411	/** @} */
412
413	/** Initialization safty marker. */
414	uint32_t u32VersionEnd;
415	} PDMDEVREGR3;
416	/** Pointer to a PDM Device Structure. */
417	typedef PDMDEVREGR3 *PPDMDEVREGR3;
418	/** Const pointer to a PDM Device Structure. */
419	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
420	/** Current DEVREGR3 version number. */
421	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
422
423
424	/** PDM Device Flags.
425	* @{ */
426	/** This flag is used to indicate that the device has a R0 component. */
427	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
428	/** Requires the ring-0 component, ignore configuration values. */
429	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
430	/** Requires the ring-0 component, ignore configuration values. */
431	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
432
433	/** This flag is used to indicate that the device has a RC component. */
434	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
435	/** Requires the raw-mode component, ignore configuration values. */
436	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
437	/** Requires the raw-mode component, ignore configuration values. */
438	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
439
440	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
441	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
442
443	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
444	* The bit count for the current host.
445	* @note Superfluous, but still around for hysterical raisins. */
446	#if HC_ARCH_BITS == 32
447	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
448	#elif HC_ARCH_BITS == 64
449	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
450	#else
451	# error Unsupported HC_ARCH_BITS value.
452	#endif
453	/** The host bit count mask. */
454	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
455
456	/** The device support only 32-bit guests. */
457	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
458	/** The device support only 64-bit guests. */
459	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
460	/** The device support both 32-bit & 64-bit guests. */
461	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
462	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
463	* The guest bit count for the current compilation. */
464	#if GC_ARCH_BITS == 32
465	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
466	#elif GC_ARCH_BITS == 64
467	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
468	#else
469	# error Unsupported GC_ARCH_BITS value.
470	#endif
471	/** The guest bit count mask. */
472	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
473
474	/** A convenience. */
475	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
476
477	/** Indicates that the device needs to be notified before the drivers when suspending. */
478	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
479	/** Indicates that the device needs to be notified before the drivers when powering off. */
480	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
481	/** Indicates that the device needs to be notified before the drivers when resetting. */
482	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
483
484	/** This flag is used to indicate that the device has been converted to the
485	* new device style. */
486	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
487
488	/** @} */
489
490
491	/** PDM Device Classes.
492	* The order is important, lower bit earlier instantiation.
493	* @{ */
494	/** Architecture device. */
495	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
496	/** Architecture BIOS device. */
497	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
498	/** PCI bus brigde. */
499	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
500	/** PCI built-in device (e.g. PCI root complex devices). */
501	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
502	/** Input device (mouse, keyboard, joystick, HID, ...). */
503	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
504	/** Interrupt controller (PIC). */
505	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
506	/** Interval controoler (PIT). */
507	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
508	/** RTC/CMOS. */
509	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
510	/** DMA controller. */
511	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
512	/** VMM Device. */
513	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
514	/** Graphics device, like VGA. */
515	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
516	/** Storage controller device. */
517	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
518	/** Network interface controller. */
519	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
520	/** Audio. */
521	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
522	/** USB HIC. */
523	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
524	/** ACPI. */
525	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
526	/** Serial controller device. */
527	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
528	/** Parallel controller device */
529	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
530	/** Host PCI pass-through device */
531	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
532	/** Misc devices (always last). */
533	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
534	/** @} */
535
536
537	/**
538	* PDM Device Registration Structure, ring-0.
539	*
540	* This structure is used when registering a device from VBoxInitDevices() in HC
541	* Ring-0. PDM will continue use till the VM is terminated.
542	*/
543	typedef struct PDMDEVREGR0
544	{
545	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
546	uint32_t u32Version;
547	/** Reserved, must be zero. */
548	uint32_t uReserved0;
549	/** Device name, must match the ring-3 one. */
550	char szName[32];
551	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
552	uint32_t fFlags;
553	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
554	uint32_t fClass;
555	/** Maximum number of instances (per VM). */
556	uint32_t cMaxInstances;
557	/** The shared data structure version number. */
558	uint32_t uSharedVersion;
559	/** Size of the instance data. */
560	uint32_t cbInstanceShared;
561	/** Size of the ring-0 instance data. */
562	uint32_t cbInstanceCC;
563	/** Size of the raw-mode instance data. */
564	uint32_t cbInstanceRC;
565	/** Max number of PCI devices. */
566	uint16_t cMaxPciDevices;
567	/** Max number of MSI-X vectors in any of the PCI devices. */
568	uint16_t cMaxMsixVectors;
569	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
570	* remain unchanged from registration till VM destruction. */
571	const char *pszDescription;
572
573	/**
574	* Early construction callback (optional).
575	*
576	* This is called right after the device instance structure has been allocated
577	* and before the ring-3 constructor gets called.
578	*
579	* @returns VBox status code.
580	* @param pDevIns The device instance data.
581	* @note The destructure is always called, regardless of the return status.
582	*/
583	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
584
585	/**
586	* Regular construction callback (optional).
587	*
588	* This is called after (or during) the ring-3 constructor.
589	*
590	* @returns VBox status code.
591	* @param pDevIns The device instance data.
592	* @note The destructure is always called, regardless of the return status.
593	*/
594	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
595
596	/**
597	* Destructor (optional).
598	*
599	* This is called after the ring-3 destruction. This is not called if ring-3
600	* fails to trigger it (e.g. process is killed or crashes).
601	*
602	* @param pDevIns The device instance data.
603	*/
604	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
605
606	/**
607	* Final destructor (optional).
608	*
609	* This is called right before the memory is freed, which happens when the
610	* VM/GVM object is destroyed. This is always called.
611	*
612	* @param pDevIns The device instance data.
613	*/
614	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
615
616	/**
617	* Generic request handler (optional).
618	*
619	* @param pDevIns The device instance data.
620	* @param uReq Device specific request.
621	* @param uArg Request argument.
622	*/
623	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
624
625	/** @name Reserved for future extensions, must be zero.
626	* @{ */
627	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
630	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
631	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
632	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
633	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
634	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
635	/** @} */
636
637	/** Initialization safty marker. */
638	uint32_t u32VersionEnd;
639	} PDMDEVREGR0;
640	/** Pointer to a ring-0 PDM device registration structure. */
641	typedef PDMDEVREGR0 *PPDMDEVREGR0;
642	/** Pointer to a const ring-0 PDM device registration structure. */
643	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
644	/** Current DEVREGR0 version number. */
645	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
646
647
648	/**
649	* PDM Device Registration Structure, raw-mode
650	*
651	* At the moment, this structure is mostly here to match the other two contexts.
652	*/
653	typedef struct PDMDEVREGRC
654	{
655	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
656	uint32_t u32Version;
657	/** Reserved, must be zero. */
658	uint32_t uReserved0;
659	/** Device name, must match the ring-3 one. */
660	char szName[32];
661	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
662	uint32_t fFlags;
663	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
664	uint32_t fClass;
665	/** Maximum number of instances (per VM). */
666	uint32_t cMaxInstances;
667	/** The shared data structure version number. */
668	uint32_t uSharedVersion;
669	/** Size of the instance data. */
670	uint32_t cbInstanceShared;
671	/** Size of the ring-0 instance data. */
672	uint32_t cbInstanceCC;
673	/** Size of the raw-mode instance data. */
674	uint32_t cbInstanceRC;
675	/** Max number of PCI devices. */
676	uint16_t cMaxPciDevices;
677	/** Max number of MSI-X vectors in any of the PCI devices. */
678	uint16_t cMaxMsixVectors;
679	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
680	* remain unchanged from registration till VM destruction. */
681	const char *pszDescription;
682
683	/**
684	* Constructor callback.
685	*
686	* This is called much later than both the ring-0 and ring-3 constructors, since
687	* raw-mode v2 require a working VMM to run actual code.
688	*
689	* @returns VBox status code.
690	* @param pDevIns The device instance data.
691	* @note The destructure is always called, regardless of the return status.
692	*/
693	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
694
695	/** @name Reserved for future extensions, must be zero.
696	* @{ */
697	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
700	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
701	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
702	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
703	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
704	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
705	/** @} */
706
707	/** Initialization safty marker. */
708	uint32_t u32VersionEnd;
709	} PDMDEVREGRC;
710	/** Pointer to a raw-mode PDM device registration structure. */
711	typedef PDMDEVREGRC *PPDMDEVREGRC;
712	/** Pointer to a const raw-mode PDM device registration structure. */
713	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
714	/** Current DEVREGRC version number. */
715	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
716
717
718
719	/** @def PDM_DEVREG_VERSION
720	* Current DEVREG version number. */
721	/** @typedef PDMDEVREGR3
722	* A current context PDM device registration structure. */
723	/** @typedef PPDMDEVREGR3
724	* Pointer to a current context PDM device registration structure. */
725	/** @typedef PCPDMDEVREGR3
726	* Pointer to a const current context PDM device registration structure. */
727	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
728	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
729	typedef PDMDEVREGR3 PDMDEVREG;
730	typedef PPDMDEVREGR3 PPDMDEVREG;
731	typedef PCPDMDEVREGR3 PCPDMDEVREG;
732	#elif defined(IN_RING0)
733	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
734	typedef PDMDEVREGR0 PDMDEVREG;
735	typedef PPDMDEVREGR0 PPDMDEVREG;
736	typedef PCPDMDEVREGR0 PCPDMDEVREG;
737	#elif defined(IN_RC)
738	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
739	typedef PDMDEVREGRC PDMDEVREG;
740	typedef PPDMDEVREGRC PPDMDEVREG;
741	typedef PCPDMDEVREGRC PCPDMDEVREG;
742	#else
743	# error "Not IN_RING3, IN_RING0 or IN_RC"
744	#endif
745
746
747	/**
748	* Device registrations for ring-0 modules.
749	*
750	* This structure is used directly and must therefore reside in persistent
751	* memory (i.e. the data section).
752	*/
753	typedef struct PDMDEVMODREGR0
754	{
755	/** The structure version (PDM_DEVMODREGR0_VERSION). */
756	uint32_t u32Version;
757	/** Number of devices in the array papDevRegs points to. */
758	uint32_t cDevRegs;
759	/** Pointer to device registration structures. */
760	PCPDMDEVREGR0 *papDevRegs;
761	/** The ring-0 module handle - PDM internal, fingers off. */
762	void *hMod;
763	/** List entry - PDM internal, fingers off. */
764	RTLISTNODE ListEntry;
765	} PDMDEVMODREGR0;
766	/** Pointer to device registriations for a ring-0 module. */
767	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
768	/** Current PDMDEVMODREGR0 version number. */
769	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
770
771
772	/** @name IRQ Level for use with the *SetIrq APIs.
773	* @{
774	*/
775	/** Assert the IRQ (can assume value 1). */
776	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
777	/** Deassert the IRQ (can assume value 0). */
778	#define PDM_IRQ_LEVEL_LOW 0
779	/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
780	* automatically deasserts it after delivery to the APIC (IOAPIC).
781	* @note Only suitable for edge trigger interrupts. */
782	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
783	/** @} */
784
785	/**
786	* Registration record for MSI/MSI-X emulation.
787	*/
788	typedef struct PDMMSIREG
789	{
790	/** Number of MSI interrupt vectors, 0 if MSI not supported */
791	uint16_t cMsiVectors;
792	/** Offset of MSI capability */
793	uint8_t iMsiCapOffset;
794	/** Offset of next capability to MSI */
795	uint8_t iMsiNextOffset;
796	/** If we support 64-bit MSI addressing */
797	bool fMsi64bit;
798	/** If we do not support per-vector masking */
799	bool fMsiNoMasking;
800
801	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
802	uint16_t cMsixVectors;
803	/** Offset of MSI-X capability */
804	uint8_t iMsixCapOffset;
805	/** Offset of next capability to MSI-X */
806	uint8_t iMsixNextOffset;
807	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
808	uint8_t iMsixBar;
809	} PDMMSIREG;
810	typedef PDMMSIREG *PPDMMSIREG;
811
812	/**
813	* PCI Bus registration structure.
814	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
815	*/
816	typedef struct PDMPCIBUSREGR3
817	{
818	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
819	uint32_t u32Version;
820
821	/**
822	* Registers the device with the default PCI bus.
823	*
824	* @returns VBox status code.
825	* @param pDevIns Device instance of the PCI Bus.
826	* @param pPciDev The PCI device structure.
827	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
828	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
829	* device number (0-31).
830	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
831	* function number (0-7).
832	* @param pszName Device name (static but not unique).
833	*
834	* @remarks Caller enters the PDM critical section.
835	*/
836	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
837	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
838
839	/**
840	* Initialize MSI or MSI-X emulation support in a PCI device.
841	*
842	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
843	* vast majority of device emulation it covers everything necessary. It's
844	* fully automatic, taking care of all BAR and config space requirements,
845	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
846	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
847	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
848	*
849	* A device not using this can still offer MSI/MSI-X. In this case it's
850	* completely up to the device (in the MSI-X case) to create/register the
851	* necessary MMIO BAR, handle all config space/BAR updating and take care
852	* of delivering the interrupts appropriately.
853	*
854	* @returns VBox status code.
855	* @param pDevIns Device instance of the PCI Bus.
856	* @param pPciDev The PCI device structure.
857	* @param pMsiReg MSI emulation registration structure
858	* @remarks Caller enters the PDM critical section.
859	*/
860	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
861
862	/**
863	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
864	*
865	* @returns VBox status code.
866	* @param pDevIns Device instance of the PCI Bus.
867	* @param pPciDev The PCI device structure.
868	* @param iRegion The region number.
869	* @param cbRegion Size of the region.
870	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
871	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
872	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
873	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
874	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
875	* @a fFlags, UINT64_MAX if no handle is passed
876	* (old style).
877	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
878	* is given.
879	* @remarks Caller enters the PDM critical section.
880	*/
881	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
882	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
883	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
884
885	/**
886	* Register PCI configuration space read/write intercept callbacks.
887	*
888	* @param pDevIns Device instance of the PCI Bus.
889	* @param pPciDev The PCI device structure.
890	* @param pfnRead Pointer to the user defined PCI config read function.
891	* @param pfnWrite Pointer to the user defined PCI config write function.
892	* to call default PCI config write function. Can be NULL.
893	* @remarks Caller enters the PDM critical section.
894	* @thread EMT
895	*/
896	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
897	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
898
899	/**
900	* Perform a PCI configuration space write, bypassing interception.
901	*
902	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
903	*
904	* @returns Strict VBox status code (mainly DBGFSTOP).
905	* @param pDevIns Device instance of the PCI Bus.
906	* @param pPciDev The PCI device which config space is being read.
907	* @param uAddress The config space address.
908	* @param cb The size of the read: 1, 2 or 4 bytes.
909	* @param u32Value The value to write.
910	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
911	* that the (root) bus will have done that already.
912	*/
913	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
914	uint32_t uAddress, unsigned cb, uint32_t u32Value));
915
916	/**
917	* Perform a PCI configuration space read, bypassing interception.
918	*
919	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
920	*
921	* @returns Strict VBox status code (mainly DBGFSTOP).
922	* @param pDevIns Device instance of the PCI Bus.
923	* @param pPciDev The PCI device which config space is being read.
924	* @param uAddress The config space address.
925	* @param cb The size of the read: 1, 2 or 4 bytes.
926	* @param pu32Value Where to return the value.
927	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
928	* that the (root) bus will have done that already.
929	*/
930	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
931	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
932
933	/**
934	* Set the IRQ for a PCI device.
935	*
936	* @param pDevIns Device instance of the PCI Bus.
937	* @param pPciDev The PCI device structure.
938	* @param iIrq IRQ number to set.
939	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
940	* @param uTagSrc The IRQ tag and source (for tracing).
941	* @remarks Caller enters the PDM critical section.
942	*/
943	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
944
945	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
946	uint32_t u32EndVersion;
947	} PDMPCIBUSREGR3;
948	/** Pointer to a PCI bus registration structure. */
949	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
950	/** Current PDMPCIBUSREGR3 version number. */
951	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
952
953	/**
954	* PCI Bus registration structure for ring-0.
955	*/
956	typedef struct PDMPCIBUSREGR0
957	{
958	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
959	uint32_t u32Version;
960	/** The PCI bus number (from ring-3 registration). */
961	uint32_t iBus;
962	/**
963	* Set the IRQ for a PCI device.
964	*
965	* @param pDevIns Device instance of the PCI Bus.
966	* @param pPciDev The PCI device structure.
967	* @param iIrq IRQ number to set.
968	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
969	* @param uTagSrc The IRQ tag and source (for tracing).
970	* @remarks Caller enters the PDM critical section.
971	*/
972	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
973	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
974	uint32_t u32EndVersion;
975	} PDMPCIBUSREGR0;
976	/** Pointer to a PCI bus ring-0 registration structure. */
977	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
978	/** Current PDMPCIBUSREGR0 version number. */
979	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
980
981	/**
982	* PCI Bus registration structure for raw-mode.
983	*/
984	typedef struct PDMPCIBUSREGRC
985	{
986	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
987	uint32_t u32Version;
988	/** The PCI bus number (from ring-3 registration). */
989	uint32_t iBus;
990	/**
991	* Set the IRQ for a PCI device.
992	*
993	* @param pDevIns Device instance of the PCI Bus.
994	* @param pPciDev The PCI device structure.
995	* @param iIrq IRQ number to set.
996	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
997	* @param uTagSrc The IRQ tag and source (for tracing).
998	* @remarks Caller enters the PDM critical section.
999	*/
1000	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
1001	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1002	uint32_t u32EndVersion;
1003	} PDMPCIBUSREGRC;
1004	/** Pointer to a PCI bus raw-mode registration structure. */
1005	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1006	/** Current PDMPCIBUSREGRC version number. */
1007	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1008
1009	/** PCI bus registration structure for the current context. */
1010	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1011	/** Pointer to a PCI bus registration structure for the current context. */
1012	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1013	/** PCI bus registration structure version for the current context. */
1014	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1015
1016
1017	/**
1018	* PCI Bus RC helpers.
1019	*/
1020	typedef struct PDMPCIHLPRC
1021	{
1022	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1023	uint32_t u32Version;
1024
1025	/**
1026	* Set an ISA IRQ.
1027	*
1028	* @param pDevIns PCI device instance.
1029	* @param iIrq IRQ number to set.
1030	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1031	* @param uTagSrc The IRQ tag and source (for tracing).
1032	* @thread EMT only.
1033	*/
1034	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1035
1036	/**
1037	* Set an I/O-APIC IRQ.
1038	*
1039	* @param pDevIns PCI device instance.
1040	* @param uBusDevFn The bus:device:function of the device initiating the
1041	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1042	* interrupt.
1043	* @param iIrq IRQ number to set.
1044	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1045	* @param uTagSrc The IRQ tag and source (for tracing).
1046	* @thread EMT only.
1047	*/
1048	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1049
1050	/**
1051	* Send an MSI.
1052	*
1053	* @param pDevIns PCI device instance.
1054	* @param uBusDevFn The bus:device:function of the device initiating the
1055	* MSI. Cannot be NIL_PCIBDF.
1056	* @param pMsi The MSI to send.
1057	* @param uTagSrc The IRQ tag and source (for tracing).
1058	* @thread EMT only.
1059	*/
1060	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1061
1062
1063	/**
1064	* Acquires the PDM lock.
1065	*
1066	* @returns VINF_SUCCESS on success.
1067	* @returns rc if we failed to acquire the lock.
1068	* @param pDevIns The PCI device instance.
1069	* @param rc What to return if we fail to acquire the lock.
1070	*
1071	* @sa PDMCritSectEnter
1072	*/
1073	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1074
1075	/**
1076	* Releases the PDM lock.
1077	*
1078	* @param pDevIns The PCI device instance.
1079	*/
1080	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1081
1082	/**
1083	* Gets a bus by it's PDM ordinal (typically the parent bus).
1084	*
1085	* @returns Pointer to the device instance of the bus.
1086	* @param pDevIns The PCI bus device instance.
1087	* @param idxPdmBus The PDM ordinal value of the bus to get.
1088	*/
1089	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1090
1091	/** Just a safety precaution. */
1092	uint32_t u32TheEnd;
1093	} PDMPCIHLPRC;
1094	/** Pointer to PCI helpers. */
1095	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1096	/** Pointer to const PCI helpers. */
1097	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1098
1099	/** Current PDMPCIHLPRC version number. */
1100	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1101
1102
1103	/**
1104	* PCI Bus R0 helpers.
1105	*/
1106	typedef struct PDMPCIHLPR0
1107	{
1108	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1109	uint32_t u32Version;
1110
1111	/**
1112	* Set an ISA IRQ.
1113	*
1114	* @param pDevIns PCI device instance.
1115	* @param iIrq IRQ number to set.
1116	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1117	* @param uTagSrc The IRQ tag and source (for tracing).
1118	* @thread EMT only.
1119	*/
1120	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1121
1122	/**
1123	* Set an I/O-APIC IRQ.
1124	*
1125	* @param pDevIns PCI device instance.
1126	* @param uBusDevFn The bus:device:function of the device initiating the
1127	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1128	* interrupt.
1129	* @param iIrq IRQ number to set.
1130	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1131	* @param uTagSrc The IRQ tag and source (for tracing).
1132	* @thread EMT only.
1133	*/
1134	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1135
1136	/**
1137	* Send an MSI.
1138	*
1139	* @param pDevIns PCI device instance.
1140	* @param uBusDevFn The bus:device:function of the device initiating the
1141	* MSI. Cannot be NIL_PCIBDF.
1142	* @param pMsi The MSI to send.
1143	* @param uTagSrc The IRQ tag and source (for tracing).
1144	* @thread EMT only.
1145	*/
1146	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1147
1148	/**
1149	* Acquires the PDM lock.
1150	*
1151	* @returns VINF_SUCCESS on success.
1152	* @returns rc if we failed to acquire the lock.
1153	* @param pDevIns The PCI device instance.
1154	* @param rc What to return if we fail to acquire the lock.
1155	*
1156	* @sa PDMCritSectEnter
1157	*/
1158	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1159
1160	/**
1161	* Releases the PDM lock.
1162	*
1163	* @param pDevIns The PCI device instance.
1164	*/
1165	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1166
1167	/**
1168	* Gets a bus by it's PDM ordinal (typically the parent bus).
1169	*
1170	* @returns Pointer to the device instance of the bus.
1171	* @param pDevIns The PCI bus device instance.
1172	* @param idxPdmBus The PDM ordinal value of the bus to get.
1173	*/
1174	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1175
1176	/** Just a safety precaution. */
1177	uint32_t u32TheEnd;
1178	} PDMPCIHLPR0;
1179	/** Pointer to PCI helpers. */
1180	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1181	/** Pointer to const PCI helpers. */
1182	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1183
1184	/** Current PDMPCIHLPR0 version number. */
1185	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1186
1187	/**
1188	* PCI device helpers.
1189	*/
1190	typedef struct PDMPCIHLPR3
1191	{
1192	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1193	uint32_t u32Version;
1194
1195	/**
1196	* Set an ISA IRQ.
1197	*
1198	* @param pDevIns The PCI device instance.
1199	* @param iIrq IRQ number to set.
1200	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1201	* @param uTagSrc The IRQ tag and source (for tracing).
1202	*/
1203	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1204
1205	/**
1206	* Set an I/O-APIC IRQ.
1207	*
1208	* @param pDevIns The PCI device instance.
1209	* @param uBusDevFn The bus:device:function of the device initiating the
1210	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1211	* interrupt.
1212	* @param iIrq IRQ number to set.
1213	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1214	* @param uTagSrc The IRQ tag and source (for tracing).
1215	*/
1216	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1217
1218	/**
1219	* Send an MSI.
1220	*
1221	* @param pDevIns PCI device instance.
1222	* @param uBusDevFn The bus:device:function of the device initiating the
1223	* MSI. Cannot be NIL_PCIBDF.
1224	* @param pMsi The MSI to send.
1225	* @param uTagSrc The IRQ tag and source (for tracing).
1226	*/
1227	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1228
1229	/**
1230	* Acquires the PDM lock.
1231	*
1232	* @returns VINF_SUCCESS on success.
1233	* @returns Fatal error on failure.
1234	* @param pDevIns The PCI device instance.
1235	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1236	*
1237	* @sa PDMCritSectEnter
1238	*/
1239	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1240
1241	/**
1242	* Releases the PDM lock.
1243	*
1244	* @param pDevIns The PCI device instance.
1245	*/
1246	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1247
1248	/**
1249	* Gets a bus by it's PDM ordinal (typically the parent bus).
1250	*
1251	* @returns Pointer to the device instance of the bus.
1252	* @param pDevIns The PCI bus device instance.
1253	* @param idxPdmBus The PDM ordinal value of the bus to get.
1254	*/
1255	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1256
1257	/** Just a safety precaution. */
1258	uint32_t u32TheEnd;
1259	} PDMPCIHLPR3;
1260	/** Pointer to PCI helpers. */
1261	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1262	/** Pointer to const PCI helpers. */
1263	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1264
1265	/** Current PDMPCIHLPR3 version number. */
1266	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1267
1268
1269	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1270	* These flags are used for memory access transactions via the IOMMU interface.
1271	* @{ */
1272	/** Memory read. */
1273	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1274	/** Memory write. */
1275	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1276	/** Valid flag mask. */
1277	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1278	/** @} */
1279
1280	/**
1281	* IOMMU registration structure for ring-0.
1282	*/
1283	typedef struct PDMIOMMUREGR0
1284	{
1285	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1286	* version. */
1287	uint32_t u32Version;
1288	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1289	uint32_t idxIommu;
1290
1291	/**
1292	* Translates the physical address for a memory transaction through the IOMMU.
1293	*
1294	* @returns VBox status code.
1295	* @param pDevIns The IOMMU device instance.
1296	* @param idDevice The device identifier (bus, device, function).
1297	* @param uIova The I/O virtual address being accessed.
1298	* @param cbIova The size of the access.
1299	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1300	* @param pGCPhysSpa Where to store the translated system physical address.
1301	* @param pcbContiguous Where to store the number of contiguous bytes translated
1302	* and permission-checked.
1303	*
1304	* @thread Any.
1305	*/
1306	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1307	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1308
1309	/**
1310	* Translates in bulk physical page addresses for memory transactions through the
1311	* IOMMU.
1312	*
1313	* @returns VBox status code.
1314	* @param pDevIns The IOMMU device instance.
1315	* @param idDevice The device identifier (bus, device, function).
1316	* @param cIovas The number of I/O virtual addresses being accessed.
1317	* @param pauIovas The I/O virtual addresses being accessed.
1318	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1319	* @param paGCPhysSpa Where to store the translated system physical page
1320	* addresses.
1321	*
1322	* @thread Any.
1323	*/
1324	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1325	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1326
1327	/**
1328	* Performs an interrupt remap request through the IOMMU.
1329	*
1330	* @returns VBox status code.
1331	* @param pDevIns The IOMMU device instance.
1332	* @param idDevice The device identifier (bus, device, function).
1333	* @param pMsiIn The source MSI.
1334	* @param pMsiOut Where to store the remapped MSI.
1335	*
1336	* @thread Any.
1337	*/
1338	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1339
1340	/** Just a safety precaution. */
1341	uint32_t u32TheEnd;
1342	} PDMIOMMUREGR0;
1343	/** Pointer to a IOMMU registration structure. */
1344	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1345
1346	/** Current PDMIOMMUREG version number. */
1347	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1348
1349
1350	/**
1351	* IOMMU registration structure for raw-mode.
1352	*/
1353	typedef struct PDMIOMMUREGRC
1354	{
1355	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1356	* version. */
1357	uint32_t u32Version;
1358	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1359	uint32_t idxIommu;
1360
1361	/**
1362	* Translates the physical address for a memory transaction through the IOMMU.
1363	*
1364	* @returns VBox status code.
1365	* @param pDevIns The IOMMU device instance.
1366	* @param idDevice The device identifier (bus, device, function).
1367	* @param uIova The I/O virtual address being accessed.
1368	* @param cbIova The size of the access.
1369	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1370	* @param pGCPhysSpa Where to store the translated system physical address.
1371	* @param pcbContiguous Where to store the number of contiguous bytes translated
1372	* and permission-checked.
1373	*
1374	* @thread Any.
1375	*/
1376	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1377	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1378
1379	/**
1380	* Translates in bulk physical page addresses for memory transactions through the
1381	* IOMMU.
1382	*
1383	* @returns VBox status code.
1384	* @param pDevIns The IOMMU device instance.
1385	* @param idDevice The device identifier (bus, device, function).
1386	* @param cIovas The number of I/O virtual addresses being accessed.
1387	* @param pauIovas The I/O virtual addresses being accessed.
1388	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1389	* @param paGCPhysSpa Where to store the translated system physical page
1390	* addresses.
1391	*
1392	* @thread Any.
1393	*/
1394	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1395	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1396
1397	/**
1398	* Performs an interrupt remap request through the IOMMU.
1399	*
1400	* @returns VBox status code.
1401	* @param pDevIns The IOMMU device instance.
1402	* @param idDevice The device identifier (bus, device, function).
1403	* @param pMsiIn The source MSI.
1404	* @param pMsiOut Where to store the remapped MSI.
1405	*
1406	* @thread Any.
1407	*/
1408	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1409
1410	/** Just a safety precaution. */
1411	uint32_t u32TheEnd;
1412	} PDMIOMMUREGRC;
1413	/** Pointer to a IOMMU registration structure. */
1414	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1415
1416	/** Current PDMIOMMUREG version number. */
1417	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1418
1419
1420	/**
1421	* IOMMU registration structure for ring-3.
1422	*/
1423	typedef struct PDMIOMMUREGR3
1424	{
1425	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1426	* version. */
1427	uint32_t u32Version;
1428	/** Padding. */
1429	uint32_t uPadding0;
1430
1431	/**
1432	* Translates the physical address for a memory transaction through the IOMMU.
1433	*
1434	* @returns VBox status code.
1435	* @param pDevIns The IOMMU device instance.
1436	* @param idDevice The device identifier (bus, device, function).
1437	* @param uIova The I/O virtual address being accessed.
1438	* @param cbIova The size of the access.
1439	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1440	* @param pGCPhysSpa Where to store the translated system physical address.
1441	* @param pcbContiguous Where to store the number of contiguous bytes translated
1442	* and permission-checked.
1443	*
1444	* @thread Any.
1445	*/
1446	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1447	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1448
1449	/**
1450	* Translates in bulk physical page addresses for memory transactions through the
1451	* IOMMU.
1452	*
1453	* @returns VBox status code.
1454	* @param pDevIns The IOMMU device instance.
1455	* @param idDevice The device identifier (bus, device, function).
1456	* @param cIovas The number of I/O virtual addresses being accessed.
1457	* @param pauIovas The I/O virtual addresses being accessed.
1458	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1459	* @param paGCPhysSpa Where to store the translated system physical page
1460	* addresses.
1461	*
1462	* @thread Any.
1463	*/
1464	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1465	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1466
1467	/**
1468	* Performs an interrupt remap request through the IOMMU.
1469	*
1470	* @returns VBox status code.
1471	* @param pDevIns The IOMMU device instance.
1472	* @param idDevice The device identifier (bus, device, function).
1473	* @param pMsiIn The source MSI.
1474	* @param pMsiOut Where to store the remapped MSI.
1475	*
1476	* @thread Any.
1477	*/
1478	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1479
1480	/** Just a safety precaution. */
1481	uint32_t u32TheEnd;
1482	} PDMIOMMUREGR3;
1483	/** Pointer to a IOMMU registration structure. */
1484	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1485
1486	/** Current PDMIOMMUREG version number. */
1487	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1488
1489	/** IOMMU registration structure for the current context. */
1490	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1491	/** Pointer to an IOMMU registration structure for the current context. */
1492	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1493	/** IOMMU registration structure version for the current context. */
1494	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1495
1496
1497	/**
1498	* IOMMU helpers for ring-0.
1499	*/
1500	typedef struct PDMIOMMUHLPR0
1501	{
1502	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1503	uint32_t u32Version;
1504
1505	/**
1506	* Acquires the PDM lock.
1507	*
1508	* @returns VINF_SUCCESS on success.
1509	* @returns rc if we failed to acquire the lock.
1510	* @param pDevIns The PCI device instance.
1511	* @param rc What to return if we fail to acquire the lock.
1512	*
1513	* @sa PDMCritSectEnter
1514	*/
1515	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1516
1517	/**
1518	* Releases the PDM lock.
1519	*
1520	* @param pDevIns The PCI device instance.
1521	*/
1522	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1523
1524	/**
1525	* Check whether the calling thread owns the PDM lock.
1526	*
1527	* @returns @c true if the PDM lock is owned, @c false otherwise.
1528	* @param pDevIns The PCI device instance.
1529	*/
1530	DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1531
1532	/**
1533	* Send an MSI (when generated by the IOMMU device itself).
1534	*
1535	* @param pDevIns PCI device instance.
1536	* @param pMsi The MSI to send.
1537	* @param uTagSrc The IRQ tag and source (for tracing).
1538	*/
1539	DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1540
1541	/** Just a safety precaution. */
1542	uint32_t u32TheEnd;
1543	} PDMIOMMUHLPR0;
1544	/** Pointer to IOMMU helpers for ring-0. */
1545	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1546	/** Pointer to const IOMMU helpers for ring-0. */
1547	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1548
1549	/** Current PDMIOMMUHLPR0 version number. */
1550	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1551
1552
1553	/**
1554	* IOMMU helpers for raw-mode.
1555	*/
1556	typedef struct PDMIOMMUHLPRC
1557	{
1558	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1559	uint32_t u32Version;
1560
1561	/**
1562	* Acquires the PDM lock.
1563	*
1564	* @returns VINF_SUCCESS on success.
1565	* @returns rc if we failed to acquire the lock.
1566	* @param pDevIns The PCI device instance.
1567	* @param rc What to return if we fail to acquire the lock.
1568	*
1569	* @sa PDMCritSectEnter
1570	*/
1571	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1572
1573	/**
1574	* Releases the PDM lock.
1575	*
1576	* @param pDevIns The PCI device instance.
1577	*/
1578	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1579
1580	/**
1581	* Check whether the threads owns the PDM lock.
1582	*
1583	* @returns @c true if the PDM lock is owned, @c false otherwise.
1584	* @param pDevIns The PCI device instance.
1585	*/
1586	DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1587
1588	/**
1589	* Send an MSI (when generated by the IOMMU device itself).
1590	*
1591	* @param pDevIns PCI device instance.
1592	* @param pMsi The MSI to send.
1593	* @param uTagSrc The IRQ tag and source (for tracing).
1594	*/
1595	DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1596
1597	/** Just a safety precaution. */
1598	uint32_t u32TheEnd;
1599	} PDMIOMMUHLPRC;
1600	/** Pointer to IOMMU helpers for raw-mode. */
1601	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1602	/** Pointer to const IOMMU helpers for raw-mode. */
1603	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1604
1605	/** Current PDMIOMMUHLPRC version number. */
1606	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1607
1608
1609	/**
1610	* IOMMU helpers for ring-3.
1611	*/
1612	typedef struct PDMIOMMUHLPR3
1613	{
1614	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1615	uint32_t u32Version;
1616
1617	/**
1618	* Acquires the PDM lock.
1619	*
1620	* @returns VINF_SUCCESS on success.
1621	* @returns rc if we failed to acquire the lock.
1622	* @param pDevIns The PCI device instance.
1623	* @param rc What to return if we fail to acquire the lock.
1624	*
1625	* @sa PDMCritSectEnter
1626	*/
1627	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1628
1629	/**
1630	* Releases the PDM lock.
1631	*
1632	* @param pDevIns The PCI device instance.
1633	*/
1634	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1635
1636	/**
1637	* Check whether the threads owns the PDM lock.
1638	*
1639	* @returns @c true if the PDM lock is owned, @c false otherwise.
1640	* @param pDevIns The PCI device instance.
1641	*/
1642	DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1643
1644	/**
1645	* Send an MSI (when generated by the IOMMU device itself).
1646	*
1647	* @param pDevIns PCI device instance.
1648	* @param pMsi The MSI to send.
1649	* @param uTagSrc The IRQ tag and source (for tracing).
1650	*/
1651	DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1652
1653	/** Just a safety precaution. */
1654	uint32_t u32TheEnd;
1655	} PDMIOMMUHLPR3;
1656	/** Pointer to IOMMU helpers for raw-mode. */
1657	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1658	/** Pointer to const IOMMU helpers for raw-mode. */
1659	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1660
1661	/** Current PDMIOMMUHLPR3 version number. */
1662	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1663
1664
1665	/**
1666	* Programmable Interrupt Controller registration structure (all contexts).
1667	*/
1668	typedef struct PDMPICREG
1669	{
1670	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1671	uint32_t u32Version;
1672
1673	/**
1674	* Set the an IRQ.
1675	*
1676	* @param pDevIns Device instance of the PIC.
1677	* @param iIrq IRQ number to set.
1678	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1679	* @param uTagSrc The IRQ tag and source (for tracing).
1680	* @remarks Caller enters the PDM critical section.
1681	*/
1682	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1683
1684	/**
1685	* Get a pending interrupt.
1686	*
1687	* @returns Pending interrupt number.
1688	* @param pDevIns Device instance of the PIC.
1689	* @param puTagSrc Where to return the IRQ tag and source.
1690	* @remarks Caller enters the PDM critical section.
1691	*/
1692	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1693
1694	/** Just a safety precaution. */
1695	uint32_t u32TheEnd;
1696	} PDMPICREG;
1697	/** Pointer to a PIC registration structure. */
1698	typedef PDMPICREG *PPDMPICREG;
1699
1700	/** Current PDMPICREG version number. */
1701	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1702
1703	/**
1704	* PIC helpers, same in all contexts.
1705	*/
1706	typedef struct PDMPICHLP
1707	{
1708	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1709	uint32_t u32Version;
1710
1711	/**
1712	* Set the interrupt force action flag.
1713	*
1714	* @param pDevIns Device instance of the PIC.
1715	*/
1716	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1717
1718	/**
1719	* Clear the interrupt force action flag.
1720	*
1721	* @param pDevIns Device instance of the PIC.
1722	*/
1723	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1724
1725	/**
1726	* Acquires the PDM lock.
1727	*
1728	* @returns VINF_SUCCESS on success.
1729	* @returns rc if we failed to acquire the lock.
1730	* @param pDevIns The PIC device instance.
1731	* @param rc What to return if we fail to acquire the lock.
1732	*
1733	* @sa PDMCritSectEnter
1734	*/
1735	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1736
1737	/**
1738	* Releases the PDM lock.
1739	*
1740	* @param pDevIns The PIC device instance.
1741	*/
1742	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1743
1744	/** Just a safety precaution. */
1745	uint32_t u32TheEnd;
1746	} PDMPICHLP;
1747	/** Pointer to PIC helpers. */
1748	typedef PDMPICHLP *PPDMPICHLP;
1749	/** Pointer to const PIC helpers. */
1750	typedef const PDMPICHLP *PCPDMPICHLP;
1751
1752	/** Current PDMPICHLP version number. */
1753	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1754
1755
1756	/**
1757	* Firmware registration structure.
1758	*/
1759	typedef struct PDMFWREG
1760	{
1761	/** Struct version+magic number (PDM_FWREG_VERSION). */
1762	uint32_t u32Version;
1763
1764	/**
1765	* Checks whether this is a hard or soft reset.
1766	*
1767	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1768	* is 5, 9 or 0xA.
1769	*
1770	* @returns true if hard reset, false if soft.
1771	* @param pDevIns Device instance of the firmware.
1772	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1773	*/
1774	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1775
1776	/** Just a safety precaution. */
1777	uint32_t u32TheEnd;
1778	} PDMFWREG;
1779	/** Pointer to a FW registration structure. */
1780	typedef PDMFWREG *PPDMFWREG;
1781	/** Pointer to a const FW registration structure. */
1782	typedef PDMFWREG const *PCPDMFWREG;
1783
1784	/** Current PDMFWREG version number. */
1785	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1786
1787	/**
1788	* Firmware R3 helpers.
1789	*/
1790	typedef struct PDMFWHLPR3
1791	{
1792	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1793	uint32_t u32Version;
1794
1795	/** Just a safety precaution. */
1796	uint32_t u32TheEnd;
1797	} PDMFWHLPR3;
1798
1799	/** Pointer to FW R3 helpers. */
1800	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1801	/** Pointer to const FW R3 helpers. */
1802	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1803
1804	/** Current PDMFWHLPR3 version number. */
1805	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1806
1807
1808	/**
1809	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1810	*
1811	* Also used in saved-states, CFGM don't change existing values.
1812	*/
1813	typedef enum PDMAPICMODE
1814	{
1815	/** Invalid 0 entry. */
1816	PDMAPICMODE_INVALID = 0,
1817	/** No APIC. */
1818	PDMAPICMODE_NONE,
1819	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1820	PDMAPICMODE_APIC,
1821	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1822	PDMAPICMODE_X2APIC,
1823	/** The usual 32-bit paranoia. */
1824	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1825	} PDMAPICMODE;
1826
1827	/**
1828	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1829	*/
1830	typedef enum PDMAPICIRQ
1831	{
1832	/** Invalid 0 entry. */
1833	PDMAPICIRQ_INVALID = 0,
1834	/** Normal hardware interrupt. */
1835	PDMAPICIRQ_HARDWARE,
1836	/** NMI. */
1837	PDMAPICIRQ_NMI,
1838	/** SMI. */
1839	PDMAPICIRQ_SMI,
1840	/** ExtINT (HW interrupt via PIC). */
1841	PDMAPICIRQ_EXTINT,
1842	/** Interrupt arrived, needs to be updated to the IRR. */
1843	PDMAPICIRQ_UPDATE_PENDING,
1844	/** The usual 32-bit paranoia. */
1845	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1846	} PDMAPICIRQ;
1847
1848
1849	/**
1850	* I/O APIC registration structure (all contexts).
1851	*/
1852	typedef struct PDMIOAPICREG
1853	{
1854	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1855	uint32_t u32Version;
1856
1857	/**
1858	* Set an IRQ.
1859	*
1860	* @param pDevIns Device instance of the I/O APIC.
1861	* @param uBusDevFn The bus:device:function of the device initiating the
1862	* IRQ. Can be NIL_PCIBDF.
1863	* @param iIrq IRQ number to set.
1864	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1865	* @param uTagSrc The IRQ tag and source (for tracing).
1866	*
1867	* @remarks Caller enters the PDM critical section
1868	* Actually, as per 2018-07-21 this isn't true (bird).
1869	*/
1870	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1871
1872	/**
1873	* Send a MSI.
1874	*
1875	* @param pDevIns Device instance of the I/O APIC.
1876	* @param uBusDevFn The bus:device:function of the device initiating the
1877	* MSI. Cannot be NIL_PCIBDF.
1878	* @param pMsi The MSI to send.
1879	* @param uTagSrc The IRQ tag and source (for tracing).
1880	*
1881	* @remarks Caller enters the PDM critical section
1882	* Actually, as per 2018-07-21 this isn't true (bird).
1883	*/
1884	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1885
1886	/**
1887	* Set the EOI for an interrupt vector.
1888	*
1889	* @param pDevIns Device instance of the I/O APIC.
1890	* @param u8Vector The vector.
1891	*
1892	* @remarks Caller enters the PDM critical section
1893	* Actually, as per 2018-07-21 this isn't true (bird).
1894	*/
1895	DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1896
1897	/** Just a safety precaution. */
1898	uint32_t u32TheEnd;
1899	} PDMIOAPICREG;
1900	/** Pointer to an APIC registration structure. */
1901	typedef PDMIOAPICREG *PPDMIOAPICREG;
1902
1903	/** Current PDMAPICREG version number. */
1904	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1905
1906
1907	/**
1908	* IOAPIC helpers, same in all contexts.
1909	*/
1910	typedef struct PDMIOAPICHLP
1911	{
1912	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1913	uint32_t u32Version;
1914
1915	/**
1916	* Private interface between the IOAPIC and APIC.
1917	*
1918	* @returns status code.
1919	* @param pDevIns Device instance of the IOAPIC.
1920	* @param u8Dest See APIC implementation.
1921	* @param u8DestMode See APIC implementation.
1922	* @param u8DeliveryMode See APIC implementation.
1923	* @param uVector See APIC implementation.
1924	* @param u8Polarity See APIC implementation.
1925	* @param u8TriggerMode See APIC implementation.
1926	* @param uTagSrc The IRQ tag and source (for tracing).
1927	*
1928	* @sa APICBusDeliver()
1929	*/
1930	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1931	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1932
1933	/**
1934	* Acquires the PDM lock.
1935	*
1936	* @returns VINF_SUCCESS on success.
1937	* @returns rc if we failed to acquire the lock.
1938	* @param pDevIns The IOAPIC device instance.
1939	* @param rc What to return if we fail to acquire the lock.
1940	*
1941	* @sa PDMCritSectEnter
1942	*/
1943	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1944
1945	/**
1946	* Releases the PDM lock.
1947	*
1948	* @param pDevIns The IOAPIC device instance.
1949	*/
1950	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1951
1952	/**
1953	* Checks if the calling thread owns the PDM lock.
1954	*
1955	* @param pDevIns The IOAPIC device instance.
1956	*/
1957	DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1958
1959	/**
1960	* Private interface between the IOAPIC and IOMMU.
1961	*
1962	* @returns status code.
1963	* @param pDevIns Device instance of the IOAPIC.
1964	* @param idDevice The device identifier (bus, device, function).
1965	* @param pMsiIn The source MSI.
1966	* @param pMsiOut Where to store the remapped MSI (only updated when
1967	* VINF_SUCCESS is returned).
1968	*/
1969	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1970
1971	/** Just a safety precaution. */
1972	uint32_t u32TheEnd;
1973	} PDMIOAPICHLP;
1974	/** Pointer to IOAPIC helpers. */
1975	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1976	/** Pointer to const IOAPIC helpers. */
1977	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1978
1979	/** Current PDMIOAPICHLP version number. */
1980	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1981
1982
1983	/**
1984	* HPET registration structure.
1985	*/
1986	typedef struct PDMHPETREG
1987	{
1988	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1989	uint32_t u32Version;
1990	} PDMHPETREG;
1991	/** Pointer to an HPET registration structure. */
1992	typedef PDMHPETREG *PPDMHPETREG;
1993
1994	/** Current PDMHPETREG version number. */
1995	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1996
1997	/**
1998	* HPET RC helpers.
1999	*
2000	* @remarks Keep this around in case HPET will need PDM interaction in again RC
2001	* at some later point.
2002	*/
2003	typedef struct PDMHPETHLPRC
2004	{
2005	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
2006	uint32_t u32Version;
2007
2008	/** Just a safety precaution. */
2009	uint32_t u32TheEnd;
2010	} PDMHPETHLPRC;
2011
2012	/** Pointer to HPET RC helpers. */
2013	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
2014	/** Pointer to const HPET RC helpers. */
2015	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
2016
2017	/** Current PDMHPETHLPRC version number. */
2018	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
2019
2020
2021	/**
2022	* HPET R0 helpers.
2023	*
2024	* @remarks Keep this around in case HPET will need PDM interaction in again R0
2025	* at some later point.
2026	*/
2027	typedef struct PDMHPETHLPR0
2028	{
2029	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2030	uint32_t u32Version;
2031
2032	/** Just a safety precaution. */
2033	uint32_t u32TheEnd;
2034	} PDMHPETHLPR0;
2035
2036	/** Pointer to HPET R0 helpers. */
2037	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2038	/** Pointer to const HPET R0 helpers. */
2039	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2040
2041	/** Current PDMHPETHLPR0 version number. */
2042	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2043
2044	/**
2045	* HPET R3 helpers.
2046	*/
2047	typedef struct PDMHPETHLPR3
2048	{
2049	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2050	uint32_t u32Version;
2051
2052	/**
2053	* Set legacy mode on PIT and RTC.
2054	*
2055	* @returns VINF_SUCCESS on success.
2056	* @returns rc if we failed to set legacy mode.
2057	* @param pDevIns Device instance of the HPET.
2058	* @param fActivated Whether legacy mode is activated or deactivated.
2059	*/
2060	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2061
2062
2063	/**
2064	* Set IRQ, bypassing ISA bus override rules.
2065	*
2066	* @returns VINF_SUCCESS on success.
2067	* @returns rc if we failed to set legacy mode.
2068	* @param pDevIns Device instance of the HPET.
2069	* @param iIrq IRQ number to set.
2070	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2071	*/
2072	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2073
2074	/** Just a safety precaution. */
2075	uint32_t u32TheEnd;
2076	} PDMHPETHLPR3;
2077
2078	/** Pointer to HPET R3 helpers. */
2079	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2080	/** Pointer to const HPET R3 helpers. */
2081	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2082
2083	/** Current PDMHPETHLPR3 version number. */
2084	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2085
2086
2087	/**
2088	* Raw PCI device registration structure.
2089	*/
2090	typedef struct PDMPCIRAWREG
2091	{
2092	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2093	uint32_t u32Version;
2094	/** Just a safety precaution. */
2095	uint32_t u32TheEnd;
2096	} PDMPCIRAWREG;
2097	/** Pointer to a raw PCI registration structure. */
2098	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2099
2100	/** Current PDMPCIRAWREG version number. */
2101	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2102
2103	/**
2104	* Raw PCI device raw-mode context helpers.
2105	*/
2106	typedef struct PDMPCIRAWHLPRC
2107	{
2108	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2109	uint32_t u32Version;
2110	/** Just a safety precaution. */
2111	uint32_t u32TheEnd;
2112	} PDMPCIRAWHLPRC;
2113	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2114	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2115	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2116	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2117
2118	/** Current PDMPCIRAWHLPRC version number. */
2119	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2120
2121	/**
2122	* Raw PCI device ring-0 context helpers.
2123	*/
2124	typedef struct PDMPCIRAWHLPR0
2125	{
2126	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2127	uint32_t u32Version;
2128	/** Just a safety precaution. */
2129	uint32_t u32TheEnd;
2130	} PDMPCIRAWHLPR0;
2131	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2132	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2133	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2134	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2135
2136	/** Current PDMPCIRAWHLPR0 version number. */
2137	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2138
2139
2140	/**
2141	* Raw PCI device ring-3 context helpers.
2142	*/
2143	typedef struct PDMPCIRAWHLPR3
2144	{
2145	/** Undefined structure version and magic number. */
2146	uint32_t u32Version;
2147
2148	/**
2149	* Gets the address of the RC raw PCI device helpers.
2150	*
2151	* This should be called at both construction and relocation time to obtain
2152	* the correct address of the RC helpers.
2153	*
2154	* @returns RC pointer to the raw PCI device helpers.
2155	* @param pDevIns Device instance of the raw PCI device.
2156	*/
2157	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2158
2159	/**
2160	* Gets the address of the R0 raw PCI device helpers.
2161	*
2162	* This should be called at both construction and relocation time to obtain
2163	* the correct address of the R0 helpers.
2164	*
2165	* @returns R0 pointer to the raw PCI device helpers.
2166	* @param pDevIns Device instance of the raw PCI device.
2167	*/
2168	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2169
2170	/** Just a safety precaution. */
2171	uint32_t u32TheEnd;
2172	} PDMPCIRAWHLPR3;
2173	/** Pointer to raw PCI R3 helpers. */
2174	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2175	/** Pointer to const raw PCI R3 helpers. */
2176	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2177
2178	/** Current PDMPCIRAWHLPR3 version number. */
2179	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2180
2181
2182	#ifdef IN_RING3
2183
2184	/**
2185	* DMA Transfer Handler.
2186	*
2187	* @returns Number of bytes transferred.
2188	* @param pDevIns The device instance that registered the handler.
2189	* @param pvUser User pointer.
2190	* @param uChannel Channel number.
2191	* @param off DMA position.
2192	* @param cb Block size.
2193	* @remarks The device lock is take before the callback (in fact, the locks of
2194	* DMA devices and the DMA controller itself are taken).
2195	*/
2196	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2197	uint32_t off, uint32_t cb));
2198	/** Pointer to a FNDMATRANSFERHANDLER(). */
2199	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2200
2201	/**
2202	* DMA Controller registration structure.
2203	*/
2204	typedef struct PDMDMAREG
2205	{
2206	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2207	uint32_t u32Version;
2208
2209	/**
2210	* Execute pending transfers.
2211	*
2212	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2213	* @param pDevIns Device instance of the DMAC.
2214	* @remarks No locks held, called on EMT(0) as a form of serialization.
2215	*/
2216	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2217
2218	/**
2219	* Register transfer function for DMA channel.
2220	*
2221	* @param pDevIns Device instance of the DMAC.
2222	* @param uChannel Channel number.
2223	* @param pDevInsHandler The device instance of the device making the
2224	* regstration (will be passed to the callback).
2225	* @param pfnTransferHandler Device specific transfer function.
2226	* @param pvUser User pointer to be passed to the callback.
2227	* @remarks No locks held, called on an EMT.
2228	*/
2229	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2230	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2231
2232	/**
2233	* Read memory
2234	*
2235	* @returns Number of bytes read.
2236	* @param pDevIns Device instance of the DMAC.
2237	* @param uChannel Channel number.
2238	* @param pvBuffer Pointer to target buffer.
2239	* @param off DMA position.
2240	* @param cbBlock Block size.
2241	* @remarks No locks held, called on an EMT.
2242	*/
2243	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2244
2245	/**
2246	* Write memory
2247	*
2248	* @returns Number of bytes written.
2249	* @param pDevIns Device instance of the DMAC.
2250	* @param uChannel Channel number.
2251	* @param pvBuffer Memory to write.
2252	* @param off DMA position.
2253	* @param cbBlock Block size.
2254	* @remarks No locks held, called on an EMT.
2255	*/
2256	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2257
2258	/**
2259	* Set the DREQ line.
2260	*
2261	* @param pDevIns Device instance of the DMAC.
2262	* @param uChannel Channel number.
2263	* @param uLevel Level of the line.
2264	* @remarks No locks held, called on an EMT.
2265	*/
2266	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2267
2268	/**
2269	* Get channel mode
2270	*
2271	* @returns Channel mode.
2272	* @param pDevIns Device instance of the DMAC.
2273	* @param uChannel Channel number.
2274	* @remarks No locks held, called on an EMT.
2275	*/
2276	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2277
2278	} PDMDMACREG;
2279	/** Pointer to a DMAC registration structure. */
2280	typedef PDMDMACREG *PPDMDMACREG;
2281
2282	/** Current PDMDMACREG version number. */
2283	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2284
2285
2286	/**
2287	* DMA Controller device helpers.
2288	*/
2289	typedef struct PDMDMACHLP
2290	{
2291	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2292	uint32_t u32Version;
2293
2294	/* to-be-defined */
2295
2296	} PDMDMACHLP;
2297	/** Pointer to DMAC helpers. */
2298	typedef PDMDMACHLP *PPDMDMACHLP;
2299	/** Pointer to const DMAC helpers. */
2300	typedef const PDMDMACHLP *PCPDMDMACHLP;
2301
2302	/** Current PDMDMACHLP version number. */
2303	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2304
2305	#endif /* IN_RING3 */
2306
2307
2308
2309	/**
2310	* RTC registration structure.
2311	*/
2312	typedef struct PDMRTCREG
2313	{
2314	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2315	uint32_t u32Version;
2316	uint32_t u32Alignment; /*< structure size alignment. /
2317
2318	/**
2319	* Write to a CMOS register and update the checksum if necessary.
2320	*
2321	* @returns VBox status code.
2322	* @param pDevIns Device instance of the RTC.
2323	* @param iReg The CMOS register index.
2324	* @param u8Value The CMOS register value.
2325	* @remarks Caller enters the device critical section.
2326	*/
2327	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2328
2329	/**
2330	* Read a CMOS register.
2331	*
2332	* @returns VBox status code.
2333	* @param pDevIns Device instance of the RTC.
2334	* @param iReg The CMOS register index.
2335	* @param pu8Value Where to store the CMOS register value.
2336	* @remarks Caller enters the device critical section.
2337	*/
2338	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2339
2340	} PDMRTCREG;
2341	/** Pointer to a RTC registration structure. */
2342	typedef PDMRTCREG *PPDMRTCREG;
2343	/** Pointer to a const RTC registration structure. */
2344	typedef const PDMRTCREG *PCPDMRTCREG;
2345
2346	/** Current PDMRTCREG version number. */
2347	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2348
2349
2350	/**
2351	* RTC device helpers.
2352	*/
2353	typedef struct PDMRTCHLP
2354	{
2355	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2356	uint32_t u32Version;
2357
2358	/* to-be-defined */
2359
2360	} PDMRTCHLP;
2361	/** Pointer to RTC helpers. */
2362	typedef PDMRTCHLP *PPDMRTCHLP;
2363	/** Pointer to const RTC helpers. */
2364	typedef const PDMRTCHLP *PCPDMRTCHLP;
2365
2366	/** Current PDMRTCHLP version number. */
2367	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2368
2369
2370
2371	/** @name Flags for PCI I/O region registration
2372	* @{ */
2373	/** No handle is passed. */
2374	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2375	/** An I/O port handle is passed. */
2376	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2377	/** An MMIO range handle is passed. */
2378	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2379	/** An MMIO2 handle is passed. */
2380	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2381	/** Handle type mask. */
2382	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2383	/** New-style (mostly wrt callbacks). */
2384	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2385	/** Mask of valid flags. */
2386	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2387	/** @} */
2388
2389
2390	/** @name Flags for the guest physical read/write helpers
2391	* @{ */
2392	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2393	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2394	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2395	* by the device in any way. */
2396	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2397	/** The data is metadata and being processed by the device in some way. */
2398	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2399	/** @} */
2400
2401
2402	#ifdef IN_RING3
2403
2404	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2405	* @{ */
2406	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2407	* This is handy when registering multiple PCI device functions and the device
2408	* number is left up to the PCI bus. In order to facilitate one PDM device
2409	* instance for each PCI function, this searches earlier PDM device
2410	* instances as well. */
2411	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2412	/** Use the first unused device number (all functions must be unused). */
2413	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2414	/** Use the first unused device function. */
2415	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2416
2417	/** The device and function numbers are not mandatory, just suggestions. */
2418	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2419	/** Registering a PCI bridge device. */
2420	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2421	/** Valid flag mask. */
2422	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2423	/** @} */
2424
2425	/** Current PDMDEVHLPR3 version number. */
2426	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 55, 0)
2427
2428	/**
2429	* PDM Device API.
2430	*/
2431	typedef struct PDMDEVHLPR3
2432	{
2433	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2434	uint32_t u32Version;
2435
2436	/** @name I/O ports
2437	* @{ */
2438	/**
2439	* Creates a range of I/O ports for a device.
2440	*
2441	* The I/O port range must be mapped in a separately call. Any ring-0 and
2442	* raw-mode context callback handlers needs to be set up in the respective
2443	* contexts.
2444	*
2445	* @returns VBox status.
2446	* @param pDevIns The device instance to register the ports with.
2447	* @param cPorts Number of ports to register.
2448	* @param fFlags IOM_IOPORT_F_XXX.
2449	* @param pPciDev The PCI device the range is associated with, if
2450	* applicable.
2451	* @param iPciRegion The PCI device region in the high 16-bit word and
2452	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2453	* @param pfnOut Pointer to function which is gonna handle OUT
2454	* operations. Optional.
2455	* @param pfnIn Pointer to function which is gonna handle IN operations.
2456	* Optional.
2457	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2458	* operations. Optional.
2459	* @param pfnInStr Pointer to function which is gonna handle string IN
2460	* operations. Optional.
2461	* @param pvUser User argument to pass to the callbacks.
2462	* @param pszDesc Pointer to description string. This must not be freed.
2463	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2464	* coverage is allowed. This must not be freed.
2465	* @param phIoPorts Where to return the I/O port range handle.
2466	*
2467	* @remarks Caller enters the device critical section prior to invoking the
2468	* registered callback methods.
2469	*
2470	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2471	* PDMDevHlpIoPortUnmap.
2472	*/
2473	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2474	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2475	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2476	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2477
2478	/**
2479	* Maps an I/O port range.
2480	*
2481	* @returns VBox status.
2482	* @param pDevIns The device instance to register the ports with.
2483	* @param hIoPorts The I/O port range handle.
2484	* @param Port Where to map the range.
2485	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2486	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2487	*/
2488	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2489
2490	/**
2491	* Unmaps an I/O port range.
2492	*
2493	* @returns VBox status.
2494	* @param pDevIns The device instance to register the ports with.
2495	* @param hIoPorts The I/O port range handle.
2496	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2497	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2498	*/
2499	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2500
2501	/**
2502	* Gets the mapping address of the I/O port range @a hIoPorts.
2503	*
2504	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2505	* parameters).
2506	* @param pDevIns The device instance to register the ports with.
2507	* @param hIoPorts The I/O port range handle.
2508	*/
2509	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2510	/** @} */
2511
2512	/** @name MMIO
2513	* @{ */
2514	/**
2515	* Creates a memory mapped I/O (MMIO) region for a device.
2516	*
2517	* The MMIO region must be mapped in a separately call. Any ring-0 and
2518	* raw-mode context callback handlers needs to be set up in the respective
2519	* contexts.
2520	*
2521	* @returns VBox status.
2522	* @param pDevIns The device instance to register the ports with.
2523	* @param cbRegion The size of the region in bytes.
2524	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2525	* @param pPciDev The PCI device the range is associated with, if
2526	* applicable.
2527	* @param iPciRegion The PCI device region in the high 16-bit word and
2528	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2529	* @param pfnWrite Pointer to function which is gonna handle Write
2530	* operations.
2531	* @param pfnRead Pointer to function which is gonna handle Read
2532	* operations.
2533	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2534	* operations. (optional)
2535	* @param pvUser User argument to pass to the callbacks.
2536	* @param pszDesc Pointer to description string. This must not be freed.
2537	* @param phRegion Where to return the MMIO region handle.
2538	*
2539	* @remarks Caller enters the device critical section prior to invoking the
2540	* registered callback methods.
2541	*
2542	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2543	*/
2544	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2545	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2546	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2547	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2548
2549	/**
2550	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2551	*
2552	* @returns VBox status.
2553	* @param pDevIns The device instance the region is associated with.
2554	* @param hRegion The MMIO region handle.
2555	* @param GCPhys Where to map the region.
2556	* @note An MMIO range may overlap with base memory if a lot of RAM is
2557	* configured for the VM, in which case we'll drop the base memory
2558	* pages. Presently we will make no attempt to preserve anything that
2559	* happens to be present in the base memory that is replaced, this is
2560	* technically incorrect but it's just not worth the effort to do
2561	* right, at least not at this point.
2562	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2563	* PDMDevHlpMmioSetUpContext
2564	*/
2565	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2566
2567	/**
2568	* Unmaps a memory mapped I/O (MMIO) region.
2569	*
2570	* @returns VBox status.
2571	* @param pDevIns The device instance the region is associated with.
2572	* @param hRegion The MMIO region handle.
2573	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2574	* PDMDevHlpMmioSetUpContext
2575	*/
2576	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2577
2578	/**
2579	* Reduces the length of a MMIO range.
2580	*
2581	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2582	* only work during saved state restore. It will not call the PCI bus code, as
2583	* that is expected to restore the saved resource configuration.
2584	*
2585	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2586	* called it will only map @a cbRegion bytes and not the value set during
2587	* registration.
2588	*
2589	* @return VBox status code.
2590	* @param pDevIns The device owning the range.
2591	* @param hRegion The MMIO region handle.
2592	* @param cbRegion The new size, must be smaller.
2593	*/
2594	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2595
2596	/**
2597	* Gets the mapping address of the MMIO region @a hRegion.
2598	*
2599	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2600	* @param pDevIns The device instance to register the ports with.
2601	* @param hRegion The MMIO region handle.
2602	*/
2603	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2604	/** @} */
2605
2606	/** @name MMIO2
2607	* @{ */
2608	/**
2609	* Creates a MMIO2 region.
2610	*
2611	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2612	* associated with a device. It is also non-shared memory with a permanent
2613	* ring-3 mapping and page backing (presently).
2614	*
2615	* @returns VBox status.
2616	* @param pDevIns The device instance.
2617	* @param pPciDev The PCI device the region is associated with, or
2618	* NULL if no PCI device association.
2619	* @param iPciRegion The region number. Use the PCI region number as
2620	* this must be known to the PCI bus device too. If
2621	* it's not associated with the PCI device, then
2622	* any number up to UINT8_MAX is fine.
2623	* @param cbRegion The size (in bytes) of the region.
2624	* @param fFlags Reserved for future use, must be zero.
2625	* @param pszDesc Pointer to description string. This must not be
2626	* freed.
2627	* @param ppvMapping Where to store the address of the ring-3 mapping
2628	* of the memory.
2629	* @param phRegion Where to return the MMIO2 region handle.
2630	*
2631	* @thread EMT(0)
2632	*/
2633	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2634	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2635
2636	/**
2637	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2638	*
2639	* Any physical access handlers registered for the region must be deregistered
2640	* before calling this function.
2641	*
2642	* @returns VBox status code.
2643	* @param pDevIns The device instance.
2644	* @param hRegion The MMIO2 region handle.
2645	* @thread EMT.
2646	*/
2647	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2648
2649	/**
2650	* Maps a MMIO2 region (into the guest physical address space).
2651	*
2652	* @returns VBox status.
2653	* @param pDevIns The device instance the region is associated with.
2654	* @param hRegion The MMIO2 region handle.
2655	* @param GCPhys Where to map the region.
2656	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2657	* configured for the VM, in which case we'll drop the base memory
2658	* pages. Presently we will make no attempt to preserve anything that
2659	* happens to be present in the base memory that is replaced, this is
2660	* technically incorrect but it's just not worth the effort to do
2661	* right, at least not at this point.
2662	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2663	*/
2664	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2665
2666	/**
2667	* Unmaps a MMIO2 region.
2668	*
2669	* @returns VBox status.
2670	* @param pDevIns The device instance the region is associated with.
2671	* @param hRegion The MMIO2 region handle.
2672	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2673	*/
2674	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2675
2676	/**
2677	* Reduces the length of a MMIO range.
2678	*
2679	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2680	* only work during saved state restore. It will not call the PCI bus code, as
2681	* that is expected to restore the saved resource configuration.
2682	*
2683	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2684	* called it will only map @a cbRegion bytes and not the value set during
2685	* registration.
2686	*
2687	* @return VBox status code.
2688	* @param pDevIns The device owning the range.
2689	* @param hRegion The MMIO2 region handle.
2690	* @param cbRegion The new size, must be smaller.
2691	*/
2692	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2693
2694	/**
2695	* Gets the mapping address of the MMIO region @a hRegion.
2696	*
2697	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2698	* @param pDevIns The device instance to register the ports with.
2699	* @param hRegion The MMIO2 region handle.
2700	*/
2701	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2702
2703	/**
2704	* Changes the number of an MMIO2 or pre-registered MMIO region.
2705	*
2706	* This should only be used to deal with saved state problems, so there is no
2707	* convenience inline wrapper for this method.
2708	*
2709	* @returns VBox status code.
2710	* @param pDevIns The device instance.
2711	* @param hRegion The MMIO2 region handle.
2712	* @param iNewRegion The new region index.
2713	*
2714	* @sa @bugref{9359}
2715	*/
2716	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2717	/** @} */
2718
2719	/**
2720	* Register a ROM (BIOS) region.
2721	*
2722	* It goes without saying that this is read-only memory. The memory region must be
2723	* in unassigned memory. I.e. from the top of the address space or on the PC in
2724	* the 0xa0000-0xfffff range.
2725	*
2726	* @returns VBox status.
2727	* @param pDevIns The device instance owning the ROM region.
2728	* @param GCPhysStart First physical address in the range.
2729	* Must be page aligned!
2730	* @param cbRange The size of the range (in bytes).
2731	* Must be page aligned!
2732	* @param pvBinary Pointer to the binary data backing the ROM image.
2733	* @param cbBinary The size of the binary pointer. This must
2734	* be equal or smaller than @a cbRange.
2735	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2736	* @param pszDesc Pointer to description string. This must not be freed.
2737	*
2738	* @remark There is no way to remove the rom, automatically on device cleanup or
2739	* manually from the device yet. At present I doubt we need such features...
2740	*/
2741	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2742	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2743
2744	/**
2745	* Changes the protection of shadowed ROM mapping.
2746	*
2747	* This is intented for use by the system BIOS, chipset or device in question to
2748	* change the protection of shadowed ROM code after init and on reset.
2749	*
2750	* @param pDevIns The device instance.
2751	* @param GCPhysStart Where the mapping starts.
2752	* @param cbRange The size of the mapping.
2753	* @param enmProt The new protection type.
2754	*/
2755	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2756
2757	/**
2758	* Register a save state data unit.
2759	*
2760	* @returns VBox status.
2761	* @param pDevIns The device instance.
2762	* @param uVersion Data layout version number.
2763	* @param cbGuess The approximate amount of data in the unit.
2764	* Only for progress indicators.
2765	* @param pszBefore Name of data unit which we should be put in
2766	* front of. Optional (NULL).
2767	*
2768	* @param pfnLivePrep Prepare live save callback, optional.
2769	* @param pfnLiveExec Execute live save callback, optional.
2770	* @param pfnLiveVote Vote live save callback, optional.
2771	*
2772	* @param pfnSavePrep Prepare save callback, optional.
2773	* @param pfnSaveExec Execute save callback, optional.
2774	* @param pfnSaveDone Done save callback, optional.
2775	*
2776	* @param pfnLoadPrep Prepare load callback, optional.
2777	* @param pfnLoadExec Execute load callback, optional.
2778	* @param pfnLoadDone Done load callback, optional.
2779	* @remarks Caller enters the device critical section prior to invoking the
2780	* registered callback methods.
2781	*/
2782	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2783	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2784	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2785	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2786
2787	/** @name Exported SSM Functions
2788	* @{ */
2789	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2790	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2791	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2792	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2793	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2794	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2795	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2796	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2797	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2798	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2799	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2800	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2801	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2802	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2803	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2804	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2805	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2806	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2807	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2808	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2809	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2810	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2811	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2812	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2813	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2814	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2815	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2816	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2817	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2818	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2819	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2820	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2821	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2822	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2823	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2824	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2825	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2826	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2827	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2828	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2829	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2830	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2831	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2832	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2833	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2834	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2835	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2836	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2837	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2838	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2839	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2840	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2841	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2842	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2843	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2844	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2845	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2846	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2847	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2848	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2849	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2850	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2851	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2852	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2853	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2854	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2855	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2856	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2857	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2858	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2859	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2860	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2861	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2862	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2863	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2864	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2865	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2866	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2867	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2868	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2869	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2870	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2871	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2872	/** @} */
2873
2874	/**
2875	* Creates a timer w/ a cross context handle.
2876	*
2877	* @returns VBox status.
2878	* @param pDevIns The device instance.
2879	* @param enmClock The clock to use on this timer.
2880	* @param pfnCallback Callback function.
2881	* @param pvUser User argument for the callback.
2882	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2883	* @param pszDesc Pointer to description string which must stay around
2884	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2885	* @param phTimer Where to store the timer handle on success.
2886	* @remarks Caller enters the device critical section prior to invoking the
2887	* callback.
2888	*/
2889	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2890	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
2891
2892	/** @name Timer handle method wrappers
2893	* @{ */
2894	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2895	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2896	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2897	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2898	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2899	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2900	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2901	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2902	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2903	/** Takes the clock lock then enters the specified critical section. */
2904	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2905	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2906	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2907	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2908	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2909	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2910	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2911	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2912	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2913	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2914	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2915	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2916	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2917	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2918	/** @sa TMR3TimerSkip */
2919	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2920	/** @} */
2921
2922	/**
2923	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2924	*
2925	* @returns pTime.
2926	* @param pDevIns The device instance.
2927	* @param pTime Where to store the time.
2928	*/
2929	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2930
2931	/** @name Exported CFGM Functions.
2932	* @{ */
2933	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2934	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2935	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
2936	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2937	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2938	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
2939	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
2940	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
2941	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2942	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2943	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
2944	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
2945	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
2946	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
2947	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
2948	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
2949	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
2950	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
2951	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
2952	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
2953	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
2954	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
2955	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
2956	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
2957	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
2958	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
2959	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2960	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2961	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
2962	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
2963	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
2964	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
2965	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
2966	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
2967	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
2968	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
2969	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
2970	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
2971	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
2972	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
2973	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
2974	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
2975	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
2976	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
2977	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
2978	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
2979	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
2980	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
2981	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
2982	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
2983	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
2984	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
2985	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
2986	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
2987	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
2988	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
2989	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
2990	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
2991	const char pszValidValues, const char pszValidNodes,
2992	const char *pszWho, uint32_t uInstance));
2993	/** @} */
2994
2995	/**
2996	* Read physical memory.
2997	*
2998	* @returns VINF_SUCCESS (for now).
2999	* @param pDevIns The device instance.
3000	* @param GCPhys Physical address start reading from.
3001	* @param pvBuf Where to put the read bits.
3002	* @param cbRead How many bytes to read.
3003	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3004	* @thread Any thread, but the call may involve the emulation thread.
3005	*/
3006	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3007
3008	/**
3009	* Write to physical memory.
3010	*
3011	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3012	* @param pDevIns The device instance.
3013	* @param GCPhys Physical address to write to.
3014	* @param pvBuf What to write.
3015	* @param cbWrite How many bytes to write.
3016	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3017	* @thread Any thread, but the call may involve the emulation thread.
3018	*/
3019	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3020
3021	/**
3022	* Requests the mapping of a guest page into ring-3.
3023	*
3024	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3025	* release it.
3026	*
3027	* This API will assume your intention is to write to the page, and will
3028	* therefore replace shared and zero pages. If you do not intend to modify the
3029	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3030	*
3031	* @returns VBox status code.
3032	* @retval VINF_SUCCESS on success.
3033	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3034	* backing or if the page has any active access handlers. The caller
3035	* must fall back on using PGMR3PhysWriteExternal.
3036	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3037	*
3038	* @param pDevIns The device instance.
3039	* @param GCPhys The guest physical address of the page that
3040	* should be mapped.
3041	* @param fFlags Flags reserved for future use, MBZ.
3042	* @param ppv Where to store the address corresponding to
3043	* GCPhys.
3044	* @param pLock Where to store the lock information that
3045	* pfnPhysReleasePageMappingLock needs.
3046	*
3047	* @remark Avoid calling this API from within critical sections (other than the
3048	* PGM one) because of the deadlock risk when we have to delegating the
3049	* task to an EMT.
3050	* @thread Any.
3051	*/
3052	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3053	PPGMPAGEMAPLOCK pLock));
3054
3055	/**
3056	* Requests the mapping of a guest page into ring-3, external threads.
3057	*
3058	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3059	* release it.
3060	*
3061	* @returns VBox status code.
3062	* @retval VINF_SUCCESS on success.
3063	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3064	* backing or if the page as an active ALL access handler. The caller
3065	* must fall back on using PGMPhysRead.
3066	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3067	*
3068	* @param pDevIns The device instance.
3069	* @param GCPhys The guest physical address of the page that
3070	* should be mapped.
3071	* @param fFlags Flags reserved for future use, MBZ.
3072	* @param ppv Where to store the address corresponding to
3073	* GCPhys.
3074	* @param pLock Where to store the lock information that
3075	* pfnPhysReleasePageMappingLock needs.
3076	*
3077	* @remark Avoid calling this API from within critical sections.
3078	* @thread Any.
3079	*/
3080	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3081	void const **ppv, PPGMPAGEMAPLOCK pLock));
3082
3083	/**
3084	* Release the mapping of a guest page.
3085	*
3086	* This is the counter part of pfnPhysGCPhys2CCPtr and
3087	* pfnPhysGCPhys2CCPtrReadOnly.
3088	*
3089	* @param pDevIns The device instance.
3090	* @param pLock The lock structure initialized by the mapping
3091	* function.
3092	*/
3093	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3094
3095	/**
3096	* Read guest physical memory by virtual address.
3097	*
3098	* @param pDevIns The device instance.
3099	* @param pvDst Where to put the read bits.
3100	* @param GCVirtSrc Guest virtual address to start reading from.
3101	* @param cb How many bytes to read.
3102	* @thread The emulation thread.
3103	*/
3104	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3105
3106	/**
3107	* Write to guest physical memory by virtual address.
3108	*
3109	* @param pDevIns The device instance.
3110	* @param GCVirtDst Guest virtual address to write to.
3111	* @param pvSrc What to write.
3112	* @param cb How many bytes to write.
3113	* @thread The emulation thread.
3114	*/
3115	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3116
3117	/**
3118	* Convert a guest virtual address to a guest physical address.
3119	*
3120	* @returns VBox status code.
3121	* @param pDevIns The device instance.
3122	* @param GCPtr Guest virtual address.
3123	* @param pGCPhys Where to store the GC physical address
3124	* corresponding to GCPtr.
3125	* @thread The emulation thread.
3126	* @remark Careful with page boundaries.
3127	*/
3128	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3129
3130	/**
3131	* Checks if a GC physical address is a normal page,
3132	* i.e. not ROM, MMIO or reserved.
3133	*
3134	* @returns true if normal.
3135	* @returns false if invalid, ROM, MMIO or reserved page.
3136	* @param pDevIns The device instance.
3137	* @param GCPhys The physical address to check.
3138	*/
3139	DECLR3CALLBACKMEMBER(bool, pfnPhysIsGCPhysNormal,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
3140
3141	/**
3142	* Inflate or deflate a memory balloon
3143	*
3144	* @returns VBox status code.
3145	* @param pDevIns The device instance.
3146	* @param fInflate Inflate or deflate memory balloon
3147	* @param cPages Number of pages to free
3148	* @param paPhysPage Array of guest physical addresses
3149	*/
3150	DECLR3CALLBACKMEMBER(int, pfnPhysChangeMemBalloon,(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage));
3151
3152	/**
3153	* Allocate memory which is associated with current VM instance
3154	* and automatically freed on it's destruction.
3155	*
3156	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3157	* @param pDevIns The device instance.
3158	* @param cb Number of bytes to allocate.
3159	*/
3160	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3161
3162	/**
3163	* Allocate memory which is associated with current VM instance
3164	* and automatically freed on it's destruction. The memory is ZEROed.
3165	*
3166	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3167	* @param pDevIns The device instance.
3168	* @param cb Number of bytes to allocate.
3169	*/
3170	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3171
3172	/**
3173	* Allocating string printf.
3174	*
3175	* @returns Pointer to the string.
3176	* @param pDevIns The device instance.
3177	* @param enmTag The statistics tag.
3178	* @param pszFormat The format string.
3179	* @param va Format arguments.
3180	*/
3181	DECLR3CALLBACKMEMBER(char , pfnMMHeapAPrintfV,(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, va_list va));
3182
3183	/**
3184	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3185	*
3186	* @param pDevIns The device instance.
3187	* @param pv Pointer to the memory to free.
3188	*/
3189	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3190
3191	/**
3192	* Returns the physical RAM size of the VM.
3193	*
3194	* @returns RAM size in bytes.
3195	* @param pDevIns The device instance.
3196	*/
3197	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSize,(PPDMDEVINS pDevIns));
3198
3199	/**
3200	* Returns the physical RAM size of the VM below the 4GB boundary.
3201	*
3202	* @returns RAM size in bytes.
3203	* @param pDevIns The device instance.
3204	*/
3205	DECLR3CALLBACKMEMBER(uint32_t, pfnMMPhysGetRamSizeBelow4GB,(PPDMDEVINS pDevIns));
3206
3207	/**
3208	* Returns the physical RAM size of the VM above the 4GB boundary.
3209	*
3210	* @returns RAM size in bytes.
3211	* @param pDevIns The device instance.
3212	*/
3213	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSizeAbove4GB,(PPDMDEVINS pDevIns));
3214
3215	/**
3216	* Gets the VM state.
3217	*
3218	* @returns VM state.
3219	* @param pDevIns The device instance.
3220	* @thread Any thread (just keep in mind that it's volatile info).
3221	*/
3222	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3223
3224	/**
3225	* Checks if the VM was teleported and hasn't been fully resumed yet.
3226	*
3227	* @returns true / false.
3228	* @param pDevIns The device instance.
3229	* @thread Any thread.
3230	*/
3231	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3232
3233	/**
3234	* Set the VM error message
3235	*
3236	* @returns rc.
3237	* @param pDevIns The device instance.
3238	* @param rc VBox status code.
3239	* @param SRC_POS Use RT_SRC_POS.
3240	* @param pszFormat Error message format string.
3241	* @param va Error message arguments.
3242	*/
3243	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3244	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3245
3246	/**
3247	* Set the VM runtime error message
3248	*
3249	* @returns VBox status code.
3250	* @param pDevIns The device instance.
3251	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3252	* @param pszErrorId Error ID string.
3253	* @param pszFormat Error message format string.
3254	* @param va Error message arguments.
3255	*/
3256	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3257	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3258
3259	/**
3260	* Special interface for implementing a HLT-like port on a device.
3261	*
3262	* This can be called directly from device code, provide the device is trusted
3263	* to access the VMM directly. Since we may not have an accurate register set
3264	* and the caller certainly shouldn't (device code does not access CPU
3265	* registers), this function will return when interrupts are pending regardless
3266	* of the actual EFLAGS.IF state.
3267	*
3268	* @returns VBox error status (never informational statuses).
3269	* @param pDevIns The device instance.
3270	* @param idCpu The id of the calling EMT.
3271	*/
3272	DECLR3CALLBACKMEMBER(int, pfnVMWaitForDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3273
3274	/**
3275	* Wakes up a CPU that has called PDMDEVHLPR3::pfnVMWaitForDeviceReady.
3276	*
3277	* @returns VBox error status (never informational statuses).
3278	* @param pDevIns The device instance.
3279	* @param idCpu The id of the calling EMT.
3280	*/
3281	DECLR3CALLBACKMEMBER(int, pfnVMNotifyCpuDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3282
3283	/**
3284	* Convenience wrapper for VMR3ReqCallU.
3285	*
3286	* This assumes (1) you're calling a function that returns an VBox status code
3287	* and that you do not wish to wait for it to complete.
3288	*
3289	* @returns VBox status code returned by VMR3ReqCallVU.
3290	*
3291	* @param pDevIns The device instance.
3292	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3293	* one of the following special values:
3294	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3295	* @param pfnFunction Pointer to the function to call.
3296	* @param cArgs Number of arguments following in the ellipsis.
3297	* @param Args Argument vector.
3298	*
3299	* @remarks See remarks on VMR3ReqCallVU.
3300	*/
3301	DECLR3CALLBACKMEMBER(int, pfnVMReqCallNoWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3302
3303	/**
3304	* Convenience wrapper for VMR3ReqCallU.
3305	*
3306	* This assumes (1) you're calling a function that returns void, (2) that you
3307	* wish to wait for ever for it to return, and (3) that it's priority request
3308	* that can be safely be handled during async suspend and power off.
3309	*
3310	* @returns VBox status code of VMR3ReqCallVU.
3311	*
3312	* @param pDevIns The device instance.
3313	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3314	* one of the following special values:
3315	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3316	* @param pfnFunction Pointer to the function to call.
3317	* @param cArgs Number of arguments following in the ellipsis.
3318	* @param Args Argument vector.
3319	*
3320	* @remarks See remarks on VMR3ReqCallVU.
3321	*/
3322	DECLR3CALLBACKMEMBER(int, pfnVMReqPriorityCallWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3323
3324	/**
3325	* Stops the VM and enters the debugger to look at the guest state.
3326	*
3327	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3328	* invoking this function directly.
3329	*
3330	* @returns VBox status code which must be passed up to the VMM.
3331	* @param pDevIns The device instance.
3332	* @param pszFile Filename of the assertion location.
3333	* @param iLine The linenumber of the assertion location.
3334	* @param pszFunction Function of the assertion location.
3335	* @param pszFormat Message. (optional)
3336	* @param args Message parameters.
3337	*/
3338	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3339	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3340
3341	/**
3342	* Register a info handler with DBGF.
3343	*
3344	* @returns VBox status code.
3345	* @param pDevIns The device instance.
3346	* @param pszName The identifier of the info.
3347	* @param pszDesc The description of the info and any arguments
3348	* the handler may take.
3349	* @param pfnHandler The handler function to be called to display the
3350	* info.
3351	*/
3352	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3353
3354	/**
3355	* Register a info handler with DBGF, argv style.
3356	*
3357	* @returns VBox status code.
3358	* @param pDevIns The device instance.
3359	* @param pszName The identifier of the info.
3360	* @param pszDesc The description of the info and any arguments
3361	* the handler may take.
3362	* @param pfnHandler The handler function to be called to display the
3363	* info.
3364	*/
3365	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3366
3367	/**
3368	* Registers a set of registers for a device.
3369	*
3370	* The @a pvUser argument of the getter and setter callbacks will be
3371	* @a pDevIns. The register names will be prefixed by the device name followed
3372	* immediately by the instance number.
3373	*
3374	* @returns VBox status code.
3375	* @param pDevIns The device instance.
3376	* @param paRegisters The register descriptors.
3377	*
3378	* @remarks The device critical section is NOT entered prior to working the
3379	* callbacks registered via this helper!
3380	*/
3381	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3382
3383	/**
3384	* Gets the trace buffer handle.
3385	*
3386	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3387	* really inteded for direct usage, thus no inline wrapper function.
3388	*
3389	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3390	* @param pDevIns The device instance.
3391	*/
3392	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3393
3394	/**
3395	* Registers a statistics sample.
3396	*
3397	* @param pDevIns Device instance of the DMA.
3398	* @param pvSample Pointer to the sample.
3399	* @param enmType Sample type. This indicates what pvSample is
3400	* pointing at.
3401	* @param pszName Sample name, unix path style. If this does not
3402	* start with a '/', the default prefix will be
3403	* prepended, otherwise it will be used as-is.
3404	* @param enmUnit Sample unit.
3405	* @param pszDesc Sample description.
3406	*/
3407	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3408
3409	/**
3410	* Same as pfnSTAMRegister except that the name is specified in a
3411	* RTStrPrintfV like fashion.
3412	*
3413	* @returns VBox status.
3414	* @param pDevIns Device instance of the DMA.
3415	* @param pvSample Pointer to the sample.
3416	* @param enmType Sample type. This indicates what pvSample is
3417	* pointing at.
3418	* @param enmVisibility Visibility type specifying whether unused
3419	* statistics should be visible or not.
3420	* @param enmUnit Sample unit.
3421	* @param pszDesc Sample description.
3422	* @param pszName Sample name format string, unix path style. If
3423	* this does not start with a '/', the default
3424	* prefix will be prepended, otherwise it will be
3425	* used as-is.
3426	* @param args Arguments to the format string.
3427	*/
3428	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3429	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3430	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3431
3432	/**
3433	* Registers a PCI device with the default PCI bus.
3434	*
3435	* If a PDM device has more than one PCI device, they must be registered in the
3436	* order of PDMDEVINSR3::apPciDevs.
3437	*
3438	* @returns VBox status code.
3439	* @param pDevIns The device instance.
3440	* @param pPciDev The PCI device structure.
3441	* This must be kept in the instance data.
3442	* The PCI configuration must be initialized before registration.
3443	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3444	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3445	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3446	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3447	* device number (0-31). This will be ignored if
3448	* the CFGM configuration contains a PCIDeviceNo
3449	* value.
3450	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3451	* function number (0-7). This will be ignored if
3452	* the CFGM configuration contains a PCIFunctionNo
3453	* value.
3454	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3455	* The pointer is saved, so don't free or changed.
3456	* @note The PCI device configuration is now implicit from the apPciDevs
3457	* index, meaning that the zero'th entry is the primary one and
3458	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3459	*/
3460	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3461	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3462
3463	/**
3464	* Initialize MSI or MSI-X emulation support for the given PCI device.
3465	*
3466	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3467	*
3468	* @returns VBox status code.
3469	* @param pDevIns The device instance.
3470	* @param pPciDev The PCI device. NULL is an alias for the first
3471	* one registered.
3472	* @param pMsiReg MSI emulation registration structure.
3473	*/
3474	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3475
3476	/**
3477	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3478	*
3479	* @returns VBox status code.
3480	* @param pDevIns The device instance.
3481	* @param pPciDev The PCI device structure. If NULL the default
3482	* PCI device for this device instance is used.
3483	* @param iRegion The region number.
3484	* @param cbRegion Size of the region.
3485	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3486	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3487	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3488	* @a fFlags, UINT64_MAX if no handle is passed
3489	* (old style).
3490	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3491	* handle is specified. The callback will be
3492	* invoked holding only the PDM lock. The device
3493	* lock will _not_ be taken (due to lock order).
3494	*/
3495	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3496	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3497	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3498
3499	/**
3500	* Register PCI configuration space read/write callbacks.
3501	*
3502	* @returns VBox status code.
3503	* @param pDevIns The device instance.
3504	* @param pPciDev The PCI device structure. If NULL the default
3505	* PCI device for this device instance is used.
3506	* @param pfnRead Pointer to the user defined PCI config read function.
3507	* to call default PCI config read function. Can be NULL.
3508	* @param pfnWrite Pointer to the user defined PCI config write function.
3509	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3510	* is NOT take because that is very likely be a lock order violation.
3511	* @thread EMT(0)
3512	* @note Only callable during VM creation.
3513	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3514	*/
3515	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3516	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3517
3518	/**
3519	* Perform a PCI configuration space write.
3520	*
3521	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3522	*
3523	* @returns Strict VBox status code (mainly DBGFSTOP).
3524	* @param pDevIns The device instance.
3525	* @param pPciDev The PCI device which config space is being read.
3526	* @param uAddress The config space address.
3527	* @param cb The size of the read: 1, 2 or 4 bytes.
3528	* @param u32Value The value to write.
3529	*/
3530	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3531	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3532
3533	/**
3534	* Perform a PCI configuration space read.
3535	*
3536	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3537	*
3538	* @returns Strict VBox status code (mainly DBGFSTOP).
3539	* @param pDevIns The device instance.
3540	* @param pPciDev The PCI device which config space is being read.
3541	* @param uAddress The config space address.
3542	* @param cb The size of the read: 1, 2 or 4 bytes.
3543	* @param pu32Value Where to return the value.
3544	*/
3545	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3546	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3547
3548	/**
3549	* Bus master physical memory read.
3550	*
3551	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3552	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3553	* @param pDevIns The device instance.
3554	* @param pPciDev The PCI device structure. If NULL the default
3555	* PCI device for this device instance is used.
3556	* @param GCPhys Physical address start reading from.
3557	* @param pvBuf Where to put the read bits.
3558	* @param cbRead How many bytes to read.
3559	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3560	* @thread Any thread, but the call may involve the emulation thread.
3561	*/
3562	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3563
3564	/**
3565	* Bus master physical memory write.
3566	*
3567	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3568	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3569	* @param pDevIns The device instance.
3570	* @param pPciDev The PCI device structure. If NULL the default
3571	* PCI device for this device instance is used.
3572	* @param GCPhys Physical address to write to.
3573	* @param pvBuf What to write.
3574	* @param cbWrite How many bytes to write.
3575	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3576	* @thread Any thread, but the call may involve the emulation thread.
3577	*/
3578	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3579
3580	/**
3581	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3582	* physical memory write operation.
3583	*
3584	* Refer pfnPhysGCPhys2CCPtr() for further details.
3585	*
3586	* @returns VBox status code.
3587	* @param pDevIns The device instance.
3588	* @param pPciDev The PCI device structure. If NULL the default
3589	* PCI device for this device instance is used.
3590	* @param GCPhys The guest physical address of the page that should be
3591	* mapped.
3592	* @param fFlags Flags reserved for future use, MBZ.
3593	* @param ppv Where to store the address corresponding to GCPhys.
3594	* @param pLock Where to store the lock information that
3595	* pfnPhysReleasePageMappingLock needs.
3596	*
3597	* @remarks Avoid calling this API from within critical sections (other than the PGM
3598	* one) because of the deadlock risk when we have to delegating the task to
3599	* an EMT.
3600	* @thread Any.
3601	*/
3602	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3603	void **ppv, PPGMPAGEMAPLOCK pLock));
3604
3605	/**
3606	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3607	* for a bus master physical memory read operation.
3608	*
3609	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3610	*
3611	* @returns VBox status code.
3612	* @param pDevIns The device instance.
3613	* @param pPciDev The PCI device structure. If NULL the default
3614	* PCI device for this device instance is used.
3615	* @param GCPhys The guest physical address of the page that
3616	* should be mapped.
3617	* @param fFlags Flags reserved for future use, MBZ.
3618	* @param ppv Where to store the address corresponding to
3619	* GCPhys.
3620	* @param pLock Where to store the lock information that
3621	* pfnPhysReleasePageMappingLock needs.
3622	*
3623	* @remarks Avoid calling this API from within critical sections.
3624	* @thread Any.
3625	*/
3626	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3627	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3628
3629	/**
3630	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3631	* master physical memory write operation.
3632	*
3633	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3634	* ASAP to release them.
3635	*
3636	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3637	*
3638	* @returns VBox status code.
3639	* @param pDevIns The device instance.
3640	* @param pPciDev The PCI device structure. If NULL the default
3641	* PCI device for this device instance is used.
3642	* @param cPages Number of pages to lock.
3643	* @param paGCPhysPages The guest physical address of the pages that
3644	* should be mapped (@a cPages entries).
3645	* @param fFlags Flags reserved for future use, MBZ.
3646	* @param papvPages Where to store the ring-3 mapping addresses
3647	* corresponding to @a paGCPhysPages.
3648	* @param paLocks Where to store the locking information that
3649	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3650	* in length).
3651	*/
3652	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3653	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3654	PPGMPAGEMAPLOCK paLocks));
3655
3656	/**
3657	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3658	* master physical memory read operation.
3659	*
3660	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3661	* ASAP to release them.
3662	*
3663	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3664	*
3665	* @returns VBox status code.
3666	* @param pDevIns The device instance.
3667	* @param pPciDev The PCI device structure. If NULL the default
3668	* PCI device for this device instance is used.
3669	* @param cPages Number of pages to lock.
3670	* @param paGCPhysPages The guest physical address of the pages that
3671	* should be mapped (@a cPages entries).
3672	* @param fFlags Flags reserved for future use, MBZ.
3673	* @param papvPages Where to store the ring-3 mapping addresses
3674	* corresponding to @a paGCPhysPages.
3675	* @param paLocks Where to store the lock information that
3676	* pfnPhysReleasePageMappingLock needs (@a cPages
3677	* in length).
3678	*/
3679	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3680	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3681	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3682
3683	/**
3684	* Sets the IRQ for the given PCI device.
3685	*
3686	* @param pDevIns The device instance.
3687	* @param pPciDev The PCI device structure. If NULL the default
3688	* PCI device for this device instance is used.
3689	* @param iIrq IRQ number to set.
3690	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3691	* @thread Any thread, but will involve the emulation thread.
3692	*/
3693	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3694
3695	/**
3696	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3697	* the request when not called from EMT.
3698	*
3699	* @param pDevIns The device instance.
3700	* @param pPciDev The PCI device structure. If NULL the default
3701	* PCI device for this device instance is used.
3702	* @param iIrq IRQ number to set.
3703	* @param iLevel IRQ level.
3704	* @thread Any thread, but will involve the emulation thread.
3705	*/
3706	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3707
3708	/**
3709	* Set ISA IRQ for a device.
3710	*
3711	* @param pDevIns The device instance.
3712	* @param iIrq IRQ number to set.
3713	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3714	* @thread Any thread, but will involve the emulation thread.
3715	*/
3716	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3717
3718	/**
3719	* Set the ISA IRQ for a device, but don't wait for EMT to process
3720	* the request when not called from EMT.
3721	*
3722	* @param pDevIns The device instance.
3723	* @param iIrq IRQ number to set.
3724	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3725	* @thread Any thread, but will involve the emulation thread.
3726	*/
3727	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3728
3729	/**
3730	* Attaches a driver (chain) to the device.
3731	*
3732	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3733	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3734	*
3735	* @returns VBox status code.
3736	* @param pDevIns The device instance.
3737	* @param iLun The logical unit to attach.
3738	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3739	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3740	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3741	* for the live of the device instance.
3742	*/
3743	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3744	PPDMIBASE ppBaseInterface, const char pszDesc));
3745
3746	/**
3747	* Detaches an attached driver (chain) from the device again.
3748	*
3749	* @returns VBox status code.
3750	* @param pDevIns The device instance.
3751	* @param pDrvIns The driver instance to detach.
3752	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3753	*/
3754	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3755
3756	/**
3757	* Reconfigures the driver chain for a LUN, detaching any driver currently
3758	* present there.
3759	*
3760	* Caller will have attach it, of course.
3761	*
3762	* @returns VBox status code.
3763	* @param pDevIns The device instance.
3764	* @param iLun The logical unit to reconfigure.
3765	* @param cDepth The depth of the driver chain. Determins the
3766	* size of @a papszDrivers and @a papConfigs.
3767	* @param papszDrivers The names of the drivers to configure in the
3768	* chain, first entry is the one immediately
3769	* below the device/LUN
3770	* @param papConfigs The configurations for each of the drivers
3771	* in @a papszDrivers array. NULL entries
3772	* corresponds to empty 'Config' nodes. This
3773	* function will take ownership of non-NULL
3774	* CFGM sub-trees and set the array member to
3775	* NULL, so the caller can do cleanups on
3776	* failure. This parameter is optional.
3777	* @param fFlags Reserved, MBZ.
3778	*/
3779	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3780	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3781
3782	/** @name Exported PDM Queue Functions
3783	* @{ */
3784	/**
3785	* Create a queue.
3786	*
3787	* @returns VBox status code.
3788	* @param pDevIns The device instance.
3789	* @param cbItem The size of a queue item.
3790	* @param cItems The number of items in the queue.
3791	* @param cMilliesInterval The number of milliseconds between polling the queue.
3792	* If 0 then the emulation thread will be notified whenever an item arrives.
3793	* @param pfnCallback The consumer function.
3794	* @param fRZEnabled Set if the queue should work in RC and R0.
3795	* @param pszName The queue base name. The instance number will be
3796	* appended automatically.
3797	* @param phQueue Where to store the queue handle on success.
3798	* @thread EMT(0)
3799	* @remarks The device critical section will NOT be entered before calling the
3800	* callback. No locks will be held, but for now it's safe to assume
3801	* that only one EMT will do queue callbacks at any one time.
3802	*/
3803	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3804	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3805	PDMQUEUEHANDLE *phQueue));
3806
3807	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3808	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3809	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3810	/** @} */
3811
3812	/** @name PDM Task
3813	* @{ */
3814	/**
3815	* Create an asynchronous ring-3 task.
3816	*
3817	* @returns VBox status code.
3818	* @param pDevIns The device instance.
3819	* @param fFlags PDMTASK_F_XXX
3820	* @param pszName The function name or similar. Used for statistics,
3821	* so no slashes.
3822	* @param pfnCallback The task function.
3823	* @param pvUser User argument for the task function.
3824	* @param phTask Where to return the task handle.
3825	* @thread EMT(0)
3826	*/
3827	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3828	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3829	/**
3830	* Triggers the running the given task.
3831	*
3832	* @returns VBox status code.
3833	* @retval VINF_ALREADY_POSTED is the task is already pending.
3834	* @param pDevIns The device instance.
3835	* @param hTask The task to trigger.
3836	* @thread Any thread.
3837	*/
3838	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3839	/** @} */
3840
3841	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3842	* These semaphores can be signalled from ring-0.
3843	* @{ */
3844	/** @sa SUPSemEventCreate */
3845	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3846	/** @sa SUPSemEventClose */
3847	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3848	/** @sa SUPSemEventSignal */
3849	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3850	/** @sa SUPSemEventWaitNoResume */
3851	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3852	/** @sa SUPSemEventWaitNsAbsIntr */
3853	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3854	/** @sa SUPSemEventWaitNsRelIntr */
3855	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3856	/** @sa SUPSemEventGetResolution */
3857	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3858	/** @} */
3859
3860	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3861	* These semaphores can be signalled from ring-0.
3862	* @{ */
3863	/** @sa SUPSemEventMultiCreate */
3864	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3865	/** @sa SUPSemEventMultiClose */
3866	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3867	/** @sa SUPSemEventMultiSignal */
3868	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3869	/** @sa SUPSemEventMultiReset */
3870	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3871	/** @sa SUPSemEventMultiWaitNoResume */
3872	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3873	/** @sa SUPSemEventMultiWaitNsAbsIntr */
3874	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3875	/** @sa SUPSemEventMultiWaitNsRelIntr */
3876	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3877	/** @sa SUPSemEventMultiGetResolution */
3878	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3879	/** @} */
3880
3881	/**
3882	* Initializes a PDM critical section.
3883	*
3884	* The PDM critical sections are derived from the IPRT critical sections, but
3885	* works in RC and R0 as well.
3886	*
3887	* @returns VBox status code.
3888	* @param pDevIns The device instance.
3889	* @param pCritSect Pointer to the critical section.
3890	* @param SRC_POS Use RT_SRC_POS.
3891	* @param pszNameFmt Format string for naming the critical section.
3892	* For statistics and lock validation.
3893	* @param va Arguments for the format string.
3894	*/
3895	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3896	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3897
3898	/**
3899	* Gets the NOP critical section.
3900	*
3901	* @returns The ring-3 address of the NOP critical section.
3902	* @param pDevIns The device instance.
3903	*/
3904	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3905
3906	/**
3907	* Changes the device level critical section from the automatically created
3908	* default to one desired by the device constructor.
3909	*
3910	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
3911	* the additional contexts.
3912	*
3913	* @returns VBox status code.
3914	* @param pDevIns The device instance.
3915	* @param pCritSect The critical section to use. NULL is not
3916	* valid, instead use the NOP critical
3917	* section.
3918	*/
3919	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3920
3921	/** @name Exported PDM Critical Section Functions
3922	* @{ */
3923	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3924	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3925	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3926	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3927	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3928	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3929	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3930	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3931	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3932	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3933	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3934	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3935	/** @} */
3936
3937	/** @name Exported PDM Read/Write Critical Section Functions
3938	* @{ */
3939	DECLR3CALLBACKMEMBER(int, pfnCritSectRwInit,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
3940	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3941	DECLR3CALLBACKMEMBER(int, pfnCritSectRwDelete,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3942
3943	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
3944	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3945	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3946	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3947	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3948
3949	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
3950	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3951	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3952	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3953	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3954
3955	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3956	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
3957	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3958	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3959	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3960	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3961	/** @} */
3962
3963	/**
3964	* Creates a PDM thread.
3965	*
3966	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3967	* resuming, and destroying the thread as the VM state changes.
3968	*
3969	* @returns VBox status code.
3970	* @param pDevIns The device instance.
3971	* @param ppThread Where to store the thread 'handle'.
3972	* @param pvUser The user argument to the thread function.
3973	* @param pfnThread The thread function.
3974	* @param pfnWakeup The wakup callback. This is called on the EMT
3975	* thread when a state change is pending.
3976	* @param cbStack See RTThreadCreate.
3977	* @param enmType See RTThreadCreate.
3978	* @param pszName See RTThreadCreate.
3979	* @remarks The device critical section will NOT be entered prior to invoking
3980	* the function pointers.
3981	*/
3982	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3983	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3984
3985	/** @name Exported PDM Thread Functions
3986	* @{ */
3987	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3988	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3989	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3990	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3991	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3992	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3993	/** @} */
3994
3995	/**
3996	* Set up asynchronous handling of a suspend, reset or power off notification.
3997	*
3998	* This shall only be called when getting the notification. It must be called
3999	* for each one.
4000	*
4001	* @returns VBox status code.
4002	* @param pDevIns The device instance.
4003	* @param pfnAsyncNotify The callback.
4004	* @thread EMT(0)
4005	* @remarks The caller will enter the device critical section prior to invoking
4006	* the callback.
4007	*/
4008	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
4009
4010	/**
4011	* Notify EMT(0) that the device has completed the asynchronous notification
4012	* handling.
4013	*
4014	* This can be called at any time, spurious calls will simply be ignored.
4015	*
4016	* @param pDevIns The device instance.
4017	* @thread Any
4018	*/
4019	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
4020
4021	/**
4022	* Register the RTC device.
4023	*
4024	* @returns VBox status code.
4025	* @param pDevIns The device instance.
4026	* @param pRtcReg Pointer to a RTC registration structure.
4027	* @param ppRtcHlp Where to store the pointer to the helper
4028	* functions.
4029	*/
4030	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
4031
4032	/**
4033	* Register a PCI Bus.
4034	*
4035	* @returns VBox status code, but the positive values 0..31 are used to indicate
4036	* bus number rather than informational status codes.
4037	* @param pDevIns The device instance.
4038	* @param pPciBusReg Pointer to PCI bus registration structure.
4039	* @param ppPciHlp Where to store the pointer to the PCI Bus
4040	* helpers.
4041	* @param piBus Where to return the PDM bus number. Optional.
4042	*/
4043	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
4044	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
4045
4046	/**
4047	* Register the IOMMU device.
4048	*
4049	* @returns VBox status code.
4050	* @param pDevIns The device instance.
4051	* @param pIommuReg Pointer to a IOMMU registration structure.
4052	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
4053	* helpers.
4054	* @param pidxIommu Where to return the IOMMU index. Optional.
4055	*/
4056	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
4057	uint32_t *pidxIommu));
4058
4059	/**
4060	* Register the PIC device.
4061	*
4062	* @returns VBox status code.
4063	* @param pDevIns The device instance.
4064	* @param pPicReg Pointer to a PIC registration structure.
4065	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
4066	* helpers.
4067	* @sa PDMDevHlpPICSetUpContext
4068	*/
4069	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4070
4071	/**
4072	* Register the APIC device.
4073	*
4074	* @returns VBox status code.
4075	* @param pDevIns The device instance.
4076	*/
4077	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
4078
4079	/**
4080	* Register the I/O APIC device.
4081	*
4082	* @returns VBox status code.
4083	* @param pDevIns The device instance.
4084	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4085	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
4086	* helpers.
4087	*/
4088	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4089
4090	/**
4091	* Register the HPET device.
4092	*
4093	* @returns VBox status code.
4094	* @param pDevIns The device instance.
4095	* @param pHpetReg Pointer to a HPET registration structure.
4096	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4097	* helpers.
4098	*/
4099	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4100
4101	/**
4102	* Register a raw PCI device.
4103	*
4104	* @returns VBox status code.
4105	* @param pDevIns The device instance.
4106	* @param pPciRawReg Pointer to a raw PCI registration structure.
4107	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4108	* device helpers.
4109	*/
4110	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4111
4112	/**
4113	* Register the DMA device.
4114	*
4115	* @returns VBox status code.
4116	* @param pDevIns The device instance.
4117	* @param pDmacReg Pointer to a DMAC registration structure.
4118	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4119	*/
4120	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4121
4122	/**
4123	* Register transfer function for DMA channel.
4124	*
4125	* @returns VBox status code.
4126	* @param pDevIns The device instance.
4127	* @param uChannel Channel number.
4128	* @param pfnTransferHandler Device specific transfer callback function.
4129	* @param pvUser User pointer to pass to the callback.
4130	* @thread EMT
4131	*/
4132	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4133
4134	/**
4135	* Read memory.
4136	*
4137	* @returns VBox status code.
4138	* @param pDevIns The device instance.
4139	* @param uChannel Channel number.
4140	* @param pvBuffer Pointer to target buffer.
4141	* @param off DMA position.
4142	* @param cbBlock Block size.
4143	* @param pcbRead Where to store the number of bytes which was
4144	* read. optional.
4145	* @thread EMT
4146	*/
4147	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4148
4149	/**
4150	* Write memory.
4151	*
4152	* @returns VBox status code.
4153	* @param pDevIns The device instance.
4154	* @param uChannel Channel number.
4155	* @param pvBuffer Memory to write.
4156	* @param off DMA position.
4157	* @param cbBlock Block size.
4158	* @param pcbWritten Where to store the number of bytes which was
4159	* written. optional.
4160	* @thread EMT
4161	*/
4162	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4163
4164	/**
4165	* Set the DREQ line.
4166	*
4167	* @returns VBox status code.
4168	* @param pDevIns Device instance.
4169	* @param uChannel Channel number.
4170	* @param uLevel Level of the line.
4171	* @thread EMT
4172	*/
4173	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4174
4175	/**
4176	* Get channel mode.
4177	*
4178	* @returns Channel mode. See specs.
4179	* @param pDevIns The device instance.
4180	* @param uChannel Channel number.
4181	* @thread EMT
4182	*/
4183	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4184
4185	/**
4186	* Schedule DMA execution.
4187	*
4188	* @param pDevIns The device instance.
4189	* @thread Any thread.
4190	*/
4191	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4192
4193	/**
4194	* Write CMOS value and update the checksum(s).
4195	*
4196	* @returns VBox status code.
4197	* @param pDevIns The device instance.
4198	* @param iReg The CMOS register index.
4199	* @param u8Value The CMOS register value.
4200	* @thread EMT
4201	*/
4202	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4203
4204	/**
4205	* Read CMOS value.
4206	*
4207	* @returns VBox status code.
4208	* @param pDevIns The device instance.
4209	* @param iReg The CMOS register index.
4210	* @param pu8Value Where to store the CMOS register value.
4211	* @thread EMT
4212	*/
4213	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4214
4215	/**
4216	* Assert that the current thread is the emulation thread.
4217	*
4218	* @returns True if correct.
4219	* @returns False if wrong.
4220	* @param pDevIns The device instance.
4221	* @param pszFile Filename of the assertion location.
4222	* @param iLine The linenumber of the assertion location.
4223	* @param pszFunction Function of the assertion location.
4224	*/
4225	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4226
4227	/**
4228	* Assert that the current thread is NOT the emulation thread.
4229	*
4230	* @returns True if correct.
4231	* @returns False if wrong.
4232	* @param pDevIns The device instance.
4233	* @param pszFile Filename of the assertion location.
4234	* @param iLine The linenumber of the assertion location.
4235	* @param pszFunction Function of the assertion location.
4236	*/
4237	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4238
4239	/**
4240	* Resolves the symbol for a raw-mode context interface.
4241	*
4242	* @returns VBox status code.
4243	* @param pDevIns The device instance.
4244	* @param pvInterface The interface structure.
4245	* @param cbInterface The size of the interface structure.
4246	* @param pszSymPrefix What to prefix the symbols in the list with
4247	* before resolving them. This must start with
4248	* 'dev' and contain the driver name.
4249	* @param pszSymList List of symbols corresponding to the interface.
4250	* There is generally a there is generally a define
4251	* holding this list associated with the interface
4252	* definition (INTERFACE_SYM_LIST). For more
4253	* details see PDMR3LdrGetInterfaceSymbols.
4254	* @thread EMT
4255	*/
4256	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4257	const char pszSymPrefix, const char pszSymList));
4258
4259	/**
4260	* Resolves the symbol for a ring-0 context interface.
4261	*
4262	* @returns VBox status code.
4263	* @param pDevIns The device instance.
4264	* @param pvInterface The interface structure.
4265	* @param cbInterface The size of the interface structure.
4266	* @param pszSymPrefix What to prefix the symbols in the list with
4267	* before resolving them. This must start with
4268	* 'dev' and contain the driver name.
4269	* @param pszSymList List of symbols corresponding to the interface.
4270	* There is generally a there is generally a define
4271	* holding this list associated with the interface
4272	* definition (INTERFACE_SYM_LIST). For more
4273	* details see PDMR3LdrGetInterfaceSymbols.
4274	* @thread EMT
4275	*/
4276	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4277	const char pszSymPrefix, const char pszSymList));
4278
4279	/**
4280	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4281	*
4282	* @returns VBox status code.
4283	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4284	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4285	*
4286	* @param pDevIns The device instance.
4287	* @param uOperation The operation to perform.
4288	* @param u64Arg 64-bit integer argument.
4289	* @thread EMT
4290	*/
4291	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4292
4293	/**
4294	* Gets the reason for the most recent VM suspend.
4295	*
4296	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4297	* suspend has been made or if the pDevIns is invalid.
4298	* @param pDevIns The device instance.
4299	*/
4300	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4301
4302	/**
4303	* Gets the reason for the most recent VM resume.
4304	*
4305	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4306	* resume has been made or if the pDevIns is invalid.
4307	* @param pDevIns The device instance.
4308	*/
4309	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4310
4311	/**
4312	* Requests the mapping of multiple guest page into ring-3.
4313	*
4314	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4315	* ASAP to release them.
4316	*
4317	* This API will assume your intention is to write to the pages, and will
4318	* therefore replace shared and zero pages. If you do not intend to modify the
4319	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4320	*
4321	* @returns VBox status code.
4322	* @retval VINF_SUCCESS on success.
4323	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4324	* backing or if any of the pages the page has any active access
4325	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4326	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4327	* an invalid physical address.
4328	*
4329	* @param pDevIns The device instance.
4330	* @param cPages Number of pages to lock.
4331	* @param paGCPhysPages The guest physical address of the pages that
4332	* should be mapped (@a cPages entries).
4333	* @param fFlags Flags reserved for future use, MBZ.
4334	* @param papvPages Where to store the ring-3 mapping addresses
4335	* corresponding to @a paGCPhysPages.
4336	* @param paLocks Where to store the locking information that
4337	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4338	* in length).
4339	*
4340	* @remark Avoid calling this API from within critical sections (other than the
4341	* PGM one) because of the deadlock risk when we have to delegating the
4342	* task to an EMT.
4343	* @thread Any.
4344	* @since 6.0.6
4345	*/
4346	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4347	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4348
4349	/**
4350	* Requests the mapping of multiple guest page into ring-3, for reading only.
4351	*
4352	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4353	* ASAP to release them.
4354	*
4355	* @returns VBox status code.
4356	* @retval VINF_SUCCESS on success.
4357	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4358	* backing or if any of the pages the page has an active ALL access
4359	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4360	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4361	* an invalid physical address.
4362	*
4363	* @param pDevIns The device instance.
4364	* @param cPages Number of pages to lock.
4365	* @param paGCPhysPages The guest physical address of the pages that
4366	* should be mapped (@a cPages entries).
4367	* @param fFlags Flags reserved for future use, MBZ.
4368	* @param papvPages Where to store the ring-3 mapping addresses
4369	* corresponding to @a paGCPhysPages.
4370	* @param paLocks Where to store the lock information that
4371	* pfnPhysReleasePageMappingLock needs (@a cPages
4372	* in length).
4373	*
4374	* @remark Avoid calling this API from within critical sections.
4375	* @thread Any.
4376	* @since 6.0.6
4377	*/
4378	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4379	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4380
4381	/**
4382	* Release the mappings of multiple guest pages.
4383	*
4384	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4385	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4386	*
4387	* @param pDevIns The device instance.
4388	* @param cPages Number of pages to unlock.
4389	* @param paLocks The lock structures initialized by the mapping
4390	* function (@a cPages in length).
4391	* @thread Any.
4392	* @since 6.0.6
4393	*/
4394	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4395
4396	/**
4397	* Returns the micro architecture used for the guest.
4398	*
4399	* @returns CPU micro architecture enum.
4400	* @param pDevIns The device instance.
4401	*/
4402	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4403
4404	/**
4405	* Get the number of physical and linear address bits supported by the guest.
4406	*
4407	* @param pDevIns The device instance.
4408	* @param pcPhysAddrWidth Where to store the number of physical address bits
4409	* supported by the guest.
4410	* @param pcLinearAddrWidth Where to store the number of linear address bits
4411	* supported by the guest.
4412	*/
4413	DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4414	uint8_t *pcLinearAddrWidth));
4415
4416	/** Space reserved for future members.
4417	* @{ */
4418	/**
4419	* Deregister zero or more samples given their name prefix.
4420	*
4421	* @returns VBox status code.
4422	* @param pDevIns The device instance.
4423	* @param pszPrefix The name prefix of the samples to remove. If this does
4424	* not start with a '/', the default prefix will be
4425	* prepended, otherwise it will be used as-is.
4426	*/
4427	DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4428	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4429	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4430	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4431	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4432	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4433	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4434	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4435	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4436	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4437	/** @} */
4438
4439
4440	/** API available to trusted devices only.
4441	*
4442	* These APIs are providing unrestricted access to the guest and the VM,
4443	* or they are interacting intimately with PDM.
4444	*
4445	* @{
4446	*/
4447
4448	/**
4449	* Gets the user mode VM handle. Restricted API.
4450	*
4451	* @returns User mode VM Handle.
4452	* @param pDevIns The device instance.
4453	*/
4454	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4455
4456	/**
4457	* Gets the global VM handle. Restricted API.
4458	*
4459	* @returns VM Handle.
4460	* @param pDevIns The device instance.
4461	*/
4462	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4463
4464	/**
4465	* Gets the VMCPU handle. Restricted API.
4466	*
4467	* @returns VMCPU Handle.
4468	* @param pDevIns The device instance.
4469	*/
4470	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4471
4472	/**
4473	* The the VM CPU ID of the current thread (restricted API).
4474	*
4475	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4476	* @param pDevIns The device instance.
4477	*/
4478	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4479
4480	/**
4481	* Registers the VMM device heap or notifies about mapping/unmapping.
4482	*
4483	* This interface serves three purposes:
4484	*
4485	* -# Register the VMM device heap during device construction
4486	* for the HM to use.
4487	* -# Notify PDM/HM that it's mapped into guest address
4488	* space (i.e. usable).
4489	* -# Notify PDM/HM that it is being unmapped from the guest
4490	* address space (i.e. not usable).
4491	*
4492	* @returns VBox status code.
4493	* @param pDevIns The device instance.
4494	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4495	* not mapped.
4496	* @param pvHeap Ring 3 heap pointer.
4497	* @param cbHeap Size of the heap.
4498	* @thread EMT.
4499	*/
4500	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4501
4502	/**
4503	* Registers the firmware (BIOS, EFI) device with PDM.
4504	*
4505	* The firmware provides a callback table and gets a special PDM helper table.
4506	* There can only be one firmware device for a VM.
4507	*
4508	* @returns VBox status code.
4509	* @param pDevIns The device instance.
4510	* @param pFwReg Firmware registration structure.
4511	* @param ppFwHlp Where to return the firmware helper structure.
4512	* @remarks Only valid during device construction.
4513	* @thread EMT(0)
4514	*/
4515	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4516
4517	/**
4518	* Resets the VM.
4519	*
4520	* @returns The appropriate VBox status code to pass around on reset.
4521	* @param pDevIns The device instance.
4522	* @param fFlags PDMVMRESET_F_XXX flags.
4523	* @thread The emulation thread.
4524	*/
4525	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4526
4527	/**
4528	* Suspends the VM.
4529	*
4530	* @returns The appropriate VBox status code to pass around on suspend.
4531	* @param pDevIns The device instance.
4532	* @thread The emulation thread.
4533	*/
4534	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4535
4536	/**
4537	* Suspends, saves and powers off the VM.
4538	*
4539	* @returns The appropriate VBox status code to pass around.
4540	* @param pDevIns The device instance.
4541	* @thread An emulation thread.
4542	*/
4543	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4544
4545	/**
4546	* Power off the VM.
4547	*
4548	* @returns The appropriate VBox status code to pass around on power off.
4549	* @param pDevIns The device instance.
4550	* @thread The emulation thread.
4551	*/
4552	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4553
4554	/**
4555	* Checks if the Gate A20 is enabled or not.
4556	*
4557	* @returns true if A20 is enabled.
4558	* @returns false if A20 is disabled.
4559	* @param pDevIns The device instance.
4560	* @thread The emulation thread.
4561	*/
4562	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4563
4564	/**
4565	* Enables or disables the Gate A20.
4566	*
4567	* @param pDevIns The device instance.
4568	* @param fEnable Set this flag to enable the Gate A20; clear it
4569	* to disable.
4570	* @thread The emulation thread.
4571	*/
4572	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4573
4574	/**
4575	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4576	* thread.
4577	*
4578	* @param pDevIns The device instance.
4579	* @param iLeaf The CPUID leaf to get.
4580	* @param pEax Where to store the EAX value.
4581	* @param pEbx Where to store the EBX value.
4582	* @param pEcx Where to store the ECX value.
4583	* @param pEdx Where to store the EDX value.
4584	* @thread EMT.
4585	*/
4586	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4587
4588	/**
4589	* Get the current virtual clock time in a VM. The clock frequency must be
4590	* queried separately.
4591	*
4592	* @returns Current clock time.
4593	* @param pDevIns The device instance.
4594	*/
4595	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4596
4597	/**
4598	* Get the frequency of the virtual clock.
4599	*
4600	* @returns The clock frequency (not variable at run-time).
4601	* @param pDevIns The device instance.
4602	*/
4603	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4604
4605	/**
4606	* Get the current virtual clock time in a VM, in nanoseconds.
4607	*
4608	* @returns Current clock time (in ns).
4609	* @param pDevIns The device instance.
4610	*/
4611	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4612
4613	/**
4614	* Gets the support driver session.
4615	*
4616	* This is intended for working with the semaphore API.
4617	*
4618	* @returns Support driver session handle.
4619	* @param pDevIns The device instance.
4620	*/
4621	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4622
4623	/**
4624	* Queries a generic object from the VMM user.
4625	*
4626	* @returns Pointer to the object if found, NULL if not.
4627	* @param pDevIns The device instance.
4628	* @param pUuid The UUID of what's being queried. The UUIDs and
4629	* the usage conventions are defined by the user.
4630	*
4631	* @note It is strictly forbidden to call this internally in VBox! This
4632	* interface is exclusively for hacks in externally developed devices.
4633	*/
4634	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4635
4636	/**
4637	* Register a physical page access handler type.
4638	*
4639	* @returns VBox status code.
4640	* @param pDevIns The device instance.
4641	* @param enmKind The kind of access handler.
4642	* @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4643	* @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4644	* handler should be called.
4645	* @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4646	* ring-3 handler should be called.
4647	* @param pszHandlerRC The name of the raw-mode context handler, NULL if
4648	* the ring-3 handler should be called.
4649	* @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4650	* if the ring-3 handler should be called.
4651	* @param pszDesc The type description.
4652	* @param phType Where to return the type handle (cross context
4653	* safe).
4654	*/
4655	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4656	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4657	const char pszHandlerR0, const char pszPfHandlerR0,
4658	const char pszHandlerRC, const char pszPfHandlerRC,
4659	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4660
4661	/**
4662	* Register a access handler for a physical range.
4663	*
4664	* @returns VBox status code.
4665	* @retval VINF_SUCCESS when successfully installed.
4666	* @retval VINF_PGM_GCPHYS_ALIASED when the shadow PTs could be updated because
4667	* the guest page aliased or/and mapped by multiple PTs. A CR3 sync has been
4668	* flagged together with a pool clearing.
4669	* @retval VERR_PGM_HANDLER_PHYSICAL_CONFLICT if the range conflicts with an existing
4670	* one. A debug assertion is raised.
4671	*
4672	* @param pDevIns The device instance.
4673	* @param GCPhys Start physical address.
4674	* @param GCPhysLast Last physical address. (inclusive)
4675	* @param hType The handler type registration handle.
4676	* @param pvUserR3 User argument to the R3 handler.
4677	* @param pvUserR0 User argument to the R0 handler.
4678	* @param pvUserRC User argument to the RC handler. This can be a value
4679	* less that 0x10000 or a (non-null) pointer that is
4680	* automatically relocated.
4681	* @param pszDesc Description of this handler. If NULL, the type
4682	* description will be used instead.
4683	*/
4684	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalRegister, (PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
4685	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4686	RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc));
4687
4688	/**
4689	* Deregister a physical page access handler.
4690	*
4691	* @returns VBox status code.
4692	* @param pDevIns The device instance.
4693	* @param GCPhys Start physical address.
4694	*/
4695	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalDeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4696
4697	/**
4698	* Temporarily turns off the access monitoring of a page within a monitored
4699	* physical write/all page access handler region.
4700	*
4701	* Use this when no further \#PFs are required for that page. Be aware that
4702	* a page directory sync might reset the flags, and turn on access monitoring
4703	* for the page.
4704	*
4705	* The caller must do required page table modifications.
4706	*
4707	* @returns VBox status code.
4708	* @param pDevIns The device instance.
4709	* @param GCPhys The start address of the access handler. This
4710	* must be a fully page aligned range or we risk
4711	* messing up other handlers installed for the
4712	* start and end pages.
4713	* @param GCPhysPage The physical address of the page to turn off
4714	* access monitoring for.
4715	*/
4716	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
4717
4718	/**
4719	* Resets any modifications to individual pages in a physical page access
4720	* handler region.
4721	*
4722	* This is used in pair with PGMHandlerPhysicalPageTempOff(),
4723	* PGMHandlerPhysicalPageAliasMmio2() or PGMHandlerPhysicalPageAliasHC().
4724	*
4725	* @returns VBox status code.
4726	* @param pDevIns The device instance.
4727	* @param GCPhys The start address of the handler regions, i.e. what you
4728	* passed to PGMR3HandlerPhysicalRegister(),
4729	* PGMHandlerPhysicalRegisterEx() or
4730	* PGMHandlerPhysicalModify().
4731	*/
4732	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalReset,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4733
4734	/**
4735	* Registers the guest memory range that can be used for patching.
4736	*
4737	* @returns VBox status code.
4738	* @param pDevIns The device instance.
4739	* @param GCPtrPatchMem Patch memory range.
4740	* @param cbPatchMem Size of the memory range.
4741	*/
4742	DECLR3CALLBACKMEMBER(int, pfnVMMRegisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4743
4744	/**
4745	* Deregisters the guest memory range that can be used for patching.
4746	*
4747	* @returns VBox status code.
4748	* @param pDevIns The device instance.
4749	* @param GCPtrPatchMem Patch memory range.
4750	* @param cbPatchMem Size of the memory range.
4751	*/
4752	DECLR3CALLBACKMEMBER(int, pfnVMMDeregisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4753
4754	/**
4755	* Registers a new shared module for the VM
4756	*
4757	* @returns VBox status code.
4758	* @param pDevIns The device instance.
4759	* @param enmGuestOS Guest OS type.
4760	* @param pszModuleName Module name.
4761	* @param pszVersion Module version.
4762	* @param GCBaseAddr Module base address.
4763	* @param cbModule Module size.
4764	* @param cRegions Number of shared region descriptors.
4765	* @param paRegions Shared region(s).
4766	*/
4767	DECLR3CALLBACKMEMBER(int, pfnSharedModuleRegister,(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
4768	RTGCPTR GCBaseAddr, uint32_t cbModule,
4769	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions));
4770
4771	/**
4772	* Unregisters a shared module for the VM
4773	*
4774	* @returns VBox status code.
4775	* @param pDevIns The device instance.
4776	* @param pszModuleName Module name.
4777	* @param pszVersion Module version.
4778	* @param GCBaseAddr Module base address.
4779	* @param cbModule Module size.
4780	*/
4781	DECLR3CALLBACKMEMBER(int, pfnSharedModuleUnregister,(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
4782	RTGCPTR GCBaseAddr, uint32_t cbModule));
4783
4784	/**
4785	* Query the state of a page in a shared module
4786	*
4787	* @returns VBox status code.
4788	* @param pDevIns The device instance.
4789	* @param GCPtrPage Page address.
4790	* @param pfShared Shared status (out).
4791	* @param pfPageFlags Page flags (out).
4792	*/
4793	DECLR3CALLBACKMEMBER(int, pfnSharedModuleGetPageState, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags));
4794
4795	/**
4796	* Check all registered modules for changes.
4797	*
4798	* @returns VBox status code.
4799	* @param pDevIns The device instance.
4800	*/
4801	DECLR3CALLBACKMEMBER(int, pfnSharedModuleCheckAll,(PPDMDEVINS pDevIns));
4802
4803	/** @} */
4804
4805	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4806	uint32_t u32TheEnd;
4807	} PDMDEVHLPR3;
4808	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4809	/** Pointer to the R3 PDM Device API. */
4810	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4811	/** Pointer to the R3 PDM Device API, const variant. */
4812	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4813
4814
4815	/**
4816	* PDM Device API - RC Variant.
4817	*/
4818	typedef struct PDMDEVHLPRC
4819	{
4820	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4821	uint32_t u32Version;
4822
4823	/**
4824	* Sets up raw-mode context callback handlers for an I/O port range.
4825	*
4826	* The range must have been registered in ring-3 first using
4827	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4828	*
4829	* @returns VBox status.
4830	* @param pDevIns The device instance to register the ports with.
4831	* @param hIoPorts The I/O port range handle.
4832	* @param pfnOut Pointer to function which is gonna handle OUT
4833	* operations. Optional.
4834	* @param pfnIn Pointer to function which is gonna handle IN operations.
4835	* Optional.
4836	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4837	* operations. Optional.
4838	* @param pfnInStr Pointer to function which is gonna handle string IN
4839	* operations. Optional.
4840	* @param pvUser User argument to pass to the callbacks.
4841	*
4842	* @remarks Caller enters the device critical section prior to invoking the
4843	* registered callback methods.
4844	*
4845	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4846	* PDMDevHlpIoPortUnmap.
4847	*/
4848	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4849	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4850	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4851	void *pvUser));
4852
4853	/**
4854	* Sets up raw-mode context callback handlers for an MMIO region.
4855	*
4856	* The region must have been registered in ring-3 first using
4857	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4858	*
4859	* @returns VBox status.
4860	* @param pDevIns The device instance to register the ports with.
4861	* @param hRegion The MMIO region handle.
4862	* @param pfnWrite Pointer to function which is gonna handle Write
4863	* operations.
4864	* @param pfnRead Pointer to function which is gonna handle Read
4865	* operations.
4866	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4867	* operations. (optional)
4868	* @param pvUser User argument to pass to the callbacks.
4869	*
4870	* @remarks Caller enters the device critical section prior to invoking the
4871	* registered callback methods.
4872	*
4873	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4874	* PDMDevHlpMmioUnmap.
4875	*/
4876	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4877	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4878
4879	/**
4880	* Sets up a raw-mode mapping for an MMIO2 region.
4881	*
4882	* The region must have been created in ring-3 first using
4883	* PDMDevHlpMmio2Create().
4884	*
4885	* @returns VBox status.
4886	* @param pDevIns The device instance to register the ports with.
4887	* @param hRegion The MMIO2 region handle.
4888	* @param offSub Start of what to map into raw-mode. Must be page aligned.
4889	* @param cbSub Number of bytes to map into raw-mode. Must be page
4890	* aligned. Zero is an alias for everything.
4891	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4892	* @thread EMT(0)
4893	* @note Only available at VM creation time.
4894	*
4895	* @sa PDMDevHlpMmio2Create().
4896	*/
4897	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4898	size_t offSub, size_t cbSub, void **ppvMapping));
4899
4900	/**
4901	* Bus master physical memory read from the given PCI device.
4902	*
4903	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4904	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4905	* @param pDevIns The device instance.
4906	* @param pPciDev The PCI device structure. If NULL the default
4907	* PCI device for this device instance is used.
4908	* @param GCPhys Physical address start reading from.
4909	* @param pvBuf Where to put the read bits.
4910	* @param cbRead How many bytes to read.
4911	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4912	* @thread Any thread, but the call may involve the emulation thread.
4913	*/
4914	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4915	void *pvBuf, size_t cbRead, uint32_t fFlags));
4916
4917	/**
4918	* Bus master physical memory write from the given PCI device.
4919	*
4920	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4921	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4922	* @param pDevIns The device instance.
4923	* @param pPciDev The PCI device structure. If NULL the default
4924	* PCI device for this device instance is used.
4925	* @param GCPhys Physical address to write to.
4926	* @param pvBuf What to write.
4927	* @param cbWrite How many bytes to write.
4928	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4929	* @thread Any thread, but the call may involve the emulation thread.
4930	*/
4931	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4932	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4933
4934	/**
4935	* Set the IRQ for the given PCI device.
4936	*
4937	* @param pDevIns Device instance.
4938	* @param pPciDev The PCI device structure. If NULL the default
4939	* PCI device for this device instance is used.
4940	* @param iIrq IRQ number to set.
4941	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4942	* @thread Any thread, but will involve the emulation thread.
4943	*/
4944	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4945
4946	/**
4947	* Set ISA IRQ for a device.
4948	*
4949	* @param pDevIns Device instance.
4950	* @param iIrq IRQ number to set.
4951	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4952	* @thread Any thread, but will involve the emulation thread.
4953	*/
4954	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4955
4956	/**
4957	* Read physical memory.
4958	*
4959	* @returns VINF_SUCCESS (for now).
4960	* @param pDevIns Device instance.
4961	* @param GCPhys Physical address start reading from.
4962	* @param pvBuf Where to put the read bits.
4963	* @param cbRead How many bytes to read.
4964	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4965	*/
4966	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
4967
4968	/**
4969	* Write to physical memory.
4970	*
4971	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4972	* @param pDevIns Device instance.
4973	* @param GCPhys Physical address to write to.
4974	* @param pvBuf What to write.
4975	* @param cbWrite How many bytes to write.
4976	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4977	*/
4978	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4979
4980	/**
4981	* Checks if the Gate A20 is enabled or not.
4982	*
4983	* @returns true if A20 is enabled.
4984	* @returns false if A20 is disabled.
4985	* @param pDevIns Device instance.
4986	* @thread The emulation thread.
4987	*/
4988	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4989
4990	/**
4991	* Gets the VM state.
4992	*
4993	* @returns VM state.
4994	* @param pDevIns The device instance.
4995	* @thread Any thread (just keep in mind that it's volatile info).
4996	*/
4997	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4998
4999	/**
5000	* Gets the VM handle. Restricted API.
5001	*
5002	* @returns VM Handle.
5003	* @param pDevIns Device instance.
5004	*/
5005	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5006
5007	/**
5008	* Gets the VMCPU handle. Restricted API.
5009	*
5010	* @returns VMCPU Handle.
5011	* @param pDevIns The device instance.
5012	*/
5013	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5014
5015	/**
5016	* The the VM CPU ID of the current thread (restricted API).
5017	*
5018	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5019	* @param pDevIns The device instance.
5020	*/
5021	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5022
5023	/**
5024	* Get the current virtual clock time in a VM. The clock frequency must be
5025	* queried separately.
5026	*
5027	* @returns Current clock time.
5028	* @param pDevIns The device instance.
5029	*/
5030	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5031
5032	/**
5033	* Get the frequency of the virtual clock.
5034	*
5035	* @returns The clock frequency (not variable at run-time).
5036	* @param pDevIns The device instance.
5037	*/
5038	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5039
5040	/**
5041	* Get the current virtual clock time in a VM, in nanoseconds.
5042	*
5043	* @returns Current clock time (in ns).
5044	* @param pDevIns The device instance.
5045	*/
5046	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5047
5048	/**
5049	* Gets the NOP critical section.
5050	*
5051	* @returns The ring-3 address of the NOP critical section.
5052	* @param pDevIns The device instance.
5053	*/
5054	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5055
5056	/**
5057	* Changes the device level critical section from the automatically created
5058	* default to one desired by the device constructor.
5059	*
5060	* Must first be done in ring-3.
5061	*
5062	* @returns VBox status code.
5063	* @param pDevIns The device instance.
5064	* @param pCritSect The critical section to use. NULL is not
5065	* valid, instead use the NOP critical
5066	* section.
5067	*/
5068	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5069
5070	/** @name Exported PDM Critical Section Functions
5071	* @{ */
5072	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5073	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5074	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5075	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5076	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5077	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5078	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5079	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5080	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5081	/** @} */
5082
5083	/** @name Exported PDM Read/Write Critical Section Functions
5084	* @{ */
5085	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5086	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5087	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5088	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5089	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5090
5091	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5092	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5093	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5094	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5095	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5096
5097	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5098	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5099	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5100	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5101	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5102	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5103	/** @} */
5104
5105	/**
5106	* Gets the trace buffer handle.
5107	*
5108	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5109	* really inteded for direct usage, thus no inline wrapper function.
5110	*
5111	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5112	* @param pDevIns The device instance.
5113	*/
5114	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5115
5116	/**
5117	* Sets up the PCI bus for the raw-mode context.
5118	*
5119	* This must be called after ring-3 has registered the PCI bus using
5120	* PDMDevHlpPCIBusRegister().
5121	*
5122	* @returns VBox status code.
5123	* @param pDevIns The device instance.
5124	* @param pPciBusReg The PCI bus registration information for raw-mode,
5125	* considered volatile.
5126	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
5127	*/
5128	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
5129
5130	/**
5131	* Sets up the IOMMU for the raw-mode context.
5132	*
5133	* This must be called after ring-3 has registered the IOMMU using
5134	* PDMDevHlpIommuRegister().
5135	*
5136	* @returns VBox status code.
5137	* @param pDevIns The device instance.
5138	* @param pIommuReg The IOMMU registration information for raw-mode,
5139	* considered volatile.
5140	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
5141	*/
5142	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
5143
5144	/**
5145	* Sets up the PIC for the ring-0 context.
5146	*
5147	* This must be called after ring-3 has registered the PIC using
5148	* PDMDevHlpPICRegister().
5149	*
5150	* @returns VBox status code.
5151	* @param pDevIns The device instance.
5152	* @param pPicReg The PIC registration information for ring-0,
5153	* considered volatile and copied.
5154	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5155	*/
5156	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5157
5158	/**
5159	* Sets up the APIC for the raw-mode context.
5160	*
5161	* This must be called after ring-3 has registered the APIC using
5162	* PDMDevHlpApicRegister().
5163	*
5164	* @returns VBox status code.
5165	* @param pDevIns The device instance.
5166	*/
5167	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5168
5169	/**
5170	* Sets up the IOAPIC for the ring-0 context.
5171	*
5172	* This must be called after ring-3 has registered the PIC using
5173	* PDMDevHlpIoApicRegister().
5174	*
5175	* @returns VBox status code.
5176	* @param pDevIns The device instance.
5177	* @param pIoApicReg The PIC registration information for ring-0,
5178	* considered volatile and copied.
5179	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5180	*/
5181	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5182
5183	/**
5184	* Sets up the HPET for the raw-mode context.
5185	*
5186	* This must be called after ring-3 has registered the PIC using
5187	* PDMDevHlpHpetRegister().
5188	*
5189	* @returns VBox status code.
5190	* @param pDevIns The device instance.
5191	* @param pHpetReg The PIC registration information for raw-mode,
5192	* considered volatile and copied.
5193	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
5194	*/
5195	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
5196
5197	/** Space reserved for future members.
5198	* @{ */
5199	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
5200	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
5201	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
5202	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
5203	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
5204	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
5205	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
5206	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
5207	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
5208	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
5209	/** @} */
5210
5211	/** Just a safety precaution. */
5212	uint32_t u32TheEnd;
5213	} PDMDEVHLPRC;
5214	/** Pointer PDM Device RC API. */
5215	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
5216	/** Pointer PDM Device RC API. */
5217	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
5218
5219	/** Current PDMDEVHLP version number. */
5220	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 18, 0)
5221
5222
5223	/**
5224	* PDM Device API - R0 Variant.
5225	*/
5226	typedef struct PDMDEVHLPR0
5227	{
5228	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5229	uint32_t u32Version;
5230
5231	/**
5232	* Sets up ring-0 callback handlers for an I/O port range.
5233	*
5234	* The range must have been created in ring-3 first using
5235	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5236	*
5237	* @returns VBox status.
5238	* @param pDevIns The device instance to register the ports with.
5239	* @param hIoPorts The I/O port range handle.
5240	* @param pfnOut Pointer to function which is gonna handle OUT
5241	* operations. Optional.
5242	* @param pfnIn Pointer to function which is gonna handle IN operations.
5243	* Optional.
5244	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5245	* operations. Optional.
5246	* @param pfnInStr Pointer to function which is gonna handle string IN
5247	* operations. Optional.
5248	* @param pvUser User argument to pass to the callbacks.
5249	*
5250	* @remarks Caller enters the device critical section prior to invoking the
5251	* registered callback methods.
5252	*
5253	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5254	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5255	*/
5256	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5257	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5258	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5259	void *pvUser));
5260
5261	/**
5262	* Sets up ring-0 callback handlers for an MMIO region.
5263	*
5264	* The region must have been created in ring-3 first using
5265	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5266	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5267	*
5268	* @returns VBox status.
5269	* @param pDevIns The device instance to register the ports with.
5270	* @param hRegion The MMIO region handle.
5271	* @param pfnWrite Pointer to function which is gonna handle Write
5272	* operations.
5273	* @param pfnRead Pointer to function which is gonna handle Read
5274	* operations.
5275	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5276	* operations. (optional)
5277	* @param pvUser User argument to pass to the callbacks.
5278	*
5279	* @remarks Caller enters the device critical section prior to invoking the
5280	* registered callback methods.
5281	*
5282	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5283	* PDMDevHlpMmioUnmap().
5284	*/
5285	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5286	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5287
5288	/**
5289	* Sets up a ring-0 mapping for an MMIO2 region.
5290	*
5291	* The region must have been created in ring-3 first using
5292	* PDMDevHlpMmio2Create().
5293	*
5294	* @returns VBox status.
5295	* @param pDevIns The device instance to register the ports with.
5296	* @param hRegion The MMIO2 region handle.
5297	* @param offSub Start of what to map into ring-0. Must be page aligned.
5298	* @param cbSub Number of bytes to map into ring-0. Must be page
5299	* aligned. Zero is an alias for everything.
5300	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5301	*
5302	* @thread EMT(0)
5303	* @note Only available at VM creation time.
5304	*
5305	* @sa PDMDevHlpMmio2Create().
5306	*/
5307	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5308	void **ppvMapping));
5309
5310	/**
5311	* Bus master physical memory read from the given PCI device.
5312	*
5313	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5314	* VERR_EM_MEMORY.
5315	* @param pDevIns The device instance.
5316	* @param pPciDev The PCI device structure. If NULL the default
5317	* PCI device for this device instance is used.
5318	* @param GCPhys Physical address start reading from.
5319	* @param pvBuf Where to put the read bits.
5320	* @param cbRead How many bytes to read.
5321	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5322	* @thread Any thread, but the call may involve the emulation thread.
5323	*/
5324	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5325	void *pvBuf, size_t cbRead, uint32_t fFlags));
5326
5327	/**
5328	* Bus master physical memory write from the given PCI device.
5329	*
5330	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5331	* VERR_EM_MEMORY.
5332	* @param pDevIns The device instance.
5333	* @param pPciDev The PCI device structure. If NULL the default
5334	* PCI device for this device instance is used.
5335	* @param GCPhys Physical address to write to.
5336	* @param pvBuf What to write.
5337	* @param cbWrite How many bytes to write.
5338	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5339	* @thread Any thread, but the call may involve the emulation thread.
5340	*/
5341	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5342	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5343
5344	/**
5345	* Set the IRQ for the given PCI device.
5346	*
5347	* @param pDevIns Device instance.
5348	* @param pPciDev The PCI device structure. If NULL the default
5349	* PCI device for this device instance is used.
5350	* @param iIrq IRQ number to set.
5351	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5352	* @thread Any thread, but will involve the emulation thread.
5353	*/
5354	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5355
5356	/**
5357	* Set ISA IRQ for a device.
5358	*
5359	* @param pDevIns Device instance.
5360	* @param iIrq IRQ number to set.
5361	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5362	* @thread Any thread, but will involve the emulation thread.
5363	*/
5364	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5365
5366	/**
5367	* Read physical memory.
5368	*
5369	* @returns VINF_SUCCESS (for now).
5370	* @param pDevIns Device instance.
5371	* @param GCPhys Physical address start reading from.
5372	* @param pvBuf Where to put the read bits.
5373	* @param cbRead How many bytes to read.
5374	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5375	*/
5376	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5377
5378	/**
5379	* Write to physical memory.
5380	*
5381	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5382	* @param pDevIns Device instance.
5383	* @param GCPhys Physical address to write to.
5384	* @param pvBuf What to write.
5385	* @param cbWrite How many bytes to write.
5386	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5387	*/
5388	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5389
5390	/**
5391	* Checks if the Gate A20 is enabled or not.
5392	*
5393	* @returns true if A20 is enabled.
5394	* @returns false if A20 is disabled.
5395	* @param pDevIns Device instance.
5396	* @thread The emulation thread.
5397	*/
5398	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5399
5400	/**
5401	* Gets the VM state.
5402	*
5403	* @returns VM state.
5404	* @param pDevIns The device instance.
5405	* @thread Any thread (just keep in mind that it's volatile info).
5406	*/
5407	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5408
5409	/**
5410	* Gets the VM handle. Restricted API.
5411	*
5412	* @returns VM Handle.
5413	* @param pDevIns Device instance.
5414	*/
5415	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5416
5417	/**
5418	* Gets the VMCPU handle. Restricted API.
5419	*
5420	* @returns VMCPU Handle.
5421	* @param pDevIns The device instance.
5422	*/
5423	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5424
5425	/**
5426	* The the VM CPU ID of the current thread (restricted API).
5427	*
5428	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5429	* @param pDevIns The device instance.
5430	*/
5431	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5432
5433	/** @name Timer handle method wrappers
5434	* @{ */
5435	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5436	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5437	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5438	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5439	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5440	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5441	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5442	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5443	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5444	/** Takes the clock lock then enters the specified critical section. */
5445	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5446	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5447	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5448	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5449	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5450	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5451	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5452	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5453	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5454	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5455	/** @} */
5456
5457	/**
5458	* Get the current virtual clock time in a VM. The clock frequency must be
5459	* queried separately.
5460	*
5461	* @returns Current clock time.
5462	* @param pDevIns The device instance.
5463	*/
5464	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5465
5466	/**
5467	* Get the frequency of the virtual clock.
5468	*
5469	* @returns The clock frequency (not variable at run-time).
5470	* @param pDevIns The device instance.
5471	*/
5472	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5473
5474	/**
5475	* Get the current virtual clock time in a VM, in nanoseconds.
5476	*
5477	* @returns Current clock time (in ns).
5478	* @param pDevIns The device instance.
5479	*/
5480	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5481
5482	/** @name Exported PDM Queue Functions
5483	* @{ */
5484	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5485	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5486	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5487	/** @} */
5488
5489	/** @name PDM Task
5490	* @{ */
5491	/**
5492	* Triggers the running the given task.
5493	*
5494	* @returns VBox status code.
5495	* @retval VINF_ALREADY_POSTED is the task is already pending.
5496	* @param pDevIns The device instance.
5497	* @param hTask The task to trigger.
5498	* @thread Any thread.
5499	*/
5500	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5501	/** @} */
5502
5503	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5504	* These semaphores can be signalled from ring-0.
5505	* @{ */
5506	/** @sa SUPSemEventSignal */
5507	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5508	/** @sa SUPSemEventWaitNoResume */
5509	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5510	/** @sa SUPSemEventWaitNsAbsIntr */
5511	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5512	/** @sa SUPSemEventWaitNsRelIntr */
5513	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5514	/** @sa SUPSemEventGetResolution */
5515	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5516	/** @} */
5517
5518	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5519	* These semaphores can be signalled from ring-0.
5520	* @{ */
5521	/** @sa SUPSemEventMultiSignal */
5522	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5523	/** @sa SUPSemEventMultiReset */
5524	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5525	/** @sa SUPSemEventMultiWaitNoResume */
5526	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5527	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5528	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5529	/** @sa SUPSemEventMultiWaitNsRelIntr */
5530	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5531	/** @sa SUPSemEventMultiGetResolution */
5532	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5533	/** @} */
5534
5535	/**
5536	* Gets the NOP critical section.
5537	*
5538	* @returns The ring-3 address of the NOP critical section.
5539	* @param pDevIns The device instance.
5540	*/
5541	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5542
5543	/**
5544	* Changes the device level critical section from the automatically created
5545	* default to one desired by the device constructor.
5546	*
5547	* Must first be done in ring-3.
5548	*
5549	* @returns VBox status code.
5550	* @param pDevIns The device instance.
5551	* @param pCritSect The critical section to use. NULL is not
5552	* valid, instead use the NOP critical
5553	* section.
5554	*/
5555	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5556
5557	/** @name Exported PDM Critical Section Functions
5558	* @{ */
5559	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5560	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5561	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5562	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5563	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5564	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5565	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5566	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5567	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5568	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5569	/** @} */
5570
5571	/** @name Exported PDM Read/Write Critical Section Functions
5572	* @{ */
5573	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5574	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5575	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5576	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5577	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5578
5579	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5580	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5581	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5582	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5583	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5584
5585	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5586	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5587	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5588	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5589	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5590	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5591	/** @} */
5592
5593	/**
5594	* Gets the trace buffer handle.
5595	*
5596	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5597	* really inteded for direct usage, thus no inline wrapper function.
5598	*
5599	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5600	* @param pDevIns The device instance.
5601	*/
5602	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5603
5604	/**
5605	* Sets up the PCI bus for the ring-0 context.
5606	*
5607	* This must be called after ring-3 has registered the PCI bus using
5608	* PDMDevHlpPCIBusRegister().
5609	*
5610	* @returns VBox status code.
5611	* @param pDevIns The device instance.
5612	* @param pPciBusReg The PCI bus registration information for ring-0,
5613	* considered volatile and copied.
5614	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5615	*/
5616	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5617
5618	/**
5619	* Sets up the IOMMU for the ring-0 context.
5620	*
5621	* This must be called after ring-3 has registered the IOMMU using
5622	* PDMDevHlpIommuRegister().
5623	*
5624	* @returns VBox status code.
5625	* @param pDevIns The device instance.
5626	* @param pIommuReg The IOMMU registration information for ring-0,
5627	* considered volatile and copied.
5628	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5629	*/
5630	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5631
5632	/**
5633	* Sets up the PIC for the ring-0 context.
5634	*
5635	* This must be called after ring-3 has registered the PIC using
5636	* PDMDevHlpPICRegister().
5637	*
5638	* @returns VBox status code.
5639	* @param pDevIns The device instance.
5640	* @param pPicReg The PIC registration information for ring-0,
5641	* considered volatile and copied.
5642	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5643	*/
5644	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5645
5646	/**
5647	* Sets up the APIC for the ring-0 context.
5648	*
5649	* This must be called after ring-3 has registered the APIC using
5650	* PDMDevHlpApicRegister().
5651	*
5652	* @returns VBox status code.
5653	* @param pDevIns The device instance.
5654	*/
5655	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5656
5657	/**
5658	* Sets up the IOAPIC for the ring-0 context.
5659	*
5660	* This must be called after ring-3 has registered the PIC using
5661	* PDMDevHlpIoApicRegister().
5662	*
5663	* @returns VBox status code.
5664	* @param pDevIns The device instance.
5665	* @param pIoApicReg The PIC registration information for ring-0,
5666	* considered volatile and copied.
5667	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5668	*/
5669	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5670
5671	/**
5672	* Sets up the HPET for the ring-0 context.
5673	*
5674	* This must be called after ring-3 has registered the PIC using
5675	* PDMDevHlpHpetRegister().
5676	*
5677	* @returns VBox status code.
5678	* @param pDevIns The device instance.
5679	* @param pHpetReg The PIC registration information for ring-0,
5680	* considered volatile and copied.
5681	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5682	*/
5683	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5684
5685	/**
5686	* Temporarily turns off the access monitoring of a page within a monitored
5687	* physical write/all page access handler region.
5688	*
5689	* Use this when no further \#PFs are required for that page. Be aware that
5690	* a page directory sync might reset the flags, and turn on access monitoring
5691	* for the page.
5692	*
5693	* The caller must do required page table modifications.
5694	*
5695	* @returns VBox status code.
5696	* @param pDevIns The device instance.
5697	* @param GCPhys The start address of the access handler. This
5698	* must be a fully page aligned range or we risk
5699	* messing up other handlers installed for the
5700	* start and end pages.
5701	* @param GCPhysPage The physical address of the page to turn off
5702	* access monitoring for.
5703	*/
5704	DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
5705
5706	/** Space reserved for future members.
5707	* @{ */
5708	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5709	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5710	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5711	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5712	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5713	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5714	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5715	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5716	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5717	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5718	/** @} */
5719
5720	/** Just a safety precaution. */
5721	uint32_t u32TheEnd;
5722	} PDMDEVHLPR0;
5723	/** Pointer PDM Device R0 API. */
5724	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5725	/** Pointer PDM Device GC API. */
5726	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5727
5728	/** Current PDMDEVHLP version number. */
5729	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 23, 0)
5730
5731
5732	/**
5733	* PDM Device Instance.
5734	*/
5735	typedef struct PDMDEVINSR3
5736	{
5737	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5738	uint32_t u32Version;
5739	/** Device instance number. */
5740	uint32_t iInstance;
5741	/** Size of the ring-3, raw-mode and shared bits. */
5742	uint32_t cbRing3;
5743	/** Set if ring-0 context is enabled. */
5744	bool fR0Enabled;
5745	/** Set if raw-mode context is enabled. */
5746	bool fRCEnabled;
5747	/** Alignment padding. */
5748	bool afReserved[2];
5749	/** Pointer the HC PDM Device API. */
5750	PCPDMDEVHLPR3 pHlpR3;
5751	/** Pointer to the shared device instance data. */
5752	RTR3PTR pvInstanceDataR3;
5753	/** Pointer to the device instance data for ring-3. */
5754	RTR3PTR pvInstanceDataForR3;
5755	/** The critical section for the device.
5756	*
5757	* TM and IOM will enter this critical section before calling into the device
5758	* code. PDM will when doing power on, power off, reset, suspend and resume
5759	* notifications. SSM will currently not, but this will be changed later on.
5760	*
5761	* The device gets a critical section automatically assigned to it before
5762	* the constructor is called. If the constructor wishes to use a different
5763	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5764	* very early on.
5765	*/
5766	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5767	/** Pointer to device registration structure. */
5768	R3PTRTYPE(PCPDMDEVREG) pReg;
5769	/** Configuration handle. */
5770	R3PTRTYPE(PCFGMNODE) pCfg;
5771	/** The base interface of the device.
5772	*
5773	* The device constructor initializes this if it has any
5774	* device level interfaces to export. To obtain this interface
5775	* call PDMR3QueryDevice(). */
5776	PDMIBASE IBase;
5777
5778	/** Tracing indicator. */
5779	uint32_t fTracing;
5780	/** The tracing ID of this device. */
5781	uint32_t idTracing;
5782
5783	/** Ring-3 pointer to the raw-mode device instance. */
5784	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5785	/** Raw-mode address of the raw-mode device instance. */
5786	RTRGPTR pDevInsForRC;
5787	/** Ring-3 pointer to the raw-mode instance data. */
5788	RTR3PTR pvInstanceDataForRCR3;
5789
5790	/** PCI device structure size. */
5791	uint32_t cbPciDev;
5792	/** Number of PCI devices in apPciDevs. */
5793	uint32_t cPciDevs;
5794	/** Pointer to the PCI devices for this device.
5795	* (Allocated after the shared instance data.)
5796	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5797	* two devices ever needing it can use cbPciDev and do the address
5798	* calculations that for entries 8+. */
5799	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5800
5801	/** Temporarily. */
5802	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5803	/** Temporarily. */
5804	RTR0PTR pvInstanceDataR0;
5805	/** Temporarily. */
5806	RTRCPTR pvInstanceDataRC;
5807	/** Align the internal data more naturally. */
5808	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5809
5810	/** Internal data. */
5811	union
5812	{
5813	#ifdef PDMDEVINSINT_DECLARED
5814	PDMDEVINSINTR3 s;
5815	#endif
5816	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
5817	} Internal;
5818
5819	/** Device instance data for ring-3. The size of this area is defined
5820	* in the PDMDEVREG::cbInstanceR3 field. */
5821	char achInstanceData[8];
5822	} PDMDEVINSR3;
5823
5824	/** Current PDMDEVINSR3 version number. */
5825	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5826
5827	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5828	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5829
5830
5831	/**
5832	* PDM ring-0 device instance.
5833	*/
5834	typedef struct PDMDEVINSR0
5835	{
5836	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5837	uint32_t u32Version;
5838	/** Device instance number. */
5839	uint32_t iInstance;
5840
5841	/** Pointer the HC PDM Device API. */
5842	PCPDMDEVHLPR0 pHlpR0;
5843	/** Pointer to the shared device instance data. */
5844	RTR0PTR pvInstanceDataR0;
5845	/** Pointer to the device instance data for ring-0. */
5846	RTR0PTR pvInstanceDataForR0;
5847	/** The critical section for the device.
5848	*
5849	* TM and IOM will enter this critical section before calling into the device
5850	* code. PDM will when doing power on, power off, reset, suspend and resume
5851	* notifications. SSM will currently not, but this will be changed later on.
5852	*
5853	* The device gets a critical section automatically assigned to it before
5854	* the constructor is called. If the constructor wishes to use a different
5855	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5856	* very early on.
5857	*/
5858	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5859	/** Pointer to the ring-0 device registration structure. */
5860	R0PTRTYPE(PCPDMDEVREGR0) pReg;
5861	/** Ring-3 address of the ring-3 device instance. */
5862	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5863	/** Ring-0 pointer to the ring-3 device instance. */
5864	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5865	/** Ring-0 pointer to the ring-3 instance data. */
5866	RTR0PTR pvInstanceDataForR3R0;
5867	/** Raw-mode address of the raw-mode device instance. */
5868	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5869	/** Ring-0 pointer to the raw-mode device instance. */
5870	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5871	/** Ring-0 pointer to the raw-mode instance data. */
5872	RTR0PTR pvInstanceDataForRCR0;
5873
5874	/** PCI device structure size. */
5875	uint32_t cbPciDev;
5876	/** Number of PCI devices in apPciDevs. */
5877	uint32_t cPciDevs;
5878	/** Pointer to the PCI devices for this device.
5879	* (Allocated after the shared instance data.)
5880	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5881	* two devices ever needing it can use cbPciDev and do the address
5882	* calculations that for entries 8+. */
5883	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5884
5885	/** Align the internal data more naturally. */
5886	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5887
5888	/** Internal data. */
5889	union
5890	{
5891	#ifdef PDMDEVINSINT_DECLARED
5892	PDMDEVINSINTR0 s;
5893	#endif
5894	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
5895	} Internal;
5896
5897	/** Device instance data for ring-0. The size of this area is defined
5898	* in the PDMDEVREG::cbInstanceR0 field. */
5899	char achInstanceData[8];
5900	} PDMDEVINSR0;
5901
5902	/** Current PDMDEVINSR0 version number. */
5903	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5904
5905
5906	/**
5907	* PDM raw-mode device instance.
5908	*/
5909	typedef struct PDMDEVINSRC
5910	{
5911	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5912	uint32_t u32Version;
5913	/** Device instance number. */
5914	uint32_t iInstance;
5915
5916	/** Pointer the HC PDM Device API. */
5917	PCPDMDEVHLPRC pHlpRC;
5918	/** Pointer to the shared device instance data. */
5919	RTRGPTR pvInstanceDataRC;
5920	/** Pointer to the device instance data for raw-mode. */
5921	RTRGPTR pvInstanceDataForRC;
5922	/** The critical section for the device.
5923	*
5924	* TM and IOM will enter this critical section before calling into the device
5925	* code. PDM will when doing power on, power off, reset, suspend and resume
5926	* notifications. SSM will currently not, but this will be changed later on.
5927	*
5928	* The device gets a critical section automatically assigned to it before
5929	* the constructor is called. If the constructor wishes to use a different
5930	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5931	* very early on.
5932	*/
5933	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5934	/** Pointer to the raw-mode device registration structure. */
5935	RGPTRTYPE(PCPDMDEVREGRC) pReg;
5936
5937	/** PCI device structure size. */
5938	uint32_t cbPciDev;
5939	/** Number of PCI devices in apPciDevs. */
5940	uint32_t cPciDevs;
5941	/** Pointer to the PCI devices for this device.
5942	* (Allocated after the shared instance data.) */
5943	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5944
5945	/** Align the internal data more naturally. */
5946	uint32_t au32Padding[14];
5947
5948	/** Internal data. */
5949	union
5950	{
5951	#ifdef PDMDEVINSINT_DECLARED
5952	PDMDEVINSINTRC s;
5953	#endif
5954	uint8_t padding[0x10];
5955	} Internal;
5956
5957	/** Device instance data for ring-0. The size of this area is defined
5958	* in the PDMDEVREG::cbInstanceR0 field. */
5959	char achInstanceData[8];
5960	} PDMDEVINSRC;
5961
5962	/** Current PDMDEVINSR0 version number. */
5963	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5964
5965
5966	/** @def PDM_DEVINS_VERSION
5967	* Current PDMDEVINS version number. */
5968	/** @typedef PDMDEVINS
5969	* The device instance structure for the current context. */
5970	#ifdef IN_RING3
5971	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5972	typedef PDMDEVINSR3 PDMDEVINS;
5973	#elif defined(IN_RING0)
5974	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5975	typedef PDMDEVINSR0 PDMDEVINS;
5976	#elif defined(IN_RC)
5977	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5978	typedef PDMDEVINSRC PDMDEVINS;
5979	#else
5980	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5981	#endif
5982
5983	/**
5984	* Get the pointer to an PCI device.
5985	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5986	*/
5987	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5988	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5989	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5990
5991	/**
5992	* Calc the pointer to of a given PCI device.
5993	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5994	*/
5995	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5996	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5997	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
5998	: (PPDMPCIDEV)NULL )
5999
6000
6001	/**
6002	* Checks the structure versions of the device instance and device helpers,
6003	* returning if they are incompatible.
6004	*
6005	* This is for use in the constructor.
6006	*
6007	* @param pDevIns The device instance pointer.
6008	*/
6009	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
6010	do \
6011	{ \
6012	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6013	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6014	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6015	VERR_PDM_DEVINS_VERSION_MISMATCH); \
6016	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6017	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6018	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
6019	} while (0)
6020
6021	/**
6022	* Quietly checks the structure versions of the device instance and device
6023	* helpers, returning if they are incompatible.
6024	*
6025	* This is for use in the destructor.
6026	*
6027	* @param pDevIns The device instance pointer.
6028	*/
6029	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
6030	do \
6031	{ \
6032	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6033	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
6034	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
6035	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
6036	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
6037	} while (0)
6038
6039	/**
6040	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
6041	* constructor - returns on failure.
6042	*
6043	* This should be invoked after having initialized the instance data
6044	* sufficiently for the correct operation of the destructor. The destructor is
6045	* always called!
6046	*
6047	* @param pDevIns Pointer to the PDM device instance.
6048	* @param pszValidValues Patterns describing the valid value names. See
6049	* RTStrSimplePatternMultiMatch for details on the
6050	* pattern syntax.
6051	* @param pszValidNodes Patterns describing the valid node (key) names.
6052	* Pass empty string if no valid nodes.
6053	*/
6054	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
6055	do \
6056	{ \
6057	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
6058	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
6059	if (RT_SUCCESS(rcValCfg)) \
6060	{ /* likely */ } else return rcValCfg; \
6061	} while (0)
6062
6063	/** @def PDMDEV_ASSERT_EMT
6064	* Assert that the current thread is the emulation thread.
6065	*/
6066	#ifdef VBOX_STRICT
6067	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6068	#else
6069	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
6070	#endif
6071
6072	/** @def PDMDEV_ASSERT_OTHER
6073	* Assert that the current thread is NOT the emulation thread.
6074	*/
6075	#ifdef VBOX_STRICT
6076	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6077	#else
6078	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
6079	#endif
6080
6081	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
6082	* Assert that the current thread is owner of the VM lock.
6083	*/
6084	#ifdef VBOX_STRICT
6085	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6086	#else
6087	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
6088	#endif
6089
6090	/** @def PDMDEV_SET_ERROR
6091	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
6092	*/
6093	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
6094	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
6095
6096	/** @def PDMDEV_SET_RUNTIME_ERROR
6097	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
6098	*/
6099	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
6100	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
6101
6102	/** @def PDMDEVINS_2_RCPTR
6103	* Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
6104	*/
6105	#ifdef IN_RC
6106	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
6107	#else
6108	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
6109	#endif
6110
6111	/** @def PDMDEVINS_2_R3PTR
6112	* Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
6113	*/
6114	#ifdef IN_RING3
6115	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
6116	#else
6117	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
6118	#endif
6119
6120	/** @def PDMDEVINS_2_R0PTR
6121	* Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
6122	*/
6123	#ifdef IN_RING0
6124	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
6125	#else
6126	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
6127	#endif
6128
6129	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
6130	* Converts a PDM device instance data pointer to a ring-0 one.
6131	* @deprecated
6132	*/
6133	#ifdef IN_RING0
6134	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
6135	#else
6136	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
6137	#endif
6138
6139
6140	/** @def PDMDEVINS_2_DATA
6141	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
6142	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
6143	*
6144	* @note Do no use this macro in common code working on a core structure which
6145	* device specific code has expanded.
6146	*/
6147	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6148	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
6149	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6150	{ \
6151	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
6152	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
6153	return pLambdaRet; \
6154	}(a_pDevIns))
6155	#else
6156	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
6157	#endif
6158
6159	/** @def PDMDEVINS_2_DATA_CC
6160	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
6161	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
6162	*
6163	* @note Do no use this macro in common code working on a core structure which
6164	* device specific code has expanded.
6165	*/
6166	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6167	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
6168	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6169	{ \
6170	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
6171	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
6172	return pLambdaRet; \
6173	}(a_pDevIns))
6174	#else
6175	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
6176	#endif
6177
6178
6179	#ifdef IN_RING3
6180
6181	/**
6182	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
6183	*/
6184	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6185	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
6186	PIOMIOPORTHANDLE phIoPorts)
6187	{
6188	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6189	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6190	if (RT_SUCCESS(rc))
6191	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6192	return rc;
6193	}
6194
6195	/**
6196	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
6197	*/
6198	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6199	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6200	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6201	{
6202	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6203	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6204	if (RT_SUCCESS(rc))
6205	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6206	return rc;
6207	}
6208
6209	/**
6210	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
6211	*/
6212	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6213	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6214	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6215	{
6216	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6217	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6218	if (RT_SUCCESS(rc))
6219	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6220	return rc;
6221	}
6222
6223	/**
6224	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
6225	*/
6226	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6227	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6228	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6229	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6230	{
6231	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6232	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6233	if (RT_SUCCESS(rc))
6234	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6235	return rc;
6236	}
6237
6238	/**
6239	* @sa PDMDevHlpIoPortCreateEx
6240	*/
6241	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6242	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6243	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6244	{
6245	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
6246	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6247	}
6248
6249
6250	/**
6251	* @sa PDMDevHlpIoPortCreateEx
6252	*/
6253	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6254	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6255	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6256	{
6257	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6258	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6259	}
6260
6261	/**
6262	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6263	*/
6264	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6265	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6266	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6267	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6268	{
6269	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6270	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6271	}
6272
6273	/**
6274	* @copydoc PDMDEVHLPR3::pfnIoPortMap
6275	*/
6276	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6277	{
6278	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6279	}
6280
6281	/**
6282	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6283	*/
6284	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6285	{
6286	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6287	}
6288
6289	/**
6290	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6291	*/
6292	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6293	{
6294	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6295	}
6296
6297
6298	#endif /* IN_RING3 */
6299	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6300
6301	/**
6302	* @sa PDMDevHlpIoPortSetUpContextEx
6303	*/
6304	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6305	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6306	{
6307	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6308	}
6309
6310	/**
6311	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6312	*/
6313	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6314	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6315	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6316	{
6317	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6318	}
6319
6320	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6321	#ifdef IN_RING3
6322
6323	/**
6324	* @sa PDMDevHlpMmioCreateEx
6325	*/
6326	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6327	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6328	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6329	{
6330	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6331	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6332	}
6333
6334	/**
6335	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6336	*/
6337	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6338	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6339	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6340	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6341	{
6342	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6343	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6344	}
6345
6346	/**
6347	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6348	*/
6349	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6350	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6351	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6352	{
6353	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6354	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6355	if (RT_SUCCESS(rc))
6356	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6357	return rc;
6358	}
6359
6360	/**
6361	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6362	*/
6363	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6364	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6365	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6366	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6367	{
6368	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6369	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6370	if (RT_SUCCESS(rc))
6371	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6372	return rc;
6373	}
6374
6375	/**
6376	* @copydoc PDMDEVHLPR3::pfnMmioMap
6377	*/
6378	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6379	{
6380	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6381	}
6382
6383	/**
6384	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6385	*/
6386	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6387	{
6388	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6389	}
6390
6391	/**
6392	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6393	*/
6394	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6395	{
6396	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6397	}
6398
6399	/**
6400	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6401	*/
6402	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6403	{
6404	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6405	}
6406
6407	#endif /* IN_RING3 */
6408	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6409
6410	/**
6411	* @sa PDMDevHlpMmioSetUpContextEx
6412	*/
6413	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6414	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6415	{
6416	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6417	}
6418
6419	/**
6420	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6421	*/
6422	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6423	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6424	{
6425	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6426	}
6427
6428	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6429	#ifdef IN_RING3
6430
6431	/**
6432	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6433	*/
6434	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6435	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6436	{
6437	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6438	}
6439
6440	/**
6441	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6442	*/
6443	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6444	{
6445	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6446	}
6447
6448	/**
6449	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6450	*/
6451	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6452	{
6453	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6454	}
6455
6456	/**
6457	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6458	*/
6459	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6460	{
6461	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6462	}
6463
6464	/**
6465	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6466	*/
6467	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6468	{
6469	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6470	}
6471
6472	#endif /* IN_RING3 */
6473	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6474
6475	/**
6476	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6477	*/
6478	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6479	size_t offSub, size_t cbSub, void **ppvMapping)
6480	{
6481	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6482	}
6483
6484	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6485	#ifdef IN_RING3
6486
6487	/**
6488	* @copydoc PDMDEVHLPR3::pfnROMRegister
6489	*/
6490	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6491	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6492	{
6493	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6494	}
6495
6496	/**
6497	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6498	*/
6499	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6500	{
6501	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6502	}
6503
6504	/**
6505	* Register a save state data unit.
6506	*
6507	* @returns VBox status.
6508	* @param pDevIns The device instance.
6509	* @param uVersion Data layout version number.
6510	* @param cbGuess The approximate amount of data in the unit.
6511	* Only for progress indicators.
6512	* @param pfnSaveExec Execute save callback, optional.
6513	* @param pfnLoadExec Execute load callback, optional.
6514	*/
6515	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6516	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6517	{
6518	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6519	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6520	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6521	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6522	}
6523
6524	/**
6525	* Register a save state data unit with a live save callback as well.
6526	*
6527	* @returns VBox status.
6528	* @param pDevIns The device instance.
6529	* @param uVersion Data layout version number.
6530	* @param cbGuess The approximate amount of data in the unit.
6531	* Only for progress indicators.
6532	* @param pfnLiveExec Execute live callback, optional.
6533	* @param pfnSaveExec Execute save callback, optional.
6534	* @param pfnLoadExec Execute load callback, optional.
6535	*/
6536	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6537	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6538	{
6539	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6540	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6541	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6542	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6543	}
6544
6545	/**
6546	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6547	*/
6548	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6549	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6550	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6551	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6552	{
6553	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6554	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6555	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6556	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6557	}
6558
6559	/**
6560	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6561	*/
6562	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6563	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6564	{
6565	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6566	}
6567
6568	#endif /* IN_RING3 */
6569
6570	/**
6571	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6572	*/
6573	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6574	{
6575	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6576	}
6577
6578	/**
6579	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6580	*/
6581	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6582	{
6583	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6584	}
6585
6586	/**
6587	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6588	*/
6589	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6590	{
6591	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6592	}
6593
6594	/**
6595	* @copydoc PDMDEVHLPR3::pfnTimerGet
6596	*/
6597	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6598	{
6599	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6600	}
6601
6602	/**
6603	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6604	*/
6605	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6606	{
6607	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6608	}
6609
6610	/**
6611	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6612	*/
6613	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6614	{
6615	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6616	}
6617
6618	/**
6619	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6620	*/
6621	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6622	{
6623	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6624	}
6625
6626	/**
6627	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6628	*/
6629	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6630	{
6631	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6632	}
6633
6634	/**
6635	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
6636	*/
6637	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6638	{
6639	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6640	}
6641
6642	/**
6643	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6644	*/
6645	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6646	{
6647	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6648	}
6649
6650	/**
6651	* @copydoc PDMDEVHLPR3::pfnTimerSet
6652	*/
6653	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6654	{
6655	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6656	}
6657
6658	/**
6659	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6660	*/
6661	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6662	{
6663	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6664	}
6665
6666	/**
6667	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6668	*/
6669	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6670	{
6671	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6672	}
6673
6674	/**
6675	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6676	*/
6677	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6678	{
6679	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6680	}
6681
6682	/**
6683	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6684	*/
6685	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6686	{
6687	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6688	}
6689
6690	/**
6691	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6692	*/
6693	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6694	{
6695	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6696	}
6697
6698	/**
6699	* @copydoc PDMDEVHLPR3::pfnTimerStop
6700	*/
6701	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6702	{
6703	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6704	}
6705
6706	/**
6707	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6708	*/
6709	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6710	{
6711	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6712	}
6713
6714	/**
6715	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6716	*/
6717	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6718	{
6719	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6720	}
6721
6722	#ifdef IN_RING3
6723
6724	/**
6725	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6726	*/
6727	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6728	{
6729	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6730	}
6731
6732	/**
6733	* @copydoc PDMDEVHLPR3::pfnTimerSave
6734	*/
6735	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6736	{
6737	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6738	}
6739
6740	/**
6741	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6742	*/
6743	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6744	{
6745	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6746	}
6747
6748	/**
6749	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6750	*/
6751	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6752	{
6753	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6754	}
6755
6756	/**
6757	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6758	*/
6759	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6760	{
6761	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6762	}
6763
6764	#endif
6765
6766	/**
6767	* Read physical memory - unknown data usage.
6768	*
6769	* @returns VINF_SUCCESS (for now).
6770	* @param pDevIns The device instance.
6771	* @param GCPhys Physical address start reading from.
6772	* @param pvBuf Where to put the read bits.
6773	* @param cbRead How many bytes to read.
6774	* @thread Any thread, but the call may involve the emulation thread.
6775	*/
6776	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6777	{
6778	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6779	}
6780
6781	/**
6782	* Write to physical memory - unknown data usage.
6783	*
6784	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6785	* @param pDevIns The device instance.
6786	* @param GCPhys Physical address to write to.
6787	* @param pvBuf What to write.
6788	* @param cbWrite How many bytes to write.
6789	* @thread Any thread, but the call may involve the emulation thread.
6790	*/
6791	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6792	{
6793	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6794	}
6795
6796	/**
6797	* Read physical memory - reads meta data processed by the device.
6798	*
6799	* @returns VINF_SUCCESS (for now).
6800	* @param pDevIns The device instance.
6801	* @param GCPhys Physical address start reading from.
6802	* @param pvBuf Where to put the read bits.
6803	* @param cbRead How many bytes to read.
6804	* @thread Any thread, but the call may involve the emulation thread.
6805	*/
6806	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6807	{
6808	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6809	}
6810
6811	/**
6812	* Write to physical memory - written data was created/altered by the device.
6813	*
6814	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6815	* @param pDevIns The device instance.
6816	* @param GCPhys Physical address to write to.
6817	* @param pvBuf What to write.
6818	* @param cbWrite How many bytes to write.
6819	* @thread Any thread, but the call may involve the emulation thread.
6820	*/
6821	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6822	{
6823	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6824	}
6825
6826	/**
6827	* Read physical memory - read data will not be touched by the device.
6828	*
6829	* @returns VINF_SUCCESS (for now).
6830	* @param pDevIns The device instance.
6831	* @param GCPhys Physical address start reading from.
6832	* @param pvBuf Where to put the read bits.
6833	* @param cbRead How many bytes to read.
6834	* @thread Any thread, but the call may involve the emulation thread.
6835	*/
6836	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6837	{
6838	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6839	}
6840
6841	/**
6842	* Write to physical memory - written data was not touched/created by the device.
6843	*
6844	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6845	* @param pDevIns The device instance.
6846	* @param GCPhys Physical address to write to.
6847	* @param pvBuf What to write.
6848	* @param cbWrite How many bytes to write.
6849	* @thread Any thread, but the call may involve the emulation thread.
6850	*/
6851	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6852	{
6853	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6854	}
6855
6856	#ifdef IN_RING3
6857
6858	/**
6859	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6860	*/
6861	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6862	{
6863	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6864	}
6865
6866	/**
6867	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6868	*/
6869	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6870	PPGMPAGEMAPLOCK pLock)
6871	{
6872	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6873	}
6874
6875	/**
6876	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6877	*/
6878	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6879	{
6880	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6881	}
6882
6883	/**
6884	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6885	*/
6886	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6887	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6888	{
6889	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6890	}
6891
6892	/**
6893	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6894	*/
6895	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6896	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6897	{
6898	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6899	}
6900
6901	/**
6902	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6903	*/
6904	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6905	{
6906	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6907	}
6908
6909	/**
6910	* @copydoc PDMDEVHLPR3::pfnPhysIsGCPhysNormal
6911	*/
6912	DECLINLINE(bool) PDMDevHlpPhysIsGCPhysNormal(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
6913	{
6914	return pDevIns->CTX_SUFF(pHlp)->pfnPhysIsGCPhysNormal(pDevIns, GCPhys);
6915	}
6916
6917	/**
6918	* @copydoc PDMDEVHLPR3::pfnPhysChangeMemBalloon
6919	*/
6920	DECLINLINE(int) PDMDevHlpPhysChangeMemBalloon(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
6921	{
6922	return pDevIns->CTX_SUFF(pHlp)->pfnPhysChangeMemBalloon(pDevIns, fInflate, cPages, paPhysPage);
6923	}
6924
6925	/**
6926	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
6927	*/
6928	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
6929	{
6930	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
6931	}
6932
6933	/**
6934	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
6935	*/
6936	DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth)
6937	{
6938	pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
6939	}
6940
6941	/**
6942	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6943	*/
6944	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6945	{
6946	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6947	}
6948
6949	/**
6950	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6951	*/
6952	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6953	{
6954	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6955	}
6956
6957	/**
6958	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6959	*/
6960	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6961	{
6962	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6963	}
6964
6965	/**
6966	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6967	*/
6968	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6969	{
6970	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6971	}
6972
6973	/**
6974	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6975	*/
6976	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6977	{
6978	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6979	}
6980
6981	/**
6982	* Allocating string printf.
6983	*
6984	* @returns Pointer to the string.
6985	* @param pDevIns The device instance.
6986	* @param enmTag The statistics tag.
6987	* @param pszFormat The format string.
6988	* @param ... Format arguments.
6989	*/
6990	DECLINLINE(char ) RT_IPRT_FORMAT_ATTR(2, 3) PDMDevHlpMMHeapAPrintf(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, ...)
6991	{
6992	va_list va;
6993	va_start(va, pszFormat);
6994	char *psz = pDevIns->pHlpR3->pfnMMHeapAPrintfV(pDevIns, enmTag, pszFormat, va);
6995	va_end(va);
6996
6997	return psz;
6998	}
6999
7000	/**
7001	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
7002	*/
7003	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
7004	{
7005	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
7006	}
7007
7008	/**
7009	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSize
7010	*/
7011	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSize(PPDMDEVINS pDevIns)
7012	{
7013	return pDevIns->pHlpR3->pfnMMPhysGetRamSize(pDevIns);
7014	}
7015
7016	/**
7017	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeBelow4GB
7018	*/
7019	DECLINLINE(uint32_t) PDMDevHlpMMPhysGetRamSizeBelow4GB(PPDMDEVINS pDevIns)
7020	{
7021	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeBelow4GB(pDevIns);
7022	}
7023
7024	/**
7025	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeAbove4GB
7026	*/
7027	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSizeAbove4GB(PPDMDEVINS pDevIns)
7028	{
7029	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeAbove4GB(pDevIns);
7030	}
7031	#endif /* IN_RING3 */
7032
7033	/**
7034	* @copydoc PDMDEVHLPR3::pfnVMState
7035	*/
7036	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
7037	{
7038	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
7039	}
7040
7041	#ifdef IN_RING3
7042
7043	/**
7044	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
7045	*/
7046	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
7047	{
7048	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
7049	}
7050
7051	/**
7052	* Set the VM error message
7053	*
7054	* @returns rc.
7055	* @param pDevIns The device instance.
7056	* @param rc VBox status code.
7057	* @param SRC_POS Use RT_SRC_POS.
7058	* @param pszFormat Error message format string.
7059	* @param ... Error message arguments.
7060	* @sa VMSetError
7061	*/
7062	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
7063	const char *pszFormat, ...)
7064	{
7065	va_list va;
7066	va_start(va, pszFormat);
7067	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
7068	va_end(va);
7069	return rc;
7070	}
7071
7072	/**
7073	* Set the VM runtime error message
7074	*
7075	* @returns VBox status code.
7076	* @param pDevIns The device instance.
7077	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
7078	* @param pszErrorId Error ID string.
7079	* @param pszFormat Error message format string.
7080	* @param ... Error message arguments.
7081	* @sa VMSetRuntimeError
7082	*/
7083	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
7084	const char *pszFormat, ...)
7085	{
7086	va_list va;
7087	int rc;
7088	va_start(va, pszFormat);
7089	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
7090	va_end(va);
7091	return rc;
7092	}
7093
7094	/**
7095	* @copydoc PDMDEVHLPR3::pfnVMWaitForDeviceReady
7096	*/
7097	DECLINLINE(int) PDMDevHlpVMWaitForDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7098	{
7099	return pDevIns->CTX_SUFF(pHlp)->pfnVMWaitForDeviceReady(pDevIns, idCpu);
7100	}
7101
7102	/**
7103	* @copydoc PDMDEVHLPR3::pfnVMNotifyCpuDeviceReady
7104	*/
7105	DECLINLINE(int) PDMDevHlpVMNotifyCpuDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7106	{
7107	return pDevIns->CTX_SUFF(pHlp)->pfnVMNotifyCpuDeviceReady(pDevIns, idCpu);
7108	}
7109
7110	/**
7111	* Convenience wrapper for VMR3ReqCallU.
7112	*
7113	* This assumes (1) you're calling a function that returns an VBox status code
7114	* and that you do not wish to wait for it to complete.
7115	*
7116	* @returns VBox status code returned by VMR3ReqCallVU.
7117	*
7118	* @param pDevIns The device instance.
7119	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7120	* one of the following special values:
7121	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7122	* @param pfnFunction Pointer to the function to call.
7123	* @param cArgs Number of arguments following in the ellipsis.
7124	* @param ... Argument list.
7125	*
7126	* @remarks See remarks on VMR3ReqCallVU.
7127	*/
7128	DECLINLINE(int) PDMDevHlpVMReqCallNoWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7129	{
7130	va_list Args;
7131	va_start(Args, cArgs);
7132	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqCallNoWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7133	va_end(Args);
7134	return rc;
7135	}
7136
7137	/**
7138	* Convenience wrapper for VMR3ReqCallU.
7139	*
7140	* This assumes (1) you're calling a function that returns void, (2) that you
7141	* wish to wait for ever for it to return, and (3) that it's priority request
7142	* that can be safely be handled during async suspend and power off.
7143	*
7144	* @returns VBox status code of VMR3ReqCallVU.
7145	*
7146	* @param pDevIns The device instance.
7147	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7148	* one of the following special values:
7149	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7150	* @param pfnFunction Pointer to the function to call.
7151	* @param cArgs Number of arguments following in the ellipsis.
7152	* @param ... Argument list.
7153	*
7154	* @remarks See remarks on VMR3ReqCallVU.
7155	*/
7156	DECLINLINE(int) PDMDevHlpVMReqPriorityCallWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7157	{
7158	va_list Args;
7159	va_start(Args, cArgs);
7160	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqPriorityCallWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7161	va_end(Args);
7162	return rc;
7163	}
7164
7165	#endif /* IN_RING3 */
7166
7167	/**
7168	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
7169	*
7170	* @returns VBox status code which must be passed up to the VMM. This will be
7171	* VINF_SUCCESS in non-strict builds.
7172	* @param pDevIns The device instance.
7173	* @param SRC_POS Use RT_SRC_POS.
7174	* @param pszFormat Message. (optional)
7175	* @param ... Message parameters.
7176	*/
7177	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
7178	{
7179	#ifdef VBOX_STRICT
7180	# ifdef IN_RING3
7181	int rc;
7182	va_list args;
7183	va_start(args, pszFormat);
7184	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
7185	va_end(args);
7186	return rc;
7187	# else
7188	NOREF(pDevIns);
7189	NOREF(pszFile);
7190	NOREF(iLine);
7191	NOREF(pszFunction);
7192	NOREF(pszFormat);
7193	return VINF_EM_DBG_STOP;
7194	# endif
7195	#else
7196	NOREF(pDevIns);
7197	NOREF(pszFile);
7198	NOREF(iLine);
7199	NOREF(pszFunction);
7200	NOREF(pszFormat);
7201	return VINF_SUCCESS;
7202	#endif
7203	}
7204
7205	#ifdef IN_RING3
7206
7207	/**
7208	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
7209	*/
7210	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
7211	{
7212	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
7213	}
7214
7215	/**
7216	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
7217	*/
7218	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
7219	{
7220	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
7221	}
7222
7223	/**
7224	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
7225	*/
7226	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
7227	{
7228	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
7229	}
7230
7231	/**
7232	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
7233	*/
7234	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
7235	{
7236	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
7237	}
7238
7239	/**
7240	* Same as pfnSTAMRegister except that the name is specified in a
7241	* RTStrPrintf like fashion.
7242	*
7243	* @returns VBox status.
7244	* @param pDevIns Device instance of the DMA.
7245	* @param pvSample Pointer to the sample.
7246	* @param enmType Sample type. This indicates what pvSample is
7247	* pointing at.
7248	* @param enmVisibility Visibility type specifying whether unused
7249	* statistics should be visible or not.
7250	* @param enmUnit Sample unit.
7251	* @param pszDesc Sample description.
7252	* @param pszName Sample name format string, unix path style. If
7253	* this does not start with a '/', the default
7254	* prefix will be prepended, otherwise it will be
7255	* used as-is.
7256	* @param ... Arguments to the format string.
7257	*/
7258	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
7259	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
7260	const char pszDesc, const char pszName, ...)
7261	{
7262	va_list va;
7263	va_start(va, pszName);
7264	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
7265	va_end(va);
7266	}
7267
7268	/**
7269	* @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
7270	*/
7271	DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
7272	{
7273	return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
7274	}
7275
7276	/**
7277	* Registers the device with the default PCI bus.
7278	*
7279	* @returns VBox status code.
7280	* @param pDevIns The device instance.
7281	* @param pPciDev The PCI device structure.
7282	* This must be kept in the instance data.
7283	* The PCI configuration must be initialized before registration.
7284	*/
7285	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
7286	{
7287	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
7288	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
7289	}
7290
7291	/**
7292	* @copydoc PDMDEVHLPR3::pfnPCIRegister
7293	*/
7294	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
7295	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
7296	{
7297	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
7298	}
7299
7300	/**
7301	* Initialize MSI emulation support for the first PCI device.
7302	*
7303	* @returns VBox status code.
7304	* @param pDevIns The device instance.
7305	* @param pMsiReg MSI emulation registration structure.
7306	*/
7307	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
7308	{
7309	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
7310	}
7311
7312	/**
7313	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
7314	*/
7315	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
7316	{
7317	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
7318	}
7319
7320	/**
7321	* Registers a I/O port region for the default PCI device.
7322	*
7323	* @returns VBox status code.
7324	* @param pDevIns The device instance.
7325	* @param iRegion The region number.
7326	* @param cbRegion Size of the region.
7327	* @param hIoPorts Handle to the I/O port region.
7328	*/
7329	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
7330	{
7331	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7332	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
7333	}
7334
7335	/**
7336	* Registers a I/O port region for the default PCI device, custom map/unmap.
7337	*
7338	* @returns VBox status code.
7339	* @param pDevIns The device instance.
7340	* @param iRegion The region number.
7341	* @param cbRegion Size of the region.
7342	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7343	* callback will be invoked holding only the PDM lock.
7344	* The device lock will _not_ be taken (due to lock
7345	* order).
7346	*/
7347	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7348	PFNPCIIOREGIONMAP pfnMapUnmap)
7349	{
7350	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7351	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7352	UINT64_MAX, pfnMapUnmap);
7353	}
7354
7355	/**
7356	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7357	* and registering an I/O port region for the default PCI device.
7358	*
7359	* @returns VBox status code.
7360	* @param pDevIns The device instance to register the ports with.
7361	* @param cPorts The count of I/O ports in the region (the size).
7362	* @param iPciRegion The PCI device region.
7363	* @param pfnOut Pointer to function which is gonna handle OUT
7364	* operations. Optional.
7365	* @param pfnIn Pointer to function which is gonna handle IN operations.
7366	* Optional.
7367	* @param pvUser User argument to pass to the callbacks.
7368	* @param pszDesc Pointer to description string. This must not be freed.
7369	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7370	* coverage is allowed. This must not be freed.
7371	* @param phIoPorts Where to return the I/O port range handle.
7372	*
7373	*/
7374	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7375	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7376	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7377
7378	{
7379	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7380	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7381	if (RT_SUCCESS(rc))
7382	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7383	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7384	phIoPorts, NULL /pfnMapUnmap*/);
7385	return rc;
7386	}
7387
7388	/**
7389	* Registers an MMIO region for the default PCI device.
7390	*
7391	* @returns VBox status code.
7392	* @param pDevIns The device instance.
7393	* @param iRegion The region number.
7394	* @param cbRegion Size of the region.
7395	* @param enmType PCI_ADDRESS_SPACE_MEM or
7396	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7397	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7398	* @param hMmioRegion Handle to the MMIO region.
7399	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7400	* callback will be invoked holding only the PDM lock.
7401	* The device lock will _not_ be taken (due to lock
7402	* order).
7403	*/
7404	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7405	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7406	{
7407	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7408	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7409	hMmioRegion, pfnMapUnmap);
7410	}
7411
7412	/**
7413	* Registers an MMIO region for the default PCI device, extended version.
7414	*
7415	* @returns VBox status code.
7416	* @param pDevIns The device instance.
7417	* @param pPciDev The PCI device structure.
7418	* @param iRegion The region number.
7419	* @param cbRegion Size of the region.
7420	* @param enmType PCI_ADDRESS_SPACE_MEM or
7421	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7422	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7423	* @param hMmioRegion Handle to the MMIO region.
7424	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7425	* callback will be invoked holding only the PDM lock.
7426	* The device lock will _not_ be taken (due to lock
7427	* order).
7428	*/
7429	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7430	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7431	PFNPCIIOREGIONMAP pfnMapUnmap)
7432	{
7433	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7434	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7435	hMmioRegion, pfnMapUnmap);
7436	}
7437
7438	/**
7439	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7440	* and registering an MMIO region for the default PCI device.
7441	*
7442	* @returns VBox status code.
7443	* @param pDevIns The device instance to register the ports with.
7444	* @param cbRegion The size of the region in bytes.
7445	* @param iPciRegion The PCI device region.
7446	* @param enmType PCI_ADDRESS_SPACE_MEM or
7447	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7448	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7449	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7450	* @param pfnWrite Pointer to function which is gonna handle Write
7451	* operations.
7452	* @param pfnRead Pointer to function which is gonna handle Read
7453	* operations.
7454	* @param pvUser User argument to pass to the callbacks.
7455	* @param pszDesc Pointer to description string. This must not be freed.
7456	* @param phRegion Where to return the MMIO region handle.
7457	*
7458	*/
7459	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7460	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7461	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7462
7463	{
7464	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7465	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7466	if (RT_SUCCESS(rc))
7467	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7468	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7469	phRegion, NULL /pfnMapUnmap*/);
7470	return rc;
7471	}
7472
7473
7474	/**
7475	* Registers an MMIO2 region for the default PCI device.
7476	*
7477	* @returns VBox status code.
7478	* @param pDevIns The device instance.
7479	* @param iRegion The region number.
7480	* @param cbRegion Size of the region.
7481	* @param enmType PCI_ADDRESS_SPACE_MEM or
7482	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7483	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7484	* @param hMmio2Region Handle to the MMIO2 region.
7485	*/
7486	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7487	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7488	{
7489	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7490	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7491	hMmio2Region, NULL);
7492	}
7493
7494	/**
7495	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7496	* and registering an MMIO2 region for the default PCI device, extended edition.
7497	*
7498	* @returns VBox status code.
7499	* @param pDevIns The device instance to register the ports with.
7500	* @param cbRegion The size of the region in bytes.
7501	* @param iPciRegion The PCI device region.
7502	* @param enmType PCI_ADDRESS_SPACE_MEM or
7503	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7504	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7505	* @param pszDesc Pointer to description string. This must not be freed.
7506	* @param ppvMapping Where to store the address of the ring-3 mapping of
7507	* the memory.
7508	* @param phRegion Where to return the MMIO2 region handle.
7509	*
7510	*/
7511	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7512	PCIADDRESSSPACE enmType, const char *pszDesc,
7513	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7514
7515	{
7516	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7517	pszDesc, ppvMapping, phRegion);
7518	if (RT_SUCCESS(rc))
7519	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7520	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7521	phRegion, NULL /pfnCallback*/);
7522	return rc;
7523	}
7524
7525	/**
7526	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7527	* and registering an MMIO2 region for the default PCI device.
7528	*
7529	* @returns VBox status code.
7530	* @param pDevIns The device instance to register the ports with.
7531	* @param cbRegion The size of the region in bytes.
7532	* @param iPciRegion The PCI device region.
7533	* @param enmType PCI_ADDRESS_SPACE_MEM or
7534	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7535	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7536	* @param fMmio2Flags To be defined, must be zero.
7537	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7538	* callback will be invoked holding only the PDM lock.
7539	* The device lock will _not_ be taken (due to lock
7540	* order).
7541	* @param pszDesc Pointer to description string. This must not be freed.
7542	* @param ppvMapping Where to store the address of the ring-3 mapping of
7543	* the memory.
7544	* @param phRegion Where to return the MMIO2 region handle.
7545	*
7546	*/
7547	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7548	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7549	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
7550
7551	{
7552	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7553	pszDesc, ppvMapping, phRegion);
7554	if (RT_SUCCESS(rc))
7555	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7556	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7557	*phRegion, pfnMapUnmap);
7558	return rc;
7559	}
7560
7561	/**
7562	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7563	*/
7564	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7565	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7566	{
7567	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7568	}
7569
7570	/**
7571	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7572	*/
7573	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7574	unsigned cb, uint32_t *pu32Value)
7575	{
7576	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7577	}
7578
7579	/**
7580	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7581	*/
7582	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7583	unsigned cb, uint32_t u32Value)
7584	{
7585	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7586	}
7587
7588	#endif /* IN_RING3 */
7589
7590	/**
7591	* Bus master physical memory read from the default PCI device.
7592	*
7593	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7594	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7595	* @param pDevIns The device instance.
7596	* @param GCPhys Physical address start reading from.
7597	* @param pvBuf Where to put the read bits.
7598	* @param cbRead How many bytes to read.
7599	* @thread Any thread, but the call may involve the emulation thread.
7600	*/
7601	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7602	{
7603	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7604	}
7605
7606	/**
7607	* Bus master physical memory read - unknown data usage.
7608	*
7609	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7610	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7611	* @param pDevIns The device instance.
7612	* @param pPciDev The PCI device structure. If NULL the default
7613	* PCI device for this device instance is used.
7614	* @param GCPhys Physical address start reading from.
7615	* @param pvBuf Where to put the read bits.
7616	* @param cbRead How many bytes to read.
7617	* @thread Any thread, but the call may involve the emulation thread.
7618	*/
7619	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7620	{
7621	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7622	}
7623
7624	/**
7625	* Bus master physical memory read from the default PCI device.
7626	*
7627	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7628	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7629	* @param pDevIns The device instance.
7630	* @param GCPhys Physical address start reading from.
7631	* @param pvBuf Where to put the read bits.
7632	* @param cbRead How many bytes to read.
7633	* @thread Any thread, but the call may involve the emulation thread.
7634	*/
7635	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7636	{
7637	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7638	}
7639
7640	/**
7641	* Bus master physical memory read - reads meta data processed by the device.
7642	*
7643	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7644	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7645	* @param pDevIns The device instance.
7646	* @param pPciDev The PCI device structure. If NULL the default
7647	* PCI device for this device instance is used.
7648	* @param GCPhys Physical address start reading from.
7649	* @param pvBuf Where to put the read bits.
7650	* @param cbRead How many bytes to read.
7651	* @thread Any thread, but the call may involve the emulation thread.
7652	*/
7653	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7654	{
7655	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7656	}
7657
7658	/**
7659	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
7660	*
7661	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7662	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7663	* @param pDevIns The device instance.
7664	* @param GCPhys Physical address start reading from.
7665	* @param pvBuf Where to put the read bits.
7666	* @param cbRead How many bytes to read.
7667	* @thread Any thread, but the call may involve the emulation thread.
7668	*/
7669	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7670	{
7671	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7672	}
7673
7674	/**
7675	* Bus master physical memory read - read data will not be touched by the device.
7676	*
7677	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7678	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7679	* @param pDevIns The device instance.
7680	* @param pPciDev The PCI device structure. If NULL the default
7681	* PCI device for this device instance is used.
7682	* @param GCPhys Physical address start reading from.
7683	* @param pvBuf Where to put the read bits.
7684	* @param cbRead How many bytes to read.
7685	* @thread Any thread, but the call may involve the emulation thread.
7686	*/
7687	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7688	{
7689	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7690	}
7691
7692	/**
7693	* Bus master physical memory write from the default PCI device - unknown data usage.
7694	*
7695	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7696	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7697	* @param pDevIns The device instance.
7698	* @param GCPhys Physical address to write to.
7699	* @param pvBuf What to write.
7700	* @param cbWrite How many bytes to write.
7701	* @thread Any thread, but the call may involve the emulation thread.
7702	*/
7703	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7704	{
7705	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7706	}
7707
7708	/**
7709	* Bus master physical memory write - unknown data usage.
7710	*
7711	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7712	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7713	* @param pDevIns The device instance.
7714	* @param pPciDev The PCI device structure. If NULL the default
7715	* PCI device for this device instance is used.
7716	* @param GCPhys Physical address to write to.
7717	* @param pvBuf What to write.
7718	* @param cbWrite How many bytes to write.
7719	* @thread Any thread, but the call may involve the emulation thread.
7720	*/
7721	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7722	{
7723	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7724	}
7725
7726	/**
7727	* Bus master physical memory write from the default PCI device.
7728	*
7729	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7730	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7731	* @param pDevIns The device instance.
7732	* @param GCPhys Physical address to write to.
7733	* @param pvBuf What to write.
7734	* @param cbWrite How many bytes to write.
7735	* @thread Any thread, but the call may involve the emulation thread.
7736	*/
7737	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7738	{
7739	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7740	}
7741
7742	/**
7743	* Bus master physical memory write - written data was created/altered by the device.
7744	*
7745	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7746	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7747	* @param pDevIns The device instance.
7748	* @param pPciDev The PCI device structure. If NULL the default
7749	* PCI device for this device instance is used.
7750	* @param GCPhys Physical address to write to.
7751	* @param pvBuf What to write.
7752	* @param cbWrite How many bytes to write.
7753	* @thread Any thread, but the call may involve the emulation thread.
7754	*/
7755	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7756	{
7757	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7758	}
7759
7760	/**
7761	* Bus master physical memory write from the default PCI device.
7762	*
7763	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7764	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7765	* @param pDevIns The device instance.
7766	* @param GCPhys Physical address to write to.
7767	* @param pvBuf What to write.
7768	* @param cbWrite How many bytes to write.
7769	* @thread Any thread, but the call may involve the emulation thread.
7770	*/
7771	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7772	{
7773	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7774	}
7775
7776	/**
7777	* Bus master physical memory write - written data was not touched/created by the device.
7778	*
7779	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7780	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7781	* @param pDevIns The device instance.
7782	* @param pPciDev The PCI device structure. If NULL the default
7783	* PCI device for this device instance is used.
7784	* @param GCPhys Physical address to write to.
7785	* @param pvBuf What to write.
7786	* @param cbWrite How many bytes to write.
7787	* @thread Any thread, but the call may involve the emulation thread.
7788	*/
7789	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7790	{
7791	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7792	}
7793
7794	#ifdef IN_RING3
7795	/**
7796	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
7797	*/
7798	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7799	void **ppv, PPGMPAGEMAPLOCK pLock)
7800	{
7801	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7802	}
7803
7804	/**
7805	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
7806	*/
7807	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7808	void const **ppv, PPGMPAGEMAPLOCK pLock)
7809	{
7810	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7811	}
7812
7813	/**
7814	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
7815	*/
7816	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7817	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
7818	PPGMPAGEMAPLOCK paLocks)
7819	{
7820	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
7821	paLocks);
7822	}
7823
7824	/**
7825	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
7826	*/
7827	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7828	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
7829	PPGMPAGEMAPLOCK paLocks)
7830	{
7831	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
7832	papvPages, paLocks);
7833	}
7834	#endif /* IN_RING3 */
7835
7836	/**
7837	* Sets the IRQ for the default PCI device.
7838	*
7839	* @param pDevIns The device instance.
7840	* @param iIrq IRQ number to set.
7841	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7842	* @thread Any thread, but will involve the emulation thread.
7843	*/
7844	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7845	{
7846	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7847	}
7848
7849	/**
7850	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
7851	*/
7852	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7853	{
7854	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7855	}
7856
7857	/**
7858	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7859	* the request when not called from EMT.
7860	*
7861	* @param pDevIns The device instance.
7862	* @param iIrq IRQ number to set.
7863	* @param iLevel IRQ level.
7864	* @thread Any thread, but will involve the emulation thread.
7865	*/
7866	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7867	{
7868	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7869	}
7870
7871	/**
7872	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7873	*/
7874	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7875	{
7876	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7877	}
7878
7879	/**
7880	* @copydoc PDMDEVHLPR3::pfnISASetIrq
7881	*/
7882	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7883	{
7884	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7885	}
7886
7887	/**
7888	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7889	*/
7890	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7891	{
7892	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7893	}
7894
7895	#ifdef IN_RING3
7896
7897	/**
7898	* @copydoc PDMDEVHLPR3::pfnDriverAttach
7899	*/
7900	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
7901	{
7902	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7903	}
7904
7905	/**
7906	* @copydoc PDMDEVHLPR3::pfnDriverDetach
7907	*/
7908	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7909	{
7910	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7911	}
7912
7913	/**
7914	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
7915	*/
7916	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
7917	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
7918	{
7919	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
7920	}
7921
7922	/**
7923	* Reconfigures with a single driver reattachement, no config, noflags.
7924	* @sa PDMDevHlpDriverReconfigure
7925	*/
7926	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
7927	{
7928	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
7929	}
7930
7931	/**
7932	* Reconfigures with a two drivers reattachement, no config, noflags.
7933	* @sa PDMDevHlpDriverReconfigure
7934	*/
7935	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
7936	{
7937	char const * apszDrivers[2];
7938	apszDrivers[0] = pszDriver0;
7939	apszDrivers[1] = pszDriver1;
7940	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
7941	}
7942
7943	/**
7944	* @copydoc PDMDEVHLPR3::pfnQueueCreate
7945	*/
7946	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7947	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
7948	{
7949	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7950	}
7951
7952	#endif /* IN_RING3 */
7953
7954	/**
7955	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
7956	*/
7957	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7958	{
7959	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7960	}
7961
7962	/**
7963	* @copydoc PDMDEVHLPR3::pfnQueueInsert
7964	*/
7965	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7966	{
7967	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7968	}
7969
7970	/**
7971	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7972	*/
7973	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7974	{
7975	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7976	}
7977
7978	#ifdef IN_RING3
7979	/**
7980	* @copydoc PDMDEVHLPR3::pfnTaskCreate
7981	*/
7982	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7983	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
7984	{
7985	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7986	}
7987	#endif
7988
7989	/**
7990	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
7991	*/
7992	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7993	{
7994	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7995	}
7996
7997	#ifdef IN_RING3
7998
7999	/**
8000	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
8001	*/
8002	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
8003	{
8004	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
8005	}
8006
8007	/**
8008	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
8009	*/
8010	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8011	{
8012	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
8013	}
8014
8015	#endif /* IN_RING3 */
8016
8017	/**
8018	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
8019	*/
8020	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8021	{
8022	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
8023	}
8024
8025	/**
8026	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
8027	*/
8028	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
8029	{
8030	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
8031	}
8032
8033	/**
8034	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
8035	*/
8036	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
8037	{
8038	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
8039	}
8040
8041	/**
8042	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
8043	*/
8044	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
8045	{
8046	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
8047	}
8048
8049	/**
8050	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
8051	*/
8052	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
8053	{
8054	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
8055	}
8056
8057	#ifdef IN_RING3
8058
8059	/**
8060	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
8061	*/
8062	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
8063	{
8064	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
8065	}
8066
8067	/**
8068	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
8069	*/
8070	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8071	{
8072	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
8073	}
8074
8075	#endif /* IN_RING3 */
8076
8077	/**
8078	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
8079	*/
8080	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8081	{
8082	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
8083	}
8084
8085	/**
8086	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
8087	*/
8088	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8089	{
8090	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
8091	}
8092
8093	/**
8094	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
8095	*/
8096	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
8097	{
8098	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
8099	}
8100
8101	/**
8102	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
8103	*/
8104	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
8105	{
8106	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
8107	}
8108
8109	/**
8110	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
8111	*/
8112	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
8113	{
8114	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
8115	}
8116
8117	/**
8118	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
8119	*/
8120	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
8121	{
8122	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
8123	}
8124
8125	#ifdef IN_RING3
8126
8127	/**
8128	* Initializes a PDM critical section.
8129	*
8130	* The PDM critical sections are derived from the IPRT critical sections, but
8131	* works in RC and R0 as well.
8132	*
8133	* @returns VBox status code.
8134	* @param pDevIns The device instance.
8135	* @param pCritSect Pointer to the critical section.
8136	* @param SRC_POS Use RT_SRC_POS.
8137	* @param pszNameFmt Format string for naming the critical section.
8138	* For statistics and lock validation.
8139	* @param ... Arguments for the format string.
8140	*/
8141	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
8142	const char *pszNameFmt, ...)
8143	{
8144	int rc;
8145	va_list va;
8146	va_start(va, pszNameFmt);
8147	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8148	va_end(va);
8149	return rc;
8150	}
8151
8152	#endif /* IN_RING3 */
8153
8154	/**
8155	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
8156	*/
8157	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
8158	{
8159	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
8160	}
8161
8162	/**
8163	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
8164	*/
8165	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8166	{
8167	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
8168	}
8169
8170	/**
8171	* Enters a PDM critical section.
8172	*
8173	* @returns VINF_SUCCESS if entered successfully.
8174	* @returns rcBusy when encountering a busy critical section in RC/R0.
8175	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8176	* during the operation.
8177	*
8178	* @param pDevIns The device instance.
8179	* @param pCritSect The PDM critical section to enter.
8180	* @param rcBusy The status code to return when we're in RC or R0
8181	* and the section is busy. Pass VINF_SUCCESS to
8182	* acquired the critical section thru a ring-3
8183	* call if necessary.
8184	*
8185	* @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
8186	* possible failures in ring-0 or at least apply
8187	* PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
8188	* function.
8189	*
8190	* @sa PDMCritSectEnter
8191	*/
8192	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
8193	{
8194	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
8195	}
8196
8197	/**
8198	* Enters a PDM critical section, with location information for debugging.
8199	*
8200	* @returns VINF_SUCCESS if entered successfully.
8201	* @returns rcBusy when encountering a busy critical section in RC/R0.
8202	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8203	* during the operation.
8204	*
8205	* @param pDevIns The device instance.
8206	* @param pCritSect The PDM critical section to enter.
8207	* @param rcBusy The status code to return when we're in RC or R0
8208	* and the section is busy. Pass VINF_SUCCESS to
8209	* acquired the critical section thru a ring-3
8210	* call if necessary.
8211	* @param uId Some kind of locking location ID. Typically a
8212	* return address up the stack. Optional (0).
8213	* @param SRC_POS The source position where to lock is being
8214	* acquired from. Optional.
8215	* @sa PDMCritSectEnterDebug
8216	*/
8217	DECLINLINE(DECL_CHECK_RETURN(int))
8218	PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8219	{
8220	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8221	}
8222
8223	/**
8224	* Try enter a critical section.
8225	*
8226	* @retval VINF_SUCCESS on success.
8227	* @retval VERR_SEM_BUSY if the critsect was owned.
8228	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8229	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8230	* during the operation.
8231	*
8232	* @param pDevIns The device instance.
8233	* @param pCritSect The critical section.
8234	* @sa PDMCritSectTryEnter
8235	*/
8236	DECLINLINE(DECL_CHECK_RETURN(int))
8237	PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8238	{
8239	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
8240	}
8241
8242	/**
8243	* Try enter a critical section, with location information for debugging.
8244	*
8245	* @retval VINF_SUCCESS on success.
8246	* @retval VERR_SEM_BUSY if the critsect was owned.
8247	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8248	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8249	* during the operation.
8250	*
8251	* @param pDevIns The device instance.
8252	* @param pCritSect The critical section.
8253	* @param uId Some kind of locking location ID. Typically a
8254	* return address up the stack. Optional (0).
8255	* @param SRC_POS The source position where to lock is being
8256	* acquired from. Optional.
8257	* @sa PDMCritSectTryEnterDebug
8258	*/
8259	DECLINLINE(DECL_CHECK_RETURN(int))
8260	PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8261	{
8262	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8263	}
8264
8265	/**
8266	* Leaves a critical section entered with PDMCritSectEnter().
8267	*
8268	* @returns Indication whether we really exited the critical section.
8269	* @retval VINF_SUCCESS if we really exited.
8270	* @retval VINF_SEM_NESTED if we only reduced the nesting count.
8271	* @retval VERR_NOT_OWNER if you somehow ignore release assertions.
8272	*
8273	* @param pDevIns The device instance.
8274	* @param pCritSect The PDM critical section to leave.
8275	* @sa PDMCritSectLeave
8276	*/
8277	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8278	{
8279	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
8280	}
8281
8282	/**
8283	* @see PDMCritSectIsOwner
8284	*/
8285	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8286	{
8287	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
8288	}
8289
8290	/**
8291	* @see PDMCritSectIsInitialized
8292	*/
8293	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8294	{
8295	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
8296	}
8297
8298	/**
8299	* @see PDMCritSectHasWaiters
8300	*/
8301	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8302	{
8303	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
8304	}
8305
8306	/**
8307	* @see PDMCritSectGetRecursion
8308	*/
8309	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8310	{
8311	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
8312	}
8313
8314	#if defined(IN_RING3) \|\| defined(IN_RING0)
8315	/**
8316	* @see PDMHCCritSectScheduleExitEvent
8317	*/
8318	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
8319	{
8320	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
8321	}
8322	#endif
8323
8324	/* Strict build: Remap the two enter calls to the debug versions. */
8325	#ifdef VBOX_STRICT
8326	# ifdef IPRT_INCLUDED_asm_h
8327	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8328	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8329	# else
8330	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8331	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8332	# endif
8333	#endif
8334
8335	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8336
8337	/**
8338	* Deletes the critical section.
8339	*
8340	* @returns VBox status code.
8341	* @param pDevIns The device instance.
8342	* @param pCritSect The PDM critical section to destroy.
8343	* @sa PDMR3CritSectDelete
8344	*/
8345	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8346	{
8347	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8348	}
8349
8350	/**
8351	* Initializes a PDM read/write critical section.
8352	*
8353	* The PDM read/write critical sections are derived from the IPRT critical
8354	* sections, but works in RC and R0 as well.
8355	*
8356	* @returns VBox status code.
8357	* @param pDevIns The device instance.
8358	* @param pCritSect Pointer to the read/write critical section.
8359	* @param SRC_POS Use RT_SRC_POS.
8360	* @param pszNameFmt Format string for naming the critical section.
8361	* For statistics and lock validation.
8362	* @param ... Arguments for the format string.
8363	*/
8364	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
8365	const char *pszNameFmt, ...)
8366	{
8367	int rc;
8368	va_list va;
8369	va_start(va, pszNameFmt);
8370	rc = pDevIns->pHlpR3->pfnCritSectRwInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8371	va_end(va);
8372	return rc;
8373	}
8374
8375	/**
8376	* Deletes the read/write critical section.
8377	*
8378	* @returns VBox status code.
8379	* @param pDevIns The device instance.
8380	* @param pCritSect The PDM read/write critical section to destroy.
8381	* @sa PDMR3CritSectRwDelete
8382	*/
8383	DECLINLINE(int) PDMDevHlpCritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8384	{
8385	return pDevIns->pHlpR3->pfnCritSectRwDelete(pDevIns, pCritSect);
8386	}
8387
8388	#endif /* IN_RING3 */
8389
8390	/**
8391	* @sa PDMCritSectRwEnterShared, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8392	*/
8393	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8394	{
8395	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterShared(pDevIns, pCritSect, rcBusy);
8396	}
8397
8398	/**
8399	* @sa PDMCritSectRwEnterSharedDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8400	*/
8401	DECLINLINE(DECL_CHECK_RETURN(int))
8402	PDMDevHlpCritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8403	{
8404	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterSharedDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8405	}
8406
8407	/**
8408	* @sa PDMCritSectRwTryEnterShared
8409	*/
8410	DECLINLINE(DECL_CHECK_RETURN(int))
8411	PDMDevHlpCritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8412	{
8413	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterShared(pDevIns, pCritSect);
8414	}
8415
8416	/**
8417	* @sa PDMCritSectRwTryEnterSharedDebug
8418	*/
8419	DECLINLINE(DECL_CHECK_RETURN(int))
8420	PDMDevHlpCritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8421	{
8422	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterSharedDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8423	}
8424
8425	/**
8426	* @sa PDMCritSectRwLeaveShared
8427	*/
8428	DECLINLINE(int) PDMDevHlpCritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8429	{
8430	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveShared(pDevIns, pCritSect);
8431	}
8432
8433	/**
8434	* @sa PDMCritSectRwEnterExcl, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8435	*/
8436	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8437	{
8438	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy);
8439	}
8440
8441	/**
8442	* @sa PDMCritSectRwEnterExclDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8443	*/
8444	DECLINLINE(DECL_CHECK_RETURN(int))
8445	PDMDevHlpCritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8446	{
8447	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExclDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8448	}
8449
8450	/**
8451	* @sa PDMCritSectRwTryEnterExcl
8452	*/
8453	DECLINLINE(DECL_CHECK_RETURN(int))
8454	PDMDevHlpCritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8455	{
8456	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExcl(pDevIns, pCritSect);
8457	}
8458
8459	/**
8460	* @sa PDMCritSectRwTryEnterExclDebug
8461	*/
8462	DECLINLINE(DECL_CHECK_RETURN(int))
8463	PDMDevHlpCritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8464	{
8465	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExclDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8466	}
8467
8468	/**
8469	* @sa PDMCritSectRwLeaveExcl
8470	*/
8471	DECLINLINE(int) PDMDevHlpCritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8472	{
8473	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveExcl(pDevIns, pCritSect);
8474	}
8475
8476	/**
8477	* @see PDMCritSectRwIsWriteOwner
8478	*/
8479	DECLINLINE(bool) PDMDevHlpCritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8480	{
8481	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsWriteOwner(pDevIns, pCritSect);
8482	}
8483
8484	/**
8485	* @see PDMCritSectRwIsReadOwner
8486	*/
8487	DECLINLINE(bool) PDMDevHlpCritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
8488	{
8489	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsReadOwner(pDevIns, pCritSect, fWannaHear);
8490	}
8491
8492	/**
8493	* @see PDMCritSectRwGetWriteRecursion
8494	*/
8495	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8496	{
8497	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriteRecursion(pDevIns, pCritSect);
8498	}
8499
8500	/**
8501	* @see PDMCritSectRwGetWriterReadRecursion
8502	*/
8503	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8504	{
8505	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriterReadRecursion(pDevIns, pCritSect);
8506	}
8507
8508	/**
8509	* @see PDMCritSectRwGetReadCount
8510	*/
8511	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8512	{
8513	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetReadCount(pDevIns, pCritSect);
8514	}
8515
8516	/**
8517	* @see PDMCritSectRwIsInitialized
8518	*/
8519	DECLINLINE(bool) PDMDevHlpCritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8520	{
8521	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsInitialized(pDevIns, pCritSect);
8522	}
8523
8524	/* Strict build: Remap the two enter calls to the debug versions. */
8525	#ifdef VBOX_STRICT
8526	# ifdef IPRT_INCLUDED_asm_h
8527	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8528	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8529	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8530	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8531	# else
8532	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8533	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8534	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8535	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8536	# endif
8537	#endif
8538
8539	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8540
8541	/**
8542	* @copydoc PDMDEVHLPR3::pfnThreadCreate
8543	*/
8544	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
8545	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
8546	{
8547	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
8548	}
8549
8550	/**
8551	* @copydoc PDMR3ThreadDestroy
8552	* @param pDevIns The device instance.
8553	*/
8554	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
8555	{
8556	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
8557	}
8558
8559	/**
8560	* @copydoc PDMR3ThreadIAmSuspending
8561	* @param pDevIns The device instance.
8562	*/
8563	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8564	{
8565	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
8566	}
8567
8568	/**
8569	* @copydoc PDMR3ThreadIAmRunning
8570	* @param pDevIns The device instance.
8571	*/
8572	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8573	{
8574	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
8575	}
8576
8577	/**
8578	* @copydoc PDMR3ThreadSleep
8579	* @param pDevIns The device instance.
8580	*/
8581	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
8582	{
8583	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
8584	}
8585
8586	/**
8587	* @copydoc PDMR3ThreadSuspend
8588	* @param pDevIns The device instance.
8589	*/
8590	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8591	{
8592	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
8593	}
8594
8595	/**
8596	* @copydoc PDMR3ThreadResume
8597	* @param pDevIns The device instance.
8598	*/
8599	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8600	{
8601	return pDevIns->pHlpR3->pfnThreadResume(pThread);
8602	}
8603
8604	/**
8605	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
8606	*/
8607	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
8608	{
8609	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
8610	}
8611
8612	/**
8613	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
8614	*/
8615	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
8616	{
8617	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
8618	}
8619
8620	/**
8621	* @copydoc PDMDEVHLPR3::pfnA20Set
8622	*/
8623	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
8624	{
8625	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
8626	}
8627
8628	/**
8629	* @copydoc PDMDEVHLPR3::pfnRTCRegister
8630	*/
8631	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
8632	{
8633	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
8634	}
8635
8636	/**
8637	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
8638	*/
8639	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
8640	{
8641	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
8642	}
8643
8644	/**
8645	* @copydoc PDMDEVHLPR3::pfnIommuRegister
8646	*/
8647	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
8648	{
8649	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
8650	}
8651
8652	/**
8653	* @copydoc PDMDEVHLPR3::pfnPICRegister
8654	*/
8655	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8656	{
8657	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
8658	}
8659
8660	/**
8661	* @copydoc PDMDEVHLPR3::pfnApicRegister
8662	*/
8663	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
8664	{
8665	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
8666	}
8667
8668	/**
8669	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
8670	*/
8671	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8672	{
8673	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
8674	}
8675
8676	/**
8677	* @copydoc PDMDEVHLPR3::pfnHpetRegister
8678	*/
8679	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
8680	{
8681	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
8682	}
8683
8684	/**
8685	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
8686	*/
8687	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
8688	{
8689	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
8690	}
8691
8692	/**
8693	* @copydoc PDMDEVHLPR3::pfnDMACRegister
8694	*/
8695	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
8696	{
8697	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
8698	}
8699
8700	/**
8701	* @copydoc PDMDEVHLPR3::pfnDMARegister
8702	*/
8703	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
8704	{
8705	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
8706	}
8707
8708	/**
8709	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
8710	*/
8711	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
8712	{
8713	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
8714	}
8715
8716	/**
8717	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
8718	*/
8719	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
8720	{
8721	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
8722	}
8723
8724	/**
8725	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
8726	*/
8727	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
8728	{
8729	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
8730	}
8731
8732	/**
8733	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
8734	*/
8735	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
8736	{
8737	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
8738	}
8739
8740	/**
8741	* @copydoc PDMDEVHLPR3::pfnDMASchedule
8742	*/
8743	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
8744	{
8745	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
8746	}
8747
8748	/**
8749	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
8750	*/
8751	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
8752	{
8753	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
8754	}
8755
8756	/**
8757	* @copydoc PDMDEVHLPR3::pfnCMOSRead
8758	*/
8759	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
8760	{
8761	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
8762	}
8763
8764	/**
8765	* @copydoc PDMDEVHLPR3::pfnCallR0
8766	*/
8767	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
8768	{
8769	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
8770	}
8771
8772	/**
8773	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
8774	*/
8775	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
8776	{
8777	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
8778	}
8779
8780	/**
8781	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
8782	*/
8783	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
8784	{
8785	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
8786	}
8787
8788	/**
8789	* @copydoc PDMDEVHLPR3::pfnGetUVM
8790	*/
8791	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
8792	{
8793	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
8794	}
8795
8796	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
8797
8798	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8799
8800	/**
8801	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
8802	*/
8803	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
8804	{
8805	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
8806	}
8807
8808	/**
8809	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
8810	*/
8811	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
8812	{
8813	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
8814	}
8815
8816	/**
8817	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
8818	*/
8819	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8820	{
8821	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
8822	}
8823
8824	/**
8825	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
8826	*/
8827	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
8828	{
8829	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
8830	}
8831
8832	/**
8833	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
8834	*/
8835	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8836	{
8837	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
8838	}
8839
8840	/**
8841	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
8842	*/
8843	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
8844	{
8845	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
8846	}
8847
8848	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
8849
8850	/**
8851	* @copydoc PDMDEVHLPR3::pfnGetVM
8852	*/
8853	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
8854	{
8855	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
8856	}
8857
8858	/**
8859	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
8860	*/
8861	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
8862	{
8863	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
8864	}
8865
8866	/**
8867	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
8868	*/
8869	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
8870	{
8871	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
8872	}
8873
8874	/**
8875	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
8876	*/
8877	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
8878	{
8879	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
8880	}
8881
8882	/**
8883	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8884	*/
8885	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8886	{
8887	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8888	}
8889
8890	/**
8891	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8892	*/
8893	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8894	{
8895	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8896	}
8897
8898	#ifdef IN_RING3
8899
8900	/**
8901	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8902	*/
8903	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8904	{
8905	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
8906	}
8907
8908	/**
8909	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
8910	*/
8911	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
8912	{
8913	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
8914	}
8915
8916	/**
8917	* @copydoc PDMDEVHLPR3::pfnVMReset
8918	*/
8919	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
8920	{
8921	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
8922	}
8923
8924	/**
8925	* @copydoc PDMDEVHLPR3::pfnVMSuspend
8926	*/
8927	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8928	{
8929	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8930	}
8931
8932	/**
8933	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8934	*/
8935	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8936	{
8937	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8938	}
8939
8940	/**
8941	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
8942	*/
8943	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8944	{
8945	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8946	}
8947
8948	#endif /* IN_RING3 */
8949
8950	/**
8951	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8952	*/
8953	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8954	{
8955	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8956	}
8957
8958	#ifdef IN_RING3
8959
8960	/**
8961	* @copydoc PDMDEVHLPR3::pfnGetCpuId
8962	*/
8963	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
8964	{
8965	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8966	}
8967
8968	/**
8969	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8970	*/
8971	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8972	{
8973	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8974	}
8975
8976	/**
8977	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8978	*/
8979	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8980	{
8981	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8982	}
8983
8984	/**
8985	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
8986	*/
8987	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
8988	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
8989	const char pszHandlerR0, const char pszPfHandlerR0,
8990	const char pszHandlerRC, const char pszPfHandlerRC,
8991	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
8992	{
8993	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
8994	pszHandlerR0, pszPfHandlerR0,
8995	pszHandlerRC, pszPfHandlerRC,
8996	pszDesc, phType);
8997	}
8998
8999	/**
9000	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalRegister
9001	*/
9002	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
9003	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
9004	RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc)
9005	{
9006	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalRegister(pDevIns, GCPhys, GCPhysLast, hType,
9007	pvUserR3, pvUserR0, pvUserRC, pszDesc);
9008	}
9009
9010	/**
9011	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalDeregister
9012	*/
9013	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalDeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9014	{
9015	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalDeregister(pDevIns, GCPhys);
9016	}
9017	#endif
9018
9019	/**
9020	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalPageTempOff
9021	*/
9022	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
9023	{
9024	return pDevIns->CTX_SUFF(pHlp)->pfnPGMHandlerPhysicalPageTempOff(pDevIns, GCPhys, GCPhysPage);
9025	}
9026
9027	#ifdef IN_RING3
9028	/**
9029	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalReset
9030	*/
9031	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalReset(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9032	{
9033	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalReset(pDevIns, GCPhys);
9034	}
9035
9036	/**
9037	* @copydoc PDMDEVHLPR3::pfnVMMRegisterPatchMemory
9038	*/
9039	DECLINLINE(int) PDMDevHlpVMMRegisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9040	{
9041	return pDevIns->pHlpR3->pfnVMMRegisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9042	}
9043
9044	/**
9045	* @copydoc PDMDEVHLPR3::pfnVMMDeregisterPatchMemory
9046	*/
9047	DECLINLINE(int) PDMDevHlpVMMDeregisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9048	{
9049	return pDevIns->pHlpR3->pfnVMMDeregisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9050	}
9051
9052	/**
9053	* @copydoc PDMDEVHLPR3::pfnSharedModuleRegister
9054	*/
9055	DECLINLINE(int) PDMDevHlpSharedModuleRegister(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
9056	RTGCPTR GCBaseAddr, uint32_t cbModule,
9057	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions)
9058	{
9059	return pDevIns->pHlpR3->pfnSharedModuleRegister(pDevIns, enmGuestOS, pszModuleName, pszVersion,
9060	GCBaseAddr, cbModule, cRegions, paRegions);
9061	}
9062
9063	/**
9064	* @copydoc PDMDEVHLPR3::pfnSharedModuleUnregister
9065	*/
9066	DECLINLINE(int) PDMDevHlpSharedModuleUnregister(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
9067	RTGCPTR GCBaseAddr, uint32_t cbModule)
9068	{
9069	return pDevIns->pHlpR3->pfnSharedModuleUnregister(pDevIns, pszModuleName, pszVersion, GCBaseAddr, cbModule);
9070	}
9071
9072	/**
9073	* @copydoc PDMDEVHLPR3::pfnSharedModuleGetPageState
9074	*/
9075	DECLINLINE(int) PDMDevHlpSharedModuleGetPageState(PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool *pfShared,
9076	uint64_t *pfPageFlags)
9077	{
9078	return pDevIns->pHlpR3->pfnSharedModuleGetPageState(pDevIns, GCPtrPage, pfShared, pfPageFlags);
9079	}
9080
9081	/**
9082	* @copydoc PDMDEVHLPR3::pfnSharedModuleCheckAll
9083	*/
9084	DECLINLINE(int) PDMDevHlpSharedModuleCheckAll(PPDMDEVINS pDevIns)
9085	{
9086	return pDevIns->pHlpR3->pfnSharedModuleCheckAll(pDevIns);
9087	}
9088
9089	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
9090	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9091	do { \
9092	uint32_t u32GetEnumTmp = 0; \
9093	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
9094	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9095	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
9096	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
9097	} while (0)
9098
9099	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
9100	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9101	do { \
9102	uint8_t bGetEnumTmp = 0; \
9103	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
9104	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9105	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
9106	} while (0)
9107
9108	#endif /* IN_RING3 */
9109
9110	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
9111	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
9112
9113	/**
9114	* Callbacks for VBoxDeviceRegister().
9115	*/
9116	typedef struct PDMDEVREGCB
9117	{
9118	/** Interface version.
9119	* This is set to PDM_DEVREG_CB_VERSION. */
9120	uint32_t u32Version;
9121
9122	/**
9123	* Registers a device with the current VM instance.
9124	*
9125	* @returns VBox status code.
9126	* @param pCallbacks Pointer to the callback table.
9127	* @param pReg Pointer to the device registration record.
9128	* This data must be permanent and readonly.
9129	*/
9130	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
9131	} PDMDEVREGCB;
9132
9133	/** Current version of the PDMDEVREGCB structure. */
9134	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
9135
9136
9137	/**
9138	* The VBoxDevicesRegister callback function.
9139	*
9140	* PDM will invoke this function after loading a device module and letting
9141	* the module decide which devices to register and how to handle conflicts.
9142	*
9143	* @returns VBox status code.
9144	* @param pCallbacks Pointer to the callback table.
9145	* @param u32Version VBox version number.
9146	*/
9147	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
9148
9149	/** @} */
9150
9151	RT_C_DECLS_END
9152
9153	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 91928

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