pdmdev.h@ 91930

Last change on this file since 91930 was 91930, checked in by vboxsync, 3 years ago
VMM,Devices: Eliminate direct calls to IOMMmioResetRegion and IOMMmioMapMmio2Page APIs and introduce callbacks in the device helper callback table, bugref:10074
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 388.1 KB

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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmcritsectrw.h>
34	#include <VBox/vmm/pdmqueue.h>
35	#include <VBox/vmm/pdmtask.h>
36	#ifdef IN_RING3
37	# include <VBox/vmm/pdmthread.h>
38	#endif
39	#include <VBox/vmm/pdmifs.h>
40	#include <VBox/vmm/pdmins.h>
41	#include <VBox/vmm/pdmcommon.h>
42	#include <VBox/vmm/pdmpcidev.h>
43	#include <VBox/vmm/iom.h>
44	#include <VBox/vmm/mm.h>
45	#include <VBox/vmm/tm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/cfgm.h>
48	#include <VBox/vmm/cpum.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
51	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
52	#include <VBox/msi.h>
53	#include <iprt/stdarg.h>
54	#include <iprt/list.h>
55
56
57	RT_C_DECLS_BEGIN
58
59	/** @defgroup grp_pdm_device The PDM Devices API
60	* @ingroup grp_pdm
61	* @{
62	*/
63
64	/**
65	* Construct a device instance for a VM.
66	*
67	* @returns VBox status.
68	* @param pDevIns The device instance data. If the registration structure
69	* is needed, it can be accessed thru pDevIns->pReg.
70	* @param iInstance Instance number. Use this to figure out which registers
71	* and such to use. The instance number is also found in
72	* pDevIns->iInstance, but since it's likely to be
73	* frequently used PDM passes it as parameter.
74	* @param pCfg Configuration node handle for the driver. This is
75	* expected to be in high demand in the constructor and is
76	* therefore passed as an argument. When using it at other
77	* times, it can be found in pDevIns->pCfg.
78	*/
79	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
80	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
81	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
82
83	/**
84	* Destruct a device instance.
85	*
86	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
87	* resources can be freed correctly.
88	*
89	* @returns VBox status.
90	* @param pDevIns The device instance data.
91	*
92	* @remarks The device critical section is not entered. The routine may delete
93	* the critical section, so the caller cannot exit it.
94	*/
95	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
96	/** Pointer to a FNPDMDEVDESTRUCT() function. */
97	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
98
99	/**
100	* Device relocation callback.
101	*
102	* This is called when the instance data has been relocated in raw-mode context
103	* (RC). It is also called when the RC hypervisor selects changes. The device
104	* must fixup all necessary pointers and re-query all interfaces to other RC
105	* devices and drivers.
106	*
107	* Before the RC code is executed the first time, this function will be called
108	* with a 0 delta so RC pointer calculations can be one in one place.
109	*
110	* @param pDevIns Pointer to the device instance.
111	* @param offDelta The relocation delta relative to the old location.
112	*
113	* @remarks A relocation CANNOT fail.
114	*
115	* @remarks The device critical section is not entered. The relocations should
116	* not normally require any locking.
117	*/
118	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
119	/** Pointer to a FNPDMDEVRELOCATE() function. */
120	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
121
122	/**
123	* Power On notification.
124	*
125	* @returns VBox status.
126	* @param pDevIns The device instance data.
127	*
128	* @remarks Caller enters the device critical section.
129	*/
130	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
131	/** Pointer to a FNPDMDEVPOWERON() function. */
132	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
133
134	/**
135	* Reset notification.
136	*
137	* @returns VBox status.
138	* @param pDevIns The device instance data.
139	*
140	* @remarks Caller enters the device critical section.
141	*/
142	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
143	/** Pointer to a FNPDMDEVRESET() function. */
144	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
145
146	/**
147	* Soft reset notification.
148	*
149	* This is mainly for emulating the 286 style protected mode exits, in which
150	* most devices should remain in their current state.
151	*
152	* @returns VBox status.
153	* @param pDevIns The device instance data.
154	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
155	*
156	* @remarks Caller enters the device critical section.
157	*/
158	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
159	/** Pointer to a FNPDMDEVSOFTRESET() function. */
160	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
161
162	/** @name PDMVMRESET_F_XXX - VM reset flags.
163	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
164	* reset via PDMDevHlpVMReset.
165	* @{ */
166	/** Unknown reason. */
167	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
168	/** GIM triggered reset. */
169	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
170	/** The last source always causing hard resets. */
171	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
172	/** ACPI triggered reset. */
173	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
174	/** PS/2 system port A (92h) reset. */
175	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
176	/** Keyboard reset. */
177	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
178	/** Tripple fault. */
179	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
180	/** Reset source mask. */
181	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
182	/** @} */
183
184	/**
185	* Suspend notification.
186	*
187	* @returns VBox status.
188	* @param pDevIns The device instance data.
189	* @thread EMT(0)
190	*
191	* @remarks Caller enters the device critical section.
192	*/
193	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
194	/** Pointer to a FNPDMDEVSUSPEND() function. */
195	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
196
197	/**
198	* Resume notification.
199	*
200	* @returns VBox status.
201	* @param pDevIns The device instance data.
202	*
203	* @remarks Caller enters the device critical section.
204	*/
205	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
206	/** Pointer to a FNPDMDEVRESUME() function. */
207	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
208
209	/**
210	* Power Off notification.
211	*
212	* This is always called when VMR3PowerOff is called.
213	* There will be no callback when hot plugging devices.
214	*
215	* @param pDevIns The device instance data.
216	* @thread EMT(0)
217	*
218	* @remarks Caller enters the device critical section.
219	*/
220	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
221	/** Pointer to a FNPDMDEVPOWEROFF() function. */
222	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
223
224	/**
225	* Attach command.
226	*
227	* This is called to let the device attach to a driver for a specified LUN
228	* at runtime. This is not called during VM construction, the device
229	* constructor has to attach to all the available drivers.
230	*
231	* This is like plugging in the keyboard or mouse after turning on the PC.
232	*
233	* @returns VBox status code.
234	* @param pDevIns The device instance.
235	* @param iLUN The logical unit which is being attached.
236	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
237	*
238	* @remarks Caller enters the device critical section.
239	*/
240	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
241	/** Pointer to a FNPDMDEVATTACH() function. */
242	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
243
244	/**
245	* Detach notification.
246	*
247	* This is called when a driver is detaching itself from a LUN of the device.
248	* The device should adjust its state to reflect this.
249	*
250	* This is like unplugging the network cable to use it for the laptop or
251	* something while the PC is still running.
252	*
253	* @param pDevIns The device instance.
254	* @param iLUN The logical unit which is being detached.
255	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
256	*
257	* @remarks Caller enters the device critical section.
258	*/
259	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
260	/** Pointer to a FNPDMDEVDETACH() function. */
261	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
262
263	/**
264	* Query the base interface of a logical unit.
265	*
266	* @returns VBOX status code.
267	* @param pDevIns The device instance.
268	* @param iLUN The logicial unit to query.
269	* @param ppBase Where to store the pointer to the base interface of the LUN.
270	*
271	* @remarks The device critical section is not entered.
272	*/
273	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
274	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
275	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
276
277	/**
278	* Init complete notification (after ring-0 & RC init since 5.1).
279	*
280	* This can be done to do communication with other devices and other
281	* initialization which requires everything to be in place.
282	*
283	* @returns VBOX status code.
284	* @param pDevIns The device instance.
285	*
286	* @remarks Caller enters the device critical section.
287	*/
288	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
289	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
290	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
291
292
293	/**
294	* The context of a pfnMemSetup call.
295	*/
296	typedef enum PDMDEVMEMSETUPCTX
297	{
298	/** Invalid zero value. */
299	PDMDEVMEMSETUPCTX_INVALID = 0,
300	/** After construction. */
301	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
302	/** After reset. */
303	PDMDEVMEMSETUPCTX_AFTER_RESET,
304	/** Type size hack. */
305	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
306	} PDMDEVMEMSETUPCTX;
307
308
309	/**
310	* PDM Device Registration Structure.
311	*
312	* This structure is used when registering a device from VBoxInitDevices() in HC
313	* Ring-3. PDM will continue use till the VM is terminated.
314	*
315	* @note The first part is the same in every context.
316	*/
317	typedef struct PDMDEVREGR3
318	{
319	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
320	uint32_t u32Version;
321	/** Reserved, must be zero. */
322	uint32_t uReserved0;
323	/** Device name, must match the ring-3 one. */
324	char szName[32];
325	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
326	uint32_t fFlags;
327	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
328	uint32_t fClass;
329	/** Maximum number of instances (per VM). */
330	uint32_t cMaxInstances;
331	/** The shared data structure version number. */
332	uint32_t uSharedVersion;
333	/** Size of the instance data. */
334	uint32_t cbInstanceShared;
335	/** Size of the ring-0 instance data. */
336	uint32_t cbInstanceCC;
337	/** Size of the raw-mode instance data. */
338	uint32_t cbInstanceRC;
339	/** Max number of PCI devices. */
340	uint16_t cMaxPciDevices;
341	/** Max number of MSI-X vectors in any of the PCI devices. */
342	uint16_t cMaxMsixVectors;
343	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
344	* remain unchanged from registration till VM destruction. */
345	const char *pszDescription;
346
347	/** Name of the raw-mode context module (no path).
348	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
349	const char *pszRCMod;
350	/** Name of the ring-0 module (no path).
351	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
352	const char *pszR0Mod;
353
354	/** Construct instance - required. */
355	PFNPDMDEVCONSTRUCT pfnConstruct;
356	/** Destruct instance - optional.
357	* Critical section NOT entered (will be destroyed). */
358	PFNPDMDEVDESTRUCT pfnDestruct;
359	/** Relocation command - optional.
360	* Critical section NOT entered. */
361	PFNPDMDEVRELOCATE pfnRelocate;
362	/**
363	* Memory setup callback.
364	*
365	* @param pDevIns The device instance data.
366	* @param enmCtx Indicates the context of the call.
367	* @remarks The critical section is entered prior to calling this method.
368	*/
369	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
370	/** Power on notification - optional.
371	* Critical section is entered. */
372	PFNPDMDEVPOWERON pfnPowerOn;
373	/** Reset notification - optional.
374	* Critical section is entered. */
375	PFNPDMDEVRESET pfnReset;
376	/** Suspend notification - optional.
377	* Critical section is entered. */
378	PFNPDMDEVSUSPEND pfnSuspend;
379	/** Resume notification - optional.
380	* Critical section is entered. */
381	PFNPDMDEVRESUME pfnResume;
382	/** Attach command - optional.
383	* Critical section is entered. */
384	PFNPDMDEVATTACH pfnAttach;
385	/** Detach notification - optional.
386	* Critical section is entered. */
387	PFNPDMDEVDETACH pfnDetach;
388	/** Query a LUN base interface - optional.
389	* Critical section is NOT entered. */
390	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
391	/** Init complete notification - optional.
392	* Critical section is entered. */
393	PFNPDMDEVINITCOMPLETE pfnInitComplete;
394	/** Power off notification - optional.
395	* Critical section is entered. */
396	PFNPDMDEVPOWEROFF pfnPowerOff;
397	/** Software system reset notification - optional.
398	* Critical section is entered. */
399	PFNPDMDEVSOFTRESET pfnSoftReset;
400
401	/** @name Reserved for future extensions, must be zero.
402	* @{ */
403	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
406	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
407	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
408	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
409	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
410	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
411	/** @} */
412
413	/** Initialization safty marker. */
414	uint32_t u32VersionEnd;
415	} PDMDEVREGR3;
416	/** Pointer to a PDM Device Structure. */
417	typedef PDMDEVREGR3 *PPDMDEVREGR3;
418	/** Const pointer to a PDM Device Structure. */
419	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
420	/** Current DEVREGR3 version number. */
421	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
422
423
424	/** PDM Device Flags.
425	* @{ */
426	/** This flag is used to indicate that the device has a R0 component. */
427	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
428	/** Requires the ring-0 component, ignore configuration values. */
429	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
430	/** Requires the ring-0 component, ignore configuration values. */
431	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
432
433	/** This flag is used to indicate that the device has a RC component. */
434	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
435	/** Requires the raw-mode component, ignore configuration values. */
436	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
437	/** Requires the raw-mode component, ignore configuration values. */
438	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
439
440	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
441	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
442
443	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
444	* The bit count for the current host.
445	* @note Superfluous, but still around for hysterical raisins. */
446	#if HC_ARCH_BITS == 32
447	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
448	#elif HC_ARCH_BITS == 64
449	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
450	#else
451	# error Unsupported HC_ARCH_BITS value.
452	#endif
453	/** The host bit count mask. */
454	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
455
456	/** The device support only 32-bit guests. */
457	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
458	/** The device support only 64-bit guests. */
459	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
460	/** The device support both 32-bit & 64-bit guests. */
461	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
462	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
463	* The guest bit count for the current compilation. */
464	#if GC_ARCH_BITS == 32
465	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
466	#elif GC_ARCH_BITS == 64
467	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
468	#else
469	# error Unsupported GC_ARCH_BITS value.
470	#endif
471	/** The guest bit count mask. */
472	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
473
474	/** A convenience. */
475	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
476
477	/** Indicates that the device needs to be notified before the drivers when suspending. */
478	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
479	/** Indicates that the device needs to be notified before the drivers when powering off. */
480	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
481	/** Indicates that the device needs to be notified before the drivers when resetting. */
482	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
483
484	/** This flag is used to indicate that the device has been converted to the
485	* new device style. */
486	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
487
488	/** @} */
489
490
491	/** PDM Device Classes.
492	* The order is important, lower bit earlier instantiation.
493	* @{ */
494	/** Architecture device. */
495	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
496	/** Architecture BIOS device. */
497	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
498	/** PCI bus brigde. */
499	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
500	/** PCI built-in device (e.g. PCI root complex devices). */
501	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
502	/** Input device (mouse, keyboard, joystick, HID, ...). */
503	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
504	/** Interrupt controller (PIC). */
505	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
506	/** Interval controoler (PIT). */
507	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
508	/** RTC/CMOS. */
509	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
510	/** DMA controller. */
511	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
512	/** VMM Device. */
513	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
514	/** Graphics device, like VGA. */
515	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
516	/** Storage controller device. */
517	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
518	/** Network interface controller. */
519	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
520	/** Audio. */
521	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
522	/** USB HIC. */
523	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
524	/** ACPI. */
525	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
526	/** Serial controller device. */
527	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
528	/** Parallel controller device */
529	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
530	/** Host PCI pass-through device */
531	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
532	/** Misc devices (always last). */
533	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
534	/** @} */
535
536
537	/**
538	* PDM Device Registration Structure, ring-0.
539	*
540	* This structure is used when registering a device from VBoxInitDevices() in HC
541	* Ring-0. PDM will continue use till the VM is terminated.
542	*/
543	typedef struct PDMDEVREGR0
544	{
545	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
546	uint32_t u32Version;
547	/** Reserved, must be zero. */
548	uint32_t uReserved0;
549	/** Device name, must match the ring-3 one. */
550	char szName[32];
551	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
552	uint32_t fFlags;
553	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
554	uint32_t fClass;
555	/** Maximum number of instances (per VM). */
556	uint32_t cMaxInstances;
557	/** The shared data structure version number. */
558	uint32_t uSharedVersion;
559	/** Size of the instance data. */
560	uint32_t cbInstanceShared;
561	/** Size of the ring-0 instance data. */
562	uint32_t cbInstanceCC;
563	/** Size of the raw-mode instance data. */
564	uint32_t cbInstanceRC;
565	/** Max number of PCI devices. */
566	uint16_t cMaxPciDevices;
567	/** Max number of MSI-X vectors in any of the PCI devices. */
568	uint16_t cMaxMsixVectors;
569	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
570	* remain unchanged from registration till VM destruction. */
571	const char *pszDescription;
572
573	/**
574	* Early construction callback (optional).
575	*
576	* This is called right after the device instance structure has been allocated
577	* and before the ring-3 constructor gets called.
578	*
579	* @returns VBox status code.
580	* @param pDevIns The device instance data.
581	* @note The destructure is always called, regardless of the return status.
582	*/
583	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
584
585	/**
586	* Regular construction callback (optional).
587	*
588	* This is called after (or during) the ring-3 constructor.
589	*
590	* @returns VBox status code.
591	* @param pDevIns The device instance data.
592	* @note The destructure is always called, regardless of the return status.
593	*/
594	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
595
596	/**
597	* Destructor (optional).
598	*
599	* This is called after the ring-3 destruction. This is not called if ring-3
600	* fails to trigger it (e.g. process is killed or crashes).
601	*
602	* @param pDevIns The device instance data.
603	*/
604	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
605
606	/**
607	* Final destructor (optional).
608	*
609	* This is called right before the memory is freed, which happens when the
610	* VM/GVM object is destroyed. This is always called.
611	*
612	* @param pDevIns The device instance data.
613	*/
614	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
615
616	/**
617	* Generic request handler (optional).
618	*
619	* @param pDevIns The device instance data.
620	* @param uReq Device specific request.
621	* @param uArg Request argument.
622	*/
623	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
624
625	/** @name Reserved for future extensions, must be zero.
626	* @{ */
627	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
630	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
631	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
632	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
633	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
634	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
635	/** @} */
636
637	/** Initialization safty marker. */
638	uint32_t u32VersionEnd;
639	} PDMDEVREGR0;
640	/** Pointer to a ring-0 PDM device registration structure. */
641	typedef PDMDEVREGR0 *PPDMDEVREGR0;
642	/** Pointer to a const ring-0 PDM device registration structure. */
643	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
644	/** Current DEVREGR0 version number. */
645	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
646
647
648	/**
649	* PDM Device Registration Structure, raw-mode
650	*
651	* At the moment, this structure is mostly here to match the other two contexts.
652	*/
653	typedef struct PDMDEVREGRC
654	{
655	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
656	uint32_t u32Version;
657	/** Reserved, must be zero. */
658	uint32_t uReserved0;
659	/** Device name, must match the ring-3 one. */
660	char szName[32];
661	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
662	uint32_t fFlags;
663	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
664	uint32_t fClass;
665	/** Maximum number of instances (per VM). */
666	uint32_t cMaxInstances;
667	/** The shared data structure version number. */
668	uint32_t uSharedVersion;
669	/** Size of the instance data. */
670	uint32_t cbInstanceShared;
671	/** Size of the ring-0 instance data. */
672	uint32_t cbInstanceCC;
673	/** Size of the raw-mode instance data. */
674	uint32_t cbInstanceRC;
675	/** Max number of PCI devices. */
676	uint16_t cMaxPciDevices;
677	/** Max number of MSI-X vectors in any of the PCI devices. */
678	uint16_t cMaxMsixVectors;
679	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
680	* remain unchanged from registration till VM destruction. */
681	const char *pszDescription;
682
683	/**
684	* Constructor callback.
685	*
686	* This is called much later than both the ring-0 and ring-3 constructors, since
687	* raw-mode v2 require a working VMM to run actual code.
688	*
689	* @returns VBox status code.
690	* @param pDevIns The device instance data.
691	* @note The destructure is always called, regardless of the return status.
692	*/
693	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
694
695	/** @name Reserved for future extensions, must be zero.
696	* @{ */
697	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
700	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
701	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
702	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
703	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
704	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
705	/** @} */
706
707	/** Initialization safty marker. */
708	uint32_t u32VersionEnd;
709	} PDMDEVREGRC;
710	/** Pointer to a raw-mode PDM device registration structure. */
711	typedef PDMDEVREGRC *PPDMDEVREGRC;
712	/** Pointer to a const raw-mode PDM device registration structure. */
713	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
714	/** Current DEVREGRC version number. */
715	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
716
717
718
719	/** @def PDM_DEVREG_VERSION
720	* Current DEVREG version number. */
721	/** @typedef PDMDEVREGR3
722	* A current context PDM device registration structure. */
723	/** @typedef PPDMDEVREGR3
724	* Pointer to a current context PDM device registration structure. */
725	/** @typedef PCPDMDEVREGR3
726	* Pointer to a const current context PDM device registration structure. */
727	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
728	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
729	typedef PDMDEVREGR3 PDMDEVREG;
730	typedef PPDMDEVREGR3 PPDMDEVREG;
731	typedef PCPDMDEVREGR3 PCPDMDEVREG;
732	#elif defined(IN_RING0)
733	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
734	typedef PDMDEVREGR0 PDMDEVREG;
735	typedef PPDMDEVREGR0 PPDMDEVREG;
736	typedef PCPDMDEVREGR0 PCPDMDEVREG;
737	#elif defined(IN_RC)
738	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
739	typedef PDMDEVREGRC PDMDEVREG;
740	typedef PPDMDEVREGRC PPDMDEVREG;
741	typedef PCPDMDEVREGRC PCPDMDEVREG;
742	#else
743	# error "Not IN_RING3, IN_RING0 or IN_RC"
744	#endif
745
746
747	/**
748	* Device registrations for ring-0 modules.
749	*
750	* This structure is used directly and must therefore reside in persistent
751	* memory (i.e. the data section).
752	*/
753	typedef struct PDMDEVMODREGR0
754	{
755	/** The structure version (PDM_DEVMODREGR0_VERSION). */
756	uint32_t u32Version;
757	/** Number of devices in the array papDevRegs points to. */
758	uint32_t cDevRegs;
759	/** Pointer to device registration structures. */
760	PCPDMDEVREGR0 *papDevRegs;
761	/** The ring-0 module handle - PDM internal, fingers off. */
762	void *hMod;
763	/** List entry - PDM internal, fingers off. */
764	RTLISTNODE ListEntry;
765	} PDMDEVMODREGR0;
766	/** Pointer to device registriations for a ring-0 module. */
767	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
768	/** Current PDMDEVMODREGR0 version number. */
769	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
770
771
772	/** @name IRQ Level for use with the *SetIrq APIs.
773	* @{
774	*/
775	/** Assert the IRQ (can assume value 1). */
776	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
777	/** Deassert the IRQ (can assume value 0). */
778	#define PDM_IRQ_LEVEL_LOW 0
779	/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
780	* automatically deasserts it after delivery to the APIC (IOAPIC).
781	* @note Only suitable for edge trigger interrupts. */
782	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
783	/** @} */
784
785	/**
786	* Registration record for MSI/MSI-X emulation.
787	*/
788	typedef struct PDMMSIREG
789	{
790	/** Number of MSI interrupt vectors, 0 if MSI not supported */
791	uint16_t cMsiVectors;
792	/** Offset of MSI capability */
793	uint8_t iMsiCapOffset;
794	/** Offset of next capability to MSI */
795	uint8_t iMsiNextOffset;
796	/** If we support 64-bit MSI addressing */
797	bool fMsi64bit;
798	/** If we do not support per-vector masking */
799	bool fMsiNoMasking;
800
801	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
802	uint16_t cMsixVectors;
803	/** Offset of MSI-X capability */
804	uint8_t iMsixCapOffset;
805	/** Offset of next capability to MSI-X */
806	uint8_t iMsixNextOffset;
807	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
808	uint8_t iMsixBar;
809	} PDMMSIREG;
810	typedef PDMMSIREG *PPDMMSIREG;
811
812	/**
813	* PCI Bus registration structure.
814	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
815	*/
816	typedef struct PDMPCIBUSREGR3
817	{
818	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
819	uint32_t u32Version;
820
821	/**
822	* Registers the device with the default PCI bus.
823	*
824	* @returns VBox status code.
825	* @param pDevIns Device instance of the PCI Bus.
826	* @param pPciDev The PCI device structure.
827	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
828	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
829	* device number (0-31).
830	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
831	* function number (0-7).
832	* @param pszName Device name (static but not unique).
833	*
834	* @remarks Caller enters the PDM critical section.
835	*/
836	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
837	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
838
839	/**
840	* Initialize MSI or MSI-X emulation support in a PCI device.
841	*
842	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
843	* vast majority of device emulation it covers everything necessary. It's
844	* fully automatic, taking care of all BAR and config space requirements,
845	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
846	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
847	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
848	*
849	* A device not using this can still offer MSI/MSI-X. In this case it's
850	* completely up to the device (in the MSI-X case) to create/register the
851	* necessary MMIO BAR, handle all config space/BAR updating and take care
852	* of delivering the interrupts appropriately.
853	*
854	* @returns VBox status code.
855	* @param pDevIns Device instance of the PCI Bus.
856	* @param pPciDev The PCI device structure.
857	* @param pMsiReg MSI emulation registration structure
858	* @remarks Caller enters the PDM critical section.
859	*/
860	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
861
862	/**
863	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
864	*
865	* @returns VBox status code.
866	* @param pDevIns Device instance of the PCI Bus.
867	* @param pPciDev The PCI device structure.
868	* @param iRegion The region number.
869	* @param cbRegion Size of the region.
870	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
871	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
872	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
873	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
874	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
875	* @a fFlags, UINT64_MAX if no handle is passed
876	* (old style).
877	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
878	* is given.
879	* @remarks Caller enters the PDM critical section.
880	*/
881	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
882	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
883	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
884
885	/**
886	* Register PCI configuration space read/write intercept callbacks.
887	*
888	* @param pDevIns Device instance of the PCI Bus.
889	* @param pPciDev The PCI device structure.
890	* @param pfnRead Pointer to the user defined PCI config read function.
891	* @param pfnWrite Pointer to the user defined PCI config write function.
892	* to call default PCI config write function. Can be NULL.
893	* @remarks Caller enters the PDM critical section.
894	* @thread EMT
895	*/
896	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
897	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
898
899	/**
900	* Perform a PCI configuration space write, bypassing interception.
901	*
902	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
903	*
904	* @returns Strict VBox status code (mainly DBGFSTOP).
905	* @param pDevIns Device instance of the PCI Bus.
906	* @param pPciDev The PCI device which config space is being read.
907	* @param uAddress The config space address.
908	* @param cb The size of the read: 1, 2 or 4 bytes.
909	* @param u32Value The value to write.
910	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
911	* that the (root) bus will have done that already.
912	*/
913	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
914	uint32_t uAddress, unsigned cb, uint32_t u32Value));
915
916	/**
917	* Perform a PCI configuration space read, bypassing interception.
918	*
919	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
920	*
921	* @returns Strict VBox status code (mainly DBGFSTOP).
922	* @param pDevIns Device instance of the PCI Bus.
923	* @param pPciDev The PCI device which config space is being read.
924	* @param uAddress The config space address.
925	* @param cb The size of the read: 1, 2 or 4 bytes.
926	* @param pu32Value Where to return the value.
927	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
928	* that the (root) bus will have done that already.
929	*/
930	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
931	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
932
933	/**
934	* Set the IRQ for a PCI device.
935	*
936	* @param pDevIns Device instance of the PCI Bus.
937	* @param pPciDev The PCI device structure.
938	* @param iIrq IRQ number to set.
939	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
940	* @param uTagSrc The IRQ tag and source (for tracing).
941	* @remarks Caller enters the PDM critical section.
942	*/
943	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
944
945	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
946	uint32_t u32EndVersion;
947	} PDMPCIBUSREGR3;
948	/** Pointer to a PCI bus registration structure. */
949	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
950	/** Current PDMPCIBUSREGR3 version number. */
951	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
952
953	/**
954	* PCI Bus registration structure for ring-0.
955	*/
956	typedef struct PDMPCIBUSREGR0
957	{
958	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
959	uint32_t u32Version;
960	/** The PCI bus number (from ring-3 registration). */
961	uint32_t iBus;
962	/**
963	* Set the IRQ for a PCI device.
964	*
965	* @param pDevIns Device instance of the PCI Bus.
966	* @param pPciDev The PCI device structure.
967	* @param iIrq IRQ number to set.
968	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
969	* @param uTagSrc The IRQ tag and source (for tracing).
970	* @remarks Caller enters the PDM critical section.
971	*/
972	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
973	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
974	uint32_t u32EndVersion;
975	} PDMPCIBUSREGR0;
976	/** Pointer to a PCI bus ring-0 registration structure. */
977	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
978	/** Current PDMPCIBUSREGR0 version number. */
979	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
980
981	/**
982	* PCI Bus registration structure for raw-mode.
983	*/
984	typedef struct PDMPCIBUSREGRC
985	{
986	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
987	uint32_t u32Version;
988	/** The PCI bus number (from ring-3 registration). */
989	uint32_t iBus;
990	/**
991	* Set the IRQ for a PCI device.
992	*
993	* @param pDevIns Device instance of the PCI Bus.
994	* @param pPciDev The PCI device structure.
995	* @param iIrq IRQ number to set.
996	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
997	* @param uTagSrc The IRQ tag and source (for tracing).
998	* @remarks Caller enters the PDM critical section.
999	*/
1000	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
1001	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1002	uint32_t u32EndVersion;
1003	} PDMPCIBUSREGRC;
1004	/** Pointer to a PCI bus raw-mode registration structure. */
1005	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1006	/** Current PDMPCIBUSREGRC version number. */
1007	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1008
1009	/** PCI bus registration structure for the current context. */
1010	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1011	/** Pointer to a PCI bus registration structure for the current context. */
1012	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1013	/** PCI bus registration structure version for the current context. */
1014	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1015
1016
1017	/**
1018	* PCI Bus RC helpers.
1019	*/
1020	typedef struct PDMPCIHLPRC
1021	{
1022	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1023	uint32_t u32Version;
1024
1025	/**
1026	* Set an ISA IRQ.
1027	*
1028	* @param pDevIns PCI device instance.
1029	* @param iIrq IRQ number to set.
1030	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1031	* @param uTagSrc The IRQ tag and source (for tracing).
1032	* @thread EMT only.
1033	*/
1034	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1035
1036	/**
1037	* Set an I/O-APIC IRQ.
1038	*
1039	* @param pDevIns PCI device instance.
1040	* @param uBusDevFn The bus:device:function of the device initiating the
1041	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1042	* interrupt.
1043	* @param iIrq IRQ number to set.
1044	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1045	* @param uTagSrc The IRQ tag and source (for tracing).
1046	* @thread EMT only.
1047	*/
1048	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1049
1050	/**
1051	* Send an MSI.
1052	*
1053	* @param pDevIns PCI device instance.
1054	* @param uBusDevFn The bus:device:function of the device initiating the
1055	* MSI. Cannot be NIL_PCIBDF.
1056	* @param pMsi The MSI to send.
1057	* @param uTagSrc The IRQ tag and source (for tracing).
1058	* @thread EMT only.
1059	*/
1060	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1061
1062
1063	/**
1064	* Acquires the PDM lock.
1065	*
1066	* @returns VINF_SUCCESS on success.
1067	* @returns rc if we failed to acquire the lock.
1068	* @param pDevIns The PCI device instance.
1069	* @param rc What to return if we fail to acquire the lock.
1070	*
1071	* @sa PDMCritSectEnter
1072	*/
1073	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1074
1075	/**
1076	* Releases the PDM lock.
1077	*
1078	* @param pDevIns The PCI device instance.
1079	*/
1080	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1081
1082	/**
1083	* Gets a bus by it's PDM ordinal (typically the parent bus).
1084	*
1085	* @returns Pointer to the device instance of the bus.
1086	* @param pDevIns The PCI bus device instance.
1087	* @param idxPdmBus The PDM ordinal value of the bus to get.
1088	*/
1089	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1090
1091	/** Just a safety precaution. */
1092	uint32_t u32TheEnd;
1093	} PDMPCIHLPRC;
1094	/** Pointer to PCI helpers. */
1095	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1096	/** Pointer to const PCI helpers. */
1097	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1098
1099	/** Current PDMPCIHLPRC version number. */
1100	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1101
1102
1103	/**
1104	* PCI Bus R0 helpers.
1105	*/
1106	typedef struct PDMPCIHLPR0
1107	{
1108	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1109	uint32_t u32Version;
1110
1111	/**
1112	* Set an ISA IRQ.
1113	*
1114	* @param pDevIns PCI device instance.
1115	* @param iIrq IRQ number to set.
1116	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1117	* @param uTagSrc The IRQ tag and source (for tracing).
1118	* @thread EMT only.
1119	*/
1120	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1121
1122	/**
1123	* Set an I/O-APIC IRQ.
1124	*
1125	* @param pDevIns PCI device instance.
1126	* @param uBusDevFn The bus:device:function of the device initiating the
1127	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1128	* interrupt.
1129	* @param iIrq IRQ number to set.
1130	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1131	* @param uTagSrc The IRQ tag and source (for tracing).
1132	* @thread EMT only.
1133	*/
1134	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1135
1136	/**
1137	* Send an MSI.
1138	*
1139	* @param pDevIns PCI device instance.
1140	* @param uBusDevFn The bus:device:function of the device initiating the
1141	* MSI. Cannot be NIL_PCIBDF.
1142	* @param pMsi The MSI to send.
1143	* @param uTagSrc The IRQ tag and source (for tracing).
1144	* @thread EMT only.
1145	*/
1146	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1147
1148	/**
1149	* Acquires the PDM lock.
1150	*
1151	* @returns VINF_SUCCESS on success.
1152	* @returns rc if we failed to acquire the lock.
1153	* @param pDevIns The PCI device instance.
1154	* @param rc What to return if we fail to acquire the lock.
1155	*
1156	* @sa PDMCritSectEnter
1157	*/
1158	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1159
1160	/**
1161	* Releases the PDM lock.
1162	*
1163	* @param pDevIns The PCI device instance.
1164	*/
1165	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1166
1167	/**
1168	* Gets a bus by it's PDM ordinal (typically the parent bus).
1169	*
1170	* @returns Pointer to the device instance of the bus.
1171	* @param pDevIns The PCI bus device instance.
1172	* @param idxPdmBus The PDM ordinal value of the bus to get.
1173	*/
1174	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1175
1176	/** Just a safety precaution. */
1177	uint32_t u32TheEnd;
1178	} PDMPCIHLPR0;
1179	/** Pointer to PCI helpers. */
1180	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1181	/** Pointer to const PCI helpers. */
1182	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1183
1184	/** Current PDMPCIHLPR0 version number. */
1185	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1186
1187	/**
1188	* PCI device helpers.
1189	*/
1190	typedef struct PDMPCIHLPR3
1191	{
1192	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1193	uint32_t u32Version;
1194
1195	/**
1196	* Set an ISA IRQ.
1197	*
1198	* @param pDevIns The PCI device instance.
1199	* @param iIrq IRQ number to set.
1200	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1201	* @param uTagSrc The IRQ tag and source (for tracing).
1202	*/
1203	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1204
1205	/**
1206	* Set an I/O-APIC IRQ.
1207	*
1208	* @param pDevIns The PCI device instance.
1209	* @param uBusDevFn The bus:device:function of the device initiating the
1210	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1211	* interrupt.
1212	* @param iIrq IRQ number to set.
1213	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1214	* @param uTagSrc The IRQ tag and source (for tracing).
1215	*/
1216	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1217
1218	/**
1219	* Send an MSI.
1220	*
1221	* @param pDevIns PCI device instance.
1222	* @param uBusDevFn The bus:device:function of the device initiating the
1223	* MSI. Cannot be NIL_PCIBDF.
1224	* @param pMsi The MSI to send.
1225	* @param uTagSrc The IRQ tag and source (for tracing).
1226	*/
1227	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1228
1229	/**
1230	* Acquires the PDM lock.
1231	*
1232	* @returns VINF_SUCCESS on success.
1233	* @returns Fatal error on failure.
1234	* @param pDevIns The PCI device instance.
1235	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1236	*
1237	* @sa PDMCritSectEnter
1238	*/
1239	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1240
1241	/**
1242	* Releases the PDM lock.
1243	*
1244	* @param pDevIns The PCI device instance.
1245	*/
1246	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1247
1248	/**
1249	* Gets a bus by it's PDM ordinal (typically the parent bus).
1250	*
1251	* @returns Pointer to the device instance of the bus.
1252	* @param pDevIns The PCI bus device instance.
1253	* @param idxPdmBus The PDM ordinal value of the bus to get.
1254	*/
1255	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1256
1257	/** Just a safety precaution. */
1258	uint32_t u32TheEnd;
1259	} PDMPCIHLPR3;
1260	/** Pointer to PCI helpers. */
1261	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1262	/** Pointer to const PCI helpers. */
1263	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1264
1265	/** Current PDMPCIHLPR3 version number. */
1266	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1267
1268
1269	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1270	* These flags are used for memory access transactions via the IOMMU interface.
1271	* @{ */
1272	/** Memory read. */
1273	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1274	/** Memory write. */
1275	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1276	/** Valid flag mask. */
1277	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1278	/** @} */
1279
1280	/**
1281	* IOMMU registration structure for ring-0.
1282	*/
1283	typedef struct PDMIOMMUREGR0
1284	{
1285	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1286	* version. */
1287	uint32_t u32Version;
1288	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1289	uint32_t idxIommu;
1290
1291	/**
1292	* Translates the physical address for a memory transaction through the IOMMU.
1293	*
1294	* @returns VBox status code.
1295	* @param pDevIns The IOMMU device instance.
1296	* @param idDevice The device identifier (bus, device, function).
1297	* @param uIova The I/O virtual address being accessed.
1298	* @param cbIova The size of the access.
1299	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1300	* @param pGCPhysSpa Where to store the translated system physical address.
1301	* @param pcbContiguous Where to store the number of contiguous bytes translated
1302	* and permission-checked.
1303	*
1304	* @thread Any.
1305	*/
1306	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1307	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1308
1309	/**
1310	* Translates in bulk physical page addresses for memory transactions through the
1311	* IOMMU.
1312	*
1313	* @returns VBox status code.
1314	* @param pDevIns The IOMMU device instance.
1315	* @param idDevice The device identifier (bus, device, function).
1316	* @param cIovas The number of I/O virtual addresses being accessed.
1317	* @param pauIovas The I/O virtual addresses being accessed.
1318	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1319	* @param paGCPhysSpa Where to store the translated system physical page
1320	* addresses.
1321	*
1322	* @thread Any.
1323	*/
1324	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1325	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1326
1327	/**
1328	* Performs an interrupt remap request through the IOMMU.
1329	*
1330	* @returns VBox status code.
1331	* @param pDevIns The IOMMU device instance.
1332	* @param idDevice The device identifier (bus, device, function).
1333	* @param pMsiIn The source MSI.
1334	* @param pMsiOut Where to store the remapped MSI.
1335	*
1336	* @thread Any.
1337	*/
1338	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1339
1340	/** Just a safety precaution. */
1341	uint32_t u32TheEnd;
1342	} PDMIOMMUREGR0;
1343	/** Pointer to a IOMMU registration structure. */
1344	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1345
1346	/** Current PDMIOMMUREG version number. */
1347	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1348
1349
1350	/**
1351	* IOMMU registration structure for raw-mode.
1352	*/
1353	typedef struct PDMIOMMUREGRC
1354	{
1355	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1356	* version. */
1357	uint32_t u32Version;
1358	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1359	uint32_t idxIommu;
1360
1361	/**
1362	* Translates the physical address for a memory transaction through the IOMMU.
1363	*
1364	* @returns VBox status code.
1365	* @param pDevIns The IOMMU device instance.
1366	* @param idDevice The device identifier (bus, device, function).
1367	* @param uIova The I/O virtual address being accessed.
1368	* @param cbIova The size of the access.
1369	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1370	* @param pGCPhysSpa Where to store the translated system physical address.
1371	* @param pcbContiguous Where to store the number of contiguous bytes translated
1372	* and permission-checked.
1373	*
1374	* @thread Any.
1375	*/
1376	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1377	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1378
1379	/**
1380	* Translates in bulk physical page addresses for memory transactions through the
1381	* IOMMU.
1382	*
1383	* @returns VBox status code.
1384	* @param pDevIns The IOMMU device instance.
1385	* @param idDevice The device identifier (bus, device, function).
1386	* @param cIovas The number of I/O virtual addresses being accessed.
1387	* @param pauIovas The I/O virtual addresses being accessed.
1388	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1389	* @param paGCPhysSpa Where to store the translated system physical page
1390	* addresses.
1391	*
1392	* @thread Any.
1393	*/
1394	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1395	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1396
1397	/**
1398	* Performs an interrupt remap request through the IOMMU.
1399	*
1400	* @returns VBox status code.
1401	* @param pDevIns The IOMMU device instance.
1402	* @param idDevice The device identifier (bus, device, function).
1403	* @param pMsiIn The source MSI.
1404	* @param pMsiOut Where to store the remapped MSI.
1405	*
1406	* @thread Any.
1407	*/
1408	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1409
1410	/** Just a safety precaution. */
1411	uint32_t u32TheEnd;
1412	} PDMIOMMUREGRC;
1413	/** Pointer to a IOMMU registration structure. */
1414	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1415
1416	/** Current PDMIOMMUREG version number. */
1417	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1418
1419
1420	/**
1421	* IOMMU registration structure for ring-3.
1422	*/
1423	typedef struct PDMIOMMUREGR3
1424	{
1425	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1426	* version. */
1427	uint32_t u32Version;
1428	/** Padding. */
1429	uint32_t uPadding0;
1430
1431	/**
1432	* Translates the physical address for a memory transaction through the IOMMU.
1433	*
1434	* @returns VBox status code.
1435	* @param pDevIns The IOMMU device instance.
1436	* @param idDevice The device identifier (bus, device, function).
1437	* @param uIova The I/O virtual address being accessed.
1438	* @param cbIova The size of the access.
1439	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1440	* @param pGCPhysSpa Where to store the translated system physical address.
1441	* @param pcbContiguous Where to store the number of contiguous bytes translated
1442	* and permission-checked.
1443	*
1444	* @thread Any.
1445	*/
1446	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1447	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1448
1449	/**
1450	* Translates in bulk physical page addresses for memory transactions through the
1451	* IOMMU.
1452	*
1453	* @returns VBox status code.
1454	* @param pDevIns The IOMMU device instance.
1455	* @param idDevice The device identifier (bus, device, function).
1456	* @param cIovas The number of I/O virtual addresses being accessed.
1457	* @param pauIovas The I/O virtual addresses being accessed.
1458	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1459	* @param paGCPhysSpa Where to store the translated system physical page
1460	* addresses.
1461	*
1462	* @thread Any.
1463	*/
1464	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1465	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1466
1467	/**
1468	* Performs an interrupt remap request through the IOMMU.
1469	*
1470	* @returns VBox status code.
1471	* @param pDevIns The IOMMU device instance.
1472	* @param idDevice The device identifier (bus, device, function).
1473	* @param pMsiIn The source MSI.
1474	* @param pMsiOut Where to store the remapped MSI.
1475	*
1476	* @thread Any.
1477	*/
1478	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1479
1480	/** Just a safety precaution. */
1481	uint32_t u32TheEnd;
1482	} PDMIOMMUREGR3;
1483	/** Pointer to a IOMMU registration structure. */
1484	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1485
1486	/** Current PDMIOMMUREG version number. */
1487	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1488
1489	/** IOMMU registration structure for the current context. */
1490	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1491	/** Pointer to an IOMMU registration structure for the current context. */
1492	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1493	/** IOMMU registration structure version for the current context. */
1494	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1495
1496
1497	/**
1498	* IOMMU helpers for ring-0.
1499	*/
1500	typedef struct PDMIOMMUHLPR0
1501	{
1502	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1503	uint32_t u32Version;
1504
1505	/**
1506	* Acquires the PDM lock.
1507	*
1508	* @returns VINF_SUCCESS on success.
1509	* @returns rc if we failed to acquire the lock.
1510	* @param pDevIns The PCI device instance.
1511	* @param rc What to return if we fail to acquire the lock.
1512	*
1513	* @sa PDMCritSectEnter
1514	*/
1515	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1516
1517	/**
1518	* Releases the PDM lock.
1519	*
1520	* @param pDevIns The PCI device instance.
1521	*/
1522	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1523
1524	/**
1525	* Check whether the calling thread owns the PDM lock.
1526	*
1527	* @returns @c true if the PDM lock is owned, @c false otherwise.
1528	* @param pDevIns The PCI device instance.
1529	*/
1530	DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1531
1532	/**
1533	* Send an MSI (when generated by the IOMMU device itself).
1534	*
1535	* @param pDevIns PCI device instance.
1536	* @param pMsi The MSI to send.
1537	* @param uTagSrc The IRQ tag and source (for tracing).
1538	*/
1539	DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1540
1541	/** Just a safety precaution. */
1542	uint32_t u32TheEnd;
1543	} PDMIOMMUHLPR0;
1544	/** Pointer to IOMMU helpers for ring-0. */
1545	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1546	/** Pointer to const IOMMU helpers for ring-0. */
1547	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1548
1549	/** Current PDMIOMMUHLPR0 version number. */
1550	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1551
1552
1553	/**
1554	* IOMMU helpers for raw-mode.
1555	*/
1556	typedef struct PDMIOMMUHLPRC
1557	{
1558	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1559	uint32_t u32Version;
1560
1561	/**
1562	* Acquires the PDM lock.
1563	*
1564	* @returns VINF_SUCCESS on success.
1565	* @returns rc if we failed to acquire the lock.
1566	* @param pDevIns The PCI device instance.
1567	* @param rc What to return if we fail to acquire the lock.
1568	*
1569	* @sa PDMCritSectEnter
1570	*/
1571	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1572
1573	/**
1574	* Releases the PDM lock.
1575	*
1576	* @param pDevIns The PCI device instance.
1577	*/
1578	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1579
1580	/**
1581	* Check whether the threads owns the PDM lock.
1582	*
1583	* @returns @c true if the PDM lock is owned, @c false otherwise.
1584	* @param pDevIns The PCI device instance.
1585	*/
1586	DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1587
1588	/**
1589	* Send an MSI (when generated by the IOMMU device itself).
1590	*
1591	* @param pDevIns PCI device instance.
1592	* @param pMsi The MSI to send.
1593	* @param uTagSrc The IRQ tag and source (for tracing).
1594	*/
1595	DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1596
1597	/** Just a safety precaution. */
1598	uint32_t u32TheEnd;
1599	} PDMIOMMUHLPRC;
1600	/** Pointer to IOMMU helpers for raw-mode. */
1601	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1602	/** Pointer to const IOMMU helpers for raw-mode. */
1603	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1604
1605	/** Current PDMIOMMUHLPRC version number. */
1606	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1607
1608
1609	/**
1610	* IOMMU helpers for ring-3.
1611	*/
1612	typedef struct PDMIOMMUHLPR3
1613	{
1614	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1615	uint32_t u32Version;
1616
1617	/**
1618	* Acquires the PDM lock.
1619	*
1620	* @returns VINF_SUCCESS on success.
1621	* @returns rc if we failed to acquire the lock.
1622	* @param pDevIns The PCI device instance.
1623	* @param rc What to return if we fail to acquire the lock.
1624	*
1625	* @sa PDMCritSectEnter
1626	*/
1627	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1628
1629	/**
1630	* Releases the PDM lock.
1631	*
1632	* @param pDevIns The PCI device instance.
1633	*/
1634	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1635
1636	/**
1637	* Check whether the threads owns the PDM lock.
1638	*
1639	* @returns @c true if the PDM lock is owned, @c false otherwise.
1640	* @param pDevIns The PCI device instance.
1641	*/
1642	DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1643
1644	/**
1645	* Send an MSI (when generated by the IOMMU device itself).
1646	*
1647	* @param pDevIns PCI device instance.
1648	* @param pMsi The MSI to send.
1649	* @param uTagSrc The IRQ tag and source (for tracing).
1650	*/
1651	DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1652
1653	/** Just a safety precaution. */
1654	uint32_t u32TheEnd;
1655	} PDMIOMMUHLPR3;
1656	/** Pointer to IOMMU helpers for raw-mode. */
1657	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1658	/** Pointer to const IOMMU helpers for raw-mode. */
1659	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1660
1661	/** Current PDMIOMMUHLPR3 version number. */
1662	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1663
1664
1665	/**
1666	* Programmable Interrupt Controller registration structure (all contexts).
1667	*/
1668	typedef struct PDMPICREG
1669	{
1670	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1671	uint32_t u32Version;
1672
1673	/**
1674	* Set the an IRQ.
1675	*
1676	* @param pDevIns Device instance of the PIC.
1677	* @param iIrq IRQ number to set.
1678	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1679	* @param uTagSrc The IRQ tag and source (for tracing).
1680	* @remarks Caller enters the PDM critical section.
1681	*/
1682	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1683
1684	/**
1685	* Get a pending interrupt.
1686	*
1687	* @returns Pending interrupt number.
1688	* @param pDevIns Device instance of the PIC.
1689	* @param puTagSrc Where to return the IRQ tag and source.
1690	* @remarks Caller enters the PDM critical section.
1691	*/
1692	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1693
1694	/** Just a safety precaution. */
1695	uint32_t u32TheEnd;
1696	} PDMPICREG;
1697	/** Pointer to a PIC registration structure. */
1698	typedef PDMPICREG *PPDMPICREG;
1699
1700	/** Current PDMPICREG version number. */
1701	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1702
1703	/**
1704	* PIC helpers, same in all contexts.
1705	*/
1706	typedef struct PDMPICHLP
1707	{
1708	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1709	uint32_t u32Version;
1710
1711	/**
1712	* Set the interrupt force action flag.
1713	*
1714	* @param pDevIns Device instance of the PIC.
1715	*/
1716	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1717
1718	/**
1719	* Clear the interrupt force action flag.
1720	*
1721	* @param pDevIns Device instance of the PIC.
1722	*/
1723	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1724
1725	/**
1726	* Acquires the PDM lock.
1727	*
1728	* @returns VINF_SUCCESS on success.
1729	* @returns rc if we failed to acquire the lock.
1730	* @param pDevIns The PIC device instance.
1731	* @param rc What to return if we fail to acquire the lock.
1732	*
1733	* @sa PDMCritSectEnter
1734	*/
1735	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1736
1737	/**
1738	* Releases the PDM lock.
1739	*
1740	* @param pDevIns The PIC device instance.
1741	*/
1742	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1743
1744	/** Just a safety precaution. */
1745	uint32_t u32TheEnd;
1746	} PDMPICHLP;
1747	/** Pointer to PIC helpers. */
1748	typedef PDMPICHLP *PPDMPICHLP;
1749	/** Pointer to const PIC helpers. */
1750	typedef const PDMPICHLP *PCPDMPICHLP;
1751
1752	/** Current PDMPICHLP version number. */
1753	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1754
1755
1756	/**
1757	* Firmware registration structure.
1758	*/
1759	typedef struct PDMFWREG
1760	{
1761	/** Struct version+magic number (PDM_FWREG_VERSION). */
1762	uint32_t u32Version;
1763
1764	/**
1765	* Checks whether this is a hard or soft reset.
1766	*
1767	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1768	* is 5, 9 or 0xA.
1769	*
1770	* @returns true if hard reset, false if soft.
1771	* @param pDevIns Device instance of the firmware.
1772	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1773	*/
1774	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1775
1776	/** Just a safety precaution. */
1777	uint32_t u32TheEnd;
1778	} PDMFWREG;
1779	/** Pointer to a FW registration structure. */
1780	typedef PDMFWREG *PPDMFWREG;
1781	/** Pointer to a const FW registration structure. */
1782	typedef PDMFWREG const *PCPDMFWREG;
1783
1784	/** Current PDMFWREG version number. */
1785	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1786
1787	/**
1788	* Firmware R3 helpers.
1789	*/
1790	typedef struct PDMFWHLPR3
1791	{
1792	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1793	uint32_t u32Version;
1794
1795	/** Just a safety precaution. */
1796	uint32_t u32TheEnd;
1797	} PDMFWHLPR3;
1798
1799	/** Pointer to FW R3 helpers. */
1800	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1801	/** Pointer to const FW R3 helpers. */
1802	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1803
1804	/** Current PDMFWHLPR3 version number. */
1805	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1806
1807
1808	/**
1809	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1810	*
1811	* Also used in saved-states, CFGM don't change existing values.
1812	*/
1813	typedef enum PDMAPICMODE
1814	{
1815	/** Invalid 0 entry. */
1816	PDMAPICMODE_INVALID = 0,
1817	/** No APIC. */
1818	PDMAPICMODE_NONE,
1819	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1820	PDMAPICMODE_APIC,
1821	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1822	PDMAPICMODE_X2APIC,
1823	/** The usual 32-bit paranoia. */
1824	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1825	} PDMAPICMODE;
1826
1827	/**
1828	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1829	*/
1830	typedef enum PDMAPICIRQ
1831	{
1832	/** Invalid 0 entry. */
1833	PDMAPICIRQ_INVALID = 0,
1834	/** Normal hardware interrupt. */
1835	PDMAPICIRQ_HARDWARE,
1836	/** NMI. */
1837	PDMAPICIRQ_NMI,
1838	/** SMI. */
1839	PDMAPICIRQ_SMI,
1840	/** ExtINT (HW interrupt via PIC). */
1841	PDMAPICIRQ_EXTINT,
1842	/** Interrupt arrived, needs to be updated to the IRR. */
1843	PDMAPICIRQ_UPDATE_PENDING,
1844	/** The usual 32-bit paranoia. */
1845	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1846	} PDMAPICIRQ;
1847
1848
1849	/**
1850	* I/O APIC registration structure (all contexts).
1851	*/
1852	typedef struct PDMIOAPICREG
1853	{
1854	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1855	uint32_t u32Version;
1856
1857	/**
1858	* Set an IRQ.
1859	*
1860	* @param pDevIns Device instance of the I/O APIC.
1861	* @param uBusDevFn The bus:device:function of the device initiating the
1862	* IRQ. Can be NIL_PCIBDF.
1863	* @param iIrq IRQ number to set.
1864	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1865	* @param uTagSrc The IRQ tag and source (for tracing).
1866	*
1867	* @remarks Caller enters the PDM critical section
1868	* Actually, as per 2018-07-21 this isn't true (bird).
1869	*/
1870	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1871
1872	/**
1873	* Send a MSI.
1874	*
1875	* @param pDevIns Device instance of the I/O APIC.
1876	* @param uBusDevFn The bus:device:function of the device initiating the
1877	* MSI. Cannot be NIL_PCIBDF.
1878	* @param pMsi The MSI to send.
1879	* @param uTagSrc The IRQ tag and source (for tracing).
1880	*
1881	* @remarks Caller enters the PDM critical section
1882	* Actually, as per 2018-07-21 this isn't true (bird).
1883	*/
1884	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1885
1886	/**
1887	* Set the EOI for an interrupt vector.
1888	*
1889	* @param pDevIns Device instance of the I/O APIC.
1890	* @param u8Vector The vector.
1891	*
1892	* @remarks Caller enters the PDM critical section
1893	* Actually, as per 2018-07-21 this isn't true (bird).
1894	*/
1895	DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1896
1897	/** Just a safety precaution. */
1898	uint32_t u32TheEnd;
1899	} PDMIOAPICREG;
1900	/** Pointer to an APIC registration structure. */
1901	typedef PDMIOAPICREG *PPDMIOAPICREG;
1902
1903	/** Current PDMAPICREG version number. */
1904	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1905
1906
1907	/**
1908	* IOAPIC helpers, same in all contexts.
1909	*/
1910	typedef struct PDMIOAPICHLP
1911	{
1912	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1913	uint32_t u32Version;
1914
1915	/**
1916	* Private interface between the IOAPIC and APIC.
1917	*
1918	* @returns status code.
1919	* @param pDevIns Device instance of the IOAPIC.
1920	* @param u8Dest See APIC implementation.
1921	* @param u8DestMode See APIC implementation.
1922	* @param u8DeliveryMode See APIC implementation.
1923	* @param uVector See APIC implementation.
1924	* @param u8Polarity See APIC implementation.
1925	* @param u8TriggerMode See APIC implementation.
1926	* @param uTagSrc The IRQ tag and source (for tracing).
1927	*
1928	* @sa APICBusDeliver()
1929	*/
1930	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1931	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1932
1933	/**
1934	* Acquires the PDM lock.
1935	*
1936	* @returns VINF_SUCCESS on success.
1937	* @returns rc if we failed to acquire the lock.
1938	* @param pDevIns The IOAPIC device instance.
1939	* @param rc What to return if we fail to acquire the lock.
1940	*
1941	* @sa PDMCritSectEnter
1942	*/
1943	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1944
1945	/**
1946	* Releases the PDM lock.
1947	*
1948	* @param pDevIns The IOAPIC device instance.
1949	*/
1950	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1951
1952	/**
1953	* Checks if the calling thread owns the PDM lock.
1954	*
1955	* @param pDevIns The IOAPIC device instance.
1956	*/
1957	DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1958
1959	/**
1960	* Private interface between the IOAPIC and IOMMU.
1961	*
1962	* @returns status code.
1963	* @param pDevIns Device instance of the IOAPIC.
1964	* @param idDevice The device identifier (bus, device, function).
1965	* @param pMsiIn The source MSI.
1966	* @param pMsiOut Where to store the remapped MSI (only updated when
1967	* VINF_SUCCESS is returned).
1968	*/
1969	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1970
1971	/** Just a safety precaution. */
1972	uint32_t u32TheEnd;
1973	} PDMIOAPICHLP;
1974	/** Pointer to IOAPIC helpers. */
1975	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1976	/** Pointer to const IOAPIC helpers. */
1977	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1978
1979	/** Current PDMIOAPICHLP version number. */
1980	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1981
1982
1983	/**
1984	* HPET registration structure.
1985	*/
1986	typedef struct PDMHPETREG
1987	{
1988	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1989	uint32_t u32Version;
1990	} PDMHPETREG;
1991	/** Pointer to an HPET registration structure. */
1992	typedef PDMHPETREG *PPDMHPETREG;
1993
1994	/** Current PDMHPETREG version number. */
1995	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1996
1997	/**
1998	* HPET RC helpers.
1999	*
2000	* @remarks Keep this around in case HPET will need PDM interaction in again RC
2001	* at some later point.
2002	*/
2003	typedef struct PDMHPETHLPRC
2004	{
2005	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
2006	uint32_t u32Version;
2007
2008	/** Just a safety precaution. */
2009	uint32_t u32TheEnd;
2010	} PDMHPETHLPRC;
2011
2012	/** Pointer to HPET RC helpers. */
2013	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
2014	/** Pointer to const HPET RC helpers. */
2015	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
2016
2017	/** Current PDMHPETHLPRC version number. */
2018	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
2019
2020
2021	/**
2022	* HPET R0 helpers.
2023	*
2024	* @remarks Keep this around in case HPET will need PDM interaction in again R0
2025	* at some later point.
2026	*/
2027	typedef struct PDMHPETHLPR0
2028	{
2029	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2030	uint32_t u32Version;
2031
2032	/** Just a safety precaution. */
2033	uint32_t u32TheEnd;
2034	} PDMHPETHLPR0;
2035
2036	/** Pointer to HPET R0 helpers. */
2037	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2038	/** Pointer to const HPET R0 helpers. */
2039	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2040
2041	/** Current PDMHPETHLPR0 version number. */
2042	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2043
2044	/**
2045	* HPET R3 helpers.
2046	*/
2047	typedef struct PDMHPETHLPR3
2048	{
2049	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2050	uint32_t u32Version;
2051
2052	/**
2053	* Set legacy mode on PIT and RTC.
2054	*
2055	* @returns VINF_SUCCESS on success.
2056	* @returns rc if we failed to set legacy mode.
2057	* @param pDevIns Device instance of the HPET.
2058	* @param fActivated Whether legacy mode is activated or deactivated.
2059	*/
2060	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2061
2062
2063	/**
2064	* Set IRQ, bypassing ISA bus override rules.
2065	*
2066	* @returns VINF_SUCCESS on success.
2067	* @returns rc if we failed to set legacy mode.
2068	* @param pDevIns Device instance of the HPET.
2069	* @param iIrq IRQ number to set.
2070	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2071	*/
2072	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2073
2074	/** Just a safety precaution. */
2075	uint32_t u32TheEnd;
2076	} PDMHPETHLPR3;
2077
2078	/** Pointer to HPET R3 helpers. */
2079	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2080	/** Pointer to const HPET R3 helpers. */
2081	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2082
2083	/** Current PDMHPETHLPR3 version number. */
2084	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2085
2086
2087	/**
2088	* Raw PCI device registration structure.
2089	*/
2090	typedef struct PDMPCIRAWREG
2091	{
2092	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2093	uint32_t u32Version;
2094	/** Just a safety precaution. */
2095	uint32_t u32TheEnd;
2096	} PDMPCIRAWREG;
2097	/** Pointer to a raw PCI registration structure. */
2098	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2099
2100	/** Current PDMPCIRAWREG version number. */
2101	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2102
2103	/**
2104	* Raw PCI device raw-mode context helpers.
2105	*/
2106	typedef struct PDMPCIRAWHLPRC
2107	{
2108	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2109	uint32_t u32Version;
2110	/** Just a safety precaution. */
2111	uint32_t u32TheEnd;
2112	} PDMPCIRAWHLPRC;
2113	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2114	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2115	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2116	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2117
2118	/** Current PDMPCIRAWHLPRC version number. */
2119	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2120
2121	/**
2122	* Raw PCI device ring-0 context helpers.
2123	*/
2124	typedef struct PDMPCIRAWHLPR0
2125	{
2126	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2127	uint32_t u32Version;
2128	/** Just a safety precaution. */
2129	uint32_t u32TheEnd;
2130	} PDMPCIRAWHLPR0;
2131	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2132	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2133	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2134	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2135
2136	/** Current PDMPCIRAWHLPR0 version number. */
2137	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2138
2139
2140	/**
2141	* Raw PCI device ring-3 context helpers.
2142	*/
2143	typedef struct PDMPCIRAWHLPR3
2144	{
2145	/** Undefined structure version and magic number. */
2146	uint32_t u32Version;
2147
2148	/**
2149	* Gets the address of the RC raw PCI device helpers.
2150	*
2151	* This should be called at both construction and relocation time to obtain
2152	* the correct address of the RC helpers.
2153	*
2154	* @returns RC pointer to the raw PCI device helpers.
2155	* @param pDevIns Device instance of the raw PCI device.
2156	*/
2157	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2158
2159	/**
2160	* Gets the address of the R0 raw PCI device helpers.
2161	*
2162	* This should be called at both construction and relocation time to obtain
2163	* the correct address of the R0 helpers.
2164	*
2165	* @returns R0 pointer to the raw PCI device helpers.
2166	* @param pDevIns Device instance of the raw PCI device.
2167	*/
2168	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2169
2170	/** Just a safety precaution. */
2171	uint32_t u32TheEnd;
2172	} PDMPCIRAWHLPR3;
2173	/** Pointer to raw PCI R3 helpers. */
2174	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2175	/** Pointer to const raw PCI R3 helpers. */
2176	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2177
2178	/** Current PDMPCIRAWHLPR3 version number. */
2179	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2180
2181
2182	#ifdef IN_RING3
2183
2184	/**
2185	* DMA Transfer Handler.
2186	*
2187	* @returns Number of bytes transferred.
2188	* @param pDevIns The device instance that registered the handler.
2189	* @param pvUser User pointer.
2190	* @param uChannel Channel number.
2191	* @param off DMA position.
2192	* @param cb Block size.
2193	* @remarks The device lock is take before the callback (in fact, the locks of
2194	* DMA devices and the DMA controller itself are taken).
2195	*/
2196	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2197	uint32_t off, uint32_t cb));
2198	/** Pointer to a FNDMATRANSFERHANDLER(). */
2199	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2200
2201	/**
2202	* DMA Controller registration structure.
2203	*/
2204	typedef struct PDMDMAREG
2205	{
2206	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2207	uint32_t u32Version;
2208
2209	/**
2210	* Execute pending transfers.
2211	*
2212	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2213	* @param pDevIns Device instance of the DMAC.
2214	* @remarks No locks held, called on EMT(0) as a form of serialization.
2215	*/
2216	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2217
2218	/**
2219	* Register transfer function for DMA channel.
2220	*
2221	* @param pDevIns Device instance of the DMAC.
2222	* @param uChannel Channel number.
2223	* @param pDevInsHandler The device instance of the device making the
2224	* regstration (will be passed to the callback).
2225	* @param pfnTransferHandler Device specific transfer function.
2226	* @param pvUser User pointer to be passed to the callback.
2227	* @remarks No locks held, called on an EMT.
2228	*/
2229	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2230	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2231
2232	/**
2233	* Read memory
2234	*
2235	* @returns Number of bytes read.
2236	* @param pDevIns Device instance of the DMAC.
2237	* @param uChannel Channel number.
2238	* @param pvBuffer Pointer to target buffer.
2239	* @param off DMA position.
2240	* @param cbBlock Block size.
2241	* @remarks No locks held, called on an EMT.
2242	*/
2243	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2244
2245	/**
2246	* Write memory
2247	*
2248	* @returns Number of bytes written.
2249	* @param pDevIns Device instance of the DMAC.
2250	* @param uChannel Channel number.
2251	* @param pvBuffer Memory to write.
2252	* @param off DMA position.
2253	* @param cbBlock Block size.
2254	* @remarks No locks held, called on an EMT.
2255	*/
2256	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2257
2258	/**
2259	* Set the DREQ line.
2260	*
2261	* @param pDevIns Device instance of the DMAC.
2262	* @param uChannel Channel number.
2263	* @param uLevel Level of the line.
2264	* @remarks No locks held, called on an EMT.
2265	*/
2266	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2267
2268	/**
2269	* Get channel mode
2270	*
2271	* @returns Channel mode.
2272	* @param pDevIns Device instance of the DMAC.
2273	* @param uChannel Channel number.
2274	* @remarks No locks held, called on an EMT.
2275	*/
2276	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2277
2278	} PDMDMACREG;
2279	/** Pointer to a DMAC registration structure. */
2280	typedef PDMDMACREG *PPDMDMACREG;
2281
2282	/** Current PDMDMACREG version number. */
2283	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2284
2285
2286	/**
2287	* DMA Controller device helpers.
2288	*/
2289	typedef struct PDMDMACHLP
2290	{
2291	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2292	uint32_t u32Version;
2293
2294	/* to-be-defined */
2295
2296	} PDMDMACHLP;
2297	/** Pointer to DMAC helpers. */
2298	typedef PDMDMACHLP *PPDMDMACHLP;
2299	/** Pointer to const DMAC helpers. */
2300	typedef const PDMDMACHLP *PCPDMDMACHLP;
2301
2302	/** Current PDMDMACHLP version number. */
2303	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2304
2305	#endif /* IN_RING3 */
2306
2307
2308
2309	/**
2310	* RTC registration structure.
2311	*/
2312	typedef struct PDMRTCREG
2313	{
2314	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2315	uint32_t u32Version;
2316	uint32_t u32Alignment; /*< structure size alignment. /
2317
2318	/**
2319	* Write to a CMOS register and update the checksum if necessary.
2320	*
2321	* @returns VBox status code.
2322	* @param pDevIns Device instance of the RTC.
2323	* @param iReg The CMOS register index.
2324	* @param u8Value The CMOS register value.
2325	* @remarks Caller enters the device critical section.
2326	*/
2327	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2328
2329	/**
2330	* Read a CMOS register.
2331	*
2332	* @returns VBox status code.
2333	* @param pDevIns Device instance of the RTC.
2334	* @param iReg The CMOS register index.
2335	* @param pu8Value Where to store the CMOS register value.
2336	* @remarks Caller enters the device critical section.
2337	*/
2338	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2339
2340	} PDMRTCREG;
2341	/** Pointer to a RTC registration structure. */
2342	typedef PDMRTCREG *PPDMRTCREG;
2343	/** Pointer to a const RTC registration structure. */
2344	typedef const PDMRTCREG *PCPDMRTCREG;
2345
2346	/** Current PDMRTCREG version number. */
2347	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2348
2349
2350	/**
2351	* RTC device helpers.
2352	*/
2353	typedef struct PDMRTCHLP
2354	{
2355	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2356	uint32_t u32Version;
2357
2358	/* to-be-defined */
2359
2360	} PDMRTCHLP;
2361	/** Pointer to RTC helpers. */
2362	typedef PDMRTCHLP *PPDMRTCHLP;
2363	/** Pointer to const RTC helpers. */
2364	typedef const PDMRTCHLP *PCPDMRTCHLP;
2365
2366	/** Current PDMRTCHLP version number. */
2367	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2368
2369
2370
2371	/** @name Flags for PCI I/O region registration
2372	* @{ */
2373	/** No handle is passed. */
2374	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2375	/** An I/O port handle is passed. */
2376	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2377	/** An MMIO range handle is passed. */
2378	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2379	/** An MMIO2 handle is passed. */
2380	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2381	/** Handle type mask. */
2382	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2383	/** New-style (mostly wrt callbacks). */
2384	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2385	/** Mask of valid flags. */
2386	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2387	/** @} */
2388
2389
2390	/** @name Flags for the guest physical read/write helpers
2391	* @{ */
2392	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2393	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2394	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2395	* by the device in any way. */
2396	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2397	/** The data is metadata and being processed by the device in some way. */
2398	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2399	/** @} */
2400
2401
2402	#ifdef IN_RING3
2403
2404	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2405	* @{ */
2406	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2407	* This is handy when registering multiple PCI device functions and the device
2408	* number is left up to the PCI bus. In order to facilitate one PDM device
2409	* instance for each PCI function, this searches earlier PDM device
2410	* instances as well. */
2411	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2412	/** Use the first unused device number (all functions must be unused). */
2413	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2414	/** Use the first unused device function. */
2415	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2416
2417	/** The device and function numbers are not mandatory, just suggestions. */
2418	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2419	/** Registering a PCI bridge device. */
2420	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2421	/** Valid flag mask. */
2422	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2423	/** @} */
2424
2425	/** Current PDMDEVHLPR3 version number. */
2426	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 56, 0)
2427
2428	/**
2429	* PDM Device API.
2430	*/
2431	typedef struct PDMDEVHLPR3
2432	{
2433	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2434	uint32_t u32Version;
2435
2436	/** @name I/O ports
2437	* @{ */
2438	/**
2439	* Creates a range of I/O ports for a device.
2440	*
2441	* The I/O port range must be mapped in a separately call. Any ring-0 and
2442	* raw-mode context callback handlers needs to be set up in the respective
2443	* contexts.
2444	*
2445	* @returns VBox status.
2446	* @param pDevIns The device instance to register the ports with.
2447	* @param cPorts Number of ports to register.
2448	* @param fFlags IOM_IOPORT_F_XXX.
2449	* @param pPciDev The PCI device the range is associated with, if
2450	* applicable.
2451	* @param iPciRegion The PCI device region in the high 16-bit word and
2452	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2453	* @param pfnOut Pointer to function which is gonna handle OUT
2454	* operations. Optional.
2455	* @param pfnIn Pointer to function which is gonna handle IN operations.
2456	* Optional.
2457	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2458	* operations. Optional.
2459	* @param pfnInStr Pointer to function which is gonna handle string IN
2460	* operations. Optional.
2461	* @param pvUser User argument to pass to the callbacks.
2462	* @param pszDesc Pointer to description string. This must not be freed.
2463	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2464	* coverage is allowed. This must not be freed.
2465	* @param phIoPorts Where to return the I/O port range handle.
2466	*
2467	* @remarks Caller enters the device critical section prior to invoking the
2468	* registered callback methods.
2469	*
2470	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2471	* PDMDevHlpIoPortUnmap.
2472	*/
2473	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2474	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2475	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2476	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2477
2478	/**
2479	* Maps an I/O port range.
2480	*
2481	* @returns VBox status.
2482	* @param pDevIns The device instance to register the ports with.
2483	* @param hIoPorts The I/O port range handle.
2484	* @param Port Where to map the range.
2485	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2486	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2487	*/
2488	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2489
2490	/**
2491	* Unmaps an I/O port range.
2492	*
2493	* @returns VBox status.
2494	* @param pDevIns The device instance to register the ports with.
2495	* @param hIoPorts The I/O port range handle.
2496	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2497	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2498	*/
2499	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2500
2501	/**
2502	* Gets the mapping address of the I/O port range @a hIoPorts.
2503	*
2504	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2505	* parameters).
2506	* @param pDevIns The device instance to register the ports with.
2507	* @param hIoPorts The I/O port range handle.
2508	*/
2509	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2510	/** @} */
2511
2512	/** @name MMIO
2513	* @{ */
2514	/**
2515	* Creates a memory mapped I/O (MMIO) region for a device.
2516	*
2517	* The MMIO region must be mapped in a separately call. Any ring-0 and
2518	* raw-mode context callback handlers needs to be set up in the respective
2519	* contexts.
2520	*
2521	* @returns VBox status.
2522	* @param pDevIns The device instance to register the ports with.
2523	* @param cbRegion The size of the region in bytes.
2524	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2525	* @param pPciDev The PCI device the range is associated with, if
2526	* applicable.
2527	* @param iPciRegion The PCI device region in the high 16-bit word and
2528	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2529	* @param pfnWrite Pointer to function which is gonna handle Write
2530	* operations.
2531	* @param pfnRead Pointer to function which is gonna handle Read
2532	* operations.
2533	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2534	* operations. (optional)
2535	* @param pvUser User argument to pass to the callbacks.
2536	* @param pszDesc Pointer to description string. This must not be freed.
2537	* @param phRegion Where to return the MMIO region handle.
2538	*
2539	* @remarks Caller enters the device critical section prior to invoking the
2540	* registered callback methods.
2541	*
2542	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2543	*/
2544	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2545	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2546	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2547	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2548
2549	/**
2550	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2551	*
2552	* @returns VBox status.
2553	* @param pDevIns The device instance the region is associated with.
2554	* @param hRegion The MMIO region handle.
2555	* @param GCPhys Where to map the region.
2556	* @note An MMIO range may overlap with base memory if a lot of RAM is
2557	* configured for the VM, in which case we'll drop the base memory
2558	* pages. Presently we will make no attempt to preserve anything that
2559	* happens to be present in the base memory that is replaced, this is
2560	* technically incorrect but it's just not worth the effort to do
2561	* right, at least not at this point.
2562	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2563	* PDMDevHlpMmioSetUpContext
2564	*/
2565	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2566
2567	/**
2568	* Unmaps a memory mapped I/O (MMIO) region.
2569	*
2570	* @returns VBox status.
2571	* @param pDevIns The device instance the region is associated with.
2572	* @param hRegion The MMIO region handle.
2573	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2574	* PDMDevHlpMmioSetUpContext
2575	*/
2576	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2577
2578	/**
2579	* Reduces the length of a MMIO range.
2580	*
2581	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2582	* only work during saved state restore. It will not call the PCI bus code, as
2583	* that is expected to restore the saved resource configuration.
2584	*
2585	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2586	* called it will only map @a cbRegion bytes and not the value set during
2587	* registration.
2588	*
2589	* @return VBox status code.
2590	* @param pDevIns The device owning the range.
2591	* @param hRegion The MMIO region handle.
2592	* @param cbRegion The new size, must be smaller.
2593	*/
2594	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2595
2596	/**
2597	* Gets the mapping address of the MMIO region @a hRegion.
2598	*
2599	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2600	* @param pDevIns The device instance to register the ports with.
2601	* @param hRegion The MMIO region handle.
2602	*/
2603	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2604	/** @} */
2605
2606	/** @name MMIO2
2607	* @{ */
2608	/**
2609	* Creates a MMIO2 region.
2610	*
2611	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2612	* associated with a device. It is also non-shared memory with a permanent
2613	* ring-3 mapping and page backing (presently).
2614	*
2615	* @returns VBox status.
2616	* @param pDevIns The device instance.
2617	* @param pPciDev The PCI device the region is associated with, or
2618	* NULL if no PCI device association.
2619	* @param iPciRegion The region number. Use the PCI region number as
2620	* this must be known to the PCI bus device too. If
2621	* it's not associated with the PCI device, then
2622	* any number up to UINT8_MAX is fine.
2623	* @param cbRegion The size (in bytes) of the region.
2624	* @param fFlags Reserved for future use, must be zero.
2625	* @param pszDesc Pointer to description string. This must not be
2626	* freed.
2627	* @param ppvMapping Where to store the address of the ring-3 mapping
2628	* of the memory.
2629	* @param phRegion Where to return the MMIO2 region handle.
2630	*
2631	* @thread EMT(0)
2632	*/
2633	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2634	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2635
2636	/**
2637	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2638	*
2639	* Any physical access handlers registered for the region must be deregistered
2640	* before calling this function.
2641	*
2642	* @returns VBox status code.
2643	* @param pDevIns The device instance.
2644	* @param hRegion The MMIO2 region handle.
2645	* @thread EMT.
2646	*/
2647	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2648
2649	/**
2650	* Maps a MMIO2 region (into the guest physical address space).
2651	*
2652	* @returns VBox status.
2653	* @param pDevIns The device instance the region is associated with.
2654	* @param hRegion The MMIO2 region handle.
2655	* @param GCPhys Where to map the region.
2656	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2657	* configured for the VM, in which case we'll drop the base memory
2658	* pages. Presently we will make no attempt to preserve anything that
2659	* happens to be present in the base memory that is replaced, this is
2660	* technically incorrect but it's just not worth the effort to do
2661	* right, at least not at this point.
2662	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2663	*/
2664	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2665
2666	/**
2667	* Unmaps a MMIO2 region.
2668	*
2669	* @returns VBox status.
2670	* @param pDevIns The device instance the region is associated with.
2671	* @param hRegion The MMIO2 region handle.
2672	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2673	*/
2674	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2675
2676	/**
2677	* Reduces the length of a MMIO range.
2678	*
2679	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2680	* only work during saved state restore. It will not call the PCI bus code, as
2681	* that is expected to restore the saved resource configuration.
2682	*
2683	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2684	* called it will only map @a cbRegion bytes and not the value set during
2685	* registration.
2686	*
2687	* @return VBox status code.
2688	* @param pDevIns The device owning the range.
2689	* @param hRegion The MMIO2 region handle.
2690	* @param cbRegion The new size, must be smaller.
2691	*/
2692	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2693
2694	/**
2695	* Gets the mapping address of the MMIO region @a hRegion.
2696	*
2697	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2698	* @param pDevIns The device instance to register the ports with.
2699	* @param hRegion The MMIO2 region handle.
2700	*/
2701	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2702
2703	/**
2704	* Changes the number of an MMIO2 or pre-registered MMIO region.
2705	*
2706	* This should only be used to deal with saved state problems, so there is no
2707	* convenience inline wrapper for this method.
2708	*
2709	* @returns VBox status code.
2710	* @param pDevIns The device instance.
2711	* @param hRegion The MMIO2 region handle.
2712	* @param iNewRegion The new region index.
2713	*
2714	* @sa @bugref{9359}
2715	*/
2716	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2717
2718	/**
2719	* Mapping an MMIO2 page in place of an MMIO page for direct access.
2720	*
2721	* This is a special optimization used by the VGA device. Call
2722	* PDMDevHlpMmioResetRegion() to undo the mapping.
2723	*
2724	* @returns VBox status code. This API may return VINF_SUCCESS even if no
2725	* remapping is made.
2726	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
2727	*
2728	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
2729	* associated with.
2730	* @param hRegion The handle to the MMIO region.
2731	* @param offRegion The offset into @a hRegion of the page to be
2732	* remapped.
2733	* @param hMmio2 The MMIO2 handle.
2734	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
2735	* mapping.
2736	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
2737	* for the time being.
2738	*/
2739	DECLR3CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
2740	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
2741
2742	/**
2743	* Reset a previously modified MMIO region; restore the access flags.
2744	*
2745	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
2746	* intended for some ancient VGA hack. However, it would be great to extend it
2747	* beyond VT-x and/or nested-paging.
2748	*
2749	* @returns VBox status code.
2750	*
2751	* @param pDevIns The device instance @a hRegion is associated with.
2752	* @param hRegion The handle to the MMIO region.
2753	*/
2754	DECLR3CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2755	/** @} */
2756
2757	/**
2758	* Register a ROM (BIOS) region.
2759	*
2760	* It goes without saying that this is read-only memory. The memory region must be
2761	* in unassigned memory. I.e. from the top of the address space or on the PC in
2762	* the 0xa0000-0xfffff range.
2763	*
2764	* @returns VBox status.
2765	* @param pDevIns The device instance owning the ROM region.
2766	* @param GCPhysStart First physical address in the range.
2767	* Must be page aligned!
2768	* @param cbRange The size of the range (in bytes).
2769	* Must be page aligned!
2770	* @param pvBinary Pointer to the binary data backing the ROM image.
2771	* @param cbBinary The size of the binary pointer. This must
2772	* be equal or smaller than @a cbRange.
2773	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2774	* @param pszDesc Pointer to description string. This must not be freed.
2775	*
2776	* @remark There is no way to remove the rom, automatically on device cleanup or
2777	* manually from the device yet. At present I doubt we need such features...
2778	*/
2779	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2780	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2781
2782	/**
2783	* Changes the protection of shadowed ROM mapping.
2784	*
2785	* This is intented for use by the system BIOS, chipset or device in question to
2786	* change the protection of shadowed ROM code after init and on reset.
2787	*
2788	* @param pDevIns The device instance.
2789	* @param GCPhysStart Where the mapping starts.
2790	* @param cbRange The size of the mapping.
2791	* @param enmProt The new protection type.
2792	*/
2793	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2794
2795	/**
2796	* Register a save state data unit.
2797	*
2798	* @returns VBox status.
2799	* @param pDevIns The device instance.
2800	* @param uVersion Data layout version number.
2801	* @param cbGuess The approximate amount of data in the unit.
2802	* Only for progress indicators.
2803	* @param pszBefore Name of data unit which we should be put in
2804	* front of. Optional (NULL).
2805	*
2806	* @param pfnLivePrep Prepare live save callback, optional.
2807	* @param pfnLiveExec Execute live save callback, optional.
2808	* @param pfnLiveVote Vote live save callback, optional.
2809	*
2810	* @param pfnSavePrep Prepare save callback, optional.
2811	* @param pfnSaveExec Execute save callback, optional.
2812	* @param pfnSaveDone Done save callback, optional.
2813	*
2814	* @param pfnLoadPrep Prepare load callback, optional.
2815	* @param pfnLoadExec Execute load callback, optional.
2816	* @param pfnLoadDone Done load callback, optional.
2817	* @remarks Caller enters the device critical section prior to invoking the
2818	* registered callback methods.
2819	*/
2820	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2821	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2822	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2823	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2824
2825	/** @name Exported SSM Functions
2826	* @{ */
2827	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2828	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2829	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2830	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2831	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2832	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2833	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2834	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2835	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2836	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2837	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2838	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2839	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2840	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2841	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2842	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2843	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2844	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2845	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2846	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2847	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2848	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2849	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2850	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2851	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2852	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2853	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2854	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2855	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2856	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2857	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2858	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2859	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2860	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2861	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2862	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2863	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2864	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2865	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2866	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2867	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2868	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2869	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2870	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2871	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2872	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2873	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2874	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2875	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2876	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2877	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2878	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2879	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2880	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2881	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2882	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2883	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2884	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2885	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2886	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2887	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2888	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2889	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2890	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2891	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2892	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2893	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2894	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2895	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2896	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2897	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2898	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2899	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2900	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2901	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2902	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2903	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2904	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2905	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2906	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2907	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2908	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2909	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2910	/** @} */
2911
2912	/**
2913	* Creates a timer w/ a cross context handle.
2914	*
2915	* @returns VBox status.
2916	* @param pDevIns The device instance.
2917	* @param enmClock The clock to use on this timer.
2918	* @param pfnCallback Callback function.
2919	* @param pvUser User argument for the callback.
2920	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2921	* @param pszDesc Pointer to description string which must stay around
2922	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2923	* @param phTimer Where to store the timer handle on success.
2924	* @remarks Caller enters the device critical section prior to invoking the
2925	* callback.
2926	*/
2927	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2928	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
2929
2930	/** @name Timer handle method wrappers
2931	* @{ */
2932	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2933	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2934	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2935	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2936	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2937	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2938	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2939	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2940	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2941	/** Takes the clock lock then enters the specified critical section. */
2942	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2943	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2944	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2945	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2946	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2947	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2948	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2949	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2950	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2951	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2952	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2953	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2954	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2955	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2956	/** @sa TMR3TimerSkip */
2957	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2958	/** @} */
2959
2960	/**
2961	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2962	*
2963	* @returns pTime.
2964	* @param pDevIns The device instance.
2965	* @param pTime Where to store the time.
2966	*/
2967	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2968
2969	/** @name Exported CFGM Functions.
2970	* @{ */
2971	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2972	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2973	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
2974	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2975	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2976	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
2977	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
2978	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
2979	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2980	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2981	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
2982	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
2983	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
2984	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
2985	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
2986	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
2987	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
2988	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
2989	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
2990	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
2991	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
2992	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
2993	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
2994	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
2995	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
2996	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
2997	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2998	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2999	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
3000	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
3001	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
3002	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
3003	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
3004	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
3005	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
3006	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
3007	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
3008	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
3009	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
3010	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
3011	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
3012	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
3013	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
3014	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
3015	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
3016	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
3017	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
3018	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
3019	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
3020	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
3021	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
3022	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
3023	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
3024	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
3025	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
3026	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
3027	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
3028	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
3029	const char pszValidValues, const char pszValidNodes,
3030	const char *pszWho, uint32_t uInstance));
3031	/** @} */
3032
3033	/**
3034	* Read physical memory.
3035	*
3036	* @returns VINF_SUCCESS (for now).
3037	* @param pDevIns The device instance.
3038	* @param GCPhys Physical address start reading from.
3039	* @param pvBuf Where to put the read bits.
3040	* @param cbRead How many bytes to read.
3041	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3042	* @thread Any thread, but the call may involve the emulation thread.
3043	*/
3044	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3045
3046	/**
3047	* Write to physical memory.
3048	*
3049	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3050	* @param pDevIns The device instance.
3051	* @param GCPhys Physical address to write to.
3052	* @param pvBuf What to write.
3053	* @param cbWrite How many bytes to write.
3054	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3055	* @thread Any thread, but the call may involve the emulation thread.
3056	*/
3057	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3058
3059	/**
3060	* Requests the mapping of a guest page into ring-3.
3061	*
3062	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3063	* release it.
3064	*
3065	* This API will assume your intention is to write to the page, and will
3066	* therefore replace shared and zero pages. If you do not intend to modify the
3067	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3068	*
3069	* @returns VBox status code.
3070	* @retval VINF_SUCCESS on success.
3071	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3072	* backing or if the page has any active access handlers. The caller
3073	* must fall back on using PGMR3PhysWriteExternal.
3074	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3075	*
3076	* @param pDevIns The device instance.
3077	* @param GCPhys The guest physical address of the page that
3078	* should be mapped.
3079	* @param fFlags Flags reserved for future use, MBZ.
3080	* @param ppv Where to store the address corresponding to
3081	* GCPhys.
3082	* @param pLock Where to store the lock information that
3083	* pfnPhysReleasePageMappingLock needs.
3084	*
3085	* @remark Avoid calling this API from within critical sections (other than the
3086	* PGM one) because of the deadlock risk when we have to delegating the
3087	* task to an EMT.
3088	* @thread Any.
3089	*/
3090	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3091	PPGMPAGEMAPLOCK pLock));
3092
3093	/**
3094	* Requests the mapping of a guest page into ring-3, external threads.
3095	*
3096	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3097	* release it.
3098	*
3099	* @returns VBox status code.
3100	* @retval VINF_SUCCESS on success.
3101	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3102	* backing or if the page as an active ALL access handler. The caller
3103	* must fall back on using PGMPhysRead.
3104	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3105	*
3106	* @param pDevIns The device instance.
3107	* @param GCPhys The guest physical address of the page that
3108	* should be mapped.
3109	* @param fFlags Flags reserved for future use, MBZ.
3110	* @param ppv Where to store the address corresponding to
3111	* GCPhys.
3112	* @param pLock Where to store the lock information that
3113	* pfnPhysReleasePageMappingLock needs.
3114	*
3115	* @remark Avoid calling this API from within critical sections.
3116	* @thread Any.
3117	*/
3118	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3119	void const **ppv, PPGMPAGEMAPLOCK pLock));
3120
3121	/**
3122	* Release the mapping of a guest page.
3123	*
3124	* This is the counter part of pfnPhysGCPhys2CCPtr and
3125	* pfnPhysGCPhys2CCPtrReadOnly.
3126	*
3127	* @param pDevIns The device instance.
3128	* @param pLock The lock structure initialized by the mapping
3129	* function.
3130	*/
3131	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3132
3133	/**
3134	* Read guest physical memory by virtual address.
3135	*
3136	* @param pDevIns The device instance.
3137	* @param pvDst Where to put the read bits.
3138	* @param GCVirtSrc Guest virtual address to start reading from.
3139	* @param cb How many bytes to read.
3140	* @thread The emulation thread.
3141	*/
3142	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3143
3144	/**
3145	* Write to guest physical memory by virtual address.
3146	*
3147	* @param pDevIns The device instance.
3148	* @param GCVirtDst Guest virtual address to write to.
3149	* @param pvSrc What to write.
3150	* @param cb How many bytes to write.
3151	* @thread The emulation thread.
3152	*/
3153	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3154
3155	/**
3156	* Convert a guest virtual address to a guest physical address.
3157	*
3158	* @returns VBox status code.
3159	* @param pDevIns The device instance.
3160	* @param GCPtr Guest virtual address.
3161	* @param pGCPhys Where to store the GC physical address
3162	* corresponding to GCPtr.
3163	* @thread The emulation thread.
3164	* @remark Careful with page boundaries.
3165	*/
3166	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3167
3168	/**
3169	* Checks if a GC physical address is a normal page,
3170	* i.e. not ROM, MMIO or reserved.
3171	*
3172	* @returns true if normal.
3173	* @returns false if invalid, ROM, MMIO or reserved page.
3174	* @param pDevIns The device instance.
3175	* @param GCPhys The physical address to check.
3176	*/
3177	DECLR3CALLBACKMEMBER(bool, pfnPhysIsGCPhysNormal,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
3178
3179	/**
3180	* Inflate or deflate a memory balloon
3181	*
3182	* @returns VBox status code.
3183	* @param pDevIns The device instance.
3184	* @param fInflate Inflate or deflate memory balloon
3185	* @param cPages Number of pages to free
3186	* @param paPhysPage Array of guest physical addresses
3187	*/
3188	DECLR3CALLBACKMEMBER(int, pfnPhysChangeMemBalloon,(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage));
3189
3190	/**
3191	* Allocate memory which is associated with current VM instance
3192	* and automatically freed on it's destruction.
3193	*
3194	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3195	* @param pDevIns The device instance.
3196	* @param cb Number of bytes to allocate.
3197	*/
3198	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3199
3200	/**
3201	* Allocate memory which is associated with current VM instance
3202	* and automatically freed on it's destruction. The memory is ZEROed.
3203	*
3204	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3205	* @param pDevIns The device instance.
3206	* @param cb Number of bytes to allocate.
3207	*/
3208	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3209
3210	/**
3211	* Allocating string printf.
3212	*
3213	* @returns Pointer to the string.
3214	* @param pDevIns The device instance.
3215	* @param enmTag The statistics tag.
3216	* @param pszFormat The format string.
3217	* @param va Format arguments.
3218	*/
3219	DECLR3CALLBACKMEMBER(char , pfnMMHeapAPrintfV,(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, va_list va));
3220
3221	/**
3222	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3223	*
3224	* @param pDevIns The device instance.
3225	* @param pv Pointer to the memory to free.
3226	*/
3227	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3228
3229	/**
3230	* Returns the physical RAM size of the VM.
3231	*
3232	* @returns RAM size in bytes.
3233	* @param pDevIns The device instance.
3234	*/
3235	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSize,(PPDMDEVINS pDevIns));
3236
3237	/**
3238	* Returns the physical RAM size of the VM below the 4GB boundary.
3239	*
3240	* @returns RAM size in bytes.
3241	* @param pDevIns The device instance.
3242	*/
3243	DECLR3CALLBACKMEMBER(uint32_t, pfnMMPhysGetRamSizeBelow4GB,(PPDMDEVINS pDevIns));
3244
3245	/**
3246	* Returns the physical RAM size of the VM above the 4GB boundary.
3247	*
3248	* @returns RAM size in bytes.
3249	* @param pDevIns The device instance.
3250	*/
3251	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSizeAbove4GB,(PPDMDEVINS pDevIns));
3252
3253	/**
3254	* Gets the VM state.
3255	*
3256	* @returns VM state.
3257	* @param pDevIns The device instance.
3258	* @thread Any thread (just keep in mind that it's volatile info).
3259	*/
3260	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3261
3262	/**
3263	* Checks if the VM was teleported and hasn't been fully resumed yet.
3264	*
3265	* @returns true / false.
3266	* @param pDevIns The device instance.
3267	* @thread Any thread.
3268	*/
3269	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3270
3271	/**
3272	* Set the VM error message
3273	*
3274	* @returns rc.
3275	* @param pDevIns The device instance.
3276	* @param rc VBox status code.
3277	* @param SRC_POS Use RT_SRC_POS.
3278	* @param pszFormat Error message format string.
3279	* @param va Error message arguments.
3280	*/
3281	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3282	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3283
3284	/**
3285	* Set the VM runtime error message
3286	*
3287	* @returns VBox status code.
3288	* @param pDevIns The device instance.
3289	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3290	* @param pszErrorId Error ID string.
3291	* @param pszFormat Error message format string.
3292	* @param va Error message arguments.
3293	*/
3294	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3295	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3296
3297	/**
3298	* Special interface for implementing a HLT-like port on a device.
3299	*
3300	* This can be called directly from device code, provide the device is trusted
3301	* to access the VMM directly. Since we may not have an accurate register set
3302	* and the caller certainly shouldn't (device code does not access CPU
3303	* registers), this function will return when interrupts are pending regardless
3304	* of the actual EFLAGS.IF state.
3305	*
3306	* @returns VBox error status (never informational statuses).
3307	* @param pDevIns The device instance.
3308	* @param idCpu The id of the calling EMT.
3309	*/
3310	DECLR3CALLBACKMEMBER(int, pfnVMWaitForDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3311
3312	/**
3313	* Wakes up a CPU that has called PDMDEVHLPR3::pfnVMWaitForDeviceReady.
3314	*
3315	* @returns VBox error status (never informational statuses).
3316	* @param pDevIns The device instance.
3317	* @param idCpu The id of the calling EMT.
3318	*/
3319	DECLR3CALLBACKMEMBER(int, pfnVMNotifyCpuDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3320
3321	/**
3322	* Convenience wrapper for VMR3ReqCallU.
3323	*
3324	* This assumes (1) you're calling a function that returns an VBox status code
3325	* and that you do not wish to wait for it to complete.
3326	*
3327	* @returns VBox status code returned by VMR3ReqCallVU.
3328	*
3329	* @param pDevIns The device instance.
3330	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3331	* one of the following special values:
3332	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3333	* @param pfnFunction Pointer to the function to call.
3334	* @param cArgs Number of arguments following in the ellipsis.
3335	* @param Args Argument vector.
3336	*
3337	* @remarks See remarks on VMR3ReqCallVU.
3338	*/
3339	DECLR3CALLBACKMEMBER(int, pfnVMReqCallNoWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3340
3341	/**
3342	* Convenience wrapper for VMR3ReqCallU.
3343	*
3344	* This assumes (1) you're calling a function that returns void, (2) that you
3345	* wish to wait for ever for it to return, and (3) that it's priority request
3346	* that can be safely be handled during async suspend and power off.
3347	*
3348	* @returns VBox status code of VMR3ReqCallVU.
3349	*
3350	* @param pDevIns The device instance.
3351	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3352	* one of the following special values:
3353	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3354	* @param pfnFunction Pointer to the function to call.
3355	* @param cArgs Number of arguments following in the ellipsis.
3356	* @param Args Argument vector.
3357	*
3358	* @remarks See remarks on VMR3ReqCallVU.
3359	*/
3360	DECLR3CALLBACKMEMBER(int, pfnVMReqPriorityCallWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3361
3362	/**
3363	* Stops the VM and enters the debugger to look at the guest state.
3364	*
3365	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3366	* invoking this function directly.
3367	*
3368	* @returns VBox status code which must be passed up to the VMM.
3369	* @param pDevIns The device instance.
3370	* @param pszFile Filename of the assertion location.
3371	* @param iLine The linenumber of the assertion location.
3372	* @param pszFunction Function of the assertion location.
3373	* @param pszFormat Message. (optional)
3374	* @param args Message parameters.
3375	*/
3376	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3377	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3378
3379	/**
3380	* Register a info handler with DBGF.
3381	*
3382	* @returns VBox status code.
3383	* @param pDevIns The device instance.
3384	* @param pszName The identifier of the info.
3385	* @param pszDesc The description of the info and any arguments
3386	* the handler may take.
3387	* @param pfnHandler The handler function to be called to display the
3388	* info.
3389	*/
3390	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3391
3392	/**
3393	* Register a info handler with DBGF, argv style.
3394	*
3395	* @returns VBox status code.
3396	* @param pDevIns The device instance.
3397	* @param pszName The identifier of the info.
3398	* @param pszDesc The description of the info and any arguments
3399	* the handler may take.
3400	* @param pfnHandler The handler function to be called to display the
3401	* info.
3402	*/
3403	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3404
3405	/**
3406	* Registers a set of registers for a device.
3407	*
3408	* The @a pvUser argument of the getter and setter callbacks will be
3409	* @a pDevIns. The register names will be prefixed by the device name followed
3410	* immediately by the instance number.
3411	*
3412	* @returns VBox status code.
3413	* @param pDevIns The device instance.
3414	* @param paRegisters The register descriptors.
3415	*
3416	* @remarks The device critical section is NOT entered prior to working the
3417	* callbacks registered via this helper!
3418	*/
3419	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3420
3421	/**
3422	* Gets the trace buffer handle.
3423	*
3424	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3425	* really inteded for direct usage, thus no inline wrapper function.
3426	*
3427	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3428	* @param pDevIns The device instance.
3429	*/
3430	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3431
3432	/**
3433	* Registers a statistics sample.
3434	*
3435	* @param pDevIns Device instance of the DMA.
3436	* @param pvSample Pointer to the sample.
3437	* @param enmType Sample type. This indicates what pvSample is
3438	* pointing at.
3439	* @param pszName Sample name, unix path style. If this does not
3440	* start with a '/', the default prefix will be
3441	* prepended, otherwise it will be used as-is.
3442	* @param enmUnit Sample unit.
3443	* @param pszDesc Sample description.
3444	*/
3445	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3446
3447	/**
3448	* Same as pfnSTAMRegister except that the name is specified in a
3449	* RTStrPrintfV like fashion.
3450	*
3451	* @returns VBox status.
3452	* @param pDevIns Device instance of the DMA.
3453	* @param pvSample Pointer to the sample.
3454	* @param enmType Sample type. This indicates what pvSample is
3455	* pointing at.
3456	* @param enmVisibility Visibility type specifying whether unused
3457	* statistics should be visible or not.
3458	* @param enmUnit Sample unit.
3459	* @param pszDesc Sample description.
3460	* @param pszName Sample name format string, unix path style. If
3461	* this does not start with a '/', the default
3462	* prefix will be prepended, otherwise it will be
3463	* used as-is.
3464	* @param args Arguments to the format string.
3465	*/
3466	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3467	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3468	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3469
3470	/**
3471	* Registers a PCI device with the default PCI bus.
3472	*
3473	* If a PDM device has more than one PCI device, they must be registered in the
3474	* order of PDMDEVINSR3::apPciDevs.
3475	*
3476	* @returns VBox status code.
3477	* @param pDevIns The device instance.
3478	* @param pPciDev The PCI device structure.
3479	* This must be kept in the instance data.
3480	* The PCI configuration must be initialized before registration.
3481	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3482	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3483	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3484	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3485	* device number (0-31). This will be ignored if
3486	* the CFGM configuration contains a PCIDeviceNo
3487	* value.
3488	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3489	* function number (0-7). This will be ignored if
3490	* the CFGM configuration contains a PCIFunctionNo
3491	* value.
3492	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3493	* The pointer is saved, so don't free or changed.
3494	* @note The PCI device configuration is now implicit from the apPciDevs
3495	* index, meaning that the zero'th entry is the primary one and
3496	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3497	*/
3498	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3499	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3500
3501	/**
3502	* Initialize MSI or MSI-X emulation support for the given PCI device.
3503	*
3504	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3505	*
3506	* @returns VBox status code.
3507	* @param pDevIns The device instance.
3508	* @param pPciDev The PCI device. NULL is an alias for the first
3509	* one registered.
3510	* @param pMsiReg MSI emulation registration structure.
3511	*/
3512	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3513
3514	/**
3515	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3516	*
3517	* @returns VBox status code.
3518	* @param pDevIns The device instance.
3519	* @param pPciDev The PCI device structure. If NULL the default
3520	* PCI device for this device instance is used.
3521	* @param iRegion The region number.
3522	* @param cbRegion Size of the region.
3523	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3524	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3525	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3526	* @a fFlags, UINT64_MAX if no handle is passed
3527	* (old style).
3528	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3529	* handle is specified. The callback will be
3530	* invoked holding only the PDM lock. The device
3531	* lock will _not_ be taken (due to lock order).
3532	*/
3533	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3534	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3535	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3536
3537	/**
3538	* Register PCI configuration space read/write callbacks.
3539	*
3540	* @returns VBox status code.
3541	* @param pDevIns The device instance.
3542	* @param pPciDev The PCI device structure. If NULL the default
3543	* PCI device for this device instance is used.
3544	* @param pfnRead Pointer to the user defined PCI config read function.
3545	* to call default PCI config read function. Can be NULL.
3546	* @param pfnWrite Pointer to the user defined PCI config write function.
3547	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3548	* is NOT take because that is very likely be a lock order violation.
3549	* @thread EMT(0)
3550	* @note Only callable during VM creation.
3551	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3552	*/
3553	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3554	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3555
3556	/**
3557	* Perform a PCI configuration space write.
3558	*
3559	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3560	*
3561	* @returns Strict VBox status code (mainly DBGFSTOP).
3562	* @param pDevIns The device instance.
3563	* @param pPciDev The PCI device which config space is being read.
3564	* @param uAddress The config space address.
3565	* @param cb The size of the read: 1, 2 or 4 bytes.
3566	* @param u32Value The value to write.
3567	*/
3568	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3569	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3570
3571	/**
3572	* Perform a PCI configuration space read.
3573	*
3574	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3575	*
3576	* @returns Strict VBox status code (mainly DBGFSTOP).
3577	* @param pDevIns The device instance.
3578	* @param pPciDev The PCI device which config space is being read.
3579	* @param uAddress The config space address.
3580	* @param cb The size of the read: 1, 2 or 4 bytes.
3581	* @param pu32Value Where to return the value.
3582	*/
3583	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3584	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3585
3586	/**
3587	* Bus master physical memory read.
3588	*
3589	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3590	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3591	* @param pDevIns The device instance.
3592	* @param pPciDev The PCI device structure. If NULL the default
3593	* PCI device for this device instance is used.
3594	* @param GCPhys Physical address start reading from.
3595	* @param pvBuf Where to put the read bits.
3596	* @param cbRead How many bytes to read.
3597	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3598	* @thread Any thread, but the call may involve the emulation thread.
3599	*/
3600	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3601
3602	/**
3603	* Bus master physical memory write.
3604	*
3605	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3606	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3607	* @param pDevIns The device instance.
3608	* @param pPciDev The PCI device structure. If NULL the default
3609	* PCI device for this device instance is used.
3610	* @param GCPhys Physical address to write to.
3611	* @param pvBuf What to write.
3612	* @param cbWrite How many bytes to write.
3613	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3614	* @thread Any thread, but the call may involve the emulation thread.
3615	*/
3616	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3617
3618	/**
3619	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3620	* physical memory write operation.
3621	*
3622	* Refer pfnPhysGCPhys2CCPtr() for further details.
3623	*
3624	* @returns VBox status code.
3625	* @param pDevIns The device instance.
3626	* @param pPciDev The PCI device structure. If NULL the default
3627	* PCI device for this device instance is used.
3628	* @param GCPhys The guest physical address of the page that should be
3629	* mapped.
3630	* @param fFlags Flags reserved for future use, MBZ.
3631	* @param ppv Where to store the address corresponding to GCPhys.
3632	* @param pLock Where to store the lock information that
3633	* pfnPhysReleasePageMappingLock needs.
3634	*
3635	* @remarks Avoid calling this API from within critical sections (other than the PGM
3636	* one) because of the deadlock risk when we have to delegating the task to
3637	* an EMT.
3638	* @thread Any.
3639	*/
3640	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3641	void **ppv, PPGMPAGEMAPLOCK pLock));
3642
3643	/**
3644	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3645	* for a bus master physical memory read operation.
3646	*
3647	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3648	*
3649	* @returns VBox status code.
3650	* @param pDevIns The device instance.
3651	* @param pPciDev The PCI device structure. If NULL the default
3652	* PCI device for this device instance is used.
3653	* @param GCPhys The guest physical address of the page that
3654	* should be mapped.
3655	* @param fFlags Flags reserved for future use, MBZ.
3656	* @param ppv Where to store the address corresponding to
3657	* GCPhys.
3658	* @param pLock Where to store the lock information that
3659	* pfnPhysReleasePageMappingLock needs.
3660	*
3661	* @remarks Avoid calling this API from within critical sections.
3662	* @thread Any.
3663	*/
3664	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3665	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3666
3667	/**
3668	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3669	* master physical memory write operation.
3670	*
3671	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3672	* ASAP to release them.
3673	*
3674	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3675	*
3676	* @returns VBox status code.
3677	* @param pDevIns The device instance.
3678	* @param pPciDev The PCI device structure. If NULL the default
3679	* PCI device for this device instance is used.
3680	* @param cPages Number of pages to lock.
3681	* @param paGCPhysPages The guest physical address of the pages that
3682	* should be mapped (@a cPages entries).
3683	* @param fFlags Flags reserved for future use, MBZ.
3684	* @param papvPages Where to store the ring-3 mapping addresses
3685	* corresponding to @a paGCPhysPages.
3686	* @param paLocks Where to store the locking information that
3687	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3688	* in length).
3689	*/
3690	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3691	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3692	PPGMPAGEMAPLOCK paLocks));
3693
3694	/**
3695	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3696	* master physical memory read operation.
3697	*
3698	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3699	* ASAP to release them.
3700	*
3701	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3702	*
3703	* @returns VBox status code.
3704	* @param pDevIns The device instance.
3705	* @param pPciDev The PCI device structure. If NULL the default
3706	* PCI device for this device instance is used.
3707	* @param cPages Number of pages to lock.
3708	* @param paGCPhysPages The guest physical address of the pages that
3709	* should be mapped (@a cPages entries).
3710	* @param fFlags Flags reserved for future use, MBZ.
3711	* @param papvPages Where to store the ring-3 mapping addresses
3712	* corresponding to @a paGCPhysPages.
3713	* @param paLocks Where to store the lock information that
3714	* pfnPhysReleasePageMappingLock needs (@a cPages
3715	* in length).
3716	*/
3717	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3718	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3719	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3720
3721	/**
3722	* Sets the IRQ for the given PCI device.
3723	*
3724	* @param pDevIns The device instance.
3725	* @param pPciDev The PCI device structure. If NULL the default
3726	* PCI device for this device instance is used.
3727	* @param iIrq IRQ number to set.
3728	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3729	* @thread Any thread, but will involve the emulation thread.
3730	*/
3731	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3732
3733	/**
3734	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3735	* the request when not called from EMT.
3736	*
3737	* @param pDevIns The device instance.
3738	* @param pPciDev The PCI device structure. If NULL the default
3739	* PCI device for this device instance is used.
3740	* @param iIrq IRQ number to set.
3741	* @param iLevel IRQ level.
3742	* @thread Any thread, but will involve the emulation thread.
3743	*/
3744	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3745
3746	/**
3747	* Set ISA IRQ for a device.
3748	*
3749	* @param pDevIns The device instance.
3750	* @param iIrq IRQ number to set.
3751	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3752	* @thread Any thread, but will involve the emulation thread.
3753	*/
3754	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3755
3756	/**
3757	* Set the ISA IRQ for a device, but don't wait for EMT to process
3758	* the request when not called from EMT.
3759	*
3760	* @param pDevIns The device instance.
3761	* @param iIrq IRQ number to set.
3762	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3763	* @thread Any thread, but will involve the emulation thread.
3764	*/
3765	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3766
3767	/**
3768	* Attaches a driver (chain) to the device.
3769	*
3770	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3771	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3772	*
3773	* @returns VBox status code.
3774	* @param pDevIns The device instance.
3775	* @param iLun The logical unit to attach.
3776	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3777	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3778	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3779	* for the live of the device instance.
3780	*/
3781	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3782	PPDMIBASE ppBaseInterface, const char pszDesc));
3783
3784	/**
3785	* Detaches an attached driver (chain) from the device again.
3786	*
3787	* @returns VBox status code.
3788	* @param pDevIns The device instance.
3789	* @param pDrvIns The driver instance to detach.
3790	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3791	*/
3792	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3793
3794	/**
3795	* Reconfigures the driver chain for a LUN, detaching any driver currently
3796	* present there.
3797	*
3798	* Caller will have attach it, of course.
3799	*
3800	* @returns VBox status code.
3801	* @param pDevIns The device instance.
3802	* @param iLun The logical unit to reconfigure.
3803	* @param cDepth The depth of the driver chain. Determins the
3804	* size of @a papszDrivers and @a papConfigs.
3805	* @param papszDrivers The names of the drivers to configure in the
3806	* chain, first entry is the one immediately
3807	* below the device/LUN
3808	* @param papConfigs The configurations for each of the drivers
3809	* in @a papszDrivers array. NULL entries
3810	* corresponds to empty 'Config' nodes. This
3811	* function will take ownership of non-NULL
3812	* CFGM sub-trees and set the array member to
3813	* NULL, so the caller can do cleanups on
3814	* failure. This parameter is optional.
3815	* @param fFlags Reserved, MBZ.
3816	*/
3817	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3818	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3819
3820	/** @name Exported PDM Queue Functions
3821	* @{ */
3822	/**
3823	* Create a queue.
3824	*
3825	* @returns VBox status code.
3826	* @param pDevIns The device instance.
3827	* @param cbItem The size of a queue item.
3828	* @param cItems The number of items in the queue.
3829	* @param cMilliesInterval The number of milliseconds between polling the queue.
3830	* If 0 then the emulation thread will be notified whenever an item arrives.
3831	* @param pfnCallback The consumer function.
3832	* @param fRZEnabled Set if the queue should work in RC and R0.
3833	* @param pszName The queue base name. The instance number will be
3834	* appended automatically.
3835	* @param phQueue Where to store the queue handle on success.
3836	* @thread EMT(0)
3837	* @remarks The device critical section will NOT be entered before calling the
3838	* callback. No locks will be held, but for now it's safe to assume
3839	* that only one EMT will do queue callbacks at any one time.
3840	*/
3841	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3842	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3843	PDMQUEUEHANDLE *phQueue));
3844
3845	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3846	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3847	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3848	/** @} */
3849
3850	/** @name PDM Task
3851	* @{ */
3852	/**
3853	* Create an asynchronous ring-3 task.
3854	*
3855	* @returns VBox status code.
3856	* @param pDevIns The device instance.
3857	* @param fFlags PDMTASK_F_XXX
3858	* @param pszName The function name or similar. Used for statistics,
3859	* so no slashes.
3860	* @param pfnCallback The task function.
3861	* @param pvUser User argument for the task function.
3862	* @param phTask Where to return the task handle.
3863	* @thread EMT(0)
3864	*/
3865	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3866	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3867	/**
3868	* Triggers the running the given task.
3869	*
3870	* @returns VBox status code.
3871	* @retval VINF_ALREADY_POSTED is the task is already pending.
3872	* @param pDevIns The device instance.
3873	* @param hTask The task to trigger.
3874	* @thread Any thread.
3875	*/
3876	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3877	/** @} */
3878
3879	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3880	* These semaphores can be signalled from ring-0.
3881	* @{ */
3882	/** @sa SUPSemEventCreate */
3883	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3884	/** @sa SUPSemEventClose */
3885	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3886	/** @sa SUPSemEventSignal */
3887	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3888	/** @sa SUPSemEventWaitNoResume */
3889	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3890	/** @sa SUPSemEventWaitNsAbsIntr */
3891	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3892	/** @sa SUPSemEventWaitNsRelIntr */
3893	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3894	/** @sa SUPSemEventGetResolution */
3895	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3896	/** @} */
3897
3898	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3899	* These semaphores can be signalled from ring-0.
3900	* @{ */
3901	/** @sa SUPSemEventMultiCreate */
3902	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3903	/** @sa SUPSemEventMultiClose */
3904	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3905	/** @sa SUPSemEventMultiSignal */
3906	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3907	/** @sa SUPSemEventMultiReset */
3908	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3909	/** @sa SUPSemEventMultiWaitNoResume */
3910	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3911	/** @sa SUPSemEventMultiWaitNsAbsIntr */
3912	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3913	/** @sa SUPSemEventMultiWaitNsRelIntr */
3914	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3915	/** @sa SUPSemEventMultiGetResolution */
3916	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3917	/** @} */
3918
3919	/**
3920	* Initializes a PDM critical section.
3921	*
3922	* The PDM critical sections are derived from the IPRT critical sections, but
3923	* works in RC and R0 as well.
3924	*
3925	* @returns VBox status code.
3926	* @param pDevIns The device instance.
3927	* @param pCritSect Pointer to the critical section.
3928	* @param SRC_POS Use RT_SRC_POS.
3929	* @param pszNameFmt Format string for naming the critical section.
3930	* For statistics and lock validation.
3931	* @param va Arguments for the format string.
3932	*/
3933	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3934	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3935
3936	/**
3937	* Gets the NOP critical section.
3938	*
3939	* @returns The ring-3 address of the NOP critical section.
3940	* @param pDevIns The device instance.
3941	*/
3942	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3943
3944	/**
3945	* Changes the device level critical section from the automatically created
3946	* default to one desired by the device constructor.
3947	*
3948	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
3949	* the additional contexts.
3950	*
3951	* @returns VBox status code.
3952	* @param pDevIns The device instance.
3953	* @param pCritSect The critical section to use. NULL is not
3954	* valid, instead use the NOP critical
3955	* section.
3956	*/
3957	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3958
3959	/** @name Exported PDM Critical Section Functions
3960	* @{ */
3961	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3962	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3963	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3964	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3965	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3966	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3967	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3968	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3969	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3970	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3971	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3972	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3973	/** @} */
3974
3975	/** @name Exported PDM Read/Write Critical Section Functions
3976	* @{ */
3977	DECLR3CALLBACKMEMBER(int, pfnCritSectRwInit,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
3978	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3979	DECLR3CALLBACKMEMBER(int, pfnCritSectRwDelete,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3980
3981	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
3982	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3983	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3984	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3985	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3986
3987	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
3988	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3989	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3990	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3991	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3992
3993	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3994	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
3995	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3996	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3997	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3998	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3999	/** @} */
4000
4001	/**
4002	* Creates a PDM thread.
4003	*
4004	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
4005	* resuming, and destroying the thread as the VM state changes.
4006	*
4007	* @returns VBox status code.
4008	* @param pDevIns The device instance.
4009	* @param ppThread Where to store the thread 'handle'.
4010	* @param pvUser The user argument to the thread function.
4011	* @param pfnThread The thread function.
4012	* @param pfnWakeup The wakup callback. This is called on the EMT
4013	* thread when a state change is pending.
4014	* @param cbStack See RTThreadCreate.
4015	* @param enmType See RTThreadCreate.
4016	* @param pszName See RTThreadCreate.
4017	* @remarks The device critical section will NOT be entered prior to invoking
4018	* the function pointers.
4019	*/
4020	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
4021	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
4022
4023	/** @name Exported PDM Thread Functions
4024	* @{ */
4025	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
4026	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
4027	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
4028	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
4029	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
4030	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
4031	/** @} */
4032
4033	/**
4034	* Set up asynchronous handling of a suspend, reset or power off notification.
4035	*
4036	* This shall only be called when getting the notification. It must be called
4037	* for each one.
4038	*
4039	* @returns VBox status code.
4040	* @param pDevIns The device instance.
4041	* @param pfnAsyncNotify The callback.
4042	* @thread EMT(0)
4043	* @remarks The caller will enter the device critical section prior to invoking
4044	* the callback.
4045	*/
4046	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
4047
4048	/**
4049	* Notify EMT(0) that the device has completed the asynchronous notification
4050	* handling.
4051	*
4052	* This can be called at any time, spurious calls will simply be ignored.
4053	*
4054	* @param pDevIns The device instance.
4055	* @thread Any
4056	*/
4057	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
4058
4059	/**
4060	* Register the RTC device.
4061	*
4062	* @returns VBox status code.
4063	* @param pDevIns The device instance.
4064	* @param pRtcReg Pointer to a RTC registration structure.
4065	* @param ppRtcHlp Where to store the pointer to the helper
4066	* functions.
4067	*/
4068	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
4069
4070	/**
4071	* Register a PCI Bus.
4072	*
4073	* @returns VBox status code, but the positive values 0..31 are used to indicate
4074	* bus number rather than informational status codes.
4075	* @param pDevIns The device instance.
4076	* @param pPciBusReg Pointer to PCI bus registration structure.
4077	* @param ppPciHlp Where to store the pointer to the PCI Bus
4078	* helpers.
4079	* @param piBus Where to return the PDM bus number. Optional.
4080	*/
4081	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
4082	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
4083
4084	/**
4085	* Register the IOMMU device.
4086	*
4087	* @returns VBox status code.
4088	* @param pDevIns The device instance.
4089	* @param pIommuReg Pointer to a IOMMU registration structure.
4090	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
4091	* helpers.
4092	* @param pidxIommu Where to return the IOMMU index. Optional.
4093	*/
4094	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
4095	uint32_t *pidxIommu));
4096
4097	/**
4098	* Register the PIC device.
4099	*
4100	* @returns VBox status code.
4101	* @param pDevIns The device instance.
4102	* @param pPicReg Pointer to a PIC registration structure.
4103	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
4104	* helpers.
4105	* @sa PDMDevHlpPICSetUpContext
4106	*/
4107	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4108
4109	/**
4110	* Register the APIC device.
4111	*
4112	* @returns VBox status code.
4113	* @param pDevIns The device instance.
4114	*/
4115	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
4116
4117	/**
4118	* Register the I/O APIC device.
4119	*
4120	* @returns VBox status code.
4121	* @param pDevIns The device instance.
4122	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4123	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
4124	* helpers.
4125	*/
4126	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4127
4128	/**
4129	* Register the HPET device.
4130	*
4131	* @returns VBox status code.
4132	* @param pDevIns The device instance.
4133	* @param pHpetReg Pointer to a HPET registration structure.
4134	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4135	* helpers.
4136	*/
4137	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4138
4139	/**
4140	* Register a raw PCI device.
4141	*
4142	* @returns VBox status code.
4143	* @param pDevIns The device instance.
4144	* @param pPciRawReg Pointer to a raw PCI registration structure.
4145	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4146	* device helpers.
4147	*/
4148	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4149
4150	/**
4151	* Register the DMA device.
4152	*
4153	* @returns VBox status code.
4154	* @param pDevIns The device instance.
4155	* @param pDmacReg Pointer to a DMAC registration structure.
4156	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4157	*/
4158	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4159
4160	/**
4161	* Register transfer function for DMA channel.
4162	*
4163	* @returns VBox status code.
4164	* @param pDevIns The device instance.
4165	* @param uChannel Channel number.
4166	* @param pfnTransferHandler Device specific transfer callback function.
4167	* @param pvUser User pointer to pass to the callback.
4168	* @thread EMT
4169	*/
4170	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4171
4172	/**
4173	* Read memory.
4174	*
4175	* @returns VBox status code.
4176	* @param pDevIns The device instance.
4177	* @param uChannel Channel number.
4178	* @param pvBuffer Pointer to target buffer.
4179	* @param off DMA position.
4180	* @param cbBlock Block size.
4181	* @param pcbRead Where to store the number of bytes which was
4182	* read. optional.
4183	* @thread EMT
4184	*/
4185	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4186
4187	/**
4188	* Write memory.
4189	*
4190	* @returns VBox status code.
4191	* @param pDevIns The device instance.
4192	* @param uChannel Channel number.
4193	* @param pvBuffer Memory to write.
4194	* @param off DMA position.
4195	* @param cbBlock Block size.
4196	* @param pcbWritten Where to store the number of bytes which was
4197	* written. optional.
4198	* @thread EMT
4199	*/
4200	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4201
4202	/**
4203	* Set the DREQ line.
4204	*
4205	* @returns VBox status code.
4206	* @param pDevIns Device instance.
4207	* @param uChannel Channel number.
4208	* @param uLevel Level of the line.
4209	* @thread EMT
4210	*/
4211	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4212
4213	/**
4214	* Get channel mode.
4215	*
4216	* @returns Channel mode. See specs.
4217	* @param pDevIns The device instance.
4218	* @param uChannel Channel number.
4219	* @thread EMT
4220	*/
4221	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4222
4223	/**
4224	* Schedule DMA execution.
4225	*
4226	* @param pDevIns The device instance.
4227	* @thread Any thread.
4228	*/
4229	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4230
4231	/**
4232	* Write CMOS value and update the checksum(s).
4233	*
4234	* @returns VBox status code.
4235	* @param pDevIns The device instance.
4236	* @param iReg The CMOS register index.
4237	* @param u8Value The CMOS register value.
4238	* @thread EMT
4239	*/
4240	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4241
4242	/**
4243	* Read CMOS value.
4244	*
4245	* @returns VBox status code.
4246	* @param pDevIns The device instance.
4247	* @param iReg The CMOS register index.
4248	* @param pu8Value Where to store the CMOS register value.
4249	* @thread EMT
4250	*/
4251	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4252
4253	/**
4254	* Assert that the current thread is the emulation thread.
4255	*
4256	* @returns True if correct.
4257	* @returns False if wrong.
4258	* @param pDevIns The device instance.
4259	* @param pszFile Filename of the assertion location.
4260	* @param iLine The linenumber of the assertion location.
4261	* @param pszFunction Function of the assertion location.
4262	*/
4263	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4264
4265	/**
4266	* Assert that the current thread is NOT the emulation thread.
4267	*
4268	* @returns True if correct.
4269	* @returns False if wrong.
4270	* @param pDevIns The device instance.
4271	* @param pszFile Filename of the assertion location.
4272	* @param iLine The linenumber of the assertion location.
4273	* @param pszFunction Function of the assertion location.
4274	*/
4275	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4276
4277	/**
4278	* Resolves the symbol for a raw-mode context interface.
4279	*
4280	* @returns VBox status code.
4281	* @param pDevIns The device instance.
4282	* @param pvInterface The interface structure.
4283	* @param cbInterface The size of the interface structure.
4284	* @param pszSymPrefix What to prefix the symbols in the list with
4285	* before resolving them. This must start with
4286	* 'dev' and contain the driver name.
4287	* @param pszSymList List of symbols corresponding to the interface.
4288	* There is generally a there is generally a define
4289	* holding this list associated with the interface
4290	* definition (INTERFACE_SYM_LIST). For more
4291	* details see PDMR3LdrGetInterfaceSymbols.
4292	* @thread EMT
4293	*/
4294	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4295	const char pszSymPrefix, const char pszSymList));
4296
4297	/**
4298	* Resolves the symbol for a ring-0 context interface.
4299	*
4300	* @returns VBox status code.
4301	* @param pDevIns The device instance.
4302	* @param pvInterface The interface structure.
4303	* @param cbInterface The size of the interface structure.
4304	* @param pszSymPrefix What to prefix the symbols in the list with
4305	* before resolving them. This must start with
4306	* 'dev' and contain the driver name.
4307	* @param pszSymList List of symbols corresponding to the interface.
4308	* There is generally a there is generally a define
4309	* holding this list associated with the interface
4310	* definition (INTERFACE_SYM_LIST). For more
4311	* details see PDMR3LdrGetInterfaceSymbols.
4312	* @thread EMT
4313	*/
4314	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4315	const char pszSymPrefix, const char pszSymList));
4316
4317	/**
4318	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4319	*
4320	* @returns VBox status code.
4321	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4322	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4323	*
4324	* @param pDevIns The device instance.
4325	* @param uOperation The operation to perform.
4326	* @param u64Arg 64-bit integer argument.
4327	* @thread EMT
4328	*/
4329	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4330
4331	/**
4332	* Gets the reason for the most recent VM suspend.
4333	*
4334	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4335	* suspend has been made or if the pDevIns is invalid.
4336	* @param pDevIns The device instance.
4337	*/
4338	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4339
4340	/**
4341	* Gets the reason for the most recent VM resume.
4342	*
4343	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4344	* resume has been made or if the pDevIns is invalid.
4345	* @param pDevIns The device instance.
4346	*/
4347	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4348
4349	/**
4350	* Requests the mapping of multiple guest page into ring-3.
4351	*
4352	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4353	* ASAP to release them.
4354	*
4355	* This API will assume your intention is to write to the pages, and will
4356	* therefore replace shared and zero pages. If you do not intend to modify the
4357	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4358	*
4359	* @returns VBox status code.
4360	* @retval VINF_SUCCESS on success.
4361	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4362	* backing or if any of the pages the page has any active access
4363	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4364	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4365	* an invalid physical address.
4366	*
4367	* @param pDevIns The device instance.
4368	* @param cPages Number of pages to lock.
4369	* @param paGCPhysPages The guest physical address of the pages that
4370	* should be mapped (@a cPages entries).
4371	* @param fFlags Flags reserved for future use, MBZ.
4372	* @param papvPages Where to store the ring-3 mapping addresses
4373	* corresponding to @a paGCPhysPages.
4374	* @param paLocks Where to store the locking information that
4375	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4376	* in length).
4377	*
4378	* @remark Avoid calling this API from within critical sections (other than the
4379	* PGM one) because of the deadlock risk when we have to delegating the
4380	* task to an EMT.
4381	* @thread Any.
4382	* @since 6.0.6
4383	*/
4384	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4385	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4386
4387	/**
4388	* Requests the mapping of multiple guest page into ring-3, for reading only.
4389	*
4390	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4391	* ASAP to release them.
4392	*
4393	* @returns VBox status code.
4394	* @retval VINF_SUCCESS on success.
4395	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4396	* backing or if any of the pages the page has an active ALL access
4397	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4398	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4399	* an invalid physical address.
4400	*
4401	* @param pDevIns The device instance.
4402	* @param cPages Number of pages to lock.
4403	* @param paGCPhysPages The guest physical address of the pages that
4404	* should be mapped (@a cPages entries).
4405	* @param fFlags Flags reserved for future use, MBZ.
4406	* @param papvPages Where to store the ring-3 mapping addresses
4407	* corresponding to @a paGCPhysPages.
4408	* @param paLocks Where to store the lock information that
4409	* pfnPhysReleasePageMappingLock needs (@a cPages
4410	* in length).
4411	*
4412	* @remark Avoid calling this API from within critical sections.
4413	* @thread Any.
4414	* @since 6.0.6
4415	*/
4416	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4417	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4418
4419	/**
4420	* Release the mappings of multiple guest pages.
4421	*
4422	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4423	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4424	*
4425	* @param pDevIns The device instance.
4426	* @param cPages Number of pages to unlock.
4427	* @param paLocks The lock structures initialized by the mapping
4428	* function (@a cPages in length).
4429	* @thread Any.
4430	* @since 6.0.6
4431	*/
4432	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4433
4434	/**
4435	* Returns the micro architecture used for the guest.
4436	*
4437	* @returns CPU micro architecture enum.
4438	* @param pDevIns The device instance.
4439	*/
4440	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4441
4442	/**
4443	* Get the number of physical and linear address bits supported by the guest.
4444	*
4445	* @param pDevIns The device instance.
4446	* @param pcPhysAddrWidth Where to store the number of physical address bits
4447	* supported by the guest.
4448	* @param pcLinearAddrWidth Where to store the number of linear address bits
4449	* supported by the guest.
4450	*/
4451	DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4452	uint8_t *pcLinearAddrWidth));
4453
4454	/** Space reserved for future members.
4455	* @{ */
4456	/**
4457	* Deregister zero or more samples given their name prefix.
4458	*
4459	* @returns VBox status code.
4460	* @param pDevIns The device instance.
4461	* @param pszPrefix The name prefix of the samples to remove. If this does
4462	* not start with a '/', the default prefix will be
4463	* prepended, otherwise it will be used as-is.
4464	*/
4465	DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4466	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4467	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4468	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4469	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4470	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4471	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4472	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4473	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4474	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4475	/** @} */
4476
4477
4478	/** API available to trusted devices only.
4479	*
4480	* These APIs are providing unrestricted access to the guest and the VM,
4481	* or they are interacting intimately with PDM.
4482	*
4483	* @{
4484	*/
4485
4486	/**
4487	* Gets the user mode VM handle. Restricted API.
4488	*
4489	* @returns User mode VM Handle.
4490	* @param pDevIns The device instance.
4491	*/
4492	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4493
4494	/**
4495	* Gets the global VM handle. Restricted API.
4496	*
4497	* @returns VM Handle.
4498	* @param pDevIns The device instance.
4499	*/
4500	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4501
4502	/**
4503	* Gets the VMCPU handle. Restricted API.
4504	*
4505	* @returns VMCPU Handle.
4506	* @param pDevIns The device instance.
4507	*/
4508	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4509
4510	/**
4511	* The the VM CPU ID of the current thread (restricted API).
4512	*
4513	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4514	* @param pDevIns The device instance.
4515	*/
4516	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4517
4518	/**
4519	* Registers the VMM device heap or notifies about mapping/unmapping.
4520	*
4521	* This interface serves three purposes:
4522	*
4523	* -# Register the VMM device heap during device construction
4524	* for the HM to use.
4525	* -# Notify PDM/HM that it's mapped into guest address
4526	* space (i.e. usable).
4527	* -# Notify PDM/HM that it is being unmapped from the guest
4528	* address space (i.e. not usable).
4529	*
4530	* @returns VBox status code.
4531	* @param pDevIns The device instance.
4532	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4533	* not mapped.
4534	* @param pvHeap Ring 3 heap pointer.
4535	* @param cbHeap Size of the heap.
4536	* @thread EMT.
4537	*/
4538	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4539
4540	/**
4541	* Registers the firmware (BIOS, EFI) device with PDM.
4542	*
4543	* The firmware provides a callback table and gets a special PDM helper table.
4544	* There can only be one firmware device for a VM.
4545	*
4546	* @returns VBox status code.
4547	* @param pDevIns The device instance.
4548	* @param pFwReg Firmware registration structure.
4549	* @param ppFwHlp Where to return the firmware helper structure.
4550	* @remarks Only valid during device construction.
4551	* @thread EMT(0)
4552	*/
4553	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4554
4555	/**
4556	* Resets the VM.
4557	*
4558	* @returns The appropriate VBox status code to pass around on reset.
4559	* @param pDevIns The device instance.
4560	* @param fFlags PDMVMRESET_F_XXX flags.
4561	* @thread The emulation thread.
4562	*/
4563	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4564
4565	/**
4566	* Suspends the VM.
4567	*
4568	* @returns The appropriate VBox status code to pass around on suspend.
4569	* @param pDevIns The device instance.
4570	* @thread The emulation thread.
4571	*/
4572	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4573
4574	/**
4575	* Suspends, saves and powers off the VM.
4576	*
4577	* @returns The appropriate VBox status code to pass around.
4578	* @param pDevIns The device instance.
4579	* @thread An emulation thread.
4580	*/
4581	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4582
4583	/**
4584	* Power off the VM.
4585	*
4586	* @returns The appropriate VBox status code to pass around on power off.
4587	* @param pDevIns The device instance.
4588	* @thread The emulation thread.
4589	*/
4590	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4591
4592	/**
4593	* Checks if the Gate A20 is enabled or not.
4594	*
4595	* @returns true if A20 is enabled.
4596	* @returns false if A20 is disabled.
4597	* @param pDevIns The device instance.
4598	* @thread The emulation thread.
4599	*/
4600	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4601
4602	/**
4603	* Enables or disables the Gate A20.
4604	*
4605	* @param pDevIns The device instance.
4606	* @param fEnable Set this flag to enable the Gate A20; clear it
4607	* to disable.
4608	* @thread The emulation thread.
4609	*/
4610	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4611
4612	/**
4613	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4614	* thread.
4615	*
4616	* @param pDevIns The device instance.
4617	* @param iLeaf The CPUID leaf to get.
4618	* @param pEax Where to store the EAX value.
4619	* @param pEbx Where to store the EBX value.
4620	* @param pEcx Where to store the ECX value.
4621	* @param pEdx Where to store the EDX value.
4622	* @thread EMT.
4623	*/
4624	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4625
4626	/**
4627	* Get the current virtual clock time in a VM. The clock frequency must be
4628	* queried separately.
4629	*
4630	* @returns Current clock time.
4631	* @param pDevIns The device instance.
4632	*/
4633	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4634
4635	/**
4636	* Get the frequency of the virtual clock.
4637	*
4638	* @returns The clock frequency (not variable at run-time).
4639	* @param pDevIns The device instance.
4640	*/
4641	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4642
4643	/**
4644	* Get the current virtual clock time in a VM, in nanoseconds.
4645	*
4646	* @returns Current clock time (in ns).
4647	* @param pDevIns The device instance.
4648	*/
4649	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4650
4651	/**
4652	* Gets the support driver session.
4653	*
4654	* This is intended for working with the semaphore API.
4655	*
4656	* @returns Support driver session handle.
4657	* @param pDevIns The device instance.
4658	*/
4659	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4660
4661	/**
4662	* Queries a generic object from the VMM user.
4663	*
4664	* @returns Pointer to the object if found, NULL if not.
4665	* @param pDevIns The device instance.
4666	* @param pUuid The UUID of what's being queried. The UUIDs and
4667	* the usage conventions are defined by the user.
4668	*
4669	* @note It is strictly forbidden to call this internally in VBox! This
4670	* interface is exclusively for hacks in externally developed devices.
4671	*/
4672	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4673
4674	/**
4675	* Register a physical page access handler type.
4676	*
4677	* @returns VBox status code.
4678	* @param pDevIns The device instance.
4679	* @param enmKind The kind of access handler.
4680	* @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4681	* @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4682	* handler should be called.
4683	* @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4684	* ring-3 handler should be called.
4685	* @param pszHandlerRC The name of the raw-mode context handler, NULL if
4686	* the ring-3 handler should be called.
4687	* @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4688	* if the ring-3 handler should be called.
4689	* @param pszDesc The type description.
4690	* @param phType Where to return the type handle (cross context
4691	* safe).
4692	*/
4693	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4694	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4695	const char pszHandlerR0, const char pszPfHandlerR0,
4696	const char pszHandlerRC, const char pszPfHandlerRC,
4697	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4698
4699	/**
4700	* Register a access handler for a physical range.
4701	*
4702	* @returns VBox status code.
4703	* @retval VINF_SUCCESS when successfully installed.
4704	* @retval VINF_PGM_GCPHYS_ALIASED when the shadow PTs could be updated because
4705	* the guest page aliased or/and mapped by multiple PTs. A CR3 sync has been
4706	* flagged together with a pool clearing.
4707	* @retval VERR_PGM_HANDLER_PHYSICAL_CONFLICT if the range conflicts with an existing
4708	* one. A debug assertion is raised.
4709	*
4710	* @param pDevIns The device instance.
4711	* @param GCPhys Start physical address.
4712	* @param GCPhysLast Last physical address. (inclusive)
4713	* @param hType The handler type registration handle.
4714	* @param pvUserR3 User argument to the R3 handler.
4715	* @param pvUserR0 User argument to the R0 handler.
4716	* @param pvUserRC User argument to the RC handler. This can be a value
4717	* less that 0x10000 or a (non-null) pointer that is
4718	* automatically relocated.
4719	* @param pszDesc Description of this handler. If NULL, the type
4720	* description will be used instead.
4721	*/
4722	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalRegister, (PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
4723	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4724	RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc));
4725
4726	/**
4727	* Deregister a physical page access handler.
4728	*
4729	* @returns VBox status code.
4730	* @param pDevIns The device instance.
4731	* @param GCPhys Start physical address.
4732	*/
4733	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalDeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4734
4735	/**
4736	* Temporarily turns off the access monitoring of a page within a monitored
4737	* physical write/all page access handler region.
4738	*
4739	* Use this when no further \#PFs are required for that page. Be aware that
4740	* a page directory sync might reset the flags, and turn on access monitoring
4741	* for the page.
4742	*
4743	* The caller must do required page table modifications.
4744	*
4745	* @returns VBox status code.
4746	* @param pDevIns The device instance.
4747	* @param GCPhys The start address of the access handler. This
4748	* must be a fully page aligned range or we risk
4749	* messing up other handlers installed for the
4750	* start and end pages.
4751	* @param GCPhysPage The physical address of the page to turn off
4752	* access monitoring for.
4753	*/
4754	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
4755
4756	/**
4757	* Resets any modifications to individual pages in a physical page access
4758	* handler region.
4759	*
4760	* This is used in pair with PGMHandlerPhysicalPageTempOff(),
4761	* PGMHandlerPhysicalPageAliasMmio2() or PGMHandlerPhysicalPageAliasHC().
4762	*
4763	* @returns VBox status code.
4764	* @param pDevIns The device instance.
4765	* @param GCPhys The start address of the handler regions, i.e. what you
4766	* passed to PGMR3HandlerPhysicalRegister(),
4767	* PGMHandlerPhysicalRegisterEx() or
4768	* PGMHandlerPhysicalModify().
4769	*/
4770	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalReset,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4771
4772	/**
4773	* Registers the guest memory range that can be used for patching.
4774	*
4775	* @returns VBox status code.
4776	* @param pDevIns The device instance.
4777	* @param GCPtrPatchMem Patch memory range.
4778	* @param cbPatchMem Size of the memory range.
4779	*/
4780	DECLR3CALLBACKMEMBER(int, pfnVMMRegisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4781
4782	/**
4783	* Deregisters the guest memory range that can be used for patching.
4784	*
4785	* @returns VBox status code.
4786	* @param pDevIns The device instance.
4787	* @param GCPtrPatchMem Patch memory range.
4788	* @param cbPatchMem Size of the memory range.
4789	*/
4790	DECLR3CALLBACKMEMBER(int, pfnVMMDeregisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4791
4792	/**
4793	* Registers a new shared module for the VM
4794	*
4795	* @returns VBox status code.
4796	* @param pDevIns The device instance.
4797	* @param enmGuestOS Guest OS type.
4798	* @param pszModuleName Module name.
4799	* @param pszVersion Module version.
4800	* @param GCBaseAddr Module base address.
4801	* @param cbModule Module size.
4802	* @param cRegions Number of shared region descriptors.
4803	* @param paRegions Shared region(s).
4804	*/
4805	DECLR3CALLBACKMEMBER(int, pfnSharedModuleRegister,(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
4806	RTGCPTR GCBaseAddr, uint32_t cbModule,
4807	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions));
4808
4809	/**
4810	* Unregisters a shared module for the VM
4811	*
4812	* @returns VBox status code.
4813	* @param pDevIns The device instance.
4814	* @param pszModuleName Module name.
4815	* @param pszVersion Module version.
4816	* @param GCBaseAddr Module base address.
4817	* @param cbModule Module size.
4818	*/
4819	DECLR3CALLBACKMEMBER(int, pfnSharedModuleUnregister,(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
4820	RTGCPTR GCBaseAddr, uint32_t cbModule));
4821
4822	/**
4823	* Query the state of a page in a shared module
4824	*
4825	* @returns VBox status code.
4826	* @param pDevIns The device instance.
4827	* @param GCPtrPage Page address.
4828	* @param pfShared Shared status (out).
4829	* @param pfPageFlags Page flags (out).
4830	*/
4831	DECLR3CALLBACKMEMBER(int, pfnSharedModuleGetPageState, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags));
4832
4833	/**
4834	* Check all registered modules for changes.
4835	*
4836	* @returns VBox status code.
4837	* @param pDevIns The device instance.
4838	*/
4839	DECLR3CALLBACKMEMBER(int, pfnSharedModuleCheckAll,(PPDMDEVINS pDevIns));
4840
4841	/** @} */
4842
4843	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4844	uint32_t u32TheEnd;
4845	} PDMDEVHLPR3;
4846	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4847	/** Pointer to the R3 PDM Device API. */
4848	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4849	/** Pointer to the R3 PDM Device API, const variant. */
4850	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4851
4852
4853	/**
4854	* PDM Device API - RC Variant.
4855	*/
4856	typedef struct PDMDEVHLPRC
4857	{
4858	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4859	uint32_t u32Version;
4860
4861	/**
4862	* Sets up raw-mode context callback handlers for an I/O port range.
4863	*
4864	* The range must have been registered in ring-3 first using
4865	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4866	*
4867	* @returns VBox status.
4868	* @param pDevIns The device instance to register the ports with.
4869	* @param hIoPorts The I/O port range handle.
4870	* @param pfnOut Pointer to function which is gonna handle OUT
4871	* operations. Optional.
4872	* @param pfnIn Pointer to function which is gonna handle IN operations.
4873	* Optional.
4874	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4875	* operations. Optional.
4876	* @param pfnInStr Pointer to function which is gonna handle string IN
4877	* operations. Optional.
4878	* @param pvUser User argument to pass to the callbacks.
4879	*
4880	* @remarks Caller enters the device critical section prior to invoking the
4881	* registered callback methods.
4882	*
4883	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4884	* PDMDevHlpIoPortUnmap.
4885	*/
4886	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4887	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4888	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4889	void *pvUser));
4890
4891	/**
4892	* Sets up raw-mode context callback handlers for an MMIO region.
4893	*
4894	* The region must have been registered in ring-3 first using
4895	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4896	*
4897	* @returns VBox status.
4898	* @param pDevIns The device instance to register the ports with.
4899	* @param hRegion The MMIO region handle.
4900	* @param pfnWrite Pointer to function which is gonna handle Write
4901	* operations.
4902	* @param pfnRead Pointer to function which is gonna handle Read
4903	* operations.
4904	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4905	* operations. (optional)
4906	* @param pvUser User argument to pass to the callbacks.
4907	*
4908	* @remarks Caller enters the device critical section prior to invoking the
4909	* registered callback methods.
4910	*
4911	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4912	* PDMDevHlpMmioUnmap.
4913	*/
4914	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4915	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4916
4917	/**
4918	* Sets up a raw-mode mapping for an MMIO2 region.
4919	*
4920	* The region must have been created in ring-3 first using
4921	* PDMDevHlpMmio2Create().
4922	*
4923	* @returns VBox status.
4924	* @param pDevIns The device instance to register the ports with.
4925	* @param hRegion The MMIO2 region handle.
4926	* @param offSub Start of what to map into raw-mode. Must be page aligned.
4927	* @param cbSub Number of bytes to map into raw-mode. Must be page
4928	* aligned. Zero is an alias for everything.
4929	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4930	* @thread EMT(0)
4931	* @note Only available at VM creation time.
4932	*
4933	* @sa PDMDevHlpMmio2Create().
4934	*/
4935	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4936	size_t offSub, size_t cbSub, void **ppvMapping));
4937
4938	/**
4939	* Bus master physical memory read from the given PCI device.
4940	*
4941	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4942	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4943	* @param pDevIns The device instance.
4944	* @param pPciDev The PCI device structure. If NULL the default
4945	* PCI device for this device instance is used.
4946	* @param GCPhys Physical address start reading from.
4947	* @param pvBuf Where to put the read bits.
4948	* @param cbRead How many bytes to read.
4949	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4950	* @thread Any thread, but the call may involve the emulation thread.
4951	*/
4952	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4953	void *pvBuf, size_t cbRead, uint32_t fFlags));
4954
4955	/**
4956	* Bus master physical memory write from the given PCI device.
4957	*
4958	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4959	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4960	* @param pDevIns The device instance.
4961	* @param pPciDev The PCI device structure. If NULL the default
4962	* PCI device for this device instance is used.
4963	* @param GCPhys Physical address to write to.
4964	* @param pvBuf What to write.
4965	* @param cbWrite How many bytes to write.
4966	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4967	* @thread Any thread, but the call may involve the emulation thread.
4968	*/
4969	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4970	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4971
4972	/**
4973	* Set the IRQ for the given PCI device.
4974	*
4975	* @param pDevIns Device instance.
4976	* @param pPciDev The PCI device structure. If NULL the default
4977	* PCI device for this device instance is used.
4978	* @param iIrq IRQ number to set.
4979	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4980	* @thread Any thread, but will involve the emulation thread.
4981	*/
4982	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4983
4984	/**
4985	* Set ISA IRQ for a device.
4986	*
4987	* @param pDevIns Device instance.
4988	* @param iIrq IRQ number to set.
4989	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4990	* @thread Any thread, but will involve the emulation thread.
4991	*/
4992	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4993
4994	/**
4995	* Read physical memory.
4996	*
4997	* @returns VINF_SUCCESS (for now).
4998	* @param pDevIns Device instance.
4999	* @param GCPhys Physical address start reading from.
5000	* @param pvBuf Where to put the read bits.
5001	* @param cbRead How many bytes to read.
5002	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5003	*/
5004	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5005
5006	/**
5007	* Write to physical memory.
5008	*
5009	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5010	* @param pDevIns Device instance.
5011	* @param GCPhys Physical address to write to.
5012	* @param pvBuf What to write.
5013	* @param cbWrite How many bytes to write.
5014	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5015	*/
5016	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5017
5018	/**
5019	* Checks if the Gate A20 is enabled or not.
5020	*
5021	* @returns true if A20 is enabled.
5022	* @returns false if A20 is disabled.
5023	* @param pDevIns Device instance.
5024	* @thread The emulation thread.
5025	*/
5026	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5027
5028	/**
5029	* Gets the VM state.
5030	*
5031	* @returns VM state.
5032	* @param pDevIns The device instance.
5033	* @thread Any thread (just keep in mind that it's volatile info).
5034	*/
5035	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5036
5037	/**
5038	* Gets the VM handle. Restricted API.
5039	*
5040	* @returns VM Handle.
5041	* @param pDevIns Device instance.
5042	*/
5043	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5044
5045	/**
5046	* Gets the VMCPU handle. Restricted API.
5047	*
5048	* @returns VMCPU Handle.
5049	* @param pDevIns The device instance.
5050	*/
5051	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5052
5053	/**
5054	* The the VM CPU ID of the current thread (restricted API).
5055	*
5056	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5057	* @param pDevIns The device instance.
5058	*/
5059	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5060
5061	/**
5062	* Get the current virtual clock time in a VM. The clock frequency must be
5063	* queried separately.
5064	*
5065	* @returns Current clock time.
5066	* @param pDevIns The device instance.
5067	*/
5068	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5069
5070	/**
5071	* Get the frequency of the virtual clock.
5072	*
5073	* @returns The clock frequency (not variable at run-time).
5074	* @param pDevIns The device instance.
5075	*/
5076	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5077
5078	/**
5079	* Get the current virtual clock time in a VM, in nanoseconds.
5080	*
5081	* @returns Current clock time (in ns).
5082	* @param pDevIns The device instance.
5083	*/
5084	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5085
5086	/**
5087	* Gets the NOP critical section.
5088	*
5089	* @returns The ring-3 address of the NOP critical section.
5090	* @param pDevIns The device instance.
5091	*/
5092	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5093
5094	/**
5095	* Changes the device level critical section from the automatically created
5096	* default to one desired by the device constructor.
5097	*
5098	* Must first be done in ring-3.
5099	*
5100	* @returns VBox status code.
5101	* @param pDevIns The device instance.
5102	* @param pCritSect The critical section to use. NULL is not
5103	* valid, instead use the NOP critical
5104	* section.
5105	*/
5106	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5107
5108	/** @name Exported PDM Critical Section Functions
5109	* @{ */
5110	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5111	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5112	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5113	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5114	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5115	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5116	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5117	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5118	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5119	/** @} */
5120
5121	/** @name Exported PDM Read/Write Critical Section Functions
5122	* @{ */
5123	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5124	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5125	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5126	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5127	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5128
5129	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5130	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5131	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5132	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5133	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5134
5135	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5136	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5137	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5138	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5139	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5140	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5141	/** @} */
5142
5143	/**
5144	* Gets the trace buffer handle.
5145	*
5146	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5147	* really inteded for direct usage, thus no inline wrapper function.
5148	*
5149	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5150	* @param pDevIns The device instance.
5151	*/
5152	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5153
5154	/**
5155	* Sets up the PCI bus for the raw-mode context.
5156	*
5157	* This must be called after ring-3 has registered the PCI bus using
5158	* PDMDevHlpPCIBusRegister().
5159	*
5160	* @returns VBox status code.
5161	* @param pDevIns The device instance.
5162	* @param pPciBusReg The PCI bus registration information for raw-mode,
5163	* considered volatile.
5164	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
5165	*/
5166	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
5167
5168	/**
5169	* Sets up the IOMMU for the raw-mode context.
5170	*
5171	* This must be called after ring-3 has registered the IOMMU using
5172	* PDMDevHlpIommuRegister().
5173	*
5174	* @returns VBox status code.
5175	* @param pDevIns The device instance.
5176	* @param pIommuReg The IOMMU registration information for raw-mode,
5177	* considered volatile.
5178	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
5179	*/
5180	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
5181
5182	/**
5183	* Sets up the PIC for the ring-0 context.
5184	*
5185	* This must be called after ring-3 has registered the PIC using
5186	* PDMDevHlpPICRegister().
5187	*
5188	* @returns VBox status code.
5189	* @param pDevIns The device instance.
5190	* @param pPicReg The PIC registration information for ring-0,
5191	* considered volatile and copied.
5192	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5193	*/
5194	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5195
5196	/**
5197	* Sets up the APIC for the raw-mode context.
5198	*
5199	* This must be called after ring-3 has registered the APIC using
5200	* PDMDevHlpApicRegister().
5201	*
5202	* @returns VBox status code.
5203	* @param pDevIns The device instance.
5204	*/
5205	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5206
5207	/**
5208	* Sets up the IOAPIC for the ring-0 context.
5209	*
5210	* This must be called after ring-3 has registered the PIC using
5211	* PDMDevHlpIoApicRegister().
5212	*
5213	* @returns VBox status code.
5214	* @param pDevIns The device instance.
5215	* @param pIoApicReg The PIC registration information for ring-0,
5216	* considered volatile and copied.
5217	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5218	*/
5219	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5220
5221	/**
5222	* Sets up the HPET for the raw-mode context.
5223	*
5224	* This must be called after ring-3 has registered the PIC using
5225	* PDMDevHlpHpetRegister().
5226	*
5227	* @returns VBox status code.
5228	* @param pDevIns The device instance.
5229	* @param pHpetReg The PIC registration information for raw-mode,
5230	* considered volatile and copied.
5231	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
5232	*/
5233	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
5234
5235	/** Space reserved for future members.
5236	* @{ */
5237	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
5238	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
5239	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
5240	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
5241	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
5242	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
5243	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
5244	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
5245	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
5246	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
5247	/** @} */
5248
5249	/** Just a safety precaution. */
5250	uint32_t u32TheEnd;
5251	} PDMDEVHLPRC;
5252	/** Pointer PDM Device RC API. */
5253	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
5254	/** Pointer PDM Device RC API. */
5255	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
5256
5257	/** Current PDMDEVHLP version number. */
5258	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 18, 0)
5259
5260
5261	/**
5262	* PDM Device API - R0 Variant.
5263	*/
5264	typedef struct PDMDEVHLPR0
5265	{
5266	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5267	uint32_t u32Version;
5268
5269	/**
5270	* Sets up ring-0 callback handlers for an I/O port range.
5271	*
5272	* The range must have been created in ring-3 first using
5273	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5274	*
5275	* @returns VBox status.
5276	* @param pDevIns The device instance to register the ports with.
5277	* @param hIoPorts The I/O port range handle.
5278	* @param pfnOut Pointer to function which is gonna handle OUT
5279	* operations. Optional.
5280	* @param pfnIn Pointer to function which is gonna handle IN operations.
5281	* Optional.
5282	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5283	* operations. Optional.
5284	* @param pfnInStr Pointer to function which is gonna handle string IN
5285	* operations. Optional.
5286	* @param pvUser User argument to pass to the callbacks.
5287	*
5288	* @remarks Caller enters the device critical section prior to invoking the
5289	* registered callback methods.
5290	*
5291	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5292	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5293	*/
5294	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5295	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5296	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5297	void *pvUser));
5298
5299	/**
5300	* Sets up ring-0 callback handlers for an MMIO region.
5301	*
5302	* The region must have been created in ring-3 first using
5303	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5304	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5305	*
5306	* @returns VBox status.
5307	* @param pDevIns The device instance to register the ports with.
5308	* @param hRegion The MMIO region handle.
5309	* @param pfnWrite Pointer to function which is gonna handle Write
5310	* operations.
5311	* @param pfnRead Pointer to function which is gonna handle Read
5312	* operations.
5313	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5314	* operations. (optional)
5315	* @param pvUser User argument to pass to the callbacks.
5316	*
5317	* @remarks Caller enters the device critical section prior to invoking the
5318	* registered callback methods.
5319	*
5320	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5321	* PDMDevHlpMmioUnmap().
5322	*/
5323	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5324	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5325
5326	/**
5327	* Sets up a ring-0 mapping for an MMIO2 region.
5328	*
5329	* The region must have been created in ring-3 first using
5330	* PDMDevHlpMmio2Create().
5331	*
5332	* @returns VBox status.
5333	* @param pDevIns The device instance to register the ports with.
5334	* @param hRegion The MMIO2 region handle.
5335	* @param offSub Start of what to map into ring-0. Must be page aligned.
5336	* @param cbSub Number of bytes to map into ring-0. Must be page
5337	* aligned. Zero is an alias for everything.
5338	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5339	*
5340	* @thread EMT(0)
5341	* @note Only available at VM creation time.
5342	*
5343	* @sa PDMDevHlpMmio2Create().
5344	*/
5345	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5346	void **ppvMapping));
5347
5348	/**
5349	* Bus master physical memory read from the given PCI device.
5350	*
5351	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5352	* VERR_EM_MEMORY.
5353	* @param pDevIns The device instance.
5354	* @param pPciDev The PCI device structure. If NULL the default
5355	* PCI device for this device instance is used.
5356	* @param GCPhys Physical address start reading from.
5357	* @param pvBuf Where to put the read bits.
5358	* @param cbRead How many bytes to read.
5359	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5360	* @thread Any thread, but the call may involve the emulation thread.
5361	*/
5362	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5363	void *pvBuf, size_t cbRead, uint32_t fFlags));
5364
5365	/**
5366	* Bus master physical memory write from the given PCI device.
5367	*
5368	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5369	* VERR_EM_MEMORY.
5370	* @param pDevIns The device instance.
5371	* @param pPciDev The PCI device structure. If NULL the default
5372	* PCI device for this device instance is used.
5373	* @param GCPhys Physical address to write to.
5374	* @param pvBuf What to write.
5375	* @param cbWrite How many bytes to write.
5376	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5377	* @thread Any thread, but the call may involve the emulation thread.
5378	*/
5379	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5380	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5381
5382	/**
5383	* Set the IRQ for the given PCI device.
5384	*
5385	* @param pDevIns Device instance.
5386	* @param pPciDev The PCI device structure. If NULL the default
5387	* PCI device for this device instance is used.
5388	* @param iIrq IRQ number to set.
5389	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5390	* @thread Any thread, but will involve the emulation thread.
5391	*/
5392	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5393
5394	/**
5395	* Set ISA IRQ for a device.
5396	*
5397	* @param pDevIns Device instance.
5398	* @param iIrq IRQ number to set.
5399	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5400	* @thread Any thread, but will involve the emulation thread.
5401	*/
5402	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5403
5404	/**
5405	* Read physical memory.
5406	*
5407	* @returns VINF_SUCCESS (for now).
5408	* @param pDevIns Device instance.
5409	* @param GCPhys Physical address start reading from.
5410	* @param pvBuf Where to put the read bits.
5411	* @param cbRead How many bytes to read.
5412	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5413	*/
5414	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5415
5416	/**
5417	* Write to physical memory.
5418	*
5419	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5420	* @param pDevIns Device instance.
5421	* @param GCPhys Physical address to write to.
5422	* @param pvBuf What to write.
5423	* @param cbWrite How many bytes to write.
5424	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5425	*/
5426	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5427
5428	/**
5429	* Checks if the Gate A20 is enabled or not.
5430	*
5431	* @returns true if A20 is enabled.
5432	* @returns false if A20 is disabled.
5433	* @param pDevIns Device instance.
5434	* @thread The emulation thread.
5435	*/
5436	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5437
5438	/**
5439	* Gets the VM state.
5440	*
5441	* @returns VM state.
5442	* @param pDevIns The device instance.
5443	* @thread Any thread (just keep in mind that it's volatile info).
5444	*/
5445	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5446
5447	/**
5448	* Gets the VM handle. Restricted API.
5449	*
5450	* @returns VM Handle.
5451	* @param pDevIns Device instance.
5452	*/
5453	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5454
5455	/**
5456	* Gets the VMCPU handle. Restricted API.
5457	*
5458	* @returns VMCPU Handle.
5459	* @param pDevIns The device instance.
5460	*/
5461	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5462
5463	/**
5464	* The the VM CPU ID of the current thread (restricted API).
5465	*
5466	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5467	* @param pDevIns The device instance.
5468	*/
5469	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5470
5471	/** @name Timer handle method wrappers
5472	* @{ */
5473	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5474	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5475	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5476	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5477	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5478	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5479	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5480	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5481	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5482	/** Takes the clock lock then enters the specified critical section. */
5483	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5484	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5485	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5486	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5487	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5488	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5489	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5490	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5491	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5492	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5493	/** @} */
5494
5495	/**
5496	* Get the current virtual clock time in a VM. The clock frequency must be
5497	* queried separately.
5498	*
5499	* @returns Current clock time.
5500	* @param pDevIns The device instance.
5501	*/
5502	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5503
5504	/**
5505	* Get the frequency of the virtual clock.
5506	*
5507	* @returns The clock frequency (not variable at run-time).
5508	* @param pDevIns The device instance.
5509	*/
5510	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5511
5512	/**
5513	* Get the current virtual clock time in a VM, in nanoseconds.
5514	*
5515	* @returns Current clock time (in ns).
5516	* @param pDevIns The device instance.
5517	*/
5518	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5519
5520	/** @name Exported PDM Queue Functions
5521	* @{ */
5522	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5523	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5524	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5525	/** @} */
5526
5527	/** @name PDM Task
5528	* @{ */
5529	/**
5530	* Triggers the running the given task.
5531	*
5532	* @returns VBox status code.
5533	* @retval VINF_ALREADY_POSTED is the task is already pending.
5534	* @param pDevIns The device instance.
5535	* @param hTask The task to trigger.
5536	* @thread Any thread.
5537	*/
5538	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5539	/** @} */
5540
5541	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5542	* These semaphores can be signalled from ring-0.
5543	* @{ */
5544	/** @sa SUPSemEventSignal */
5545	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5546	/** @sa SUPSemEventWaitNoResume */
5547	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5548	/** @sa SUPSemEventWaitNsAbsIntr */
5549	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5550	/** @sa SUPSemEventWaitNsRelIntr */
5551	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5552	/** @sa SUPSemEventGetResolution */
5553	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5554	/** @} */
5555
5556	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5557	* These semaphores can be signalled from ring-0.
5558	* @{ */
5559	/** @sa SUPSemEventMultiSignal */
5560	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5561	/** @sa SUPSemEventMultiReset */
5562	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5563	/** @sa SUPSemEventMultiWaitNoResume */
5564	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5565	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5566	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5567	/** @sa SUPSemEventMultiWaitNsRelIntr */
5568	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5569	/** @sa SUPSemEventMultiGetResolution */
5570	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5571	/** @} */
5572
5573	/**
5574	* Gets the NOP critical section.
5575	*
5576	* @returns The ring-3 address of the NOP critical section.
5577	* @param pDevIns The device instance.
5578	*/
5579	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5580
5581	/**
5582	* Changes the device level critical section from the automatically created
5583	* default to one desired by the device constructor.
5584	*
5585	* Must first be done in ring-3.
5586	*
5587	* @returns VBox status code.
5588	* @param pDevIns The device instance.
5589	* @param pCritSect The critical section to use. NULL is not
5590	* valid, instead use the NOP critical
5591	* section.
5592	*/
5593	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5594
5595	/** @name Exported PDM Critical Section Functions
5596	* @{ */
5597	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5598	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5599	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5600	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5601	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5602	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5603	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5604	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5605	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5606	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5607	/** @} */
5608
5609	/** @name Exported PDM Read/Write Critical Section Functions
5610	* @{ */
5611	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5612	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5613	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5614	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5615	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5616
5617	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5618	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5619	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5620	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5621	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5622
5623	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5624	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5625	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5626	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5627	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5628	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5629	/** @} */
5630
5631	/**
5632	* Gets the trace buffer handle.
5633	*
5634	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5635	* really inteded for direct usage, thus no inline wrapper function.
5636	*
5637	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5638	* @param pDevIns The device instance.
5639	*/
5640	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5641
5642	/**
5643	* Sets up the PCI bus for the ring-0 context.
5644	*
5645	* This must be called after ring-3 has registered the PCI bus using
5646	* PDMDevHlpPCIBusRegister().
5647	*
5648	* @returns VBox status code.
5649	* @param pDevIns The device instance.
5650	* @param pPciBusReg The PCI bus registration information for ring-0,
5651	* considered volatile and copied.
5652	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5653	*/
5654	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5655
5656	/**
5657	* Sets up the IOMMU for the ring-0 context.
5658	*
5659	* This must be called after ring-3 has registered the IOMMU using
5660	* PDMDevHlpIommuRegister().
5661	*
5662	* @returns VBox status code.
5663	* @param pDevIns The device instance.
5664	* @param pIommuReg The IOMMU registration information for ring-0,
5665	* considered volatile and copied.
5666	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5667	*/
5668	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5669
5670	/**
5671	* Sets up the PIC for the ring-0 context.
5672	*
5673	* This must be called after ring-3 has registered the PIC using
5674	* PDMDevHlpPICRegister().
5675	*
5676	* @returns VBox status code.
5677	* @param pDevIns The device instance.
5678	* @param pPicReg The PIC registration information for ring-0,
5679	* considered volatile and copied.
5680	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5681	*/
5682	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5683
5684	/**
5685	* Sets up the APIC for the ring-0 context.
5686	*
5687	* This must be called after ring-3 has registered the APIC using
5688	* PDMDevHlpApicRegister().
5689	*
5690	* @returns VBox status code.
5691	* @param pDevIns The device instance.
5692	*/
5693	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5694
5695	/**
5696	* Sets up the IOAPIC for the ring-0 context.
5697	*
5698	* This must be called after ring-3 has registered the PIC using
5699	* PDMDevHlpIoApicRegister().
5700	*
5701	* @returns VBox status code.
5702	* @param pDevIns The device instance.
5703	* @param pIoApicReg The PIC registration information for ring-0,
5704	* considered volatile and copied.
5705	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5706	*/
5707	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5708
5709	/**
5710	* Sets up the HPET for the ring-0 context.
5711	*
5712	* This must be called after ring-3 has registered the PIC using
5713	* PDMDevHlpHpetRegister().
5714	*
5715	* @returns VBox status code.
5716	* @param pDevIns The device instance.
5717	* @param pHpetReg The PIC registration information for ring-0,
5718	* considered volatile and copied.
5719	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5720	*/
5721	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5722
5723	/**
5724	* Temporarily turns off the access monitoring of a page within a monitored
5725	* physical write/all page access handler region.
5726	*
5727	* Use this when no further \#PFs are required for that page. Be aware that
5728	* a page directory sync might reset the flags, and turn on access monitoring
5729	* for the page.
5730	*
5731	* The caller must do required page table modifications.
5732	*
5733	* @returns VBox status code.
5734	* @param pDevIns The device instance.
5735	* @param GCPhys The start address of the access handler. This
5736	* must be a fully page aligned range or we risk
5737	* messing up other handlers installed for the
5738	* start and end pages.
5739	* @param GCPhysPage The physical address of the page to turn off
5740	* access monitoring for.
5741	*/
5742	DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
5743
5744	/**
5745	* Mapping an MMIO2 page in place of an MMIO page for direct access.
5746	*
5747	* This is a special optimization used by the VGA device. Call
5748	* PDMDevHlpMmioResetRegion() to undo the mapping.
5749	*
5750	* @returns VBox status code. This API may return VINF_SUCCESS even if no
5751	* remapping is made.
5752	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
5753	*
5754	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
5755	* associated with.
5756	* @param hRegion The handle to the MMIO region.
5757	* @param offRegion The offset into @a hRegion of the page to be
5758	* remapped.
5759	* @param hMmio2 The MMIO2 handle.
5760	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
5761	* mapping.
5762	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
5763	* for the time being.
5764	*/
5765	DECLR0CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
5766	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
5767
5768	/**
5769	* Reset a previously modified MMIO region; restore the access flags.
5770	*
5771	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
5772	* intended for some ancient VGA hack. However, it would be great to extend it
5773	* beyond VT-x and/or nested-paging.
5774	*
5775	* @returns VBox status code.
5776	*
5777	* @param pDevIns The device instance @a hRegion is associated with.
5778	* @param hRegion The handle to the MMIO region.
5779	*/
5780	DECLR0CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
5781
5782	/** Space reserved for future members.
5783	* @{ */
5784	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5785	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5786	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5787	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5788	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5789	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5790	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5791	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5792	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5793	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5794	/** @} */
5795
5796	/** Just a safety precaution. */
5797	uint32_t u32TheEnd;
5798	} PDMDEVHLPR0;
5799	/** Pointer PDM Device R0 API. */
5800	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5801	/** Pointer PDM Device GC API. */
5802	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5803
5804	/** Current PDMDEVHLP version number. */
5805	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 24, 0)
5806
5807
5808	/**
5809	* PDM Device Instance.
5810	*/
5811	typedef struct PDMDEVINSR3
5812	{
5813	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5814	uint32_t u32Version;
5815	/** Device instance number. */
5816	uint32_t iInstance;
5817	/** Size of the ring-3, raw-mode and shared bits. */
5818	uint32_t cbRing3;
5819	/** Set if ring-0 context is enabled. */
5820	bool fR0Enabled;
5821	/** Set if raw-mode context is enabled. */
5822	bool fRCEnabled;
5823	/** Alignment padding. */
5824	bool afReserved[2];
5825	/** Pointer the HC PDM Device API. */
5826	PCPDMDEVHLPR3 pHlpR3;
5827	/** Pointer to the shared device instance data. */
5828	RTR3PTR pvInstanceDataR3;
5829	/** Pointer to the device instance data for ring-3. */
5830	RTR3PTR pvInstanceDataForR3;
5831	/** The critical section for the device.
5832	*
5833	* TM and IOM will enter this critical section before calling into the device
5834	* code. PDM will when doing power on, power off, reset, suspend and resume
5835	* notifications. SSM will currently not, but this will be changed later on.
5836	*
5837	* The device gets a critical section automatically assigned to it before
5838	* the constructor is called. If the constructor wishes to use a different
5839	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5840	* very early on.
5841	*/
5842	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5843	/** Pointer to device registration structure. */
5844	R3PTRTYPE(PCPDMDEVREG) pReg;
5845	/** Configuration handle. */
5846	R3PTRTYPE(PCFGMNODE) pCfg;
5847	/** The base interface of the device.
5848	*
5849	* The device constructor initializes this if it has any
5850	* device level interfaces to export. To obtain this interface
5851	* call PDMR3QueryDevice(). */
5852	PDMIBASE IBase;
5853
5854	/** Tracing indicator. */
5855	uint32_t fTracing;
5856	/** The tracing ID of this device. */
5857	uint32_t idTracing;
5858
5859	/** Ring-3 pointer to the raw-mode device instance. */
5860	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5861	/** Raw-mode address of the raw-mode device instance. */
5862	RTRGPTR pDevInsForRC;
5863	/** Ring-3 pointer to the raw-mode instance data. */
5864	RTR3PTR pvInstanceDataForRCR3;
5865
5866	/** PCI device structure size. */
5867	uint32_t cbPciDev;
5868	/** Number of PCI devices in apPciDevs. */
5869	uint32_t cPciDevs;
5870	/** Pointer to the PCI devices for this device.
5871	* (Allocated after the shared instance data.)
5872	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5873	* two devices ever needing it can use cbPciDev and do the address
5874	* calculations that for entries 8+. */
5875	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5876
5877	/** Temporarily. */
5878	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5879	/** Temporarily. */
5880	RTR0PTR pvInstanceDataR0;
5881	/** Temporarily. */
5882	RTRCPTR pvInstanceDataRC;
5883	/** Align the internal data more naturally. */
5884	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5885
5886	/** Internal data. */
5887	union
5888	{
5889	#ifdef PDMDEVINSINT_DECLARED
5890	PDMDEVINSINTR3 s;
5891	#endif
5892	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
5893	} Internal;
5894
5895	/** Device instance data for ring-3. The size of this area is defined
5896	* in the PDMDEVREG::cbInstanceR3 field. */
5897	char achInstanceData[8];
5898	} PDMDEVINSR3;
5899
5900	/** Current PDMDEVINSR3 version number. */
5901	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5902
5903	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5904	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5905
5906
5907	/**
5908	* PDM ring-0 device instance.
5909	*/
5910	typedef struct PDMDEVINSR0
5911	{
5912	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5913	uint32_t u32Version;
5914	/** Device instance number. */
5915	uint32_t iInstance;
5916
5917	/** Pointer the HC PDM Device API. */
5918	PCPDMDEVHLPR0 pHlpR0;
5919	/** Pointer to the shared device instance data. */
5920	RTR0PTR pvInstanceDataR0;
5921	/** Pointer to the device instance data for ring-0. */
5922	RTR0PTR pvInstanceDataForR0;
5923	/** The critical section for the device.
5924	*
5925	* TM and IOM will enter this critical section before calling into the device
5926	* code. PDM will when doing power on, power off, reset, suspend and resume
5927	* notifications. SSM will currently not, but this will be changed later on.
5928	*
5929	* The device gets a critical section automatically assigned to it before
5930	* the constructor is called. If the constructor wishes to use a different
5931	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5932	* very early on.
5933	*/
5934	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5935	/** Pointer to the ring-0 device registration structure. */
5936	R0PTRTYPE(PCPDMDEVREGR0) pReg;
5937	/** Ring-3 address of the ring-3 device instance. */
5938	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5939	/** Ring-0 pointer to the ring-3 device instance. */
5940	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5941	/** Ring-0 pointer to the ring-3 instance data. */
5942	RTR0PTR pvInstanceDataForR3R0;
5943	/** Raw-mode address of the raw-mode device instance. */
5944	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5945	/** Ring-0 pointer to the raw-mode device instance. */
5946	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5947	/** Ring-0 pointer to the raw-mode instance data. */
5948	RTR0PTR pvInstanceDataForRCR0;
5949
5950	/** PCI device structure size. */
5951	uint32_t cbPciDev;
5952	/** Number of PCI devices in apPciDevs. */
5953	uint32_t cPciDevs;
5954	/** Pointer to the PCI devices for this device.
5955	* (Allocated after the shared instance data.)
5956	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5957	* two devices ever needing it can use cbPciDev and do the address
5958	* calculations that for entries 8+. */
5959	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5960
5961	/** Align the internal data more naturally. */
5962	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5963
5964	/** Internal data. */
5965	union
5966	{
5967	#ifdef PDMDEVINSINT_DECLARED
5968	PDMDEVINSINTR0 s;
5969	#endif
5970	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
5971	} Internal;
5972
5973	/** Device instance data for ring-0. The size of this area is defined
5974	* in the PDMDEVREG::cbInstanceR0 field. */
5975	char achInstanceData[8];
5976	} PDMDEVINSR0;
5977
5978	/** Current PDMDEVINSR0 version number. */
5979	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5980
5981
5982	/**
5983	* PDM raw-mode device instance.
5984	*/
5985	typedef struct PDMDEVINSRC
5986	{
5987	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5988	uint32_t u32Version;
5989	/** Device instance number. */
5990	uint32_t iInstance;
5991
5992	/** Pointer the HC PDM Device API. */
5993	PCPDMDEVHLPRC pHlpRC;
5994	/** Pointer to the shared device instance data. */
5995	RTRGPTR pvInstanceDataRC;
5996	/** Pointer to the device instance data for raw-mode. */
5997	RTRGPTR pvInstanceDataForRC;
5998	/** The critical section for the device.
5999	*
6000	* TM and IOM will enter this critical section before calling into the device
6001	* code. PDM will when doing power on, power off, reset, suspend and resume
6002	* notifications. SSM will currently not, but this will be changed later on.
6003	*
6004	* The device gets a critical section automatically assigned to it before
6005	* the constructor is called. If the constructor wishes to use a different
6006	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6007	* very early on.
6008	*/
6009	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
6010	/** Pointer to the raw-mode device registration structure. */
6011	RGPTRTYPE(PCPDMDEVREGRC) pReg;
6012
6013	/** PCI device structure size. */
6014	uint32_t cbPciDev;
6015	/** Number of PCI devices in apPciDevs. */
6016	uint32_t cPciDevs;
6017	/** Pointer to the PCI devices for this device.
6018	* (Allocated after the shared instance data.) */
6019	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6020
6021	/** Align the internal data more naturally. */
6022	uint32_t au32Padding[14];
6023
6024	/** Internal data. */
6025	union
6026	{
6027	#ifdef PDMDEVINSINT_DECLARED
6028	PDMDEVINSINTRC s;
6029	#endif
6030	uint8_t padding[0x10];
6031	} Internal;
6032
6033	/** Device instance data for ring-0. The size of this area is defined
6034	* in the PDMDEVREG::cbInstanceR0 field. */
6035	char achInstanceData[8];
6036	} PDMDEVINSRC;
6037
6038	/** Current PDMDEVINSR0 version number. */
6039	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
6040
6041
6042	/** @def PDM_DEVINS_VERSION
6043	* Current PDMDEVINS version number. */
6044	/** @typedef PDMDEVINS
6045	* The device instance structure for the current context. */
6046	#ifdef IN_RING3
6047	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
6048	typedef PDMDEVINSR3 PDMDEVINS;
6049	#elif defined(IN_RING0)
6050	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
6051	typedef PDMDEVINSR0 PDMDEVINS;
6052	#elif defined(IN_RC)
6053	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
6054	typedef PDMDEVINSRC PDMDEVINS;
6055	#else
6056	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
6057	#endif
6058
6059	/**
6060	* Get the pointer to an PCI device.
6061	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6062	*/
6063	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
6064	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
6065	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
6066
6067	/**
6068	* Calc the pointer to of a given PCI device.
6069	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6070	*/
6071	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
6072	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
6073	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
6074	: (PPDMPCIDEV)NULL )
6075
6076
6077	/**
6078	* Checks the structure versions of the device instance and device helpers,
6079	* returning if they are incompatible.
6080	*
6081	* This is for use in the constructor.
6082	*
6083	* @param pDevIns The device instance pointer.
6084	*/
6085	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
6086	do \
6087	{ \
6088	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6089	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6090	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6091	VERR_PDM_DEVINS_VERSION_MISMATCH); \
6092	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6093	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6094	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
6095	} while (0)
6096
6097	/**
6098	* Quietly checks the structure versions of the device instance and device
6099	* helpers, returning if they are incompatible.
6100	*
6101	* This is for use in the destructor.
6102	*
6103	* @param pDevIns The device instance pointer.
6104	*/
6105	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
6106	do \
6107	{ \
6108	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6109	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
6110	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
6111	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
6112	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
6113	} while (0)
6114
6115	/**
6116	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
6117	* constructor - returns on failure.
6118	*
6119	* This should be invoked after having initialized the instance data
6120	* sufficiently for the correct operation of the destructor. The destructor is
6121	* always called!
6122	*
6123	* @param pDevIns Pointer to the PDM device instance.
6124	* @param pszValidValues Patterns describing the valid value names. See
6125	* RTStrSimplePatternMultiMatch for details on the
6126	* pattern syntax.
6127	* @param pszValidNodes Patterns describing the valid node (key) names.
6128	* Pass empty string if no valid nodes.
6129	*/
6130	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
6131	do \
6132	{ \
6133	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
6134	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
6135	if (RT_SUCCESS(rcValCfg)) \
6136	{ /* likely */ } else return rcValCfg; \
6137	} while (0)
6138
6139	/** @def PDMDEV_ASSERT_EMT
6140	* Assert that the current thread is the emulation thread.
6141	*/
6142	#ifdef VBOX_STRICT
6143	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6144	#else
6145	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
6146	#endif
6147
6148	/** @def PDMDEV_ASSERT_OTHER
6149	* Assert that the current thread is NOT the emulation thread.
6150	*/
6151	#ifdef VBOX_STRICT
6152	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6153	#else
6154	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
6155	#endif
6156
6157	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
6158	* Assert that the current thread is owner of the VM lock.
6159	*/
6160	#ifdef VBOX_STRICT
6161	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6162	#else
6163	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
6164	#endif
6165
6166	/** @def PDMDEV_SET_ERROR
6167	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
6168	*/
6169	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
6170	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
6171
6172	/** @def PDMDEV_SET_RUNTIME_ERROR
6173	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
6174	*/
6175	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
6176	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
6177
6178	/** @def PDMDEVINS_2_RCPTR
6179	* Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
6180	*/
6181	#ifdef IN_RC
6182	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
6183	#else
6184	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
6185	#endif
6186
6187	/** @def PDMDEVINS_2_R3PTR
6188	* Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
6189	*/
6190	#ifdef IN_RING3
6191	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
6192	#else
6193	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
6194	#endif
6195
6196	/** @def PDMDEVINS_2_R0PTR
6197	* Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
6198	*/
6199	#ifdef IN_RING0
6200	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
6201	#else
6202	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
6203	#endif
6204
6205	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
6206	* Converts a PDM device instance data pointer to a ring-0 one.
6207	* @deprecated
6208	*/
6209	#ifdef IN_RING0
6210	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
6211	#else
6212	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
6213	#endif
6214
6215
6216	/** @def PDMDEVINS_2_DATA
6217	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
6218	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
6219	*
6220	* @note Do no use this macro in common code working on a core structure which
6221	* device specific code has expanded.
6222	*/
6223	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6224	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
6225	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6226	{ \
6227	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
6228	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
6229	return pLambdaRet; \
6230	}(a_pDevIns))
6231	#else
6232	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
6233	#endif
6234
6235	/** @def PDMDEVINS_2_DATA_CC
6236	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
6237	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
6238	*
6239	* @note Do no use this macro in common code working on a core structure which
6240	* device specific code has expanded.
6241	*/
6242	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6243	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
6244	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6245	{ \
6246	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
6247	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
6248	return pLambdaRet; \
6249	}(a_pDevIns))
6250	#else
6251	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
6252	#endif
6253
6254
6255	#ifdef IN_RING3
6256
6257	/**
6258	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
6259	*/
6260	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6261	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
6262	PIOMIOPORTHANDLE phIoPorts)
6263	{
6264	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6265	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6266	if (RT_SUCCESS(rc))
6267	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6268	return rc;
6269	}
6270
6271	/**
6272	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
6273	*/
6274	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6275	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6276	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6277	{
6278	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6279	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6280	if (RT_SUCCESS(rc))
6281	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6282	return rc;
6283	}
6284
6285	/**
6286	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
6287	*/
6288	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6289	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6290	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6291	{
6292	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6293	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6294	if (RT_SUCCESS(rc))
6295	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6296	return rc;
6297	}
6298
6299	/**
6300	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
6301	*/
6302	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6303	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6304	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6305	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6306	{
6307	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6308	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6309	if (RT_SUCCESS(rc))
6310	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6311	return rc;
6312	}
6313
6314	/**
6315	* @sa PDMDevHlpIoPortCreateEx
6316	*/
6317	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6318	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6319	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6320	{
6321	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
6322	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6323	}
6324
6325
6326	/**
6327	* @sa PDMDevHlpIoPortCreateEx
6328	*/
6329	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6330	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6331	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6332	{
6333	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6334	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6335	}
6336
6337	/**
6338	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6339	*/
6340	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6341	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6342	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6343	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6344	{
6345	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6346	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6347	}
6348
6349	/**
6350	* @copydoc PDMDEVHLPR3::pfnIoPortMap
6351	*/
6352	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6353	{
6354	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6355	}
6356
6357	/**
6358	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6359	*/
6360	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6361	{
6362	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6363	}
6364
6365	/**
6366	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6367	*/
6368	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6369	{
6370	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6371	}
6372
6373
6374	#endif /* IN_RING3 */
6375	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6376
6377	/**
6378	* @sa PDMDevHlpIoPortSetUpContextEx
6379	*/
6380	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6381	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6382	{
6383	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6384	}
6385
6386	/**
6387	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6388	*/
6389	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6390	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6391	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6392	{
6393	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6394	}
6395
6396	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6397	#ifdef IN_RING3
6398
6399	/**
6400	* @sa PDMDevHlpMmioCreateEx
6401	*/
6402	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6403	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6404	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6405	{
6406	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6407	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6408	}
6409
6410	/**
6411	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6412	*/
6413	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6414	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6415	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6416	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6417	{
6418	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6419	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6420	}
6421
6422	/**
6423	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6424	*/
6425	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6426	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6427	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6428	{
6429	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6430	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6431	if (RT_SUCCESS(rc))
6432	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6433	return rc;
6434	}
6435
6436	/**
6437	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6438	*/
6439	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6440	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6441	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6442	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6443	{
6444	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6445	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6446	if (RT_SUCCESS(rc))
6447	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6448	return rc;
6449	}
6450
6451	/**
6452	* @copydoc PDMDEVHLPR3::pfnMmioMap
6453	*/
6454	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6455	{
6456	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6457	}
6458
6459	/**
6460	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6461	*/
6462	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6463	{
6464	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6465	}
6466
6467	/**
6468	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6469	*/
6470	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6471	{
6472	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6473	}
6474
6475	/**
6476	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6477	*/
6478	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6479	{
6480	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6481	}
6482
6483	#endif /* IN_RING3 */
6484	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6485
6486	/**
6487	* @sa PDMDevHlpMmioSetUpContextEx
6488	*/
6489	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6490	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6491	{
6492	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6493	}
6494
6495	/**
6496	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6497	*/
6498	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6499	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6500	{
6501	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6502	}
6503
6504	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6505	#ifdef IN_RING3
6506
6507	/**
6508	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6509	*/
6510	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6511	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6512	{
6513	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6514	}
6515
6516	/**
6517	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6518	*/
6519	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6520	{
6521	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6522	}
6523
6524	/**
6525	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6526	*/
6527	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6528	{
6529	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6530	}
6531
6532	/**
6533	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6534	*/
6535	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6536	{
6537	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6538	}
6539
6540	/**
6541	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6542	*/
6543	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6544	{
6545	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6546	}
6547
6548	#endif /* IN_RING3 */
6549
6550	/**
6551	* @copydoc PDMDEVHLPR3::pfnMmioMapMmio2Page
6552	*/
6553	DECLINLINE(RTGCPHYS) PDMDevHlpMmioMapMmio2Page(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6554	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags)
6555	{
6556	return pDevIns->CTX_SUFF(pHlp)->pfnMmioMapMmio2Page(pDevIns, hRegion, offRegion, hMmio2, offMmio2, fPageFlags);
6557	}
6558
6559	/**
6560	* @copydoc PDMDEVHLPR3::pfnMmioResetRegion
6561	*/
6562	DECLINLINE(RTGCPHYS) PDMDevHlpMmioResetRegion(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6563	{
6564	return pDevIns->CTX_SUFF(pHlp)->pfnMmioResetRegion(pDevIns, hRegion);
6565	}
6566
6567	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6568
6569	/**
6570	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6571	*/
6572	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6573	size_t offSub, size_t cbSub, void **ppvMapping)
6574	{
6575	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6576	}
6577
6578	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6579	#ifdef IN_RING3
6580
6581	/**
6582	* @copydoc PDMDEVHLPR3::pfnROMRegister
6583	*/
6584	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6585	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6586	{
6587	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6588	}
6589
6590	/**
6591	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6592	*/
6593	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6594	{
6595	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6596	}
6597
6598	/**
6599	* Register a save state data unit.
6600	*
6601	* @returns VBox status.
6602	* @param pDevIns The device instance.
6603	* @param uVersion Data layout version number.
6604	* @param cbGuess The approximate amount of data in the unit.
6605	* Only for progress indicators.
6606	* @param pfnSaveExec Execute save callback, optional.
6607	* @param pfnLoadExec Execute load callback, optional.
6608	*/
6609	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6610	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6611	{
6612	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6613	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6614	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6615	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6616	}
6617
6618	/**
6619	* Register a save state data unit with a live save callback as well.
6620	*
6621	* @returns VBox status.
6622	* @param pDevIns The device instance.
6623	* @param uVersion Data layout version number.
6624	* @param cbGuess The approximate amount of data in the unit.
6625	* Only for progress indicators.
6626	* @param pfnLiveExec Execute live callback, optional.
6627	* @param pfnSaveExec Execute save callback, optional.
6628	* @param pfnLoadExec Execute load callback, optional.
6629	*/
6630	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6631	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6632	{
6633	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6634	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6635	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6636	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6637	}
6638
6639	/**
6640	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6641	*/
6642	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6643	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6644	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6645	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6646	{
6647	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6648	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6649	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6650	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6651	}
6652
6653	/**
6654	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6655	*/
6656	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6657	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6658	{
6659	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6660	}
6661
6662	#endif /* IN_RING3 */
6663
6664	/**
6665	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6666	*/
6667	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6668	{
6669	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6670	}
6671
6672	/**
6673	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6674	*/
6675	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6676	{
6677	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6678	}
6679
6680	/**
6681	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6682	*/
6683	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6684	{
6685	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6686	}
6687
6688	/**
6689	* @copydoc PDMDEVHLPR3::pfnTimerGet
6690	*/
6691	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6692	{
6693	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6694	}
6695
6696	/**
6697	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6698	*/
6699	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6700	{
6701	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6702	}
6703
6704	/**
6705	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6706	*/
6707	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6708	{
6709	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6710	}
6711
6712	/**
6713	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6714	*/
6715	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6716	{
6717	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6718	}
6719
6720	/**
6721	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6722	*/
6723	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6724	{
6725	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6726	}
6727
6728	/**
6729	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
6730	*/
6731	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6732	{
6733	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6734	}
6735
6736	/**
6737	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6738	*/
6739	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6740	{
6741	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6742	}
6743
6744	/**
6745	* @copydoc PDMDEVHLPR3::pfnTimerSet
6746	*/
6747	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6748	{
6749	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6750	}
6751
6752	/**
6753	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6754	*/
6755	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6756	{
6757	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6758	}
6759
6760	/**
6761	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6762	*/
6763	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6764	{
6765	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6766	}
6767
6768	/**
6769	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6770	*/
6771	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6772	{
6773	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6774	}
6775
6776	/**
6777	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6778	*/
6779	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6780	{
6781	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6782	}
6783
6784	/**
6785	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6786	*/
6787	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6788	{
6789	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6790	}
6791
6792	/**
6793	* @copydoc PDMDEVHLPR3::pfnTimerStop
6794	*/
6795	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6796	{
6797	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6798	}
6799
6800	/**
6801	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6802	*/
6803	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6804	{
6805	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6806	}
6807
6808	/**
6809	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6810	*/
6811	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6812	{
6813	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6814	}
6815
6816	#ifdef IN_RING3
6817
6818	/**
6819	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6820	*/
6821	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6822	{
6823	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6824	}
6825
6826	/**
6827	* @copydoc PDMDEVHLPR3::pfnTimerSave
6828	*/
6829	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6830	{
6831	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6832	}
6833
6834	/**
6835	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6836	*/
6837	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6838	{
6839	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6840	}
6841
6842	/**
6843	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6844	*/
6845	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6846	{
6847	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6848	}
6849
6850	/**
6851	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6852	*/
6853	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6854	{
6855	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6856	}
6857
6858	#endif
6859
6860	/**
6861	* Read physical memory - unknown data usage.
6862	*
6863	* @returns VINF_SUCCESS (for now).
6864	* @param pDevIns The device instance.
6865	* @param GCPhys Physical address start reading from.
6866	* @param pvBuf Where to put the read bits.
6867	* @param cbRead How many bytes to read.
6868	* @thread Any thread, but the call may involve the emulation thread.
6869	*/
6870	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6871	{
6872	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6873	}
6874
6875	/**
6876	* Write to physical memory - unknown data usage.
6877	*
6878	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6879	* @param pDevIns The device instance.
6880	* @param GCPhys Physical address to write to.
6881	* @param pvBuf What to write.
6882	* @param cbWrite How many bytes to write.
6883	* @thread Any thread, but the call may involve the emulation thread.
6884	*/
6885	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6886	{
6887	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6888	}
6889
6890	/**
6891	* Read physical memory - reads meta data processed by the device.
6892	*
6893	* @returns VINF_SUCCESS (for now).
6894	* @param pDevIns The device instance.
6895	* @param GCPhys Physical address start reading from.
6896	* @param pvBuf Where to put the read bits.
6897	* @param cbRead How many bytes to read.
6898	* @thread Any thread, but the call may involve the emulation thread.
6899	*/
6900	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6901	{
6902	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6903	}
6904
6905	/**
6906	* Write to physical memory - written data was created/altered by the device.
6907	*
6908	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6909	* @param pDevIns The device instance.
6910	* @param GCPhys Physical address to write to.
6911	* @param pvBuf What to write.
6912	* @param cbWrite How many bytes to write.
6913	* @thread Any thread, but the call may involve the emulation thread.
6914	*/
6915	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6916	{
6917	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6918	}
6919
6920	/**
6921	* Read physical memory - read data will not be touched by the device.
6922	*
6923	* @returns VINF_SUCCESS (for now).
6924	* @param pDevIns The device instance.
6925	* @param GCPhys Physical address start reading from.
6926	* @param pvBuf Where to put the read bits.
6927	* @param cbRead How many bytes to read.
6928	* @thread Any thread, but the call may involve the emulation thread.
6929	*/
6930	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6931	{
6932	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6933	}
6934
6935	/**
6936	* Write to physical memory - written data was not touched/created by the device.
6937	*
6938	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6939	* @param pDevIns The device instance.
6940	* @param GCPhys Physical address to write to.
6941	* @param pvBuf What to write.
6942	* @param cbWrite How many bytes to write.
6943	* @thread Any thread, but the call may involve the emulation thread.
6944	*/
6945	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6946	{
6947	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6948	}
6949
6950	#ifdef IN_RING3
6951
6952	/**
6953	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6954	*/
6955	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6956	{
6957	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6958	}
6959
6960	/**
6961	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6962	*/
6963	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6964	PPGMPAGEMAPLOCK pLock)
6965	{
6966	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6967	}
6968
6969	/**
6970	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6971	*/
6972	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6973	{
6974	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6975	}
6976
6977	/**
6978	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6979	*/
6980	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6981	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6982	{
6983	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6984	}
6985
6986	/**
6987	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6988	*/
6989	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6990	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6991	{
6992	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6993	}
6994
6995	/**
6996	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6997	*/
6998	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6999	{
7000	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
7001	}
7002
7003	/**
7004	* @copydoc PDMDEVHLPR3::pfnPhysIsGCPhysNormal
7005	*/
7006	DECLINLINE(bool) PDMDevHlpPhysIsGCPhysNormal(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
7007	{
7008	return pDevIns->CTX_SUFF(pHlp)->pfnPhysIsGCPhysNormal(pDevIns, GCPhys);
7009	}
7010
7011	/**
7012	* @copydoc PDMDEVHLPR3::pfnPhysChangeMemBalloon
7013	*/
7014	DECLINLINE(int) PDMDevHlpPhysChangeMemBalloon(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
7015	{
7016	return pDevIns->CTX_SUFF(pHlp)->pfnPhysChangeMemBalloon(pDevIns, fInflate, cPages, paPhysPage);
7017	}
7018
7019	/**
7020	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
7021	*/
7022	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
7023	{
7024	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
7025	}
7026
7027	/**
7028	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
7029	*/
7030	DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth)
7031	{
7032	pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
7033	}
7034
7035	/**
7036	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
7037	*/
7038	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
7039	{
7040	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
7041	}
7042
7043	/**
7044	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
7045	*/
7046	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
7047	{
7048	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
7049	}
7050
7051	/**
7052	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
7053	*/
7054	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
7055	{
7056	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
7057	}
7058
7059	/**
7060	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
7061	*/
7062	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
7063	{
7064	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
7065	}
7066
7067	/**
7068	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
7069	*/
7070	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
7071	{
7072	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
7073	}
7074
7075	/**
7076	* Allocating string printf.
7077	*
7078	* @returns Pointer to the string.
7079	* @param pDevIns The device instance.
7080	* @param enmTag The statistics tag.
7081	* @param pszFormat The format string.
7082	* @param ... Format arguments.
7083	*/
7084	DECLINLINE(char ) RT_IPRT_FORMAT_ATTR(2, 3) PDMDevHlpMMHeapAPrintf(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, ...)
7085	{
7086	va_list va;
7087	va_start(va, pszFormat);
7088	char *psz = pDevIns->pHlpR3->pfnMMHeapAPrintfV(pDevIns, enmTag, pszFormat, va);
7089	va_end(va);
7090
7091	return psz;
7092	}
7093
7094	/**
7095	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
7096	*/
7097	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
7098	{
7099	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
7100	}
7101
7102	/**
7103	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSize
7104	*/
7105	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSize(PPDMDEVINS pDevIns)
7106	{
7107	return pDevIns->pHlpR3->pfnMMPhysGetRamSize(pDevIns);
7108	}
7109
7110	/**
7111	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeBelow4GB
7112	*/
7113	DECLINLINE(uint32_t) PDMDevHlpMMPhysGetRamSizeBelow4GB(PPDMDEVINS pDevIns)
7114	{
7115	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeBelow4GB(pDevIns);
7116	}
7117
7118	/**
7119	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeAbove4GB
7120	*/
7121	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSizeAbove4GB(PPDMDEVINS pDevIns)
7122	{
7123	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeAbove4GB(pDevIns);
7124	}
7125	#endif /* IN_RING3 */
7126
7127	/**
7128	* @copydoc PDMDEVHLPR3::pfnVMState
7129	*/
7130	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
7131	{
7132	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
7133	}
7134
7135	#ifdef IN_RING3
7136
7137	/**
7138	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
7139	*/
7140	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
7141	{
7142	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
7143	}
7144
7145	/**
7146	* Set the VM error message
7147	*
7148	* @returns rc.
7149	* @param pDevIns The device instance.
7150	* @param rc VBox status code.
7151	* @param SRC_POS Use RT_SRC_POS.
7152	* @param pszFormat Error message format string.
7153	* @param ... Error message arguments.
7154	* @sa VMSetError
7155	*/
7156	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
7157	const char *pszFormat, ...)
7158	{
7159	va_list va;
7160	va_start(va, pszFormat);
7161	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
7162	va_end(va);
7163	return rc;
7164	}
7165
7166	/**
7167	* Set the VM runtime error message
7168	*
7169	* @returns VBox status code.
7170	* @param pDevIns The device instance.
7171	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
7172	* @param pszErrorId Error ID string.
7173	* @param pszFormat Error message format string.
7174	* @param ... Error message arguments.
7175	* @sa VMSetRuntimeError
7176	*/
7177	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
7178	const char *pszFormat, ...)
7179	{
7180	va_list va;
7181	int rc;
7182	va_start(va, pszFormat);
7183	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
7184	va_end(va);
7185	return rc;
7186	}
7187
7188	/**
7189	* @copydoc PDMDEVHLPR3::pfnVMWaitForDeviceReady
7190	*/
7191	DECLINLINE(int) PDMDevHlpVMWaitForDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7192	{
7193	return pDevIns->CTX_SUFF(pHlp)->pfnVMWaitForDeviceReady(pDevIns, idCpu);
7194	}
7195
7196	/**
7197	* @copydoc PDMDEVHLPR3::pfnVMNotifyCpuDeviceReady
7198	*/
7199	DECLINLINE(int) PDMDevHlpVMNotifyCpuDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7200	{
7201	return pDevIns->CTX_SUFF(pHlp)->pfnVMNotifyCpuDeviceReady(pDevIns, idCpu);
7202	}
7203
7204	/**
7205	* Convenience wrapper for VMR3ReqCallU.
7206	*
7207	* This assumes (1) you're calling a function that returns an VBox status code
7208	* and that you do not wish to wait for it to complete.
7209	*
7210	* @returns VBox status code returned by VMR3ReqCallVU.
7211	*
7212	* @param pDevIns The device instance.
7213	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7214	* one of the following special values:
7215	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7216	* @param pfnFunction Pointer to the function to call.
7217	* @param cArgs Number of arguments following in the ellipsis.
7218	* @param ... Argument list.
7219	*
7220	* @remarks See remarks on VMR3ReqCallVU.
7221	*/
7222	DECLINLINE(int) PDMDevHlpVMReqCallNoWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7223	{
7224	va_list Args;
7225	va_start(Args, cArgs);
7226	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqCallNoWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7227	va_end(Args);
7228	return rc;
7229	}
7230
7231	/**
7232	* Convenience wrapper for VMR3ReqCallU.
7233	*
7234	* This assumes (1) you're calling a function that returns void, (2) that you
7235	* wish to wait for ever for it to return, and (3) that it's priority request
7236	* that can be safely be handled during async suspend and power off.
7237	*
7238	* @returns VBox status code of VMR3ReqCallVU.
7239	*
7240	* @param pDevIns The device instance.
7241	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7242	* one of the following special values:
7243	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7244	* @param pfnFunction Pointer to the function to call.
7245	* @param cArgs Number of arguments following in the ellipsis.
7246	* @param ... Argument list.
7247	*
7248	* @remarks See remarks on VMR3ReqCallVU.
7249	*/
7250	DECLINLINE(int) PDMDevHlpVMReqPriorityCallWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7251	{
7252	va_list Args;
7253	va_start(Args, cArgs);
7254	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqPriorityCallWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7255	va_end(Args);
7256	return rc;
7257	}
7258
7259	#endif /* IN_RING3 */
7260
7261	/**
7262	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
7263	*
7264	* @returns VBox status code which must be passed up to the VMM. This will be
7265	* VINF_SUCCESS in non-strict builds.
7266	* @param pDevIns The device instance.
7267	* @param SRC_POS Use RT_SRC_POS.
7268	* @param pszFormat Message. (optional)
7269	* @param ... Message parameters.
7270	*/
7271	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
7272	{
7273	#ifdef VBOX_STRICT
7274	# ifdef IN_RING3
7275	int rc;
7276	va_list args;
7277	va_start(args, pszFormat);
7278	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
7279	va_end(args);
7280	return rc;
7281	# else
7282	NOREF(pDevIns);
7283	NOREF(pszFile);
7284	NOREF(iLine);
7285	NOREF(pszFunction);
7286	NOREF(pszFormat);
7287	return VINF_EM_DBG_STOP;
7288	# endif
7289	#else
7290	NOREF(pDevIns);
7291	NOREF(pszFile);
7292	NOREF(iLine);
7293	NOREF(pszFunction);
7294	NOREF(pszFormat);
7295	return VINF_SUCCESS;
7296	#endif
7297	}
7298
7299	#ifdef IN_RING3
7300
7301	/**
7302	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
7303	*/
7304	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
7305	{
7306	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
7307	}
7308
7309	/**
7310	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
7311	*/
7312	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
7313	{
7314	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
7315	}
7316
7317	/**
7318	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
7319	*/
7320	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
7321	{
7322	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
7323	}
7324
7325	/**
7326	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
7327	*/
7328	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
7329	{
7330	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
7331	}
7332
7333	/**
7334	* Same as pfnSTAMRegister except that the name is specified in a
7335	* RTStrPrintf like fashion.
7336	*
7337	* @returns VBox status.
7338	* @param pDevIns Device instance of the DMA.
7339	* @param pvSample Pointer to the sample.
7340	* @param enmType Sample type. This indicates what pvSample is
7341	* pointing at.
7342	* @param enmVisibility Visibility type specifying whether unused
7343	* statistics should be visible or not.
7344	* @param enmUnit Sample unit.
7345	* @param pszDesc Sample description.
7346	* @param pszName Sample name format string, unix path style. If
7347	* this does not start with a '/', the default
7348	* prefix will be prepended, otherwise it will be
7349	* used as-is.
7350	* @param ... Arguments to the format string.
7351	*/
7352	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
7353	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
7354	const char pszDesc, const char pszName, ...)
7355	{
7356	va_list va;
7357	va_start(va, pszName);
7358	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
7359	va_end(va);
7360	}
7361
7362	/**
7363	* @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
7364	*/
7365	DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
7366	{
7367	return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
7368	}
7369
7370	/**
7371	* Registers the device with the default PCI bus.
7372	*
7373	* @returns VBox status code.
7374	* @param pDevIns The device instance.
7375	* @param pPciDev The PCI device structure.
7376	* This must be kept in the instance data.
7377	* The PCI configuration must be initialized before registration.
7378	*/
7379	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
7380	{
7381	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
7382	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
7383	}
7384
7385	/**
7386	* @copydoc PDMDEVHLPR3::pfnPCIRegister
7387	*/
7388	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
7389	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
7390	{
7391	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
7392	}
7393
7394	/**
7395	* Initialize MSI emulation support for the first PCI device.
7396	*
7397	* @returns VBox status code.
7398	* @param pDevIns The device instance.
7399	* @param pMsiReg MSI emulation registration structure.
7400	*/
7401	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
7402	{
7403	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
7404	}
7405
7406	/**
7407	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
7408	*/
7409	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
7410	{
7411	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
7412	}
7413
7414	/**
7415	* Registers a I/O port region for the default PCI device.
7416	*
7417	* @returns VBox status code.
7418	* @param pDevIns The device instance.
7419	* @param iRegion The region number.
7420	* @param cbRegion Size of the region.
7421	* @param hIoPorts Handle to the I/O port region.
7422	*/
7423	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
7424	{
7425	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7426	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
7427	}
7428
7429	/**
7430	* Registers a I/O port region for the default PCI device, custom map/unmap.
7431	*
7432	* @returns VBox status code.
7433	* @param pDevIns The device instance.
7434	* @param iRegion The region number.
7435	* @param cbRegion Size of the region.
7436	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7437	* callback will be invoked holding only the PDM lock.
7438	* The device lock will _not_ be taken (due to lock
7439	* order).
7440	*/
7441	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7442	PFNPCIIOREGIONMAP pfnMapUnmap)
7443	{
7444	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7445	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7446	UINT64_MAX, pfnMapUnmap);
7447	}
7448
7449	/**
7450	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7451	* and registering an I/O port region for the default PCI device.
7452	*
7453	* @returns VBox status code.
7454	* @param pDevIns The device instance to register the ports with.
7455	* @param cPorts The count of I/O ports in the region (the size).
7456	* @param iPciRegion The PCI device region.
7457	* @param pfnOut Pointer to function which is gonna handle OUT
7458	* operations. Optional.
7459	* @param pfnIn Pointer to function which is gonna handle IN operations.
7460	* Optional.
7461	* @param pvUser User argument to pass to the callbacks.
7462	* @param pszDesc Pointer to description string. This must not be freed.
7463	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7464	* coverage is allowed. This must not be freed.
7465	* @param phIoPorts Where to return the I/O port range handle.
7466	*
7467	*/
7468	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7469	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7470	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7471
7472	{
7473	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7474	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7475	if (RT_SUCCESS(rc))
7476	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7477	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7478	phIoPorts, NULL /pfnMapUnmap*/);
7479	return rc;
7480	}
7481
7482	/**
7483	* Registers an MMIO region for the default PCI device.
7484	*
7485	* @returns VBox status code.
7486	* @param pDevIns The device instance.
7487	* @param iRegion The region number.
7488	* @param cbRegion Size of the region.
7489	* @param enmType PCI_ADDRESS_SPACE_MEM or
7490	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7491	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7492	* @param hMmioRegion Handle to the MMIO region.
7493	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7494	* callback will be invoked holding only the PDM lock.
7495	* The device lock will _not_ be taken (due to lock
7496	* order).
7497	*/
7498	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7499	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7500	{
7501	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7502	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7503	hMmioRegion, pfnMapUnmap);
7504	}
7505
7506	/**
7507	* Registers an MMIO region for the default PCI device, extended version.
7508	*
7509	* @returns VBox status code.
7510	* @param pDevIns The device instance.
7511	* @param pPciDev The PCI device structure.
7512	* @param iRegion The region number.
7513	* @param cbRegion Size of the region.
7514	* @param enmType PCI_ADDRESS_SPACE_MEM or
7515	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7516	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7517	* @param hMmioRegion Handle to the MMIO region.
7518	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7519	* callback will be invoked holding only the PDM lock.
7520	* The device lock will _not_ be taken (due to lock
7521	* order).
7522	*/
7523	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7524	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7525	PFNPCIIOREGIONMAP pfnMapUnmap)
7526	{
7527	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7528	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7529	hMmioRegion, pfnMapUnmap);
7530	}
7531
7532	/**
7533	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7534	* and registering an MMIO region for the default PCI device.
7535	*
7536	* @returns VBox status code.
7537	* @param pDevIns The device instance to register the ports with.
7538	* @param cbRegion The size of the region in bytes.
7539	* @param iPciRegion The PCI device region.
7540	* @param enmType PCI_ADDRESS_SPACE_MEM or
7541	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7542	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7543	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7544	* @param pfnWrite Pointer to function which is gonna handle Write
7545	* operations.
7546	* @param pfnRead Pointer to function which is gonna handle Read
7547	* operations.
7548	* @param pvUser User argument to pass to the callbacks.
7549	* @param pszDesc Pointer to description string. This must not be freed.
7550	* @param phRegion Where to return the MMIO region handle.
7551	*
7552	*/
7553	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7554	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7555	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7556
7557	{
7558	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7559	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7560	if (RT_SUCCESS(rc))
7561	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7562	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7563	phRegion, NULL /pfnMapUnmap*/);
7564	return rc;
7565	}
7566
7567
7568	/**
7569	* Registers an MMIO2 region for the default PCI device.
7570	*
7571	* @returns VBox status code.
7572	* @param pDevIns The device instance.
7573	* @param iRegion The region number.
7574	* @param cbRegion Size of the region.
7575	* @param enmType PCI_ADDRESS_SPACE_MEM or
7576	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7577	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7578	* @param hMmio2Region Handle to the MMIO2 region.
7579	*/
7580	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7581	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7582	{
7583	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7584	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7585	hMmio2Region, NULL);
7586	}
7587
7588	/**
7589	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7590	* and registering an MMIO2 region for the default PCI device, extended edition.
7591	*
7592	* @returns VBox status code.
7593	* @param pDevIns The device instance to register the ports with.
7594	* @param cbRegion The size of the region in bytes.
7595	* @param iPciRegion The PCI device region.
7596	* @param enmType PCI_ADDRESS_SPACE_MEM or
7597	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7598	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7599	* @param pszDesc Pointer to description string. This must not be freed.
7600	* @param ppvMapping Where to store the address of the ring-3 mapping of
7601	* the memory.
7602	* @param phRegion Where to return the MMIO2 region handle.
7603	*
7604	*/
7605	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7606	PCIADDRESSSPACE enmType, const char *pszDesc,
7607	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7608
7609	{
7610	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7611	pszDesc, ppvMapping, phRegion);
7612	if (RT_SUCCESS(rc))
7613	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7614	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7615	phRegion, NULL /pfnCallback*/);
7616	return rc;
7617	}
7618
7619	/**
7620	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7621	* and registering an MMIO2 region for the default PCI device.
7622	*
7623	* @returns VBox status code.
7624	* @param pDevIns The device instance to register the ports with.
7625	* @param cbRegion The size of the region in bytes.
7626	* @param iPciRegion The PCI device region.
7627	* @param enmType PCI_ADDRESS_SPACE_MEM or
7628	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7629	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7630	* @param fMmio2Flags To be defined, must be zero.
7631	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7632	* callback will be invoked holding only the PDM lock.
7633	* The device lock will _not_ be taken (due to lock
7634	* order).
7635	* @param pszDesc Pointer to description string. This must not be freed.
7636	* @param ppvMapping Where to store the address of the ring-3 mapping of
7637	* the memory.
7638	* @param phRegion Where to return the MMIO2 region handle.
7639	*
7640	*/
7641	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7642	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7643	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
7644
7645	{
7646	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7647	pszDesc, ppvMapping, phRegion);
7648	if (RT_SUCCESS(rc))
7649	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7650	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7651	*phRegion, pfnMapUnmap);
7652	return rc;
7653	}
7654
7655	/**
7656	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7657	*/
7658	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7659	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7660	{
7661	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7662	}
7663
7664	/**
7665	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7666	*/
7667	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7668	unsigned cb, uint32_t *pu32Value)
7669	{
7670	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7671	}
7672
7673	/**
7674	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7675	*/
7676	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7677	unsigned cb, uint32_t u32Value)
7678	{
7679	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7680	}
7681
7682	#endif /* IN_RING3 */
7683
7684	/**
7685	* Bus master physical memory read from the default PCI device.
7686	*
7687	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7688	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7689	* @param pDevIns The device instance.
7690	* @param GCPhys Physical address start reading from.
7691	* @param pvBuf Where to put the read bits.
7692	* @param cbRead How many bytes to read.
7693	* @thread Any thread, but the call may involve the emulation thread.
7694	*/
7695	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7696	{
7697	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7698	}
7699
7700	/**
7701	* Bus master physical memory read - unknown data usage.
7702	*
7703	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7704	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7705	* @param pDevIns The device instance.
7706	* @param pPciDev The PCI device structure. If NULL the default
7707	* PCI device for this device instance is used.
7708	* @param GCPhys Physical address start reading from.
7709	* @param pvBuf Where to put the read bits.
7710	* @param cbRead How many bytes to read.
7711	* @thread Any thread, but the call may involve the emulation thread.
7712	*/
7713	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7714	{
7715	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7716	}
7717
7718	/**
7719	* Bus master physical memory read from the default PCI device.
7720	*
7721	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7722	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7723	* @param pDevIns The device instance.
7724	* @param GCPhys Physical address start reading from.
7725	* @param pvBuf Where to put the read bits.
7726	* @param cbRead How many bytes to read.
7727	* @thread Any thread, but the call may involve the emulation thread.
7728	*/
7729	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7730	{
7731	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7732	}
7733
7734	/**
7735	* Bus master physical memory read - reads meta data processed by the device.
7736	*
7737	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7738	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7739	* @param pDevIns The device instance.
7740	* @param pPciDev The PCI device structure. If NULL the default
7741	* PCI device for this device instance is used.
7742	* @param GCPhys Physical address start reading from.
7743	* @param pvBuf Where to put the read bits.
7744	* @param cbRead How many bytes to read.
7745	* @thread Any thread, but the call may involve the emulation thread.
7746	*/
7747	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7748	{
7749	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7750	}
7751
7752	/**
7753	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
7754	*
7755	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7756	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7757	* @param pDevIns The device instance.
7758	* @param GCPhys Physical address start reading from.
7759	* @param pvBuf Where to put the read bits.
7760	* @param cbRead How many bytes to read.
7761	* @thread Any thread, but the call may involve the emulation thread.
7762	*/
7763	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7764	{
7765	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7766	}
7767
7768	/**
7769	* Bus master physical memory read - read data will not be touched by the device.
7770	*
7771	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7772	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7773	* @param pDevIns The device instance.
7774	* @param pPciDev The PCI device structure. If NULL the default
7775	* PCI device for this device instance is used.
7776	* @param GCPhys Physical address start reading from.
7777	* @param pvBuf Where to put the read bits.
7778	* @param cbRead How many bytes to read.
7779	* @thread Any thread, but the call may involve the emulation thread.
7780	*/
7781	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7782	{
7783	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7784	}
7785
7786	/**
7787	* Bus master physical memory write from the default PCI device - unknown data usage.
7788	*
7789	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7790	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7791	* @param pDevIns The device instance.
7792	* @param GCPhys Physical address to write to.
7793	* @param pvBuf What to write.
7794	* @param cbWrite How many bytes to write.
7795	* @thread Any thread, but the call may involve the emulation thread.
7796	*/
7797	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7798	{
7799	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7800	}
7801
7802	/**
7803	* Bus master physical memory write - unknown data usage.
7804	*
7805	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7806	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7807	* @param pDevIns The device instance.
7808	* @param pPciDev The PCI device structure. If NULL the default
7809	* PCI device for this device instance is used.
7810	* @param GCPhys Physical address to write to.
7811	* @param pvBuf What to write.
7812	* @param cbWrite How many bytes to write.
7813	* @thread Any thread, but the call may involve the emulation thread.
7814	*/
7815	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7816	{
7817	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7818	}
7819
7820	/**
7821	* Bus master physical memory write from the default PCI device.
7822	*
7823	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7824	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7825	* @param pDevIns The device instance.
7826	* @param GCPhys Physical address to write to.
7827	* @param pvBuf What to write.
7828	* @param cbWrite How many bytes to write.
7829	* @thread Any thread, but the call may involve the emulation thread.
7830	*/
7831	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7832	{
7833	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7834	}
7835
7836	/**
7837	* Bus master physical memory write - written data was created/altered by the device.
7838	*
7839	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7840	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7841	* @param pDevIns The device instance.
7842	* @param pPciDev The PCI device structure. If NULL the default
7843	* PCI device for this device instance is used.
7844	* @param GCPhys Physical address to write to.
7845	* @param pvBuf What to write.
7846	* @param cbWrite How many bytes to write.
7847	* @thread Any thread, but the call may involve the emulation thread.
7848	*/
7849	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7850	{
7851	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7852	}
7853
7854	/**
7855	* Bus master physical memory write from the default PCI device.
7856	*
7857	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7858	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7859	* @param pDevIns The device instance.
7860	* @param GCPhys Physical address to write to.
7861	* @param pvBuf What to write.
7862	* @param cbWrite How many bytes to write.
7863	* @thread Any thread, but the call may involve the emulation thread.
7864	*/
7865	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7866	{
7867	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7868	}
7869
7870	/**
7871	* Bus master physical memory write - written data was not touched/created by the device.
7872	*
7873	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7874	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7875	* @param pDevIns The device instance.
7876	* @param pPciDev The PCI device structure. If NULL the default
7877	* PCI device for this device instance is used.
7878	* @param GCPhys Physical address to write to.
7879	* @param pvBuf What to write.
7880	* @param cbWrite How many bytes to write.
7881	* @thread Any thread, but the call may involve the emulation thread.
7882	*/
7883	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7884	{
7885	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7886	}
7887
7888	#ifdef IN_RING3
7889	/**
7890	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
7891	*/
7892	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7893	void **ppv, PPGMPAGEMAPLOCK pLock)
7894	{
7895	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7896	}
7897
7898	/**
7899	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
7900	*/
7901	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7902	void const **ppv, PPGMPAGEMAPLOCK pLock)
7903	{
7904	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7905	}
7906
7907	/**
7908	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
7909	*/
7910	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7911	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
7912	PPGMPAGEMAPLOCK paLocks)
7913	{
7914	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
7915	paLocks);
7916	}
7917
7918	/**
7919	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
7920	*/
7921	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7922	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
7923	PPGMPAGEMAPLOCK paLocks)
7924	{
7925	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
7926	papvPages, paLocks);
7927	}
7928	#endif /* IN_RING3 */
7929
7930	/**
7931	* Sets the IRQ for the default PCI device.
7932	*
7933	* @param pDevIns The device instance.
7934	* @param iIrq IRQ number to set.
7935	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7936	* @thread Any thread, but will involve the emulation thread.
7937	*/
7938	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7939	{
7940	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7941	}
7942
7943	/**
7944	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
7945	*/
7946	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7947	{
7948	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7949	}
7950
7951	/**
7952	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7953	* the request when not called from EMT.
7954	*
7955	* @param pDevIns The device instance.
7956	* @param iIrq IRQ number to set.
7957	* @param iLevel IRQ level.
7958	* @thread Any thread, but will involve the emulation thread.
7959	*/
7960	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7961	{
7962	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7963	}
7964
7965	/**
7966	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7967	*/
7968	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7969	{
7970	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7971	}
7972
7973	/**
7974	* @copydoc PDMDEVHLPR3::pfnISASetIrq
7975	*/
7976	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7977	{
7978	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7979	}
7980
7981	/**
7982	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7983	*/
7984	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7985	{
7986	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7987	}
7988
7989	#ifdef IN_RING3
7990
7991	/**
7992	* @copydoc PDMDEVHLPR3::pfnDriverAttach
7993	*/
7994	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
7995	{
7996	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7997	}
7998
7999	/**
8000	* @copydoc PDMDEVHLPR3::pfnDriverDetach
8001	*/
8002	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
8003	{
8004	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
8005	}
8006
8007	/**
8008	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
8009	*/
8010	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
8011	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
8012	{
8013	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
8014	}
8015
8016	/**
8017	* Reconfigures with a single driver reattachement, no config, noflags.
8018	* @sa PDMDevHlpDriverReconfigure
8019	*/
8020	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
8021	{
8022	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
8023	}
8024
8025	/**
8026	* Reconfigures with a two drivers reattachement, no config, noflags.
8027	* @sa PDMDevHlpDriverReconfigure
8028	*/
8029	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
8030	{
8031	char const * apszDrivers[2];
8032	apszDrivers[0] = pszDriver0;
8033	apszDrivers[1] = pszDriver1;
8034	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
8035	}
8036
8037	/**
8038	* @copydoc PDMDEVHLPR3::pfnQueueCreate
8039	*/
8040	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
8041	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
8042	{
8043	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
8044	}
8045
8046	#endif /* IN_RING3 */
8047
8048	/**
8049	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
8050	*/
8051	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8052	{
8053	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
8054	}
8055
8056	/**
8057	* @copydoc PDMDEVHLPR3::pfnQueueInsert
8058	*/
8059	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
8060	{
8061	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
8062	}
8063
8064	/**
8065	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
8066	*/
8067	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8068	{
8069	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
8070	}
8071
8072	#ifdef IN_RING3
8073	/**
8074	* @copydoc PDMDEVHLPR3::pfnTaskCreate
8075	*/
8076	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
8077	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
8078	{
8079	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
8080	}
8081	#endif
8082
8083	/**
8084	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
8085	*/
8086	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
8087	{
8088	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
8089	}
8090
8091	#ifdef IN_RING3
8092
8093	/**
8094	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
8095	*/
8096	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
8097	{
8098	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
8099	}
8100
8101	/**
8102	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
8103	*/
8104	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8105	{
8106	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
8107	}
8108
8109	#endif /* IN_RING3 */
8110
8111	/**
8112	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
8113	*/
8114	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8115	{
8116	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
8117	}
8118
8119	/**
8120	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
8121	*/
8122	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
8123	{
8124	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
8125	}
8126
8127	/**
8128	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
8129	*/
8130	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
8131	{
8132	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
8133	}
8134
8135	/**
8136	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
8137	*/
8138	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
8139	{
8140	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
8141	}
8142
8143	/**
8144	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
8145	*/
8146	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
8147	{
8148	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
8149	}
8150
8151	#ifdef IN_RING3
8152
8153	/**
8154	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
8155	*/
8156	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
8157	{
8158	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
8159	}
8160
8161	/**
8162	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
8163	*/
8164	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8165	{
8166	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
8167	}
8168
8169	#endif /* IN_RING3 */
8170
8171	/**
8172	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
8173	*/
8174	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8175	{
8176	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
8177	}
8178
8179	/**
8180	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
8181	*/
8182	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8183	{
8184	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
8185	}
8186
8187	/**
8188	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
8189	*/
8190	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
8191	{
8192	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
8193	}
8194
8195	/**
8196	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
8197	*/
8198	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
8199	{
8200	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
8201	}
8202
8203	/**
8204	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
8205	*/
8206	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
8207	{
8208	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
8209	}
8210
8211	/**
8212	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
8213	*/
8214	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
8215	{
8216	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
8217	}
8218
8219	#ifdef IN_RING3
8220
8221	/**
8222	* Initializes a PDM critical section.
8223	*
8224	* The PDM critical sections are derived from the IPRT critical sections, but
8225	* works in RC and R0 as well.
8226	*
8227	* @returns VBox status code.
8228	* @param pDevIns The device instance.
8229	* @param pCritSect Pointer to the critical section.
8230	* @param SRC_POS Use RT_SRC_POS.
8231	* @param pszNameFmt Format string for naming the critical section.
8232	* For statistics and lock validation.
8233	* @param ... Arguments for the format string.
8234	*/
8235	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
8236	const char *pszNameFmt, ...)
8237	{
8238	int rc;
8239	va_list va;
8240	va_start(va, pszNameFmt);
8241	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8242	va_end(va);
8243	return rc;
8244	}
8245
8246	#endif /* IN_RING3 */
8247
8248	/**
8249	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
8250	*/
8251	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
8252	{
8253	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
8254	}
8255
8256	/**
8257	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
8258	*/
8259	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8260	{
8261	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
8262	}
8263
8264	/**
8265	* Enters a PDM critical section.
8266	*
8267	* @returns VINF_SUCCESS if entered successfully.
8268	* @returns rcBusy when encountering a busy critical section in RC/R0.
8269	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8270	* during the operation.
8271	*
8272	* @param pDevIns The device instance.
8273	* @param pCritSect The PDM critical section to enter.
8274	* @param rcBusy The status code to return when we're in RC or R0
8275	* and the section is busy. Pass VINF_SUCCESS to
8276	* acquired the critical section thru a ring-3
8277	* call if necessary.
8278	*
8279	* @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
8280	* possible failures in ring-0 or at least apply
8281	* PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
8282	* function.
8283	*
8284	* @sa PDMCritSectEnter
8285	*/
8286	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
8287	{
8288	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
8289	}
8290
8291	/**
8292	* Enters a PDM critical section, with location information for debugging.
8293	*
8294	* @returns VINF_SUCCESS if entered successfully.
8295	* @returns rcBusy when encountering a busy critical section in RC/R0.
8296	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8297	* during the operation.
8298	*
8299	* @param pDevIns The device instance.
8300	* @param pCritSect The PDM critical section to enter.
8301	* @param rcBusy The status code to return when we're in RC or R0
8302	* and the section is busy. Pass VINF_SUCCESS to
8303	* acquired the critical section thru a ring-3
8304	* call if necessary.
8305	* @param uId Some kind of locking location ID. Typically a
8306	* return address up the stack. Optional (0).
8307	* @param SRC_POS The source position where to lock is being
8308	* acquired from. Optional.
8309	* @sa PDMCritSectEnterDebug
8310	*/
8311	DECLINLINE(DECL_CHECK_RETURN(int))
8312	PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8313	{
8314	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8315	}
8316
8317	/**
8318	* Try enter a critical section.
8319	*
8320	* @retval VINF_SUCCESS on success.
8321	* @retval VERR_SEM_BUSY if the critsect was owned.
8322	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8323	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8324	* during the operation.
8325	*
8326	* @param pDevIns The device instance.
8327	* @param pCritSect The critical section.
8328	* @sa PDMCritSectTryEnter
8329	*/
8330	DECLINLINE(DECL_CHECK_RETURN(int))
8331	PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8332	{
8333	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
8334	}
8335
8336	/**
8337	* Try enter a critical section, with location information for debugging.
8338	*
8339	* @retval VINF_SUCCESS on success.
8340	* @retval VERR_SEM_BUSY if the critsect was owned.
8341	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8342	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8343	* during the operation.
8344	*
8345	* @param pDevIns The device instance.
8346	* @param pCritSect The critical section.
8347	* @param uId Some kind of locking location ID. Typically a
8348	* return address up the stack. Optional (0).
8349	* @param SRC_POS The source position where to lock is being
8350	* acquired from. Optional.
8351	* @sa PDMCritSectTryEnterDebug
8352	*/
8353	DECLINLINE(DECL_CHECK_RETURN(int))
8354	PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8355	{
8356	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8357	}
8358
8359	/**
8360	* Leaves a critical section entered with PDMCritSectEnter().
8361	*
8362	* @returns Indication whether we really exited the critical section.
8363	* @retval VINF_SUCCESS if we really exited.
8364	* @retval VINF_SEM_NESTED if we only reduced the nesting count.
8365	* @retval VERR_NOT_OWNER if you somehow ignore release assertions.
8366	*
8367	* @param pDevIns The device instance.
8368	* @param pCritSect The PDM critical section to leave.
8369	* @sa PDMCritSectLeave
8370	*/
8371	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8372	{
8373	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
8374	}
8375
8376	/**
8377	* @see PDMCritSectIsOwner
8378	*/
8379	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8380	{
8381	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
8382	}
8383
8384	/**
8385	* @see PDMCritSectIsInitialized
8386	*/
8387	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8388	{
8389	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
8390	}
8391
8392	/**
8393	* @see PDMCritSectHasWaiters
8394	*/
8395	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8396	{
8397	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
8398	}
8399
8400	/**
8401	* @see PDMCritSectGetRecursion
8402	*/
8403	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8404	{
8405	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
8406	}
8407
8408	#if defined(IN_RING3) \|\| defined(IN_RING0)
8409	/**
8410	* @see PDMHCCritSectScheduleExitEvent
8411	*/
8412	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
8413	{
8414	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
8415	}
8416	#endif
8417
8418	/* Strict build: Remap the two enter calls to the debug versions. */
8419	#ifdef VBOX_STRICT
8420	# ifdef IPRT_INCLUDED_asm_h
8421	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8422	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8423	# else
8424	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8425	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8426	# endif
8427	#endif
8428
8429	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8430
8431	/**
8432	* Deletes the critical section.
8433	*
8434	* @returns VBox status code.
8435	* @param pDevIns The device instance.
8436	* @param pCritSect The PDM critical section to destroy.
8437	* @sa PDMR3CritSectDelete
8438	*/
8439	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8440	{
8441	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8442	}
8443
8444	/**
8445	* Initializes a PDM read/write critical section.
8446	*
8447	* The PDM read/write critical sections are derived from the IPRT critical
8448	* sections, but works in RC and R0 as well.
8449	*
8450	* @returns VBox status code.
8451	* @param pDevIns The device instance.
8452	* @param pCritSect Pointer to the read/write critical section.
8453	* @param SRC_POS Use RT_SRC_POS.
8454	* @param pszNameFmt Format string for naming the critical section.
8455	* For statistics and lock validation.
8456	* @param ... Arguments for the format string.
8457	*/
8458	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
8459	const char *pszNameFmt, ...)
8460	{
8461	int rc;
8462	va_list va;
8463	va_start(va, pszNameFmt);
8464	rc = pDevIns->pHlpR3->pfnCritSectRwInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8465	va_end(va);
8466	return rc;
8467	}
8468
8469	/**
8470	* Deletes the read/write critical section.
8471	*
8472	* @returns VBox status code.
8473	* @param pDevIns The device instance.
8474	* @param pCritSect The PDM read/write critical section to destroy.
8475	* @sa PDMR3CritSectRwDelete
8476	*/
8477	DECLINLINE(int) PDMDevHlpCritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8478	{
8479	return pDevIns->pHlpR3->pfnCritSectRwDelete(pDevIns, pCritSect);
8480	}
8481
8482	#endif /* IN_RING3 */
8483
8484	/**
8485	* @sa PDMCritSectRwEnterShared, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8486	*/
8487	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8488	{
8489	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterShared(pDevIns, pCritSect, rcBusy);
8490	}
8491
8492	/**
8493	* @sa PDMCritSectRwEnterSharedDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8494	*/
8495	DECLINLINE(DECL_CHECK_RETURN(int))
8496	PDMDevHlpCritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8497	{
8498	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterSharedDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8499	}
8500
8501	/**
8502	* @sa PDMCritSectRwTryEnterShared
8503	*/
8504	DECLINLINE(DECL_CHECK_RETURN(int))
8505	PDMDevHlpCritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8506	{
8507	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterShared(pDevIns, pCritSect);
8508	}
8509
8510	/**
8511	* @sa PDMCritSectRwTryEnterSharedDebug
8512	*/
8513	DECLINLINE(DECL_CHECK_RETURN(int))
8514	PDMDevHlpCritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8515	{
8516	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterSharedDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8517	}
8518
8519	/**
8520	* @sa PDMCritSectRwLeaveShared
8521	*/
8522	DECLINLINE(int) PDMDevHlpCritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8523	{
8524	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveShared(pDevIns, pCritSect);
8525	}
8526
8527	/**
8528	* @sa PDMCritSectRwEnterExcl, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8529	*/
8530	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8531	{
8532	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy);
8533	}
8534
8535	/**
8536	* @sa PDMCritSectRwEnterExclDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8537	*/
8538	DECLINLINE(DECL_CHECK_RETURN(int))
8539	PDMDevHlpCritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8540	{
8541	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExclDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8542	}
8543
8544	/**
8545	* @sa PDMCritSectRwTryEnterExcl
8546	*/
8547	DECLINLINE(DECL_CHECK_RETURN(int))
8548	PDMDevHlpCritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8549	{
8550	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExcl(pDevIns, pCritSect);
8551	}
8552
8553	/**
8554	* @sa PDMCritSectRwTryEnterExclDebug
8555	*/
8556	DECLINLINE(DECL_CHECK_RETURN(int))
8557	PDMDevHlpCritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8558	{
8559	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExclDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8560	}
8561
8562	/**
8563	* @sa PDMCritSectRwLeaveExcl
8564	*/
8565	DECLINLINE(int) PDMDevHlpCritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8566	{
8567	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveExcl(pDevIns, pCritSect);
8568	}
8569
8570	/**
8571	* @see PDMCritSectRwIsWriteOwner
8572	*/
8573	DECLINLINE(bool) PDMDevHlpCritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8574	{
8575	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsWriteOwner(pDevIns, pCritSect);
8576	}
8577
8578	/**
8579	* @see PDMCritSectRwIsReadOwner
8580	*/
8581	DECLINLINE(bool) PDMDevHlpCritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
8582	{
8583	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsReadOwner(pDevIns, pCritSect, fWannaHear);
8584	}
8585
8586	/**
8587	* @see PDMCritSectRwGetWriteRecursion
8588	*/
8589	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8590	{
8591	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriteRecursion(pDevIns, pCritSect);
8592	}
8593
8594	/**
8595	* @see PDMCritSectRwGetWriterReadRecursion
8596	*/
8597	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8598	{
8599	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriterReadRecursion(pDevIns, pCritSect);
8600	}
8601
8602	/**
8603	* @see PDMCritSectRwGetReadCount
8604	*/
8605	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8606	{
8607	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetReadCount(pDevIns, pCritSect);
8608	}
8609
8610	/**
8611	* @see PDMCritSectRwIsInitialized
8612	*/
8613	DECLINLINE(bool) PDMDevHlpCritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8614	{
8615	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsInitialized(pDevIns, pCritSect);
8616	}
8617
8618	/* Strict build: Remap the two enter calls to the debug versions. */
8619	#ifdef VBOX_STRICT
8620	# ifdef IPRT_INCLUDED_asm_h
8621	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8622	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8623	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8624	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8625	# else
8626	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8627	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8628	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8629	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8630	# endif
8631	#endif
8632
8633	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8634
8635	/**
8636	* @copydoc PDMDEVHLPR3::pfnThreadCreate
8637	*/
8638	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
8639	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
8640	{
8641	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
8642	}
8643
8644	/**
8645	* @copydoc PDMR3ThreadDestroy
8646	* @param pDevIns The device instance.
8647	*/
8648	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
8649	{
8650	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
8651	}
8652
8653	/**
8654	* @copydoc PDMR3ThreadIAmSuspending
8655	* @param pDevIns The device instance.
8656	*/
8657	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8658	{
8659	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
8660	}
8661
8662	/**
8663	* @copydoc PDMR3ThreadIAmRunning
8664	* @param pDevIns The device instance.
8665	*/
8666	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8667	{
8668	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
8669	}
8670
8671	/**
8672	* @copydoc PDMR3ThreadSleep
8673	* @param pDevIns The device instance.
8674	*/
8675	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
8676	{
8677	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
8678	}
8679
8680	/**
8681	* @copydoc PDMR3ThreadSuspend
8682	* @param pDevIns The device instance.
8683	*/
8684	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8685	{
8686	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
8687	}
8688
8689	/**
8690	* @copydoc PDMR3ThreadResume
8691	* @param pDevIns The device instance.
8692	*/
8693	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8694	{
8695	return pDevIns->pHlpR3->pfnThreadResume(pThread);
8696	}
8697
8698	/**
8699	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
8700	*/
8701	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
8702	{
8703	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
8704	}
8705
8706	/**
8707	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
8708	*/
8709	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
8710	{
8711	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
8712	}
8713
8714	/**
8715	* @copydoc PDMDEVHLPR3::pfnA20Set
8716	*/
8717	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
8718	{
8719	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
8720	}
8721
8722	/**
8723	* @copydoc PDMDEVHLPR3::pfnRTCRegister
8724	*/
8725	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
8726	{
8727	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
8728	}
8729
8730	/**
8731	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
8732	*/
8733	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
8734	{
8735	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
8736	}
8737
8738	/**
8739	* @copydoc PDMDEVHLPR3::pfnIommuRegister
8740	*/
8741	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
8742	{
8743	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
8744	}
8745
8746	/**
8747	* @copydoc PDMDEVHLPR3::pfnPICRegister
8748	*/
8749	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8750	{
8751	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
8752	}
8753
8754	/**
8755	* @copydoc PDMDEVHLPR3::pfnApicRegister
8756	*/
8757	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
8758	{
8759	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
8760	}
8761
8762	/**
8763	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
8764	*/
8765	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8766	{
8767	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
8768	}
8769
8770	/**
8771	* @copydoc PDMDEVHLPR3::pfnHpetRegister
8772	*/
8773	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
8774	{
8775	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
8776	}
8777
8778	/**
8779	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
8780	*/
8781	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
8782	{
8783	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
8784	}
8785
8786	/**
8787	* @copydoc PDMDEVHLPR3::pfnDMACRegister
8788	*/
8789	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
8790	{
8791	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
8792	}
8793
8794	/**
8795	* @copydoc PDMDEVHLPR3::pfnDMARegister
8796	*/
8797	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
8798	{
8799	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
8800	}
8801
8802	/**
8803	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
8804	*/
8805	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
8806	{
8807	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
8808	}
8809
8810	/**
8811	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
8812	*/
8813	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
8814	{
8815	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
8816	}
8817
8818	/**
8819	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
8820	*/
8821	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
8822	{
8823	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
8824	}
8825
8826	/**
8827	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
8828	*/
8829	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
8830	{
8831	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
8832	}
8833
8834	/**
8835	* @copydoc PDMDEVHLPR3::pfnDMASchedule
8836	*/
8837	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
8838	{
8839	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
8840	}
8841
8842	/**
8843	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
8844	*/
8845	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
8846	{
8847	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
8848	}
8849
8850	/**
8851	* @copydoc PDMDEVHLPR3::pfnCMOSRead
8852	*/
8853	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
8854	{
8855	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
8856	}
8857
8858	/**
8859	* @copydoc PDMDEVHLPR3::pfnCallR0
8860	*/
8861	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
8862	{
8863	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
8864	}
8865
8866	/**
8867	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
8868	*/
8869	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
8870	{
8871	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
8872	}
8873
8874	/**
8875	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
8876	*/
8877	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
8878	{
8879	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
8880	}
8881
8882	/**
8883	* @copydoc PDMDEVHLPR3::pfnGetUVM
8884	*/
8885	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
8886	{
8887	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
8888	}
8889
8890	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
8891
8892	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8893
8894	/**
8895	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
8896	*/
8897	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
8898	{
8899	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
8900	}
8901
8902	/**
8903	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
8904	*/
8905	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
8906	{
8907	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
8908	}
8909
8910	/**
8911	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
8912	*/
8913	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8914	{
8915	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
8916	}
8917
8918	/**
8919	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
8920	*/
8921	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
8922	{
8923	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
8924	}
8925
8926	/**
8927	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
8928	*/
8929	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8930	{
8931	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
8932	}
8933
8934	/**
8935	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
8936	*/
8937	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
8938	{
8939	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
8940	}
8941
8942	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
8943
8944	/**
8945	* @copydoc PDMDEVHLPR3::pfnGetVM
8946	*/
8947	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
8948	{
8949	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
8950	}
8951
8952	/**
8953	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
8954	*/
8955	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
8956	{
8957	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
8958	}
8959
8960	/**
8961	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
8962	*/
8963	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
8964	{
8965	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
8966	}
8967
8968	/**
8969	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
8970	*/
8971	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
8972	{
8973	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
8974	}
8975
8976	/**
8977	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8978	*/
8979	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8980	{
8981	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8982	}
8983
8984	/**
8985	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8986	*/
8987	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8988	{
8989	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8990	}
8991
8992	#ifdef IN_RING3
8993
8994	/**
8995	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8996	*/
8997	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8998	{
8999	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
9000	}
9001
9002	/**
9003	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
9004	*/
9005	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
9006	{
9007	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
9008	}
9009
9010	/**
9011	* @copydoc PDMDEVHLPR3::pfnVMReset
9012	*/
9013	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
9014	{
9015	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
9016	}
9017
9018	/**
9019	* @copydoc PDMDEVHLPR3::pfnVMSuspend
9020	*/
9021	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
9022	{
9023	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
9024	}
9025
9026	/**
9027	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
9028	*/
9029	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
9030	{
9031	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
9032	}
9033
9034	/**
9035	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
9036	*/
9037	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
9038	{
9039	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
9040	}
9041
9042	#endif /* IN_RING3 */
9043
9044	/**
9045	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
9046	*/
9047	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
9048	{
9049	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
9050	}
9051
9052	#ifdef IN_RING3
9053
9054	/**
9055	* @copydoc PDMDEVHLPR3::pfnGetCpuId
9056	*/
9057	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
9058	{
9059	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
9060	}
9061
9062	/**
9063	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
9064	*/
9065	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
9066	{
9067	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
9068	}
9069
9070	/**
9071	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
9072	*/
9073	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
9074	{
9075	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
9076	}
9077
9078	/**
9079	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
9080	*/
9081	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
9082	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
9083	const char pszHandlerR0, const char pszPfHandlerR0,
9084	const char pszHandlerRC, const char pszPfHandlerRC,
9085	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
9086	{
9087	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
9088	pszHandlerR0, pszPfHandlerR0,
9089	pszHandlerRC, pszPfHandlerRC,
9090	pszDesc, phType);
9091	}
9092
9093	/**
9094	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalRegister
9095	*/
9096	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
9097	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
9098	RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc)
9099	{
9100	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalRegister(pDevIns, GCPhys, GCPhysLast, hType,
9101	pvUserR3, pvUserR0, pvUserRC, pszDesc);
9102	}
9103
9104	/**
9105	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalDeregister
9106	*/
9107	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalDeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9108	{
9109	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalDeregister(pDevIns, GCPhys);
9110	}
9111	#endif
9112
9113	/**
9114	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalPageTempOff
9115	*/
9116	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
9117	{
9118	return pDevIns->CTX_SUFF(pHlp)->pfnPGMHandlerPhysicalPageTempOff(pDevIns, GCPhys, GCPhysPage);
9119	}
9120
9121	#ifdef IN_RING3
9122	/**
9123	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalReset
9124	*/
9125	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalReset(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9126	{
9127	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalReset(pDevIns, GCPhys);
9128	}
9129
9130	/**
9131	* @copydoc PDMDEVHLPR3::pfnVMMRegisterPatchMemory
9132	*/
9133	DECLINLINE(int) PDMDevHlpVMMRegisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9134	{
9135	return pDevIns->pHlpR3->pfnVMMRegisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9136	}
9137
9138	/**
9139	* @copydoc PDMDEVHLPR3::pfnVMMDeregisterPatchMemory
9140	*/
9141	DECLINLINE(int) PDMDevHlpVMMDeregisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9142	{
9143	return pDevIns->pHlpR3->pfnVMMDeregisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9144	}
9145
9146	/**
9147	* @copydoc PDMDEVHLPR3::pfnSharedModuleRegister
9148	*/
9149	DECLINLINE(int) PDMDevHlpSharedModuleRegister(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
9150	RTGCPTR GCBaseAddr, uint32_t cbModule,
9151	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions)
9152	{
9153	return pDevIns->pHlpR3->pfnSharedModuleRegister(pDevIns, enmGuestOS, pszModuleName, pszVersion,
9154	GCBaseAddr, cbModule, cRegions, paRegions);
9155	}
9156
9157	/**
9158	* @copydoc PDMDEVHLPR3::pfnSharedModuleUnregister
9159	*/
9160	DECLINLINE(int) PDMDevHlpSharedModuleUnregister(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
9161	RTGCPTR GCBaseAddr, uint32_t cbModule)
9162	{
9163	return pDevIns->pHlpR3->pfnSharedModuleUnregister(pDevIns, pszModuleName, pszVersion, GCBaseAddr, cbModule);
9164	}
9165
9166	/**
9167	* @copydoc PDMDEVHLPR3::pfnSharedModuleGetPageState
9168	*/
9169	DECLINLINE(int) PDMDevHlpSharedModuleGetPageState(PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool *pfShared,
9170	uint64_t *pfPageFlags)
9171	{
9172	return pDevIns->pHlpR3->pfnSharedModuleGetPageState(pDevIns, GCPtrPage, pfShared, pfPageFlags);
9173	}
9174
9175	/**
9176	* @copydoc PDMDEVHLPR3::pfnSharedModuleCheckAll
9177	*/
9178	DECLINLINE(int) PDMDevHlpSharedModuleCheckAll(PPDMDEVINS pDevIns)
9179	{
9180	return pDevIns->pHlpR3->pfnSharedModuleCheckAll(pDevIns);
9181	}
9182
9183	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
9184	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9185	do { \
9186	uint32_t u32GetEnumTmp = 0; \
9187	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
9188	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9189	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
9190	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
9191	} while (0)
9192
9193	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
9194	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9195	do { \
9196	uint8_t bGetEnumTmp = 0; \
9197	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
9198	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9199	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
9200	} while (0)
9201
9202	#endif /* IN_RING3 */
9203
9204	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
9205	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
9206
9207	/**
9208	* Callbacks for VBoxDeviceRegister().
9209	*/
9210	typedef struct PDMDEVREGCB
9211	{
9212	/** Interface version.
9213	* This is set to PDM_DEVREG_CB_VERSION. */
9214	uint32_t u32Version;
9215
9216	/**
9217	* Registers a device with the current VM instance.
9218	*
9219	* @returns VBox status code.
9220	* @param pCallbacks Pointer to the callback table.
9221	* @param pReg Pointer to the device registration record.
9222	* This data must be permanent and readonly.
9223	*/
9224	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
9225	} PDMDEVREGCB;
9226
9227	/** Current version of the PDMDEVREGCB structure. */
9228	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
9229
9230
9231	/**
9232	* The VBoxDevicesRegister callback function.
9233	*
9234	* PDM will invoke this function after loading a device module and letting
9235	* the module decide which devices to register and how to handle conflicts.
9236	*
9237	* @returns VBox status code.
9238	* @param pCallbacks Pointer to the callback table.
9239	* @param u32Version VBox version number.
9240	*/
9241	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
9242
9243	/** @} */
9244
9245	RT_C_DECLS_END
9246
9247	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 91930

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