pdmdev.h@ 91965

Last change on this file since 91965 was 91960, checked in by vboxsync, 3 years ago
VMM,DevPciBios: Add helper callback for PDMR3QueryLun and make use of it, also replace CPUMGetGuestMicroarch with PDMDevHlpCpuGetGuestMicroarch, bugref:10074
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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmcritsectrw.h>
34	#include <VBox/vmm/pdmqueue.h>
35	#include <VBox/vmm/pdmtask.h>
36	#ifdef IN_RING3
37	# include <VBox/vmm/pdmthread.h>
38	#endif
39	#include <VBox/vmm/pdmifs.h>
40	#include <VBox/vmm/pdmins.h>
41	#include <VBox/vmm/pdmcommon.h>
42	#include <VBox/vmm/pdmpcidev.h>
43	#include <VBox/vmm/iom.h>
44	#include <VBox/vmm/mm.h>
45	#include <VBox/vmm/tm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/cfgm.h>
48	#include <VBox/vmm/cpum.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
51	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
52	#include <VBox/msi.h>
53	#include <iprt/stdarg.h>
54	#include <iprt/list.h>
55
56
57	RT_C_DECLS_BEGIN
58
59	/** @defgroup grp_pdm_device The PDM Devices API
60	* @ingroup grp_pdm
61	* @{
62	*/
63
64	/**
65	* Construct a device instance for a VM.
66	*
67	* @returns VBox status.
68	* @param pDevIns The device instance data. If the registration structure
69	* is needed, it can be accessed thru pDevIns->pReg.
70	* @param iInstance Instance number. Use this to figure out which registers
71	* and such to use. The instance number is also found in
72	* pDevIns->iInstance, but since it's likely to be
73	* frequently used PDM passes it as parameter.
74	* @param pCfg Configuration node handle for the driver. This is
75	* expected to be in high demand in the constructor and is
76	* therefore passed as an argument. When using it at other
77	* times, it can be found in pDevIns->pCfg.
78	*/
79	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
80	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
81	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
82
83	/**
84	* Destruct a device instance.
85	*
86	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
87	* resources can be freed correctly.
88	*
89	* @returns VBox status.
90	* @param pDevIns The device instance data.
91	*
92	* @remarks The device critical section is not entered. The routine may delete
93	* the critical section, so the caller cannot exit it.
94	*/
95	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
96	/** Pointer to a FNPDMDEVDESTRUCT() function. */
97	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
98
99	/**
100	* Device relocation callback.
101	*
102	* This is called when the instance data has been relocated in raw-mode context
103	* (RC). It is also called when the RC hypervisor selects changes. The device
104	* must fixup all necessary pointers and re-query all interfaces to other RC
105	* devices and drivers.
106	*
107	* Before the RC code is executed the first time, this function will be called
108	* with a 0 delta so RC pointer calculations can be one in one place.
109	*
110	* @param pDevIns Pointer to the device instance.
111	* @param offDelta The relocation delta relative to the old location.
112	*
113	* @remarks A relocation CANNOT fail.
114	*
115	* @remarks The device critical section is not entered. The relocations should
116	* not normally require any locking.
117	*/
118	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
119	/** Pointer to a FNPDMDEVRELOCATE() function. */
120	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
121
122	/**
123	* Power On notification.
124	*
125	* @returns VBox status.
126	* @param pDevIns The device instance data.
127	*
128	* @remarks Caller enters the device critical section.
129	*/
130	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
131	/** Pointer to a FNPDMDEVPOWERON() function. */
132	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
133
134	/**
135	* Reset notification.
136	*
137	* @returns VBox status.
138	* @param pDevIns The device instance data.
139	*
140	* @remarks Caller enters the device critical section.
141	*/
142	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
143	/** Pointer to a FNPDMDEVRESET() function. */
144	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
145
146	/**
147	* Soft reset notification.
148	*
149	* This is mainly for emulating the 286 style protected mode exits, in which
150	* most devices should remain in their current state.
151	*
152	* @returns VBox status.
153	* @param pDevIns The device instance data.
154	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
155	*
156	* @remarks Caller enters the device critical section.
157	*/
158	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
159	/** Pointer to a FNPDMDEVSOFTRESET() function. */
160	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
161
162	/** @name PDMVMRESET_F_XXX - VM reset flags.
163	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
164	* reset via PDMDevHlpVMReset.
165	* @{ */
166	/** Unknown reason. */
167	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
168	/** GIM triggered reset. */
169	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
170	/** The last source always causing hard resets. */
171	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
172	/** ACPI triggered reset. */
173	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
174	/** PS/2 system port A (92h) reset. */
175	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
176	/** Keyboard reset. */
177	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
178	/** Tripple fault. */
179	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
180	/** Reset source mask. */
181	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
182	/** @} */
183
184	/**
185	* Suspend notification.
186	*
187	* @returns VBox status.
188	* @param pDevIns The device instance data.
189	* @thread EMT(0)
190	*
191	* @remarks Caller enters the device critical section.
192	*/
193	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
194	/** Pointer to a FNPDMDEVSUSPEND() function. */
195	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
196
197	/**
198	* Resume notification.
199	*
200	* @returns VBox status.
201	* @param pDevIns The device instance data.
202	*
203	* @remarks Caller enters the device critical section.
204	*/
205	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
206	/** Pointer to a FNPDMDEVRESUME() function. */
207	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
208
209	/**
210	* Power Off notification.
211	*
212	* This is always called when VMR3PowerOff is called.
213	* There will be no callback when hot plugging devices.
214	*
215	* @param pDevIns The device instance data.
216	* @thread EMT(0)
217	*
218	* @remarks Caller enters the device critical section.
219	*/
220	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
221	/** Pointer to a FNPDMDEVPOWEROFF() function. */
222	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
223
224	/**
225	* Attach command.
226	*
227	* This is called to let the device attach to a driver for a specified LUN
228	* at runtime. This is not called during VM construction, the device
229	* constructor has to attach to all the available drivers.
230	*
231	* This is like plugging in the keyboard or mouse after turning on the PC.
232	*
233	* @returns VBox status code.
234	* @param pDevIns The device instance.
235	* @param iLUN The logical unit which is being attached.
236	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
237	*
238	* @remarks Caller enters the device critical section.
239	*/
240	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
241	/** Pointer to a FNPDMDEVATTACH() function. */
242	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
243
244	/**
245	* Detach notification.
246	*
247	* This is called when a driver is detaching itself from a LUN of the device.
248	* The device should adjust its state to reflect this.
249	*
250	* This is like unplugging the network cable to use it for the laptop or
251	* something while the PC is still running.
252	*
253	* @param pDevIns The device instance.
254	* @param iLUN The logical unit which is being detached.
255	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
256	*
257	* @remarks Caller enters the device critical section.
258	*/
259	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
260	/** Pointer to a FNPDMDEVDETACH() function. */
261	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
262
263	/**
264	* Query the base interface of a logical unit.
265	*
266	* @returns VBOX status code.
267	* @param pDevIns The device instance.
268	* @param iLUN The logicial unit to query.
269	* @param ppBase Where to store the pointer to the base interface of the LUN.
270	*
271	* @remarks The device critical section is not entered.
272	*/
273	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
274	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
275	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
276
277	/**
278	* Init complete notification (after ring-0 & RC init since 5.1).
279	*
280	* This can be done to do communication with other devices and other
281	* initialization which requires everything to be in place.
282	*
283	* @returns VBOX status code.
284	* @param pDevIns The device instance.
285	*
286	* @remarks Caller enters the device critical section.
287	*/
288	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
289	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
290	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
291
292
293	/**
294	* The context of a pfnMemSetup call.
295	*/
296	typedef enum PDMDEVMEMSETUPCTX
297	{
298	/** Invalid zero value. */
299	PDMDEVMEMSETUPCTX_INVALID = 0,
300	/** After construction. */
301	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
302	/** After reset. */
303	PDMDEVMEMSETUPCTX_AFTER_RESET,
304	/** Type size hack. */
305	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
306	} PDMDEVMEMSETUPCTX;
307
308
309	/**
310	* PDM Device Registration Structure.
311	*
312	* This structure is used when registering a device from VBoxInitDevices() in HC
313	* Ring-3. PDM will continue use till the VM is terminated.
314	*
315	* @note The first part is the same in every context.
316	*/
317	typedef struct PDMDEVREGR3
318	{
319	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
320	uint32_t u32Version;
321	/** Reserved, must be zero. */
322	uint32_t uReserved0;
323	/** Device name, must match the ring-3 one. */
324	char szName[32];
325	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
326	uint32_t fFlags;
327	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
328	uint32_t fClass;
329	/** Maximum number of instances (per VM). */
330	uint32_t cMaxInstances;
331	/** The shared data structure version number. */
332	uint32_t uSharedVersion;
333	/** Size of the instance data. */
334	uint32_t cbInstanceShared;
335	/** Size of the ring-0 instance data. */
336	uint32_t cbInstanceCC;
337	/** Size of the raw-mode instance data. */
338	uint32_t cbInstanceRC;
339	/** Max number of PCI devices. */
340	uint16_t cMaxPciDevices;
341	/** Max number of MSI-X vectors in any of the PCI devices. */
342	uint16_t cMaxMsixVectors;
343	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
344	* remain unchanged from registration till VM destruction. */
345	const char *pszDescription;
346
347	/** Name of the raw-mode context module (no path).
348	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
349	const char *pszRCMod;
350	/** Name of the ring-0 module (no path).
351	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
352	const char *pszR0Mod;
353
354	/** Construct instance - required. */
355	PFNPDMDEVCONSTRUCT pfnConstruct;
356	/** Destruct instance - optional.
357	* Critical section NOT entered (will be destroyed). */
358	PFNPDMDEVDESTRUCT pfnDestruct;
359	/** Relocation command - optional.
360	* Critical section NOT entered. */
361	PFNPDMDEVRELOCATE pfnRelocate;
362	/**
363	* Memory setup callback.
364	*
365	* @param pDevIns The device instance data.
366	* @param enmCtx Indicates the context of the call.
367	* @remarks The critical section is entered prior to calling this method.
368	*/
369	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
370	/** Power on notification - optional.
371	* Critical section is entered. */
372	PFNPDMDEVPOWERON pfnPowerOn;
373	/** Reset notification - optional.
374	* Critical section is entered. */
375	PFNPDMDEVRESET pfnReset;
376	/** Suspend notification - optional.
377	* Critical section is entered. */
378	PFNPDMDEVSUSPEND pfnSuspend;
379	/** Resume notification - optional.
380	* Critical section is entered. */
381	PFNPDMDEVRESUME pfnResume;
382	/** Attach command - optional.
383	* Critical section is entered. */
384	PFNPDMDEVATTACH pfnAttach;
385	/** Detach notification - optional.
386	* Critical section is entered. */
387	PFNPDMDEVDETACH pfnDetach;
388	/** Query a LUN base interface - optional.
389	* Critical section is NOT entered. */
390	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
391	/** Init complete notification - optional.
392	* Critical section is entered. */
393	PFNPDMDEVINITCOMPLETE pfnInitComplete;
394	/** Power off notification - optional.
395	* Critical section is entered. */
396	PFNPDMDEVPOWEROFF pfnPowerOff;
397	/** Software system reset notification - optional.
398	* Critical section is entered. */
399	PFNPDMDEVSOFTRESET pfnSoftReset;
400
401	/** @name Reserved for future extensions, must be zero.
402	* @{ */
403	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
406	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
407	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
408	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
409	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
410	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
411	/** @} */
412
413	/** Initialization safty marker. */
414	uint32_t u32VersionEnd;
415	} PDMDEVREGR3;
416	/** Pointer to a PDM Device Structure. */
417	typedef PDMDEVREGR3 *PPDMDEVREGR3;
418	/** Const pointer to a PDM Device Structure. */
419	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
420	/** Current DEVREGR3 version number. */
421	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
422
423
424	/** PDM Device Flags.
425	* @{ */
426	/** This flag is used to indicate that the device has a R0 component. */
427	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
428	/** Requires the ring-0 component, ignore configuration values. */
429	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
430	/** Requires the ring-0 component, ignore configuration values. */
431	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
432
433	/** This flag is used to indicate that the device has a RC component. */
434	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
435	/** Requires the raw-mode component, ignore configuration values. */
436	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
437	/** Requires the raw-mode component, ignore configuration values. */
438	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
439
440	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
441	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
442
443	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
444	* The bit count for the current host.
445	* @note Superfluous, but still around for hysterical raisins. */
446	#if HC_ARCH_BITS == 32
447	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
448	#elif HC_ARCH_BITS == 64
449	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
450	#else
451	# error Unsupported HC_ARCH_BITS value.
452	#endif
453	/** The host bit count mask. */
454	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
455
456	/** The device support only 32-bit guests. */
457	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
458	/** The device support only 64-bit guests. */
459	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
460	/** The device support both 32-bit & 64-bit guests. */
461	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
462	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
463	* The guest bit count for the current compilation. */
464	#if GC_ARCH_BITS == 32
465	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
466	#elif GC_ARCH_BITS == 64
467	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
468	#else
469	# error Unsupported GC_ARCH_BITS value.
470	#endif
471	/** The guest bit count mask. */
472	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
473
474	/** A convenience. */
475	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
476
477	/** Indicates that the device needs to be notified before the drivers when suspending. */
478	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
479	/** Indicates that the device needs to be notified before the drivers when powering off. */
480	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
481	/** Indicates that the device needs to be notified before the drivers when resetting. */
482	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
483
484	/** This flag is used to indicate that the device has been converted to the
485	* new device style. */
486	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
487
488	/** @} */
489
490
491	/** PDM Device Classes.
492	* The order is important, lower bit earlier instantiation.
493	* @{ */
494	/** Architecture device. */
495	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
496	/** Architecture BIOS device. */
497	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
498	/** PCI bus brigde. */
499	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
500	/** PCI built-in device (e.g. PCI root complex devices). */
501	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
502	/** Input device (mouse, keyboard, joystick, HID, ...). */
503	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
504	/** Interrupt controller (PIC). */
505	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
506	/** Interval controoler (PIT). */
507	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
508	/** RTC/CMOS. */
509	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
510	/** DMA controller. */
511	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
512	/** VMM Device. */
513	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
514	/** Graphics device, like VGA. */
515	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
516	/** Storage controller device. */
517	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
518	/** Network interface controller. */
519	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
520	/** Audio. */
521	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
522	/** USB HIC. */
523	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
524	/** ACPI. */
525	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
526	/** Serial controller device. */
527	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
528	/** Parallel controller device */
529	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
530	/** Host PCI pass-through device */
531	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
532	/** Misc devices (always last). */
533	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
534	/** @} */
535
536
537	/**
538	* PDM Device Registration Structure, ring-0.
539	*
540	* This structure is used when registering a device from VBoxInitDevices() in HC
541	* Ring-0. PDM will continue use till the VM is terminated.
542	*/
543	typedef struct PDMDEVREGR0
544	{
545	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
546	uint32_t u32Version;
547	/** Reserved, must be zero. */
548	uint32_t uReserved0;
549	/** Device name, must match the ring-3 one. */
550	char szName[32];
551	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
552	uint32_t fFlags;
553	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
554	uint32_t fClass;
555	/** Maximum number of instances (per VM). */
556	uint32_t cMaxInstances;
557	/** The shared data structure version number. */
558	uint32_t uSharedVersion;
559	/** Size of the instance data. */
560	uint32_t cbInstanceShared;
561	/** Size of the ring-0 instance data. */
562	uint32_t cbInstanceCC;
563	/** Size of the raw-mode instance data. */
564	uint32_t cbInstanceRC;
565	/** Max number of PCI devices. */
566	uint16_t cMaxPciDevices;
567	/** Max number of MSI-X vectors in any of the PCI devices. */
568	uint16_t cMaxMsixVectors;
569	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
570	* remain unchanged from registration till VM destruction. */
571	const char *pszDescription;
572
573	/**
574	* Early construction callback (optional).
575	*
576	* This is called right after the device instance structure has been allocated
577	* and before the ring-3 constructor gets called.
578	*
579	* @returns VBox status code.
580	* @param pDevIns The device instance data.
581	* @note The destructure is always called, regardless of the return status.
582	*/
583	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
584
585	/**
586	* Regular construction callback (optional).
587	*
588	* This is called after (or during) the ring-3 constructor.
589	*
590	* @returns VBox status code.
591	* @param pDevIns The device instance data.
592	* @note The destructure is always called, regardless of the return status.
593	*/
594	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
595
596	/**
597	* Destructor (optional).
598	*
599	* This is called after the ring-3 destruction. This is not called if ring-3
600	* fails to trigger it (e.g. process is killed or crashes).
601	*
602	* @param pDevIns The device instance data.
603	*/
604	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
605
606	/**
607	* Final destructor (optional).
608	*
609	* This is called right before the memory is freed, which happens when the
610	* VM/GVM object is destroyed. This is always called.
611	*
612	* @param pDevIns The device instance data.
613	*/
614	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
615
616	/**
617	* Generic request handler (optional).
618	*
619	* @param pDevIns The device instance data.
620	* @param uReq Device specific request.
621	* @param uArg Request argument.
622	*/
623	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
624
625	/** @name Reserved for future extensions, must be zero.
626	* @{ */
627	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
630	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
631	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
632	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
633	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
634	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
635	/** @} */
636
637	/** Initialization safty marker. */
638	uint32_t u32VersionEnd;
639	} PDMDEVREGR0;
640	/** Pointer to a ring-0 PDM device registration structure. */
641	typedef PDMDEVREGR0 *PPDMDEVREGR0;
642	/** Pointer to a const ring-0 PDM device registration structure. */
643	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
644	/** Current DEVREGR0 version number. */
645	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
646
647
648	/**
649	* PDM Device Registration Structure, raw-mode
650	*
651	* At the moment, this structure is mostly here to match the other two contexts.
652	*/
653	typedef struct PDMDEVREGRC
654	{
655	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
656	uint32_t u32Version;
657	/** Reserved, must be zero. */
658	uint32_t uReserved0;
659	/** Device name, must match the ring-3 one. */
660	char szName[32];
661	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
662	uint32_t fFlags;
663	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
664	uint32_t fClass;
665	/** Maximum number of instances (per VM). */
666	uint32_t cMaxInstances;
667	/** The shared data structure version number. */
668	uint32_t uSharedVersion;
669	/** Size of the instance data. */
670	uint32_t cbInstanceShared;
671	/** Size of the ring-0 instance data. */
672	uint32_t cbInstanceCC;
673	/** Size of the raw-mode instance data. */
674	uint32_t cbInstanceRC;
675	/** Max number of PCI devices. */
676	uint16_t cMaxPciDevices;
677	/** Max number of MSI-X vectors in any of the PCI devices. */
678	uint16_t cMaxMsixVectors;
679	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
680	* remain unchanged from registration till VM destruction. */
681	const char *pszDescription;
682
683	/**
684	* Constructor callback.
685	*
686	* This is called much later than both the ring-0 and ring-3 constructors, since
687	* raw-mode v2 require a working VMM to run actual code.
688	*
689	* @returns VBox status code.
690	* @param pDevIns The device instance data.
691	* @note The destructure is always called, regardless of the return status.
692	*/
693	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
694
695	/** @name Reserved for future extensions, must be zero.
696	* @{ */
697	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
700	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
701	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
702	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
703	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
704	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
705	/** @} */
706
707	/** Initialization safty marker. */
708	uint32_t u32VersionEnd;
709	} PDMDEVREGRC;
710	/** Pointer to a raw-mode PDM device registration structure. */
711	typedef PDMDEVREGRC *PPDMDEVREGRC;
712	/** Pointer to a const raw-mode PDM device registration structure. */
713	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
714	/** Current DEVREGRC version number. */
715	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
716
717
718
719	/** @def PDM_DEVREG_VERSION
720	* Current DEVREG version number. */
721	/** @typedef PDMDEVREGR3
722	* A current context PDM device registration structure. */
723	/** @typedef PPDMDEVREGR3
724	* Pointer to a current context PDM device registration structure. */
725	/** @typedef PCPDMDEVREGR3
726	* Pointer to a const current context PDM device registration structure. */
727	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
728	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
729	typedef PDMDEVREGR3 PDMDEVREG;
730	typedef PPDMDEVREGR3 PPDMDEVREG;
731	typedef PCPDMDEVREGR3 PCPDMDEVREG;
732	#elif defined(IN_RING0)
733	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
734	typedef PDMDEVREGR0 PDMDEVREG;
735	typedef PPDMDEVREGR0 PPDMDEVREG;
736	typedef PCPDMDEVREGR0 PCPDMDEVREG;
737	#elif defined(IN_RC)
738	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
739	typedef PDMDEVREGRC PDMDEVREG;
740	typedef PPDMDEVREGRC PPDMDEVREG;
741	typedef PCPDMDEVREGRC PCPDMDEVREG;
742	#else
743	# error "Not IN_RING3, IN_RING0 or IN_RC"
744	#endif
745
746
747	/**
748	* Device registrations for ring-0 modules.
749	*
750	* This structure is used directly and must therefore reside in persistent
751	* memory (i.e. the data section).
752	*/
753	typedef struct PDMDEVMODREGR0
754	{
755	/** The structure version (PDM_DEVMODREGR0_VERSION). */
756	uint32_t u32Version;
757	/** Number of devices in the array papDevRegs points to. */
758	uint32_t cDevRegs;
759	/** Pointer to device registration structures. */
760	PCPDMDEVREGR0 *papDevRegs;
761	/** The ring-0 module handle - PDM internal, fingers off. */
762	void *hMod;
763	/** List entry - PDM internal, fingers off. */
764	RTLISTNODE ListEntry;
765	} PDMDEVMODREGR0;
766	/** Pointer to device registriations for a ring-0 module. */
767	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
768	/** Current PDMDEVMODREGR0 version number. */
769	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
770
771
772	/** @name IRQ Level for use with the *SetIrq APIs.
773	* @{
774	*/
775	/** Assert the IRQ (can assume value 1). */
776	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
777	/** Deassert the IRQ (can assume value 0). */
778	#define PDM_IRQ_LEVEL_LOW 0
779	/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
780	* automatically deasserts it after delivery to the APIC (IOAPIC).
781	* @note Only suitable for edge trigger interrupts. */
782	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
783	/** @} */
784
785	/**
786	* Registration record for MSI/MSI-X emulation.
787	*/
788	typedef struct PDMMSIREG
789	{
790	/** Number of MSI interrupt vectors, 0 if MSI not supported */
791	uint16_t cMsiVectors;
792	/** Offset of MSI capability */
793	uint8_t iMsiCapOffset;
794	/** Offset of next capability to MSI */
795	uint8_t iMsiNextOffset;
796	/** If we support 64-bit MSI addressing */
797	bool fMsi64bit;
798	/** If we do not support per-vector masking */
799	bool fMsiNoMasking;
800
801	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
802	uint16_t cMsixVectors;
803	/** Offset of MSI-X capability */
804	uint8_t iMsixCapOffset;
805	/** Offset of next capability to MSI-X */
806	uint8_t iMsixNextOffset;
807	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
808	uint8_t iMsixBar;
809	} PDMMSIREG;
810	typedef PDMMSIREG *PPDMMSIREG;
811
812	/**
813	* PCI Bus registration structure.
814	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
815	*/
816	typedef struct PDMPCIBUSREGR3
817	{
818	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
819	uint32_t u32Version;
820
821	/**
822	* Registers the device with the default PCI bus.
823	*
824	* @returns VBox status code.
825	* @param pDevIns Device instance of the PCI Bus.
826	* @param pPciDev The PCI device structure.
827	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
828	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
829	* device number (0-31).
830	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
831	* function number (0-7).
832	* @param pszName Device name (static but not unique).
833	*
834	* @remarks Caller enters the PDM critical section.
835	*/
836	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
837	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
838
839	/**
840	* Initialize MSI or MSI-X emulation support in a PCI device.
841	*
842	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
843	* vast majority of device emulation it covers everything necessary. It's
844	* fully automatic, taking care of all BAR and config space requirements,
845	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
846	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
847	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
848	*
849	* A device not using this can still offer MSI/MSI-X. In this case it's
850	* completely up to the device (in the MSI-X case) to create/register the
851	* necessary MMIO BAR, handle all config space/BAR updating and take care
852	* of delivering the interrupts appropriately.
853	*
854	* @returns VBox status code.
855	* @param pDevIns Device instance of the PCI Bus.
856	* @param pPciDev The PCI device structure.
857	* @param pMsiReg MSI emulation registration structure
858	* @remarks Caller enters the PDM critical section.
859	*/
860	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
861
862	/**
863	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
864	*
865	* @returns VBox status code.
866	* @param pDevIns Device instance of the PCI Bus.
867	* @param pPciDev The PCI device structure.
868	* @param iRegion The region number.
869	* @param cbRegion Size of the region.
870	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
871	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
872	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
873	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
874	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
875	* @a fFlags, UINT64_MAX if no handle is passed
876	* (old style).
877	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
878	* is given.
879	* @remarks Caller enters the PDM critical section.
880	*/
881	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
882	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
883	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
884
885	/**
886	* Register PCI configuration space read/write intercept callbacks.
887	*
888	* @param pDevIns Device instance of the PCI Bus.
889	* @param pPciDev The PCI device structure.
890	* @param pfnRead Pointer to the user defined PCI config read function.
891	* @param pfnWrite Pointer to the user defined PCI config write function.
892	* to call default PCI config write function. Can be NULL.
893	* @remarks Caller enters the PDM critical section.
894	* @thread EMT
895	*/
896	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
897	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
898
899	/**
900	* Perform a PCI configuration space write, bypassing interception.
901	*
902	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
903	*
904	* @returns Strict VBox status code (mainly DBGFSTOP).
905	* @param pDevIns Device instance of the PCI Bus.
906	* @param pPciDev The PCI device which config space is being read.
907	* @param uAddress The config space address.
908	* @param cb The size of the read: 1, 2 or 4 bytes.
909	* @param u32Value The value to write.
910	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
911	* that the (root) bus will have done that already.
912	*/
913	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
914	uint32_t uAddress, unsigned cb, uint32_t u32Value));
915
916	/**
917	* Perform a PCI configuration space read, bypassing interception.
918	*
919	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
920	*
921	* @returns Strict VBox status code (mainly DBGFSTOP).
922	* @param pDevIns Device instance of the PCI Bus.
923	* @param pPciDev The PCI device which config space is being read.
924	* @param uAddress The config space address.
925	* @param cb The size of the read: 1, 2 or 4 bytes.
926	* @param pu32Value Where to return the value.
927	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
928	* that the (root) bus will have done that already.
929	*/
930	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
931	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
932
933	/**
934	* Set the IRQ for a PCI device.
935	*
936	* @param pDevIns Device instance of the PCI Bus.
937	* @param pPciDev The PCI device structure.
938	* @param iIrq IRQ number to set.
939	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
940	* @param uTagSrc The IRQ tag and source (for tracing).
941	* @remarks Caller enters the PDM critical section.
942	*/
943	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
944
945	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
946	uint32_t u32EndVersion;
947	} PDMPCIBUSREGR3;
948	/** Pointer to a PCI bus registration structure. */
949	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
950	/** Current PDMPCIBUSREGR3 version number. */
951	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
952
953	/**
954	* PCI Bus registration structure for ring-0.
955	*/
956	typedef struct PDMPCIBUSREGR0
957	{
958	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
959	uint32_t u32Version;
960	/** The PCI bus number (from ring-3 registration). */
961	uint32_t iBus;
962	/**
963	* Set the IRQ for a PCI device.
964	*
965	* @param pDevIns Device instance of the PCI Bus.
966	* @param pPciDev The PCI device structure.
967	* @param iIrq IRQ number to set.
968	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
969	* @param uTagSrc The IRQ tag and source (for tracing).
970	* @remarks Caller enters the PDM critical section.
971	*/
972	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
973	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
974	uint32_t u32EndVersion;
975	} PDMPCIBUSREGR0;
976	/** Pointer to a PCI bus ring-0 registration structure. */
977	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
978	/** Current PDMPCIBUSREGR0 version number. */
979	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
980
981	/**
982	* PCI Bus registration structure for raw-mode.
983	*/
984	typedef struct PDMPCIBUSREGRC
985	{
986	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
987	uint32_t u32Version;
988	/** The PCI bus number (from ring-3 registration). */
989	uint32_t iBus;
990	/**
991	* Set the IRQ for a PCI device.
992	*
993	* @param pDevIns Device instance of the PCI Bus.
994	* @param pPciDev The PCI device structure.
995	* @param iIrq IRQ number to set.
996	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
997	* @param uTagSrc The IRQ tag and source (for tracing).
998	* @remarks Caller enters the PDM critical section.
999	*/
1000	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
1001	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1002	uint32_t u32EndVersion;
1003	} PDMPCIBUSREGRC;
1004	/** Pointer to a PCI bus raw-mode registration structure. */
1005	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1006	/** Current PDMPCIBUSREGRC version number. */
1007	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1008
1009	/** PCI bus registration structure for the current context. */
1010	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1011	/** Pointer to a PCI bus registration structure for the current context. */
1012	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1013	/** PCI bus registration structure version for the current context. */
1014	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1015
1016
1017	/**
1018	* PCI Bus RC helpers.
1019	*/
1020	typedef struct PDMPCIHLPRC
1021	{
1022	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1023	uint32_t u32Version;
1024
1025	/**
1026	* Set an ISA IRQ.
1027	*
1028	* @param pDevIns PCI device instance.
1029	* @param iIrq IRQ number to set.
1030	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1031	* @param uTagSrc The IRQ tag and source (for tracing).
1032	* @thread EMT only.
1033	*/
1034	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1035
1036	/**
1037	* Set an I/O-APIC IRQ.
1038	*
1039	* @param pDevIns PCI device instance.
1040	* @param uBusDevFn The bus:device:function of the device initiating the
1041	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1042	* interrupt.
1043	* @param iIrq IRQ number to set.
1044	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1045	* @param uTagSrc The IRQ tag and source (for tracing).
1046	* @thread EMT only.
1047	*/
1048	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1049
1050	/**
1051	* Send an MSI.
1052	*
1053	* @param pDevIns PCI device instance.
1054	* @param uBusDevFn The bus:device:function of the device initiating the
1055	* MSI. Cannot be NIL_PCIBDF.
1056	* @param pMsi The MSI to send.
1057	* @param uTagSrc The IRQ tag and source (for tracing).
1058	* @thread EMT only.
1059	*/
1060	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1061
1062
1063	/**
1064	* Acquires the PDM lock.
1065	*
1066	* @returns VINF_SUCCESS on success.
1067	* @returns rc if we failed to acquire the lock.
1068	* @param pDevIns The PCI device instance.
1069	* @param rc What to return if we fail to acquire the lock.
1070	*
1071	* @sa PDMCritSectEnter
1072	*/
1073	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1074
1075	/**
1076	* Releases the PDM lock.
1077	*
1078	* @param pDevIns The PCI device instance.
1079	*/
1080	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1081
1082	/**
1083	* Gets a bus by it's PDM ordinal (typically the parent bus).
1084	*
1085	* @returns Pointer to the device instance of the bus.
1086	* @param pDevIns The PCI bus device instance.
1087	* @param idxPdmBus The PDM ordinal value of the bus to get.
1088	*/
1089	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1090
1091	/** Just a safety precaution. */
1092	uint32_t u32TheEnd;
1093	} PDMPCIHLPRC;
1094	/** Pointer to PCI helpers. */
1095	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1096	/** Pointer to const PCI helpers. */
1097	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1098
1099	/** Current PDMPCIHLPRC version number. */
1100	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1101
1102
1103	/**
1104	* PCI Bus R0 helpers.
1105	*/
1106	typedef struct PDMPCIHLPR0
1107	{
1108	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1109	uint32_t u32Version;
1110
1111	/**
1112	* Set an ISA IRQ.
1113	*
1114	* @param pDevIns PCI device instance.
1115	* @param iIrq IRQ number to set.
1116	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1117	* @param uTagSrc The IRQ tag and source (for tracing).
1118	* @thread EMT only.
1119	*/
1120	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1121
1122	/**
1123	* Set an I/O-APIC IRQ.
1124	*
1125	* @param pDevIns PCI device instance.
1126	* @param uBusDevFn The bus:device:function of the device initiating the
1127	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1128	* interrupt.
1129	* @param iIrq IRQ number to set.
1130	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1131	* @param uTagSrc The IRQ tag and source (for tracing).
1132	* @thread EMT only.
1133	*/
1134	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1135
1136	/**
1137	* Send an MSI.
1138	*
1139	* @param pDevIns PCI device instance.
1140	* @param uBusDevFn The bus:device:function of the device initiating the
1141	* MSI. Cannot be NIL_PCIBDF.
1142	* @param pMsi The MSI to send.
1143	* @param uTagSrc The IRQ tag and source (for tracing).
1144	* @thread EMT only.
1145	*/
1146	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1147
1148	/**
1149	* Acquires the PDM lock.
1150	*
1151	* @returns VINF_SUCCESS on success.
1152	* @returns rc if we failed to acquire the lock.
1153	* @param pDevIns The PCI device instance.
1154	* @param rc What to return if we fail to acquire the lock.
1155	*
1156	* @sa PDMCritSectEnter
1157	*/
1158	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1159
1160	/**
1161	* Releases the PDM lock.
1162	*
1163	* @param pDevIns The PCI device instance.
1164	*/
1165	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1166
1167	/**
1168	* Gets a bus by it's PDM ordinal (typically the parent bus).
1169	*
1170	* @returns Pointer to the device instance of the bus.
1171	* @param pDevIns The PCI bus device instance.
1172	* @param idxPdmBus The PDM ordinal value of the bus to get.
1173	*/
1174	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1175
1176	/** Just a safety precaution. */
1177	uint32_t u32TheEnd;
1178	} PDMPCIHLPR0;
1179	/** Pointer to PCI helpers. */
1180	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1181	/** Pointer to const PCI helpers. */
1182	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1183
1184	/** Current PDMPCIHLPR0 version number. */
1185	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1186
1187	/**
1188	* PCI device helpers.
1189	*/
1190	typedef struct PDMPCIHLPR3
1191	{
1192	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1193	uint32_t u32Version;
1194
1195	/**
1196	* Set an ISA IRQ.
1197	*
1198	* @param pDevIns The PCI device instance.
1199	* @param iIrq IRQ number to set.
1200	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1201	* @param uTagSrc The IRQ tag and source (for tracing).
1202	*/
1203	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1204
1205	/**
1206	* Set an I/O-APIC IRQ.
1207	*
1208	* @param pDevIns The PCI device instance.
1209	* @param uBusDevFn The bus:device:function of the device initiating the
1210	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1211	* interrupt.
1212	* @param iIrq IRQ number to set.
1213	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1214	* @param uTagSrc The IRQ tag and source (for tracing).
1215	*/
1216	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1217
1218	/**
1219	* Send an MSI.
1220	*
1221	* @param pDevIns PCI device instance.
1222	* @param uBusDevFn The bus:device:function of the device initiating the
1223	* MSI. Cannot be NIL_PCIBDF.
1224	* @param pMsi The MSI to send.
1225	* @param uTagSrc The IRQ tag and source (for tracing).
1226	*/
1227	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1228
1229	/**
1230	* Acquires the PDM lock.
1231	*
1232	* @returns VINF_SUCCESS on success.
1233	* @returns Fatal error on failure.
1234	* @param pDevIns The PCI device instance.
1235	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1236	*
1237	* @sa PDMCritSectEnter
1238	*/
1239	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1240
1241	/**
1242	* Releases the PDM lock.
1243	*
1244	* @param pDevIns The PCI device instance.
1245	*/
1246	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1247
1248	/**
1249	* Gets a bus by it's PDM ordinal (typically the parent bus).
1250	*
1251	* @returns Pointer to the device instance of the bus.
1252	* @param pDevIns The PCI bus device instance.
1253	* @param idxPdmBus The PDM ordinal value of the bus to get.
1254	*/
1255	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1256
1257	/** Just a safety precaution. */
1258	uint32_t u32TheEnd;
1259	} PDMPCIHLPR3;
1260	/** Pointer to PCI helpers. */
1261	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1262	/** Pointer to const PCI helpers. */
1263	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1264
1265	/** Current PDMPCIHLPR3 version number. */
1266	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1267
1268
1269	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1270	* These flags are used for memory access transactions via the IOMMU interface.
1271	* @{ */
1272	/** Memory read. */
1273	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1274	/** Memory write. */
1275	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1276	/** Valid flag mask. */
1277	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1278	/** @} */
1279
1280	/**
1281	* IOMMU registration structure for ring-0.
1282	*/
1283	typedef struct PDMIOMMUREGR0
1284	{
1285	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1286	* version. */
1287	uint32_t u32Version;
1288	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1289	uint32_t idxIommu;
1290
1291	/**
1292	* Translates the physical address for a memory transaction through the IOMMU.
1293	*
1294	* @returns VBox status code.
1295	* @param pDevIns The IOMMU device instance.
1296	* @param idDevice The device identifier (bus, device, function).
1297	* @param uIova The I/O virtual address being accessed.
1298	* @param cbIova The size of the access.
1299	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1300	* @param pGCPhysSpa Where to store the translated system physical address.
1301	* @param pcbContiguous Where to store the number of contiguous bytes translated
1302	* and permission-checked.
1303	*
1304	* @thread Any.
1305	*/
1306	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1307	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1308
1309	/**
1310	* Translates in bulk physical page addresses for memory transactions through the
1311	* IOMMU.
1312	*
1313	* @returns VBox status code.
1314	* @param pDevIns The IOMMU device instance.
1315	* @param idDevice The device identifier (bus, device, function).
1316	* @param cIovas The number of I/O virtual addresses being accessed.
1317	* @param pauIovas The I/O virtual addresses being accessed.
1318	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1319	* @param paGCPhysSpa Where to store the translated system physical page
1320	* addresses.
1321	*
1322	* @thread Any.
1323	*/
1324	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1325	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1326
1327	/**
1328	* Performs an interrupt remap request through the IOMMU.
1329	*
1330	* @returns VBox status code.
1331	* @param pDevIns The IOMMU device instance.
1332	* @param idDevice The device identifier (bus, device, function).
1333	* @param pMsiIn The source MSI.
1334	* @param pMsiOut Where to store the remapped MSI.
1335	*
1336	* @thread Any.
1337	*/
1338	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1339
1340	/** Just a safety precaution. */
1341	uint32_t u32TheEnd;
1342	} PDMIOMMUREGR0;
1343	/** Pointer to a IOMMU registration structure. */
1344	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1345
1346	/** Current PDMIOMMUREG version number. */
1347	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1348
1349
1350	/**
1351	* IOMMU registration structure for raw-mode.
1352	*/
1353	typedef struct PDMIOMMUREGRC
1354	{
1355	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1356	* version. */
1357	uint32_t u32Version;
1358	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1359	uint32_t idxIommu;
1360
1361	/**
1362	* Translates the physical address for a memory transaction through the IOMMU.
1363	*
1364	* @returns VBox status code.
1365	* @param pDevIns The IOMMU device instance.
1366	* @param idDevice The device identifier (bus, device, function).
1367	* @param uIova The I/O virtual address being accessed.
1368	* @param cbIova The size of the access.
1369	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1370	* @param pGCPhysSpa Where to store the translated system physical address.
1371	* @param pcbContiguous Where to store the number of contiguous bytes translated
1372	* and permission-checked.
1373	*
1374	* @thread Any.
1375	*/
1376	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1377	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1378
1379	/**
1380	* Translates in bulk physical page addresses for memory transactions through the
1381	* IOMMU.
1382	*
1383	* @returns VBox status code.
1384	* @param pDevIns The IOMMU device instance.
1385	* @param idDevice The device identifier (bus, device, function).
1386	* @param cIovas The number of I/O virtual addresses being accessed.
1387	* @param pauIovas The I/O virtual addresses being accessed.
1388	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1389	* @param paGCPhysSpa Where to store the translated system physical page
1390	* addresses.
1391	*
1392	* @thread Any.
1393	*/
1394	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1395	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1396
1397	/**
1398	* Performs an interrupt remap request through the IOMMU.
1399	*
1400	* @returns VBox status code.
1401	* @param pDevIns The IOMMU device instance.
1402	* @param idDevice The device identifier (bus, device, function).
1403	* @param pMsiIn The source MSI.
1404	* @param pMsiOut Where to store the remapped MSI.
1405	*
1406	* @thread Any.
1407	*/
1408	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1409
1410	/** Just a safety precaution. */
1411	uint32_t u32TheEnd;
1412	} PDMIOMMUREGRC;
1413	/** Pointer to a IOMMU registration structure. */
1414	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1415
1416	/** Current PDMIOMMUREG version number. */
1417	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1418
1419
1420	/**
1421	* IOMMU registration structure for ring-3.
1422	*/
1423	typedef struct PDMIOMMUREGR3
1424	{
1425	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1426	* version. */
1427	uint32_t u32Version;
1428	/** Padding. */
1429	uint32_t uPadding0;
1430
1431	/**
1432	* Translates the physical address for a memory transaction through the IOMMU.
1433	*
1434	* @returns VBox status code.
1435	* @param pDevIns The IOMMU device instance.
1436	* @param idDevice The device identifier (bus, device, function).
1437	* @param uIova The I/O virtual address being accessed.
1438	* @param cbIova The size of the access.
1439	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1440	* @param pGCPhysSpa Where to store the translated system physical address.
1441	* @param pcbContiguous Where to store the number of contiguous bytes translated
1442	* and permission-checked.
1443	*
1444	* @thread Any.
1445	*/
1446	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1447	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1448
1449	/**
1450	* Translates in bulk physical page addresses for memory transactions through the
1451	* IOMMU.
1452	*
1453	* @returns VBox status code.
1454	* @param pDevIns The IOMMU device instance.
1455	* @param idDevice The device identifier (bus, device, function).
1456	* @param cIovas The number of I/O virtual addresses being accessed.
1457	* @param pauIovas The I/O virtual addresses being accessed.
1458	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1459	* @param paGCPhysSpa Where to store the translated system physical page
1460	* addresses.
1461	*
1462	* @thread Any.
1463	*/
1464	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1465	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1466
1467	/**
1468	* Performs an interrupt remap request through the IOMMU.
1469	*
1470	* @returns VBox status code.
1471	* @param pDevIns The IOMMU device instance.
1472	* @param idDevice The device identifier (bus, device, function).
1473	* @param pMsiIn The source MSI.
1474	* @param pMsiOut Where to store the remapped MSI.
1475	*
1476	* @thread Any.
1477	*/
1478	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1479
1480	/** Just a safety precaution. */
1481	uint32_t u32TheEnd;
1482	} PDMIOMMUREGR3;
1483	/** Pointer to a IOMMU registration structure. */
1484	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1485
1486	/** Current PDMIOMMUREG version number. */
1487	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1488
1489	/** IOMMU registration structure for the current context. */
1490	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1491	/** Pointer to an IOMMU registration structure for the current context. */
1492	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1493	/** IOMMU registration structure version for the current context. */
1494	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1495
1496
1497	/**
1498	* IOMMU helpers for ring-0.
1499	*/
1500	typedef struct PDMIOMMUHLPR0
1501	{
1502	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1503	uint32_t u32Version;
1504
1505	/**
1506	* Acquires the PDM lock.
1507	*
1508	* @returns VINF_SUCCESS on success.
1509	* @returns rc if we failed to acquire the lock.
1510	* @param pDevIns The PCI device instance.
1511	* @param rc What to return if we fail to acquire the lock.
1512	*
1513	* @sa PDMCritSectEnter
1514	*/
1515	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1516
1517	/**
1518	* Releases the PDM lock.
1519	*
1520	* @param pDevIns The PCI device instance.
1521	*/
1522	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1523
1524	/**
1525	* Check whether the calling thread owns the PDM lock.
1526	*
1527	* @returns @c true if the PDM lock is owned, @c false otherwise.
1528	* @param pDevIns The PCI device instance.
1529	*/
1530	DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1531
1532	/**
1533	* Send an MSI (when generated by the IOMMU device itself).
1534	*
1535	* @param pDevIns PCI device instance.
1536	* @param pMsi The MSI to send.
1537	* @param uTagSrc The IRQ tag and source (for tracing).
1538	*/
1539	DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1540
1541	/** Just a safety precaution. */
1542	uint32_t u32TheEnd;
1543	} PDMIOMMUHLPR0;
1544	/** Pointer to IOMMU helpers for ring-0. */
1545	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1546	/** Pointer to const IOMMU helpers for ring-0. */
1547	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1548
1549	/** Current PDMIOMMUHLPR0 version number. */
1550	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1551
1552
1553	/**
1554	* IOMMU helpers for raw-mode.
1555	*/
1556	typedef struct PDMIOMMUHLPRC
1557	{
1558	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1559	uint32_t u32Version;
1560
1561	/**
1562	* Acquires the PDM lock.
1563	*
1564	* @returns VINF_SUCCESS on success.
1565	* @returns rc if we failed to acquire the lock.
1566	* @param pDevIns The PCI device instance.
1567	* @param rc What to return if we fail to acquire the lock.
1568	*
1569	* @sa PDMCritSectEnter
1570	*/
1571	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1572
1573	/**
1574	* Releases the PDM lock.
1575	*
1576	* @param pDevIns The PCI device instance.
1577	*/
1578	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1579
1580	/**
1581	* Check whether the threads owns the PDM lock.
1582	*
1583	* @returns @c true if the PDM lock is owned, @c false otherwise.
1584	* @param pDevIns The PCI device instance.
1585	*/
1586	DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1587
1588	/**
1589	* Send an MSI (when generated by the IOMMU device itself).
1590	*
1591	* @param pDevIns PCI device instance.
1592	* @param pMsi The MSI to send.
1593	* @param uTagSrc The IRQ tag and source (for tracing).
1594	*/
1595	DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1596
1597	/** Just a safety precaution. */
1598	uint32_t u32TheEnd;
1599	} PDMIOMMUHLPRC;
1600	/** Pointer to IOMMU helpers for raw-mode. */
1601	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1602	/** Pointer to const IOMMU helpers for raw-mode. */
1603	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1604
1605	/** Current PDMIOMMUHLPRC version number. */
1606	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1607
1608
1609	/**
1610	* IOMMU helpers for ring-3.
1611	*/
1612	typedef struct PDMIOMMUHLPR3
1613	{
1614	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1615	uint32_t u32Version;
1616
1617	/**
1618	* Acquires the PDM lock.
1619	*
1620	* @returns VINF_SUCCESS on success.
1621	* @returns rc if we failed to acquire the lock.
1622	* @param pDevIns The PCI device instance.
1623	* @param rc What to return if we fail to acquire the lock.
1624	*
1625	* @sa PDMCritSectEnter
1626	*/
1627	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1628
1629	/**
1630	* Releases the PDM lock.
1631	*
1632	* @param pDevIns The PCI device instance.
1633	*/
1634	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1635
1636	/**
1637	* Check whether the threads owns the PDM lock.
1638	*
1639	* @returns @c true if the PDM lock is owned, @c false otherwise.
1640	* @param pDevIns The PCI device instance.
1641	*/
1642	DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1643
1644	/**
1645	* Send an MSI (when generated by the IOMMU device itself).
1646	*
1647	* @param pDevIns PCI device instance.
1648	* @param pMsi The MSI to send.
1649	* @param uTagSrc The IRQ tag and source (for tracing).
1650	*/
1651	DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1652
1653	/** Just a safety precaution. */
1654	uint32_t u32TheEnd;
1655	} PDMIOMMUHLPR3;
1656	/** Pointer to IOMMU helpers for raw-mode. */
1657	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1658	/** Pointer to const IOMMU helpers for raw-mode. */
1659	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1660
1661	/** Current PDMIOMMUHLPR3 version number. */
1662	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1663
1664
1665	/**
1666	* Programmable Interrupt Controller registration structure (all contexts).
1667	*/
1668	typedef struct PDMPICREG
1669	{
1670	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1671	uint32_t u32Version;
1672
1673	/**
1674	* Set the an IRQ.
1675	*
1676	* @param pDevIns Device instance of the PIC.
1677	* @param iIrq IRQ number to set.
1678	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1679	* @param uTagSrc The IRQ tag and source (for tracing).
1680	* @remarks Caller enters the PDM critical section.
1681	*/
1682	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1683
1684	/**
1685	* Get a pending interrupt.
1686	*
1687	* @returns Pending interrupt number.
1688	* @param pDevIns Device instance of the PIC.
1689	* @param puTagSrc Where to return the IRQ tag and source.
1690	* @remarks Caller enters the PDM critical section.
1691	*/
1692	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1693
1694	/** Just a safety precaution. */
1695	uint32_t u32TheEnd;
1696	} PDMPICREG;
1697	/** Pointer to a PIC registration structure. */
1698	typedef PDMPICREG *PPDMPICREG;
1699
1700	/** Current PDMPICREG version number. */
1701	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1702
1703	/**
1704	* PIC helpers, same in all contexts.
1705	*/
1706	typedef struct PDMPICHLP
1707	{
1708	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1709	uint32_t u32Version;
1710
1711	/**
1712	* Set the interrupt force action flag.
1713	*
1714	* @param pDevIns Device instance of the PIC.
1715	*/
1716	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1717
1718	/**
1719	* Clear the interrupt force action flag.
1720	*
1721	* @param pDevIns Device instance of the PIC.
1722	*/
1723	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1724
1725	/**
1726	* Acquires the PDM lock.
1727	*
1728	* @returns VINF_SUCCESS on success.
1729	* @returns rc if we failed to acquire the lock.
1730	* @param pDevIns The PIC device instance.
1731	* @param rc What to return if we fail to acquire the lock.
1732	*
1733	* @sa PDMCritSectEnter
1734	*/
1735	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1736
1737	/**
1738	* Releases the PDM lock.
1739	*
1740	* @param pDevIns The PIC device instance.
1741	*/
1742	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1743
1744	/** Just a safety precaution. */
1745	uint32_t u32TheEnd;
1746	} PDMPICHLP;
1747	/** Pointer to PIC helpers. */
1748	typedef PDMPICHLP *PPDMPICHLP;
1749	/** Pointer to const PIC helpers. */
1750	typedef const PDMPICHLP *PCPDMPICHLP;
1751
1752	/** Current PDMPICHLP version number. */
1753	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1754
1755
1756	/**
1757	* Firmware registration structure.
1758	*/
1759	typedef struct PDMFWREG
1760	{
1761	/** Struct version+magic number (PDM_FWREG_VERSION). */
1762	uint32_t u32Version;
1763
1764	/**
1765	* Checks whether this is a hard or soft reset.
1766	*
1767	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1768	* is 5, 9 or 0xA.
1769	*
1770	* @returns true if hard reset, false if soft.
1771	* @param pDevIns Device instance of the firmware.
1772	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1773	*/
1774	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1775
1776	/** Just a safety precaution. */
1777	uint32_t u32TheEnd;
1778	} PDMFWREG;
1779	/** Pointer to a FW registration structure. */
1780	typedef PDMFWREG *PPDMFWREG;
1781	/** Pointer to a const FW registration structure. */
1782	typedef PDMFWREG const *PCPDMFWREG;
1783
1784	/** Current PDMFWREG version number. */
1785	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1786
1787	/**
1788	* Firmware R3 helpers.
1789	*/
1790	typedef struct PDMFWHLPR3
1791	{
1792	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1793	uint32_t u32Version;
1794
1795	/** Just a safety precaution. */
1796	uint32_t u32TheEnd;
1797	} PDMFWHLPR3;
1798
1799	/** Pointer to FW R3 helpers. */
1800	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1801	/** Pointer to const FW R3 helpers. */
1802	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1803
1804	/** Current PDMFWHLPR3 version number. */
1805	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1806
1807
1808	/**
1809	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1810	*
1811	* Also used in saved-states, CFGM don't change existing values.
1812	*/
1813	typedef enum PDMAPICMODE
1814	{
1815	/** Invalid 0 entry. */
1816	PDMAPICMODE_INVALID = 0,
1817	/** No APIC. */
1818	PDMAPICMODE_NONE,
1819	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1820	PDMAPICMODE_APIC,
1821	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1822	PDMAPICMODE_X2APIC,
1823	/** The usual 32-bit paranoia. */
1824	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1825	} PDMAPICMODE;
1826
1827	/**
1828	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1829	*/
1830	typedef enum PDMAPICIRQ
1831	{
1832	/** Invalid 0 entry. */
1833	PDMAPICIRQ_INVALID = 0,
1834	/** Normal hardware interrupt. */
1835	PDMAPICIRQ_HARDWARE,
1836	/** NMI. */
1837	PDMAPICIRQ_NMI,
1838	/** SMI. */
1839	PDMAPICIRQ_SMI,
1840	/** ExtINT (HW interrupt via PIC). */
1841	PDMAPICIRQ_EXTINT,
1842	/** Interrupt arrived, needs to be updated to the IRR. */
1843	PDMAPICIRQ_UPDATE_PENDING,
1844	/** The usual 32-bit paranoia. */
1845	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1846	} PDMAPICIRQ;
1847
1848
1849	/**
1850	* I/O APIC registration structure (all contexts).
1851	*/
1852	typedef struct PDMIOAPICREG
1853	{
1854	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1855	uint32_t u32Version;
1856
1857	/**
1858	* Set an IRQ.
1859	*
1860	* @param pDevIns Device instance of the I/O APIC.
1861	* @param uBusDevFn The bus:device:function of the device initiating the
1862	* IRQ. Can be NIL_PCIBDF.
1863	* @param iIrq IRQ number to set.
1864	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1865	* @param uTagSrc The IRQ tag and source (for tracing).
1866	*
1867	* @remarks Caller enters the PDM critical section
1868	* Actually, as per 2018-07-21 this isn't true (bird).
1869	*/
1870	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1871
1872	/**
1873	* Send a MSI.
1874	*
1875	* @param pDevIns Device instance of the I/O APIC.
1876	* @param uBusDevFn The bus:device:function of the device initiating the
1877	* MSI. Cannot be NIL_PCIBDF.
1878	* @param pMsi The MSI to send.
1879	* @param uTagSrc The IRQ tag and source (for tracing).
1880	*
1881	* @remarks Caller enters the PDM critical section
1882	* Actually, as per 2018-07-21 this isn't true (bird).
1883	*/
1884	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1885
1886	/**
1887	* Set the EOI for an interrupt vector.
1888	*
1889	* @param pDevIns Device instance of the I/O APIC.
1890	* @param u8Vector The vector.
1891	*
1892	* @remarks Caller enters the PDM critical section
1893	* Actually, as per 2018-07-21 this isn't true (bird).
1894	*/
1895	DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1896
1897	/** Just a safety precaution. */
1898	uint32_t u32TheEnd;
1899	} PDMIOAPICREG;
1900	/** Pointer to an APIC registration structure. */
1901	typedef PDMIOAPICREG *PPDMIOAPICREG;
1902
1903	/** Current PDMAPICREG version number. */
1904	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1905
1906
1907	/**
1908	* IOAPIC helpers, same in all contexts.
1909	*/
1910	typedef struct PDMIOAPICHLP
1911	{
1912	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1913	uint32_t u32Version;
1914
1915	/**
1916	* Private interface between the IOAPIC and APIC.
1917	*
1918	* @returns status code.
1919	* @param pDevIns Device instance of the IOAPIC.
1920	* @param u8Dest See APIC implementation.
1921	* @param u8DestMode See APIC implementation.
1922	* @param u8DeliveryMode See APIC implementation.
1923	* @param uVector See APIC implementation.
1924	* @param u8Polarity See APIC implementation.
1925	* @param u8TriggerMode See APIC implementation.
1926	* @param uTagSrc The IRQ tag and source (for tracing).
1927	*
1928	* @sa APICBusDeliver()
1929	*/
1930	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1931	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1932
1933	/**
1934	* Acquires the PDM lock.
1935	*
1936	* @returns VINF_SUCCESS on success.
1937	* @returns rc if we failed to acquire the lock.
1938	* @param pDevIns The IOAPIC device instance.
1939	* @param rc What to return if we fail to acquire the lock.
1940	*
1941	* @sa PDMCritSectEnter
1942	*/
1943	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1944
1945	/**
1946	* Releases the PDM lock.
1947	*
1948	* @param pDevIns The IOAPIC device instance.
1949	*/
1950	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1951
1952	/**
1953	* Checks if the calling thread owns the PDM lock.
1954	*
1955	* @param pDevIns The IOAPIC device instance.
1956	*/
1957	DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1958
1959	/**
1960	* Private interface between the IOAPIC and IOMMU.
1961	*
1962	* @returns status code.
1963	* @param pDevIns Device instance of the IOAPIC.
1964	* @param idDevice The device identifier (bus, device, function).
1965	* @param pMsiIn The source MSI.
1966	* @param pMsiOut Where to store the remapped MSI (only updated when
1967	* VINF_SUCCESS is returned).
1968	*/
1969	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1970
1971	/** Just a safety precaution. */
1972	uint32_t u32TheEnd;
1973	} PDMIOAPICHLP;
1974	/** Pointer to IOAPIC helpers. */
1975	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1976	/** Pointer to const IOAPIC helpers. */
1977	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1978
1979	/** Current PDMIOAPICHLP version number. */
1980	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1981
1982
1983	/**
1984	* HPET registration structure.
1985	*/
1986	typedef struct PDMHPETREG
1987	{
1988	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1989	uint32_t u32Version;
1990	} PDMHPETREG;
1991	/** Pointer to an HPET registration structure. */
1992	typedef PDMHPETREG *PPDMHPETREG;
1993
1994	/** Current PDMHPETREG version number. */
1995	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1996
1997	/**
1998	* HPET RC helpers.
1999	*
2000	* @remarks Keep this around in case HPET will need PDM interaction in again RC
2001	* at some later point.
2002	*/
2003	typedef struct PDMHPETHLPRC
2004	{
2005	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
2006	uint32_t u32Version;
2007
2008	/** Just a safety precaution. */
2009	uint32_t u32TheEnd;
2010	} PDMHPETHLPRC;
2011
2012	/** Pointer to HPET RC helpers. */
2013	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
2014	/** Pointer to const HPET RC helpers. */
2015	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
2016
2017	/** Current PDMHPETHLPRC version number. */
2018	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
2019
2020
2021	/**
2022	* HPET R0 helpers.
2023	*
2024	* @remarks Keep this around in case HPET will need PDM interaction in again R0
2025	* at some later point.
2026	*/
2027	typedef struct PDMHPETHLPR0
2028	{
2029	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2030	uint32_t u32Version;
2031
2032	/** Just a safety precaution. */
2033	uint32_t u32TheEnd;
2034	} PDMHPETHLPR0;
2035
2036	/** Pointer to HPET R0 helpers. */
2037	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2038	/** Pointer to const HPET R0 helpers. */
2039	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2040
2041	/** Current PDMHPETHLPR0 version number. */
2042	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2043
2044	/**
2045	* HPET R3 helpers.
2046	*/
2047	typedef struct PDMHPETHLPR3
2048	{
2049	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2050	uint32_t u32Version;
2051
2052	/**
2053	* Set legacy mode on PIT and RTC.
2054	*
2055	* @returns VINF_SUCCESS on success.
2056	* @returns rc if we failed to set legacy mode.
2057	* @param pDevIns Device instance of the HPET.
2058	* @param fActivated Whether legacy mode is activated or deactivated.
2059	*/
2060	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2061
2062
2063	/**
2064	* Set IRQ, bypassing ISA bus override rules.
2065	*
2066	* @returns VINF_SUCCESS on success.
2067	* @returns rc if we failed to set legacy mode.
2068	* @param pDevIns Device instance of the HPET.
2069	* @param iIrq IRQ number to set.
2070	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2071	*/
2072	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2073
2074	/** Just a safety precaution. */
2075	uint32_t u32TheEnd;
2076	} PDMHPETHLPR3;
2077
2078	/** Pointer to HPET R3 helpers. */
2079	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2080	/** Pointer to const HPET R3 helpers. */
2081	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2082
2083	/** Current PDMHPETHLPR3 version number. */
2084	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2085
2086
2087	/**
2088	* Raw PCI device registration structure.
2089	*/
2090	typedef struct PDMPCIRAWREG
2091	{
2092	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2093	uint32_t u32Version;
2094	/** Just a safety precaution. */
2095	uint32_t u32TheEnd;
2096	} PDMPCIRAWREG;
2097	/** Pointer to a raw PCI registration structure. */
2098	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2099
2100	/** Current PDMPCIRAWREG version number. */
2101	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2102
2103	/**
2104	* Raw PCI device raw-mode context helpers.
2105	*/
2106	typedef struct PDMPCIRAWHLPRC
2107	{
2108	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2109	uint32_t u32Version;
2110	/** Just a safety precaution. */
2111	uint32_t u32TheEnd;
2112	} PDMPCIRAWHLPRC;
2113	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2114	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2115	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2116	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2117
2118	/** Current PDMPCIRAWHLPRC version number. */
2119	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2120
2121	/**
2122	* Raw PCI device ring-0 context helpers.
2123	*/
2124	typedef struct PDMPCIRAWHLPR0
2125	{
2126	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2127	uint32_t u32Version;
2128	/** Just a safety precaution. */
2129	uint32_t u32TheEnd;
2130	} PDMPCIRAWHLPR0;
2131	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2132	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2133	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2134	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2135
2136	/** Current PDMPCIRAWHLPR0 version number. */
2137	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2138
2139
2140	/**
2141	* Raw PCI device ring-3 context helpers.
2142	*/
2143	typedef struct PDMPCIRAWHLPR3
2144	{
2145	/** Undefined structure version and magic number. */
2146	uint32_t u32Version;
2147
2148	/**
2149	* Gets the address of the RC raw PCI device helpers.
2150	*
2151	* This should be called at both construction and relocation time to obtain
2152	* the correct address of the RC helpers.
2153	*
2154	* @returns RC pointer to the raw PCI device helpers.
2155	* @param pDevIns Device instance of the raw PCI device.
2156	*/
2157	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2158
2159	/**
2160	* Gets the address of the R0 raw PCI device helpers.
2161	*
2162	* This should be called at both construction and relocation time to obtain
2163	* the correct address of the R0 helpers.
2164	*
2165	* @returns R0 pointer to the raw PCI device helpers.
2166	* @param pDevIns Device instance of the raw PCI device.
2167	*/
2168	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2169
2170	/** Just a safety precaution. */
2171	uint32_t u32TheEnd;
2172	} PDMPCIRAWHLPR3;
2173	/** Pointer to raw PCI R3 helpers. */
2174	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2175	/** Pointer to const raw PCI R3 helpers. */
2176	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2177
2178	/** Current PDMPCIRAWHLPR3 version number. */
2179	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2180
2181
2182	#ifdef IN_RING3
2183
2184	/**
2185	* DMA Transfer Handler.
2186	*
2187	* @returns Number of bytes transferred.
2188	* @param pDevIns The device instance that registered the handler.
2189	* @param pvUser User pointer.
2190	* @param uChannel Channel number.
2191	* @param off DMA position.
2192	* @param cb Block size.
2193	* @remarks The device lock is take before the callback (in fact, the locks of
2194	* DMA devices and the DMA controller itself are taken).
2195	*/
2196	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2197	uint32_t off, uint32_t cb));
2198	/** Pointer to a FNDMATRANSFERHANDLER(). */
2199	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2200
2201	/**
2202	* DMA Controller registration structure.
2203	*/
2204	typedef struct PDMDMAREG
2205	{
2206	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2207	uint32_t u32Version;
2208
2209	/**
2210	* Execute pending transfers.
2211	*
2212	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2213	* @param pDevIns Device instance of the DMAC.
2214	* @remarks No locks held, called on EMT(0) as a form of serialization.
2215	*/
2216	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2217
2218	/**
2219	* Register transfer function for DMA channel.
2220	*
2221	* @param pDevIns Device instance of the DMAC.
2222	* @param uChannel Channel number.
2223	* @param pDevInsHandler The device instance of the device making the
2224	* regstration (will be passed to the callback).
2225	* @param pfnTransferHandler Device specific transfer function.
2226	* @param pvUser User pointer to be passed to the callback.
2227	* @remarks No locks held, called on an EMT.
2228	*/
2229	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2230	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2231
2232	/**
2233	* Read memory
2234	*
2235	* @returns Number of bytes read.
2236	* @param pDevIns Device instance of the DMAC.
2237	* @param uChannel Channel number.
2238	* @param pvBuffer Pointer to target buffer.
2239	* @param off DMA position.
2240	* @param cbBlock Block size.
2241	* @remarks No locks held, called on an EMT.
2242	*/
2243	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2244
2245	/**
2246	* Write memory
2247	*
2248	* @returns Number of bytes written.
2249	* @param pDevIns Device instance of the DMAC.
2250	* @param uChannel Channel number.
2251	* @param pvBuffer Memory to write.
2252	* @param off DMA position.
2253	* @param cbBlock Block size.
2254	* @remarks No locks held, called on an EMT.
2255	*/
2256	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2257
2258	/**
2259	* Set the DREQ line.
2260	*
2261	* @param pDevIns Device instance of the DMAC.
2262	* @param uChannel Channel number.
2263	* @param uLevel Level of the line.
2264	* @remarks No locks held, called on an EMT.
2265	*/
2266	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2267
2268	/**
2269	* Get channel mode
2270	*
2271	* @returns Channel mode.
2272	* @param pDevIns Device instance of the DMAC.
2273	* @param uChannel Channel number.
2274	* @remarks No locks held, called on an EMT.
2275	*/
2276	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2277
2278	} PDMDMACREG;
2279	/** Pointer to a DMAC registration structure. */
2280	typedef PDMDMACREG *PPDMDMACREG;
2281
2282	/** Current PDMDMACREG version number. */
2283	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2284
2285
2286	/**
2287	* DMA Controller device helpers.
2288	*/
2289	typedef struct PDMDMACHLP
2290	{
2291	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2292	uint32_t u32Version;
2293
2294	/* to-be-defined */
2295
2296	} PDMDMACHLP;
2297	/** Pointer to DMAC helpers. */
2298	typedef PDMDMACHLP *PPDMDMACHLP;
2299	/** Pointer to const DMAC helpers. */
2300	typedef const PDMDMACHLP *PCPDMDMACHLP;
2301
2302	/** Current PDMDMACHLP version number. */
2303	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2304
2305	#endif /* IN_RING3 */
2306
2307
2308
2309	/**
2310	* RTC registration structure.
2311	*/
2312	typedef struct PDMRTCREG
2313	{
2314	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2315	uint32_t u32Version;
2316	uint32_t u32Alignment; /*< structure size alignment. /
2317
2318	/**
2319	* Write to a CMOS register and update the checksum if necessary.
2320	*
2321	* @returns VBox status code.
2322	* @param pDevIns Device instance of the RTC.
2323	* @param iReg The CMOS register index.
2324	* @param u8Value The CMOS register value.
2325	* @remarks Caller enters the device critical section.
2326	*/
2327	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2328
2329	/**
2330	* Read a CMOS register.
2331	*
2332	* @returns VBox status code.
2333	* @param pDevIns Device instance of the RTC.
2334	* @param iReg The CMOS register index.
2335	* @param pu8Value Where to store the CMOS register value.
2336	* @remarks Caller enters the device critical section.
2337	*/
2338	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2339
2340	} PDMRTCREG;
2341	/** Pointer to a RTC registration structure. */
2342	typedef PDMRTCREG *PPDMRTCREG;
2343	/** Pointer to a const RTC registration structure. */
2344	typedef const PDMRTCREG *PCPDMRTCREG;
2345
2346	/** Current PDMRTCREG version number. */
2347	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2348
2349
2350	/**
2351	* RTC device helpers.
2352	*/
2353	typedef struct PDMRTCHLP
2354	{
2355	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2356	uint32_t u32Version;
2357
2358	/* to-be-defined */
2359
2360	} PDMRTCHLP;
2361	/** Pointer to RTC helpers. */
2362	typedef PDMRTCHLP *PPDMRTCHLP;
2363	/** Pointer to const RTC helpers. */
2364	typedef const PDMRTCHLP *PCPDMRTCHLP;
2365
2366	/** Current PDMRTCHLP version number. */
2367	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2368
2369
2370
2371	/** @name Flags for PCI I/O region registration
2372	* @{ */
2373	/** No handle is passed. */
2374	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2375	/** An I/O port handle is passed. */
2376	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2377	/** An MMIO range handle is passed. */
2378	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2379	/** An MMIO2 handle is passed. */
2380	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2381	/** Handle type mask. */
2382	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2383	/** New-style (mostly wrt callbacks). */
2384	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2385	/** Mask of valid flags. */
2386	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2387	/** @} */
2388
2389
2390	/** @name Flags for the guest physical read/write helpers
2391	* @{ */
2392	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2393	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2394	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2395	* by the device in any way. */
2396	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2397	/** The data is metadata and being processed by the device in some way. */
2398	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2399	/** @} */
2400
2401
2402	#ifdef IN_RING3
2403
2404	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2405	* @{ */
2406	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2407	* This is handy when registering multiple PCI device functions and the device
2408	* number is left up to the PCI bus. In order to facilitate one PDM device
2409	* instance for each PCI function, this searches earlier PDM device
2410	* instances as well. */
2411	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2412	/** Use the first unused device number (all functions must be unused). */
2413	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2414	/** Use the first unused device function. */
2415	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2416
2417	/** The device and function numbers are not mandatory, just suggestions. */
2418	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2419	/** Registering a PCI bridge device. */
2420	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2421	/** Valid flag mask. */
2422	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2423	/** @} */
2424
2425	/** Current PDMDEVHLPR3 version number. */
2426	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 58, 0)
2427
2428	/**
2429	* PDM Device API.
2430	*/
2431	typedef struct PDMDEVHLPR3
2432	{
2433	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2434	uint32_t u32Version;
2435
2436	/** @name I/O ports
2437	* @{ */
2438	/**
2439	* Creates a range of I/O ports for a device.
2440	*
2441	* The I/O port range must be mapped in a separately call. Any ring-0 and
2442	* raw-mode context callback handlers needs to be set up in the respective
2443	* contexts.
2444	*
2445	* @returns VBox status.
2446	* @param pDevIns The device instance to register the ports with.
2447	* @param cPorts Number of ports to register.
2448	* @param fFlags IOM_IOPORT_F_XXX.
2449	* @param pPciDev The PCI device the range is associated with, if
2450	* applicable.
2451	* @param iPciRegion The PCI device region in the high 16-bit word and
2452	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2453	* @param pfnOut Pointer to function which is gonna handle OUT
2454	* operations. Optional.
2455	* @param pfnIn Pointer to function which is gonna handle IN operations.
2456	* Optional.
2457	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2458	* operations. Optional.
2459	* @param pfnInStr Pointer to function which is gonna handle string IN
2460	* operations. Optional.
2461	* @param pvUser User argument to pass to the callbacks.
2462	* @param pszDesc Pointer to description string. This must not be freed.
2463	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2464	* coverage is allowed. This must not be freed.
2465	* @param phIoPorts Where to return the I/O port range handle.
2466	*
2467	* @remarks Caller enters the device critical section prior to invoking the
2468	* registered callback methods.
2469	*
2470	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2471	* PDMDevHlpIoPortUnmap.
2472	*/
2473	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2474	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2475	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2476	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2477
2478	/**
2479	* Maps an I/O port range.
2480	*
2481	* @returns VBox status.
2482	* @param pDevIns The device instance to register the ports with.
2483	* @param hIoPorts The I/O port range handle.
2484	* @param Port Where to map the range.
2485	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2486	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2487	*/
2488	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2489
2490	/**
2491	* Unmaps an I/O port range.
2492	*
2493	* @returns VBox status.
2494	* @param pDevIns The device instance to register the ports with.
2495	* @param hIoPorts The I/O port range handle.
2496	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2497	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2498	*/
2499	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2500
2501	/**
2502	* Gets the mapping address of the I/O port range @a hIoPorts.
2503	*
2504	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2505	* parameters).
2506	* @param pDevIns The device instance to register the ports with.
2507	* @param hIoPorts The I/O port range handle.
2508	*/
2509	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2510
2511	/**
2512	* Writes to an I/O port register.
2513	*
2514	* @returns Strict VBox status code. Informational status codes other than the one documented
2515	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2516	* @retval VINF_SUCCESS Success.
2517	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2518	* status code must be passed on to EM.
2519	*
2520	* @param pDevIns The device instance to register the ports with.
2521	* @param Port The port to write to.
2522	* @param u32Value The value to write.
2523	* @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
2524	*
2525	* @thread EMT
2526	* @todo r=aeichner This is only used by DevPCI.cpp to write the ELCR of the PIC. This shouldn't be done that way
2527	* and removed again as soon as possible (no time right now)...
2528	*/
2529	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnIoPortWrite,(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t u32Value, size_t cbValue));
2530	/** @} */
2531
2532	/** @name MMIO
2533	* @{ */
2534	/**
2535	* Creates a memory mapped I/O (MMIO) region for a device.
2536	*
2537	* The MMIO region must be mapped in a separately call. Any ring-0 and
2538	* raw-mode context callback handlers needs to be set up in the respective
2539	* contexts.
2540	*
2541	* @returns VBox status.
2542	* @param pDevIns The device instance to register the ports with.
2543	* @param cbRegion The size of the region in bytes.
2544	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2545	* @param pPciDev The PCI device the range is associated with, if
2546	* applicable.
2547	* @param iPciRegion The PCI device region in the high 16-bit word and
2548	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2549	* @param pfnWrite Pointer to function which is gonna handle Write
2550	* operations.
2551	* @param pfnRead Pointer to function which is gonna handle Read
2552	* operations.
2553	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2554	* operations. (optional)
2555	* @param pvUser User argument to pass to the callbacks.
2556	* @param pszDesc Pointer to description string. This must not be freed.
2557	* @param phRegion Where to return the MMIO region handle.
2558	*
2559	* @remarks Caller enters the device critical section prior to invoking the
2560	* registered callback methods.
2561	*
2562	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2563	*/
2564	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2565	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2566	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2567	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2568
2569	/**
2570	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2571	*
2572	* @returns VBox status.
2573	* @param pDevIns The device instance the region is associated with.
2574	* @param hRegion The MMIO region handle.
2575	* @param GCPhys Where to map the region.
2576	* @note An MMIO range may overlap with base memory if a lot of RAM is
2577	* configured for the VM, in which case we'll drop the base memory
2578	* pages. Presently we will make no attempt to preserve anything that
2579	* happens to be present in the base memory that is replaced, this is
2580	* technically incorrect but it's just not worth the effort to do
2581	* right, at least not at this point.
2582	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2583	* PDMDevHlpMmioSetUpContext
2584	*/
2585	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2586
2587	/**
2588	* Unmaps a memory mapped I/O (MMIO) region.
2589	*
2590	* @returns VBox status.
2591	* @param pDevIns The device instance the region is associated with.
2592	* @param hRegion The MMIO region handle.
2593	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2594	* PDMDevHlpMmioSetUpContext
2595	*/
2596	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2597
2598	/**
2599	* Reduces the length of a MMIO range.
2600	*
2601	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2602	* only work during saved state restore. It will not call the PCI bus code, as
2603	* that is expected to restore the saved resource configuration.
2604	*
2605	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2606	* called it will only map @a cbRegion bytes and not the value set during
2607	* registration.
2608	*
2609	* @return VBox status code.
2610	* @param pDevIns The device owning the range.
2611	* @param hRegion The MMIO region handle.
2612	* @param cbRegion The new size, must be smaller.
2613	*/
2614	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2615
2616	/**
2617	* Gets the mapping address of the MMIO region @a hRegion.
2618	*
2619	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2620	* @param pDevIns The device instance to register the ports with.
2621	* @param hRegion The MMIO region handle.
2622	*/
2623	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2624	/** @} */
2625
2626	/** @name MMIO2
2627	* @{ */
2628	/**
2629	* Creates a MMIO2 region.
2630	*
2631	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2632	* associated with a device. It is also non-shared memory with a permanent
2633	* ring-3 mapping and page backing (presently).
2634	*
2635	* @returns VBox status.
2636	* @param pDevIns The device instance.
2637	* @param pPciDev The PCI device the region is associated with, or
2638	* NULL if no PCI device association.
2639	* @param iPciRegion The region number. Use the PCI region number as
2640	* this must be known to the PCI bus device too. If
2641	* it's not associated with the PCI device, then
2642	* any number up to UINT8_MAX is fine.
2643	* @param cbRegion The size (in bytes) of the region.
2644	* @param fFlags Reserved for future use, must be zero.
2645	* @param pszDesc Pointer to description string. This must not be
2646	* freed.
2647	* @param ppvMapping Where to store the address of the ring-3 mapping
2648	* of the memory.
2649	* @param phRegion Where to return the MMIO2 region handle.
2650	*
2651	* @thread EMT(0)
2652	*/
2653	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2654	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2655
2656	/**
2657	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2658	*
2659	* Any physical access handlers registered for the region must be deregistered
2660	* before calling this function.
2661	*
2662	* @returns VBox status code.
2663	* @param pDevIns The device instance.
2664	* @param hRegion The MMIO2 region handle.
2665	* @thread EMT.
2666	*/
2667	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2668
2669	/**
2670	* Maps a MMIO2 region (into the guest physical address space).
2671	*
2672	* @returns VBox status.
2673	* @param pDevIns The device instance the region is associated with.
2674	* @param hRegion The MMIO2 region handle.
2675	* @param GCPhys Where to map the region.
2676	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2677	* configured for the VM, in which case we'll drop the base memory
2678	* pages. Presently we will make no attempt to preserve anything that
2679	* happens to be present in the base memory that is replaced, this is
2680	* technically incorrect but it's just not worth the effort to do
2681	* right, at least not at this point.
2682	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2683	*/
2684	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2685
2686	/**
2687	* Unmaps a MMIO2 region.
2688	*
2689	* @returns VBox status.
2690	* @param pDevIns The device instance the region is associated with.
2691	* @param hRegion The MMIO2 region handle.
2692	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2693	*/
2694	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2695
2696	/**
2697	* Reduces the length of a MMIO range.
2698	*
2699	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2700	* only work during saved state restore. It will not call the PCI bus code, as
2701	* that is expected to restore the saved resource configuration.
2702	*
2703	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2704	* called it will only map @a cbRegion bytes and not the value set during
2705	* registration.
2706	*
2707	* @return VBox status code.
2708	* @param pDevIns The device owning the range.
2709	* @param hRegion The MMIO2 region handle.
2710	* @param cbRegion The new size, must be smaller.
2711	*/
2712	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2713
2714	/**
2715	* Gets the mapping address of the MMIO region @a hRegion.
2716	*
2717	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2718	* @param pDevIns The device instance to register the ports with.
2719	* @param hRegion The MMIO2 region handle.
2720	*/
2721	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2722
2723	/**
2724	* Changes the number of an MMIO2 or pre-registered MMIO region.
2725	*
2726	* This should only be used to deal with saved state problems, so there is no
2727	* convenience inline wrapper for this method.
2728	*
2729	* @returns VBox status code.
2730	* @param pDevIns The device instance.
2731	* @param hRegion The MMIO2 region handle.
2732	* @param iNewRegion The new region index.
2733	*
2734	* @sa @bugref{9359}
2735	*/
2736	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2737
2738	/**
2739	* Mapping an MMIO2 page in place of an MMIO page for direct access.
2740	*
2741	* This is a special optimization used by the VGA device. Call
2742	* PDMDevHlpMmioResetRegion() to undo the mapping.
2743	*
2744	* @returns VBox status code. This API may return VINF_SUCCESS even if no
2745	* remapping is made.
2746	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
2747	*
2748	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
2749	* associated with.
2750	* @param hRegion The handle to the MMIO region.
2751	* @param offRegion The offset into @a hRegion of the page to be
2752	* remapped.
2753	* @param hMmio2 The MMIO2 handle.
2754	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
2755	* mapping.
2756	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
2757	* for the time being.
2758	*/
2759	DECLR3CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
2760	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
2761
2762	/**
2763	* Reset a previously modified MMIO region; restore the access flags.
2764	*
2765	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
2766	* intended for some ancient VGA hack. However, it would be great to extend it
2767	* beyond VT-x and/or nested-paging.
2768	*
2769	* @returns VBox status code.
2770	*
2771	* @param pDevIns The device instance @a hRegion is associated with.
2772	* @param hRegion The handle to the MMIO region.
2773	*/
2774	DECLR3CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2775	/** @} */
2776
2777	/**
2778	* Register a ROM (BIOS) region.
2779	*
2780	* It goes without saying that this is read-only memory. The memory region must be
2781	* in unassigned memory. I.e. from the top of the address space or on the PC in
2782	* the 0xa0000-0xfffff range.
2783	*
2784	* @returns VBox status.
2785	* @param pDevIns The device instance owning the ROM region.
2786	* @param GCPhysStart First physical address in the range.
2787	* Must be page aligned!
2788	* @param cbRange The size of the range (in bytes).
2789	* Must be page aligned!
2790	* @param pvBinary Pointer to the binary data backing the ROM image.
2791	* @param cbBinary The size of the binary pointer. This must
2792	* be equal or smaller than @a cbRange.
2793	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2794	* @param pszDesc Pointer to description string. This must not be freed.
2795	*
2796	* @remark There is no way to remove the rom, automatically on device cleanup or
2797	* manually from the device yet. At present I doubt we need such features...
2798	*/
2799	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2800	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2801
2802	/**
2803	* Changes the protection of shadowed ROM mapping.
2804	*
2805	* This is intented for use by the system BIOS, chipset or device in question to
2806	* change the protection of shadowed ROM code after init and on reset.
2807	*
2808	* @param pDevIns The device instance.
2809	* @param GCPhysStart Where the mapping starts.
2810	* @param cbRange The size of the mapping.
2811	* @param enmProt The new protection type.
2812	*/
2813	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2814
2815	/**
2816	* Register a save state data unit.
2817	*
2818	* @returns VBox status.
2819	* @param pDevIns The device instance.
2820	* @param uVersion Data layout version number.
2821	* @param cbGuess The approximate amount of data in the unit.
2822	* Only for progress indicators.
2823	* @param pszBefore Name of data unit which we should be put in
2824	* front of. Optional (NULL).
2825	*
2826	* @param pfnLivePrep Prepare live save callback, optional.
2827	* @param pfnLiveExec Execute live save callback, optional.
2828	* @param pfnLiveVote Vote live save callback, optional.
2829	*
2830	* @param pfnSavePrep Prepare save callback, optional.
2831	* @param pfnSaveExec Execute save callback, optional.
2832	* @param pfnSaveDone Done save callback, optional.
2833	*
2834	* @param pfnLoadPrep Prepare load callback, optional.
2835	* @param pfnLoadExec Execute load callback, optional.
2836	* @param pfnLoadDone Done load callback, optional.
2837	* @remarks Caller enters the device critical section prior to invoking the
2838	* registered callback methods.
2839	*/
2840	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2841	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2842	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2843	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2844
2845	/** @name Exported SSM Functions
2846	* @{ */
2847	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2848	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2849	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2850	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2851	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2852	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2853	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2854	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2855	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2856	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2857	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2858	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2859	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2860	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2861	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2862	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2863	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2864	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2865	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2866	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2867	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2868	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2869	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2870	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2871	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2872	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2873	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2874	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2875	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2876	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2877	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2878	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2879	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2880	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2881	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2882	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2883	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2884	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2885	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2886	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2887	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2888	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2889	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2890	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2891	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2892	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2893	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2894	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2895	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2896	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2897	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2898	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2899	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2900	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2901	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2902	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2903	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2904	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2905	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2906	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2907	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2908	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2909	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2910	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2911	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2912	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2913	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2914	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2915	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2916	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2917	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2918	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2919	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2920	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2921	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2922	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2923	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2924	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2925	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2926	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2927	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2928	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2929	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2930	/** @} */
2931
2932	/**
2933	* Creates a timer w/ a cross context handle.
2934	*
2935	* @returns VBox status.
2936	* @param pDevIns The device instance.
2937	* @param enmClock The clock to use on this timer.
2938	* @param pfnCallback Callback function.
2939	* @param pvUser User argument for the callback.
2940	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2941	* @param pszDesc Pointer to description string which must stay around
2942	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2943	* @param phTimer Where to store the timer handle on success.
2944	* @remarks Caller enters the device critical section prior to invoking the
2945	* callback.
2946	*/
2947	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2948	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
2949
2950	/** @name Timer handle method wrappers
2951	* @{ */
2952	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2953	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2954	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2955	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2956	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2957	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2958	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2959	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2960	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2961	/** Takes the clock lock then enters the specified critical section. */
2962	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2963	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2964	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2965	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2966	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2967	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2968	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2969	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2970	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2971	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2972	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2973	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2974	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2975	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2976	/** @sa TMR3TimerSkip */
2977	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2978	/** @} */
2979
2980	/**
2981	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2982	*
2983	* @returns pTime.
2984	* @param pDevIns The device instance.
2985	* @param pTime Where to store the time.
2986	*/
2987	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2988
2989	/** @name Exported CFGM Functions.
2990	* @{ */
2991	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2992	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2993	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
2994	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2995	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2996	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
2997	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
2998	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
2999	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3000	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3001	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
3002	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
3003	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
3004	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
3005	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
3006	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
3007	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
3008	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
3009	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
3010	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
3011	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
3012	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
3013	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
3014	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
3015	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
3016	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
3017	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
3018	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
3019	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
3020	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
3021	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
3022	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
3023	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
3024	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
3025	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
3026	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
3027	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
3028	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
3029	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
3030	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
3031	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
3032	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
3033	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
3034	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
3035	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
3036	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
3037	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
3038	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
3039	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
3040	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
3041	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
3042	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
3043	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
3044	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
3045	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
3046	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
3047	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
3048	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
3049	const char pszValidValues, const char pszValidNodes,
3050	const char *pszWho, uint32_t uInstance));
3051	/** @} */
3052
3053	/**
3054	* Read physical memory.
3055	*
3056	* @returns VINF_SUCCESS (for now).
3057	* @param pDevIns The device instance.
3058	* @param GCPhys Physical address start reading from.
3059	* @param pvBuf Where to put the read bits.
3060	* @param cbRead How many bytes to read.
3061	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3062	* @thread Any thread, but the call may involve the emulation thread.
3063	*/
3064	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3065
3066	/**
3067	* Write to physical memory.
3068	*
3069	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3070	* @param pDevIns The device instance.
3071	* @param GCPhys Physical address to write to.
3072	* @param pvBuf What to write.
3073	* @param cbWrite How many bytes to write.
3074	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3075	* @thread Any thread, but the call may involve the emulation thread.
3076	*/
3077	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3078
3079	/**
3080	* Requests the mapping of a guest page into ring-3.
3081	*
3082	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3083	* release it.
3084	*
3085	* This API will assume your intention is to write to the page, and will
3086	* therefore replace shared and zero pages. If you do not intend to modify the
3087	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3088	*
3089	* @returns VBox status code.
3090	* @retval VINF_SUCCESS on success.
3091	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3092	* backing or if the page has any active access handlers. The caller
3093	* must fall back on using PGMR3PhysWriteExternal.
3094	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3095	*
3096	* @param pDevIns The device instance.
3097	* @param GCPhys The guest physical address of the page that
3098	* should be mapped.
3099	* @param fFlags Flags reserved for future use, MBZ.
3100	* @param ppv Where to store the address corresponding to
3101	* GCPhys.
3102	* @param pLock Where to store the lock information that
3103	* pfnPhysReleasePageMappingLock needs.
3104	*
3105	* @remark Avoid calling this API from within critical sections (other than the
3106	* PGM one) because of the deadlock risk when we have to delegating the
3107	* task to an EMT.
3108	* @thread Any.
3109	*/
3110	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3111	PPGMPAGEMAPLOCK pLock));
3112
3113	/**
3114	* Requests the mapping of a guest page into ring-3, external threads.
3115	*
3116	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3117	* release it.
3118	*
3119	* @returns VBox status code.
3120	* @retval VINF_SUCCESS on success.
3121	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3122	* backing or if the page as an active ALL access handler. The caller
3123	* must fall back on using PGMPhysRead.
3124	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3125	*
3126	* @param pDevIns The device instance.
3127	* @param GCPhys The guest physical address of the page that
3128	* should be mapped.
3129	* @param fFlags Flags reserved for future use, MBZ.
3130	* @param ppv Where to store the address corresponding to
3131	* GCPhys.
3132	* @param pLock Where to store the lock information that
3133	* pfnPhysReleasePageMappingLock needs.
3134	*
3135	* @remark Avoid calling this API from within critical sections.
3136	* @thread Any.
3137	*/
3138	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3139	void const **ppv, PPGMPAGEMAPLOCK pLock));
3140
3141	/**
3142	* Release the mapping of a guest page.
3143	*
3144	* This is the counter part of pfnPhysGCPhys2CCPtr and
3145	* pfnPhysGCPhys2CCPtrReadOnly.
3146	*
3147	* @param pDevIns The device instance.
3148	* @param pLock The lock structure initialized by the mapping
3149	* function.
3150	*/
3151	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3152
3153	/**
3154	* Read guest physical memory by virtual address.
3155	*
3156	* @param pDevIns The device instance.
3157	* @param pvDst Where to put the read bits.
3158	* @param GCVirtSrc Guest virtual address to start reading from.
3159	* @param cb How many bytes to read.
3160	* @thread The emulation thread.
3161	*/
3162	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3163
3164	/**
3165	* Write to guest physical memory by virtual address.
3166	*
3167	* @param pDevIns The device instance.
3168	* @param GCVirtDst Guest virtual address to write to.
3169	* @param pvSrc What to write.
3170	* @param cb How many bytes to write.
3171	* @thread The emulation thread.
3172	*/
3173	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3174
3175	/**
3176	* Convert a guest virtual address to a guest physical address.
3177	*
3178	* @returns VBox status code.
3179	* @param pDevIns The device instance.
3180	* @param GCPtr Guest virtual address.
3181	* @param pGCPhys Where to store the GC physical address
3182	* corresponding to GCPtr.
3183	* @thread The emulation thread.
3184	* @remark Careful with page boundaries.
3185	*/
3186	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3187
3188	/**
3189	* Checks if a GC physical address is a normal page,
3190	* i.e. not ROM, MMIO or reserved.
3191	*
3192	* @returns true if normal.
3193	* @returns false if invalid, ROM, MMIO or reserved page.
3194	* @param pDevIns The device instance.
3195	* @param GCPhys The physical address to check.
3196	*/
3197	DECLR3CALLBACKMEMBER(bool, pfnPhysIsGCPhysNormal,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
3198
3199	/**
3200	* Inflate or deflate a memory balloon
3201	*
3202	* @returns VBox status code.
3203	* @param pDevIns The device instance.
3204	* @param fInflate Inflate or deflate memory balloon
3205	* @param cPages Number of pages to free
3206	* @param paPhysPage Array of guest physical addresses
3207	*/
3208	DECLR3CALLBACKMEMBER(int, pfnPhysChangeMemBalloon,(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage));
3209
3210	/**
3211	* Allocate memory which is associated with current VM instance
3212	* and automatically freed on it's destruction.
3213	*
3214	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3215	* @param pDevIns The device instance.
3216	* @param cb Number of bytes to allocate.
3217	*/
3218	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3219
3220	/**
3221	* Allocate memory which is associated with current VM instance
3222	* and automatically freed on it's destruction. The memory is ZEROed.
3223	*
3224	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3225	* @param pDevIns The device instance.
3226	* @param cb Number of bytes to allocate.
3227	*/
3228	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3229
3230	/**
3231	* Allocating string printf.
3232	*
3233	* @returns Pointer to the string.
3234	* @param pDevIns The device instance.
3235	* @param enmTag The statistics tag.
3236	* @param pszFormat The format string.
3237	* @param va Format arguments.
3238	*/
3239	DECLR3CALLBACKMEMBER(char , pfnMMHeapAPrintfV,(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, va_list va));
3240
3241	/**
3242	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3243	*
3244	* @param pDevIns The device instance.
3245	* @param pv Pointer to the memory to free.
3246	*/
3247	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3248
3249	/**
3250	* Returns the physical RAM size of the VM.
3251	*
3252	* @returns RAM size in bytes.
3253	* @param pDevIns The device instance.
3254	*/
3255	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSize,(PPDMDEVINS pDevIns));
3256
3257	/**
3258	* Returns the physical RAM size of the VM below the 4GB boundary.
3259	*
3260	* @returns RAM size in bytes.
3261	* @param pDevIns The device instance.
3262	*/
3263	DECLR3CALLBACKMEMBER(uint32_t, pfnMMPhysGetRamSizeBelow4GB,(PPDMDEVINS pDevIns));
3264
3265	/**
3266	* Returns the physical RAM size of the VM above the 4GB boundary.
3267	*
3268	* @returns RAM size in bytes.
3269	* @param pDevIns The device instance.
3270	*/
3271	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSizeAbove4GB,(PPDMDEVINS pDevIns));
3272
3273	/**
3274	* Gets the VM state.
3275	*
3276	* @returns VM state.
3277	* @param pDevIns The device instance.
3278	* @thread Any thread (just keep in mind that it's volatile info).
3279	*/
3280	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3281
3282	/**
3283	* Checks if the VM was teleported and hasn't been fully resumed yet.
3284	*
3285	* @returns true / false.
3286	* @param pDevIns The device instance.
3287	* @thread Any thread.
3288	*/
3289	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3290
3291	/**
3292	* Set the VM error message
3293	*
3294	* @returns rc.
3295	* @param pDevIns The device instance.
3296	* @param rc VBox status code.
3297	* @param SRC_POS Use RT_SRC_POS.
3298	* @param pszFormat Error message format string.
3299	* @param va Error message arguments.
3300	*/
3301	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3302	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3303
3304	/**
3305	* Set the VM runtime error message
3306	*
3307	* @returns VBox status code.
3308	* @param pDevIns The device instance.
3309	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3310	* @param pszErrorId Error ID string.
3311	* @param pszFormat Error message format string.
3312	* @param va Error message arguments.
3313	*/
3314	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3315	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3316
3317	/**
3318	* Special interface for implementing a HLT-like port on a device.
3319	*
3320	* This can be called directly from device code, provide the device is trusted
3321	* to access the VMM directly. Since we may not have an accurate register set
3322	* and the caller certainly shouldn't (device code does not access CPU
3323	* registers), this function will return when interrupts are pending regardless
3324	* of the actual EFLAGS.IF state.
3325	*
3326	* @returns VBox error status (never informational statuses).
3327	* @param pDevIns The device instance.
3328	* @param idCpu The id of the calling EMT.
3329	*/
3330	DECLR3CALLBACKMEMBER(int, pfnVMWaitForDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3331
3332	/**
3333	* Wakes up a CPU that has called PDMDEVHLPR3::pfnVMWaitForDeviceReady.
3334	*
3335	* @returns VBox error status (never informational statuses).
3336	* @param pDevIns The device instance.
3337	* @param idCpu The id of the calling EMT.
3338	*/
3339	DECLR3CALLBACKMEMBER(int, pfnVMNotifyCpuDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3340
3341	/**
3342	* Convenience wrapper for VMR3ReqCallU.
3343	*
3344	* This assumes (1) you're calling a function that returns an VBox status code
3345	* and that you do not wish to wait for it to complete.
3346	*
3347	* @returns VBox status code returned by VMR3ReqCallVU.
3348	*
3349	* @param pDevIns The device instance.
3350	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3351	* one of the following special values:
3352	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3353	* @param pfnFunction Pointer to the function to call.
3354	* @param cArgs Number of arguments following in the ellipsis.
3355	* @param Args Argument vector.
3356	*
3357	* @remarks See remarks on VMR3ReqCallVU.
3358	*/
3359	DECLR3CALLBACKMEMBER(int, pfnVMReqCallNoWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3360
3361	/**
3362	* Convenience wrapper for VMR3ReqCallU.
3363	*
3364	* This assumes (1) you're calling a function that returns void, (2) that you
3365	* wish to wait for ever for it to return, and (3) that it's priority request
3366	* that can be safely be handled during async suspend and power off.
3367	*
3368	* @returns VBox status code of VMR3ReqCallVU.
3369	*
3370	* @param pDevIns The device instance.
3371	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3372	* one of the following special values:
3373	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3374	* @param pfnFunction Pointer to the function to call.
3375	* @param cArgs Number of arguments following in the ellipsis.
3376	* @param Args Argument vector.
3377	*
3378	* @remarks See remarks on VMR3ReqCallVU.
3379	*/
3380	DECLR3CALLBACKMEMBER(int, pfnVMReqPriorityCallWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3381
3382	/**
3383	* Stops the VM and enters the debugger to look at the guest state.
3384	*
3385	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3386	* invoking this function directly.
3387	*
3388	* @returns VBox status code which must be passed up to the VMM.
3389	* @param pDevIns The device instance.
3390	* @param pszFile Filename of the assertion location.
3391	* @param iLine The linenumber of the assertion location.
3392	* @param pszFunction Function of the assertion location.
3393	* @param pszFormat Message. (optional)
3394	* @param args Message parameters.
3395	*/
3396	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3397	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3398
3399	/**
3400	* Register a info handler with DBGF.
3401	*
3402	* @returns VBox status code.
3403	* @param pDevIns The device instance.
3404	* @param pszName The identifier of the info.
3405	* @param pszDesc The description of the info and any arguments
3406	* the handler may take.
3407	* @param pfnHandler The handler function to be called to display the
3408	* info.
3409	*/
3410	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3411
3412	/**
3413	* Register a info handler with DBGF, argv style.
3414	*
3415	* @returns VBox status code.
3416	* @param pDevIns The device instance.
3417	* @param pszName The identifier of the info.
3418	* @param pszDesc The description of the info and any arguments
3419	* the handler may take.
3420	* @param pfnHandler The handler function to be called to display the
3421	* info.
3422	*/
3423	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3424
3425	/**
3426	* Registers a set of registers for a device.
3427	*
3428	* The @a pvUser argument of the getter and setter callbacks will be
3429	* @a pDevIns. The register names will be prefixed by the device name followed
3430	* immediately by the instance number.
3431	*
3432	* @returns VBox status code.
3433	* @param pDevIns The device instance.
3434	* @param paRegisters The register descriptors.
3435	*
3436	* @remarks The device critical section is NOT entered prior to working the
3437	* callbacks registered via this helper!
3438	*/
3439	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3440
3441	/**
3442	* Gets the trace buffer handle.
3443	*
3444	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3445	* really inteded for direct usage, thus no inline wrapper function.
3446	*
3447	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3448	* @param pDevIns The device instance.
3449	*/
3450	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3451
3452	/**
3453	* Report a bug check.
3454	*
3455	* @returns
3456	* @param pDevIns The device instance.
3457	* @param enmEvent The kind of BSOD event this is.
3458	* @param uBugCheck The bug check number.
3459	* @param uP1 The bug check parameter \#1.
3460	* @param uP2 The bug check parameter \#2.
3461	* @param uP3 The bug check parameter \#3.
3462	* @param uP4 The bug check parameter \#4.
3463	*
3464	* @thread EMT
3465	*/
3466	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnDBGFReportBugCheck,(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
3467	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4));
3468
3469	/**
3470	* Write core dump of the guest.
3471	*
3472	* @returns VBox status code.
3473	* @param pDevIns The device instance.
3474	* @param pszFilename The name of the file to which the guest core
3475	* dump should be written.
3476	* @param fReplaceFile Whether to replace the file or not.
3477	*
3478	* @remarks The VM may need to be suspended before calling this function in
3479	* order to truly stop all device threads and drivers. This function
3480	* only synchronizes EMTs.
3481	*/
3482	DECLR3CALLBACKMEMBER(int, pfnDBGFCoreWrite,(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile));
3483
3484	/**
3485	* Gets the logger info helper.
3486	* The returned info helper will unconditionally write all output to the log.
3487	*
3488	* @returns Pointer to the logger info helper.
3489	* @param pDevIns The device instance.
3490	*/
3491	DECLR3CALLBACKMEMBER(PCDBGFINFOHLP, pfnDBGFInfoLogHlp,(PPDMDEVINS pDevIns));
3492
3493	/**
3494	* Queries a 64-bit register value.
3495	*
3496	* @retval VINF_SUCCESS
3497	* @retval VERR_INVALID_VM_HANDLE
3498	* @retval VERR_INVALID_CPU_ID
3499	* @retval VERR_DBGF_REGISTER_NOT_FOUND
3500	* @retval VERR_DBGF_UNSUPPORTED_CAST
3501	* @retval VINF_DBGF_TRUNCATED_REGISTER
3502	* @retval VINF_DBGF_ZERO_EXTENDED_REGISTER
3503	*
3504	* @param pDevIns The device instance.
3505	* @param idDefCpu The default target CPU ID, VMCPUID_ANY if not
3506	* applicable. Can be OR'ed with
3507	* DBGFREG_HYPER_VMCPUID.
3508	* @param pszReg The register that's being queried. Except for
3509	* CPU registers, this must be on the form
3510	* "set.reg[.sub]".
3511	* @param pu64 Where to store the register value.
3512	*/
3513	DECLR3CALLBACKMEMBER(int, pfnDBGFRegNmQueryU64,(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64));
3514
3515	/**
3516	* Format a set of registers.
3517	*
3518	* This is restricted to registers from one CPU, that specified by @a idCpu.
3519	*
3520	* @returns VBox status code.
3521	* @param pDevIns The device instance.
3522	* @param idCpu The CPU ID of any CPU registers that may be
3523	* printed, pass VMCPUID_ANY if not applicable.
3524	* @param pszBuf The output buffer.
3525	* @param cbBuf The size of the output buffer.
3526	* @param pszFormat The format string. Register names are given by
3527	* %VR{name}, they take no arguments.
3528	* @param va Other format arguments.
3529	*/
3530	DECLR3CALLBACKMEMBER(int, pfnDBGFRegPrintfV,(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
3531	const char *pszFormat, va_list va));
3532
3533	/**
3534	* Registers a statistics sample.
3535	*
3536	* @param pDevIns Device instance of the DMA.
3537	* @param pvSample Pointer to the sample.
3538	* @param enmType Sample type. This indicates what pvSample is
3539	* pointing at.
3540	* @param pszName Sample name, unix path style. If this does not
3541	* start with a '/', the default prefix will be
3542	* prepended, otherwise it will be used as-is.
3543	* @param enmUnit Sample unit.
3544	* @param pszDesc Sample description.
3545	*/
3546	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3547
3548	/**
3549	* Same as pfnSTAMRegister except that the name is specified in a
3550	* RTStrPrintfV like fashion.
3551	*
3552	* @returns VBox status.
3553	* @param pDevIns Device instance of the DMA.
3554	* @param pvSample Pointer to the sample.
3555	* @param enmType Sample type. This indicates what pvSample is
3556	* pointing at.
3557	* @param enmVisibility Visibility type specifying whether unused
3558	* statistics should be visible or not.
3559	* @param enmUnit Sample unit.
3560	* @param pszDesc Sample description.
3561	* @param pszName Sample name format string, unix path style. If
3562	* this does not start with a '/', the default
3563	* prefix will be prepended, otherwise it will be
3564	* used as-is.
3565	* @param args Arguments to the format string.
3566	*/
3567	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3568	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3569	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3570
3571	/**
3572	* Registers a PCI device with the default PCI bus.
3573	*
3574	* If a PDM device has more than one PCI device, they must be registered in the
3575	* order of PDMDEVINSR3::apPciDevs.
3576	*
3577	* @returns VBox status code.
3578	* @param pDevIns The device instance.
3579	* @param pPciDev The PCI device structure.
3580	* This must be kept in the instance data.
3581	* The PCI configuration must be initialized before registration.
3582	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3583	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3584	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3585	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3586	* device number (0-31). This will be ignored if
3587	* the CFGM configuration contains a PCIDeviceNo
3588	* value.
3589	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3590	* function number (0-7). This will be ignored if
3591	* the CFGM configuration contains a PCIFunctionNo
3592	* value.
3593	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3594	* The pointer is saved, so don't free or changed.
3595	* @note The PCI device configuration is now implicit from the apPciDevs
3596	* index, meaning that the zero'th entry is the primary one and
3597	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3598	*/
3599	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3600	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3601
3602	/**
3603	* Initialize MSI or MSI-X emulation support for the given PCI device.
3604	*
3605	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3606	*
3607	* @returns VBox status code.
3608	* @param pDevIns The device instance.
3609	* @param pPciDev The PCI device. NULL is an alias for the first
3610	* one registered.
3611	* @param pMsiReg MSI emulation registration structure.
3612	*/
3613	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3614
3615	/**
3616	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3617	*
3618	* @returns VBox status code.
3619	* @param pDevIns The device instance.
3620	* @param pPciDev The PCI device structure. If NULL the default
3621	* PCI device for this device instance is used.
3622	* @param iRegion The region number.
3623	* @param cbRegion Size of the region.
3624	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3625	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3626	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3627	* @a fFlags, UINT64_MAX if no handle is passed
3628	* (old style).
3629	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3630	* handle is specified. The callback will be
3631	* invoked holding only the PDM lock. The device
3632	* lock will _not_ be taken (due to lock order).
3633	*/
3634	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3635	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3636	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3637
3638	/**
3639	* Register PCI configuration space read/write callbacks.
3640	*
3641	* @returns VBox status code.
3642	* @param pDevIns The device instance.
3643	* @param pPciDev The PCI device structure. If NULL the default
3644	* PCI device for this device instance is used.
3645	* @param pfnRead Pointer to the user defined PCI config read function.
3646	* to call default PCI config read function. Can be NULL.
3647	* @param pfnWrite Pointer to the user defined PCI config write function.
3648	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3649	* is NOT take because that is very likely be a lock order violation.
3650	* @thread EMT(0)
3651	* @note Only callable during VM creation.
3652	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3653	*/
3654	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3655	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3656
3657	/**
3658	* Perform a PCI configuration space write.
3659	*
3660	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3661	*
3662	* @returns Strict VBox status code (mainly DBGFSTOP).
3663	* @param pDevIns The device instance.
3664	* @param pPciDev The PCI device which config space is being read.
3665	* @param uAddress The config space address.
3666	* @param cb The size of the read: 1, 2 or 4 bytes.
3667	* @param u32Value The value to write.
3668	*/
3669	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3670	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3671
3672	/**
3673	* Perform a PCI configuration space read.
3674	*
3675	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3676	*
3677	* @returns Strict VBox status code (mainly DBGFSTOP).
3678	* @param pDevIns The device instance.
3679	* @param pPciDev The PCI device which config space is being read.
3680	* @param uAddress The config space address.
3681	* @param cb The size of the read: 1, 2 or 4 bytes.
3682	* @param pu32Value Where to return the value.
3683	*/
3684	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3685	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3686
3687	/**
3688	* Bus master physical memory read.
3689	*
3690	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3691	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3692	* @param pDevIns The device instance.
3693	* @param pPciDev The PCI device structure. If NULL the default
3694	* PCI device for this device instance is used.
3695	* @param GCPhys Physical address start reading from.
3696	* @param pvBuf Where to put the read bits.
3697	* @param cbRead How many bytes to read.
3698	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3699	* @thread Any thread, but the call may involve the emulation thread.
3700	*/
3701	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3702
3703	/**
3704	* Bus master physical memory write.
3705	*
3706	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3707	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3708	* @param pDevIns The device instance.
3709	* @param pPciDev The PCI device structure. If NULL the default
3710	* PCI device for this device instance is used.
3711	* @param GCPhys Physical address to write to.
3712	* @param pvBuf What to write.
3713	* @param cbWrite How many bytes to write.
3714	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3715	* @thread Any thread, but the call may involve the emulation thread.
3716	*/
3717	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3718
3719	/**
3720	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3721	* physical memory write operation.
3722	*
3723	* Refer pfnPhysGCPhys2CCPtr() for further details.
3724	*
3725	* @returns VBox status code.
3726	* @param pDevIns The device instance.
3727	* @param pPciDev The PCI device structure. If NULL the default
3728	* PCI device for this device instance is used.
3729	* @param GCPhys The guest physical address of the page that should be
3730	* mapped.
3731	* @param fFlags Flags reserved for future use, MBZ.
3732	* @param ppv Where to store the address corresponding to GCPhys.
3733	* @param pLock Where to store the lock information that
3734	* pfnPhysReleasePageMappingLock needs.
3735	*
3736	* @remarks Avoid calling this API from within critical sections (other than the PGM
3737	* one) because of the deadlock risk when we have to delegating the task to
3738	* an EMT.
3739	* @thread Any.
3740	*/
3741	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3742	void **ppv, PPGMPAGEMAPLOCK pLock));
3743
3744	/**
3745	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3746	* for a bus master physical memory read operation.
3747	*
3748	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3749	*
3750	* @returns VBox status code.
3751	* @param pDevIns The device instance.
3752	* @param pPciDev The PCI device structure. If NULL the default
3753	* PCI device for this device instance is used.
3754	* @param GCPhys The guest physical address of the page that
3755	* should be mapped.
3756	* @param fFlags Flags reserved for future use, MBZ.
3757	* @param ppv Where to store the address corresponding to
3758	* GCPhys.
3759	* @param pLock Where to store the lock information that
3760	* pfnPhysReleasePageMappingLock needs.
3761	*
3762	* @remarks Avoid calling this API from within critical sections.
3763	* @thread Any.
3764	*/
3765	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3766	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3767
3768	/**
3769	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3770	* master physical memory write operation.
3771	*
3772	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3773	* ASAP to release them.
3774	*
3775	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3776	*
3777	* @returns VBox status code.
3778	* @param pDevIns The device instance.
3779	* @param pPciDev The PCI device structure. If NULL the default
3780	* PCI device for this device instance is used.
3781	* @param cPages Number of pages to lock.
3782	* @param paGCPhysPages The guest physical address of the pages that
3783	* should be mapped (@a cPages entries).
3784	* @param fFlags Flags reserved for future use, MBZ.
3785	* @param papvPages Where to store the ring-3 mapping addresses
3786	* corresponding to @a paGCPhysPages.
3787	* @param paLocks Where to store the locking information that
3788	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3789	* in length).
3790	*/
3791	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3792	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3793	PPGMPAGEMAPLOCK paLocks));
3794
3795	/**
3796	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3797	* master physical memory read operation.
3798	*
3799	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3800	* ASAP to release them.
3801	*
3802	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3803	*
3804	* @returns VBox status code.
3805	* @param pDevIns The device instance.
3806	* @param pPciDev The PCI device structure. If NULL the default
3807	* PCI device for this device instance is used.
3808	* @param cPages Number of pages to lock.
3809	* @param paGCPhysPages The guest physical address of the pages that
3810	* should be mapped (@a cPages entries).
3811	* @param fFlags Flags reserved for future use, MBZ.
3812	* @param papvPages Where to store the ring-3 mapping addresses
3813	* corresponding to @a paGCPhysPages.
3814	* @param paLocks Where to store the lock information that
3815	* pfnPhysReleasePageMappingLock needs (@a cPages
3816	* in length).
3817	*/
3818	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3819	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3820	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3821
3822	/**
3823	* Sets the IRQ for the given PCI device.
3824	*
3825	* @param pDevIns The device instance.
3826	* @param pPciDev The PCI device structure. If NULL the default
3827	* PCI device for this device instance is used.
3828	* @param iIrq IRQ number to set.
3829	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3830	* @thread Any thread, but will involve the emulation thread.
3831	*/
3832	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3833
3834	/**
3835	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3836	* the request when not called from EMT.
3837	*
3838	* @param pDevIns The device instance.
3839	* @param pPciDev The PCI device structure. If NULL the default
3840	* PCI device for this device instance is used.
3841	* @param iIrq IRQ number to set.
3842	* @param iLevel IRQ level.
3843	* @thread Any thread, but will involve the emulation thread.
3844	*/
3845	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3846
3847	/**
3848	* Set ISA IRQ for a device.
3849	*
3850	* @param pDevIns The device instance.
3851	* @param iIrq IRQ number to set.
3852	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3853	* @thread Any thread, but will involve the emulation thread.
3854	*/
3855	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3856
3857	/**
3858	* Set the ISA IRQ for a device, but don't wait for EMT to process
3859	* the request when not called from EMT.
3860	*
3861	* @param pDevIns The device instance.
3862	* @param iIrq IRQ number to set.
3863	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3864	* @thread Any thread, but will involve the emulation thread.
3865	*/
3866	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3867
3868	/**
3869	* Attaches a driver (chain) to the device.
3870	*
3871	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3872	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3873	*
3874	* @returns VBox status code.
3875	* @param pDevIns The device instance.
3876	* @param iLun The logical unit to attach.
3877	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3878	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3879	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3880	* for the live of the device instance.
3881	*/
3882	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3883	PPDMIBASE ppBaseInterface, const char pszDesc));
3884
3885	/**
3886	* Detaches an attached driver (chain) from the device again.
3887	*
3888	* @returns VBox status code.
3889	* @param pDevIns The device instance.
3890	* @param pDrvIns The driver instance to detach.
3891	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3892	*/
3893	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3894
3895	/**
3896	* Reconfigures the driver chain for a LUN, detaching any driver currently
3897	* present there.
3898	*
3899	* Caller will have attach it, of course.
3900	*
3901	* @returns VBox status code.
3902	* @param pDevIns The device instance.
3903	* @param iLun The logical unit to reconfigure.
3904	* @param cDepth The depth of the driver chain. Determins the
3905	* size of @a papszDrivers and @a papConfigs.
3906	* @param papszDrivers The names of the drivers to configure in the
3907	* chain, first entry is the one immediately
3908	* below the device/LUN
3909	* @param papConfigs The configurations for each of the drivers
3910	* in @a papszDrivers array. NULL entries
3911	* corresponds to empty 'Config' nodes. This
3912	* function will take ownership of non-NULL
3913	* CFGM sub-trees and set the array member to
3914	* NULL, so the caller can do cleanups on
3915	* failure. This parameter is optional.
3916	* @param fFlags Reserved, MBZ.
3917	*/
3918	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3919	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3920
3921	/** @name Exported PDM Queue Functions
3922	* @{ */
3923	/**
3924	* Create a queue.
3925	*
3926	* @returns VBox status code.
3927	* @param pDevIns The device instance.
3928	* @param cbItem The size of a queue item.
3929	* @param cItems The number of items in the queue.
3930	* @param cMilliesInterval The number of milliseconds between polling the queue.
3931	* If 0 then the emulation thread will be notified whenever an item arrives.
3932	* @param pfnCallback The consumer function.
3933	* @param fRZEnabled Set if the queue should work in RC and R0.
3934	* @param pszName The queue base name. The instance number will be
3935	* appended automatically.
3936	* @param phQueue Where to store the queue handle on success.
3937	* @thread EMT(0)
3938	* @remarks The device critical section will NOT be entered before calling the
3939	* callback. No locks will be held, but for now it's safe to assume
3940	* that only one EMT will do queue callbacks at any one time.
3941	*/
3942	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3943	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3944	PDMQUEUEHANDLE *phQueue));
3945
3946	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3947	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3948	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3949	/** @} */
3950
3951	/** @name PDM Task
3952	* @{ */
3953	/**
3954	* Create an asynchronous ring-3 task.
3955	*
3956	* @returns VBox status code.
3957	* @param pDevIns The device instance.
3958	* @param fFlags PDMTASK_F_XXX
3959	* @param pszName The function name or similar. Used for statistics,
3960	* so no slashes.
3961	* @param pfnCallback The task function.
3962	* @param pvUser User argument for the task function.
3963	* @param phTask Where to return the task handle.
3964	* @thread EMT(0)
3965	*/
3966	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3967	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3968	/**
3969	* Triggers the running the given task.
3970	*
3971	* @returns VBox status code.
3972	* @retval VINF_ALREADY_POSTED is the task is already pending.
3973	* @param pDevIns The device instance.
3974	* @param hTask The task to trigger.
3975	* @thread Any thread.
3976	*/
3977	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3978	/** @} */
3979
3980	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3981	* These semaphores can be signalled from ring-0.
3982	* @{ */
3983	/** @sa SUPSemEventCreate */
3984	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3985	/** @sa SUPSemEventClose */
3986	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3987	/** @sa SUPSemEventSignal */
3988	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3989	/** @sa SUPSemEventWaitNoResume */
3990	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3991	/** @sa SUPSemEventWaitNsAbsIntr */
3992	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3993	/** @sa SUPSemEventWaitNsRelIntr */
3994	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3995	/** @sa SUPSemEventGetResolution */
3996	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3997	/** @} */
3998
3999	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
4000	* These semaphores can be signalled from ring-0.
4001	* @{ */
4002	/** @sa SUPSemEventMultiCreate */
4003	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
4004	/** @sa SUPSemEventMultiClose */
4005	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4006	/** @sa SUPSemEventMultiSignal */
4007	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4008	/** @sa SUPSemEventMultiReset */
4009	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4010	/** @sa SUPSemEventMultiWaitNoResume */
4011	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
4012	/** @sa SUPSemEventMultiWaitNsAbsIntr */
4013	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
4014	/** @sa SUPSemEventMultiWaitNsRelIntr */
4015	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
4016	/** @sa SUPSemEventMultiGetResolution */
4017	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
4018	/** @} */
4019
4020	/**
4021	* Initializes a PDM critical section.
4022	*
4023	* The PDM critical sections are derived from the IPRT critical sections, but
4024	* works in RC and R0 as well.
4025	*
4026	* @returns VBox status code.
4027	* @param pDevIns The device instance.
4028	* @param pCritSect Pointer to the critical section.
4029	* @param SRC_POS Use RT_SRC_POS.
4030	* @param pszNameFmt Format string for naming the critical section.
4031	* For statistics and lock validation.
4032	* @param va Arguments for the format string.
4033	*/
4034	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
4035	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4036
4037	/**
4038	* Gets the NOP critical section.
4039	*
4040	* @returns The ring-3 address of the NOP critical section.
4041	* @param pDevIns The device instance.
4042	*/
4043	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4044
4045	/**
4046	* Changes the device level critical section from the automatically created
4047	* default to one desired by the device constructor.
4048	*
4049	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
4050	* the additional contexts.
4051	*
4052	* @returns VBox status code.
4053	* @param pDevIns The device instance.
4054	* @param pCritSect The critical section to use. NULL is not
4055	* valid, instead use the NOP critical
4056	* section.
4057	*/
4058	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4059
4060	/** @name Exported PDM Critical Section Functions
4061	* @{ */
4062	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4063	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4064	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4065	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4066	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4067	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4068	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4069	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4070	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4071	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4072	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
4073	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4074	/** @} */
4075
4076	/** @name Exported PDM Read/Write Critical Section Functions
4077	* @{ */
4078	DECLR3CALLBACKMEMBER(int, pfnCritSectRwInit,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
4079	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4080	DECLR3CALLBACKMEMBER(int, pfnCritSectRwDelete,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4081
4082	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4083	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4084	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4085	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4086	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4087
4088	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4089	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4090	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4091	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4092	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4093
4094	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4095	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
4096	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4097	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4098	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4099	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4100	/** @} */
4101
4102	/**
4103	* Creates a PDM thread.
4104	*
4105	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
4106	* resuming, and destroying the thread as the VM state changes.
4107	*
4108	* @returns VBox status code.
4109	* @param pDevIns The device instance.
4110	* @param ppThread Where to store the thread 'handle'.
4111	* @param pvUser The user argument to the thread function.
4112	* @param pfnThread The thread function.
4113	* @param pfnWakeup The wakup callback. This is called on the EMT
4114	* thread when a state change is pending.
4115	* @param cbStack See RTThreadCreate.
4116	* @param enmType See RTThreadCreate.
4117	* @param pszName See RTThreadCreate.
4118	* @remarks The device critical section will NOT be entered prior to invoking
4119	* the function pointers.
4120	*/
4121	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
4122	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
4123
4124	/** @name Exported PDM Thread Functions
4125	* @{ */
4126	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
4127	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
4128	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
4129	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
4130	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
4131	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
4132	/** @} */
4133
4134	/**
4135	* Set up asynchronous handling of a suspend, reset or power off notification.
4136	*
4137	* This shall only be called when getting the notification. It must be called
4138	* for each one.
4139	*
4140	* @returns VBox status code.
4141	* @param pDevIns The device instance.
4142	* @param pfnAsyncNotify The callback.
4143	* @thread EMT(0)
4144	* @remarks The caller will enter the device critical section prior to invoking
4145	* the callback.
4146	*/
4147	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
4148
4149	/**
4150	* Notify EMT(0) that the device has completed the asynchronous notification
4151	* handling.
4152	*
4153	* This can be called at any time, spurious calls will simply be ignored.
4154	*
4155	* @param pDevIns The device instance.
4156	* @thread Any
4157	*/
4158	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
4159
4160	/**
4161	* Register the RTC device.
4162	*
4163	* @returns VBox status code.
4164	* @param pDevIns The device instance.
4165	* @param pRtcReg Pointer to a RTC registration structure.
4166	* @param ppRtcHlp Where to store the pointer to the helper
4167	* functions.
4168	*/
4169	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
4170
4171	/**
4172	* Register a PCI Bus.
4173	*
4174	* @returns VBox status code, but the positive values 0..31 are used to indicate
4175	* bus number rather than informational status codes.
4176	* @param pDevIns The device instance.
4177	* @param pPciBusReg Pointer to PCI bus registration structure.
4178	* @param ppPciHlp Where to store the pointer to the PCI Bus
4179	* helpers.
4180	* @param piBus Where to return the PDM bus number. Optional.
4181	*/
4182	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
4183	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
4184
4185	/**
4186	* Register the IOMMU device.
4187	*
4188	* @returns VBox status code.
4189	* @param pDevIns The device instance.
4190	* @param pIommuReg Pointer to a IOMMU registration structure.
4191	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
4192	* helpers.
4193	* @param pidxIommu Where to return the IOMMU index. Optional.
4194	*/
4195	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
4196	uint32_t *pidxIommu));
4197
4198	/**
4199	* Register the PIC device.
4200	*
4201	* @returns VBox status code.
4202	* @param pDevIns The device instance.
4203	* @param pPicReg Pointer to a PIC registration structure.
4204	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
4205	* helpers.
4206	* @sa PDMDevHlpPICSetUpContext
4207	*/
4208	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4209
4210	/**
4211	* Register the APIC device.
4212	*
4213	* @returns VBox status code.
4214	* @param pDevIns The device instance.
4215	*/
4216	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
4217
4218	/**
4219	* Register the I/O APIC device.
4220	*
4221	* @returns VBox status code.
4222	* @param pDevIns The device instance.
4223	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4224	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
4225	* helpers.
4226	*/
4227	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4228
4229	/**
4230	* Register the HPET device.
4231	*
4232	* @returns VBox status code.
4233	* @param pDevIns The device instance.
4234	* @param pHpetReg Pointer to a HPET registration structure.
4235	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4236	* helpers.
4237	*/
4238	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4239
4240	/**
4241	* Register a raw PCI device.
4242	*
4243	* @returns VBox status code.
4244	* @param pDevIns The device instance.
4245	* @param pPciRawReg Pointer to a raw PCI registration structure.
4246	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4247	* device helpers.
4248	*/
4249	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4250
4251	/**
4252	* Register the DMA device.
4253	*
4254	* @returns VBox status code.
4255	* @param pDevIns The device instance.
4256	* @param pDmacReg Pointer to a DMAC registration structure.
4257	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4258	*/
4259	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4260
4261	/**
4262	* Register transfer function for DMA channel.
4263	*
4264	* @returns VBox status code.
4265	* @param pDevIns The device instance.
4266	* @param uChannel Channel number.
4267	* @param pfnTransferHandler Device specific transfer callback function.
4268	* @param pvUser User pointer to pass to the callback.
4269	* @thread EMT
4270	*/
4271	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4272
4273	/**
4274	* Read memory.
4275	*
4276	* @returns VBox status code.
4277	* @param pDevIns The device instance.
4278	* @param uChannel Channel number.
4279	* @param pvBuffer Pointer to target buffer.
4280	* @param off DMA position.
4281	* @param cbBlock Block size.
4282	* @param pcbRead Where to store the number of bytes which was
4283	* read. optional.
4284	* @thread EMT
4285	*/
4286	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4287
4288	/**
4289	* Write memory.
4290	*
4291	* @returns VBox status code.
4292	* @param pDevIns The device instance.
4293	* @param uChannel Channel number.
4294	* @param pvBuffer Memory to write.
4295	* @param off DMA position.
4296	* @param cbBlock Block size.
4297	* @param pcbWritten Where to store the number of bytes which was
4298	* written. optional.
4299	* @thread EMT
4300	*/
4301	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4302
4303	/**
4304	* Set the DREQ line.
4305	*
4306	* @returns VBox status code.
4307	* @param pDevIns Device instance.
4308	* @param uChannel Channel number.
4309	* @param uLevel Level of the line.
4310	* @thread EMT
4311	*/
4312	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4313
4314	/**
4315	* Get channel mode.
4316	*
4317	* @returns Channel mode. See specs.
4318	* @param pDevIns The device instance.
4319	* @param uChannel Channel number.
4320	* @thread EMT
4321	*/
4322	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4323
4324	/**
4325	* Schedule DMA execution.
4326	*
4327	* @param pDevIns The device instance.
4328	* @thread Any thread.
4329	*/
4330	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4331
4332	/**
4333	* Write CMOS value and update the checksum(s).
4334	*
4335	* @returns VBox status code.
4336	* @param pDevIns The device instance.
4337	* @param iReg The CMOS register index.
4338	* @param u8Value The CMOS register value.
4339	* @thread EMT
4340	*/
4341	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4342
4343	/**
4344	* Read CMOS value.
4345	*
4346	* @returns VBox status code.
4347	* @param pDevIns The device instance.
4348	* @param iReg The CMOS register index.
4349	* @param pu8Value Where to store the CMOS register value.
4350	* @thread EMT
4351	*/
4352	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4353
4354	/**
4355	* Assert that the current thread is the emulation thread.
4356	*
4357	* @returns True if correct.
4358	* @returns False if wrong.
4359	* @param pDevIns The device instance.
4360	* @param pszFile Filename of the assertion location.
4361	* @param iLine The linenumber of the assertion location.
4362	* @param pszFunction Function of the assertion location.
4363	*/
4364	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4365
4366	/**
4367	* Assert that the current thread is NOT the emulation thread.
4368	*
4369	* @returns True if correct.
4370	* @returns False if wrong.
4371	* @param pDevIns The device instance.
4372	* @param pszFile Filename of the assertion location.
4373	* @param iLine The linenumber of the assertion location.
4374	* @param pszFunction Function of the assertion location.
4375	*/
4376	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4377
4378	/**
4379	* Resolves the symbol for a raw-mode context interface.
4380	*
4381	* @returns VBox status code.
4382	* @param pDevIns The device instance.
4383	* @param pvInterface The interface structure.
4384	* @param cbInterface The size of the interface structure.
4385	* @param pszSymPrefix What to prefix the symbols in the list with
4386	* before resolving them. This must start with
4387	* 'dev' and contain the driver name.
4388	* @param pszSymList List of symbols corresponding to the interface.
4389	* There is generally a there is generally a define
4390	* holding this list associated with the interface
4391	* definition (INTERFACE_SYM_LIST). For more
4392	* details see PDMR3LdrGetInterfaceSymbols.
4393	* @thread EMT
4394	*/
4395	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4396	const char pszSymPrefix, const char pszSymList));
4397
4398	/**
4399	* Resolves the symbol for a ring-0 context interface.
4400	*
4401	* @returns VBox status code.
4402	* @param pDevIns The device instance.
4403	* @param pvInterface The interface structure.
4404	* @param cbInterface The size of the interface structure.
4405	* @param pszSymPrefix What to prefix the symbols in the list with
4406	* before resolving them. This must start with
4407	* 'dev' and contain the driver name.
4408	* @param pszSymList List of symbols corresponding to the interface.
4409	* There is generally a there is generally a define
4410	* holding this list associated with the interface
4411	* definition (INTERFACE_SYM_LIST). For more
4412	* details see PDMR3LdrGetInterfaceSymbols.
4413	* @thread EMT
4414	*/
4415	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4416	const char pszSymPrefix, const char pszSymList));
4417
4418	/**
4419	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4420	*
4421	* @returns VBox status code.
4422	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4423	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4424	*
4425	* @param pDevIns The device instance.
4426	* @param uOperation The operation to perform.
4427	* @param u64Arg 64-bit integer argument.
4428	* @thread EMT
4429	*/
4430	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4431
4432	/**
4433	* Gets the reason for the most recent VM suspend.
4434	*
4435	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4436	* suspend has been made or if the pDevIns is invalid.
4437	* @param pDevIns The device instance.
4438	*/
4439	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4440
4441	/**
4442	* Gets the reason for the most recent VM resume.
4443	*
4444	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4445	* resume has been made or if the pDevIns is invalid.
4446	* @param pDevIns The device instance.
4447	*/
4448	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4449
4450	/**
4451	* Requests the mapping of multiple guest page into ring-3.
4452	*
4453	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4454	* ASAP to release them.
4455	*
4456	* This API will assume your intention is to write to the pages, and will
4457	* therefore replace shared and zero pages. If you do not intend to modify the
4458	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4459	*
4460	* @returns VBox status code.
4461	* @retval VINF_SUCCESS on success.
4462	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4463	* backing or if any of the pages the page has any active access
4464	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4465	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4466	* an invalid physical address.
4467	*
4468	* @param pDevIns The device instance.
4469	* @param cPages Number of pages to lock.
4470	* @param paGCPhysPages The guest physical address of the pages that
4471	* should be mapped (@a cPages entries).
4472	* @param fFlags Flags reserved for future use, MBZ.
4473	* @param papvPages Where to store the ring-3 mapping addresses
4474	* corresponding to @a paGCPhysPages.
4475	* @param paLocks Where to store the locking information that
4476	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4477	* in length).
4478	*
4479	* @remark Avoid calling this API from within critical sections (other than the
4480	* PGM one) because of the deadlock risk when we have to delegating the
4481	* task to an EMT.
4482	* @thread Any.
4483	* @since 6.0.6
4484	*/
4485	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4486	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4487
4488	/**
4489	* Requests the mapping of multiple guest page into ring-3, for reading only.
4490	*
4491	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4492	* ASAP to release them.
4493	*
4494	* @returns VBox status code.
4495	* @retval VINF_SUCCESS on success.
4496	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4497	* backing or if any of the pages the page has an active ALL access
4498	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4499	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4500	* an invalid physical address.
4501	*
4502	* @param pDevIns The device instance.
4503	* @param cPages Number of pages to lock.
4504	* @param paGCPhysPages The guest physical address of the pages that
4505	* should be mapped (@a cPages entries).
4506	* @param fFlags Flags reserved for future use, MBZ.
4507	* @param papvPages Where to store the ring-3 mapping addresses
4508	* corresponding to @a paGCPhysPages.
4509	* @param paLocks Where to store the lock information that
4510	* pfnPhysReleasePageMappingLock needs (@a cPages
4511	* in length).
4512	*
4513	* @remark Avoid calling this API from within critical sections.
4514	* @thread Any.
4515	* @since 6.0.6
4516	*/
4517	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4518	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4519
4520	/**
4521	* Release the mappings of multiple guest pages.
4522	*
4523	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4524	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4525	*
4526	* @param pDevIns The device instance.
4527	* @param cPages Number of pages to unlock.
4528	* @param paLocks The lock structures initialized by the mapping
4529	* function (@a cPages in length).
4530	* @thread Any.
4531	* @since 6.0.6
4532	*/
4533	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4534
4535	/**
4536	* Returns the micro architecture used for the guest.
4537	*
4538	* @returns CPU micro architecture enum.
4539	* @param pDevIns The device instance.
4540	*/
4541	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4542
4543	/**
4544	* Get the number of physical and linear address bits supported by the guest.
4545	*
4546	* @param pDevIns The device instance.
4547	* @param pcPhysAddrWidth Where to store the number of physical address bits
4548	* supported by the guest.
4549	* @param pcLinearAddrWidth Where to store the number of linear address bits
4550	* supported by the guest.
4551	*/
4552	DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4553	uint8_t *pcLinearAddrWidth));
4554
4555	/** Space reserved for future members.
4556	* @{ */
4557	/**
4558	* Deregister zero or more samples given their name prefix.
4559	*
4560	* @returns VBox status code.
4561	* @param pDevIns The device instance.
4562	* @param pszPrefix The name prefix of the samples to remove. If this does
4563	* not start with a '/', the default prefix will be
4564	* prepended, otherwise it will be used as-is.
4565	*/
4566	DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4567	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4568	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4569	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4570	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4571	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4572	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4573	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4574	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4575	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4576	/** @} */
4577
4578
4579	/** API available to trusted devices only.
4580	*
4581	* These APIs are providing unrestricted access to the guest and the VM,
4582	* or they are interacting intimately with PDM.
4583	*
4584	* @{
4585	*/
4586
4587	/**
4588	* Gets the user mode VM handle. Restricted API.
4589	*
4590	* @returns User mode VM Handle.
4591	* @param pDevIns The device instance.
4592	*/
4593	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4594
4595	/**
4596	* Gets the global VM handle. Restricted API.
4597	*
4598	* @returns VM Handle.
4599	* @param pDevIns The device instance.
4600	*/
4601	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4602
4603	/**
4604	* Gets the VMCPU handle. Restricted API.
4605	*
4606	* @returns VMCPU Handle.
4607	* @param pDevIns The device instance.
4608	*/
4609	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4610
4611	/**
4612	* The the VM CPU ID of the current thread (restricted API).
4613	*
4614	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4615	* @param pDevIns The device instance.
4616	*/
4617	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4618
4619	/**
4620	* Registers the VMM device heap or notifies about mapping/unmapping.
4621	*
4622	* This interface serves three purposes:
4623	*
4624	* -# Register the VMM device heap during device construction
4625	* for the HM to use.
4626	* -# Notify PDM/HM that it's mapped into guest address
4627	* space (i.e. usable).
4628	* -# Notify PDM/HM that it is being unmapped from the guest
4629	* address space (i.e. not usable).
4630	*
4631	* @returns VBox status code.
4632	* @param pDevIns The device instance.
4633	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4634	* not mapped.
4635	* @param pvHeap Ring 3 heap pointer.
4636	* @param cbHeap Size of the heap.
4637	* @thread EMT.
4638	*/
4639	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4640
4641	/**
4642	* Registers the firmware (BIOS, EFI) device with PDM.
4643	*
4644	* The firmware provides a callback table and gets a special PDM helper table.
4645	* There can only be one firmware device for a VM.
4646	*
4647	* @returns VBox status code.
4648	* @param pDevIns The device instance.
4649	* @param pFwReg Firmware registration structure.
4650	* @param ppFwHlp Where to return the firmware helper structure.
4651	* @remarks Only valid during device construction.
4652	* @thread EMT(0)
4653	*/
4654	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4655
4656	/**
4657	* Resets the VM.
4658	*
4659	* @returns The appropriate VBox status code to pass around on reset.
4660	* @param pDevIns The device instance.
4661	* @param fFlags PDMVMRESET_F_XXX flags.
4662	* @thread The emulation thread.
4663	*/
4664	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4665
4666	/**
4667	* Suspends the VM.
4668	*
4669	* @returns The appropriate VBox status code to pass around on suspend.
4670	* @param pDevIns The device instance.
4671	* @thread The emulation thread.
4672	*/
4673	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4674
4675	/**
4676	* Suspends, saves and powers off the VM.
4677	*
4678	* @returns The appropriate VBox status code to pass around.
4679	* @param pDevIns The device instance.
4680	* @thread An emulation thread.
4681	*/
4682	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4683
4684	/**
4685	* Power off the VM.
4686	*
4687	* @returns The appropriate VBox status code to pass around on power off.
4688	* @param pDevIns The device instance.
4689	* @thread The emulation thread.
4690	*/
4691	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4692
4693	/**
4694	* Checks if the Gate A20 is enabled or not.
4695	*
4696	* @returns true if A20 is enabled.
4697	* @returns false if A20 is disabled.
4698	* @param pDevIns The device instance.
4699	* @thread The emulation thread.
4700	*/
4701	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4702
4703	/**
4704	* Enables or disables the Gate A20.
4705	*
4706	* @param pDevIns The device instance.
4707	* @param fEnable Set this flag to enable the Gate A20; clear it
4708	* to disable.
4709	* @thread The emulation thread.
4710	*/
4711	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4712
4713	/**
4714	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4715	* thread.
4716	*
4717	* @param pDevIns The device instance.
4718	* @param iLeaf The CPUID leaf to get.
4719	* @param pEax Where to store the EAX value.
4720	* @param pEbx Where to store the EBX value.
4721	* @param pEcx Where to store the ECX value.
4722	* @param pEdx Where to store the EDX value.
4723	* @thread EMT.
4724	*/
4725	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4726
4727	/**
4728	* Get the current virtual clock time in a VM. The clock frequency must be
4729	* queried separately.
4730	*
4731	* @returns Current clock time.
4732	* @param pDevIns The device instance.
4733	*/
4734	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4735
4736	/**
4737	* Get the frequency of the virtual clock.
4738	*
4739	* @returns The clock frequency (not variable at run-time).
4740	* @param pDevIns The device instance.
4741	*/
4742	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4743
4744	/**
4745	* Get the current virtual clock time in a VM, in nanoseconds.
4746	*
4747	* @returns Current clock time (in ns).
4748	* @param pDevIns The device instance.
4749	*/
4750	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4751
4752	/**
4753	* Gets the support driver session.
4754	*
4755	* This is intended for working with the semaphore API.
4756	*
4757	* @returns Support driver session handle.
4758	* @param pDevIns The device instance.
4759	*/
4760	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4761
4762	/**
4763	* Queries a generic object from the VMM user.
4764	*
4765	* @returns Pointer to the object if found, NULL if not.
4766	* @param pDevIns The device instance.
4767	* @param pUuid The UUID of what's being queried. The UUIDs and
4768	* the usage conventions are defined by the user.
4769	*
4770	* @note It is strictly forbidden to call this internally in VBox! This
4771	* interface is exclusively for hacks in externally developed devices.
4772	*/
4773	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4774
4775	/**
4776	* Register a physical page access handler type.
4777	*
4778	* @returns VBox status code.
4779	* @param pDevIns The device instance.
4780	* @param enmKind The kind of access handler.
4781	* @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4782	* @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4783	* handler should be called.
4784	* @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4785	* ring-3 handler should be called.
4786	* @param pszHandlerRC The name of the raw-mode context handler, NULL if
4787	* the ring-3 handler should be called.
4788	* @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4789	* if the ring-3 handler should be called.
4790	* @param pszDesc The type description.
4791	* @param phType Where to return the type handle (cross context
4792	* safe).
4793	*/
4794	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4795	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4796	const char pszHandlerR0, const char pszPfHandlerR0,
4797	const char pszHandlerRC, const char pszPfHandlerRC,
4798	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4799
4800	/**
4801	* Register a access handler for a physical range.
4802	*
4803	* @returns VBox status code.
4804	* @retval VINF_SUCCESS when successfully installed.
4805	* @retval VINF_PGM_GCPHYS_ALIASED when the shadow PTs could be updated because
4806	* the guest page aliased or/and mapped by multiple PTs. A CR3 sync has been
4807	* flagged together with a pool clearing.
4808	* @retval VERR_PGM_HANDLER_PHYSICAL_CONFLICT if the range conflicts with an existing
4809	* one. A debug assertion is raised.
4810	*
4811	* @param pDevIns The device instance.
4812	* @param GCPhys Start physical address.
4813	* @param GCPhysLast Last physical address. (inclusive)
4814	* @param hType The handler type registration handle.
4815	* @param pvUserR3 User argument to the R3 handler.
4816	* @param pvUserR0 User argument to the R0 handler.
4817	* @param pvUserRC User argument to the RC handler. This can be a value
4818	* less that 0x10000 or a (non-null) pointer that is
4819	* automatically relocated.
4820	* @param pszDesc Description of this handler. If NULL, the type
4821	* description will be used instead.
4822	*/
4823	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalRegister, (PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
4824	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4825	RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc));
4826
4827	/**
4828	* Deregister a physical page access handler.
4829	*
4830	* @returns VBox status code.
4831	* @param pDevIns The device instance.
4832	* @param GCPhys Start physical address.
4833	*/
4834	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalDeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4835
4836	/**
4837	* Temporarily turns off the access monitoring of a page within a monitored
4838	* physical write/all page access handler region.
4839	*
4840	* Use this when no further \#PFs are required for that page. Be aware that
4841	* a page directory sync might reset the flags, and turn on access monitoring
4842	* for the page.
4843	*
4844	* The caller must do required page table modifications.
4845	*
4846	* @returns VBox status code.
4847	* @param pDevIns The device instance.
4848	* @param GCPhys The start address of the access handler. This
4849	* must be a fully page aligned range or we risk
4850	* messing up other handlers installed for the
4851	* start and end pages.
4852	* @param GCPhysPage The physical address of the page to turn off
4853	* access monitoring for.
4854	*/
4855	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
4856
4857	/**
4858	* Resets any modifications to individual pages in a physical page access
4859	* handler region.
4860	*
4861	* This is used in pair with PGMHandlerPhysicalPageTempOff(),
4862	* PGMHandlerPhysicalPageAliasMmio2() or PGMHandlerPhysicalPageAliasHC().
4863	*
4864	* @returns VBox status code.
4865	* @param pDevIns The device instance.
4866	* @param GCPhys The start address of the handler regions, i.e. what you
4867	* passed to PGMR3HandlerPhysicalRegister(),
4868	* PGMHandlerPhysicalRegisterEx() or
4869	* PGMHandlerPhysicalModify().
4870	*/
4871	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalReset,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4872
4873	/**
4874	* Registers the guest memory range that can be used for patching.
4875	*
4876	* @returns VBox status code.
4877	* @param pDevIns The device instance.
4878	* @param GCPtrPatchMem Patch memory range.
4879	* @param cbPatchMem Size of the memory range.
4880	*/
4881	DECLR3CALLBACKMEMBER(int, pfnVMMRegisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4882
4883	/**
4884	* Deregisters the guest memory range that can be used for patching.
4885	*
4886	* @returns VBox status code.
4887	* @param pDevIns The device instance.
4888	* @param GCPtrPatchMem Patch memory range.
4889	* @param cbPatchMem Size of the memory range.
4890	*/
4891	DECLR3CALLBACKMEMBER(int, pfnVMMDeregisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4892
4893	/**
4894	* Registers a new shared module for the VM
4895	*
4896	* @returns VBox status code.
4897	* @param pDevIns The device instance.
4898	* @param enmGuestOS Guest OS type.
4899	* @param pszModuleName Module name.
4900	* @param pszVersion Module version.
4901	* @param GCBaseAddr Module base address.
4902	* @param cbModule Module size.
4903	* @param cRegions Number of shared region descriptors.
4904	* @param paRegions Shared region(s).
4905	*/
4906	DECLR3CALLBACKMEMBER(int, pfnSharedModuleRegister,(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
4907	RTGCPTR GCBaseAddr, uint32_t cbModule,
4908	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions));
4909
4910	/**
4911	* Unregisters a shared module for the VM
4912	*
4913	* @returns VBox status code.
4914	* @param pDevIns The device instance.
4915	* @param pszModuleName Module name.
4916	* @param pszVersion Module version.
4917	* @param GCBaseAddr Module base address.
4918	* @param cbModule Module size.
4919	*/
4920	DECLR3CALLBACKMEMBER(int, pfnSharedModuleUnregister,(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
4921	RTGCPTR GCBaseAddr, uint32_t cbModule));
4922
4923	/**
4924	* Query the state of a page in a shared module
4925	*
4926	* @returns VBox status code.
4927	* @param pDevIns The device instance.
4928	* @param GCPtrPage Page address.
4929	* @param pfShared Shared status (out).
4930	* @param pfPageFlags Page flags (out).
4931	*/
4932	DECLR3CALLBACKMEMBER(int, pfnSharedModuleGetPageState, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags));
4933
4934	/**
4935	* Check all registered modules for changes.
4936	*
4937	* @returns VBox status code.
4938	* @param pDevIns The device instance.
4939	*/
4940	DECLR3CALLBACKMEMBER(int, pfnSharedModuleCheckAll,(PPDMDEVINS pDevIns));
4941
4942	/**
4943	* Query the interface of the top level driver on a LUN.
4944	*
4945	* @returns VBox status code.
4946	* @param pDevIns The device instance.
4947	* @param pszDevice Device name.
4948	* @param iInstance Device instance.
4949	* @param iLun The Logical Unit to obtain the interface of.
4950	* @param ppBase Where to store the base interface pointer.
4951	*
4952	* @remark We're not doing any locking ATM, so don't try call this at times when the
4953	* device chain is known to be updated.
4954	*/
4955	DECLR3CALLBACKMEMBER(int, pfnQueryLun,(PPDMDEVINS pDevIns, const char *pszDevice, unsigned iInstance, unsigned iLun, PPPDMIBASE ppBase));
4956
4957	/** @} */
4958
4959	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4960	uint32_t u32TheEnd;
4961	} PDMDEVHLPR3;
4962	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4963	/** Pointer to the R3 PDM Device API. */
4964	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4965	/** Pointer to the R3 PDM Device API, const variant. */
4966	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4967
4968
4969	/**
4970	* PDM Device API - RC Variant.
4971	*/
4972	typedef struct PDMDEVHLPRC
4973	{
4974	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4975	uint32_t u32Version;
4976
4977	/**
4978	* Sets up raw-mode context callback handlers for an I/O port range.
4979	*
4980	* The range must have been registered in ring-3 first using
4981	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4982	*
4983	* @returns VBox status.
4984	* @param pDevIns The device instance to register the ports with.
4985	* @param hIoPorts The I/O port range handle.
4986	* @param pfnOut Pointer to function which is gonna handle OUT
4987	* operations. Optional.
4988	* @param pfnIn Pointer to function which is gonna handle IN operations.
4989	* Optional.
4990	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4991	* operations. Optional.
4992	* @param pfnInStr Pointer to function which is gonna handle string IN
4993	* operations. Optional.
4994	* @param pvUser User argument to pass to the callbacks.
4995	*
4996	* @remarks Caller enters the device critical section prior to invoking the
4997	* registered callback methods.
4998	*
4999	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
5000	* PDMDevHlpIoPortUnmap.
5001	*/
5002	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5003	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5004	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5005	void *pvUser));
5006
5007	/**
5008	* Sets up raw-mode context callback handlers for an MMIO region.
5009	*
5010	* The region must have been registered in ring-3 first using
5011	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
5012	*
5013	* @returns VBox status.
5014	* @param pDevIns The device instance to register the ports with.
5015	* @param hRegion The MMIO region handle.
5016	* @param pfnWrite Pointer to function which is gonna handle Write
5017	* operations.
5018	* @param pfnRead Pointer to function which is gonna handle Read
5019	* operations.
5020	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5021	* operations. (optional)
5022	* @param pvUser User argument to pass to the callbacks.
5023	*
5024	* @remarks Caller enters the device critical section prior to invoking the
5025	* registered callback methods.
5026	*
5027	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
5028	* PDMDevHlpMmioUnmap.
5029	*/
5030	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5031	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5032
5033	/**
5034	* Sets up a raw-mode mapping for an MMIO2 region.
5035	*
5036	* The region must have been created in ring-3 first using
5037	* PDMDevHlpMmio2Create().
5038	*
5039	* @returns VBox status.
5040	* @param pDevIns The device instance to register the ports with.
5041	* @param hRegion The MMIO2 region handle.
5042	* @param offSub Start of what to map into raw-mode. Must be page aligned.
5043	* @param cbSub Number of bytes to map into raw-mode. Must be page
5044	* aligned. Zero is an alias for everything.
5045	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5046	* @thread EMT(0)
5047	* @note Only available at VM creation time.
5048	*
5049	* @sa PDMDevHlpMmio2Create().
5050	*/
5051	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
5052	size_t offSub, size_t cbSub, void **ppvMapping));
5053
5054	/**
5055	* Bus master physical memory read from the given PCI device.
5056	*
5057	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
5058	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
5059	* @param pDevIns The device instance.
5060	* @param pPciDev The PCI device structure. If NULL the default
5061	* PCI device for this device instance is used.
5062	* @param GCPhys Physical address start reading from.
5063	* @param pvBuf Where to put the read bits.
5064	* @param cbRead How many bytes to read.
5065	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5066	* @thread Any thread, but the call may involve the emulation thread.
5067	*/
5068	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5069	void *pvBuf, size_t cbRead, uint32_t fFlags));
5070
5071	/**
5072	* Bus master physical memory write from the given PCI device.
5073	*
5074	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
5075	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
5076	* @param pDevIns The device instance.
5077	* @param pPciDev The PCI device structure. If NULL the default
5078	* PCI device for this device instance is used.
5079	* @param GCPhys Physical address to write to.
5080	* @param pvBuf What to write.
5081	* @param cbWrite How many bytes to write.
5082	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5083	* @thread Any thread, but the call may involve the emulation thread.
5084	*/
5085	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5086	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5087
5088	/**
5089	* Set the IRQ for the given PCI device.
5090	*
5091	* @param pDevIns Device instance.
5092	* @param pPciDev The PCI device structure. If NULL the default
5093	* PCI device for this device instance is used.
5094	* @param iIrq IRQ number to set.
5095	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5096	* @thread Any thread, but will involve the emulation thread.
5097	*/
5098	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5099
5100	/**
5101	* Set ISA IRQ for a device.
5102	*
5103	* @param pDevIns Device instance.
5104	* @param iIrq IRQ number to set.
5105	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5106	* @thread Any thread, but will involve the emulation thread.
5107	*/
5108	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5109
5110	/**
5111	* Read physical memory.
5112	*
5113	* @returns VINF_SUCCESS (for now).
5114	* @param pDevIns Device instance.
5115	* @param GCPhys Physical address start reading from.
5116	* @param pvBuf Where to put the read bits.
5117	* @param cbRead How many bytes to read.
5118	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5119	*/
5120	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5121
5122	/**
5123	* Write to physical memory.
5124	*
5125	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5126	* @param pDevIns Device instance.
5127	* @param GCPhys Physical address to write to.
5128	* @param pvBuf What to write.
5129	* @param cbWrite How many bytes to write.
5130	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5131	*/
5132	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5133
5134	/**
5135	* Checks if the Gate A20 is enabled or not.
5136	*
5137	* @returns true if A20 is enabled.
5138	* @returns false if A20 is disabled.
5139	* @param pDevIns Device instance.
5140	* @thread The emulation thread.
5141	*/
5142	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5143
5144	/**
5145	* Gets the VM state.
5146	*
5147	* @returns VM state.
5148	* @param pDevIns The device instance.
5149	* @thread Any thread (just keep in mind that it's volatile info).
5150	*/
5151	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5152
5153	/**
5154	* Gets the VM handle. Restricted API.
5155	*
5156	* @returns VM Handle.
5157	* @param pDevIns Device instance.
5158	*/
5159	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5160
5161	/**
5162	* Gets the VMCPU handle. Restricted API.
5163	*
5164	* @returns VMCPU Handle.
5165	* @param pDevIns The device instance.
5166	*/
5167	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5168
5169	/**
5170	* The the VM CPU ID of the current thread (restricted API).
5171	*
5172	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5173	* @param pDevIns The device instance.
5174	*/
5175	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5176
5177	/**
5178	* Get the current virtual clock time in a VM. The clock frequency must be
5179	* queried separately.
5180	*
5181	* @returns Current clock time.
5182	* @param pDevIns The device instance.
5183	*/
5184	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5185
5186	/**
5187	* Get the frequency of the virtual clock.
5188	*
5189	* @returns The clock frequency (not variable at run-time).
5190	* @param pDevIns The device instance.
5191	*/
5192	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5193
5194	/**
5195	* Get the current virtual clock time in a VM, in nanoseconds.
5196	*
5197	* @returns Current clock time (in ns).
5198	* @param pDevIns The device instance.
5199	*/
5200	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5201
5202	/**
5203	* Gets the NOP critical section.
5204	*
5205	* @returns The ring-3 address of the NOP critical section.
5206	* @param pDevIns The device instance.
5207	*/
5208	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5209
5210	/**
5211	* Changes the device level critical section from the automatically created
5212	* default to one desired by the device constructor.
5213	*
5214	* Must first be done in ring-3.
5215	*
5216	* @returns VBox status code.
5217	* @param pDevIns The device instance.
5218	* @param pCritSect The critical section to use. NULL is not
5219	* valid, instead use the NOP critical
5220	* section.
5221	*/
5222	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5223
5224	/** @name Exported PDM Critical Section Functions
5225	* @{ */
5226	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5227	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5228	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5229	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5230	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5231	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5232	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5233	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5234	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5235	/** @} */
5236
5237	/** @name Exported PDM Read/Write Critical Section Functions
5238	* @{ */
5239	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5240	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5241	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5242	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5243	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5244
5245	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5246	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5247	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5248	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5249	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5250
5251	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5252	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5253	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5254	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5255	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5256	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5257	/** @} */
5258
5259	/**
5260	* Gets the trace buffer handle.
5261	*
5262	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5263	* really inteded for direct usage, thus no inline wrapper function.
5264	*
5265	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5266	* @param pDevIns The device instance.
5267	*/
5268	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5269
5270	/**
5271	* Sets up the PCI bus for the raw-mode context.
5272	*
5273	* This must be called after ring-3 has registered the PCI bus using
5274	* PDMDevHlpPCIBusRegister().
5275	*
5276	* @returns VBox status code.
5277	* @param pDevIns The device instance.
5278	* @param pPciBusReg The PCI bus registration information for raw-mode,
5279	* considered volatile.
5280	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
5281	*/
5282	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
5283
5284	/**
5285	* Sets up the IOMMU for the raw-mode context.
5286	*
5287	* This must be called after ring-3 has registered the IOMMU using
5288	* PDMDevHlpIommuRegister().
5289	*
5290	* @returns VBox status code.
5291	* @param pDevIns The device instance.
5292	* @param pIommuReg The IOMMU registration information for raw-mode,
5293	* considered volatile.
5294	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
5295	*/
5296	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
5297
5298	/**
5299	* Sets up the PIC for the ring-0 context.
5300	*
5301	* This must be called after ring-3 has registered the PIC using
5302	* PDMDevHlpPICRegister().
5303	*
5304	* @returns VBox status code.
5305	* @param pDevIns The device instance.
5306	* @param pPicReg The PIC registration information for ring-0,
5307	* considered volatile and copied.
5308	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5309	*/
5310	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5311
5312	/**
5313	* Sets up the APIC for the raw-mode context.
5314	*
5315	* This must be called after ring-3 has registered the APIC using
5316	* PDMDevHlpApicRegister().
5317	*
5318	* @returns VBox status code.
5319	* @param pDevIns The device instance.
5320	*/
5321	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5322
5323	/**
5324	* Sets up the IOAPIC for the ring-0 context.
5325	*
5326	* This must be called after ring-3 has registered the PIC using
5327	* PDMDevHlpIoApicRegister().
5328	*
5329	* @returns VBox status code.
5330	* @param pDevIns The device instance.
5331	* @param pIoApicReg The PIC registration information for ring-0,
5332	* considered volatile and copied.
5333	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5334	*/
5335	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5336
5337	/**
5338	* Sets up the HPET for the raw-mode context.
5339	*
5340	* This must be called after ring-3 has registered the PIC using
5341	* PDMDevHlpHpetRegister().
5342	*
5343	* @returns VBox status code.
5344	* @param pDevIns The device instance.
5345	* @param pHpetReg The PIC registration information for raw-mode,
5346	* considered volatile and copied.
5347	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
5348	*/
5349	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
5350
5351	/** Space reserved for future members.
5352	* @{ */
5353	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
5354	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
5355	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
5356	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
5357	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
5358	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
5359	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
5360	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
5361	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
5362	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
5363	/** @} */
5364
5365	/** Just a safety precaution. */
5366	uint32_t u32TheEnd;
5367	} PDMDEVHLPRC;
5368	/** Pointer PDM Device RC API. */
5369	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
5370	/** Pointer PDM Device RC API. */
5371	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
5372
5373	/** Current PDMDEVHLP version number. */
5374	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 18, 0)
5375
5376
5377	/**
5378	* PDM Device API - R0 Variant.
5379	*/
5380	typedef struct PDMDEVHLPR0
5381	{
5382	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5383	uint32_t u32Version;
5384
5385	/**
5386	* Sets up ring-0 callback handlers for an I/O port range.
5387	*
5388	* The range must have been created in ring-3 first using
5389	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5390	*
5391	* @returns VBox status.
5392	* @param pDevIns The device instance to register the ports with.
5393	* @param hIoPorts The I/O port range handle.
5394	* @param pfnOut Pointer to function which is gonna handle OUT
5395	* operations. Optional.
5396	* @param pfnIn Pointer to function which is gonna handle IN operations.
5397	* Optional.
5398	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5399	* operations. Optional.
5400	* @param pfnInStr Pointer to function which is gonna handle string IN
5401	* operations. Optional.
5402	* @param pvUser User argument to pass to the callbacks.
5403	*
5404	* @remarks Caller enters the device critical section prior to invoking the
5405	* registered callback methods.
5406	*
5407	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5408	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5409	*/
5410	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5411	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5412	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5413	void *pvUser));
5414
5415	/**
5416	* Sets up ring-0 callback handlers for an MMIO region.
5417	*
5418	* The region must have been created in ring-3 first using
5419	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5420	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5421	*
5422	* @returns VBox status.
5423	* @param pDevIns The device instance to register the ports with.
5424	* @param hRegion The MMIO region handle.
5425	* @param pfnWrite Pointer to function which is gonna handle Write
5426	* operations.
5427	* @param pfnRead Pointer to function which is gonna handle Read
5428	* operations.
5429	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5430	* operations. (optional)
5431	* @param pvUser User argument to pass to the callbacks.
5432	*
5433	* @remarks Caller enters the device critical section prior to invoking the
5434	* registered callback methods.
5435	*
5436	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5437	* PDMDevHlpMmioUnmap().
5438	*/
5439	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5440	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5441
5442	/**
5443	* Sets up a ring-0 mapping for an MMIO2 region.
5444	*
5445	* The region must have been created in ring-3 first using
5446	* PDMDevHlpMmio2Create().
5447	*
5448	* @returns VBox status.
5449	* @param pDevIns The device instance to register the ports with.
5450	* @param hRegion The MMIO2 region handle.
5451	* @param offSub Start of what to map into ring-0. Must be page aligned.
5452	* @param cbSub Number of bytes to map into ring-0. Must be page
5453	* aligned. Zero is an alias for everything.
5454	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5455	*
5456	* @thread EMT(0)
5457	* @note Only available at VM creation time.
5458	*
5459	* @sa PDMDevHlpMmio2Create().
5460	*/
5461	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5462	void **ppvMapping));
5463
5464	/**
5465	* Bus master physical memory read from the given PCI device.
5466	*
5467	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5468	* VERR_EM_MEMORY.
5469	* @param pDevIns The device instance.
5470	* @param pPciDev The PCI device structure. If NULL the default
5471	* PCI device for this device instance is used.
5472	* @param GCPhys Physical address start reading from.
5473	* @param pvBuf Where to put the read bits.
5474	* @param cbRead How many bytes to read.
5475	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5476	* @thread Any thread, but the call may involve the emulation thread.
5477	*/
5478	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5479	void *pvBuf, size_t cbRead, uint32_t fFlags));
5480
5481	/**
5482	* Bus master physical memory write from the given PCI device.
5483	*
5484	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5485	* VERR_EM_MEMORY.
5486	* @param pDevIns The device instance.
5487	* @param pPciDev The PCI device structure. If NULL the default
5488	* PCI device for this device instance is used.
5489	* @param GCPhys Physical address to write to.
5490	* @param pvBuf What to write.
5491	* @param cbWrite How many bytes to write.
5492	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5493	* @thread Any thread, but the call may involve the emulation thread.
5494	*/
5495	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5496	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5497
5498	/**
5499	* Set the IRQ for the given PCI device.
5500	*
5501	* @param pDevIns Device instance.
5502	* @param pPciDev The PCI device structure. If NULL the default
5503	* PCI device for this device instance is used.
5504	* @param iIrq IRQ number to set.
5505	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5506	* @thread Any thread, but will involve the emulation thread.
5507	*/
5508	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5509
5510	/**
5511	* Set ISA IRQ for a device.
5512	*
5513	* @param pDevIns Device instance.
5514	* @param iIrq IRQ number to set.
5515	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5516	* @thread Any thread, but will involve the emulation thread.
5517	*/
5518	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5519
5520	/**
5521	* Read physical memory.
5522	*
5523	* @returns VINF_SUCCESS (for now).
5524	* @param pDevIns Device instance.
5525	* @param GCPhys Physical address start reading from.
5526	* @param pvBuf Where to put the read bits.
5527	* @param cbRead How many bytes to read.
5528	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5529	*/
5530	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5531
5532	/**
5533	* Write to physical memory.
5534	*
5535	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5536	* @param pDevIns Device instance.
5537	* @param GCPhys Physical address to write to.
5538	* @param pvBuf What to write.
5539	* @param cbWrite How many bytes to write.
5540	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5541	*/
5542	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5543
5544	/**
5545	* Checks if the Gate A20 is enabled or not.
5546	*
5547	* @returns true if A20 is enabled.
5548	* @returns false if A20 is disabled.
5549	* @param pDevIns Device instance.
5550	* @thread The emulation thread.
5551	*/
5552	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5553
5554	/**
5555	* Gets the VM state.
5556	*
5557	* @returns VM state.
5558	* @param pDevIns The device instance.
5559	* @thread Any thread (just keep in mind that it's volatile info).
5560	*/
5561	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5562
5563	/**
5564	* Gets the VM handle. Restricted API.
5565	*
5566	* @returns VM Handle.
5567	* @param pDevIns Device instance.
5568	*/
5569	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5570
5571	/**
5572	* Gets the VMCPU handle. Restricted API.
5573	*
5574	* @returns VMCPU Handle.
5575	* @param pDevIns The device instance.
5576	*/
5577	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5578
5579	/**
5580	* The the VM CPU ID of the current thread (restricted API).
5581	*
5582	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5583	* @param pDevIns The device instance.
5584	*/
5585	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5586
5587	/** @name Timer handle method wrappers
5588	* @{ */
5589	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5590	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5591	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5592	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5593	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5594	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5595	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5596	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5597	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5598	/** Takes the clock lock then enters the specified critical section. */
5599	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5600	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5601	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5602	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5603	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5604	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5605	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5606	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5607	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5608	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5609	/** @} */
5610
5611	/**
5612	* Get the current virtual clock time in a VM. The clock frequency must be
5613	* queried separately.
5614	*
5615	* @returns Current clock time.
5616	* @param pDevIns The device instance.
5617	*/
5618	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5619
5620	/**
5621	* Get the frequency of the virtual clock.
5622	*
5623	* @returns The clock frequency (not variable at run-time).
5624	* @param pDevIns The device instance.
5625	*/
5626	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5627
5628	/**
5629	* Get the current virtual clock time in a VM, in nanoseconds.
5630	*
5631	* @returns Current clock time (in ns).
5632	* @param pDevIns The device instance.
5633	*/
5634	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5635
5636	/** @name Exported PDM Queue Functions
5637	* @{ */
5638	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5639	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5640	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5641	/** @} */
5642
5643	/** @name PDM Task
5644	* @{ */
5645	/**
5646	* Triggers the running the given task.
5647	*
5648	* @returns VBox status code.
5649	* @retval VINF_ALREADY_POSTED is the task is already pending.
5650	* @param pDevIns The device instance.
5651	* @param hTask The task to trigger.
5652	* @thread Any thread.
5653	*/
5654	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5655	/** @} */
5656
5657	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5658	* These semaphores can be signalled from ring-0.
5659	* @{ */
5660	/** @sa SUPSemEventSignal */
5661	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5662	/** @sa SUPSemEventWaitNoResume */
5663	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5664	/** @sa SUPSemEventWaitNsAbsIntr */
5665	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5666	/** @sa SUPSemEventWaitNsRelIntr */
5667	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5668	/** @sa SUPSemEventGetResolution */
5669	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5670	/** @} */
5671
5672	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5673	* These semaphores can be signalled from ring-0.
5674	* @{ */
5675	/** @sa SUPSemEventMultiSignal */
5676	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5677	/** @sa SUPSemEventMultiReset */
5678	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5679	/** @sa SUPSemEventMultiWaitNoResume */
5680	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5681	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5682	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5683	/** @sa SUPSemEventMultiWaitNsRelIntr */
5684	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5685	/** @sa SUPSemEventMultiGetResolution */
5686	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5687	/** @} */
5688
5689	/**
5690	* Gets the NOP critical section.
5691	*
5692	* @returns The ring-3 address of the NOP critical section.
5693	* @param pDevIns The device instance.
5694	*/
5695	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5696
5697	/**
5698	* Changes the device level critical section from the automatically created
5699	* default to one desired by the device constructor.
5700	*
5701	* Must first be done in ring-3.
5702	*
5703	* @returns VBox status code.
5704	* @param pDevIns The device instance.
5705	* @param pCritSect The critical section to use. NULL is not
5706	* valid, instead use the NOP critical
5707	* section.
5708	*/
5709	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5710
5711	/** @name Exported PDM Critical Section Functions
5712	* @{ */
5713	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5714	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5715	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5716	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5717	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5718	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5719	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5720	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5721	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5722	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5723	/** @} */
5724
5725	/** @name Exported PDM Read/Write Critical Section Functions
5726	* @{ */
5727	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5728	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5729	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5730	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5731	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5732
5733	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5734	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5735	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5736	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5737	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5738
5739	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5740	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5741	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5742	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5743	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5744	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5745	/** @} */
5746
5747	/**
5748	* Gets the trace buffer handle.
5749	*
5750	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5751	* really inteded for direct usage, thus no inline wrapper function.
5752	*
5753	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5754	* @param pDevIns The device instance.
5755	*/
5756	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5757
5758	/**
5759	* Sets up the PCI bus for the ring-0 context.
5760	*
5761	* This must be called after ring-3 has registered the PCI bus using
5762	* PDMDevHlpPCIBusRegister().
5763	*
5764	* @returns VBox status code.
5765	* @param pDevIns The device instance.
5766	* @param pPciBusReg The PCI bus registration information for ring-0,
5767	* considered volatile and copied.
5768	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5769	*/
5770	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5771
5772	/**
5773	* Sets up the IOMMU for the ring-0 context.
5774	*
5775	* This must be called after ring-3 has registered the IOMMU using
5776	* PDMDevHlpIommuRegister().
5777	*
5778	* @returns VBox status code.
5779	* @param pDevIns The device instance.
5780	* @param pIommuReg The IOMMU registration information for ring-0,
5781	* considered volatile and copied.
5782	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5783	*/
5784	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5785
5786	/**
5787	* Sets up the PIC for the ring-0 context.
5788	*
5789	* This must be called after ring-3 has registered the PIC using
5790	* PDMDevHlpPICRegister().
5791	*
5792	* @returns VBox status code.
5793	* @param pDevIns The device instance.
5794	* @param pPicReg The PIC registration information for ring-0,
5795	* considered volatile and copied.
5796	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5797	*/
5798	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5799
5800	/**
5801	* Sets up the APIC for the ring-0 context.
5802	*
5803	* This must be called after ring-3 has registered the APIC using
5804	* PDMDevHlpApicRegister().
5805	*
5806	* @returns VBox status code.
5807	* @param pDevIns The device instance.
5808	*/
5809	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5810
5811	/**
5812	* Sets up the IOAPIC for the ring-0 context.
5813	*
5814	* This must be called after ring-3 has registered the PIC using
5815	* PDMDevHlpIoApicRegister().
5816	*
5817	* @returns VBox status code.
5818	* @param pDevIns The device instance.
5819	* @param pIoApicReg The PIC registration information for ring-0,
5820	* considered volatile and copied.
5821	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5822	*/
5823	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5824
5825	/**
5826	* Sets up the HPET for the ring-0 context.
5827	*
5828	* This must be called after ring-3 has registered the PIC using
5829	* PDMDevHlpHpetRegister().
5830	*
5831	* @returns VBox status code.
5832	* @param pDevIns The device instance.
5833	* @param pHpetReg The PIC registration information for ring-0,
5834	* considered volatile and copied.
5835	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5836	*/
5837	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5838
5839	/**
5840	* Temporarily turns off the access monitoring of a page within a monitored
5841	* physical write/all page access handler region.
5842	*
5843	* Use this when no further \#PFs are required for that page. Be aware that
5844	* a page directory sync might reset the flags, and turn on access monitoring
5845	* for the page.
5846	*
5847	* The caller must do required page table modifications.
5848	*
5849	* @returns VBox status code.
5850	* @param pDevIns The device instance.
5851	* @param GCPhys The start address of the access handler. This
5852	* must be a fully page aligned range or we risk
5853	* messing up other handlers installed for the
5854	* start and end pages.
5855	* @param GCPhysPage The physical address of the page to turn off
5856	* access monitoring for.
5857	*/
5858	DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
5859
5860	/**
5861	* Mapping an MMIO2 page in place of an MMIO page for direct access.
5862	*
5863	* This is a special optimization used by the VGA device. Call
5864	* PDMDevHlpMmioResetRegion() to undo the mapping.
5865	*
5866	* @returns VBox status code. This API may return VINF_SUCCESS even if no
5867	* remapping is made.
5868	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
5869	*
5870	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
5871	* associated with.
5872	* @param hRegion The handle to the MMIO region.
5873	* @param offRegion The offset into @a hRegion of the page to be
5874	* remapped.
5875	* @param hMmio2 The MMIO2 handle.
5876	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
5877	* mapping.
5878	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
5879	* for the time being.
5880	*/
5881	DECLR0CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
5882	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
5883
5884	/**
5885	* Reset a previously modified MMIO region; restore the access flags.
5886	*
5887	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
5888	* intended for some ancient VGA hack. However, it would be great to extend it
5889	* beyond VT-x and/or nested-paging.
5890	*
5891	* @returns VBox status code.
5892	*
5893	* @param pDevIns The device instance @a hRegion is associated with.
5894	* @param hRegion The handle to the MMIO region.
5895	*/
5896	DECLR0CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
5897
5898	/** Space reserved for future members.
5899	* @{ */
5900	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5901	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5902	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5903	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5904	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5905	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5906	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5907	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5908	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5909	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5910	/** @} */
5911
5912	/** Just a safety precaution. */
5913	uint32_t u32TheEnd;
5914	} PDMDEVHLPR0;
5915	/** Pointer PDM Device R0 API. */
5916	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5917	/** Pointer PDM Device GC API. */
5918	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5919
5920	/** Current PDMDEVHLP version number. */
5921	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 24, 0)
5922
5923
5924	/**
5925	* PDM Device Instance.
5926	*/
5927	typedef struct PDMDEVINSR3
5928	{
5929	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5930	uint32_t u32Version;
5931	/** Device instance number. */
5932	uint32_t iInstance;
5933	/** Size of the ring-3, raw-mode and shared bits. */
5934	uint32_t cbRing3;
5935	/** Set if ring-0 context is enabled. */
5936	bool fR0Enabled;
5937	/** Set if raw-mode context is enabled. */
5938	bool fRCEnabled;
5939	/** Alignment padding. */
5940	bool afReserved[2];
5941	/** Pointer the HC PDM Device API. */
5942	PCPDMDEVHLPR3 pHlpR3;
5943	/** Pointer to the shared device instance data. */
5944	RTR3PTR pvInstanceDataR3;
5945	/** Pointer to the device instance data for ring-3. */
5946	RTR3PTR pvInstanceDataForR3;
5947	/** The critical section for the device.
5948	*
5949	* TM and IOM will enter this critical section before calling into the device
5950	* code. PDM will when doing power on, power off, reset, suspend and resume
5951	* notifications. SSM will currently not, but this will be changed later on.
5952	*
5953	* The device gets a critical section automatically assigned to it before
5954	* the constructor is called. If the constructor wishes to use a different
5955	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5956	* very early on.
5957	*/
5958	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5959	/** Pointer to device registration structure. */
5960	R3PTRTYPE(PCPDMDEVREG) pReg;
5961	/** Configuration handle. */
5962	R3PTRTYPE(PCFGMNODE) pCfg;
5963	/** The base interface of the device.
5964	*
5965	* The device constructor initializes this if it has any
5966	* device level interfaces to export. To obtain this interface
5967	* call PDMR3QueryDevice(). */
5968	PDMIBASE IBase;
5969
5970	/** Tracing indicator. */
5971	uint32_t fTracing;
5972	/** The tracing ID of this device. */
5973	uint32_t idTracing;
5974
5975	/** Ring-3 pointer to the raw-mode device instance. */
5976	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5977	/** Raw-mode address of the raw-mode device instance. */
5978	RTRGPTR pDevInsForRC;
5979	/** Ring-3 pointer to the raw-mode instance data. */
5980	RTR3PTR pvInstanceDataForRCR3;
5981
5982	/** PCI device structure size. */
5983	uint32_t cbPciDev;
5984	/** Number of PCI devices in apPciDevs. */
5985	uint32_t cPciDevs;
5986	/** Pointer to the PCI devices for this device.
5987	* (Allocated after the shared instance data.)
5988	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5989	* two devices ever needing it can use cbPciDev and do the address
5990	* calculations that for entries 8+. */
5991	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5992
5993	/** Temporarily. */
5994	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5995	/** Temporarily. */
5996	RTR0PTR pvInstanceDataR0;
5997	/** Temporarily. */
5998	RTRCPTR pvInstanceDataRC;
5999	/** Align the internal data more naturally. */
6000	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
6001
6002	/** Internal data. */
6003	union
6004	{
6005	#ifdef PDMDEVINSINT_DECLARED
6006	PDMDEVINSINTR3 s;
6007	#endif
6008	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
6009	} Internal;
6010
6011	/** Device instance data for ring-3. The size of this area is defined
6012	* in the PDMDEVREG::cbInstanceR3 field. */
6013	char achInstanceData[8];
6014	} PDMDEVINSR3;
6015
6016	/** Current PDMDEVINSR3 version number. */
6017	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
6018
6019	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
6020	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
6021
6022
6023	/**
6024	* PDM ring-0 device instance.
6025	*/
6026	typedef struct PDMDEVINSR0
6027	{
6028	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
6029	uint32_t u32Version;
6030	/** Device instance number. */
6031	uint32_t iInstance;
6032
6033	/** Pointer the HC PDM Device API. */
6034	PCPDMDEVHLPR0 pHlpR0;
6035	/** Pointer to the shared device instance data. */
6036	RTR0PTR pvInstanceDataR0;
6037	/** Pointer to the device instance data for ring-0. */
6038	RTR0PTR pvInstanceDataForR0;
6039	/** The critical section for the device.
6040	*
6041	* TM and IOM will enter this critical section before calling into the device
6042	* code. PDM will when doing power on, power off, reset, suspend and resume
6043	* notifications. SSM will currently not, but this will be changed later on.
6044	*
6045	* The device gets a critical section automatically assigned to it before
6046	* the constructor is called. If the constructor wishes to use a different
6047	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6048	* very early on.
6049	*/
6050	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
6051	/** Pointer to the ring-0 device registration structure. */
6052	R0PTRTYPE(PCPDMDEVREGR0) pReg;
6053	/** Ring-3 address of the ring-3 device instance. */
6054	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
6055	/** Ring-0 pointer to the ring-3 device instance. */
6056	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
6057	/** Ring-0 pointer to the ring-3 instance data. */
6058	RTR0PTR pvInstanceDataForR3R0;
6059	/** Raw-mode address of the raw-mode device instance. */
6060	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
6061	/** Ring-0 pointer to the raw-mode device instance. */
6062	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
6063	/** Ring-0 pointer to the raw-mode instance data. */
6064	RTR0PTR pvInstanceDataForRCR0;
6065
6066	/** PCI device structure size. */
6067	uint32_t cbPciDev;
6068	/** Number of PCI devices in apPciDevs. */
6069	uint32_t cPciDevs;
6070	/** Pointer to the PCI devices for this device.
6071	* (Allocated after the shared instance data.)
6072	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6073	* two devices ever needing it can use cbPciDev and do the address
6074	* calculations that for entries 8+. */
6075	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6076
6077	/** Align the internal data more naturally. */
6078	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
6079
6080	/** Internal data. */
6081	union
6082	{
6083	#ifdef PDMDEVINSINT_DECLARED
6084	PDMDEVINSINTR0 s;
6085	#endif
6086	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
6087	} Internal;
6088
6089	/** Device instance data for ring-0. The size of this area is defined
6090	* in the PDMDEVREG::cbInstanceR0 field. */
6091	char achInstanceData[8];
6092	} PDMDEVINSR0;
6093
6094	/** Current PDMDEVINSR0 version number. */
6095	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
6096
6097
6098	/**
6099	* PDM raw-mode device instance.
6100	*/
6101	typedef struct PDMDEVINSRC
6102	{
6103	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
6104	uint32_t u32Version;
6105	/** Device instance number. */
6106	uint32_t iInstance;
6107
6108	/** Pointer the HC PDM Device API. */
6109	PCPDMDEVHLPRC pHlpRC;
6110	/** Pointer to the shared device instance data. */
6111	RTRGPTR pvInstanceDataRC;
6112	/** Pointer to the device instance data for raw-mode. */
6113	RTRGPTR pvInstanceDataForRC;
6114	/** The critical section for the device.
6115	*
6116	* TM and IOM will enter this critical section before calling into the device
6117	* code. PDM will when doing power on, power off, reset, suspend and resume
6118	* notifications. SSM will currently not, but this will be changed later on.
6119	*
6120	* The device gets a critical section automatically assigned to it before
6121	* the constructor is called. If the constructor wishes to use a different
6122	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6123	* very early on.
6124	*/
6125	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
6126	/** Pointer to the raw-mode device registration structure. */
6127	RGPTRTYPE(PCPDMDEVREGRC) pReg;
6128
6129	/** PCI device structure size. */
6130	uint32_t cbPciDev;
6131	/** Number of PCI devices in apPciDevs. */
6132	uint32_t cPciDevs;
6133	/** Pointer to the PCI devices for this device.
6134	* (Allocated after the shared instance data.) */
6135	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6136
6137	/** Align the internal data more naturally. */
6138	uint32_t au32Padding[14];
6139
6140	/** Internal data. */
6141	union
6142	{
6143	#ifdef PDMDEVINSINT_DECLARED
6144	PDMDEVINSINTRC s;
6145	#endif
6146	uint8_t padding[0x10];
6147	} Internal;
6148
6149	/** Device instance data for ring-0. The size of this area is defined
6150	* in the PDMDEVREG::cbInstanceR0 field. */
6151	char achInstanceData[8];
6152	} PDMDEVINSRC;
6153
6154	/** Current PDMDEVINSR0 version number. */
6155	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
6156
6157
6158	/** @def PDM_DEVINS_VERSION
6159	* Current PDMDEVINS version number. */
6160	/** @typedef PDMDEVINS
6161	* The device instance structure for the current context. */
6162	#ifdef IN_RING3
6163	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
6164	typedef PDMDEVINSR3 PDMDEVINS;
6165	#elif defined(IN_RING0)
6166	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
6167	typedef PDMDEVINSR0 PDMDEVINS;
6168	#elif defined(IN_RC)
6169	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
6170	typedef PDMDEVINSRC PDMDEVINS;
6171	#else
6172	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
6173	#endif
6174
6175	/**
6176	* Get the pointer to an PCI device.
6177	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6178	*/
6179	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
6180	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
6181	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
6182
6183	/**
6184	* Calc the pointer to of a given PCI device.
6185	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6186	*/
6187	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
6188	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
6189	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
6190	: (PPDMPCIDEV)NULL )
6191
6192
6193	/**
6194	* Checks the structure versions of the device instance and device helpers,
6195	* returning if they are incompatible.
6196	*
6197	* This is for use in the constructor.
6198	*
6199	* @param pDevIns The device instance pointer.
6200	*/
6201	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
6202	do \
6203	{ \
6204	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6205	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6206	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6207	VERR_PDM_DEVINS_VERSION_MISMATCH); \
6208	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6209	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6210	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
6211	} while (0)
6212
6213	/**
6214	* Quietly checks the structure versions of the device instance and device
6215	* helpers, returning if they are incompatible.
6216	*
6217	* This is for use in the destructor.
6218	*
6219	* @param pDevIns The device instance pointer.
6220	*/
6221	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
6222	do \
6223	{ \
6224	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6225	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
6226	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
6227	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
6228	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
6229	} while (0)
6230
6231	/**
6232	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
6233	* constructor - returns on failure.
6234	*
6235	* This should be invoked after having initialized the instance data
6236	* sufficiently for the correct operation of the destructor. The destructor is
6237	* always called!
6238	*
6239	* @param pDevIns Pointer to the PDM device instance.
6240	* @param pszValidValues Patterns describing the valid value names. See
6241	* RTStrSimplePatternMultiMatch for details on the
6242	* pattern syntax.
6243	* @param pszValidNodes Patterns describing the valid node (key) names.
6244	* Pass empty string if no valid nodes.
6245	*/
6246	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
6247	do \
6248	{ \
6249	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
6250	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
6251	if (RT_SUCCESS(rcValCfg)) \
6252	{ /* likely */ } else return rcValCfg; \
6253	} while (0)
6254
6255	/** @def PDMDEV_ASSERT_EMT
6256	* Assert that the current thread is the emulation thread.
6257	*/
6258	#ifdef VBOX_STRICT
6259	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6260	#else
6261	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
6262	#endif
6263
6264	/** @def PDMDEV_ASSERT_OTHER
6265	* Assert that the current thread is NOT the emulation thread.
6266	*/
6267	#ifdef VBOX_STRICT
6268	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6269	#else
6270	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
6271	#endif
6272
6273	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
6274	* Assert that the current thread is owner of the VM lock.
6275	*/
6276	#ifdef VBOX_STRICT
6277	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6278	#else
6279	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
6280	#endif
6281
6282	/** @def PDMDEV_SET_ERROR
6283	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
6284	*/
6285	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
6286	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
6287
6288	/** @def PDMDEV_SET_RUNTIME_ERROR
6289	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
6290	*/
6291	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
6292	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
6293
6294	/** @def PDMDEVINS_2_RCPTR
6295	* Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
6296	*/
6297	#ifdef IN_RC
6298	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
6299	#else
6300	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
6301	#endif
6302
6303	/** @def PDMDEVINS_2_R3PTR
6304	* Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
6305	*/
6306	#ifdef IN_RING3
6307	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
6308	#else
6309	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
6310	#endif
6311
6312	/** @def PDMDEVINS_2_R0PTR
6313	* Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
6314	*/
6315	#ifdef IN_RING0
6316	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
6317	#else
6318	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
6319	#endif
6320
6321	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
6322	* Converts a PDM device instance data pointer to a ring-0 one.
6323	* @deprecated
6324	*/
6325	#ifdef IN_RING0
6326	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
6327	#else
6328	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
6329	#endif
6330
6331
6332	/** @def PDMDEVINS_2_DATA
6333	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
6334	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
6335	*
6336	* @note Do no use this macro in common code working on a core structure which
6337	* device specific code has expanded.
6338	*/
6339	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6340	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
6341	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6342	{ \
6343	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
6344	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
6345	return pLambdaRet; \
6346	}(a_pDevIns))
6347	#else
6348	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
6349	#endif
6350
6351	/** @def PDMDEVINS_2_DATA_CC
6352	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
6353	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
6354	*
6355	* @note Do no use this macro in common code working on a core structure which
6356	* device specific code has expanded.
6357	*/
6358	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6359	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
6360	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6361	{ \
6362	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
6363	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
6364	return pLambdaRet; \
6365	}(a_pDevIns))
6366	#else
6367	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
6368	#endif
6369
6370
6371	#ifdef IN_RING3
6372
6373	/**
6374	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
6375	*/
6376	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6377	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
6378	PIOMIOPORTHANDLE phIoPorts)
6379	{
6380	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6381	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6382	if (RT_SUCCESS(rc))
6383	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6384	return rc;
6385	}
6386
6387	/**
6388	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
6389	*/
6390	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6391	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6392	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6393	{
6394	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6395	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6396	if (RT_SUCCESS(rc))
6397	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6398	return rc;
6399	}
6400
6401	/**
6402	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
6403	*/
6404	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6405	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6406	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6407	{
6408	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6409	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6410	if (RT_SUCCESS(rc))
6411	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6412	return rc;
6413	}
6414
6415	/**
6416	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
6417	*/
6418	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6419	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6420	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6421	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6422	{
6423	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6424	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6425	if (RT_SUCCESS(rc))
6426	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6427	return rc;
6428	}
6429
6430	/**
6431	* @sa PDMDevHlpIoPortCreateEx
6432	*/
6433	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6434	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6435	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6436	{
6437	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
6438	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6439	}
6440
6441
6442	/**
6443	* @sa PDMDevHlpIoPortCreateEx
6444	*/
6445	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6446	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6447	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6448	{
6449	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6450	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6451	}
6452
6453	/**
6454	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6455	*/
6456	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6457	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6458	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6459	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6460	{
6461	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6462	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6463	}
6464
6465	/**
6466	* @copydoc PDMDEVHLPR3::pfnIoPortMap
6467	*/
6468	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6469	{
6470	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6471	}
6472
6473	/**
6474	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6475	*/
6476	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6477	{
6478	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6479	}
6480
6481	/**
6482	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6483	*/
6484	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6485	{
6486	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6487	}
6488
6489
6490	#endif /* IN_RING3 */
6491	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6492
6493	/**
6494	* @sa PDMDevHlpIoPortSetUpContextEx
6495	*/
6496	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6497	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6498	{
6499	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6500	}
6501
6502	/**
6503	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6504	*/
6505	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6506	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6507	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6508	{
6509	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6510	}
6511
6512	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6513	#ifdef IN_RING3
6514
6515	/**
6516	* @sa PDMDevHlpMmioCreateEx
6517	*/
6518	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6519	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6520	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6521	{
6522	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6523	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6524	}
6525
6526	/**
6527	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6528	*/
6529	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6530	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6531	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6532	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6533	{
6534	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6535	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6536	}
6537
6538	/**
6539	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6540	*/
6541	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6542	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6543	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6544	{
6545	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6546	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6547	if (RT_SUCCESS(rc))
6548	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6549	return rc;
6550	}
6551
6552	/**
6553	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6554	*/
6555	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6556	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6557	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6558	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6559	{
6560	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6561	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6562	if (RT_SUCCESS(rc))
6563	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6564	return rc;
6565	}
6566
6567	/**
6568	* @copydoc PDMDEVHLPR3::pfnMmioMap
6569	*/
6570	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6571	{
6572	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6573	}
6574
6575	/**
6576	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6577	*/
6578	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6579	{
6580	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6581	}
6582
6583	/**
6584	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6585	*/
6586	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6587	{
6588	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6589	}
6590
6591	/**
6592	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6593	*/
6594	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6595	{
6596	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6597	}
6598
6599	#endif /* IN_RING3 */
6600	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6601
6602	/**
6603	* @sa PDMDevHlpMmioSetUpContextEx
6604	*/
6605	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6606	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6607	{
6608	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6609	}
6610
6611	/**
6612	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6613	*/
6614	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6615	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6616	{
6617	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6618	}
6619
6620	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6621	#ifdef IN_RING3
6622
6623	/**
6624	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6625	*/
6626	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6627	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6628	{
6629	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6630	}
6631
6632	/**
6633	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6634	*/
6635	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6636	{
6637	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6638	}
6639
6640	/**
6641	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6642	*/
6643	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6644	{
6645	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6646	}
6647
6648	/**
6649	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6650	*/
6651	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6652	{
6653	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6654	}
6655
6656	/**
6657	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6658	*/
6659	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6660	{
6661	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6662	}
6663
6664	#endif /* IN_RING3 */
6665
6666	/**
6667	* @copydoc PDMDEVHLPR3::pfnMmioMapMmio2Page
6668	*/
6669	DECLINLINE(RTGCPHYS) PDMDevHlpMmioMapMmio2Page(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6670	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags)
6671	{
6672	return pDevIns->CTX_SUFF(pHlp)->pfnMmioMapMmio2Page(pDevIns, hRegion, offRegion, hMmio2, offMmio2, fPageFlags);
6673	}
6674
6675	/**
6676	* @copydoc PDMDEVHLPR3::pfnMmioResetRegion
6677	*/
6678	DECLINLINE(RTGCPHYS) PDMDevHlpMmioResetRegion(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6679	{
6680	return pDevIns->CTX_SUFF(pHlp)->pfnMmioResetRegion(pDevIns, hRegion);
6681	}
6682
6683	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6684
6685	/**
6686	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6687	*/
6688	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6689	size_t offSub, size_t cbSub, void **ppvMapping)
6690	{
6691	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6692	}
6693
6694	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6695	#ifdef IN_RING3
6696
6697	/**
6698	* @copydoc PDMDEVHLPR3::pfnROMRegister
6699	*/
6700	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6701	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6702	{
6703	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6704	}
6705
6706	/**
6707	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6708	*/
6709	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6710	{
6711	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6712	}
6713
6714	/**
6715	* Register a save state data unit.
6716	*
6717	* @returns VBox status.
6718	* @param pDevIns The device instance.
6719	* @param uVersion Data layout version number.
6720	* @param cbGuess The approximate amount of data in the unit.
6721	* Only for progress indicators.
6722	* @param pfnSaveExec Execute save callback, optional.
6723	* @param pfnLoadExec Execute load callback, optional.
6724	*/
6725	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6726	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6727	{
6728	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6729	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6730	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6731	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6732	}
6733
6734	/**
6735	* Register a save state data unit with a live save callback as well.
6736	*
6737	* @returns VBox status.
6738	* @param pDevIns The device instance.
6739	* @param uVersion Data layout version number.
6740	* @param cbGuess The approximate amount of data in the unit.
6741	* Only for progress indicators.
6742	* @param pfnLiveExec Execute live callback, optional.
6743	* @param pfnSaveExec Execute save callback, optional.
6744	* @param pfnLoadExec Execute load callback, optional.
6745	*/
6746	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6747	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6748	{
6749	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6750	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6751	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6752	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6753	}
6754
6755	/**
6756	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6757	*/
6758	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6759	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6760	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6761	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6762	{
6763	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6764	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6765	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6766	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6767	}
6768
6769	/**
6770	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6771	*/
6772	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6773	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6774	{
6775	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6776	}
6777
6778	#endif /* IN_RING3 */
6779
6780	/**
6781	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6782	*/
6783	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6784	{
6785	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6786	}
6787
6788	/**
6789	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6790	*/
6791	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6792	{
6793	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6794	}
6795
6796	/**
6797	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6798	*/
6799	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6800	{
6801	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6802	}
6803
6804	/**
6805	* @copydoc PDMDEVHLPR3::pfnTimerGet
6806	*/
6807	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6808	{
6809	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6810	}
6811
6812	/**
6813	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6814	*/
6815	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6816	{
6817	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6818	}
6819
6820	/**
6821	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6822	*/
6823	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6824	{
6825	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6826	}
6827
6828	/**
6829	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6830	*/
6831	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6832	{
6833	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6834	}
6835
6836	/**
6837	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6838	*/
6839	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6840	{
6841	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6842	}
6843
6844	/**
6845	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
6846	*/
6847	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6848	{
6849	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6850	}
6851
6852	/**
6853	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6854	*/
6855	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6856	{
6857	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6858	}
6859
6860	/**
6861	* @copydoc PDMDEVHLPR3::pfnTimerSet
6862	*/
6863	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6864	{
6865	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6866	}
6867
6868	/**
6869	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6870	*/
6871	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6872	{
6873	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6874	}
6875
6876	/**
6877	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6878	*/
6879	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6880	{
6881	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6882	}
6883
6884	/**
6885	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6886	*/
6887	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6888	{
6889	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6890	}
6891
6892	/**
6893	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6894	*/
6895	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6896	{
6897	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6898	}
6899
6900	/**
6901	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6902	*/
6903	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6904	{
6905	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6906	}
6907
6908	/**
6909	* @copydoc PDMDEVHLPR3::pfnTimerStop
6910	*/
6911	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6912	{
6913	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6914	}
6915
6916	/**
6917	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6918	*/
6919	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6920	{
6921	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6922	}
6923
6924	/**
6925	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6926	*/
6927	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6928	{
6929	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6930	}
6931
6932	#ifdef IN_RING3
6933
6934	/**
6935	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6936	*/
6937	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6938	{
6939	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6940	}
6941
6942	/**
6943	* @copydoc PDMDEVHLPR3::pfnTimerSave
6944	*/
6945	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6946	{
6947	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6948	}
6949
6950	/**
6951	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6952	*/
6953	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6954	{
6955	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6956	}
6957
6958	/**
6959	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6960	*/
6961	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6962	{
6963	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6964	}
6965
6966	/**
6967	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6968	*/
6969	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6970	{
6971	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6972	}
6973
6974	#endif
6975
6976	/**
6977	* Read physical memory - unknown data usage.
6978	*
6979	* @returns VINF_SUCCESS (for now).
6980	* @param pDevIns The device instance.
6981	* @param GCPhys Physical address start reading from.
6982	* @param pvBuf Where to put the read bits.
6983	* @param cbRead How many bytes to read.
6984	* @thread Any thread, but the call may involve the emulation thread.
6985	*/
6986	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6987	{
6988	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6989	}
6990
6991	/**
6992	* Write to physical memory - unknown data usage.
6993	*
6994	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6995	* @param pDevIns The device instance.
6996	* @param GCPhys Physical address to write to.
6997	* @param pvBuf What to write.
6998	* @param cbWrite How many bytes to write.
6999	* @thread Any thread, but the call may involve the emulation thread.
7000	*/
7001	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7002	{
7003	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7004	}
7005
7006	/**
7007	* Read physical memory - reads meta data processed by the device.
7008	*
7009	* @returns VINF_SUCCESS (for now).
7010	* @param pDevIns The device instance.
7011	* @param GCPhys Physical address start reading from.
7012	* @param pvBuf Where to put the read bits.
7013	* @param cbRead How many bytes to read.
7014	* @thread Any thread, but the call may involve the emulation thread.
7015	*/
7016	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7017	{
7018	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7019	}
7020
7021	/**
7022	* Write to physical memory - written data was created/altered by the device.
7023	*
7024	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7025	* @param pDevIns The device instance.
7026	* @param GCPhys Physical address to write to.
7027	* @param pvBuf What to write.
7028	* @param cbWrite How many bytes to write.
7029	* @thread Any thread, but the call may involve the emulation thread.
7030	*/
7031	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7032	{
7033	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7034	}
7035
7036	/**
7037	* Read physical memory - read data will not be touched by the device.
7038	*
7039	* @returns VINF_SUCCESS (for now).
7040	* @param pDevIns The device instance.
7041	* @param GCPhys Physical address start reading from.
7042	* @param pvBuf Where to put the read bits.
7043	* @param cbRead How many bytes to read.
7044	* @thread Any thread, but the call may involve the emulation thread.
7045	*/
7046	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7047	{
7048	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7049	}
7050
7051	/**
7052	* Write to physical memory - written data was not touched/created by the device.
7053	*
7054	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7055	* @param pDevIns The device instance.
7056	* @param GCPhys Physical address to write to.
7057	* @param pvBuf What to write.
7058	* @param cbWrite How many bytes to write.
7059	* @thread Any thread, but the call may involve the emulation thread.
7060	*/
7061	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7062	{
7063	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7064	}
7065
7066	#ifdef IN_RING3
7067
7068	/**
7069	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
7070	*/
7071	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
7072	{
7073	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
7074	}
7075
7076	/**
7077	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
7078	*/
7079	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
7080	PPGMPAGEMAPLOCK pLock)
7081	{
7082	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
7083	}
7084
7085	/**
7086	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
7087	*/
7088	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
7089	{
7090	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
7091	}
7092
7093	/**
7094	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
7095	*/
7096	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7097	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
7098	{
7099	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7100	}
7101
7102	/**
7103	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
7104	*/
7105	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7106	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
7107	{
7108	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7109	}
7110
7111	/**
7112	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
7113	*/
7114	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
7115	{
7116	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
7117	}
7118
7119	/**
7120	* @copydoc PDMDEVHLPR3::pfnPhysIsGCPhysNormal
7121	*/
7122	DECLINLINE(bool) PDMDevHlpPhysIsGCPhysNormal(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
7123	{
7124	return pDevIns->CTX_SUFF(pHlp)->pfnPhysIsGCPhysNormal(pDevIns, GCPhys);
7125	}
7126
7127	/**
7128	* @copydoc PDMDEVHLPR3::pfnPhysChangeMemBalloon
7129	*/
7130	DECLINLINE(int) PDMDevHlpPhysChangeMemBalloon(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
7131	{
7132	return pDevIns->CTX_SUFF(pHlp)->pfnPhysChangeMemBalloon(pDevIns, fInflate, cPages, paPhysPage);
7133	}
7134
7135	/**
7136	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
7137	*/
7138	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
7139	{
7140	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
7141	}
7142
7143	/**
7144	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
7145	*/
7146	DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth)
7147	{
7148	pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
7149	}
7150
7151	/**
7152	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
7153	*/
7154	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
7155	{
7156	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
7157	}
7158
7159	/**
7160	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
7161	*/
7162	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
7163	{
7164	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
7165	}
7166
7167	/**
7168	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
7169	*/
7170	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
7171	{
7172	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
7173	}
7174
7175	/**
7176	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
7177	*/
7178	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
7179	{
7180	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
7181	}
7182
7183	/**
7184	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
7185	*/
7186	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
7187	{
7188	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
7189	}
7190
7191	/**
7192	* Allocating string printf.
7193	*
7194	* @returns Pointer to the string.
7195	* @param pDevIns The device instance.
7196	* @param enmTag The statistics tag.
7197	* @param pszFormat The format string.
7198	* @param ... Format arguments.
7199	*/
7200	DECLINLINE(char ) RT_IPRT_FORMAT_ATTR(2, 3) PDMDevHlpMMHeapAPrintf(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, ...)
7201	{
7202	va_list va;
7203	va_start(va, pszFormat);
7204	char *psz = pDevIns->pHlpR3->pfnMMHeapAPrintfV(pDevIns, enmTag, pszFormat, va);
7205	va_end(va);
7206
7207	return psz;
7208	}
7209
7210	/**
7211	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
7212	*/
7213	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
7214	{
7215	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
7216	}
7217
7218	/**
7219	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSize
7220	*/
7221	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSize(PPDMDEVINS pDevIns)
7222	{
7223	return pDevIns->pHlpR3->pfnMMPhysGetRamSize(pDevIns);
7224	}
7225
7226	/**
7227	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeBelow4GB
7228	*/
7229	DECLINLINE(uint32_t) PDMDevHlpMMPhysGetRamSizeBelow4GB(PPDMDEVINS pDevIns)
7230	{
7231	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeBelow4GB(pDevIns);
7232	}
7233
7234	/**
7235	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeAbove4GB
7236	*/
7237	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSizeAbove4GB(PPDMDEVINS pDevIns)
7238	{
7239	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeAbove4GB(pDevIns);
7240	}
7241	#endif /* IN_RING3 */
7242
7243	/**
7244	* @copydoc PDMDEVHLPR3::pfnVMState
7245	*/
7246	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
7247	{
7248	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
7249	}
7250
7251	#ifdef IN_RING3
7252
7253	/**
7254	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
7255	*/
7256	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
7257	{
7258	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
7259	}
7260
7261	/**
7262	* Set the VM error message
7263	*
7264	* @returns rc.
7265	* @param pDevIns The device instance.
7266	* @param rc VBox status code.
7267	* @param SRC_POS Use RT_SRC_POS.
7268	* @param pszFormat Error message format string.
7269	* @param ... Error message arguments.
7270	* @sa VMSetError
7271	*/
7272	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
7273	const char *pszFormat, ...)
7274	{
7275	va_list va;
7276	va_start(va, pszFormat);
7277	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
7278	va_end(va);
7279	return rc;
7280	}
7281
7282	/**
7283	* Set the VM runtime error message
7284	*
7285	* @returns VBox status code.
7286	* @param pDevIns The device instance.
7287	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
7288	* @param pszErrorId Error ID string.
7289	* @param pszFormat Error message format string.
7290	* @param ... Error message arguments.
7291	* @sa VMSetRuntimeError
7292	*/
7293	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
7294	const char *pszFormat, ...)
7295	{
7296	va_list va;
7297	int rc;
7298	va_start(va, pszFormat);
7299	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
7300	va_end(va);
7301	return rc;
7302	}
7303
7304	/**
7305	* @copydoc PDMDEVHLPR3::pfnVMWaitForDeviceReady
7306	*/
7307	DECLINLINE(int) PDMDevHlpVMWaitForDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7308	{
7309	return pDevIns->CTX_SUFF(pHlp)->pfnVMWaitForDeviceReady(pDevIns, idCpu);
7310	}
7311
7312	/**
7313	* @copydoc PDMDEVHLPR3::pfnVMNotifyCpuDeviceReady
7314	*/
7315	DECLINLINE(int) PDMDevHlpVMNotifyCpuDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7316	{
7317	return pDevIns->CTX_SUFF(pHlp)->pfnVMNotifyCpuDeviceReady(pDevIns, idCpu);
7318	}
7319
7320	/**
7321	* Convenience wrapper for VMR3ReqCallU.
7322	*
7323	* This assumes (1) you're calling a function that returns an VBox status code
7324	* and that you do not wish to wait for it to complete.
7325	*
7326	* @returns VBox status code returned by VMR3ReqCallVU.
7327	*
7328	* @param pDevIns The device instance.
7329	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7330	* one of the following special values:
7331	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7332	* @param pfnFunction Pointer to the function to call.
7333	* @param cArgs Number of arguments following in the ellipsis.
7334	* @param ... Argument list.
7335	*
7336	* @remarks See remarks on VMR3ReqCallVU.
7337	*/
7338	DECLINLINE(int) PDMDevHlpVMReqCallNoWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7339	{
7340	va_list Args;
7341	va_start(Args, cArgs);
7342	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqCallNoWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7343	va_end(Args);
7344	return rc;
7345	}
7346
7347	/**
7348	* Convenience wrapper for VMR3ReqCallU.
7349	*
7350	* This assumes (1) you're calling a function that returns void, (2) that you
7351	* wish to wait for ever for it to return, and (3) that it's priority request
7352	* that can be safely be handled during async suspend and power off.
7353	*
7354	* @returns VBox status code of VMR3ReqCallVU.
7355	*
7356	* @param pDevIns The device instance.
7357	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7358	* one of the following special values:
7359	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7360	* @param pfnFunction Pointer to the function to call.
7361	* @param cArgs Number of arguments following in the ellipsis.
7362	* @param ... Argument list.
7363	*
7364	* @remarks See remarks on VMR3ReqCallVU.
7365	*/
7366	DECLINLINE(int) PDMDevHlpVMReqPriorityCallWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7367	{
7368	va_list Args;
7369	va_start(Args, cArgs);
7370	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqPriorityCallWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7371	va_end(Args);
7372	return rc;
7373	}
7374
7375	#endif /* IN_RING3 */
7376
7377	/**
7378	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
7379	*
7380	* @returns VBox status code which must be passed up to the VMM. This will be
7381	* VINF_SUCCESS in non-strict builds.
7382	* @param pDevIns The device instance.
7383	* @param SRC_POS Use RT_SRC_POS.
7384	* @param pszFormat Message. (optional)
7385	* @param ... Message parameters.
7386	*/
7387	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
7388	{
7389	#ifdef VBOX_STRICT
7390	# ifdef IN_RING3
7391	int rc;
7392	va_list args;
7393	va_start(args, pszFormat);
7394	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
7395	va_end(args);
7396	return rc;
7397	# else
7398	NOREF(pDevIns);
7399	NOREF(pszFile);
7400	NOREF(iLine);
7401	NOREF(pszFunction);
7402	NOREF(pszFormat);
7403	return VINF_EM_DBG_STOP;
7404	# endif
7405	#else
7406	NOREF(pDevIns);
7407	NOREF(pszFile);
7408	NOREF(iLine);
7409	NOREF(pszFunction);
7410	NOREF(pszFormat);
7411	return VINF_SUCCESS;
7412	#endif
7413	}
7414
7415	#ifdef IN_RING3
7416
7417	/**
7418	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
7419	*/
7420	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
7421	{
7422	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
7423	}
7424
7425	/**
7426	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
7427	*/
7428	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
7429	{
7430	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
7431	}
7432
7433	/**
7434	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
7435	*/
7436	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
7437	{
7438	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
7439	}
7440
7441	/**
7442	* @copydoc PDMDEVHLPR3::pfnDBGFReportBugCheck
7443	*/
7444	DECLINLINE(VBOXSTRICTRC) PDMDevHlpDBGFReportBugCheck(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
7445	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4)
7446	{
7447	return pDevIns->pHlpR3->pfnDBGFReportBugCheck(pDevIns, enmEvent, uBugCheck, uP1, uP2, uP3, uP4);
7448	}
7449
7450	/**
7451	* @copydoc PDMDEVHLPR3::pfnDBGFCoreWrite
7452	*/
7453	DECLINLINE(int) PDMDevHlpDBGFCoreWrite(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile)
7454	{
7455	return pDevIns->pHlpR3->pfnDBGFCoreWrite(pDevIns, pszFilename, fReplaceFile);
7456	}
7457
7458	/**
7459	* @copydoc PDMDEVHLPR3::pfnDBGFInfoLogHlp
7460	*/
7461	DECLINLINE(PCDBGFINFOHLP) PDMDevHlpDBGFInfoLogHlp(PPDMDEVINS pDevIns)
7462	{
7463	return pDevIns->pHlpR3->pfnDBGFInfoLogHlp(pDevIns);
7464	}
7465
7466	/**
7467	* @copydoc PDMDEVHLPR3::pfnDBGFRegNmQueryU64
7468	*/
7469	DECLINLINE(int) PDMDevHlpDBGFRegNmQueryU64(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64)
7470	{
7471	return pDevIns->pHlpR3->pfnDBGFRegNmQueryU64(pDevIns, idDefCpu, pszReg, pu64);
7472	}
7473
7474	/**
7475	* Format a set of registers.
7476	*
7477	* This is restricted to registers from one CPU, that specified by @a idCpu.
7478	*
7479	* @returns VBox status code.
7480	* @param pDevIns The device instance.
7481	* @param idCpu The CPU ID of any CPU registers that may be
7482	* printed, pass VMCPUID_ANY if not applicable.
7483	* @param pszBuf The output buffer.
7484	* @param cbBuf The size of the output buffer.
7485	* @param pszFormat The format string. Register names are given by
7486	* %VR{name}, they take no arguments.
7487	* @param ... Argument list.
7488	*/
7489	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpDBGFRegPrintf(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
7490	const char *pszFormat, ...)
7491	{
7492	va_list Args;
7493	va_start(Args, pszFormat);
7494	int rc = pDevIns->pHlpR3->pfnDBGFRegPrintfV(pDevIns, idCpu, pszBuf, cbBuf, pszFormat, Args);
7495	va_end(Args);
7496	return rc;
7497	}
7498
7499	/**
7500	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
7501	*/
7502	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
7503	{
7504	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
7505	}
7506
7507	/**
7508	* Same as pfnSTAMRegister except that the name is specified in a
7509	* RTStrPrintf like fashion.
7510	*
7511	* @returns VBox status.
7512	* @param pDevIns Device instance of the DMA.
7513	* @param pvSample Pointer to the sample.
7514	* @param enmType Sample type. This indicates what pvSample is
7515	* pointing at.
7516	* @param enmVisibility Visibility type specifying whether unused
7517	* statistics should be visible or not.
7518	* @param enmUnit Sample unit.
7519	* @param pszDesc Sample description.
7520	* @param pszName Sample name format string, unix path style. If
7521	* this does not start with a '/', the default
7522	* prefix will be prepended, otherwise it will be
7523	* used as-is.
7524	* @param ... Arguments to the format string.
7525	*/
7526	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
7527	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
7528	const char pszDesc, const char pszName, ...)
7529	{
7530	va_list va;
7531	va_start(va, pszName);
7532	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
7533	va_end(va);
7534	}
7535
7536	/**
7537	* @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
7538	*/
7539	DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
7540	{
7541	return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
7542	}
7543
7544	/**
7545	* Registers the device with the default PCI bus.
7546	*
7547	* @returns VBox status code.
7548	* @param pDevIns The device instance.
7549	* @param pPciDev The PCI device structure.
7550	* This must be kept in the instance data.
7551	* The PCI configuration must be initialized before registration.
7552	*/
7553	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
7554	{
7555	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
7556	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
7557	}
7558
7559	/**
7560	* @copydoc PDMDEVHLPR3::pfnPCIRegister
7561	*/
7562	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
7563	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
7564	{
7565	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
7566	}
7567
7568	/**
7569	* Initialize MSI emulation support for the first PCI device.
7570	*
7571	* @returns VBox status code.
7572	* @param pDevIns The device instance.
7573	* @param pMsiReg MSI emulation registration structure.
7574	*/
7575	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
7576	{
7577	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
7578	}
7579
7580	/**
7581	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
7582	*/
7583	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
7584	{
7585	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
7586	}
7587
7588	/**
7589	* Registers a I/O port region for the default PCI device.
7590	*
7591	* @returns VBox status code.
7592	* @param pDevIns The device instance.
7593	* @param iRegion The region number.
7594	* @param cbRegion Size of the region.
7595	* @param hIoPorts Handle to the I/O port region.
7596	*/
7597	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
7598	{
7599	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7600	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
7601	}
7602
7603	/**
7604	* Registers a I/O port region for the default PCI device, custom map/unmap.
7605	*
7606	* @returns VBox status code.
7607	* @param pDevIns The device instance.
7608	* @param iRegion The region number.
7609	* @param cbRegion Size of the region.
7610	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7611	* callback will be invoked holding only the PDM lock.
7612	* The device lock will _not_ be taken (due to lock
7613	* order).
7614	*/
7615	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7616	PFNPCIIOREGIONMAP pfnMapUnmap)
7617	{
7618	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7619	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7620	UINT64_MAX, pfnMapUnmap);
7621	}
7622
7623	/**
7624	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7625	* and registering an I/O port region for the default PCI device.
7626	*
7627	* @returns VBox status code.
7628	* @param pDevIns The device instance to register the ports with.
7629	* @param cPorts The count of I/O ports in the region (the size).
7630	* @param iPciRegion The PCI device region.
7631	* @param pfnOut Pointer to function which is gonna handle OUT
7632	* operations. Optional.
7633	* @param pfnIn Pointer to function which is gonna handle IN operations.
7634	* Optional.
7635	* @param pvUser User argument to pass to the callbacks.
7636	* @param pszDesc Pointer to description string. This must not be freed.
7637	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7638	* coverage is allowed. This must not be freed.
7639	* @param phIoPorts Where to return the I/O port range handle.
7640	*
7641	*/
7642	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7643	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7644	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7645
7646	{
7647	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7648	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7649	if (RT_SUCCESS(rc))
7650	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7651	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7652	phIoPorts, NULL /pfnMapUnmap*/);
7653	return rc;
7654	}
7655
7656	/**
7657	* Registers an MMIO region for the default PCI device.
7658	*
7659	* @returns VBox status code.
7660	* @param pDevIns The device instance.
7661	* @param iRegion The region number.
7662	* @param cbRegion Size of the region.
7663	* @param enmType PCI_ADDRESS_SPACE_MEM or
7664	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7665	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7666	* @param hMmioRegion Handle to the MMIO region.
7667	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7668	* callback will be invoked holding only the PDM lock.
7669	* The device lock will _not_ be taken (due to lock
7670	* order).
7671	*/
7672	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7673	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7674	{
7675	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7676	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7677	hMmioRegion, pfnMapUnmap);
7678	}
7679
7680	/**
7681	* Registers an MMIO region for the default PCI device, extended version.
7682	*
7683	* @returns VBox status code.
7684	* @param pDevIns The device instance.
7685	* @param pPciDev The PCI device structure.
7686	* @param iRegion The region number.
7687	* @param cbRegion Size of the region.
7688	* @param enmType PCI_ADDRESS_SPACE_MEM or
7689	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7690	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7691	* @param hMmioRegion Handle to the MMIO region.
7692	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7693	* callback will be invoked holding only the PDM lock.
7694	* The device lock will _not_ be taken (due to lock
7695	* order).
7696	*/
7697	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7698	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7699	PFNPCIIOREGIONMAP pfnMapUnmap)
7700	{
7701	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7702	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7703	hMmioRegion, pfnMapUnmap);
7704	}
7705
7706	/**
7707	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7708	* and registering an MMIO region for the default PCI device.
7709	*
7710	* @returns VBox status code.
7711	* @param pDevIns The device instance to register the ports with.
7712	* @param cbRegion The size of the region in bytes.
7713	* @param iPciRegion The PCI device region.
7714	* @param enmType PCI_ADDRESS_SPACE_MEM or
7715	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7716	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7717	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7718	* @param pfnWrite Pointer to function which is gonna handle Write
7719	* operations.
7720	* @param pfnRead Pointer to function which is gonna handle Read
7721	* operations.
7722	* @param pvUser User argument to pass to the callbacks.
7723	* @param pszDesc Pointer to description string. This must not be freed.
7724	* @param phRegion Where to return the MMIO region handle.
7725	*
7726	*/
7727	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7728	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7729	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7730
7731	{
7732	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7733	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7734	if (RT_SUCCESS(rc))
7735	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7736	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7737	phRegion, NULL /pfnMapUnmap*/);
7738	return rc;
7739	}
7740
7741
7742	/**
7743	* Registers an MMIO2 region for the default PCI device.
7744	*
7745	* @returns VBox status code.
7746	* @param pDevIns The device instance.
7747	* @param iRegion The region number.
7748	* @param cbRegion Size of the region.
7749	* @param enmType PCI_ADDRESS_SPACE_MEM or
7750	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7751	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7752	* @param hMmio2Region Handle to the MMIO2 region.
7753	*/
7754	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7755	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7756	{
7757	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7758	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7759	hMmio2Region, NULL);
7760	}
7761
7762	/**
7763	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7764	* and registering an MMIO2 region for the default PCI device, extended edition.
7765	*
7766	* @returns VBox status code.
7767	* @param pDevIns The device instance to register the ports with.
7768	* @param cbRegion The size of the region in bytes.
7769	* @param iPciRegion The PCI device region.
7770	* @param enmType PCI_ADDRESS_SPACE_MEM or
7771	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7772	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7773	* @param pszDesc Pointer to description string. This must not be freed.
7774	* @param ppvMapping Where to store the address of the ring-3 mapping of
7775	* the memory.
7776	* @param phRegion Where to return the MMIO2 region handle.
7777	*
7778	*/
7779	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7780	PCIADDRESSSPACE enmType, const char *pszDesc,
7781	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7782
7783	{
7784	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7785	pszDesc, ppvMapping, phRegion);
7786	if (RT_SUCCESS(rc))
7787	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7788	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7789	phRegion, NULL /pfnCallback*/);
7790	return rc;
7791	}
7792
7793	/**
7794	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7795	* and registering an MMIO2 region for the default PCI device.
7796	*
7797	* @returns VBox status code.
7798	* @param pDevIns The device instance to register the ports with.
7799	* @param cbRegion The size of the region in bytes.
7800	* @param iPciRegion The PCI device region.
7801	* @param enmType PCI_ADDRESS_SPACE_MEM or
7802	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7803	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7804	* @param fMmio2Flags To be defined, must be zero.
7805	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7806	* callback will be invoked holding only the PDM lock.
7807	* The device lock will _not_ be taken (due to lock
7808	* order).
7809	* @param pszDesc Pointer to description string. This must not be freed.
7810	* @param ppvMapping Where to store the address of the ring-3 mapping of
7811	* the memory.
7812	* @param phRegion Where to return the MMIO2 region handle.
7813	*
7814	*/
7815	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7816	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7817	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
7818
7819	{
7820	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7821	pszDesc, ppvMapping, phRegion);
7822	if (RT_SUCCESS(rc))
7823	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7824	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7825	*phRegion, pfnMapUnmap);
7826	return rc;
7827	}
7828
7829	/**
7830	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7831	*/
7832	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7833	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7834	{
7835	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7836	}
7837
7838	/**
7839	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7840	*/
7841	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7842	unsigned cb, uint32_t *pu32Value)
7843	{
7844	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7845	}
7846
7847	/**
7848	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7849	*/
7850	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7851	unsigned cb, uint32_t u32Value)
7852	{
7853	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7854	}
7855
7856	#endif /* IN_RING3 */
7857
7858	/**
7859	* Bus master physical memory read from the default PCI device.
7860	*
7861	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7862	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7863	* @param pDevIns The device instance.
7864	* @param GCPhys Physical address start reading from.
7865	* @param pvBuf Where to put the read bits.
7866	* @param cbRead How many bytes to read.
7867	* @thread Any thread, but the call may involve the emulation thread.
7868	*/
7869	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7870	{
7871	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7872	}
7873
7874	/**
7875	* Bus master physical memory read - unknown data usage.
7876	*
7877	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7878	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7879	* @param pDevIns The device instance.
7880	* @param pPciDev The PCI device structure. If NULL the default
7881	* PCI device for this device instance is used.
7882	* @param GCPhys Physical address start reading from.
7883	* @param pvBuf Where to put the read bits.
7884	* @param cbRead How many bytes to read.
7885	* @thread Any thread, but the call may involve the emulation thread.
7886	*/
7887	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7888	{
7889	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7890	}
7891
7892	/**
7893	* Bus master physical memory read from the default PCI device.
7894	*
7895	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7896	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7897	* @param pDevIns The device instance.
7898	* @param GCPhys Physical address start reading from.
7899	* @param pvBuf Where to put the read bits.
7900	* @param cbRead How many bytes to read.
7901	* @thread Any thread, but the call may involve the emulation thread.
7902	*/
7903	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7904	{
7905	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7906	}
7907
7908	/**
7909	* Bus master physical memory read - reads meta data processed by the device.
7910	*
7911	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7912	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7913	* @param pDevIns The device instance.
7914	* @param pPciDev The PCI device structure. If NULL the default
7915	* PCI device for this device instance is used.
7916	* @param GCPhys Physical address start reading from.
7917	* @param pvBuf Where to put the read bits.
7918	* @param cbRead How many bytes to read.
7919	* @thread Any thread, but the call may involve the emulation thread.
7920	*/
7921	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7922	{
7923	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7924	}
7925
7926	/**
7927	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
7928	*
7929	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7930	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7931	* @param pDevIns The device instance.
7932	* @param GCPhys Physical address start reading from.
7933	* @param pvBuf Where to put the read bits.
7934	* @param cbRead How many bytes to read.
7935	* @thread Any thread, but the call may involve the emulation thread.
7936	*/
7937	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7938	{
7939	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7940	}
7941
7942	/**
7943	* Bus master physical memory read - read data will not be touched by the device.
7944	*
7945	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7946	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7947	* @param pDevIns The device instance.
7948	* @param pPciDev The PCI device structure. If NULL the default
7949	* PCI device for this device instance is used.
7950	* @param GCPhys Physical address start reading from.
7951	* @param pvBuf Where to put the read bits.
7952	* @param cbRead How many bytes to read.
7953	* @thread Any thread, but the call may involve the emulation thread.
7954	*/
7955	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7956	{
7957	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7958	}
7959
7960	/**
7961	* Bus master physical memory write from the default PCI device - unknown data usage.
7962	*
7963	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7964	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7965	* @param pDevIns The device instance.
7966	* @param GCPhys Physical address to write to.
7967	* @param pvBuf What to write.
7968	* @param cbWrite How many bytes to write.
7969	* @thread Any thread, but the call may involve the emulation thread.
7970	*/
7971	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7972	{
7973	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7974	}
7975
7976	/**
7977	* Bus master physical memory write - unknown data usage.
7978	*
7979	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7980	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7981	* @param pDevIns The device instance.
7982	* @param pPciDev The PCI device structure. If NULL the default
7983	* PCI device for this device instance is used.
7984	* @param GCPhys Physical address to write to.
7985	* @param pvBuf What to write.
7986	* @param cbWrite How many bytes to write.
7987	* @thread Any thread, but the call may involve the emulation thread.
7988	*/
7989	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7990	{
7991	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7992	}
7993
7994	/**
7995	* Bus master physical memory write from the default PCI device.
7996	*
7997	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7998	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7999	* @param pDevIns The device instance.
8000	* @param GCPhys Physical address to write to.
8001	* @param pvBuf What to write.
8002	* @param cbWrite How many bytes to write.
8003	* @thread Any thread, but the call may involve the emulation thread.
8004	*/
8005	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8006	{
8007	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8008	}
8009
8010	/**
8011	* Bus master physical memory write - written data was created/altered by the device.
8012	*
8013	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8014	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8015	* @param pDevIns The device instance.
8016	* @param pPciDev The PCI device structure. If NULL the default
8017	* PCI device for this device instance is used.
8018	* @param GCPhys Physical address to write to.
8019	* @param pvBuf What to write.
8020	* @param cbWrite How many bytes to write.
8021	* @thread Any thread, but the call may involve the emulation thread.
8022	*/
8023	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8024	{
8025	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8026	}
8027
8028	/**
8029	* Bus master physical memory write from the default PCI device.
8030	*
8031	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8032	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8033	* @param pDevIns The device instance.
8034	* @param GCPhys Physical address to write to.
8035	* @param pvBuf What to write.
8036	* @param cbWrite How many bytes to write.
8037	* @thread Any thread, but the call may involve the emulation thread.
8038	*/
8039	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8040	{
8041	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8042	}
8043
8044	/**
8045	* Bus master physical memory write - written data was not touched/created by the device.
8046	*
8047	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8048	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8049	* @param pDevIns The device instance.
8050	* @param pPciDev The PCI device structure. If NULL the default
8051	* PCI device for this device instance is used.
8052	* @param GCPhys Physical address to write to.
8053	* @param pvBuf What to write.
8054	* @param cbWrite How many bytes to write.
8055	* @thread Any thread, but the call may involve the emulation thread.
8056	*/
8057	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8058	{
8059	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8060	}
8061
8062	#ifdef IN_RING3
8063	/**
8064	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
8065	*/
8066	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8067	void **ppv, PPGMPAGEMAPLOCK pLock)
8068	{
8069	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8070	}
8071
8072	/**
8073	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
8074	*/
8075	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8076	void const **ppv, PPGMPAGEMAPLOCK pLock)
8077	{
8078	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8079	}
8080
8081	/**
8082	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
8083	*/
8084	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8085	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
8086	PPGMPAGEMAPLOCK paLocks)
8087	{
8088	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
8089	paLocks);
8090	}
8091
8092	/**
8093	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
8094	*/
8095	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8096	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
8097	PPGMPAGEMAPLOCK paLocks)
8098	{
8099	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
8100	papvPages, paLocks);
8101	}
8102	#endif /* IN_RING3 */
8103
8104	/**
8105	* Sets the IRQ for the default PCI device.
8106	*
8107	* @param pDevIns The device instance.
8108	* @param iIrq IRQ number to set.
8109	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
8110	* @thread Any thread, but will involve the emulation thread.
8111	*/
8112	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8113	{
8114	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8115	}
8116
8117	/**
8118	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
8119	*/
8120	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8121	{
8122	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8123	}
8124
8125	/**
8126	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
8127	* the request when not called from EMT.
8128	*
8129	* @param pDevIns The device instance.
8130	* @param iIrq IRQ number to set.
8131	* @param iLevel IRQ level.
8132	* @thread Any thread, but will involve the emulation thread.
8133	*/
8134	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8135	{
8136	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8137	}
8138
8139	/**
8140	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
8141	*/
8142	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8143	{
8144	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8145	}
8146
8147	/**
8148	* @copydoc PDMDEVHLPR3::pfnISASetIrq
8149	*/
8150	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8151	{
8152	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8153	}
8154
8155	/**
8156	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
8157	*/
8158	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8159	{
8160	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8161	}
8162
8163	#ifdef IN_RING3
8164
8165	/**
8166	* @copydoc PDMDEVHLPR3::pfnDriverAttach
8167	*/
8168	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
8169	{
8170	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
8171	}
8172
8173	/**
8174	* @copydoc PDMDEVHLPR3::pfnDriverDetach
8175	*/
8176	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
8177	{
8178	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
8179	}
8180
8181	/**
8182	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
8183	*/
8184	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
8185	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
8186	{
8187	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
8188	}
8189
8190	/**
8191	* Reconfigures with a single driver reattachement, no config, noflags.
8192	* @sa PDMDevHlpDriverReconfigure
8193	*/
8194	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
8195	{
8196	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
8197	}
8198
8199	/**
8200	* Reconfigures with a two drivers reattachement, no config, noflags.
8201	* @sa PDMDevHlpDriverReconfigure
8202	*/
8203	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
8204	{
8205	char const * apszDrivers[2];
8206	apszDrivers[0] = pszDriver0;
8207	apszDrivers[1] = pszDriver1;
8208	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
8209	}
8210
8211	/**
8212	* @copydoc PDMDEVHLPR3::pfnQueueCreate
8213	*/
8214	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
8215	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
8216	{
8217	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
8218	}
8219
8220	#endif /* IN_RING3 */
8221
8222	/**
8223	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
8224	*/
8225	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8226	{
8227	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
8228	}
8229
8230	/**
8231	* @copydoc PDMDEVHLPR3::pfnQueueInsert
8232	*/
8233	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
8234	{
8235	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
8236	}
8237
8238	/**
8239	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
8240	*/
8241	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8242	{
8243	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
8244	}
8245
8246	#ifdef IN_RING3
8247	/**
8248	* @copydoc PDMDEVHLPR3::pfnTaskCreate
8249	*/
8250	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
8251	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
8252	{
8253	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
8254	}
8255	#endif
8256
8257	/**
8258	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
8259	*/
8260	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
8261	{
8262	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
8263	}
8264
8265	#ifdef IN_RING3
8266
8267	/**
8268	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
8269	*/
8270	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
8271	{
8272	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
8273	}
8274
8275	/**
8276	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
8277	*/
8278	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8279	{
8280	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
8281	}
8282
8283	#endif /* IN_RING3 */
8284
8285	/**
8286	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
8287	*/
8288	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8289	{
8290	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
8291	}
8292
8293	/**
8294	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
8295	*/
8296	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
8297	{
8298	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
8299	}
8300
8301	/**
8302	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
8303	*/
8304	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
8305	{
8306	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
8307	}
8308
8309	/**
8310	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
8311	*/
8312	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
8313	{
8314	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
8315	}
8316
8317	/**
8318	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
8319	*/
8320	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
8321	{
8322	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
8323	}
8324
8325	#ifdef IN_RING3
8326
8327	/**
8328	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
8329	*/
8330	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
8331	{
8332	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
8333	}
8334
8335	/**
8336	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
8337	*/
8338	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8339	{
8340	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
8341	}
8342
8343	#endif /* IN_RING3 */
8344
8345	/**
8346	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
8347	*/
8348	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8349	{
8350	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
8351	}
8352
8353	/**
8354	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
8355	*/
8356	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8357	{
8358	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
8359	}
8360
8361	/**
8362	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
8363	*/
8364	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
8365	{
8366	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
8367	}
8368
8369	/**
8370	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
8371	*/
8372	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
8373	{
8374	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
8375	}
8376
8377	/**
8378	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
8379	*/
8380	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
8381	{
8382	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
8383	}
8384
8385	/**
8386	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
8387	*/
8388	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
8389	{
8390	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
8391	}
8392
8393	#ifdef IN_RING3
8394
8395	/**
8396	* Initializes a PDM critical section.
8397	*
8398	* The PDM critical sections are derived from the IPRT critical sections, but
8399	* works in RC and R0 as well.
8400	*
8401	* @returns VBox status code.
8402	* @param pDevIns The device instance.
8403	* @param pCritSect Pointer to the critical section.
8404	* @param SRC_POS Use RT_SRC_POS.
8405	* @param pszNameFmt Format string for naming the critical section.
8406	* For statistics and lock validation.
8407	* @param ... Arguments for the format string.
8408	*/
8409	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
8410	const char *pszNameFmt, ...)
8411	{
8412	int rc;
8413	va_list va;
8414	va_start(va, pszNameFmt);
8415	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8416	va_end(va);
8417	return rc;
8418	}
8419
8420	#endif /* IN_RING3 */
8421
8422	/**
8423	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
8424	*/
8425	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
8426	{
8427	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
8428	}
8429
8430	/**
8431	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
8432	*/
8433	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8434	{
8435	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
8436	}
8437
8438	/**
8439	* Enters a PDM critical section.
8440	*
8441	* @returns VINF_SUCCESS if entered successfully.
8442	* @returns rcBusy when encountering a busy critical section in RC/R0.
8443	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8444	* during the operation.
8445	*
8446	* @param pDevIns The device instance.
8447	* @param pCritSect The PDM critical section to enter.
8448	* @param rcBusy The status code to return when we're in RC or R0
8449	* and the section is busy. Pass VINF_SUCCESS to
8450	* acquired the critical section thru a ring-3
8451	* call if necessary.
8452	*
8453	* @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
8454	* possible failures in ring-0 or at least apply
8455	* PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
8456	* function.
8457	*
8458	* @sa PDMCritSectEnter
8459	*/
8460	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
8461	{
8462	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
8463	}
8464
8465	/**
8466	* Enters a PDM critical section, with location information for debugging.
8467	*
8468	* @returns VINF_SUCCESS if entered successfully.
8469	* @returns rcBusy when encountering a busy critical section in RC/R0.
8470	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8471	* during the operation.
8472	*
8473	* @param pDevIns The device instance.
8474	* @param pCritSect The PDM critical section to enter.
8475	* @param rcBusy The status code to return when we're in RC or R0
8476	* and the section is busy. Pass VINF_SUCCESS to
8477	* acquired the critical section thru a ring-3
8478	* call if necessary.
8479	* @param uId Some kind of locking location ID. Typically a
8480	* return address up the stack. Optional (0).
8481	* @param SRC_POS The source position where to lock is being
8482	* acquired from. Optional.
8483	* @sa PDMCritSectEnterDebug
8484	*/
8485	DECLINLINE(DECL_CHECK_RETURN(int))
8486	PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8487	{
8488	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8489	}
8490
8491	/**
8492	* Try enter a critical section.
8493	*
8494	* @retval VINF_SUCCESS on success.
8495	* @retval VERR_SEM_BUSY if the critsect was owned.
8496	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8497	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8498	* during the operation.
8499	*
8500	* @param pDevIns The device instance.
8501	* @param pCritSect The critical section.
8502	* @sa PDMCritSectTryEnter
8503	*/
8504	DECLINLINE(DECL_CHECK_RETURN(int))
8505	PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8506	{
8507	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
8508	}
8509
8510	/**
8511	* Try enter a critical section, with location information for debugging.
8512	*
8513	* @retval VINF_SUCCESS on success.
8514	* @retval VERR_SEM_BUSY if the critsect was owned.
8515	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8516	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8517	* during the operation.
8518	*
8519	* @param pDevIns The device instance.
8520	* @param pCritSect The critical section.
8521	* @param uId Some kind of locking location ID. Typically a
8522	* return address up the stack. Optional (0).
8523	* @param SRC_POS The source position where to lock is being
8524	* acquired from. Optional.
8525	* @sa PDMCritSectTryEnterDebug
8526	*/
8527	DECLINLINE(DECL_CHECK_RETURN(int))
8528	PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8529	{
8530	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8531	}
8532
8533	/**
8534	* Leaves a critical section entered with PDMCritSectEnter().
8535	*
8536	* @returns Indication whether we really exited the critical section.
8537	* @retval VINF_SUCCESS if we really exited.
8538	* @retval VINF_SEM_NESTED if we only reduced the nesting count.
8539	* @retval VERR_NOT_OWNER if you somehow ignore release assertions.
8540	*
8541	* @param pDevIns The device instance.
8542	* @param pCritSect The PDM critical section to leave.
8543	* @sa PDMCritSectLeave
8544	*/
8545	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8546	{
8547	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
8548	}
8549
8550	/**
8551	* @see PDMCritSectIsOwner
8552	*/
8553	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8554	{
8555	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
8556	}
8557
8558	/**
8559	* @see PDMCritSectIsInitialized
8560	*/
8561	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8562	{
8563	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
8564	}
8565
8566	/**
8567	* @see PDMCritSectHasWaiters
8568	*/
8569	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8570	{
8571	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
8572	}
8573
8574	/**
8575	* @see PDMCritSectGetRecursion
8576	*/
8577	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8578	{
8579	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
8580	}
8581
8582	#if defined(IN_RING3) \|\| defined(IN_RING0)
8583	/**
8584	* @see PDMHCCritSectScheduleExitEvent
8585	*/
8586	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
8587	{
8588	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
8589	}
8590	#endif
8591
8592	/* Strict build: Remap the two enter calls to the debug versions. */
8593	#ifdef VBOX_STRICT
8594	# ifdef IPRT_INCLUDED_asm_h
8595	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8596	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8597	# else
8598	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8599	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8600	# endif
8601	#endif
8602
8603	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8604
8605	/**
8606	* Deletes the critical section.
8607	*
8608	* @returns VBox status code.
8609	* @param pDevIns The device instance.
8610	* @param pCritSect The PDM critical section to destroy.
8611	* @sa PDMR3CritSectDelete
8612	*/
8613	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8614	{
8615	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8616	}
8617
8618	/**
8619	* Initializes a PDM read/write critical section.
8620	*
8621	* The PDM read/write critical sections are derived from the IPRT critical
8622	* sections, but works in RC and R0 as well.
8623	*
8624	* @returns VBox status code.
8625	* @param pDevIns The device instance.
8626	* @param pCritSect Pointer to the read/write critical section.
8627	* @param SRC_POS Use RT_SRC_POS.
8628	* @param pszNameFmt Format string for naming the critical section.
8629	* For statistics and lock validation.
8630	* @param ... Arguments for the format string.
8631	*/
8632	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
8633	const char *pszNameFmt, ...)
8634	{
8635	int rc;
8636	va_list va;
8637	va_start(va, pszNameFmt);
8638	rc = pDevIns->pHlpR3->pfnCritSectRwInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8639	va_end(va);
8640	return rc;
8641	}
8642
8643	/**
8644	* Deletes the read/write critical section.
8645	*
8646	* @returns VBox status code.
8647	* @param pDevIns The device instance.
8648	* @param pCritSect The PDM read/write critical section to destroy.
8649	* @sa PDMR3CritSectRwDelete
8650	*/
8651	DECLINLINE(int) PDMDevHlpCritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8652	{
8653	return pDevIns->pHlpR3->pfnCritSectRwDelete(pDevIns, pCritSect);
8654	}
8655
8656	#endif /* IN_RING3 */
8657
8658	/**
8659	* @sa PDMCritSectRwEnterShared, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8660	*/
8661	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8662	{
8663	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterShared(pDevIns, pCritSect, rcBusy);
8664	}
8665
8666	/**
8667	* @sa PDMCritSectRwEnterSharedDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8668	*/
8669	DECLINLINE(DECL_CHECK_RETURN(int))
8670	PDMDevHlpCritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8671	{
8672	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterSharedDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8673	}
8674
8675	/**
8676	* @sa PDMCritSectRwTryEnterShared
8677	*/
8678	DECLINLINE(DECL_CHECK_RETURN(int))
8679	PDMDevHlpCritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8680	{
8681	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterShared(pDevIns, pCritSect);
8682	}
8683
8684	/**
8685	* @sa PDMCritSectRwTryEnterSharedDebug
8686	*/
8687	DECLINLINE(DECL_CHECK_RETURN(int))
8688	PDMDevHlpCritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8689	{
8690	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterSharedDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8691	}
8692
8693	/**
8694	* @sa PDMCritSectRwLeaveShared
8695	*/
8696	DECLINLINE(int) PDMDevHlpCritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8697	{
8698	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveShared(pDevIns, pCritSect);
8699	}
8700
8701	/**
8702	* @sa PDMCritSectRwEnterExcl, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8703	*/
8704	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8705	{
8706	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy);
8707	}
8708
8709	/**
8710	* @sa PDMCritSectRwEnterExclDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8711	*/
8712	DECLINLINE(DECL_CHECK_RETURN(int))
8713	PDMDevHlpCritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8714	{
8715	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExclDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8716	}
8717
8718	/**
8719	* @sa PDMCritSectRwTryEnterExcl
8720	*/
8721	DECLINLINE(DECL_CHECK_RETURN(int))
8722	PDMDevHlpCritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8723	{
8724	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExcl(pDevIns, pCritSect);
8725	}
8726
8727	/**
8728	* @sa PDMCritSectRwTryEnterExclDebug
8729	*/
8730	DECLINLINE(DECL_CHECK_RETURN(int))
8731	PDMDevHlpCritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8732	{
8733	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExclDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8734	}
8735
8736	/**
8737	* @sa PDMCritSectRwLeaveExcl
8738	*/
8739	DECLINLINE(int) PDMDevHlpCritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8740	{
8741	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveExcl(pDevIns, pCritSect);
8742	}
8743
8744	/**
8745	* @see PDMCritSectRwIsWriteOwner
8746	*/
8747	DECLINLINE(bool) PDMDevHlpCritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8748	{
8749	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsWriteOwner(pDevIns, pCritSect);
8750	}
8751
8752	/**
8753	* @see PDMCritSectRwIsReadOwner
8754	*/
8755	DECLINLINE(bool) PDMDevHlpCritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
8756	{
8757	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsReadOwner(pDevIns, pCritSect, fWannaHear);
8758	}
8759
8760	/**
8761	* @see PDMCritSectRwGetWriteRecursion
8762	*/
8763	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8764	{
8765	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriteRecursion(pDevIns, pCritSect);
8766	}
8767
8768	/**
8769	* @see PDMCritSectRwGetWriterReadRecursion
8770	*/
8771	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8772	{
8773	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriterReadRecursion(pDevIns, pCritSect);
8774	}
8775
8776	/**
8777	* @see PDMCritSectRwGetReadCount
8778	*/
8779	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8780	{
8781	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetReadCount(pDevIns, pCritSect);
8782	}
8783
8784	/**
8785	* @see PDMCritSectRwIsInitialized
8786	*/
8787	DECLINLINE(bool) PDMDevHlpCritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8788	{
8789	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsInitialized(pDevIns, pCritSect);
8790	}
8791
8792	/* Strict build: Remap the two enter calls to the debug versions. */
8793	#ifdef VBOX_STRICT
8794	# ifdef IPRT_INCLUDED_asm_h
8795	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8796	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8797	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8798	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8799	# else
8800	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8801	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8802	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8803	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8804	# endif
8805	#endif
8806
8807	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8808
8809	/**
8810	* @copydoc PDMDEVHLPR3::pfnThreadCreate
8811	*/
8812	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
8813	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
8814	{
8815	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
8816	}
8817
8818	/**
8819	* @copydoc PDMR3ThreadDestroy
8820	* @param pDevIns The device instance.
8821	*/
8822	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
8823	{
8824	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
8825	}
8826
8827	/**
8828	* @copydoc PDMR3ThreadIAmSuspending
8829	* @param pDevIns The device instance.
8830	*/
8831	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8832	{
8833	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
8834	}
8835
8836	/**
8837	* @copydoc PDMR3ThreadIAmRunning
8838	* @param pDevIns The device instance.
8839	*/
8840	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8841	{
8842	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
8843	}
8844
8845	/**
8846	* @copydoc PDMR3ThreadSleep
8847	* @param pDevIns The device instance.
8848	*/
8849	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
8850	{
8851	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
8852	}
8853
8854	/**
8855	* @copydoc PDMR3ThreadSuspend
8856	* @param pDevIns The device instance.
8857	*/
8858	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8859	{
8860	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
8861	}
8862
8863	/**
8864	* @copydoc PDMR3ThreadResume
8865	* @param pDevIns The device instance.
8866	*/
8867	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8868	{
8869	return pDevIns->pHlpR3->pfnThreadResume(pThread);
8870	}
8871
8872	/**
8873	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
8874	*/
8875	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
8876	{
8877	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
8878	}
8879
8880	/**
8881	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
8882	*/
8883	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
8884	{
8885	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
8886	}
8887
8888	/**
8889	* @copydoc PDMDEVHLPR3::pfnA20Set
8890	*/
8891	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
8892	{
8893	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
8894	}
8895
8896	/**
8897	* @copydoc PDMDEVHLPR3::pfnRTCRegister
8898	*/
8899	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
8900	{
8901	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
8902	}
8903
8904	/**
8905	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
8906	*/
8907	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
8908	{
8909	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
8910	}
8911
8912	/**
8913	* @copydoc PDMDEVHLPR3::pfnIommuRegister
8914	*/
8915	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
8916	{
8917	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
8918	}
8919
8920	/**
8921	* @copydoc PDMDEVHLPR3::pfnPICRegister
8922	*/
8923	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8924	{
8925	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
8926	}
8927
8928	/**
8929	* @copydoc PDMDEVHLPR3::pfnApicRegister
8930	*/
8931	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
8932	{
8933	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
8934	}
8935
8936	/**
8937	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
8938	*/
8939	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8940	{
8941	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
8942	}
8943
8944	/**
8945	* @copydoc PDMDEVHLPR3::pfnHpetRegister
8946	*/
8947	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
8948	{
8949	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
8950	}
8951
8952	/**
8953	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
8954	*/
8955	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
8956	{
8957	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
8958	}
8959
8960	/**
8961	* @copydoc PDMDEVHLPR3::pfnDMACRegister
8962	*/
8963	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
8964	{
8965	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
8966	}
8967
8968	/**
8969	* @copydoc PDMDEVHLPR3::pfnDMARegister
8970	*/
8971	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
8972	{
8973	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
8974	}
8975
8976	/**
8977	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
8978	*/
8979	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
8980	{
8981	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
8982	}
8983
8984	/**
8985	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
8986	*/
8987	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
8988	{
8989	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
8990	}
8991
8992	/**
8993	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
8994	*/
8995	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
8996	{
8997	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
8998	}
8999
9000	/**
9001	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
9002	*/
9003	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
9004	{
9005	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
9006	}
9007
9008	/**
9009	* @copydoc PDMDEVHLPR3::pfnDMASchedule
9010	*/
9011	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
9012	{
9013	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
9014	}
9015
9016	/**
9017	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
9018	*/
9019	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
9020	{
9021	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
9022	}
9023
9024	/**
9025	* @copydoc PDMDEVHLPR3::pfnCMOSRead
9026	*/
9027	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
9028	{
9029	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
9030	}
9031
9032	/**
9033	* @copydoc PDMDEVHLPR3::pfnCallR0
9034	*/
9035	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
9036	{
9037	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
9038	}
9039
9040	/**
9041	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
9042	*/
9043	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
9044	{
9045	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
9046	}
9047
9048	/**
9049	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
9050	*/
9051	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
9052	{
9053	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
9054	}
9055
9056	/**
9057	* @copydoc PDMDEVHLPR3::pfnGetUVM
9058	*/
9059	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
9060	{
9061	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
9062	}
9063
9064	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
9065
9066	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
9067
9068	/**
9069	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
9070	*/
9071	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
9072	{
9073	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
9074	}
9075
9076	/**
9077	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
9078	*/
9079	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
9080	{
9081	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
9082	}
9083
9084	/**
9085	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
9086	*/
9087	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
9088	{
9089	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
9090	}
9091
9092	/**
9093	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
9094	*/
9095	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
9096	{
9097	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
9098	}
9099
9100	/**
9101	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
9102	*/
9103	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9104	{
9105	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
9106	}
9107
9108	/**
9109	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
9110	*/
9111	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
9112	{
9113	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
9114	}
9115
9116	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
9117
9118	/**
9119	* @copydoc PDMDEVHLPR3::pfnGetVM
9120	*/
9121	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
9122	{
9123	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
9124	}
9125
9126	/**
9127	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
9128	*/
9129	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
9130	{
9131	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
9132	}
9133
9134	/**
9135	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
9136	*/
9137	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
9138	{
9139	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
9140	}
9141
9142	/**
9143	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
9144	*/
9145	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
9146	{
9147	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
9148	}
9149
9150	/**
9151	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9152	*/
9153	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
9154	{
9155	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
9156	}
9157
9158	/**
9159	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9160	*/
9161	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
9162	{
9163	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
9164	}
9165
9166	#ifdef IN_RING3
9167
9168	/**
9169	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
9170	*/
9171	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
9172	{
9173	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
9174	}
9175
9176	/**
9177	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
9178	*/
9179	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
9180	{
9181	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
9182	}
9183
9184	/**
9185	* @copydoc PDMDEVHLPR3::pfnVMReset
9186	*/
9187	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
9188	{
9189	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
9190	}
9191
9192	/**
9193	* @copydoc PDMDEVHLPR3::pfnVMSuspend
9194	*/
9195	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
9196	{
9197	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
9198	}
9199
9200	/**
9201	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
9202	*/
9203	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
9204	{
9205	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
9206	}
9207
9208	/**
9209	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
9210	*/
9211	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
9212	{
9213	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
9214	}
9215
9216	#endif /* IN_RING3 */
9217
9218	/**
9219	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
9220	*/
9221	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
9222	{
9223	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
9224	}
9225
9226	#ifdef IN_RING3
9227
9228	/**
9229	* @copydoc PDMDEVHLPR3::pfnGetCpuId
9230	*/
9231	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
9232	{
9233	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
9234	}
9235
9236	/**
9237	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
9238	*/
9239	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
9240	{
9241	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
9242	}
9243
9244	/**
9245	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
9246	*/
9247	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
9248	{
9249	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
9250	}
9251
9252	/**
9253	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
9254	*/
9255	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
9256	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
9257	const char pszHandlerR0, const char pszPfHandlerR0,
9258	const char pszHandlerRC, const char pszPfHandlerRC,
9259	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
9260	{
9261	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
9262	pszHandlerR0, pszPfHandlerR0,
9263	pszHandlerRC, pszPfHandlerRC,
9264	pszDesc, phType);
9265	}
9266
9267	/**
9268	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalRegister
9269	*/
9270	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
9271	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
9272	RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc)
9273	{
9274	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalRegister(pDevIns, GCPhys, GCPhysLast, hType,
9275	pvUserR3, pvUserR0, pvUserRC, pszDesc);
9276	}
9277
9278	/**
9279	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalDeregister
9280	*/
9281	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalDeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9282	{
9283	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalDeregister(pDevIns, GCPhys);
9284	}
9285	#endif
9286
9287	/**
9288	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalPageTempOff
9289	*/
9290	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
9291	{
9292	return pDevIns->CTX_SUFF(pHlp)->pfnPGMHandlerPhysicalPageTempOff(pDevIns, GCPhys, GCPhysPage);
9293	}
9294
9295	#ifdef IN_RING3
9296	/**
9297	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalReset
9298	*/
9299	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalReset(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9300	{
9301	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalReset(pDevIns, GCPhys);
9302	}
9303
9304	/**
9305	* @copydoc PDMDEVHLPR3::pfnVMMRegisterPatchMemory
9306	*/
9307	DECLINLINE(int) PDMDevHlpVMMRegisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9308	{
9309	return pDevIns->pHlpR3->pfnVMMRegisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9310	}
9311
9312	/**
9313	* @copydoc PDMDEVHLPR3::pfnVMMDeregisterPatchMemory
9314	*/
9315	DECLINLINE(int) PDMDevHlpVMMDeregisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9316	{
9317	return pDevIns->pHlpR3->pfnVMMDeregisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9318	}
9319
9320	/**
9321	* @copydoc PDMDEVHLPR3::pfnSharedModuleRegister
9322	*/
9323	DECLINLINE(int) PDMDevHlpSharedModuleRegister(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
9324	RTGCPTR GCBaseAddr, uint32_t cbModule,
9325	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions)
9326	{
9327	return pDevIns->pHlpR3->pfnSharedModuleRegister(pDevIns, enmGuestOS, pszModuleName, pszVersion,
9328	GCBaseAddr, cbModule, cRegions, paRegions);
9329	}
9330
9331	/**
9332	* @copydoc PDMDEVHLPR3::pfnSharedModuleUnregister
9333	*/
9334	DECLINLINE(int) PDMDevHlpSharedModuleUnregister(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
9335	RTGCPTR GCBaseAddr, uint32_t cbModule)
9336	{
9337	return pDevIns->pHlpR3->pfnSharedModuleUnregister(pDevIns, pszModuleName, pszVersion, GCBaseAddr, cbModule);
9338	}
9339
9340	/**
9341	* @copydoc PDMDEVHLPR3::pfnSharedModuleGetPageState
9342	*/
9343	DECLINLINE(int) PDMDevHlpSharedModuleGetPageState(PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool *pfShared,
9344	uint64_t *pfPageFlags)
9345	{
9346	return pDevIns->pHlpR3->pfnSharedModuleGetPageState(pDevIns, GCPtrPage, pfShared, pfPageFlags);
9347	}
9348
9349	/**
9350	* @copydoc PDMDEVHLPR3::pfnSharedModuleCheckAll
9351	*/
9352	DECLINLINE(int) PDMDevHlpSharedModuleCheckAll(PPDMDEVINS pDevIns)
9353	{
9354	return pDevIns->pHlpR3->pfnSharedModuleCheckAll(pDevIns);
9355	}
9356
9357	/**
9358	* @copydoc PDMDEVHLPR3::pfnQueryLun
9359	*/
9360	DECLINLINE(int) PDMDevHlpQueryLun(PPDMDEVINS pDevIns, const char pszDevice, unsigned iInstance, unsigned iLun, PPDMIBASE ppBase)
9361	{
9362	return pDevIns->pHlpR3->pfnQueryLun(pDevIns, pszDevice, iInstance, iLun, ppBase);
9363	}
9364
9365	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
9366	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9367	do { \
9368	uint32_t u32GetEnumTmp = 0; \
9369	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
9370	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9371	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
9372	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
9373	} while (0)
9374
9375	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
9376	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9377	do { \
9378	uint8_t bGetEnumTmp = 0; \
9379	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
9380	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9381	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
9382	} while (0)
9383
9384	#endif /* IN_RING3 */
9385
9386	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
9387	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
9388
9389	/**
9390	* Callbacks for VBoxDeviceRegister().
9391	*/
9392	typedef struct PDMDEVREGCB
9393	{
9394	/** Interface version.
9395	* This is set to PDM_DEVREG_CB_VERSION. */
9396	uint32_t u32Version;
9397
9398	/**
9399	* Registers a device with the current VM instance.
9400	*
9401	* @returns VBox status code.
9402	* @param pCallbacks Pointer to the callback table.
9403	* @param pReg Pointer to the device registration record.
9404	* This data must be permanent and readonly.
9405	*/
9406	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
9407	} PDMDEVREGCB;
9408
9409	/** Current version of the PDMDEVREGCB structure. */
9410	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
9411
9412
9413	/**
9414	* The VBoxDevicesRegister callback function.
9415	*
9416	* PDM will invoke this function after loading a device module and letting
9417	* the module decide which devices to register and how to handle conflicts.
9418	*
9419	* @returns VBox status code.
9420	* @param pCallbacks Pointer to the callback table.
9421	* @param u32Version VBox version number.
9422	*/
9423	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
9424
9425	/** @} */
9426
9427	RT_C_DECLS_END
9428
9429	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 91965

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