pdmdev.h@ 92843

Last change on this file since 92843 was 92527, checked in by vboxsync, 3 years ago
VMM/PDMDevHlp: Added PDMDevHlpGetMainExecutionEngine for VMMDevTesting. bugref:9044
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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmcritsectrw.h>
34	#include <VBox/vmm/pdmqueue.h>
35	#include <VBox/vmm/pdmtask.h>
36	#ifdef IN_RING3
37	# include <VBox/vmm/pdmthread.h>
38	#endif
39	#include <VBox/vmm/pdmifs.h>
40	#include <VBox/vmm/pdmins.h>
41	#include <VBox/vmm/pdmcommon.h>
42	#include <VBox/vmm/pdmpcidev.h>
43	#include <VBox/vmm/iom.h>
44	#include <VBox/vmm/mm.h>
45	#include <VBox/vmm/tm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/cfgm.h>
48	#include <VBox/vmm/cpum.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
51	#include <VBox/vmm/gim.h>
52	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
53	#include <VBox/msi.h>
54	#include <iprt/stdarg.h>
55	#include <iprt/list.h>
56
57
58	RT_C_DECLS_BEGIN
59
60	/** @defgroup grp_pdm_device The PDM Devices API
61	* @ingroup grp_pdm
62	* @{
63	*/
64
65	/**
66	* Construct a device instance for a VM.
67	*
68	* @returns VBox status.
69	* @param pDevIns The device instance data. If the registration structure
70	* is needed, it can be accessed thru pDevIns->pReg.
71	* @param iInstance Instance number. Use this to figure out which registers
72	* and such to use. The instance number is also found in
73	* pDevIns->iInstance, but since it's likely to be
74	* frequently used PDM passes it as parameter.
75	* @param pCfg Configuration node handle for the driver. This is
76	* expected to be in high demand in the constructor and is
77	* therefore passed as an argument. When using it at other
78	* times, it can be found in pDevIns->pCfg.
79	*/
80	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
81	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
82	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
83
84	/**
85	* Destruct a device instance.
86	*
87	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
88	* resources can be freed correctly.
89	*
90	* @returns VBox status.
91	* @param pDevIns The device instance data.
92	*
93	* @remarks The device critical section is not entered. The routine may delete
94	* the critical section, so the caller cannot exit it.
95	*/
96	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
97	/** Pointer to a FNPDMDEVDESTRUCT() function. */
98	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
99
100	/**
101	* Device relocation callback.
102	*
103	* This is called when the instance data has been relocated in raw-mode context
104	* (RC). It is also called when the RC hypervisor selects changes. The device
105	* must fixup all necessary pointers and re-query all interfaces to other RC
106	* devices and drivers.
107	*
108	* Before the RC code is executed the first time, this function will be called
109	* with a 0 delta so RC pointer calculations can be one in one place.
110	*
111	* @param pDevIns Pointer to the device instance.
112	* @param offDelta The relocation delta relative to the old location.
113	*
114	* @remarks A relocation CANNOT fail.
115	*
116	* @remarks The device critical section is not entered. The relocations should
117	* not normally require any locking.
118	*/
119	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
120	/** Pointer to a FNPDMDEVRELOCATE() function. */
121	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
122
123	/**
124	* Power On notification.
125	*
126	* @returns VBox status.
127	* @param pDevIns The device instance data.
128	*
129	* @remarks Caller enters the device critical section.
130	*/
131	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
132	/** Pointer to a FNPDMDEVPOWERON() function. */
133	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
134
135	/**
136	* Reset notification.
137	*
138	* @returns VBox status.
139	* @param pDevIns The device instance data.
140	*
141	* @remarks Caller enters the device critical section.
142	*/
143	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
144	/** Pointer to a FNPDMDEVRESET() function. */
145	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
146
147	/**
148	* Soft reset notification.
149	*
150	* This is mainly for emulating the 286 style protected mode exits, in which
151	* most devices should remain in their current state.
152	*
153	* @returns VBox status.
154	* @param pDevIns The device instance data.
155	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
156	*
157	* @remarks Caller enters the device critical section.
158	*/
159	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
160	/** Pointer to a FNPDMDEVSOFTRESET() function. */
161	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
162
163	/** @name PDMVMRESET_F_XXX - VM reset flags.
164	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
165	* reset via PDMDevHlpVMReset.
166	* @{ */
167	/** Unknown reason. */
168	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
169	/** GIM triggered reset. */
170	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
171	/** The last source always causing hard resets. */
172	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
173	/** ACPI triggered reset. */
174	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
175	/** PS/2 system port A (92h) reset. */
176	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
177	/** Keyboard reset. */
178	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
179	/** Tripple fault. */
180	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
181	/** Reset source mask. */
182	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
183	/** @} */
184
185	/**
186	* Suspend notification.
187	*
188	* @returns VBox status.
189	* @param pDevIns The device instance data.
190	* @thread EMT(0)
191	*
192	* @remarks Caller enters the device critical section.
193	*/
194	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
195	/** Pointer to a FNPDMDEVSUSPEND() function. */
196	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
197
198	/**
199	* Resume notification.
200	*
201	* @returns VBox status.
202	* @param pDevIns The device instance data.
203	*
204	* @remarks Caller enters the device critical section.
205	*/
206	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
207	/** Pointer to a FNPDMDEVRESUME() function. */
208	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
209
210	/**
211	* Power Off notification.
212	*
213	* This is always called when VMR3PowerOff is called.
214	* There will be no callback when hot plugging devices.
215	*
216	* @param pDevIns The device instance data.
217	* @thread EMT(0)
218	*
219	* @remarks Caller enters the device critical section.
220	*/
221	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
222	/** Pointer to a FNPDMDEVPOWEROFF() function. */
223	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
224
225	/**
226	* Attach command.
227	*
228	* This is called to let the device attach to a driver for a specified LUN
229	* at runtime. This is not called during VM construction, the device
230	* constructor has to attach to all the available drivers.
231	*
232	* This is like plugging in the keyboard or mouse after turning on the PC.
233	*
234	* @returns VBox status code.
235	* @param pDevIns The device instance.
236	* @param iLUN The logical unit which is being attached.
237	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
238	*
239	* @remarks Caller enters the device critical section.
240	*/
241	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
242	/** Pointer to a FNPDMDEVATTACH() function. */
243	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
244
245	/**
246	* Detach notification.
247	*
248	* This is called when a driver is detaching itself from a LUN of the device.
249	* The device should adjust its state to reflect this.
250	*
251	* This is like unplugging the network cable to use it for the laptop or
252	* something while the PC is still running.
253	*
254	* @param pDevIns The device instance.
255	* @param iLUN The logical unit which is being detached.
256	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
257	*
258	* @remarks Caller enters the device critical section.
259	*/
260	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
261	/** Pointer to a FNPDMDEVDETACH() function. */
262	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
263
264	/**
265	* Query the base interface of a logical unit.
266	*
267	* @returns VBOX status code.
268	* @param pDevIns The device instance.
269	* @param iLUN The logicial unit to query.
270	* @param ppBase Where to store the pointer to the base interface of the LUN.
271	*
272	* @remarks The device critical section is not entered.
273	*/
274	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
275	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
276	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
277
278	/**
279	* Init complete notification (after ring-0 & RC init since 5.1).
280	*
281	* This can be done to do communication with other devices and other
282	* initialization which requires everything to be in place.
283	*
284	* @returns VBOX status code.
285	* @param pDevIns The device instance.
286	*
287	* @remarks Caller enters the device critical section.
288	*/
289	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
290	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
291	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
292
293
294	/**
295	* The context of a pfnMemSetup call.
296	*/
297	typedef enum PDMDEVMEMSETUPCTX
298	{
299	/** Invalid zero value. */
300	PDMDEVMEMSETUPCTX_INVALID = 0,
301	/** After construction. */
302	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
303	/** After reset. */
304	PDMDEVMEMSETUPCTX_AFTER_RESET,
305	/** Type size hack. */
306	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
307	} PDMDEVMEMSETUPCTX;
308
309
310	/**
311	* PDM Device Registration Structure.
312	*
313	* This structure is used when registering a device from VBoxInitDevices() in HC
314	* Ring-3. PDM will continue use till the VM is terminated.
315	*
316	* @note The first part is the same in every context.
317	*/
318	typedef struct PDMDEVREGR3
319	{
320	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
321	uint32_t u32Version;
322	/** Reserved, must be zero. */
323	uint32_t uReserved0;
324	/** Device name, must match the ring-3 one. */
325	char szName[32];
326	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
327	uint32_t fFlags;
328	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
329	uint32_t fClass;
330	/** Maximum number of instances (per VM). */
331	uint32_t cMaxInstances;
332	/** The shared data structure version number. */
333	uint32_t uSharedVersion;
334	/** Size of the instance data. */
335	uint32_t cbInstanceShared;
336	/** Size of the ring-0 instance data. */
337	uint32_t cbInstanceCC;
338	/** Size of the raw-mode instance data. */
339	uint32_t cbInstanceRC;
340	/** Max number of PCI devices. */
341	uint16_t cMaxPciDevices;
342	/** Max number of MSI-X vectors in any of the PCI devices. */
343	uint16_t cMaxMsixVectors;
344	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
345	* remain unchanged from registration till VM destruction. */
346	const char *pszDescription;
347
348	/** Name of the raw-mode context module (no path).
349	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
350	const char *pszRCMod;
351	/** Name of the ring-0 module (no path).
352	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
353	const char *pszR0Mod;
354
355	/** Construct instance - required. */
356	PFNPDMDEVCONSTRUCT pfnConstruct;
357	/** Destruct instance - optional.
358	* Critical section NOT entered (will be destroyed). */
359	PFNPDMDEVDESTRUCT pfnDestruct;
360	/** Relocation command - optional.
361	* Critical section NOT entered. */
362	PFNPDMDEVRELOCATE pfnRelocate;
363	/**
364	* Memory setup callback.
365	*
366	* @param pDevIns The device instance data.
367	* @param enmCtx Indicates the context of the call.
368	* @remarks The critical section is entered prior to calling this method.
369	*/
370	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
371	/** Power on notification - optional.
372	* Critical section is entered. */
373	PFNPDMDEVPOWERON pfnPowerOn;
374	/** Reset notification - optional.
375	* Critical section is entered. */
376	PFNPDMDEVRESET pfnReset;
377	/** Suspend notification - optional.
378	* Critical section is entered. */
379	PFNPDMDEVSUSPEND pfnSuspend;
380	/** Resume notification - optional.
381	* Critical section is entered. */
382	PFNPDMDEVRESUME pfnResume;
383	/** Attach command - optional.
384	* Critical section is entered. */
385	PFNPDMDEVATTACH pfnAttach;
386	/** Detach notification - optional.
387	* Critical section is entered. */
388	PFNPDMDEVDETACH pfnDetach;
389	/** Query a LUN base interface - optional.
390	* Critical section is NOT entered. */
391	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
392	/** Init complete notification - optional.
393	* Critical section is entered. */
394	PFNPDMDEVINITCOMPLETE pfnInitComplete;
395	/** Power off notification - optional.
396	* Critical section is entered. */
397	PFNPDMDEVPOWEROFF pfnPowerOff;
398	/** Software system reset notification - optional.
399	* Critical section is entered. */
400	PFNPDMDEVSOFTRESET pfnSoftReset;
401
402	/** @name Reserved for future extensions, must be zero.
403	* @{ */
404	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
406	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
407	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
408	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
409	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
410	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
411	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
412	/** @} */
413
414	/** Initialization safty marker. */
415	uint32_t u32VersionEnd;
416	} PDMDEVREGR3;
417	/** Pointer to a PDM Device Structure. */
418	typedef PDMDEVREGR3 *PPDMDEVREGR3;
419	/** Const pointer to a PDM Device Structure. */
420	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
421	/** Current DEVREGR3 version number. */
422	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
423
424
425	/** PDM Device Flags.
426	* @{ */
427	/** This flag is used to indicate that the device has a R0 component. */
428	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
429	/** Requires the ring-0 component, ignore configuration values. */
430	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
431	/** Requires the ring-0 component, ignore configuration values. */
432	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
433
434	/** This flag is used to indicate that the device has a RC component. */
435	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
436	/** Requires the raw-mode component, ignore configuration values. */
437	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
438	/** Requires the raw-mode component, ignore configuration values. */
439	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
440
441	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
442	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
443
444	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
445	* The bit count for the current host.
446	* @note Superfluous, but still around for hysterical raisins. */
447	#if HC_ARCH_BITS == 32
448	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
449	#elif HC_ARCH_BITS == 64
450	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
451	#else
452	# error Unsupported HC_ARCH_BITS value.
453	#endif
454	/** The host bit count mask. */
455	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
456
457	/** The device support only 32-bit guests. */
458	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
459	/** The device support only 64-bit guests. */
460	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
461	/** The device support both 32-bit & 64-bit guests. */
462	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
463	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
464	* The guest bit count for the current compilation. */
465	#if GC_ARCH_BITS == 32
466	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
467	#elif GC_ARCH_BITS == 64
468	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
469	#else
470	# error Unsupported GC_ARCH_BITS value.
471	#endif
472	/** The guest bit count mask. */
473	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
474
475	/** A convenience. */
476	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
477
478	/** Indicates that the device needs to be notified before the drivers when suspending. */
479	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
480	/** Indicates that the device needs to be notified before the drivers when powering off. */
481	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
482	/** Indicates that the device needs to be notified before the drivers when resetting. */
483	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
484
485	/** This flag is used to indicate that the device has been converted to the
486	* new device style. */
487	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
488
489	/** @} */
490
491
492	/** PDM Device Classes.
493	* The order is important, lower bit earlier instantiation.
494	* @{ */
495	/** Architecture device. */
496	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
497	/** Architecture BIOS device. */
498	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
499	/** PCI bus brigde. */
500	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
501	/** PCI built-in device (e.g. PCI root complex devices). */
502	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
503	/** Input device (mouse, keyboard, joystick, HID, ...). */
504	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
505	/** Interrupt controller (PIC). */
506	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
507	/** Interval controoler (PIT). */
508	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
509	/** RTC/CMOS. */
510	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
511	/** DMA controller. */
512	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
513	/** VMM Device. */
514	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
515	/** Graphics device, like VGA. */
516	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
517	/** Storage controller device. */
518	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
519	/** Network interface controller. */
520	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
521	/** Audio. */
522	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
523	/** USB HIC. */
524	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
525	/** ACPI. */
526	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
527	/** Serial controller device. */
528	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
529	/** Parallel controller device */
530	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
531	/** Host PCI pass-through device */
532	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
533	/** Misc devices (always last). */
534	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
535	/** @} */
536
537
538	/**
539	* PDM Device Registration Structure, ring-0.
540	*
541	* This structure is used when registering a device from VBoxInitDevices() in HC
542	* Ring-0. PDM will continue use till the VM is terminated.
543	*/
544	typedef struct PDMDEVREGR0
545	{
546	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
547	uint32_t u32Version;
548	/** Reserved, must be zero. */
549	uint32_t uReserved0;
550	/** Device name, must match the ring-3 one. */
551	char szName[32];
552	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
553	uint32_t fFlags;
554	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
555	uint32_t fClass;
556	/** Maximum number of instances (per VM). */
557	uint32_t cMaxInstances;
558	/** The shared data structure version number. */
559	uint32_t uSharedVersion;
560	/** Size of the instance data. */
561	uint32_t cbInstanceShared;
562	/** Size of the ring-0 instance data. */
563	uint32_t cbInstanceCC;
564	/** Size of the raw-mode instance data. */
565	uint32_t cbInstanceRC;
566	/** Max number of PCI devices. */
567	uint16_t cMaxPciDevices;
568	/** Max number of MSI-X vectors in any of the PCI devices. */
569	uint16_t cMaxMsixVectors;
570	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
571	* remain unchanged from registration till VM destruction. */
572	const char *pszDescription;
573
574	/**
575	* Early construction callback (optional).
576	*
577	* This is called right after the device instance structure has been allocated
578	* and before the ring-3 constructor gets called.
579	*
580	* @returns VBox status code.
581	* @param pDevIns The device instance data.
582	* @note The destructure is always called, regardless of the return status.
583	*/
584	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
585
586	/**
587	* Regular construction callback (optional).
588	*
589	* This is called after (or during) the ring-3 constructor.
590	*
591	* @returns VBox status code.
592	* @param pDevIns The device instance data.
593	* @note The destructure is always called, regardless of the return status.
594	*/
595	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
596
597	/**
598	* Destructor (optional).
599	*
600	* This is called after the ring-3 destruction. This is not called if ring-3
601	* fails to trigger it (e.g. process is killed or crashes).
602	*
603	* @param pDevIns The device instance data.
604	*/
605	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
606
607	/**
608	* Final destructor (optional).
609	*
610	* This is called right before the memory is freed, which happens when the
611	* VM/GVM object is destroyed. This is always called.
612	*
613	* @param pDevIns The device instance data.
614	*/
615	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
616
617	/**
618	* Generic request handler (optional).
619	*
620	* @param pDevIns The device instance data.
621	* @param uReq Device specific request.
622	* @param uArg Request argument.
623	*/
624	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
625
626	/** @name Reserved for future extensions, must be zero.
627	* @{ */
628	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
630	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
631	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
632	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
633	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
634	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
635	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
636	/** @} */
637
638	/** Initialization safty marker. */
639	uint32_t u32VersionEnd;
640	} PDMDEVREGR0;
641	/** Pointer to a ring-0 PDM device registration structure. */
642	typedef PDMDEVREGR0 *PPDMDEVREGR0;
643	/** Pointer to a const ring-0 PDM device registration structure. */
644	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
645	/** Current DEVREGR0 version number. */
646	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
647
648
649	/**
650	* PDM Device Registration Structure, raw-mode
651	*
652	* At the moment, this structure is mostly here to match the other two contexts.
653	*/
654	typedef struct PDMDEVREGRC
655	{
656	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
657	uint32_t u32Version;
658	/** Reserved, must be zero. */
659	uint32_t uReserved0;
660	/** Device name, must match the ring-3 one. */
661	char szName[32];
662	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
663	uint32_t fFlags;
664	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
665	uint32_t fClass;
666	/** Maximum number of instances (per VM). */
667	uint32_t cMaxInstances;
668	/** The shared data structure version number. */
669	uint32_t uSharedVersion;
670	/** Size of the instance data. */
671	uint32_t cbInstanceShared;
672	/** Size of the ring-0 instance data. */
673	uint32_t cbInstanceCC;
674	/** Size of the raw-mode instance data. */
675	uint32_t cbInstanceRC;
676	/** Max number of PCI devices. */
677	uint16_t cMaxPciDevices;
678	/** Max number of MSI-X vectors in any of the PCI devices. */
679	uint16_t cMaxMsixVectors;
680	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
681	* remain unchanged from registration till VM destruction. */
682	const char *pszDescription;
683
684	/**
685	* Constructor callback.
686	*
687	* This is called much later than both the ring-0 and ring-3 constructors, since
688	* raw-mode v2 require a working VMM to run actual code.
689	*
690	* @returns VBox status code.
691	* @param pDevIns The device instance data.
692	* @note The destructure is always called, regardless of the return status.
693	*/
694	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
695
696	/** @name Reserved for future extensions, must be zero.
697	* @{ */
698	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
700	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
701	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
702	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
703	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
704	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
705	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
706	/** @} */
707
708	/** Initialization safty marker. */
709	uint32_t u32VersionEnd;
710	} PDMDEVREGRC;
711	/** Pointer to a raw-mode PDM device registration structure. */
712	typedef PDMDEVREGRC *PPDMDEVREGRC;
713	/** Pointer to a const raw-mode PDM device registration structure. */
714	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
715	/** Current DEVREGRC version number. */
716	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
717
718
719
720	/** @def PDM_DEVREG_VERSION
721	* Current DEVREG version number. */
722	/** @typedef PDMDEVREGR3
723	* A current context PDM device registration structure. */
724	/** @typedef PPDMDEVREGR3
725	* Pointer to a current context PDM device registration structure. */
726	/** @typedef PCPDMDEVREGR3
727	* Pointer to a const current context PDM device registration structure. */
728	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
729	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
730	typedef PDMDEVREGR3 PDMDEVREG;
731	typedef PPDMDEVREGR3 PPDMDEVREG;
732	typedef PCPDMDEVREGR3 PCPDMDEVREG;
733	#elif defined(IN_RING0)
734	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
735	typedef PDMDEVREGR0 PDMDEVREG;
736	typedef PPDMDEVREGR0 PPDMDEVREG;
737	typedef PCPDMDEVREGR0 PCPDMDEVREG;
738	#elif defined(IN_RC)
739	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
740	typedef PDMDEVREGRC PDMDEVREG;
741	typedef PPDMDEVREGRC PPDMDEVREG;
742	typedef PCPDMDEVREGRC PCPDMDEVREG;
743	#else
744	# error "Not IN_RING3, IN_RING0 or IN_RC"
745	#endif
746
747
748	/**
749	* Device registrations for ring-0 modules.
750	*
751	* This structure is used directly and must therefore reside in persistent
752	* memory (i.e. the data section).
753	*/
754	typedef struct PDMDEVMODREGR0
755	{
756	/** The structure version (PDM_DEVMODREGR0_VERSION). */
757	uint32_t u32Version;
758	/** Number of devices in the array papDevRegs points to. */
759	uint32_t cDevRegs;
760	/** Pointer to device registration structures. */
761	PCPDMDEVREGR0 *papDevRegs;
762	/** The ring-0 module handle - PDM internal, fingers off. */
763	void *hMod;
764	/** List entry - PDM internal, fingers off. */
765	RTLISTNODE ListEntry;
766	} PDMDEVMODREGR0;
767	/** Pointer to device registriations for a ring-0 module. */
768	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
769	/** Current PDMDEVMODREGR0 version number. */
770	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
771
772
773	/** @name IRQ Level for use with the *SetIrq APIs.
774	* @{
775	*/
776	/** Assert the IRQ (can assume value 1). */
777	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
778	/** Deassert the IRQ (can assume value 0). */
779	#define PDM_IRQ_LEVEL_LOW 0
780	/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
781	* automatically deasserts it after delivery to the APIC (IOAPIC).
782	* @note Only suitable for edge trigger interrupts. */
783	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
784	/** @} */
785
786	/**
787	* Registration record for MSI/MSI-X emulation.
788	*/
789	typedef struct PDMMSIREG
790	{
791	/** Number of MSI interrupt vectors, 0 if MSI not supported */
792	uint16_t cMsiVectors;
793	/** Offset of MSI capability */
794	uint8_t iMsiCapOffset;
795	/** Offset of next capability to MSI */
796	uint8_t iMsiNextOffset;
797	/** If we support 64-bit MSI addressing */
798	bool fMsi64bit;
799	/** If we do not support per-vector masking */
800	bool fMsiNoMasking;
801
802	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
803	uint16_t cMsixVectors;
804	/** Offset of MSI-X capability */
805	uint8_t iMsixCapOffset;
806	/** Offset of next capability to MSI-X */
807	uint8_t iMsixNextOffset;
808	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
809	uint8_t iMsixBar;
810	} PDMMSIREG;
811	typedef PDMMSIREG *PPDMMSIREG;
812
813	/**
814	* PCI Bus registration structure.
815	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
816	*/
817	typedef struct PDMPCIBUSREGR3
818	{
819	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
820	uint32_t u32Version;
821
822	/**
823	* Registers the device with the default PCI bus.
824	*
825	* @returns VBox status code.
826	* @param pDevIns Device instance of the PCI Bus.
827	* @param pPciDev The PCI device structure.
828	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
829	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
830	* device number (0-31).
831	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
832	* function number (0-7).
833	* @param pszName Device name (static but not unique).
834	*
835	* @remarks Caller enters the PDM critical section.
836	*/
837	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
838	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
839
840	/**
841	* Initialize MSI or MSI-X emulation support in a PCI device.
842	*
843	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
844	* vast majority of device emulation it covers everything necessary. It's
845	* fully automatic, taking care of all BAR and config space requirements,
846	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
847	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
848	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
849	*
850	* A device not using this can still offer MSI/MSI-X. In this case it's
851	* completely up to the device (in the MSI-X case) to create/register the
852	* necessary MMIO BAR, handle all config space/BAR updating and take care
853	* of delivering the interrupts appropriately.
854	*
855	* @returns VBox status code.
856	* @param pDevIns Device instance of the PCI Bus.
857	* @param pPciDev The PCI device structure.
858	* @param pMsiReg MSI emulation registration structure
859	* @remarks Caller enters the PDM critical section.
860	*/
861	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
862
863	/**
864	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
865	*
866	* @returns VBox status code.
867	* @param pDevIns Device instance of the PCI Bus.
868	* @param pPciDev The PCI device structure.
869	* @param iRegion The region number.
870	* @param cbRegion Size of the region.
871	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
872	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
873	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
874	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
875	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
876	* @a fFlags, UINT64_MAX if no handle is passed
877	* (old style).
878	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
879	* is given.
880	* @remarks Caller enters the PDM critical section.
881	*/
882	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
883	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
884	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
885
886	/**
887	* Register PCI configuration space read/write intercept callbacks.
888	*
889	* @param pDevIns Device instance of the PCI Bus.
890	* @param pPciDev The PCI device structure.
891	* @param pfnRead Pointer to the user defined PCI config read function.
892	* @param pfnWrite Pointer to the user defined PCI config write function.
893	* to call default PCI config write function. Can be NULL.
894	* @remarks Caller enters the PDM critical section.
895	* @thread EMT
896	*/
897	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
898	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
899
900	/**
901	* Perform a PCI configuration space write, bypassing interception.
902	*
903	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
904	*
905	* @returns Strict VBox status code (mainly DBGFSTOP).
906	* @param pDevIns Device instance of the PCI Bus.
907	* @param pPciDev The PCI device which config space is being read.
908	* @param uAddress The config space address.
909	* @param cb The size of the read: 1, 2 or 4 bytes.
910	* @param u32Value The value to write.
911	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
912	* that the (root) bus will have done that already.
913	*/
914	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
915	uint32_t uAddress, unsigned cb, uint32_t u32Value));
916
917	/**
918	* Perform a PCI configuration space read, bypassing interception.
919	*
920	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
921	*
922	* @returns Strict VBox status code (mainly DBGFSTOP).
923	* @param pDevIns Device instance of the PCI Bus.
924	* @param pPciDev The PCI device which config space is being read.
925	* @param uAddress The config space address.
926	* @param cb The size of the read: 1, 2 or 4 bytes.
927	* @param pu32Value Where to return the value.
928	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
929	* that the (root) bus will have done that already.
930	*/
931	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
932	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
933
934	/**
935	* Set the IRQ for a PCI device.
936	*
937	* @param pDevIns Device instance of the PCI Bus.
938	* @param pPciDev The PCI device structure.
939	* @param iIrq IRQ number to set.
940	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
941	* @param uTagSrc The IRQ tag and source (for tracing).
942	* @remarks Caller enters the PDM critical section.
943	*/
944	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
945
946	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
947	uint32_t u32EndVersion;
948	} PDMPCIBUSREGR3;
949	/** Pointer to a PCI bus registration structure. */
950	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
951	/** Current PDMPCIBUSREGR3 version number. */
952	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
953
954	/**
955	* PCI Bus registration structure for ring-0.
956	*/
957	typedef struct PDMPCIBUSREGR0
958	{
959	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
960	uint32_t u32Version;
961	/** The PCI bus number (from ring-3 registration). */
962	uint32_t iBus;
963	/**
964	* Set the IRQ for a PCI device.
965	*
966	* @param pDevIns Device instance of the PCI Bus.
967	* @param pPciDev The PCI device structure.
968	* @param iIrq IRQ number to set.
969	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
970	* @param uTagSrc The IRQ tag and source (for tracing).
971	* @remarks Caller enters the PDM critical section.
972	*/
973	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
974	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
975	uint32_t u32EndVersion;
976	} PDMPCIBUSREGR0;
977	/** Pointer to a PCI bus ring-0 registration structure. */
978	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
979	/** Current PDMPCIBUSREGR0 version number. */
980	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
981
982	/**
983	* PCI Bus registration structure for raw-mode.
984	*/
985	typedef struct PDMPCIBUSREGRC
986	{
987	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
988	uint32_t u32Version;
989	/** The PCI bus number (from ring-3 registration). */
990	uint32_t iBus;
991	/**
992	* Set the IRQ for a PCI device.
993	*
994	* @param pDevIns Device instance of the PCI Bus.
995	* @param pPciDev The PCI device structure.
996	* @param iIrq IRQ number to set.
997	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
998	* @param uTagSrc The IRQ tag and source (for tracing).
999	* @remarks Caller enters the PDM critical section.
1000	*/
1001	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
1002	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1003	uint32_t u32EndVersion;
1004	} PDMPCIBUSREGRC;
1005	/** Pointer to a PCI bus raw-mode registration structure. */
1006	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1007	/** Current PDMPCIBUSREGRC version number. */
1008	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1009
1010	/** PCI bus registration structure for the current context. */
1011	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1012	/** Pointer to a PCI bus registration structure for the current context. */
1013	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1014	/** PCI bus registration structure version for the current context. */
1015	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1016
1017
1018	/**
1019	* PCI Bus RC helpers.
1020	*/
1021	typedef struct PDMPCIHLPRC
1022	{
1023	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1024	uint32_t u32Version;
1025
1026	/**
1027	* Set an ISA IRQ.
1028	*
1029	* @param pDevIns PCI device instance.
1030	* @param iIrq IRQ number to set.
1031	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1032	* @param uTagSrc The IRQ tag and source (for tracing).
1033	* @thread EMT only.
1034	*/
1035	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1036
1037	/**
1038	* Set an I/O-APIC IRQ.
1039	*
1040	* @param pDevIns PCI device instance.
1041	* @param uBusDevFn The bus:device:function of the device initiating the
1042	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1043	* interrupt.
1044	* @param iIrq IRQ number to set.
1045	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1046	* @param uTagSrc The IRQ tag and source (for tracing).
1047	* @thread EMT only.
1048	*/
1049	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1050
1051	/**
1052	* Send an MSI.
1053	*
1054	* @param pDevIns PCI device instance.
1055	* @param uBusDevFn The bus:device:function of the device initiating the
1056	* MSI. Cannot be NIL_PCIBDF.
1057	* @param pMsi The MSI to send.
1058	* @param uTagSrc The IRQ tag and source (for tracing).
1059	* @thread EMT only.
1060	*/
1061	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1062
1063
1064	/**
1065	* Acquires the PDM lock.
1066	*
1067	* @returns VINF_SUCCESS on success.
1068	* @returns rc if we failed to acquire the lock.
1069	* @param pDevIns The PCI device instance.
1070	* @param rc What to return if we fail to acquire the lock.
1071	*
1072	* @sa PDMCritSectEnter
1073	*/
1074	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1075
1076	/**
1077	* Releases the PDM lock.
1078	*
1079	* @param pDevIns The PCI device instance.
1080	*/
1081	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1082
1083	/**
1084	* Gets a bus by it's PDM ordinal (typically the parent bus).
1085	*
1086	* @returns Pointer to the device instance of the bus.
1087	* @param pDevIns The PCI bus device instance.
1088	* @param idxPdmBus The PDM ordinal value of the bus to get.
1089	*/
1090	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1091
1092	/** Just a safety precaution. */
1093	uint32_t u32TheEnd;
1094	} PDMPCIHLPRC;
1095	/** Pointer to PCI helpers. */
1096	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1097	/** Pointer to const PCI helpers. */
1098	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1099
1100	/** Current PDMPCIHLPRC version number. */
1101	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1102
1103
1104	/**
1105	* PCI Bus R0 helpers.
1106	*/
1107	typedef struct PDMPCIHLPR0
1108	{
1109	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1110	uint32_t u32Version;
1111
1112	/**
1113	* Set an ISA IRQ.
1114	*
1115	* @param pDevIns PCI device instance.
1116	* @param iIrq IRQ number to set.
1117	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1118	* @param uTagSrc The IRQ tag and source (for tracing).
1119	* @thread EMT only.
1120	*/
1121	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1122
1123	/**
1124	* Set an I/O-APIC IRQ.
1125	*
1126	* @param pDevIns PCI device instance.
1127	* @param uBusDevFn The bus:device:function of the device initiating the
1128	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1129	* interrupt.
1130	* @param iIrq IRQ number to set.
1131	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1132	* @param uTagSrc The IRQ tag and source (for tracing).
1133	* @thread EMT only.
1134	*/
1135	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1136
1137	/**
1138	* Send an MSI.
1139	*
1140	* @param pDevIns PCI device instance.
1141	* @param uBusDevFn The bus:device:function of the device initiating the
1142	* MSI. Cannot be NIL_PCIBDF.
1143	* @param pMsi The MSI to send.
1144	* @param uTagSrc The IRQ tag and source (for tracing).
1145	* @thread EMT only.
1146	*/
1147	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1148
1149	/**
1150	* Acquires the PDM lock.
1151	*
1152	* @returns VINF_SUCCESS on success.
1153	* @returns rc if we failed to acquire the lock.
1154	* @param pDevIns The PCI device instance.
1155	* @param rc What to return if we fail to acquire the lock.
1156	*
1157	* @sa PDMCritSectEnter
1158	*/
1159	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1160
1161	/**
1162	* Releases the PDM lock.
1163	*
1164	* @param pDevIns The PCI device instance.
1165	*/
1166	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1167
1168	/**
1169	* Gets a bus by it's PDM ordinal (typically the parent bus).
1170	*
1171	* @returns Pointer to the device instance of the bus.
1172	* @param pDevIns The PCI bus device instance.
1173	* @param idxPdmBus The PDM ordinal value of the bus to get.
1174	*/
1175	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1176
1177	/** Just a safety precaution. */
1178	uint32_t u32TheEnd;
1179	} PDMPCIHLPR0;
1180	/** Pointer to PCI helpers. */
1181	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1182	/** Pointer to const PCI helpers. */
1183	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1184
1185	/** Current PDMPCIHLPR0 version number. */
1186	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1187
1188	/**
1189	* PCI device helpers.
1190	*/
1191	typedef struct PDMPCIHLPR3
1192	{
1193	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1194	uint32_t u32Version;
1195
1196	/**
1197	* Set an ISA IRQ.
1198	*
1199	* @param pDevIns The PCI device instance.
1200	* @param iIrq IRQ number to set.
1201	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1202	* @param uTagSrc The IRQ tag and source (for tracing).
1203	*/
1204	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1205
1206	/**
1207	* Set an I/O-APIC IRQ.
1208	*
1209	* @param pDevIns The PCI device instance.
1210	* @param uBusDevFn The bus:device:function of the device initiating the
1211	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1212	* interrupt.
1213	* @param iIrq IRQ number to set.
1214	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1215	* @param uTagSrc The IRQ tag and source (for tracing).
1216	*/
1217	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1218
1219	/**
1220	* Send an MSI.
1221	*
1222	* @param pDevIns PCI device instance.
1223	* @param uBusDevFn The bus:device:function of the device initiating the
1224	* MSI. Cannot be NIL_PCIBDF.
1225	* @param pMsi The MSI to send.
1226	* @param uTagSrc The IRQ tag and source (for tracing).
1227	*/
1228	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1229
1230	/**
1231	* Acquires the PDM lock.
1232	*
1233	* @returns VINF_SUCCESS on success.
1234	* @returns Fatal error on failure.
1235	* @param pDevIns The PCI device instance.
1236	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1237	*
1238	* @sa PDMCritSectEnter
1239	*/
1240	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1241
1242	/**
1243	* Releases the PDM lock.
1244	*
1245	* @param pDevIns The PCI device instance.
1246	*/
1247	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1248
1249	/**
1250	* Gets a bus by it's PDM ordinal (typically the parent bus).
1251	*
1252	* @returns Pointer to the device instance of the bus.
1253	* @param pDevIns The PCI bus device instance.
1254	* @param idxPdmBus The PDM ordinal value of the bus to get.
1255	*/
1256	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1257
1258	/** Just a safety precaution. */
1259	uint32_t u32TheEnd;
1260	} PDMPCIHLPR3;
1261	/** Pointer to PCI helpers. */
1262	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1263	/** Pointer to const PCI helpers. */
1264	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1265
1266	/** Current PDMPCIHLPR3 version number. */
1267	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1268
1269
1270	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1271	* These flags are used for memory access transactions via the IOMMU interface.
1272	* @{ */
1273	/** Memory read. */
1274	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1275	/** Memory write. */
1276	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1277	/** Valid flag mask. */
1278	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1279	/** @} */
1280
1281	/**
1282	* IOMMU registration structure for ring-0.
1283	*/
1284	typedef struct PDMIOMMUREGR0
1285	{
1286	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1287	* version. */
1288	uint32_t u32Version;
1289	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1290	uint32_t idxIommu;
1291
1292	/**
1293	* Translates the physical address for a memory transaction through the IOMMU.
1294	*
1295	* @returns VBox status code.
1296	* @param pDevIns The IOMMU device instance.
1297	* @param idDevice The device identifier (bus, device, function).
1298	* @param uIova The I/O virtual address being accessed.
1299	* @param cbIova The size of the access.
1300	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1301	* @param pGCPhysSpa Where to store the translated system physical address.
1302	* @param pcbContiguous Where to store the number of contiguous bytes translated
1303	* and permission-checked.
1304	*
1305	* @thread Any.
1306	*/
1307	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1308	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1309
1310	/**
1311	* Translates in bulk physical page addresses for memory transactions through the
1312	* IOMMU.
1313	*
1314	* @returns VBox status code.
1315	* @param pDevIns The IOMMU device instance.
1316	* @param idDevice The device identifier (bus, device, function).
1317	* @param cIovas The number of I/O virtual addresses being accessed.
1318	* @param pauIovas The I/O virtual addresses being accessed.
1319	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1320	* @param paGCPhysSpa Where to store the translated system physical page
1321	* addresses.
1322	*
1323	* @thread Any.
1324	*/
1325	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1326	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1327
1328	/**
1329	* Performs an interrupt remap request through the IOMMU.
1330	*
1331	* @returns VBox status code.
1332	* @param pDevIns The IOMMU device instance.
1333	* @param idDevice The device identifier (bus, device, function).
1334	* @param pMsiIn The source MSI.
1335	* @param pMsiOut Where to store the remapped MSI.
1336	*
1337	* @thread Any.
1338	*/
1339	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1340
1341	/** Just a safety precaution. */
1342	uint32_t u32TheEnd;
1343	} PDMIOMMUREGR0;
1344	/** Pointer to a IOMMU registration structure. */
1345	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1346
1347	/** Current PDMIOMMUREG version number. */
1348	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1349
1350
1351	/**
1352	* IOMMU registration structure for raw-mode.
1353	*/
1354	typedef struct PDMIOMMUREGRC
1355	{
1356	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1357	* version. */
1358	uint32_t u32Version;
1359	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1360	uint32_t idxIommu;
1361
1362	/**
1363	* Translates the physical address for a memory transaction through the IOMMU.
1364	*
1365	* @returns VBox status code.
1366	* @param pDevIns The IOMMU device instance.
1367	* @param idDevice The device identifier (bus, device, function).
1368	* @param uIova The I/O virtual address being accessed.
1369	* @param cbIova The size of the access.
1370	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1371	* @param pGCPhysSpa Where to store the translated system physical address.
1372	* @param pcbContiguous Where to store the number of contiguous bytes translated
1373	* and permission-checked.
1374	*
1375	* @thread Any.
1376	*/
1377	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1378	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1379
1380	/**
1381	* Translates in bulk physical page addresses for memory transactions through the
1382	* IOMMU.
1383	*
1384	* @returns VBox status code.
1385	* @param pDevIns The IOMMU device instance.
1386	* @param idDevice The device identifier (bus, device, function).
1387	* @param cIovas The number of I/O virtual addresses being accessed.
1388	* @param pauIovas The I/O virtual addresses being accessed.
1389	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1390	* @param paGCPhysSpa Where to store the translated system physical page
1391	* addresses.
1392	*
1393	* @thread Any.
1394	*/
1395	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1396	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1397
1398	/**
1399	* Performs an interrupt remap request through the IOMMU.
1400	*
1401	* @returns VBox status code.
1402	* @param pDevIns The IOMMU device instance.
1403	* @param idDevice The device identifier (bus, device, function).
1404	* @param pMsiIn The source MSI.
1405	* @param pMsiOut Where to store the remapped MSI.
1406	*
1407	* @thread Any.
1408	*/
1409	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1410
1411	/** Just a safety precaution. */
1412	uint32_t u32TheEnd;
1413	} PDMIOMMUREGRC;
1414	/** Pointer to a IOMMU registration structure. */
1415	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1416
1417	/** Current PDMIOMMUREG version number. */
1418	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1419
1420
1421	/**
1422	* IOMMU registration structure for ring-3.
1423	*/
1424	typedef struct PDMIOMMUREGR3
1425	{
1426	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1427	* version. */
1428	uint32_t u32Version;
1429	/** Padding. */
1430	uint32_t uPadding0;
1431
1432	/**
1433	* Translates the physical address for a memory transaction through the IOMMU.
1434	*
1435	* @returns VBox status code.
1436	* @param pDevIns The IOMMU device instance.
1437	* @param idDevice The device identifier (bus, device, function).
1438	* @param uIova The I/O virtual address being accessed.
1439	* @param cbIova The size of the access.
1440	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1441	* @param pGCPhysSpa Where to store the translated system physical address.
1442	* @param pcbContiguous Where to store the number of contiguous bytes translated
1443	* and permission-checked.
1444	*
1445	* @thread Any.
1446	*/
1447	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1448	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1449
1450	/**
1451	* Translates in bulk physical page addresses for memory transactions through the
1452	* IOMMU.
1453	*
1454	* @returns VBox status code.
1455	* @param pDevIns The IOMMU device instance.
1456	* @param idDevice The device identifier (bus, device, function).
1457	* @param cIovas The number of I/O virtual addresses being accessed.
1458	* @param pauIovas The I/O virtual addresses being accessed.
1459	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1460	* @param paGCPhysSpa Where to store the translated system physical page
1461	* addresses.
1462	*
1463	* @thread Any.
1464	*/
1465	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1466	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1467
1468	/**
1469	* Performs an interrupt remap request through the IOMMU.
1470	*
1471	* @returns VBox status code.
1472	* @param pDevIns The IOMMU device instance.
1473	* @param idDevice The device identifier (bus, device, function).
1474	* @param pMsiIn The source MSI.
1475	* @param pMsiOut Where to store the remapped MSI.
1476	*
1477	* @thread Any.
1478	*/
1479	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1480
1481	/** Just a safety precaution. */
1482	uint32_t u32TheEnd;
1483	} PDMIOMMUREGR3;
1484	/** Pointer to a IOMMU registration structure. */
1485	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1486
1487	/** Current PDMIOMMUREG version number. */
1488	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1489
1490	/** IOMMU registration structure for the current context. */
1491	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1492	/** Pointer to an IOMMU registration structure for the current context. */
1493	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1494	/** IOMMU registration structure version for the current context. */
1495	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1496
1497
1498	/**
1499	* IOMMU helpers for ring-0.
1500	*/
1501	typedef struct PDMIOMMUHLPR0
1502	{
1503	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1504	uint32_t u32Version;
1505
1506	/**
1507	* Acquires the PDM lock.
1508	*
1509	* @returns VINF_SUCCESS on success.
1510	* @returns rc if we failed to acquire the lock.
1511	* @param pDevIns The PCI device instance.
1512	* @param rc What to return if we fail to acquire the lock.
1513	*
1514	* @sa PDMCritSectEnter
1515	*/
1516	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1517
1518	/**
1519	* Releases the PDM lock.
1520	*
1521	* @param pDevIns The PCI device instance.
1522	*/
1523	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1524
1525	/**
1526	* Check whether the calling thread owns the PDM lock.
1527	*
1528	* @returns @c true if the PDM lock is owned, @c false otherwise.
1529	* @param pDevIns The PCI device instance.
1530	*/
1531	DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1532
1533	/**
1534	* Send an MSI (when generated by the IOMMU device itself).
1535	*
1536	* @param pDevIns PCI device instance.
1537	* @param pMsi The MSI to send.
1538	* @param uTagSrc The IRQ tag and source (for tracing).
1539	*/
1540	DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1541
1542	/** Just a safety precaution. */
1543	uint32_t u32TheEnd;
1544	} PDMIOMMUHLPR0;
1545	/** Pointer to IOMMU helpers for ring-0. */
1546	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1547	/** Pointer to const IOMMU helpers for ring-0. */
1548	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1549
1550	/** Current PDMIOMMUHLPR0 version number. */
1551	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1552
1553
1554	/**
1555	* IOMMU helpers for raw-mode.
1556	*/
1557	typedef struct PDMIOMMUHLPRC
1558	{
1559	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1560	uint32_t u32Version;
1561
1562	/**
1563	* Acquires the PDM lock.
1564	*
1565	* @returns VINF_SUCCESS on success.
1566	* @returns rc if we failed to acquire the lock.
1567	* @param pDevIns The PCI device instance.
1568	* @param rc What to return if we fail to acquire the lock.
1569	*
1570	* @sa PDMCritSectEnter
1571	*/
1572	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1573
1574	/**
1575	* Releases the PDM lock.
1576	*
1577	* @param pDevIns The PCI device instance.
1578	*/
1579	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1580
1581	/**
1582	* Check whether the threads owns the PDM lock.
1583	*
1584	* @returns @c true if the PDM lock is owned, @c false otherwise.
1585	* @param pDevIns The PCI device instance.
1586	*/
1587	DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1588
1589	/**
1590	* Send an MSI (when generated by the IOMMU device itself).
1591	*
1592	* @param pDevIns PCI device instance.
1593	* @param pMsi The MSI to send.
1594	* @param uTagSrc The IRQ tag and source (for tracing).
1595	*/
1596	DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1597
1598	/** Just a safety precaution. */
1599	uint32_t u32TheEnd;
1600	} PDMIOMMUHLPRC;
1601	/** Pointer to IOMMU helpers for raw-mode. */
1602	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1603	/** Pointer to const IOMMU helpers for raw-mode. */
1604	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1605
1606	/** Current PDMIOMMUHLPRC version number. */
1607	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1608
1609
1610	/**
1611	* IOMMU helpers for ring-3.
1612	*/
1613	typedef struct PDMIOMMUHLPR3
1614	{
1615	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1616	uint32_t u32Version;
1617
1618	/**
1619	* Acquires the PDM lock.
1620	*
1621	* @returns VINF_SUCCESS on success.
1622	* @returns rc if we failed to acquire the lock.
1623	* @param pDevIns The PCI device instance.
1624	* @param rc What to return if we fail to acquire the lock.
1625	*
1626	* @sa PDMCritSectEnter
1627	*/
1628	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1629
1630	/**
1631	* Releases the PDM lock.
1632	*
1633	* @param pDevIns The PCI device instance.
1634	*/
1635	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1636
1637	/**
1638	* Check whether the threads owns the PDM lock.
1639	*
1640	* @returns @c true if the PDM lock is owned, @c false otherwise.
1641	* @param pDevIns The PCI device instance.
1642	*/
1643	DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1644
1645	/**
1646	* Send an MSI (when generated by the IOMMU device itself).
1647	*
1648	* @param pDevIns PCI device instance.
1649	* @param pMsi The MSI to send.
1650	* @param uTagSrc The IRQ tag and source (for tracing).
1651	*/
1652	DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1653
1654	/** Just a safety precaution. */
1655	uint32_t u32TheEnd;
1656	} PDMIOMMUHLPR3;
1657	/** Pointer to IOMMU helpers for raw-mode. */
1658	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1659	/** Pointer to const IOMMU helpers for raw-mode. */
1660	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1661
1662	/** Current PDMIOMMUHLPR3 version number. */
1663	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1664
1665
1666	/**
1667	* Programmable Interrupt Controller registration structure (all contexts).
1668	*/
1669	typedef struct PDMPICREG
1670	{
1671	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1672	uint32_t u32Version;
1673
1674	/**
1675	* Set the an IRQ.
1676	*
1677	* @param pDevIns Device instance of the PIC.
1678	* @param iIrq IRQ number to set.
1679	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1680	* @param uTagSrc The IRQ tag and source (for tracing).
1681	* @remarks Caller enters the PDM critical section.
1682	*/
1683	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1684
1685	/**
1686	* Get a pending interrupt.
1687	*
1688	* @returns Pending interrupt number.
1689	* @param pDevIns Device instance of the PIC.
1690	* @param puTagSrc Where to return the IRQ tag and source.
1691	* @remarks Caller enters the PDM critical section.
1692	*/
1693	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1694
1695	/** Just a safety precaution. */
1696	uint32_t u32TheEnd;
1697	} PDMPICREG;
1698	/** Pointer to a PIC registration structure. */
1699	typedef PDMPICREG *PPDMPICREG;
1700
1701	/** Current PDMPICREG version number. */
1702	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1703
1704	/**
1705	* PIC helpers, same in all contexts.
1706	*/
1707	typedef struct PDMPICHLP
1708	{
1709	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1710	uint32_t u32Version;
1711
1712	/**
1713	* Set the interrupt force action flag.
1714	*
1715	* @param pDevIns Device instance of the PIC.
1716	*/
1717	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1718
1719	/**
1720	* Clear the interrupt force action flag.
1721	*
1722	* @param pDevIns Device instance of the PIC.
1723	*/
1724	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1725
1726	/**
1727	* Acquires the PDM lock.
1728	*
1729	* @returns VINF_SUCCESS on success.
1730	* @returns rc if we failed to acquire the lock.
1731	* @param pDevIns The PIC device instance.
1732	* @param rc What to return if we fail to acquire the lock.
1733	*
1734	* @sa PDMCritSectEnter
1735	*/
1736	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1737
1738	/**
1739	* Releases the PDM lock.
1740	*
1741	* @param pDevIns The PIC device instance.
1742	*/
1743	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1744
1745	/** Just a safety precaution. */
1746	uint32_t u32TheEnd;
1747	} PDMPICHLP;
1748	/** Pointer to PIC helpers. */
1749	typedef PDMPICHLP *PPDMPICHLP;
1750	/** Pointer to const PIC helpers. */
1751	typedef const PDMPICHLP *PCPDMPICHLP;
1752
1753	/** Current PDMPICHLP version number. */
1754	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1755
1756
1757	/**
1758	* Firmware registration structure.
1759	*/
1760	typedef struct PDMFWREG
1761	{
1762	/** Struct version+magic number (PDM_FWREG_VERSION). */
1763	uint32_t u32Version;
1764
1765	/**
1766	* Checks whether this is a hard or soft reset.
1767	*
1768	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1769	* is 5, 9 or 0xA.
1770	*
1771	* @returns true if hard reset, false if soft.
1772	* @param pDevIns Device instance of the firmware.
1773	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1774	*/
1775	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1776
1777	/** Just a safety precaution. */
1778	uint32_t u32TheEnd;
1779	} PDMFWREG;
1780	/** Pointer to a FW registration structure. */
1781	typedef PDMFWREG *PPDMFWREG;
1782	/** Pointer to a const FW registration structure. */
1783	typedef PDMFWREG const *PCPDMFWREG;
1784
1785	/** Current PDMFWREG version number. */
1786	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1787
1788	/**
1789	* Firmware R3 helpers.
1790	*/
1791	typedef struct PDMFWHLPR3
1792	{
1793	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1794	uint32_t u32Version;
1795
1796	/** Just a safety precaution. */
1797	uint32_t u32TheEnd;
1798	} PDMFWHLPR3;
1799
1800	/** Pointer to FW R3 helpers. */
1801	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1802	/** Pointer to const FW R3 helpers. */
1803	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1804
1805	/** Current PDMFWHLPR3 version number. */
1806	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1807
1808
1809	/**
1810	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1811	*
1812	* Also used in saved-states, CFGM don't change existing values.
1813	*/
1814	typedef enum PDMAPICMODE
1815	{
1816	/** Invalid 0 entry. */
1817	PDMAPICMODE_INVALID = 0,
1818	/** No APIC. */
1819	PDMAPICMODE_NONE,
1820	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1821	PDMAPICMODE_APIC,
1822	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1823	PDMAPICMODE_X2APIC,
1824	/** The usual 32-bit paranoia. */
1825	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1826	} PDMAPICMODE;
1827
1828	/**
1829	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1830	*/
1831	typedef enum PDMAPICIRQ
1832	{
1833	/** Invalid 0 entry. */
1834	PDMAPICIRQ_INVALID = 0,
1835	/** Normal hardware interrupt. */
1836	PDMAPICIRQ_HARDWARE,
1837	/** NMI. */
1838	PDMAPICIRQ_NMI,
1839	/** SMI. */
1840	PDMAPICIRQ_SMI,
1841	/** ExtINT (HW interrupt via PIC). */
1842	PDMAPICIRQ_EXTINT,
1843	/** Interrupt arrived, needs to be updated to the IRR. */
1844	PDMAPICIRQ_UPDATE_PENDING,
1845	/** The usual 32-bit paranoia. */
1846	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1847	} PDMAPICIRQ;
1848
1849
1850	/**
1851	* I/O APIC registration structure (all contexts).
1852	*/
1853	typedef struct PDMIOAPICREG
1854	{
1855	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1856	uint32_t u32Version;
1857
1858	/**
1859	* Set an IRQ.
1860	*
1861	* @param pDevIns Device instance of the I/O APIC.
1862	* @param uBusDevFn The bus:device:function of the device initiating the
1863	* IRQ. Can be NIL_PCIBDF.
1864	* @param iIrq IRQ number to set.
1865	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1866	* @param uTagSrc The IRQ tag and source (for tracing).
1867	*
1868	* @remarks Caller enters the PDM critical section
1869	* Actually, as per 2018-07-21 this isn't true (bird).
1870	*/
1871	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1872
1873	/**
1874	* Send a MSI.
1875	*
1876	* @param pDevIns Device instance of the I/O APIC.
1877	* @param uBusDevFn The bus:device:function of the device initiating the
1878	* MSI. Cannot be NIL_PCIBDF.
1879	* @param pMsi The MSI to send.
1880	* @param uTagSrc The IRQ tag and source (for tracing).
1881	*
1882	* @remarks Caller enters the PDM critical section
1883	* Actually, as per 2018-07-21 this isn't true (bird).
1884	*/
1885	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1886
1887	/**
1888	* Set the EOI for an interrupt vector.
1889	*
1890	* @param pDevIns Device instance of the I/O APIC.
1891	* @param u8Vector The vector.
1892	*
1893	* @remarks Caller enters the PDM critical section
1894	* Actually, as per 2018-07-21 this isn't true (bird).
1895	*/
1896	DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1897
1898	/** Just a safety precaution. */
1899	uint32_t u32TheEnd;
1900	} PDMIOAPICREG;
1901	/** Pointer to an APIC registration structure. */
1902	typedef PDMIOAPICREG *PPDMIOAPICREG;
1903
1904	/** Current PDMAPICREG version number. */
1905	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1906
1907
1908	/**
1909	* IOAPIC helpers, same in all contexts.
1910	*/
1911	typedef struct PDMIOAPICHLP
1912	{
1913	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1914	uint32_t u32Version;
1915
1916	/**
1917	* Private interface between the IOAPIC and APIC.
1918	*
1919	* @returns status code.
1920	* @param pDevIns Device instance of the IOAPIC.
1921	* @param u8Dest See APIC implementation.
1922	* @param u8DestMode See APIC implementation.
1923	* @param u8DeliveryMode See APIC implementation.
1924	* @param uVector See APIC implementation.
1925	* @param u8Polarity See APIC implementation.
1926	* @param u8TriggerMode See APIC implementation.
1927	* @param uTagSrc The IRQ tag and source (for tracing).
1928	*
1929	* @sa APICBusDeliver()
1930	*/
1931	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1932	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1933
1934	/**
1935	* Acquires the PDM lock.
1936	*
1937	* @returns VINF_SUCCESS on success.
1938	* @returns rc if we failed to acquire the lock.
1939	* @param pDevIns The IOAPIC device instance.
1940	* @param rc What to return if we fail to acquire the lock.
1941	*
1942	* @sa PDMCritSectEnter
1943	*/
1944	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1945
1946	/**
1947	* Releases the PDM lock.
1948	*
1949	* @param pDevIns The IOAPIC device instance.
1950	*/
1951	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1952
1953	/**
1954	* Checks if the calling thread owns the PDM lock.
1955	*
1956	* @param pDevIns The IOAPIC device instance.
1957	*/
1958	DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1959
1960	/**
1961	* Private interface between the IOAPIC and IOMMU.
1962	*
1963	* @returns status code.
1964	* @param pDevIns Device instance of the IOAPIC.
1965	* @param idDevice The device identifier (bus, device, function).
1966	* @param pMsiIn The source MSI.
1967	* @param pMsiOut Where to store the remapped MSI (only updated when
1968	* VINF_SUCCESS is returned).
1969	*/
1970	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1971
1972	/** Just a safety precaution. */
1973	uint32_t u32TheEnd;
1974	} PDMIOAPICHLP;
1975	/** Pointer to IOAPIC helpers. */
1976	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1977	/** Pointer to const IOAPIC helpers. */
1978	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1979
1980	/** Current PDMIOAPICHLP version number. */
1981	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1982
1983
1984	/**
1985	* HPET registration structure.
1986	*/
1987	typedef struct PDMHPETREG
1988	{
1989	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1990	uint32_t u32Version;
1991	} PDMHPETREG;
1992	/** Pointer to an HPET registration structure. */
1993	typedef PDMHPETREG *PPDMHPETREG;
1994
1995	/** Current PDMHPETREG version number. */
1996	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1997
1998	/**
1999	* HPET RC helpers.
2000	*
2001	* @remarks Keep this around in case HPET will need PDM interaction in again RC
2002	* at some later point.
2003	*/
2004	typedef struct PDMHPETHLPRC
2005	{
2006	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
2007	uint32_t u32Version;
2008
2009	/** Just a safety precaution. */
2010	uint32_t u32TheEnd;
2011	} PDMHPETHLPRC;
2012
2013	/** Pointer to HPET RC helpers. */
2014	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
2015	/** Pointer to const HPET RC helpers. */
2016	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
2017
2018	/** Current PDMHPETHLPRC version number. */
2019	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
2020
2021
2022	/**
2023	* HPET R0 helpers.
2024	*
2025	* @remarks Keep this around in case HPET will need PDM interaction in again R0
2026	* at some later point.
2027	*/
2028	typedef struct PDMHPETHLPR0
2029	{
2030	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2031	uint32_t u32Version;
2032
2033	/** Just a safety precaution. */
2034	uint32_t u32TheEnd;
2035	} PDMHPETHLPR0;
2036
2037	/** Pointer to HPET R0 helpers. */
2038	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2039	/** Pointer to const HPET R0 helpers. */
2040	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2041
2042	/** Current PDMHPETHLPR0 version number. */
2043	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2044
2045	/**
2046	* HPET R3 helpers.
2047	*/
2048	typedef struct PDMHPETHLPR3
2049	{
2050	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2051	uint32_t u32Version;
2052
2053	/**
2054	* Set legacy mode on PIT and RTC.
2055	*
2056	* @returns VINF_SUCCESS on success.
2057	* @returns rc if we failed to set legacy mode.
2058	* @param pDevIns Device instance of the HPET.
2059	* @param fActivated Whether legacy mode is activated or deactivated.
2060	*/
2061	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2062
2063
2064	/**
2065	* Set IRQ, bypassing ISA bus override rules.
2066	*
2067	* @returns VINF_SUCCESS on success.
2068	* @returns rc if we failed to set legacy mode.
2069	* @param pDevIns Device instance of the HPET.
2070	* @param iIrq IRQ number to set.
2071	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2072	*/
2073	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2074
2075	/** Just a safety precaution. */
2076	uint32_t u32TheEnd;
2077	} PDMHPETHLPR3;
2078
2079	/** Pointer to HPET R3 helpers. */
2080	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2081	/** Pointer to const HPET R3 helpers. */
2082	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2083
2084	/** Current PDMHPETHLPR3 version number. */
2085	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2086
2087
2088	/**
2089	* Raw PCI device registration structure.
2090	*/
2091	typedef struct PDMPCIRAWREG
2092	{
2093	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2094	uint32_t u32Version;
2095	/** Just a safety precaution. */
2096	uint32_t u32TheEnd;
2097	} PDMPCIRAWREG;
2098	/** Pointer to a raw PCI registration structure. */
2099	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2100
2101	/** Current PDMPCIRAWREG version number. */
2102	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2103
2104	/**
2105	* Raw PCI device raw-mode context helpers.
2106	*/
2107	typedef struct PDMPCIRAWHLPRC
2108	{
2109	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2110	uint32_t u32Version;
2111	/** Just a safety precaution. */
2112	uint32_t u32TheEnd;
2113	} PDMPCIRAWHLPRC;
2114	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2115	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2116	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2117	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2118
2119	/** Current PDMPCIRAWHLPRC version number. */
2120	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2121
2122	/**
2123	* Raw PCI device ring-0 context helpers.
2124	*/
2125	typedef struct PDMPCIRAWHLPR0
2126	{
2127	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2128	uint32_t u32Version;
2129	/** Just a safety precaution. */
2130	uint32_t u32TheEnd;
2131	} PDMPCIRAWHLPR0;
2132	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2133	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2134	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2135	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2136
2137	/** Current PDMPCIRAWHLPR0 version number. */
2138	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2139
2140
2141	/**
2142	* Raw PCI device ring-3 context helpers.
2143	*/
2144	typedef struct PDMPCIRAWHLPR3
2145	{
2146	/** Undefined structure version and magic number. */
2147	uint32_t u32Version;
2148
2149	/**
2150	* Gets the address of the RC raw PCI device helpers.
2151	*
2152	* This should be called at both construction and relocation time to obtain
2153	* the correct address of the RC helpers.
2154	*
2155	* @returns RC pointer to the raw PCI device helpers.
2156	* @param pDevIns Device instance of the raw PCI device.
2157	*/
2158	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2159
2160	/**
2161	* Gets the address of the R0 raw PCI device helpers.
2162	*
2163	* This should be called at both construction and relocation time to obtain
2164	* the correct address of the R0 helpers.
2165	*
2166	* @returns R0 pointer to the raw PCI device helpers.
2167	* @param pDevIns Device instance of the raw PCI device.
2168	*/
2169	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2170
2171	/** Just a safety precaution. */
2172	uint32_t u32TheEnd;
2173	} PDMPCIRAWHLPR3;
2174	/** Pointer to raw PCI R3 helpers. */
2175	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2176	/** Pointer to const raw PCI R3 helpers. */
2177	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2178
2179	/** Current PDMPCIRAWHLPR3 version number. */
2180	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2181
2182
2183	#ifdef IN_RING3
2184
2185	/**
2186	* DMA Transfer Handler.
2187	*
2188	* @returns Number of bytes transferred.
2189	* @param pDevIns The device instance that registered the handler.
2190	* @param pvUser User pointer.
2191	* @param uChannel Channel number.
2192	* @param off DMA position.
2193	* @param cb Block size.
2194	* @remarks The device lock is take before the callback (in fact, the locks of
2195	* DMA devices and the DMA controller itself are taken).
2196	*/
2197	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2198	uint32_t off, uint32_t cb));
2199	/** Pointer to a FNDMATRANSFERHANDLER(). */
2200	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2201
2202	/**
2203	* DMA Controller registration structure.
2204	*/
2205	typedef struct PDMDMAREG
2206	{
2207	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2208	uint32_t u32Version;
2209
2210	/**
2211	* Execute pending transfers.
2212	*
2213	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2214	* @param pDevIns Device instance of the DMAC.
2215	* @remarks No locks held, called on EMT(0) as a form of serialization.
2216	*/
2217	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2218
2219	/**
2220	* Register transfer function for DMA channel.
2221	*
2222	* @param pDevIns Device instance of the DMAC.
2223	* @param uChannel Channel number.
2224	* @param pDevInsHandler The device instance of the device making the
2225	* regstration (will be passed to the callback).
2226	* @param pfnTransferHandler Device specific transfer function.
2227	* @param pvUser User pointer to be passed to the callback.
2228	* @remarks No locks held, called on an EMT.
2229	*/
2230	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2231	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2232
2233	/**
2234	* Read memory
2235	*
2236	* @returns Number of bytes read.
2237	* @param pDevIns Device instance of the DMAC.
2238	* @param uChannel Channel number.
2239	* @param pvBuffer Pointer to target buffer.
2240	* @param off DMA position.
2241	* @param cbBlock Block size.
2242	* @remarks No locks held, called on an EMT.
2243	*/
2244	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2245
2246	/**
2247	* Write memory
2248	*
2249	* @returns Number of bytes written.
2250	* @param pDevIns Device instance of the DMAC.
2251	* @param uChannel Channel number.
2252	* @param pvBuffer Memory to write.
2253	* @param off DMA position.
2254	* @param cbBlock Block size.
2255	* @remarks No locks held, called on an EMT.
2256	*/
2257	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2258
2259	/**
2260	* Set the DREQ line.
2261	*
2262	* @param pDevIns Device instance of the DMAC.
2263	* @param uChannel Channel number.
2264	* @param uLevel Level of the line.
2265	* @remarks No locks held, called on an EMT.
2266	*/
2267	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2268
2269	/**
2270	* Get channel mode
2271	*
2272	* @returns Channel mode.
2273	* @param pDevIns Device instance of the DMAC.
2274	* @param uChannel Channel number.
2275	* @remarks No locks held, called on an EMT.
2276	*/
2277	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2278
2279	} PDMDMACREG;
2280	/** Pointer to a DMAC registration structure. */
2281	typedef PDMDMACREG *PPDMDMACREG;
2282
2283	/** Current PDMDMACREG version number. */
2284	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2285
2286
2287	/**
2288	* DMA Controller device helpers.
2289	*/
2290	typedef struct PDMDMACHLP
2291	{
2292	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2293	uint32_t u32Version;
2294
2295	/* to-be-defined */
2296
2297	} PDMDMACHLP;
2298	/** Pointer to DMAC helpers. */
2299	typedef PDMDMACHLP *PPDMDMACHLP;
2300	/** Pointer to const DMAC helpers. */
2301	typedef const PDMDMACHLP *PCPDMDMACHLP;
2302
2303	/** Current PDMDMACHLP version number. */
2304	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2305
2306	#endif /* IN_RING3 */
2307
2308
2309
2310	/**
2311	* RTC registration structure.
2312	*/
2313	typedef struct PDMRTCREG
2314	{
2315	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2316	uint32_t u32Version;
2317	uint32_t u32Alignment; /*< structure size alignment. /
2318
2319	/**
2320	* Write to a CMOS register and update the checksum if necessary.
2321	*
2322	* @returns VBox status code.
2323	* @param pDevIns Device instance of the RTC.
2324	* @param iReg The CMOS register index.
2325	* @param u8Value The CMOS register value.
2326	* @remarks Caller enters the device critical section.
2327	*/
2328	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2329
2330	/**
2331	* Read a CMOS register.
2332	*
2333	* @returns VBox status code.
2334	* @param pDevIns Device instance of the RTC.
2335	* @param iReg The CMOS register index.
2336	* @param pu8Value Where to store the CMOS register value.
2337	* @remarks Caller enters the device critical section.
2338	*/
2339	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2340
2341	} PDMRTCREG;
2342	/** Pointer to a RTC registration structure. */
2343	typedef PDMRTCREG *PPDMRTCREG;
2344	/** Pointer to a const RTC registration structure. */
2345	typedef const PDMRTCREG *PCPDMRTCREG;
2346
2347	/** Current PDMRTCREG version number. */
2348	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2349
2350
2351	/**
2352	* RTC device helpers.
2353	*/
2354	typedef struct PDMRTCHLP
2355	{
2356	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2357	uint32_t u32Version;
2358
2359	/* to-be-defined */
2360
2361	} PDMRTCHLP;
2362	/** Pointer to RTC helpers. */
2363	typedef PDMRTCHLP *PPDMRTCHLP;
2364	/** Pointer to const RTC helpers. */
2365	typedef const PDMRTCHLP *PCPDMRTCHLP;
2366
2367	/** Current PDMRTCHLP version number. */
2368	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2369
2370
2371
2372	/** @name Flags for PCI I/O region registration
2373	* @{ */
2374	/** No handle is passed. */
2375	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2376	/** An I/O port handle is passed. */
2377	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2378	/** An MMIO range handle is passed. */
2379	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2380	/** An MMIO2 handle is passed. */
2381	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2382	/** Handle type mask. */
2383	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2384	/** New-style (mostly wrt callbacks). */
2385	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2386	/** Mask of valid flags. */
2387	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2388	/** @} */
2389
2390
2391	/** @name Flags for the guest physical read/write helpers
2392	* @{ */
2393	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2394	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2395	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2396	* by the device in any way. */
2397	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2398	/** The data is metadata and being processed by the device in some way. */
2399	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2400	/** @} */
2401
2402
2403	#ifdef IN_RING3
2404
2405	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2406	* @{ */
2407	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2408	* This is handy when registering multiple PCI device functions and the device
2409	* number is left up to the PCI bus. In order to facilitate one PDM device
2410	* instance for each PCI function, this searches earlier PDM device
2411	* instances as well. */
2412	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2413	/** Use the first unused device number (all functions must be unused). */
2414	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2415	/** Use the first unused device function. */
2416	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2417
2418	/** The device and function numbers are not mandatory, just suggestions. */
2419	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2420	/** Registering a PCI bridge device. */
2421	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2422	/** Valid flag mask. */
2423	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2424	/** @} */
2425
2426	/** Current PDMDEVHLPR3 version number. */
2427	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 63, 0)
2428
2429	/**
2430	* PDM Device API.
2431	*/
2432	typedef struct PDMDEVHLPR3
2433	{
2434	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2435	uint32_t u32Version;
2436
2437	/** @name I/O ports
2438	* @{ */
2439	/**
2440	* Creates a range of I/O ports for a device.
2441	*
2442	* The I/O port range must be mapped in a separately call. Any ring-0 and
2443	* raw-mode context callback handlers needs to be set up in the respective
2444	* contexts.
2445	*
2446	* @returns VBox status.
2447	* @param pDevIns The device instance to register the ports with.
2448	* @param cPorts Number of ports to register.
2449	* @param fFlags IOM_IOPORT_F_XXX.
2450	* @param pPciDev The PCI device the range is associated with, if
2451	* applicable.
2452	* @param iPciRegion The PCI device region in the high 16-bit word and
2453	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2454	* @param pfnOut Pointer to function which is gonna handle OUT
2455	* operations. Optional.
2456	* @param pfnIn Pointer to function which is gonna handle IN operations.
2457	* Optional.
2458	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2459	* operations. Optional.
2460	* @param pfnInStr Pointer to function which is gonna handle string IN
2461	* operations. Optional.
2462	* @param pvUser User argument to pass to the callbacks.
2463	* @param pszDesc Pointer to description string. This must not be freed.
2464	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2465	* coverage is allowed. This must not be freed.
2466	* @param phIoPorts Where to return the I/O port range handle.
2467	*
2468	* @remarks Caller enters the device critical section prior to invoking the
2469	* registered callback methods.
2470	*
2471	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2472	* PDMDevHlpIoPortUnmap.
2473	*/
2474	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2475	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2476	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2477	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2478
2479	/**
2480	* Maps an I/O port range.
2481	*
2482	* @returns VBox status.
2483	* @param pDevIns The device instance to register the ports with.
2484	* @param hIoPorts The I/O port range handle.
2485	* @param Port Where to map the range.
2486	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2487	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2488	*/
2489	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2490
2491	/**
2492	* Unmaps an I/O port range.
2493	*
2494	* @returns VBox status.
2495	* @param pDevIns The device instance to register the ports with.
2496	* @param hIoPorts The I/O port range handle.
2497	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2498	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2499	*/
2500	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2501
2502	/**
2503	* Gets the mapping address of the I/O port range @a hIoPorts.
2504	*
2505	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2506	* parameters).
2507	* @param pDevIns The device instance to register the ports with.
2508	* @param hIoPorts The I/O port range handle.
2509	*/
2510	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2511
2512	/**
2513	* Writes to an I/O port register.
2514	*
2515	* @returns Strict VBox status code. Informational status codes other than the one documented
2516	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2517	* @retval VINF_SUCCESS Success.
2518	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2519	* status code must be passed on to EM.
2520	*
2521	* @param pDevIns The device instance to register the ports with.
2522	* @param Port The port to write to.
2523	* @param u32Value The value to write.
2524	* @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
2525	*
2526	* @thread EMT
2527	* @todo r=aeichner This is only used by DevPCI.cpp to write the ELCR of the PIC. This shouldn't be done that way
2528	* and removed again as soon as possible (no time right now)...
2529	*/
2530	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnIoPortWrite,(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t u32Value, size_t cbValue));
2531	/** @} */
2532
2533	/** @name MMIO
2534	* @{ */
2535	/**
2536	* Creates a memory mapped I/O (MMIO) region for a device.
2537	*
2538	* The MMIO region must be mapped in a separately call. Any ring-0 and
2539	* raw-mode context callback handlers needs to be set up in the respective
2540	* contexts.
2541	*
2542	* @returns VBox status.
2543	* @param pDevIns The device instance to register the ports with.
2544	* @param cbRegion The size of the region in bytes.
2545	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2546	* @param pPciDev The PCI device the range is associated with, if
2547	* applicable.
2548	* @param iPciRegion The PCI device region in the high 16-bit word and
2549	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2550	* @param pfnWrite Pointer to function which is gonna handle Write
2551	* operations.
2552	* @param pfnRead Pointer to function which is gonna handle Read
2553	* operations.
2554	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2555	* operations. (optional)
2556	* @param pvUser User argument to pass to the callbacks.
2557	* @param pszDesc Pointer to description string. This must not be freed.
2558	* @param phRegion Where to return the MMIO region handle.
2559	*
2560	* @remarks Caller enters the device critical section prior to invoking the
2561	* registered callback methods.
2562	*
2563	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2564	*/
2565	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2566	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2567	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2568	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2569
2570	/**
2571	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2572	*
2573	* @returns VBox status.
2574	* @param pDevIns The device instance the region is associated with.
2575	* @param hRegion The MMIO region handle.
2576	* @param GCPhys Where to map the region.
2577	* @note An MMIO range may overlap with base memory if a lot of RAM is
2578	* configured for the VM, in which case we'll drop the base memory
2579	* pages. Presently we will make no attempt to preserve anything that
2580	* happens to be present in the base memory that is replaced, this is
2581	* technically incorrect but it's just not worth the effort to do
2582	* right, at least not at this point.
2583	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2584	* PDMDevHlpMmioSetUpContext
2585	*/
2586	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2587
2588	/**
2589	* Unmaps a memory mapped I/O (MMIO) region.
2590	*
2591	* @returns VBox status.
2592	* @param pDevIns The device instance the region is associated with.
2593	* @param hRegion The MMIO region handle.
2594	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2595	* PDMDevHlpMmioSetUpContext
2596	*/
2597	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2598
2599	/**
2600	* Reduces the length of a MMIO range.
2601	*
2602	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2603	* only work during saved state restore. It will not call the PCI bus code, as
2604	* that is expected to restore the saved resource configuration.
2605	*
2606	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2607	* called it will only map @a cbRegion bytes and not the value set during
2608	* registration.
2609	*
2610	* @return VBox status code.
2611	* @param pDevIns The device owning the range.
2612	* @param hRegion The MMIO region handle.
2613	* @param cbRegion The new size, must be smaller.
2614	*/
2615	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2616
2617	/**
2618	* Gets the mapping address of the MMIO region @a hRegion.
2619	*
2620	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2621	* @param pDevIns The device instance to register the ports with.
2622	* @param hRegion The MMIO region handle.
2623	*/
2624	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2625	/** @} */
2626
2627	/** @name MMIO2
2628	* @{ */
2629	/**
2630	* Creates a MMIO2 region.
2631	*
2632	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2633	* associated with a device. It is also non-shared memory with a permanent
2634	* ring-3 mapping and page backing (presently).
2635	*
2636	* @returns VBox status.
2637	* @param pDevIns The device instance.
2638	* @param pPciDev The PCI device the region is associated with, or
2639	* NULL if no PCI device association.
2640	* @param iPciRegion The region number. Use the PCI region number as
2641	* this must be known to the PCI bus device too. If
2642	* it's not associated with the PCI device, then
2643	* any number up to UINT8_MAX is fine.
2644	* @param cbRegion The size (in bytes) of the region.
2645	* @param fFlags PGMPHYS_MMIO2_FLAGS_XXX (see pgm.h).
2646	* @param pszDesc Pointer to description string. This must not be
2647	* freed.
2648	* @param ppvMapping Where to store the address of the ring-3 mapping
2649	* of the memory.
2650	* @param phRegion Where to return the MMIO2 region handle.
2651	*
2652	* @thread EMT(0)
2653	*/
2654	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2655	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2656
2657	/**
2658	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2659	*
2660	* Any physical access handlers registered for the region must be deregistered
2661	* before calling this function.
2662	*
2663	* @returns VBox status code.
2664	* @param pDevIns The device instance.
2665	* @param hRegion The MMIO2 region handle.
2666	* @thread EMT.
2667	*/
2668	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2669
2670	/**
2671	* Maps a MMIO2 region (into the guest physical address space).
2672	*
2673	* @returns VBox status.
2674	* @param pDevIns The device instance the region is associated with.
2675	* @param hRegion The MMIO2 region handle.
2676	* @param GCPhys Where to map the region.
2677	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2678	* configured for the VM, in which case we'll drop the base memory
2679	* pages. Presently we will make no attempt to preserve anything that
2680	* happens to be present in the base memory that is replaced, this is
2681	* technically incorrect but it's just not worth the effort to do
2682	* right, at least not at this point.
2683	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2684	*/
2685	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2686
2687	/**
2688	* Unmaps a MMIO2 region.
2689	*
2690	* @returns VBox status.
2691	* @param pDevIns The device instance the region is associated with.
2692	* @param hRegion The MMIO2 region handle.
2693	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2694	*/
2695	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2696
2697	/**
2698	* Reduces the length of a MMIO range.
2699	*
2700	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2701	* only work during saved state restore. It will not call the PCI bus code, as
2702	* that is expected to restore the saved resource configuration.
2703	*
2704	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2705	* called it will only map @a cbRegion bytes and not the value set during
2706	* registration.
2707	*
2708	* @return VBox status code.
2709	* @param pDevIns The device owning the range.
2710	* @param hRegion The MMIO2 region handle.
2711	* @param cbRegion The new size, must be smaller.
2712	*/
2713	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2714
2715	/**
2716	* Gets the mapping address of the MMIO region @a hRegion.
2717	*
2718	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2719	* @param pDevIns The device instance to register the ports with.
2720	* @param hRegion The MMIO2 region handle.
2721	*/
2722	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2723
2724	/**
2725	* Queries and resets the dirty bitmap for an MMIO2 region.
2726	*
2727	* The MMIO2 region must have been created with the
2728	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
2729	*
2730	* @returns VBox status code.
2731	* @param pDevIns The device instance.
2732	* @param hRegion The MMIO2 region handle.
2733	* @param pvBitmap Where to return the bitmap. Must be 8-byte aligned.
2734	* Can be NULL if only resetting the tracking is desired.
2735	* @param cbBitmap The bitmap size. One bit per page in the region,
2736	* rounded up to 8-bytes. If pvBitmap is NULL this must
2737	* also be zero.
2738	*/
2739	DECLR3CALLBACKMEMBER(int, pfnMmio2QueryAndResetDirtyBitmap, (PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
2740	void *pvBitmap, size_t cbBitmap));
2741
2742	/**
2743	* Controls the dirty page tracking for an MMIO2 region.
2744	*
2745	* The MMIO2 region must have been created with the
2746	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
2747	*
2748	* @returns VBox status code.
2749	* @param pDevIns The device instance.
2750	* @param hRegion The MMIO2 region handle.
2751	* @param fEnabled When set to @c true the dirty page tracking will be
2752	* enabled if currently disabled (bitmap is reset). When
2753	* set to @c false the dirty page tracking will be
2754	* disabled.
2755	*/
2756	DECLR3CALLBACKMEMBER(int, pfnMmio2ControlDirtyPageTracking, (PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, bool fEnabled));
2757
2758	/**
2759	* Changes the number of an MMIO2 or pre-registered MMIO region.
2760	*
2761	* This should only be used to deal with saved state problems, so there is no
2762	* convenience inline wrapper for this method.
2763	*
2764	* @returns VBox status code.
2765	* @param pDevIns The device instance.
2766	* @param hRegion The MMIO2 region handle.
2767	* @param iNewRegion The new region index.
2768	*
2769	* @sa @bugref{9359}
2770	*/
2771	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2772
2773	/**
2774	* Mapping an MMIO2 page in place of an MMIO page for direct access.
2775	*
2776	* This is a special optimization used by the VGA device. Call
2777	* PDMDevHlpMmioResetRegion() to undo the mapping.
2778	*
2779	* @returns VBox status code. This API may return VINF_SUCCESS even if no
2780	* remapping is made.
2781	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
2782	*
2783	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
2784	* associated with.
2785	* @param hRegion The handle to the MMIO region.
2786	* @param offRegion The offset into @a hRegion of the page to be
2787	* remapped.
2788	* @param hMmio2 The MMIO2 handle.
2789	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
2790	* mapping.
2791	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
2792	* for the time being.
2793	*/
2794	DECLR3CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
2795	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
2796
2797	/**
2798	* Reset a previously modified MMIO region; restore the access flags.
2799	*
2800	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
2801	* intended for some ancient VGA hack. However, it would be great to extend it
2802	* beyond VT-x and/or nested-paging.
2803	*
2804	* @returns VBox status code.
2805	*
2806	* @param pDevIns The device instance @a hRegion is associated with.
2807	* @param hRegion The handle to the MMIO region.
2808	*/
2809	DECLR3CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2810	/** @} */
2811
2812	/**
2813	* Register a ROM (BIOS) region.
2814	*
2815	* It goes without saying that this is read-only memory. The memory region must be
2816	* in unassigned memory. I.e. from the top of the address space or on the PC in
2817	* the 0xa0000-0xfffff range.
2818	*
2819	* @returns VBox status.
2820	* @param pDevIns The device instance owning the ROM region.
2821	* @param GCPhysStart First physical address in the range.
2822	* Must be page aligned!
2823	* @param cbRange The size of the range (in bytes).
2824	* Must be page aligned!
2825	* @param pvBinary Pointer to the binary data backing the ROM image.
2826	* @param cbBinary The size of the binary pointer. This must
2827	* be equal or smaller than @a cbRange.
2828	* @param fFlags PGMPHYS_ROM_FLAGS_XXX (see pgm.h).
2829	* @param pszDesc Pointer to description string. This must not be freed.
2830	*
2831	* @remark There is no way to remove the rom, automatically on device cleanup or
2832	* manually from the device yet. At present I doubt we need such features...
2833	*/
2834	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2835	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2836
2837	/**
2838	* Changes the protection of shadowed ROM mapping.
2839	*
2840	* This is intented for use by the system BIOS, chipset or device in question to
2841	* change the protection of shadowed ROM code after init and on reset.
2842	*
2843	* @param pDevIns The device instance.
2844	* @param GCPhysStart Where the mapping starts.
2845	* @param cbRange The size of the mapping.
2846	* @param enmProt The new protection type.
2847	*/
2848	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2849
2850	/**
2851	* Register a save state data unit.
2852	*
2853	* @returns VBox status.
2854	* @param pDevIns The device instance.
2855	* @param uVersion Data layout version number.
2856	* @param cbGuess The approximate amount of data in the unit.
2857	* Only for progress indicators.
2858	* @param pszBefore Name of data unit which we should be put in
2859	* front of. Optional (NULL).
2860	*
2861	* @param pfnLivePrep Prepare live save callback, optional.
2862	* @param pfnLiveExec Execute live save callback, optional.
2863	* @param pfnLiveVote Vote live save callback, optional.
2864	*
2865	* @param pfnSavePrep Prepare save callback, optional.
2866	* @param pfnSaveExec Execute save callback, optional.
2867	* @param pfnSaveDone Done save callback, optional.
2868	*
2869	* @param pfnLoadPrep Prepare load callback, optional.
2870	* @param pfnLoadExec Execute load callback, optional.
2871	* @param pfnLoadDone Done load callback, optional.
2872	* @remarks Caller enters the device critical section prior to invoking the
2873	* registered callback methods.
2874	*/
2875	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2876	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2877	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2878	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2879
2880	/**
2881	* Register a save state data unit for backward compatibility.
2882	*
2883	* This is for migrating from an old device name to a new one or for merging
2884	* devices. It will only help loading old saved states.
2885	*
2886	* @returns VBox status.
2887	* @param pDevIns The device instance.
2888	* @param pszOldName The old unit name.
2889	* @param pfnLoadPrep Prepare load callback, optional.
2890	* @param pfnLoadExec Execute load callback, optional.
2891	* @param pfnLoadDone Done load callback, optional.
2892	* @remarks Caller enters the device critical section prior to invoking the
2893	* registered callback methods.
2894	*/
2895	DECLR3CALLBACKMEMBER(int, pfnSSMRegisterLegacy,(PPDMDEVINS pDevIns, const char *pszOldName, PFNSSMDEVLOADPREP pfnLoadPrep,
2896	PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2897
2898	/** @name Exported SSM Functions
2899	* @{ */
2900	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2901	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2902	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2903	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2904	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2905	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2906	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2907	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2908	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2909	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2910	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2911	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2912	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2913	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2914	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2915	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2916	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2917	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2918	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2919	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2920	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2921	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2922	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2923	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2924	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2925	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2926	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2927	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2928	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2929	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2930	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2931	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2932	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2933	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2934	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2935	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2936	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2937	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2938	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2939	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2940	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2941	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2942	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2943	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2944	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2945	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2946	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2947	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2948	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2949	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2950	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2951	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2952	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2953	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2954	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2955	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2956	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2957	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2958	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2959	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2960	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2961	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2962	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2963	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2964	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2965	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2966	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2967	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2968	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2969	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2970	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2971	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2972	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2973	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2974	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2975	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2976	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2977	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2978	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2979	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2980	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2981	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2982	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2983	/** @} */
2984
2985	/**
2986	* Creates a timer w/ a cross context handle.
2987	*
2988	* @returns VBox status.
2989	* @param pDevIns The device instance.
2990	* @param enmClock The clock to use on this timer.
2991	* @param pfnCallback Callback function.
2992	* @param pvUser User argument for the callback.
2993	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2994	* @param pszDesc Pointer to description string which must stay around
2995	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2996	* @param phTimer Where to store the timer handle on success.
2997	* @remarks Caller enters the device critical section prior to invoking the
2998	* callback.
2999	*/
3000	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
3001	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
3002
3003	/** @name Timer handle method wrappers
3004	* @{ */
3005	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
3006	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
3007	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
3008	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3009	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3010	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3011	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3012	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3013	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
3014	/** Takes the clock lock then enters the specified critical section. */
3015	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
3016	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
3017	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
3018	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
3019	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
3020	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
3021	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
3022	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3023	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3024	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
3025	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
3026	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3027	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3028	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3029	/** @sa TMR3TimerSkip */
3030	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
3031	/** @} */
3032
3033	/**
3034	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
3035	*
3036	* @returns pTime.
3037	* @param pDevIns The device instance.
3038	* @param pTime Where to store the time.
3039	*/
3040	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
3041
3042	/** @name Exported CFGM Functions.
3043	* @{ */
3044	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
3045	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
3046	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
3047	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3048	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3049	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
3050	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
3051	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
3052	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3053	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3054	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
3055	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
3056	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
3057	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
3058	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
3059	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
3060	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
3061	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
3062	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
3063	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
3064	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
3065	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
3066	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
3067	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
3068	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
3069	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
3070	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
3071	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
3072	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
3073	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
3074	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
3075	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
3076	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
3077	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
3078	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
3079	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
3080	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
3081	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
3082	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
3083	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
3084	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
3085	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
3086	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
3087	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
3088	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
3089	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
3090	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
3091	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
3092	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
3093	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
3094	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
3095	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
3096	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
3097	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
3098	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
3099	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
3100	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
3101	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
3102	const char pszValidValues, const char pszValidNodes,
3103	const char *pszWho, uint32_t uInstance));
3104	/** @} */
3105
3106	/**
3107	* Read physical memory.
3108	*
3109	* @returns VINF_SUCCESS (for now).
3110	* @param pDevIns The device instance.
3111	* @param GCPhys Physical address start reading from.
3112	* @param pvBuf Where to put the read bits.
3113	* @param cbRead How many bytes to read.
3114	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3115	* @thread Any thread, but the call may involve the emulation thread.
3116	*/
3117	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3118
3119	/**
3120	* Write to physical memory.
3121	*
3122	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3123	* @param pDevIns The device instance.
3124	* @param GCPhys Physical address to write to.
3125	* @param pvBuf What to write.
3126	* @param cbWrite How many bytes to write.
3127	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3128	* @thread Any thread, but the call may involve the emulation thread.
3129	*/
3130	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3131
3132	/**
3133	* Requests the mapping of a guest page into ring-3.
3134	*
3135	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3136	* release it.
3137	*
3138	* This API will assume your intention is to write to the page, and will
3139	* therefore replace shared and zero pages. If you do not intend to modify the
3140	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3141	*
3142	* @returns VBox status code.
3143	* @retval VINF_SUCCESS on success.
3144	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3145	* backing or if the page has any active access handlers. The caller
3146	* must fall back on using PGMR3PhysWriteExternal.
3147	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3148	*
3149	* @param pDevIns The device instance.
3150	* @param GCPhys The guest physical address of the page that
3151	* should be mapped.
3152	* @param fFlags Flags reserved for future use, MBZ.
3153	* @param ppv Where to store the address corresponding to
3154	* GCPhys.
3155	* @param pLock Where to store the lock information that
3156	* pfnPhysReleasePageMappingLock needs.
3157	*
3158	* @remark Avoid calling this API from within critical sections (other than the
3159	* PGM one) because of the deadlock risk when we have to delegating the
3160	* task to an EMT.
3161	* @thread Any.
3162	*/
3163	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3164	PPGMPAGEMAPLOCK pLock));
3165
3166	/**
3167	* Requests the mapping of a guest page into ring-3, external threads.
3168	*
3169	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3170	* release it.
3171	*
3172	* @returns VBox status code.
3173	* @retval VINF_SUCCESS on success.
3174	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3175	* backing or if the page as an active ALL access handler. The caller
3176	* must fall back on using PGMPhysRead.
3177	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3178	*
3179	* @param pDevIns The device instance.
3180	* @param GCPhys The guest physical address of the page that
3181	* should be mapped.
3182	* @param fFlags Flags reserved for future use, MBZ.
3183	* @param ppv Where to store the address corresponding to
3184	* GCPhys.
3185	* @param pLock Where to store the lock information that
3186	* pfnPhysReleasePageMappingLock needs.
3187	*
3188	* @remark Avoid calling this API from within critical sections.
3189	* @thread Any.
3190	*/
3191	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3192	void const **ppv, PPGMPAGEMAPLOCK pLock));
3193
3194	/**
3195	* Release the mapping of a guest page.
3196	*
3197	* This is the counter part of pfnPhysGCPhys2CCPtr and
3198	* pfnPhysGCPhys2CCPtrReadOnly.
3199	*
3200	* @param pDevIns The device instance.
3201	* @param pLock The lock structure initialized by the mapping
3202	* function.
3203	*/
3204	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3205
3206	/**
3207	* Read guest physical memory by virtual address.
3208	*
3209	* @param pDevIns The device instance.
3210	* @param pvDst Where to put the read bits.
3211	* @param GCVirtSrc Guest virtual address to start reading from.
3212	* @param cb How many bytes to read.
3213	* @thread The emulation thread.
3214	*/
3215	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3216
3217	/**
3218	* Write to guest physical memory by virtual address.
3219	*
3220	* @param pDevIns The device instance.
3221	* @param GCVirtDst Guest virtual address to write to.
3222	* @param pvSrc What to write.
3223	* @param cb How many bytes to write.
3224	* @thread The emulation thread.
3225	*/
3226	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3227
3228	/**
3229	* Convert a guest virtual address to a guest physical address.
3230	*
3231	* @returns VBox status code.
3232	* @param pDevIns The device instance.
3233	* @param GCPtr Guest virtual address.
3234	* @param pGCPhys Where to store the GC physical address
3235	* corresponding to GCPtr.
3236	* @thread The emulation thread.
3237	* @remark Careful with page boundaries.
3238	*/
3239	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3240
3241	/**
3242	* Checks if a GC physical address is a normal page,
3243	* i.e. not ROM, MMIO or reserved.
3244	*
3245	* @returns true if normal.
3246	* @returns false if invalid, ROM, MMIO or reserved page.
3247	* @param pDevIns The device instance.
3248	* @param GCPhys The physical address to check.
3249	*/
3250	DECLR3CALLBACKMEMBER(bool, pfnPhysIsGCPhysNormal,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
3251
3252	/**
3253	* Inflate or deflate a memory balloon
3254	*
3255	* @returns VBox status code.
3256	* @param pDevIns The device instance.
3257	* @param fInflate Inflate or deflate memory balloon
3258	* @param cPages Number of pages to free
3259	* @param paPhysPage Array of guest physical addresses
3260	*/
3261	DECLR3CALLBACKMEMBER(int, pfnPhysChangeMemBalloon,(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage));
3262
3263	/**
3264	* Allocate memory which is associated with current VM instance
3265	* and automatically freed on it's destruction.
3266	*
3267	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3268	* @param pDevIns The device instance.
3269	* @param cb Number of bytes to allocate.
3270	*/
3271	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3272
3273	/**
3274	* Allocate memory which is associated with current VM instance
3275	* and automatically freed on it's destruction. The memory is ZEROed.
3276	*
3277	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3278	* @param pDevIns The device instance.
3279	* @param cb Number of bytes to allocate.
3280	*/
3281	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3282
3283	/**
3284	* Allocating string printf.
3285	*
3286	* @returns Pointer to the string.
3287	* @param pDevIns The device instance.
3288	* @param enmTag The statistics tag.
3289	* @param pszFormat The format string.
3290	* @param va Format arguments.
3291	*/
3292	DECLR3CALLBACKMEMBER(char , pfnMMHeapAPrintfV,(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, va_list va));
3293
3294	/**
3295	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3296	*
3297	* @param pDevIns The device instance.
3298	* @param pv Pointer to the memory to free.
3299	*/
3300	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3301
3302	/**
3303	* Returns the physical RAM size of the VM.
3304	*
3305	* @returns RAM size in bytes.
3306	* @param pDevIns The device instance.
3307	*/
3308	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSize,(PPDMDEVINS pDevIns));
3309
3310	/**
3311	* Returns the physical RAM size of the VM below the 4GB boundary.
3312	*
3313	* @returns RAM size in bytes.
3314	* @param pDevIns The device instance.
3315	*/
3316	DECLR3CALLBACKMEMBER(uint32_t, pfnMMPhysGetRamSizeBelow4GB,(PPDMDEVINS pDevIns));
3317
3318	/**
3319	* Returns the physical RAM size of the VM above the 4GB boundary.
3320	*
3321	* @returns RAM size in bytes.
3322	* @param pDevIns The device instance.
3323	*/
3324	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSizeAbove4GB,(PPDMDEVINS pDevIns));
3325
3326	/**
3327	* Gets the VM state.
3328	*
3329	* @returns VM state.
3330	* @param pDevIns The device instance.
3331	* @thread Any thread (just keep in mind that it's volatile info).
3332	*/
3333	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3334
3335	/**
3336	* Checks if the VM was teleported and hasn't been fully resumed yet.
3337	*
3338	* @returns true / false.
3339	* @param pDevIns The device instance.
3340	* @thread Any thread.
3341	*/
3342	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3343
3344	/**
3345	* Set the VM error message
3346	*
3347	* @returns rc.
3348	* @param pDevIns The device instance.
3349	* @param rc VBox status code.
3350	* @param SRC_POS Use RT_SRC_POS.
3351	* @param pszFormat Error message format string.
3352	* @param va Error message arguments.
3353	*/
3354	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3355	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3356
3357	/**
3358	* Set the VM runtime error message
3359	*
3360	* @returns VBox status code.
3361	* @param pDevIns The device instance.
3362	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3363	* @param pszErrorId Error ID string.
3364	* @param pszFormat Error message format string.
3365	* @param va Error message arguments.
3366	*/
3367	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3368	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3369
3370	/**
3371	* Special interface for implementing a HLT-like port on a device.
3372	*
3373	* This can be called directly from device code, provide the device is trusted
3374	* to access the VMM directly. Since we may not have an accurate register set
3375	* and the caller certainly shouldn't (device code does not access CPU
3376	* registers), this function will return when interrupts are pending regardless
3377	* of the actual EFLAGS.IF state.
3378	*
3379	* @returns VBox error status (never informational statuses).
3380	* @param pDevIns The device instance.
3381	* @param idCpu The id of the calling EMT.
3382	*/
3383	DECLR3CALLBACKMEMBER(int, pfnVMWaitForDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3384
3385	/**
3386	* Wakes up a CPU that has called PDMDEVHLPR3::pfnVMWaitForDeviceReady.
3387	*
3388	* @returns VBox error status (never informational statuses).
3389	* @param pDevIns The device instance.
3390	* @param idCpu The id of the calling EMT.
3391	*/
3392	DECLR3CALLBACKMEMBER(int, pfnVMNotifyCpuDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3393
3394	/**
3395	* Convenience wrapper for VMR3ReqCallU.
3396	*
3397	* This assumes (1) you're calling a function that returns an VBox status code
3398	* and that you do not wish to wait for it to complete.
3399	*
3400	* @returns VBox status code returned by VMR3ReqCallVU.
3401	*
3402	* @param pDevIns The device instance.
3403	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3404	* one of the following special values:
3405	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3406	* @param pfnFunction Pointer to the function to call.
3407	* @param cArgs Number of arguments following in the ellipsis.
3408	* @param Args Argument vector.
3409	*
3410	* @remarks See remarks on VMR3ReqCallVU.
3411	*/
3412	DECLR3CALLBACKMEMBER(int, pfnVMReqCallNoWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3413
3414	/**
3415	* Convenience wrapper for VMR3ReqCallU.
3416	*
3417	* This assumes (1) you're calling a function that returns void, (2) that you
3418	* wish to wait for ever for it to return, and (3) that it's priority request
3419	* that can be safely be handled during async suspend and power off.
3420	*
3421	* @returns VBox status code of VMR3ReqCallVU.
3422	*
3423	* @param pDevIns The device instance.
3424	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3425	* one of the following special values:
3426	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3427	* @param pfnFunction Pointer to the function to call.
3428	* @param cArgs Number of arguments following in the ellipsis.
3429	* @param Args Argument vector.
3430	*
3431	* @remarks See remarks on VMR3ReqCallVU.
3432	*/
3433	DECLR3CALLBACKMEMBER(int, pfnVMReqPriorityCallWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3434
3435	/**
3436	* Stops the VM and enters the debugger to look at the guest state.
3437	*
3438	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3439	* invoking this function directly.
3440	*
3441	* @returns VBox status code which must be passed up to the VMM.
3442	* @param pDevIns The device instance.
3443	* @param pszFile Filename of the assertion location.
3444	* @param iLine The linenumber of the assertion location.
3445	* @param pszFunction Function of the assertion location.
3446	* @param pszFormat Message. (optional)
3447	* @param args Message parameters.
3448	*/
3449	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3450	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3451
3452	/**
3453	* Register a info handler with DBGF.
3454	*
3455	* @returns VBox status code.
3456	* @param pDevIns The device instance.
3457	* @param pszName The identifier of the info.
3458	* @param pszDesc The description of the info and any arguments
3459	* the handler may take.
3460	* @param pfnHandler The handler function to be called to display the
3461	* info.
3462	*/
3463	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3464
3465	/**
3466	* Register a info handler with DBGF, argv style.
3467	*
3468	* @returns VBox status code.
3469	* @param pDevIns The device instance.
3470	* @param pszName The identifier of the info.
3471	* @param pszDesc The description of the info and any arguments
3472	* the handler may take.
3473	* @param pfnHandler The handler function to be called to display the
3474	* info.
3475	*/
3476	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3477
3478	/**
3479	* Registers a set of registers for a device.
3480	*
3481	* The @a pvUser argument of the getter and setter callbacks will be
3482	* @a pDevIns. The register names will be prefixed by the device name followed
3483	* immediately by the instance number.
3484	*
3485	* @returns VBox status code.
3486	* @param pDevIns The device instance.
3487	* @param paRegisters The register descriptors.
3488	*
3489	* @remarks The device critical section is NOT entered prior to working the
3490	* callbacks registered via this helper!
3491	*/
3492	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3493
3494	/**
3495	* Gets the trace buffer handle.
3496	*
3497	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3498	* really inteded for direct usage, thus no inline wrapper function.
3499	*
3500	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3501	* @param pDevIns The device instance.
3502	*/
3503	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3504
3505	/**
3506	* Report a bug check.
3507	*
3508	* @returns
3509	* @param pDevIns The device instance.
3510	* @param enmEvent The kind of BSOD event this is.
3511	* @param uBugCheck The bug check number.
3512	* @param uP1 The bug check parameter \#1.
3513	* @param uP2 The bug check parameter \#2.
3514	* @param uP3 The bug check parameter \#3.
3515	* @param uP4 The bug check parameter \#4.
3516	*
3517	* @thread EMT
3518	*/
3519	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnDBGFReportBugCheck,(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
3520	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4));
3521
3522	/**
3523	* Write core dump of the guest.
3524	*
3525	* @returns VBox status code.
3526	* @param pDevIns The device instance.
3527	* @param pszFilename The name of the file to which the guest core
3528	* dump should be written.
3529	* @param fReplaceFile Whether to replace the file or not.
3530	*
3531	* @remarks The VM may need to be suspended before calling this function in
3532	* order to truly stop all device threads and drivers. This function
3533	* only synchronizes EMTs.
3534	*/
3535	DECLR3CALLBACKMEMBER(int, pfnDBGFCoreWrite,(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile));
3536
3537	/**
3538	* Gets the logger info helper.
3539	* The returned info helper will unconditionally write all output to the log.
3540	*
3541	* @returns Pointer to the logger info helper.
3542	* @param pDevIns The device instance.
3543	*/
3544	DECLR3CALLBACKMEMBER(PCDBGFINFOHLP, pfnDBGFInfoLogHlp,(PPDMDEVINS pDevIns));
3545
3546	/**
3547	* Queries a 64-bit register value.
3548	*
3549	* @retval VINF_SUCCESS
3550	* @retval VERR_INVALID_VM_HANDLE
3551	* @retval VERR_INVALID_CPU_ID
3552	* @retval VERR_DBGF_REGISTER_NOT_FOUND
3553	* @retval VERR_DBGF_UNSUPPORTED_CAST
3554	* @retval VINF_DBGF_TRUNCATED_REGISTER
3555	* @retval VINF_DBGF_ZERO_EXTENDED_REGISTER
3556	*
3557	* @param pDevIns The device instance.
3558	* @param idDefCpu The default target CPU ID, VMCPUID_ANY if not
3559	* applicable. Can be OR'ed with
3560	* DBGFREG_HYPER_VMCPUID.
3561	* @param pszReg The register that's being queried. Except for
3562	* CPU registers, this must be on the form
3563	* "set.reg[.sub]".
3564	* @param pu64 Where to store the register value.
3565	*/
3566	DECLR3CALLBACKMEMBER(int, pfnDBGFRegNmQueryU64,(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64));
3567
3568	/**
3569	* Format a set of registers.
3570	*
3571	* This is restricted to registers from one CPU, that specified by @a idCpu.
3572	*
3573	* @returns VBox status code.
3574	* @param pDevIns The device instance.
3575	* @param idCpu The CPU ID of any CPU registers that may be
3576	* printed, pass VMCPUID_ANY if not applicable.
3577	* @param pszBuf The output buffer.
3578	* @param cbBuf The size of the output buffer.
3579	* @param pszFormat The format string. Register names are given by
3580	* %VR{name}, they take no arguments.
3581	* @param va Other format arguments.
3582	*/
3583	DECLR3CALLBACKMEMBER(int, pfnDBGFRegPrintfV,(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
3584	const char *pszFormat, va_list va));
3585
3586	/**
3587	* Registers a statistics sample.
3588	*
3589	* @param pDevIns Device instance of the DMA.
3590	* @param pvSample Pointer to the sample.
3591	* @param enmType Sample type. This indicates what pvSample is
3592	* pointing at.
3593	* @param pszName Sample name, unix path style. If this does not
3594	* start with a '/', the default prefix will be
3595	* prepended, otherwise it will be used as-is.
3596	* @param enmUnit Sample unit.
3597	* @param pszDesc Sample description.
3598	*/
3599	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3600
3601	/**
3602	* Same as pfnSTAMRegister except that the name is specified in a
3603	* RTStrPrintfV like fashion.
3604	*
3605	* @returns VBox status.
3606	* @param pDevIns Device instance of the DMA.
3607	* @param pvSample Pointer to the sample.
3608	* @param enmType Sample type. This indicates what pvSample is
3609	* pointing at.
3610	* @param enmVisibility Visibility type specifying whether unused
3611	* statistics should be visible or not.
3612	* @param enmUnit Sample unit.
3613	* @param pszDesc Sample description.
3614	* @param pszName Sample name format string, unix path style. If
3615	* this does not start with a '/', the default
3616	* prefix will be prepended, otherwise it will be
3617	* used as-is.
3618	* @param args Arguments to the format string.
3619	*/
3620	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3621	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3622	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3623
3624	/**
3625	* Registers a PCI device with the default PCI bus.
3626	*
3627	* If a PDM device has more than one PCI device, they must be registered in the
3628	* order of PDMDEVINSR3::apPciDevs.
3629	*
3630	* @returns VBox status code.
3631	* @param pDevIns The device instance.
3632	* @param pPciDev The PCI device structure.
3633	* This must be kept in the instance data.
3634	* The PCI configuration must be initialized before registration.
3635	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3636	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3637	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3638	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3639	* device number (0-31). This will be ignored if
3640	* the CFGM configuration contains a PCIDeviceNo
3641	* value.
3642	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3643	* function number (0-7). This will be ignored if
3644	* the CFGM configuration contains a PCIFunctionNo
3645	* value.
3646	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3647	* The pointer is saved, so don't free or changed.
3648	* @note The PCI device configuration is now implicit from the apPciDevs
3649	* index, meaning that the zero'th entry is the primary one and
3650	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3651	*/
3652	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3653	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3654
3655	/**
3656	* Initialize MSI or MSI-X emulation support for the given PCI device.
3657	*
3658	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3659	*
3660	* @returns VBox status code.
3661	* @param pDevIns The device instance.
3662	* @param pPciDev The PCI device. NULL is an alias for the first
3663	* one registered.
3664	* @param pMsiReg MSI emulation registration structure.
3665	*/
3666	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3667
3668	/**
3669	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3670	*
3671	* @returns VBox status code.
3672	* @param pDevIns The device instance.
3673	* @param pPciDev The PCI device structure. If NULL the default
3674	* PCI device for this device instance is used.
3675	* @param iRegion The region number.
3676	* @param cbRegion Size of the region.
3677	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3678	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3679	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3680	* @a fFlags, UINT64_MAX if no handle is passed
3681	* (old style).
3682	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3683	* handle is specified. The callback will be
3684	* invoked holding only the PDM lock. The device
3685	* lock will _not_ be taken (due to lock order).
3686	*/
3687	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3688	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3689	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3690
3691	/**
3692	* Register PCI configuration space read/write callbacks.
3693	*
3694	* @returns VBox status code.
3695	* @param pDevIns The device instance.
3696	* @param pPciDev The PCI device structure. If NULL the default
3697	* PCI device for this device instance is used.
3698	* @param pfnRead Pointer to the user defined PCI config read function.
3699	* to call default PCI config read function. Can be NULL.
3700	* @param pfnWrite Pointer to the user defined PCI config write function.
3701	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3702	* is NOT take because that is very likely be a lock order violation.
3703	* @thread EMT(0)
3704	* @note Only callable during VM creation.
3705	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3706	*/
3707	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3708	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3709
3710	/**
3711	* Perform a PCI configuration space write.
3712	*
3713	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3714	*
3715	* @returns Strict VBox status code (mainly DBGFSTOP).
3716	* @param pDevIns The device instance.
3717	* @param pPciDev The PCI device which config space is being read.
3718	* @param uAddress The config space address.
3719	* @param cb The size of the read: 1, 2 or 4 bytes.
3720	* @param u32Value The value to write.
3721	*/
3722	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3723	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3724
3725	/**
3726	* Perform a PCI configuration space read.
3727	*
3728	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3729	*
3730	* @returns Strict VBox status code (mainly DBGFSTOP).
3731	* @param pDevIns The device instance.
3732	* @param pPciDev The PCI device which config space is being read.
3733	* @param uAddress The config space address.
3734	* @param cb The size of the read: 1, 2 or 4 bytes.
3735	* @param pu32Value Where to return the value.
3736	*/
3737	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3738	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3739
3740	/**
3741	* Bus master physical memory read.
3742	*
3743	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3744	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3745	* @param pDevIns The device instance.
3746	* @param pPciDev The PCI device structure. If NULL the default
3747	* PCI device for this device instance is used.
3748	* @param GCPhys Physical address start reading from.
3749	* @param pvBuf Where to put the read bits.
3750	* @param cbRead How many bytes to read.
3751	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3752	* @thread Any thread, but the call may involve the emulation thread.
3753	*/
3754	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3755
3756	/**
3757	* Bus master physical memory write.
3758	*
3759	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3760	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3761	* @param pDevIns The device instance.
3762	* @param pPciDev The PCI device structure. If NULL the default
3763	* PCI device for this device instance is used.
3764	* @param GCPhys Physical address to write to.
3765	* @param pvBuf What to write.
3766	* @param cbWrite How many bytes to write.
3767	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3768	* @thread Any thread, but the call may involve the emulation thread.
3769	*/
3770	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3771
3772	/**
3773	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3774	* physical memory write operation.
3775	*
3776	* Refer pfnPhysGCPhys2CCPtr() for further details.
3777	*
3778	* @returns VBox status code.
3779	* @param pDevIns The device instance.
3780	* @param pPciDev The PCI device structure. If NULL the default
3781	* PCI device for this device instance is used.
3782	* @param GCPhys The guest physical address of the page that should be
3783	* mapped.
3784	* @param fFlags Flags reserved for future use, MBZ.
3785	* @param ppv Where to store the address corresponding to GCPhys.
3786	* @param pLock Where to store the lock information that
3787	* pfnPhysReleasePageMappingLock needs.
3788	*
3789	* @remarks Avoid calling this API from within critical sections (other than the PGM
3790	* one) because of the deadlock risk when we have to delegating the task to
3791	* an EMT.
3792	* @thread Any.
3793	*/
3794	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3795	void **ppv, PPGMPAGEMAPLOCK pLock));
3796
3797	/**
3798	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3799	* for a bus master physical memory read operation.
3800	*
3801	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3802	*
3803	* @returns VBox status code.
3804	* @param pDevIns The device instance.
3805	* @param pPciDev The PCI device structure. If NULL the default
3806	* PCI device for this device instance is used.
3807	* @param GCPhys The guest physical address of the page that
3808	* should be mapped.
3809	* @param fFlags Flags reserved for future use, MBZ.
3810	* @param ppv Where to store the address corresponding to
3811	* GCPhys.
3812	* @param pLock Where to store the lock information that
3813	* pfnPhysReleasePageMappingLock needs.
3814	*
3815	* @remarks Avoid calling this API from within critical sections.
3816	* @thread Any.
3817	*/
3818	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3819	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3820
3821	/**
3822	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3823	* master physical memory write operation.
3824	*
3825	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3826	* ASAP to release them.
3827	*
3828	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3829	*
3830	* @returns VBox status code.
3831	* @param pDevIns The device instance.
3832	* @param pPciDev The PCI device structure. If NULL the default
3833	* PCI device for this device instance is used.
3834	* @param cPages Number of pages to lock.
3835	* @param paGCPhysPages The guest physical address of the pages that
3836	* should be mapped (@a cPages entries).
3837	* @param fFlags Flags reserved for future use, MBZ.
3838	* @param papvPages Where to store the ring-3 mapping addresses
3839	* corresponding to @a paGCPhysPages.
3840	* @param paLocks Where to store the locking information that
3841	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3842	* in length).
3843	*/
3844	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3845	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3846	PPGMPAGEMAPLOCK paLocks));
3847
3848	/**
3849	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3850	* master physical memory read operation.
3851	*
3852	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3853	* ASAP to release them.
3854	*
3855	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3856	*
3857	* @returns VBox status code.
3858	* @param pDevIns The device instance.
3859	* @param pPciDev The PCI device structure. If NULL the default
3860	* PCI device for this device instance is used.
3861	* @param cPages Number of pages to lock.
3862	* @param paGCPhysPages The guest physical address of the pages that
3863	* should be mapped (@a cPages entries).
3864	* @param fFlags Flags reserved for future use, MBZ.
3865	* @param papvPages Where to store the ring-3 mapping addresses
3866	* corresponding to @a paGCPhysPages.
3867	* @param paLocks Where to store the lock information that
3868	* pfnPhysReleasePageMappingLock needs (@a cPages
3869	* in length).
3870	*/
3871	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3872	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3873	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3874
3875	/**
3876	* Sets the IRQ for the given PCI device.
3877	*
3878	* @param pDevIns The device instance.
3879	* @param pPciDev The PCI device structure. If NULL the default
3880	* PCI device for this device instance is used.
3881	* @param iIrq IRQ number to set.
3882	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3883	* @thread Any thread, but will involve the emulation thread.
3884	*/
3885	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3886
3887	/**
3888	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3889	* the request when not called from EMT.
3890	*
3891	* @param pDevIns The device instance.
3892	* @param pPciDev The PCI device structure. If NULL the default
3893	* PCI device for this device instance is used.
3894	* @param iIrq IRQ number to set.
3895	* @param iLevel IRQ level.
3896	* @thread Any thread, but will involve the emulation thread.
3897	*/
3898	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3899
3900	/**
3901	* Set ISA IRQ for a device.
3902	*
3903	* @param pDevIns The device instance.
3904	* @param iIrq IRQ number to set.
3905	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3906	* @thread Any thread, but will involve the emulation thread.
3907	*/
3908	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3909
3910	/**
3911	* Set the ISA IRQ for a device, but don't wait for EMT to process
3912	* the request when not called from EMT.
3913	*
3914	* @param pDevIns The device instance.
3915	* @param iIrq IRQ number to set.
3916	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3917	* @thread Any thread, but will involve the emulation thread.
3918	*/
3919	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3920
3921	/**
3922	* Attaches a driver (chain) to the device.
3923	*
3924	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3925	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3926	*
3927	* @returns VBox status code.
3928	* @param pDevIns The device instance.
3929	* @param iLun The logical unit to attach.
3930	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3931	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3932	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3933	* for the live of the device instance.
3934	*/
3935	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3936	PPDMIBASE ppBaseInterface, const char pszDesc));
3937
3938	/**
3939	* Detaches an attached driver (chain) from the device again.
3940	*
3941	* @returns VBox status code.
3942	* @param pDevIns The device instance.
3943	* @param pDrvIns The driver instance to detach.
3944	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3945	*/
3946	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3947
3948	/**
3949	* Reconfigures the driver chain for a LUN, detaching any driver currently
3950	* present there.
3951	*
3952	* Caller will have attach it, of course.
3953	*
3954	* @returns VBox status code.
3955	* @param pDevIns The device instance.
3956	* @param iLun The logical unit to reconfigure.
3957	* @param cDepth The depth of the driver chain. Determins the
3958	* size of @a papszDrivers and @a papConfigs.
3959	* @param papszDrivers The names of the drivers to configure in the
3960	* chain, first entry is the one immediately
3961	* below the device/LUN
3962	* @param papConfigs The configurations for each of the drivers
3963	* in @a papszDrivers array. NULL entries
3964	* corresponds to empty 'Config' nodes. This
3965	* function will take ownership of non-NULL
3966	* CFGM sub-trees and set the array member to
3967	* NULL, so the caller can do cleanups on
3968	* failure. This parameter is optional.
3969	* @param fFlags Reserved, MBZ.
3970	*/
3971	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3972	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3973
3974	/** @name Exported PDM Queue Functions
3975	* @{ */
3976	/**
3977	* Create a queue.
3978	*
3979	* @returns VBox status code.
3980	* @param pDevIns The device instance.
3981	* @param cbItem The size of a queue item.
3982	* @param cItems The number of items in the queue.
3983	* @param cMilliesInterval The number of milliseconds between polling the queue.
3984	* If 0 then the emulation thread will be notified whenever an item arrives.
3985	* @param pfnCallback The consumer function.
3986	* @param fRZEnabled Set if the queue should work in RC and R0.
3987	* @param pszName The queue base name. The instance number will be
3988	* appended automatically.
3989	* @param phQueue Where to store the queue handle on success.
3990	* @thread EMT(0)
3991	* @remarks The device critical section will NOT be entered before calling the
3992	* callback. No locks will be held, but for now it's safe to assume
3993	* that only one EMT will do queue callbacks at any one time.
3994	*/
3995	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3996	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3997	PDMQUEUEHANDLE *phQueue));
3998
3999	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
4000	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
4001	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
4002	/** @} */
4003
4004	/** @name PDM Task
4005	* @{ */
4006	/**
4007	* Create an asynchronous ring-3 task.
4008	*
4009	* @returns VBox status code.
4010	* @param pDevIns The device instance.
4011	* @param fFlags PDMTASK_F_XXX
4012	* @param pszName The function name or similar. Used for statistics,
4013	* so no slashes.
4014	* @param pfnCallback The task function.
4015	* @param pvUser User argument for the task function.
4016	* @param phTask Where to return the task handle.
4017	* @thread EMT(0)
4018	*/
4019	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
4020	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
4021	/**
4022	* Triggers the running the given task.
4023	*
4024	* @returns VBox status code.
4025	* @retval VINF_ALREADY_POSTED is the task is already pending.
4026	* @param pDevIns The device instance.
4027	* @param hTask The task to trigger.
4028	* @thread Any thread.
4029	*/
4030	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
4031	/** @} */
4032
4033	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
4034	* These semaphores can be signalled from ring-0.
4035	* @{ */
4036	/** @sa SUPSemEventCreate */
4037	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
4038	/** @sa SUPSemEventClose */
4039	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
4040	/** @sa SUPSemEventSignal */
4041	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
4042	/** @sa SUPSemEventWaitNoResume */
4043	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
4044	/** @sa SUPSemEventWaitNsAbsIntr */
4045	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
4046	/** @sa SUPSemEventWaitNsRelIntr */
4047	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
4048	/** @sa SUPSemEventGetResolution */
4049	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
4050	/** @} */
4051
4052	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
4053	* These semaphores can be signalled from ring-0.
4054	* @{ */
4055	/** @sa SUPSemEventMultiCreate */
4056	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
4057	/** @sa SUPSemEventMultiClose */
4058	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4059	/** @sa SUPSemEventMultiSignal */
4060	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4061	/** @sa SUPSemEventMultiReset */
4062	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4063	/** @sa SUPSemEventMultiWaitNoResume */
4064	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
4065	/** @sa SUPSemEventMultiWaitNsAbsIntr */
4066	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
4067	/** @sa SUPSemEventMultiWaitNsRelIntr */
4068	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
4069	/** @sa SUPSemEventMultiGetResolution */
4070	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
4071	/** @} */
4072
4073	/**
4074	* Initializes a PDM critical section.
4075	*
4076	* The PDM critical sections are derived from the IPRT critical sections, but
4077	* works in RC and R0 as well.
4078	*
4079	* @returns VBox status code.
4080	* @param pDevIns The device instance.
4081	* @param pCritSect Pointer to the critical section.
4082	* @param SRC_POS Use RT_SRC_POS.
4083	* @param pszNameFmt Format string for naming the critical section.
4084	* For statistics and lock validation.
4085	* @param va Arguments for the format string.
4086	*/
4087	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
4088	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4089
4090	/**
4091	* Gets the NOP critical section.
4092	*
4093	* @returns The ring-3 address of the NOP critical section.
4094	* @param pDevIns The device instance.
4095	*/
4096	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4097
4098	/**
4099	* Changes the device level critical section from the automatically created
4100	* default to one desired by the device constructor.
4101	*
4102	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
4103	* the additional contexts.
4104	*
4105	* @returns VBox status code.
4106	* @param pDevIns The device instance.
4107	* @param pCritSect The critical section to use. NULL is not
4108	* valid, instead use the NOP critical
4109	* section.
4110	*/
4111	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4112
4113	/** @name Exported PDM Critical Section Functions
4114	* @{ */
4115	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4116	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4117	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4118	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4119	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4120	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4121	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4122	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4123	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4124	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4125	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
4126	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4127	/** @} */
4128
4129	/** @name Exported PDM Read/Write Critical Section Functions
4130	* @{ */
4131	DECLR3CALLBACKMEMBER(int, pfnCritSectRwInit,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
4132	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4133	DECLR3CALLBACKMEMBER(int, pfnCritSectRwDelete,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4134
4135	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4136	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4137	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4138	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4139	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4140
4141	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4142	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4143	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4144	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4145	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4146
4147	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4148	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
4149	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4150	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4151	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4152	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4153	/** @} */
4154
4155	/**
4156	* Creates a PDM thread.
4157	*
4158	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
4159	* resuming, and destroying the thread as the VM state changes.
4160	*
4161	* @returns VBox status code.
4162	* @param pDevIns The device instance.
4163	* @param ppThread Where to store the thread 'handle'.
4164	* @param pvUser The user argument to the thread function.
4165	* @param pfnThread The thread function.
4166	* @param pfnWakeup The wakup callback. This is called on the EMT
4167	* thread when a state change is pending.
4168	* @param cbStack See RTThreadCreate.
4169	* @param enmType See RTThreadCreate.
4170	* @param pszName See RTThreadCreate.
4171	* @remarks The device critical section will NOT be entered prior to invoking
4172	* the function pointers.
4173	*/
4174	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
4175	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
4176
4177	/** @name Exported PDM Thread Functions
4178	* @{ */
4179	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
4180	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
4181	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
4182	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
4183	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
4184	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
4185	/** @} */
4186
4187	/**
4188	* Set up asynchronous handling of a suspend, reset or power off notification.
4189	*
4190	* This shall only be called when getting the notification. It must be called
4191	* for each one.
4192	*
4193	* @returns VBox status code.
4194	* @param pDevIns The device instance.
4195	* @param pfnAsyncNotify The callback.
4196	* @thread EMT(0)
4197	* @remarks The caller will enter the device critical section prior to invoking
4198	* the callback.
4199	*/
4200	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
4201
4202	/**
4203	* Notify EMT(0) that the device has completed the asynchronous notification
4204	* handling.
4205	*
4206	* This can be called at any time, spurious calls will simply be ignored.
4207	*
4208	* @param pDevIns The device instance.
4209	* @thread Any
4210	*/
4211	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
4212
4213	/**
4214	* Register the RTC device.
4215	*
4216	* @returns VBox status code.
4217	* @param pDevIns The device instance.
4218	* @param pRtcReg Pointer to a RTC registration structure.
4219	* @param ppRtcHlp Where to store the pointer to the helper
4220	* functions.
4221	*/
4222	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
4223
4224	/**
4225	* Register a PCI Bus.
4226	*
4227	* @returns VBox status code, but the positive values 0..31 are used to indicate
4228	* bus number rather than informational status codes.
4229	* @param pDevIns The device instance.
4230	* @param pPciBusReg Pointer to PCI bus registration structure.
4231	* @param ppPciHlp Where to store the pointer to the PCI Bus
4232	* helpers.
4233	* @param piBus Where to return the PDM bus number. Optional.
4234	*/
4235	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
4236	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
4237
4238	/**
4239	* Register the IOMMU device.
4240	*
4241	* @returns VBox status code.
4242	* @param pDevIns The device instance.
4243	* @param pIommuReg Pointer to a IOMMU registration structure.
4244	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
4245	* helpers.
4246	* @param pidxIommu Where to return the IOMMU index. Optional.
4247	*/
4248	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
4249	uint32_t *pidxIommu));
4250
4251	/**
4252	* Register the PIC device.
4253	*
4254	* @returns VBox status code.
4255	* @param pDevIns The device instance.
4256	* @param pPicReg Pointer to a PIC registration structure.
4257	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
4258	* helpers.
4259	* @sa PDMDevHlpPICSetUpContext
4260	*/
4261	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4262
4263	/**
4264	* Register the APIC device.
4265	*
4266	* @returns VBox status code.
4267	* @param pDevIns The device instance.
4268	*/
4269	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
4270
4271	/**
4272	* Register the I/O APIC device.
4273	*
4274	* @returns VBox status code.
4275	* @param pDevIns The device instance.
4276	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4277	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
4278	* helpers.
4279	*/
4280	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4281
4282	/**
4283	* Register the HPET device.
4284	*
4285	* @returns VBox status code.
4286	* @param pDevIns The device instance.
4287	* @param pHpetReg Pointer to a HPET registration structure.
4288	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4289	* helpers.
4290	*/
4291	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4292
4293	/**
4294	* Register a raw PCI device.
4295	*
4296	* @returns VBox status code.
4297	* @param pDevIns The device instance.
4298	* @param pPciRawReg Pointer to a raw PCI registration structure.
4299	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4300	* device helpers.
4301	*/
4302	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4303
4304	/**
4305	* Register the DMA device.
4306	*
4307	* @returns VBox status code.
4308	* @param pDevIns The device instance.
4309	* @param pDmacReg Pointer to a DMAC registration structure.
4310	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4311	*/
4312	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4313
4314	/**
4315	* Register transfer function for DMA channel.
4316	*
4317	* @returns VBox status code.
4318	* @param pDevIns The device instance.
4319	* @param uChannel Channel number.
4320	* @param pfnTransferHandler Device specific transfer callback function.
4321	* @param pvUser User pointer to pass to the callback.
4322	* @thread EMT
4323	*/
4324	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4325
4326	/**
4327	* Read memory.
4328	*
4329	* @returns VBox status code.
4330	* @param pDevIns The device instance.
4331	* @param uChannel Channel number.
4332	* @param pvBuffer Pointer to target buffer.
4333	* @param off DMA position.
4334	* @param cbBlock Block size.
4335	* @param pcbRead Where to store the number of bytes which was
4336	* read. optional.
4337	* @thread EMT
4338	*/
4339	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4340
4341	/**
4342	* Write memory.
4343	*
4344	* @returns VBox status code.
4345	* @param pDevIns The device instance.
4346	* @param uChannel Channel number.
4347	* @param pvBuffer Memory to write.
4348	* @param off DMA position.
4349	* @param cbBlock Block size.
4350	* @param pcbWritten Where to store the number of bytes which was
4351	* written. optional.
4352	* @thread EMT
4353	*/
4354	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4355
4356	/**
4357	* Set the DREQ line.
4358	*
4359	* @returns VBox status code.
4360	* @param pDevIns Device instance.
4361	* @param uChannel Channel number.
4362	* @param uLevel Level of the line.
4363	* @thread EMT
4364	*/
4365	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4366
4367	/**
4368	* Get channel mode.
4369	*
4370	* @returns Channel mode. See specs.
4371	* @param pDevIns The device instance.
4372	* @param uChannel Channel number.
4373	* @thread EMT
4374	*/
4375	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4376
4377	/**
4378	* Schedule DMA execution.
4379	*
4380	* @param pDevIns The device instance.
4381	* @thread Any thread.
4382	*/
4383	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4384
4385	/**
4386	* Write CMOS value and update the checksum(s).
4387	*
4388	* @returns VBox status code.
4389	* @param pDevIns The device instance.
4390	* @param iReg The CMOS register index.
4391	* @param u8Value The CMOS register value.
4392	* @thread EMT
4393	*/
4394	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4395
4396	/**
4397	* Read CMOS value.
4398	*
4399	* @returns VBox status code.
4400	* @param pDevIns The device instance.
4401	* @param iReg The CMOS register index.
4402	* @param pu8Value Where to store the CMOS register value.
4403	* @thread EMT
4404	*/
4405	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4406
4407	/**
4408	* Assert that the current thread is the emulation thread.
4409	*
4410	* @returns True if correct.
4411	* @returns False if wrong.
4412	* @param pDevIns The device instance.
4413	* @param pszFile Filename of the assertion location.
4414	* @param iLine The linenumber of the assertion location.
4415	* @param pszFunction Function of the assertion location.
4416	*/
4417	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4418
4419	/**
4420	* Assert that the current thread is NOT the emulation thread.
4421	*
4422	* @returns True if correct.
4423	* @returns False if wrong.
4424	* @param pDevIns The device instance.
4425	* @param pszFile Filename of the assertion location.
4426	* @param iLine The linenumber of the assertion location.
4427	* @param pszFunction Function of the assertion location.
4428	*/
4429	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4430
4431	/**
4432	* Resolves the symbol for a raw-mode context interface.
4433	*
4434	* @returns VBox status code.
4435	* @param pDevIns The device instance.
4436	* @param pvInterface The interface structure.
4437	* @param cbInterface The size of the interface structure.
4438	* @param pszSymPrefix What to prefix the symbols in the list with
4439	* before resolving them. This must start with
4440	* 'dev' and contain the driver name.
4441	* @param pszSymList List of symbols corresponding to the interface.
4442	* There is generally a there is generally a define
4443	* holding this list associated with the interface
4444	* definition (INTERFACE_SYM_LIST). For more
4445	* details see PDMR3LdrGetInterfaceSymbols.
4446	* @thread EMT
4447	*/
4448	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4449	const char pszSymPrefix, const char pszSymList));
4450
4451	/**
4452	* Resolves the symbol for a ring-0 context interface.
4453	*
4454	* @returns VBox status code.
4455	* @param pDevIns The device instance.
4456	* @param pvInterface The interface structure.
4457	* @param cbInterface The size of the interface structure.
4458	* @param pszSymPrefix What to prefix the symbols in the list with
4459	* before resolving them. This must start with
4460	* 'dev' and contain the driver name.
4461	* @param pszSymList List of symbols corresponding to the interface.
4462	* There is generally a there is generally a define
4463	* holding this list associated with the interface
4464	* definition (INTERFACE_SYM_LIST). For more
4465	* details see PDMR3LdrGetInterfaceSymbols.
4466	* @thread EMT
4467	*/
4468	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4469	const char pszSymPrefix, const char pszSymList));
4470
4471	/**
4472	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4473	*
4474	* @returns VBox status code.
4475	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4476	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4477	*
4478	* @param pDevIns The device instance.
4479	* @param uOperation The operation to perform.
4480	* @param u64Arg 64-bit integer argument.
4481	* @thread EMT
4482	*/
4483	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4484
4485	/**
4486	* Gets the reason for the most recent VM suspend.
4487	*
4488	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4489	* suspend has been made or if the pDevIns is invalid.
4490	* @param pDevIns The device instance.
4491	*/
4492	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4493
4494	/**
4495	* Gets the reason for the most recent VM resume.
4496	*
4497	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4498	* resume has been made or if the pDevIns is invalid.
4499	* @param pDevIns The device instance.
4500	*/
4501	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4502
4503	/**
4504	* Requests the mapping of multiple guest page into ring-3.
4505	*
4506	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4507	* ASAP to release them.
4508	*
4509	* This API will assume your intention is to write to the pages, and will
4510	* therefore replace shared and zero pages. If you do not intend to modify the
4511	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4512	*
4513	* @returns VBox status code.
4514	* @retval VINF_SUCCESS on success.
4515	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4516	* backing or if any of the pages the page has any active access
4517	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4518	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4519	* an invalid physical address.
4520	*
4521	* @param pDevIns The device instance.
4522	* @param cPages Number of pages to lock.
4523	* @param paGCPhysPages The guest physical address of the pages that
4524	* should be mapped (@a cPages entries).
4525	* @param fFlags Flags reserved for future use, MBZ.
4526	* @param papvPages Where to store the ring-3 mapping addresses
4527	* corresponding to @a paGCPhysPages.
4528	* @param paLocks Where to store the locking information that
4529	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4530	* in length).
4531	*
4532	* @remark Avoid calling this API from within critical sections (other than the
4533	* PGM one) because of the deadlock risk when we have to delegating the
4534	* task to an EMT.
4535	* @thread Any.
4536	* @since 6.0.6
4537	*/
4538	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4539	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4540
4541	/**
4542	* Requests the mapping of multiple guest page into ring-3, for reading only.
4543	*
4544	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4545	* ASAP to release them.
4546	*
4547	* @returns VBox status code.
4548	* @retval VINF_SUCCESS on success.
4549	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4550	* backing or if any of the pages the page has an active ALL access
4551	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4552	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4553	* an invalid physical address.
4554	*
4555	* @param pDevIns The device instance.
4556	* @param cPages Number of pages to lock.
4557	* @param paGCPhysPages The guest physical address of the pages that
4558	* should be mapped (@a cPages entries).
4559	* @param fFlags Flags reserved for future use, MBZ.
4560	* @param papvPages Where to store the ring-3 mapping addresses
4561	* corresponding to @a paGCPhysPages.
4562	* @param paLocks Where to store the lock information that
4563	* pfnPhysReleasePageMappingLock needs (@a cPages
4564	* in length).
4565	*
4566	* @remark Avoid calling this API from within critical sections.
4567	* @thread Any.
4568	* @since 6.0.6
4569	*/
4570	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4571	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4572
4573	/**
4574	* Release the mappings of multiple guest pages.
4575	*
4576	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4577	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4578	*
4579	* @param pDevIns The device instance.
4580	* @param cPages Number of pages to unlock.
4581	* @param paLocks The lock structures initialized by the mapping
4582	* function (@a cPages in length).
4583	* @thread Any.
4584	* @since 6.0.6
4585	*/
4586	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4587
4588	/**
4589	* Returns the micro architecture used for the guest.
4590	*
4591	* @returns CPU micro architecture enum.
4592	* @param pDevIns The device instance.
4593	*/
4594	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4595
4596	/**
4597	* Get the number of physical and linear address bits supported by the guest.
4598	*
4599	* @param pDevIns The device instance.
4600	* @param pcPhysAddrWidth Where to store the number of physical address bits
4601	* supported by the guest.
4602	* @param pcLinearAddrWidth Where to store the number of linear address bits
4603	* supported by the guest.
4604	*/
4605	DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4606	uint8_t *pcLinearAddrWidth));
4607
4608	/**
4609	* Gets the scalable bus frequency.
4610	*
4611	* The bus frequency is used as a base in several MSRs that gives the CPU and
4612	* other frequency ratios.
4613	*
4614	* @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
4615	* @param pDevIns The device instance.
4616	*/
4617	DECLR3CALLBACKMEMBER(uint64_t, pfnCpuGetGuestScalableBusFrequency,(PPDMDEVINS pDevIns));
4618
4619	/** Space reserved for future members.
4620	* @{ */
4621	/**
4622	* Deregister zero or more samples given their name prefix.
4623	*
4624	* @returns VBox status code.
4625	* @param pDevIns The device instance.
4626	* @param pszPrefix The name prefix of the samples to remove. If this does
4627	* not start with a '/', the default prefix will be
4628	* prepended, otherwise it will be used as-is.
4629	*/
4630	DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4631	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4632	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4633	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4634	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4635	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4636	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4637	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4638	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4639	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4640	/** @} */
4641
4642
4643	/** API available to trusted devices only.
4644	*
4645	* These APIs are providing unrestricted access to the guest and the VM,
4646	* or they are interacting intimately with PDM.
4647	*
4648	* @{
4649	*/
4650
4651	/**
4652	* Gets the user mode VM handle. Restricted API.
4653	*
4654	* @returns User mode VM Handle.
4655	* @param pDevIns The device instance.
4656	*/
4657	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4658
4659	/**
4660	* Gets the global VM handle. Restricted API.
4661	*
4662	* @returns VM Handle.
4663	* @param pDevIns The device instance.
4664	*/
4665	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4666
4667	/**
4668	* Gets the VMCPU handle. Restricted API.
4669	*
4670	* @returns VMCPU Handle.
4671	* @param pDevIns The device instance.
4672	*/
4673	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4674
4675	/**
4676	* The the VM CPU ID of the current thread (restricted API).
4677	*
4678	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4679	* @param pDevIns The device instance.
4680	*/
4681	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4682
4683	/**
4684	* Registers the VMM device heap or notifies about mapping/unmapping.
4685	*
4686	* This interface serves three purposes:
4687	*
4688	* -# Register the VMM device heap during device construction
4689	* for the HM to use.
4690	* -# Notify PDM/HM that it's mapped into guest address
4691	* space (i.e. usable).
4692	* -# Notify PDM/HM that it is being unmapped from the guest
4693	* address space (i.e. not usable).
4694	*
4695	* @returns VBox status code.
4696	* @param pDevIns The device instance.
4697	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4698	* not mapped.
4699	* @param pvHeap Ring 3 heap pointer.
4700	* @param cbHeap Size of the heap.
4701	* @thread EMT.
4702	*/
4703	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4704
4705	/**
4706	* Registers the firmware (BIOS, EFI) device with PDM.
4707	*
4708	* The firmware provides a callback table and gets a special PDM helper table.
4709	* There can only be one firmware device for a VM.
4710	*
4711	* @returns VBox status code.
4712	* @param pDevIns The device instance.
4713	* @param pFwReg Firmware registration structure.
4714	* @param ppFwHlp Where to return the firmware helper structure.
4715	* @remarks Only valid during device construction.
4716	* @thread EMT(0)
4717	*/
4718	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4719
4720	/**
4721	* Resets the VM.
4722	*
4723	* @returns The appropriate VBox status code to pass around on reset.
4724	* @param pDevIns The device instance.
4725	* @param fFlags PDMVMRESET_F_XXX flags.
4726	* @thread The emulation thread.
4727	*/
4728	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4729
4730	/**
4731	* Suspends the VM.
4732	*
4733	* @returns The appropriate VBox status code to pass around on suspend.
4734	* @param pDevIns The device instance.
4735	* @thread The emulation thread.
4736	*/
4737	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4738
4739	/**
4740	* Suspends, saves and powers off the VM.
4741	*
4742	* @returns The appropriate VBox status code to pass around.
4743	* @param pDevIns The device instance.
4744	* @thread An emulation thread.
4745	*/
4746	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4747
4748	/**
4749	* Power off the VM.
4750	*
4751	* @returns The appropriate VBox status code to pass around on power off.
4752	* @param pDevIns The device instance.
4753	* @thread The emulation thread.
4754	*/
4755	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4756
4757	/**
4758	* Checks if the Gate A20 is enabled or not.
4759	*
4760	* @returns true if A20 is enabled.
4761	* @returns false if A20 is disabled.
4762	* @param pDevIns The device instance.
4763	* @thread The emulation thread.
4764	*/
4765	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4766
4767	/**
4768	* Enables or disables the Gate A20.
4769	*
4770	* @param pDevIns The device instance.
4771	* @param fEnable Set this flag to enable the Gate A20; clear it
4772	* to disable.
4773	* @thread The emulation thread.
4774	*/
4775	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4776
4777	/**
4778	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4779	* thread.
4780	*
4781	* @param pDevIns The device instance.
4782	* @param iLeaf The CPUID leaf to get.
4783	* @param pEax Where to store the EAX value.
4784	* @param pEbx Where to store the EBX value.
4785	* @param pEcx Where to store the ECX value.
4786	* @param pEdx Where to store the EDX value.
4787	* @thread EMT.
4788	*/
4789	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4790
4791	/**
4792	* Gets the main execution engine for the VM.
4793	*
4794	* @returns VM_EXEC_ENGINE_XXX
4795	* @param pDevIns The device instance.
4796	*/
4797	DECLR3CALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
4798
4799	/**
4800	* Get the current virtual clock time in a VM. The clock frequency must be
4801	* queried separately.
4802	*
4803	* @returns Current clock time.
4804	* @param pDevIns The device instance.
4805	*/
4806	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4807
4808	/**
4809	* Get the frequency of the virtual clock.
4810	*
4811	* @returns The clock frequency (not variable at run-time).
4812	* @param pDevIns The device instance.
4813	*/
4814	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4815
4816	/**
4817	* Get the current virtual clock time in a VM, in nanoseconds.
4818	*
4819	* @returns Current clock time (in ns).
4820	* @param pDevIns The device instance.
4821	*/
4822	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4823
4824	/**
4825	* Get the timestamp frequency.
4826	*
4827	* @returns Number of ticks per second.
4828	* @param pDevIns The device instance.
4829	*/
4830	DECLR3CALLBACKMEMBER(uint64_t, pfnTMCpuTicksPerSecond,(PPDMDEVINS pDevIns));
4831
4832	/**
4833	* Gets the support driver session.
4834	*
4835	* This is intended for working with the semaphore API.
4836	*
4837	* @returns Support driver session handle.
4838	* @param pDevIns The device instance.
4839	*/
4840	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4841
4842	/**
4843	* Queries a generic object from the VMM user.
4844	*
4845	* @returns Pointer to the object if found, NULL if not.
4846	* @param pDevIns The device instance.
4847	* @param pUuid The UUID of what's being queried. The UUIDs and
4848	* the usage conventions are defined by the user.
4849	*
4850	* @note It is strictly forbidden to call this internally in VBox! This
4851	* interface is exclusively for hacks in externally developed devices.
4852	*/
4853	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4854
4855	/**
4856	* Register a physical page access handler type.
4857	*
4858	* @returns VBox status code.
4859	* @param pDevIns The device instance.
4860	* @param enmKind The kind of access handler.
4861	* @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4862	* @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4863	* handler should be called.
4864	* @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4865	* ring-3 handler should be called.
4866	* @param pszHandlerRC The name of the raw-mode context handler, NULL if
4867	* the ring-3 handler should be called.
4868	* @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4869	* if the ring-3 handler should be called.
4870	* @param pszDesc The type description.
4871	* @param phType Where to return the type handle (cross context
4872	* safe).
4873	*/
4874	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4875	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4876	const char pszHandlerR0, const char pszPfHandlerR0,
4877	const char pszHandlerRC, const char pszPfHandlerRC,
4878	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4879
4880	/**
4881	* Register a access handler for a physical range.
4882	*
4883	* @returns VBox status code.
4884	* @retval VINF_SUCCESS when successfully installed.
4885	* @retval VINF_PGM_GCPHYS_ALIASED when the shadow PTs could be updated because
4886	* the guest page aliased or/and mapped by multiple PTs. A CR3 sync has been
4887	* flagged together with a pool clearing.
4888	* @retval VERR_PGM_HANDLER_PHYSICAL_CONFLICT if the range conflicts with an existing
4889	* one. A debug assertion is raised.
4890	*
4891	* @param pDevIns The device instance.
4892	* @param GCPhys Start physical address.
4893	* @param GCPhysLast Last physical address. (inclusive)
4894	* @param hType The handler type registration handle.
4895	* @param pvUserR3 User argument to the R3 handler.
4896	* @param pvUserR0 User argument to the R0 handler.
4897	* @param pvUserRC User argument to the RC handler. This can be a value
4898	* less that 0x10000 or a (non-null) pointer that is
4899	* automatically relocated.
4900	* @param pszDesc Description of this handler. If NULL, the type
4901	* description will be used instead.
4902	*/
4903	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalRegister, (PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
4904	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4905	RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc));
4906
4907	/**
4908	* Deregister a physical page access handler.
4909	*
4910	* @returns VBox status code.
4911	* @param pDevIns The device instance.
4912	* @param GCPhys Start physical address.
4913	*/
4914	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalDeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4915
4916	/**
4917	* Temporarily turns off the access monitoring of a page within a monitored
4918	* physical write/all page access handler region.
4919	*
4920	* Use this when no further \#PFs are required for that page. Be aware that
4921	* a page directory sync might reset the flags, and turn on access monitoring
4922	* for the page.
4923	*
4924	* The caller must do required page table modifications.
4925	*
4926	* @returns VBox status code.
4927	* @param pDevIns The device instance.
4928	* @param GCPhys The start address of the access handler. This
4929	* must be a fully page aligned range or we risk
4930	* messing up other handlers installed for the
4931	* start and end pages.
4932	* @param GCPhysPage The physical address of the page to turn off
4933	* access monitoring for.
4934	*/
4935	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
4936
4937	/**
4938	* Resets any modifications to individual pages in a physical page access
4939	* handler region.
4940	*
4941	* This is used in pair with PGMHandlerPhysicalPageTempOff(),
4942	* PGMHandlerPhysicalPageAliasMmio2() or PGMHandlerPhysicalPageAliasHC().
4943	*
4944	* @returns VBox status code.
4945	* @param pDevIns The device instance.
4946	* @param GCPhys The start address of the handler regions, i.e. what you
4947	* passed to PGMR3HandlerPhysicalRegister(),
4948	* PGMHandlerPhysicalRegisterEx() or
4949	* PGMHandlerPhysicalModify().
4950	*/
4951	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalReset,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4952
4953	/**
4954	* Registers the guest memory range that can be used for patching.
4955	*
4956	* @returns VBox status code.
4957	* @param pDevIns The device instance.
4958	* @param GCPtrPatchMem Patch memory range.
4959	* @param cbPatchMem Size of the memory range.
4960	*/
4961	DECLR3CALLBACKMEMBER(int, pfnVMMRegisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4962
4963	/**
4964	* Deregisters the guest memory range that can be used for patching.
4965	*
4966	* @returns VBox status code.
4967	* @param pDevIns The device instance.
4968	* @param GCPtrPatchMem Patch memory range.
4969	* @param cbPatchMem Size of the memory range.
4970	*/
4971	DECLR3CALLBACKMEMBER(int, pfnVMMDeregisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4972
4973	/**
4974	* Registers a new shared module for the VM
4975	*
4976	* @returns VBox status code.
4977	* @param pDevIns The device instance.
4978	* @param enmGuestOS Guest OS type.
4979	* @param pszModuleName Module name.
4980	* @param pszVersion Module version.
4981	* @param GCBaseAddr Module base address.
4982	* @param cbModule Module size.
4983	* @param cRegions Number of shared region descriptors.
4984	* @param paRegions Shared region(s).
4985	*/
4986	DECLR3CALLBACKMEMBER(int, pfnSharedModuleRegister,(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
4987	RTGCPTR GCBaseAddr, uint32_t cbModule,
4988	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions));
4989
4990	/**
4991	* Unregisters a shared module for the VM
4992	*
4993	* @returns VBox status code.
4994	* @param pDevIns The device instance.
4995	* @param pszModuleName Module name.
4996	* @param pszVersion Module version.
4997	* @param GCBaseAddr Module base address.
4998	* @param cbModule Module size.
4999	*/
5000	DECLR3CALLBACKMEMBER(int, pfnSharedModuleUnregister,(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
5001	RTGCPTR GCBaseAddr, uint32_t cbModule));
5002
5003	/**
5004	* Query the state of a page in a shared module
5005	*
5006	* @returns VBox status code.
5007	* @param pDevIns The device instance.
5008	* @param GCPtrPage Page address.
5009	* @param pfShared Shared status (out).
5010	* @param pfPageFlags Page flags (out).
5011	*/
5012	DECLR3CALLBACKMEMBER(int, pfnSharedModuleGetPageState, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags));
5013
5014	/**
5015	* Check all registered modules for changes.
5016	*
5017	* @returns VBox status code.
5018	* @param pDevIns The device instance.
5019	*/
5020	DECLR3CALLBACKMEMBER(int, pfnSharedModuleCheckAll,(PPDMDEVINS pDevIns));
5021
5022	/**
5023	* Query the interface of the top level driver on a LUN.
5024	*
5025	* @returns VBox status code.
5026	* @param pDevIns The device instance.
5027	* @param pszDevice Device name.
5028	* @param iInstance Device instance.
5029	* @param iLun The Logical Unit to obtain the interface of.
5030	* @param ppBase Where to store the base interface pointer.
5031	*
5032	* @remark We're not doing any locking ATM, so don't try call this at times when the
5033	* device chain is known to be updated.
5034	*/
5035	DECLR3CALLBACKMEMBER(int, pfnQueryLun,(PPDMDEVINS pDevIns, const char *pszDevice, unsigned iInstance, unsigned iLun, PPPDMIBASE ppBase));
5036
5037	/**
5038	* Registers the GIM device with VMM.
5039	*
5040	* @param pDevIns Pointer to the GIM device instance.
5041	* @param pDbg Pointer to the GIM device debug structure, can be
5042	* NULL.
5043	*/
5044	DECLR3CALLBACKMEMBER(void, pfnGIMDeviceRegister,(PPDMDEVINS pDevIns, PGIMDEBUG pDbg));
5045
5046	/**
5047	* Gets debug setup specified by the provider.
5048	*
5049	* @returns VBox status code.
5050	* @param pDevIns Pointer to the GIM device instance.
5051	* @param pDbgSetup Where to store the debug setup details.
5052	*/
5053	DECLR3CALLBACKMEMBER(int, pfnGIMGetDebugSetup,(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup));
5054
5055	/**
5056	* Returns the array of MMIO2 regions that are expected to be registered and
5057	* later mapped into the guest-physical address space for the GIM provider
5058	* configured for the VM.
5059	*
5060	* @returns Pointer to an array of GIM MMIO2 regions, may return NULL.
5061	* @param pDevIns Pointer to the GIM device instance.
5062	* @param pcRegions Where to store the number of items in the array.
5063	*
5064	* @remarks The caller does not own and therefore must -NOT- try to free the
5065	* returned pointer.
5066	*/
5067	DECLR3CALLBACKMEMBER(PGIMMMIO2REGION, pfnGIMGetMmio2Regions,(PPDMDEVINS pDevIns, uint32_t *pcRegions));
5068
5069	/** @} */
5070
5071	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
5072	uint32_t u32TheEnd;
5073	} PDMDEVHLPR3;
5074	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
5075	/** Pointer to the R3 PDM Device API. */
5076	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
5077	/** Pointer to the R3 PDM Device API, const variant. */
5078	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
5079
5080
5081	/**
5082	* PDM Device API - RC Variant.
5083	*/
5084	typedef struct PDMDEVHLPRC
5085	{
5086	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
5087	uint32_t u32Version;
5088
5089	/**
5090	* Sets up raw-mode context callback handlers for an I/O port range.
5091	*
5092	* The range must have been registered in ring-3 first using
5093	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5094	*
5095	* @returns VBox status.
5096	* @param pDevIns The device instance to register the ports with.
5097	* @param hIoPorts The I/O port range handle.
5098	* @param pfnOut Pointer to function which is gonna handle OUT
5099	* operations. Optional.
5100	* @param pfnIn Pointer to function which is gonna handle IN operations.
5101	* Optional.
5102	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5103	* operations. Optional.
5104	* @param pfnInStr Pointer to function which is gonna handle string IN
5105	* operations. Optional.
5106	* @param pvUser User argument to pass to the callbacks.
5107	*
5108	* @remarks Caller enters the device critical section prior to invoking the
5109	* registered callback methods.
5110	*
5111	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
5112	* PDMDevHlpIoPortUnmap.
5113	*/
5114	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5115	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5116	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5117	void *pvUser));
5118
5119	/**
5120	* Sets up raw-mode context callback handlers for an MMIO region.
5121	*
5122	* The region must have been registered in ring-3 first using
5123	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
5124	*
5125	* @returns VBox status.
5126	* @param pDevIns The device instance to register the ports with.
5127	* @param hRegion The MMIO region handle.
5128	* @param pfnWrite Pointer to function which is gonna handle Write
5129	* operations.
5130	* @param pfnRead Pointer to function which is gonna handle Read
5131	* operations.
5132	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5133	* operations. (optional)
5134	* @param pvUser User argument to pass to the callbacks.
5135	*
5136	* @remarks Caller enters the device critical section prior to invoking the
5137	* registered callback methods.
5138	*
5139	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
5140	* PDMDevHlpMmioUnmap.
5141	*/
5142	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5143	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5144
5145	/**
5146	* Sets up a raw-mode mapping for an MMIO2 region.
5147	*
5148	* The region must have been created in ring-3 first using
5149	* PDMDevHlpMmio2Create().
5150	*
5151	* @returns VBox status.
5152	* @param pDevIns The device instance to register the ports with.
5153	* @param hRegion The MMIO2 region handle.
5154	* @param offSub Start of what to map into raw-mode. Must be page aligned.
5155	* @param cbSub Number of bytes to map into raw-mode. Must be page
5156	* aligned. Zero is an alias for everything.
5157	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5158	* @thread EMT(0)
5159	* @note Only available at VM creation time.
5160	*
5161	* @sa PDMDevHlpMmio2Create().
5162	*/
5163	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
5164	size_t offSub, size_t cbSub, void **ppvMapping));
5165
5166	/**
5167	* Bus master physical memory read from the given PCI device.
5168	*
5169	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
5170	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
5171	* @param pDevIns The device instance.
5172	* @param pPciDev The PCI device structure. If NULL the default
5173	* PCI device for this device instance is used.
5174	* @param GCPhys Physical address start reading from.
5175	* @param pvBuf Where to put the read bits.
5176	* @param cbRead How many bytes to read.
5177	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5178	* @thread Any thread, but the call may involve the emulation thread.
5179	*/
5180	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5181	void *pvBuf, size_t cbRead, uint32_t fFlags));
5182
5183	/**
5184	* Bus master physical memory write from the given PCI device.
5185	*
5186	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
5187	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
5188	* @param pDevIns The device instance.
5189	* @param pPciDev The PCI device structure. If NULL the default
5190	* PCI device for this device instance is used.
5191	* @param GCPhys Physical address to write to.
5192	* @param pvBuf What to write.
5193	* @param cbWrite How many bytes to write.
5194	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5195	* @thread Any thread, but the call may involve the emulation thread.
5196	*/
5197	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5198	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5199
5200	/**
5201	* Set the IRQ for the given PCI device.
5202	*
5203	* @param pDevIns Device instance.
5204	* @param pPciDev The PCI device structure. If NULL the default
5205	* PCI device for this device instance is used.
5206	* @param iIrq IRQ number to set.
5207	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5208	* @thread Any thread, but will involve the emulation thread.
5209	*/
5210	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5211
5212	/**
5213	* Set ISA IRQ for a device.
5214	*
5215	* @param pDevIns Device instance.
5216	* @param iIrq IRQ number to set.
5217	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5218	* @thread Any thread, but will involve the emulation thread.
5219	*/
5220	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5221
5222	/**
5223	* Read physical memory.
5224	*
5225	* @returns VINF_SUCCESS (for now).
5226	* @param pDevIns Device instance.
5227	* @param GCPhys Physical address start reading from.
5228	* @param pvBuf Where to put the read bits.
5229	* @param cbRead How many bytes to read.
5230	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5231	*/
5232	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5233
5234	/**
5235	* Write to physical memory.
5236	*
5237	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5238	* @param pDevIns Device instance.
5239	* @param GCPhys Physical address to write to.
5240	* @param pvBuf What to write.
5241	* @param cbWrite How many bytes to write.
5242	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5243	*/
5244	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5245
5246	/**
5247	* Checks if the Gate A20 is enabled or not.
5248	*
5249	* @returns true if A20 is enabled.
5250	* @returns false if A20 is disabled.
5251	* @param pDevIns Device instance.
5252	* @thread The emulation thread.
5253	*/
5254	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5255
5256	/**
5257	* Gets the VM state.
5258	*
5259	* @returns VM state.
5260	* @param pDevIns The device instance.
5261	* @thread Any thread (just keep in mind that it's volatile info).
5262	*/
5263	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5264
5265	/**
5266	* Gets the VM handle. Restricted API.
5267	*
5268	* @returns VM Handle.
5269	* @param pDevIns Device instance.
5270	*/
5271	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5272
5273	/**
5274	* Gets the VMCPU handle. Restricted API.
5275	*
5276	* @returns VMCPU Handle.
5277	* @param pDevIns The device instance.
5278	*/
5279	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5280
5281	/**
5282	* The the VM CPU ID of the current thread (restricted API).
5283	*
5284	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5285	* @param pDevIns The device instance.
5286	*/
5287	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5288
5289	/**
5290	* Gets the main execution engine for the VM.
5291	*
5292	* @returns VM_EXEC_ENGINE_XXX
5293	* @param pDevIns The device instance.
5294	*/
5295	DECLRCCALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
5296
5297	/**
5298	* Get the current virtual clock time in a VM. The clock frequency must be
5299	* queried separately.
5300	*
5301	* @returns Current clock time.
5302	* @param pDevIns The device instance.
5303	*/
5304	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5305
5306	/**
5307	* Get the frequency of the virtual clock.
5308	*
5309	* @returns The clock frequency (not variable at run-time).
5310	* @param pDevIns The device instance.
5311	*/
5312	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5313
5314	/**
5315	* Get the current virtual clock time in a VM, in nanoseconds.
5316	*
5317	* @returns Current clock time (in ns).
5318	* @param pDevIns The device instance.
5319	*/
5320	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5321
5322	/**
5323	* Gets the NOP critical section.
5324	*
5325	* @returns The ring-3 address of the NOP critical section.
5326	* @param pDevIns The device instance.
5327	*/
5328	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5329
5330	/**
5331	* Changes the device level critical section from the automatically created
5332	* default to one desired by the device constructor.
5333	*
5334	* Must first be done in ring-3.
5335	*
5336	* @returns VBox status code.
5337	* @param pDevIns The device instance.
5338	* @param pCritSect The critical section to use. NULL is not
5339	* valid, instead use the NOP critical
5340	* section.
5341	*/
5342	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5343
5344	/** @name Exported PDM Critical Section Functions
5345	* @{ */
5346	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5347	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5348	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5349	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5350	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5351	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5352	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5353	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5354	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5355	/** @} */
5356
5357	/** @name Exported PDM Read/Write Critical Section Functions
5358	* @{ */
5359	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5360	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5361	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5362	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5363	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5364
5365	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5366	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5367	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5368	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5369	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5370
5371	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5372	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5373	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5374	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5375	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5376	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5377	/** @} */
5378
5379	/**
5380	* Gets the trace buffer handle.
5381	*
5382	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5383	* really inteded for direct usage, thus no inline wrapper function.
5384	*
5385	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5386	* @param pDevIns The device instance.
5387	*/
5388	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5389
5390	/**
5391	* Sets up the PCI bus for the raw-mode context.
5392	*
5393	* This must be called after ring-3 has registered the PCI bus using
5394	* PDMDevHlpPCIBusRegister().
5395	*
5396	* @returns VBox status code.
5397	* @param pDevIns The device instance.
5398	* @param pPciBusReg The PCI bus registration information for raw-mode,
5399	* considered volatile.
5400	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
5401	*/
5402	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
5403
5404	/**
5405	* Sets up the IOMMU for the raw-mode context.
5406	*
5407	* This must be called after ring-3 has registered the IOMMU using
5408	* PDMDevHlpIommuRegister().
5409	*
5410	* @returns VBox status code.
5411	* @param pDevIns The device instance.
5412	* @param pIommuReg The IOMMU registration information for raw-mode,
5413	* considered volatile.
5414	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
5415	*/
5416	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
5417
5418	/**
5419	* Sets up the PIC for the ring-0 context.
5420	*
5421	* This must be called after ring-3 has registered the PIC using
5422	* PDMDevHlpPICRegister().
5423	*
5424	* @returns VBox status code.
5425	* @param pDevIns The device instance.
5426	* @param pPicReg The PIC registration information for ring-0,
5427	* considered volatile and copied.
5428	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5429	*/
5430	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5431
5432	/**
5433	* Sets up the APIC for the raw-mode context.
5434	*
5435	* This must be called after ring-3 has registered the APIC using
5436	* PDMDevHlpApicRegister().
5437	*
5438	* @returns VBox status code.
5439	* @param pDevIns The device instance.
5440	*/
5441	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5442
5443	/**
5444	* Sets up the IOAPIC for the ring-0 context.
5445	*
5446	* This must be called after ring-3 has registered the PIC using
5447	* PDMDevHlpIoApicRegister().
5448	*
5449	* @returns VBox status code.
5450	* @param pDevIns The device instance.
5451	* @param pIoApicReg The PIC registration information for ring-0,
5452	* considered volatile and copied.
5453	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5454	*/
5455	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5456
5457	/**
5458	* Sets up the HPET for the raw-mode context.
5459	*
5460	* This must be called after ring-3 has registered the PIC using
5461	* PDMDevHlpHpetRegister().
5462	*
5463	* @returns VBox status code.
5464	* @param pDevIns The device instance.
5465	* @param pHpetReg The PIC registration information for raw-mode,
5466	* considered volatile and copied.
5467	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
5468	*/
5469	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
5470
5471	/** Space reserved for future members.
5472	* @{ */
5473	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
5474	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
5475	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
5476	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
5477	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
5478	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
5479	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
5480	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
5481	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
5482	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
5483	/** @} */
5484
5485	/** Just a safety precaution. */
5486	uint32_t u32TheEnd;
5487	} PDMDEVHLPRC;
5488	/** Pointer PDM Device RC API. */
5489	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
5490	/** Pointer PDM Device RC API. */
5491	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
5492
5493	/** Current PDMDEVHLP version number. */
5494	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 19, 0)
5495
5496
5497	/**
5498	* PDM Device API - R0 Variant.
5499	*/
5500	typedef struct PDMDEVHLPR0
5501	{
5502	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5503	uint32_t u32Version;
5504
5505	/**
5506	* Sets up ring-0 callback handlers for an I/O port range.
5507	*
5508	* The range must have been created in ring-3 first using
5509	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5510	*
5511	* @returns VBox status.
5512	* @param pDevIns The device instance to register the ports with.
5513	* @param hIoPorts The I/O port range handle.
5514	* @param pfnOut Pointer to function which is gonna handle OUT
5515	* operations. Optional.
5516	* @param pfnIn Pointer to function which is gonna handle IN operations.
5517	* Optional.
5518	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5519	* operations. Optional.
5520	* @param pfnInStr Pointer to function which is gonna handle string IN
5521	* operations. Optional.
5522	* @param pvUser User argument to pass to the callbacks.
5523	*
5524	* @remarks Caller enters the device critical section prior to invoking the
5525	* registered callback methods.
5526	*
5527	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5528	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5529	*/
5530	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5531	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5532	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5533	void *pvUser));
5534
5535	/**
5536	* Sets up ring-0 callback handlers for an MMIO region.
5537	*
5538	* The region must have been created in ring-3 first using
5539	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5540	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5541	*
5542	* @returns VBox status.
5543	* @param pDevIns The device instance to register the ports with.
5544	* @param hRegion The MMIO region handle.
5545	* @param pfnWrite Pointer to function which is gonna handle Write
5546	* operations.
5547	* @param pfnRead Pointer to function which is gonna handle Read
5548	* operations.
5549	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5550	* operations. (optional)
5551	* @param pvUser User argument to pass to the callbacks.
5552	*
5553	* @remarks Caller enters the device critical section prior to invoking the
5554	* registered callback methods.
5555	*
5556	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5557	* PDMDevHlpMmioUnmap().
5558	*/
5559	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5560	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5561
5562	/**
5563	* Sets up a ring-0 mapping for an MMIO2 region.
5564	*
5565	* The region must have been created in ring-3 first using
5566	* PDMDevHlpMmio2Create().
5567	*
5568	* @returns VBox status.
5569	* @param pDevIns The device instance to register the ports with.
5570	* @param hRegion The MMIO2 region handle.
5571	* @param offSub Start of what to map into ring-0. Must be page aligned.
5572	* @param cbSub Number of bytes to map into ring-0. Must be page
5573	* aligned. Zero is an alias for everything.
5574	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5575	*
5576	* @thread EMT(0)
5577	* @note Only available at VM creation time.
5578	*
5579	* @sa PDMDevHlpMmio2Create().
5580	*/
5581	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5582	void **ppvMapping));
5583
5584	/**
5585	* Bus master physical memory read from the given PCI device.
5586	*
5587	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5588	* VERR_EM_MEMORY.
5589	* @param pDevIns The device instance.
5590	* @param pPciDev The PCI device structure. If NULL the default
5591	* PCI device for this device instance is used.
5592	* @param GCPhys Physical address start reading from.
5593	* @param pvBuf Where to put the read bits.
5594	* @param cbRead How many bytes to read.
5595	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5596	* @thread Any thread, but the call may involve the emulation thread.
5597	*/
5598	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5599	void *pvBuf, size_t cbRead, uint32_t fFlags));
5600
5601	/**
5602	* Bus master physical memory write from the given PCI device.
5603	*
5604	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5605	* VERR_EM_MEMORY.
5606	* @param pDevIns The device instance.
5607	* @param pPciDev The PCI device structure. If NULL the default
5608	* PCI device for this device instance is used.
5609	* @param GCPhys Physical address to write to.
5610	* @param pvBuf What to write.
5611	* @param cbWrite How many bytes to write.
5612	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5613	* @thread Any thread, but the call may involve the emulation thread.
5614	*/
5615	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5616	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5617
5618	/**
5619	* Set the IRQ for the given PCI device.
5620	*
5621	* @param pDevIns Device instance.
5622	* @param pPciDev The PCI device structure. If NULL the default
5623	* PCI device for this device instance is used.
5624	* @param iIrq IRQ number to set.
5625	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5626	* @thread Any thread, but will involve the emulation thread.
5627	*/
5628	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5629
5630	/**
5631	* Set ISA IRQ for a device.
5632	*
5633	* @param pDevIns Device instance.
5634	* @param iIrq IRQ number to set.
5635	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5636	* @thread Any thread, but will involve the emulation thread.
5637	*/
5638	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5639
5640	/**
5641	* Read physical memory.
5642	*
5643	* @returns VINF_SUCCESS (for now).
5644	* @param pDevIns Device instance.
5645	* @param GCPhys Physical address start reading from.
5646	* @param pvBuf Where to put the read bits.
5647	* @param cbRead How many bytes to read.
5648	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5649	*/
5650	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5651
5652	/**
5653	* Write to physical memory.
5654	*
5655	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5656	* @param pDevIns Device instance.
5657	* @param GCPhys Physical address to write to.
5658	* @param pvBuf What to write.
5659	* @param cbWrite How many bytes to write.
5660	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5661	*/
5662	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5663
5664	/**
5665	* Checks if the Gate A20 is enabled or not.
5666	*
5667	* @returns true if A20 is enabled.
5668	* @returns false if A20 is disabled.
5669	* @param pDevIns Device instance.
5670	* @thread The emulation thread.
5671	*/
5672	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5673
5674	/**
5675	* Gets the VM state.
5676	*
5677	* @returns VM state.
5678	* @param pDevIns The device instance.
5679	* @thread Any thread (just keep in mind that it's volatile info).
5680	*/
5681	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5682
5683	/**
5684	* Gets the VM handle. Restricted API.
5685	*
5686	* @returns VM Handle.
5687	* @param pDevIns Device instance.
5688	*/
5689	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5690
5691	/**
5692	* Gets the VMCPU handle. Restricted API.
5693	*
5694	* @returns VMCPU Handle.
5695	* @param pDevIns The device instance.
5696	*/
5697	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5698
5699	/**
5700	* The the VM CPU ID of the current thread (restricted API).
5701	*
5702	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5703	* @param pDevIns The device instance.
5704	*/
5705	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5706
5707	/**
5708	* Gets the main execution engine for the VM.
5709	*
5710	* @returns VM_EXEC_ENGINE_XXX
5711	* @param pDevIns The device instance.
5712	*/
5713	DECLR0CALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
5714
5715	/** @name Timer handle method wrappers
5716	* @{ */
5717	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5718	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5719	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5720	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5721	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5722	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5723	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5724	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5725	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5726	/** Takes the clock lock then enters the specified critical section. */
5727	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5728	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5729	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5730	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5731	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5732	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5733	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5734	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5735	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5736	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5737	/** @} */
5738
5739	/**
5740	* Get the current virtual clock time in a VM. The clock frequency must be
5741	* queried separately.
5742	*
5743	* @returns Current clock time.
5744	* @param pDevIns The device instance.
5745	*/
5746	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5747
5748	/**
5749	* Get the frequency of the virtual clock.
5750	*
5751	* @returns The clock frequency (not variable at run-time).
5752	* @param pDevIns The device instance.
5753	*/
5754	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5755
5756	/**
5757	* Get the current virtual clock time in a VM, in nanoseconds.
5758	*
5759	* @returns Current clock time (in ns).
5760	* @param pDevIns The device instance.
5761	*/
5762	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5763
5764	/** @name Exported PDM Queue Functions
5765	* @{ */
5766	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5767	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5768	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5769	/** @} */
5770
5771	/** @name PDM Task
5772	* @{ */
5773	/**
5774	* Triggers the running the given task.
5775	*
5776	* @returns VBox status code.
5777	* @retval VINF_ALREADY_POSTED is the task is already pending.
5778	* @param pDevIns The device instance.
5779	* @param hTask The task to trigger.
5780	* @thread Any thread.
5781	*/
5782	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5783	/** @} */
5784
5785	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5786	* These semaphores can be signalled from ring-0.
5787	* @{ */
5788	/** @sa SUPSemEventSignal */
5789	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5790	/** @sa SUPSemEventWaitNoResume */
5791	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5792	/** @sa SUPSemEventWaitNsAbsIntr */
5793	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5794	/** @sa SUPSemEventWaitNsRelIntr */
5795	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5796	/** @sa SUPSemEventGetResolution */
5797	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5798	/** @} */
5799
5800	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5801	* These semaphores can be signalled from ring-0.
5802	* @{ */
5803	/** @sa SUPSemEventMultiSignal */
5804	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5805	/** @sa SUPSemEventMultiReset */
5806	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5807	/** @sa SUPSemEventMultiWaitNoResume */
5808	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5809	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5810	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5811	/** @sa SUPSemEventMultiWaitNsRelIntr */
5812	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5813	/** @sa SUPSemEventMultiGetResolution */
5814	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5815	/** @} */
5816
5817	/**
5818	* Gets the NOP critical section.
5819	*
5820	* @returns The ring-3 address of the NOP critical section.
5821	* @param pDevIns The device instance.
5822	*/
5823	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5824
5825	/**
5826	* Changes the device level critical section from the automatically created
5827	* default to one desired by the device constructor.
5828	*
5829	* Must first be done in ring-3.
5830	*
5831	* @returns VBox status code.
5832	* @param pDevIns The device instance.
5833	* @param pCritSect The critical section to use. NULL is not
5834	* valid, instead use the NOP critical
5835	* section.
5836	*/
5837	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5838
5839	/** @name Exported PDM Critical Section Functions
5840	* @{ */
5841	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5842	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5843	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5844	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5845	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5846	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5847	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5848	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5849	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5850	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5851	/** @} */
5852
5853	/** @name Exported PDM Read/Write Critical Section Functions
5854	* @{ */
5855	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5856	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5857	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5858	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5859	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5860
5861	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5862	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5863	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5864	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5865	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5866
5867	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5868	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5869	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5870	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5871	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5872	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5873	/** @} */
5874
5875	/**
5876	* Gets the trace buffer handle.
5877	*
5878	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5879	* really inteded for direct usage, thus no inline wrapper function.
5880	*
5881	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5882	* @param pDevIns The device instance.
5883	*/
5884	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5885
5886	/**
5887	* Sets up the PCI bus for the ring-0 context.
5888	*
5889	* This must be called after ring-3 has registered the PCI bus using
5890	* PDMDevHlpPCIBusRegister().
5891	*
5892	* @returns VBox status code.
5893	* @param pDevIns The device instance.
5894	* @param pPciBusReg The PCI bus registration information for ring-0,
5895	* considered volatile and copied.
5896	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5897	*/
5898	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5899
5900	/**
5901	* Sets up the IOMMU for the ring-0 context.
5902	*
5903	* This must be called after ring-3 has registered the IOMMU using
5904	* PDMDevHlpIommuRegister().
5905	*
5906	* @returns VBox status code.
5907	* @param pDevIns The device instance.
5908	* @param pIommuReg The IOMMU registration information for ring-0,
5909	* considered volatile and copied.
5910	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5911	*/
5912	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5913
5914	/**
5915	* Sets up the PIC for the ring-0 context.
5916	*
5917	* This must be called after ring-3 has registered the PIC using
5918	* PDMDevHlpPICRegister().
5919	*
5920	* @returns VBox status code.
5921	* @param pDevIns The device instance.
5922	* @param pPicReg The PIC registration information for ring-0,
5923	* considered volatile and copied.
5924	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5925	*/
5926	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5927
5928	/**
5929	* Sets up the APIC for the ring-0 context.
5930	*
5931	* This must be called after ring-3 has registered the APIC using
5932	* PDMDevHlpApicRegister().
5933	*
5934	* @returns VBox status code.
5935	* @param pDevIns The device instance.
5936	*/
5937	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5938
5939	/**
5940	* Sets up the IOAPIC for the ring-0 context.
5941	*
5942	* This must be called after ring-3 has registered the PIC using
5943	* PDMDevHlpIoApicRegister().
5944	*
5945	* @returns VBox status code.
5946	* @param pDevIns The device instance.
5947	* @param pIoApicReg The PIC registration information for ring-0,
5948	* considered volatile and copied.
5949	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5950	*/
5951	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5952
5953	/**
5954	* Sets up the HPET for the ring-0 context.
5955	*
5956	* This must be called after ring-3 has registered the PIC using
5957	* PDMDevHlpHpetRegister().
5958	*
5959	* @returns VBox status code.
5960	* @param pDevIns The device instance.
5961	* @param pHpetReg The PIC registration information for ring-0,
5962	* considered volatile and copied.
5963	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5964	*/
5965	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5966
5967	/**
5968	* Temporarily turns off the access monitoring of a page within a monitored
5969	* physical write/all page access handler region.
5970	*
5971	* Use this when no further \#PFs are required for that page. Be aware that
5972	* a page directory sync might reset the flags, and turn on access monitoring
5973	* for the page.
5974	*
5975	* The caller must do required page table modifications.
5976	*
5977	* @returns VBox status code.
5978	* @param pDevIns The device instance.
5979	* @param GCPhys The start address of the access handler. This
5980	* must be a fully page aligned range or we risk
5981	* messing up other handlers installed for the
5982	* start and end pages.
5983	* @param GCPhysPage The physical address of the page to turn off
5984	* access monitoring for.
5985	*/
5986	DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
5987
5988	/**
5989	* Mapping an MMIO2 page in place of an MMIO page for direct access.
5990	*
5991	* This is a special optimization used by the VGA device. Call
5992	* PDMDevHlpMmioResetRegion() to undo the mapping.
5993	*
5994	* @returns VBox status code. This API may return VINF_SUCCESS even if no
5995	* remapping is made.
5996	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
5997	*
5998	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
5999	* associated with.
6000	* @param hRegion The handle to the MMIO region.
6001	* @param offRegion The offset into @a hRegion of the page to be
6002	* remapped.
6003	* @param hMmio2 The MMIO2 handle.
6004	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
6005	* mapping.
6006	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
6007	* for the time being.
6008	*/
6009	DECLR0CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6010	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
6011
6012	/**
6013	* Reset a previously modified MMIO region; restore the access flags.
6014	*
6015	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
6016	* intended for some ancient VGA hack. However, it would be great to extend it
6017	* beyond VT-x and/or nested-paging.
6018	*
6019	* @returns VBox status code.
6020	*
6021	* @param pDevIns The device instance @a hRegion is associated with.
6022	* @param hRegion The handle to the MMIO region.
6023	*/
6024	DECLR0CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
6025
6026	/**
6027	* Returns the array of MMIO2 regions that are expected to be registered and
6028	* later mapped into the guest-physical address space for the GIM provider
6029	* configured for the VM.
6030	*
6031	* @returns Pointer to an array of GIM MMIO2 regions, may return NULL.
6032	* @param pDevIns Pointer to the GIM device instance.
6033	* @param pcRegions Where to store the number of items in the array.
6034	*
6035	* @remarks The caller does not own and therefore must -NOT- try to free the
6036	* returned pointer.
6037	*/
6038	DECLR0CALLBACKMEMBER(PGIMMMIO2REGION, pfnGIMGetMmio2Regions,(PPDMDEVINS pDevIns, uint32_t *pcRegions));
6039
6040	/** Space reserved for future members.
6041	* @{ */
6042	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
6043	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
6044	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
6045	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
6046	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
6047	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
6048	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
6049	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
6050	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
6051	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
6052	/** @} */
6053
6054	/** Just a safety precaution. */
6055	uint32_t u32TheEnd;
6056	} PDMDEVHLPR0;
6057	/** Pointer PDM Device R0 API. */
6058	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
6059	/** Pointer PDM Device GC API. */
6060	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
6061
6062	/** Current PDMDEVHLP version number. */
6063	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 26, 0)
6064
6065
6066	/**
6067	* PDM Device Instance.
6068	*/
6069	typedef struct PDMDEVINSR3
6070	{
6071	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
6072	uint32_t u32Version;
6073	/** Device instance number. */
6074	uint32_t iInstance;
6075	/** Size of the ring-3, raw-mode and shared bits. */
6076	uint32_t cbRing3;
6077	/** Set if ring-0 context is enabled. */
6078	bool fR0Enabled;
6079	/** Set if raw-mode context is enabled. */
6080	bool fRCEnabled;
6081	/** Alignment padding. */
6082	bool afReserved[2];
6083	/** Pointer the HC PDM Device API. */
6084	PCPDMDEVHLPR3 pHlpR3;
6085	/** Pointer to the shared device instance data. */
6086	RTR3PTR pvInstanceDataR3;
6087	/** Pointer to the device instance data for ring-3. */
6088	RTR3PTR pvInstanceDataForR3;
6089	/** The critical section for the device.
6090	*
6091	* TM and IOM will enter this critical section before calling into the device
6092	* code. PDM will when doing power on, power off, reset, suspend and resume
6093	* notifications. SSM will currently not, but this will be changed later on.
6094	*
6095	* The device gets a critical section automatically assigned to it before
6096	* the constructor is called. If the constructor wishes to use a different
6097	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6098	* very early on.
6099	*/
6100	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
6101	/** Pointer to device registration structure. */
6102	R3PTRTYPE(PCPDMDEVREG) pReg;
6103	/** Configuration handle. */
6104	R3PTRTYPE(PCFGMNODE) pCfg;
6105	/** The base interface of the device.
6106	*
6107	* The device constructor initializes this if it has any
6108	* device level interfaces to export. To obtain this interface
6109	* call PDMR3QueryDevice(). */
6110	PDMIBASE IBase;
6111
6112	/** Tracing indicator. */
6113	uint32_t fTracing;
6114	/** The tracing ID of this device. */
6115	uint32_t idTracing;
6116
6117	/** Ring-3 pointer to the raw-mode device instance. */
6118	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
6119	/** Raw-mode address of the raw-mode device instance. */
6120	RTRGPTR pDevInsForRC;
6121	/** Ring-3 pointer to the raw-mode instance data. */
6122	RTR3PTR pvInstanceDataForRCR3;
6123
6124	/** PCI device structure size. */
6125	uint32_t cbPciDev;
6126	/** Number of PCI devices in apPciDevs. */
6127	uint32_t cPciDevs;
6128	/** Pointer to the PCI devices for this device.
6129	* (Allocated after the shared instance data.)
6130	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6131	* two devices ever needing it can use cbPciDev and do the address
6132	* calculations that for entries 8+. */
6133	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6134
6135	/** Temporarily. */
6136	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
6137	/** Temporarily. */
6138	RTR0PTR pvInstanceDataR0;
6139	/** Temporarily. */
6140	RTRCPTR pvInstanceDataRC;
6141	/** Align the internal data more naturally. */
6142	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
6143
6144	/** Internal data. */
6145	union
6146	{
6147	#ifdef PDMDEVINSINT_DECLARED
6148	PDMDEVINSINTR3 s;
6149	#endif
6150	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
6151	} Internal;
6152
6153	/** Device instance data for ring-3. The size of this area is defined
6154	* in the PDMDEVREG::cbInstanceR3 field. */
6155	char achInstanceData[8];
6156	} PDMDEVINSR3;
6157
6158	/** Current PDMDEVINSR3 version number. */
6159	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
6160
6161	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
6162	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
6163
6164
6165	/**
6166	* PDM ring-0 device instance.
6167	*/
6168	typedef struct PDMDEVINSR0
6169	{
6170	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
6171	uint32_t u32Version;
6172	/** Device instance number. */
6173	uint32_t iInstance;
6174
6175	/** Pointer the HC PDM Device API. */
6176	PCPDMDEVHLPR0 pHlpR0;
6177	/** Pointer to the shared device instance data. */
6178	RTR0PTR pvInstanceDataR0;
6179	/** Pointer to the device instance data for ring-0. */
6180	RTR0PTR pvInstanceDataForR0;
6181	/** The critical section for the device.
6182	*
6183	* TM and IOM will enter this critical section before calling into the device
6184	* code. PDM will when doing power on, power off, reset, suspend and resume
6185	* notifications. SSM will currently not, but this will be changed later on.
6186	*
6187	* The device gets a critical section automatically assigned to it before
6188	* the constructor is called. If the constructor wishes to use a different
6189	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6190	* very early on.
6191	*/
6192	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
6193	/** Pointer to the ring-0 device registration structure. */
6194	R0PTRTYPE(PCPDMDEVREGR0) pReg;
6195	/** Ring-3 address of the ring-3 device instance. */
6196	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
6197	/** Ring-0 pointer to the ring-3 device instance. */
6198	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
6199	/** Ring-0 pointer to the ring-3 instance data. */
6200	RTR0PTR pvInstanceDataForR3R0;
6201	/** Raw-mode address of the raw-mode device instance. */
6202	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
6203	/** Ring-0 pointer to the raw-mode device instance. */
6204	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
6205	/** Ring-0 pointer to the raw-mode instance data. */
6206	RTR0PTR pvInstanceDataForRCR0;
6207
6208	/** PCI device structure size. */
6209	uint32_t cbPciDev;
6210	/** Number of PCI devices in apPciDevs. */
6211	uint32_t cPciDevs;
6212	/** Pointer to the PCI devices for this device.
6213	* (Allocated after the shared instance data.)
6214	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6215	* two devices ever needing it can use cbPciDev and do the address
6216	* calculations that for entries 8+. */
6217	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6218
6219	/** Align the internal data more naturally. */
6220	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
6221
6222	/** Internal data. */
6223	union
6224	{
6225	#ifdef PDMDEVINSINT_DECLARED
6226	PDMDEVINSINTR0 s;
6227	#endif
6228	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
6229	} Internal;
6230
6231	/** Device instance data for ring-0. The size of this area is defined
6232	* in the PDMDEVREG::cbInstanceR0 field. */
6233	char achInstanceData[8];
6234	} PDMDEVINSR0;
6235
6236	/** Current PDMDEVINSR0 version number. */
6237	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
6238
6239
6240	/**
6241	* PDM raw-mode device instance.
6242	*/
6243	typedef struct PDMDEVINSRC
6244	{
6245	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
6246	uint32_t u32Version;
6247	/** Device instance number. */
6248	uint32_t iInstance;
6249
6250	/** Pointer the HC PDM Device API. */
6251	PCPDMDEVHLPRC pHlpRC;
6252	/** Pointer to the shared device instance data. */
6253	RTRGPTR pvInstanceDataRC;
6254	/** Pointer to the device instance data for raw-mode. */
6255	RTRGPTR pvInstanceDataForRC;
6256	/** The critical section for the device.
6257	*
6258	* TM and IOM will enter this critical section before calling into the device
6259	* code. PDM will when doing power on, power off, reset, suspend and resume
6260	* notifications. SSM will currently not, but this will be changed later on.
6261	*
6262	* The device gets a critical section automatically assigned to it before
6263	* the constructor is called. If the constructor wishes to use a different
6264	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6265	* very early on.
6266	*/
6267	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
6268	/** Pointer to the raw-mode device registration structure. */
6269	RGPTRTYPE(PCPDMDEVREGRC) pReg;
6270
6271	/** PCI device structure size. */
6272	uint32_t cbPciDev;
6273	/** Number of PCI devices in apPciDevs. */
6274	uint32_t cPciDevs;
6275	/** Pointer to the PCI devices for this device.
6276	* (Allocated after the shared instance data.) */
6277	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6278
6279	/** Align the internal data more naturally. */
6280	uint32_t au32Padding[14];
6281
6282	/** Internal data. */
6283	union
6284	{
6285	#ifdef PDMDEVINSINT_DECLARED
6286	PDMDEVINSINTRC s;
6287	#endif
6288	uint8_t padding[0x10];
6289	} Internal;
6290
6291	/** Device instance data for ring-0. The size of this area is defined
6292	* in the PDMDEVREG::cbInstanceR0 field. */
6293	char achInstanceData[8];
6294	} PDMDEVINSRC;
6295
6296	/** Current PDMDEVINSR0 version number. */
6297	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
6298
6299
6300	/** @def PDM_DEVINS_VERSION
6301	* Current PDMDEVINS version number. */
6302	/** @typedef PDMDEVINS
6303	* The device instance structure for the current context. */
6304	#ifdef IN_RING3
6305	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
6306	typedef PDMDEVINSR3 PDMDEVINS;
6307	#elif defined(IN_RING0)
6308	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
6309	typedef PDMDEVINSR0 PDMDEVINS;
6310	#elif defined(IN_RC)
6311	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
6312	typedef PDMDEVINSRC PDMDEVINS;
6313	#else
6314	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
6315	#endif
6316
6317	/**
6318	* Get the pointer to an PCI device.
6319	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6320	*/
6321	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
6322	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
6323	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
6324
6325	/**
6326	* Calc the pointer to of a given PCI device.
6327	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6328	*/
6329	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
6330	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
6331	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
6332	: (PPDMPCIDEV)NULL )
6333
6334
6335	/**
6336	* Checks the structure versions of the device instance and device helpers,
6337	* returning if they are incompatible.
6338	*
6339	* This is for use in the constructor.
6340	*
6341	* @param pDevIns The device instance pointer.
6342	*/
6343	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
6344	do \
6345	{ \
6346	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6347	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6348	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6349	VERR_PDM_DEVINS_VERSION_MISMATCH); \
6350	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6351	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6352	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
6353	} while (0)
6354
6355	/**
6356	* Quietly checks the structure versions of the device instance and device
6357	* helpers, returning if they are incompatible.
6358	*
6359	* This is for use in the destructor.
6360	*
6361	* @param pDevIns The device instance pointer.
6362	*/
6363	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
6364	do \
6365	{ \
6366	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6367	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
6368	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
6369	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
6370	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
6371	} while (0)
6372
6373	/**
6374	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
6375	* constructor - returns on failure.
6376	*
6377	* This should be invoked after having initialized the instance data
6378	* sufficiently for the correct operation of the destructor. The destructor is
6379	* always called!
6380	*
6381	* @param pDevIns Pointer to the PDM device instance.
6382	* @param pszValidValues Patterns describing the valid value names. See
6383	* RTStrSimplePatternMultiMatch for details on the
6384	* pattern syntax.
6385	* @param pszValidNodes Patterns describing the valid node (key) names.
6386	* Pass empty string if no valid nodes.
6387	*/
6388	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
6389	do \
6390	{ \
6391	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
6392	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
6393	if (RT_SUCCESS(rcValCfg)) \
6394	{ /* likely */ } else return rcValCfg; \
6395	} while (0)
6396
6397	/** @def PDMDEV_ASSERT_EMT
6398	* Assert that the current thread is the emulation thread.
6399	*/
6400	#ifdef VBOX_STRICT
6401	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6402	#else
6403	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
6404	#endif
6405
6406	/** @def PDMDEV_ASSERT_OTHER
6407	* Assert that the current thread is NOT the emulation thread.
6408	*/
6409	#ifdef VBOX_STRICT
6410	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6411	#else
6412	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
6413	#endif
6414
6415	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
6416	* Assert that the current thread is owner of the VM lock.
6417	*/
6418	#ifdef VBOX_STRICT
6419	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6420	#else
6421	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
6422	#endif
6423
6424	/** @def PDMDEV_SET_ERROR
6425	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
6426	*/
6427	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
6428	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
6429
6430	/** @def PDMDEV_SET_RUNTIME_ERROR
6431	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
6432	*/
6433	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
6434	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
6435
6436	/** @def PDMDEVINS_2_RCPTR
6437	* Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
6438	*/
6439	#ifdef IN_RC
6440	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
6441	#else
6442	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
6443	#endif
6444
6445	/** @def PDMDEVINS_2_R3PTR
6446	* Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
6447	*/
6448	#ifdef IN_RING3
6449	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
6450	#else
6451	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
6452	#endif
6453
6454	/** @def PDMDEVINS_2_R0PTR
6455	* Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
6456	*/
6457	#ifdef IN_RING0
6458	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
6459	#else
6460	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
6461	#endif
6462
6463	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
6464	* Converts a PDM device instance data pointer to a ring-0 one.
6465	* @deprecated
6466	*/
6467	#ifdef IN_RING0
6468	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
6469	#else
6470	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
6471	#endif
6472
6473
6474	/** @def PDMDEVINS_2_DATA
6475	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
6476	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
6477	*
6478	* @note Do no use this macro in common code working on a core structure which
6479	* device specific code has expanded.
6480	*/
6481	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6482	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
6483	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6484	{ \
6485	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
6486	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
6487	return pLambdaRet; \
6488	}(a_pDevIns))
6489	#else
6490	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
6491	#endif
6492
6493	/** @def PDMDEVINS_2_DATA_CC
6494	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
6495	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
6496	*
6497	* @note Do no use this macro in common code working on a core structure which
6498	* device specific code has expanded.
6499	*/
6500	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6501	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
6502	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6503	{ \
6504	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
6505	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
6506	return pLambdaRet; \
6507	}(a_pDevIns))
6508	#else
6509	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
6510	#endif
6511
6512
6513	#ifdef IN_RING3
6514
6515	/**
6516	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
6517	*/
6518	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6519	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
6520	PIOMIOPORTHANDLE phIoPorts)
6521	{
6522	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6523	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6524	if (RT_SUCCESS(rc))
6525	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6526	return rc;
6527	}
6528
6529	/**
6530	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
6531	*/
6532	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6533	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6534	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6535	{
6536	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6537	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6538	if (RT_SUCCESS(rc))
6539	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6540	return rc;
6541	}
6542
6543	/**
6544	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
6545	*/
6546	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6547	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6548	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6549	{
6550	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6551	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6552	if (RT_SUCCESS(rc))
6553	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6554	return rc;
6555	}
6556
6557	/**
6558	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
6559	*/
6560	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6561	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6562	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6563	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6564	{
6565	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6566	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6567	if (RT_SUCCESS(rc))
6568	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6569	return rc;
6570	}
6571
6572	/**
6573	* @sa PDMDevHlpIoPortCreateEx
6574	*/
6575	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6576	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6577	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6578	{
6579	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
6580	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6581	}
6582
6583
6584	/**
6585	* @sa PDMDevHlpIoPortCreateEx
6586	*/
6587	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6588	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6589	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6590	{
6591	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6592	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6593	}
6594
6595	/**
6596	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6597	*/
6598	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6599	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6600	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6601	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6602	{
6603	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6604	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6605	}
6606
6607	/**
6608	* @copydoc PDMDEVHLPR3::pfnIoPortMap
6609	*/
6610	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6611	{
6612	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6613	}
6614
6615	/**
6616	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6617	*/
6618	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6619	{
6620	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6621	}
6622
6623	/**
6624	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6625	*/
6626	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6627	{
6628	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6629	}
6630
6631
6632	#endif /* IN_RING3 */
6633	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6634
6635	/**
6636	* @sa PDMDevHlpIoPortSetUpContextEx
6637	*/
6638	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6639	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6640	{
6641	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6642	}
6643
6644	/**
6645	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6646	*/
6647	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6648	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6649	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6650	{
6651	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6652	}
6653
6654	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6655	#ifdef IN_RING3
6656
6657	/**
6658	* @sa PDMDevHlpMmioCreateEx
6659	*/
6660	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6661	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6662	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6663	{
6664	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6665	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6666	}
6667
6668	/**
6669	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6670	*/
6671	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6672	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6673	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6674	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6675	{
6676	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6677	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6678	}
6679
6680	/**
6681	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6682	*/
6683	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6684	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6685	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6686	{
6687	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6688	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6689	if (RT_SUCCESS(rc))
6690	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6691	return rc;
6692	}
6693
6694	/**
6695	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6696	*/
6697	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6698	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6699	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6700	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6701	{
6702	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6703	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6704	if (RT_SUCCESS(rc))
6705	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6706	return rc;
6707	}
6708
6709	/**
6710	* @copydoc PDMDEVHLPR3::pfnMmioMap
6711	*/
6712	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6713	{
6714	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6715	}
6716
6717	/**
6718	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6719	*/
6720	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6721	{
6722	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6723	}
6724
6725	/**
6726	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6727	*/
6728	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6729	{
6730	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6731	}
6732
6733	/**
6734	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6735	*/
6736	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6737	{
6738	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6739	}
6740
6741	#endif /* IN_RING3 */
6742	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6743
6744	/**
6745	* @sa PDMDevHlpMmioSetUpContextEx
6746	*/
6747	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6748	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6749	{
6750	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6751	}
6752
6753	/**
6754	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6755	*/
6756	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6757	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6758	{
6759	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6760	}
6761
6762	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6763	#ifdef IN_RING3
6764
6765	/**
6766	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6767	*/
6768	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6769	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6770	{
6771	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6772	}
6773
6774	/**
6775	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6776	*/
6777	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6778	{
6779	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6780	}
6781
6782	/**
6783	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6784	*/
6785	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6786	{
6787	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6788	}
6789
6790	/**
6791	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6792	*/
6793	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6794	{
6795	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6796	}
6797
6798	/**
6799	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6800	*/
6801	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6802	{
6803	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6804	}
6805
6806	/**
6807	* @copydoc PDMDEVHLPR3::pfnMmio2QueryAndResetDirtyBitmap
6808	*/
6809	DECLINLINE(int) PDMDevHlpMmio2QueryAndResetDirtyBitmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6810	void *pvBitmap, size_t cbBitmap)
6811	{
6812	return pDevIns->pHlpR3->pfnMmio2QueryAndResetDirtyBitmap(pDevIns, hRegion, pvBitmap, cbBitmap);
6813	}
6814
6815	/**
6816	* Reset the dirty bitmap tracking for an MMIO2 region.
6817	*
6818	* The MMIO2 region must have been created with the
6819	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
6820	*
6821	* @returns VBox status code.
6822	* @param pDevIns The device instance.
6823	* @param hRegion The MMIO2 region handle.
6824	*/
6825	DECLINLINE(int) PDMDevHlpMmio2ResetDirtyBitmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6826	{
6827	return pDevIns->pHlpR3->pfnMmio2QueryAndResetDirtyBitmap(pDevIns, hRegion, NULL, 0);
6828	}
6829
6830	/**
6831	* @copydoc PDMDEVHLPR3::pfnMmio2ControlDirtyPageTracking
6832	*/
6833	DECLINLINE(int) PDMDevHlpMmio2ControlDirtyPageTracking(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, bool fEnabled)
6834	{
6835	return pDevIns->pHlpR3->pfnMmio2ControlDirtyPageTracking(pDevIns, hRegion, fEnabled);
6836	}
6837
6838	#endif /* IN_RING3 */
6839
6840	/**
6841	* @copydoc PDMDEVHLPR3::pfnMmioMapMmio2Page
6842	*/
6843	DECLINLINE(RTGCPHYS) PDMDevHlpMmioMapMmio2Page(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6844	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags)
6845	{
6846	return pDevIns->CTX_SUFF(pHlp)->pfnMmioMapMmio2Page(pDevIns, hRegion, offRegion, hMmio2, offMmio2, fPageFlags);
6847	}
6848
6849	/**
6850	* @copydoc PDMDEVHLPR3::pfnMmioResetRegion
6851	*/
6852	DECLINLINE(RTGCPHYS) PDMDevHlpMmioResetRegion(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6853	{
6854	return pDevIns->CTX_SUFF(pHlp)->pfnMmioResetRegion(pDevIns, hRegion);
6855	}
6856
6857	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6858
6859	/**
6860	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6861	*/
6862	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6863	size_t offSub, size_t cbSub, void **ppvMapping)
6864	{
6865	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6866	}
6867
6868	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6869	#ifdef IN_RING3
6870
6871	/**
6872	* @copydoc PDMDEVHLPR3::pfnROMRegister
6873	*/
6874	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6875	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6876	{
6877	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6878	}
6879
6880	/**
6881	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6882	*/
6883	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6884	{
6885	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6886	}
6887
6888	/**
6889	* Register a save state data unit.
6890	*
6891	* @returns VBox status.
6892	* @param pDevIns The device instance.
6893	* @param uVersion Data layout version number.
6894	* @param cbGuess The approximate amount of data in the unit.
6895	* Only for progress indicators.
6896	* @param pfnSaveExec Execute save callback, optional.
6897	* @param pfnLoadExec Execute load callback, optional.
6898	*/
6899	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6900	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6901	{
6902	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6903	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6904	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6905	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6906	}
6907
6908	/**
6909	* Register a save state data unit with a live save callback as well.
6910	*
6911	* @returns VBox status.
6912	* @param pDevIns The device instance.
6913	* @param uVersion Data layout version number.
6914	* @param cbGuess The approximate amount of data in the unit.
6915	* Only for progress indicators.
6916	* @param pfnLiveExec Execute live callback, optional.
6917	* @param pfnSaveExec Execute save callback, optional.
6918	* @param pfnLoadExec Execute load callback, optional.
6919	*/
6920	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6921	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6922	{
6923	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6924	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6925	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6926	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6927	}
6928
6929	/**
6930	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6931	*/
6932	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6933	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6934	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6935	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6936	{
6937	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6938	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6939	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6940	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6941	}
6942
6943	/**
6944	* @copydoc PDMDEVHLPR3::pfnSSMRegisterLegacy
6945	*/
6946	DECLINLINE(int) PDMDevHlpSSMRegisterLegacy(PPDMDEVINS pDevIns, const char *pszOldName, PFNSSMDEVLOADPREP pfnLoadPrep,
6947	PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6948	{
6949	return pDevIns->pHlpR3->pfnSSMRegisterLegacy(pDevIns, pszOldName, pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6950	}
6951
6952	/**
6953	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6954	*/
6955	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6956	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6957	{
6958	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6959	}
6960
6961	#endif /* IN_RING3 */
6962
6963	/**
6964	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6965	*/
6966	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6967	{
6968	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6969	}
6970
6971	/**
6972	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6973	*/
6974	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6975	{
6976	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6977	}
6978
6979	/**
6980	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6981	*/
6982	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6983	{
6984	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6985	}
6986
6987	/**
6988	* @copydoc PDMDEVHLPR3::pfnTimerGet
6989	*/
6990	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6991	{
6992	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6993	}
6994
6995	/**
6996	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6997	*/
6998	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6999	{
7000	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
7001	}
7002
7003	/**
7004	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
7005	*/
7006	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7007	{
7008	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
7009	}
7010
7011	/**
7012	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
7013	*/
7014	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7015	{
7016	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
7017	}
7018
7019	/**
7020	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
7021	*/
7022	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7023	{
7024	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
7025	}
7026
7027	/**
7028	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
7029	*/
7030	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
7031	{
7032	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
7033	}
7034
7035	/**
7036	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
7037	*/
7038	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
7039	{
7040	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
7041	}
7042
7043	/**
7044	* @copydoc PDMDEVHLPR3::pfnTimerSet
7045	*/
7046	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
7047	{
7048	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
7049	}
7050
7051	/**
7052	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
7053	*/
7054	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
7055	{
7056	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
7057	}
7058
7059	/**
7060	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
7061	*/
7062	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
7063	{
7064	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
7065	}
7066
7067	/**
7068	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
7069	*/
7070	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
7071	{
7072	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
7073	}
7074
7075	/**
7076	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
7077	*/
7078	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
7079	{
7080	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
7081	}
7082
7083	/**
7084	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
7085	*/
7086	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
7087	{
7088	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
7089	}
7090
7091	/**
7092	* @copydoc PDMDEVHLPR3::pfnTimerStop
7093	*/
7094	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7095	{
7096	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
7097	}
7098
7099	/**
7100	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
7101	*/
7102	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7103	{
7104	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
7105	}
7106
7107	/**
7108	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
7109	*/
7110	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
7111	{
7112	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
7113	}
7114
7115	#ifdef IN_RING3
7116
7117	/**
7118	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
7119	*/
7120	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
7121	{
7122	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
7123	}
7124
7125	/**
7126	* @copydoc PDMDEVHLPR3::pfnTimerSave
7127	*/
7128	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
7129	{
7130	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
7131	}
7132
7133	/**
7134	* @copydoc PDMDEVHLPR3::pfnTimerLoad
7135	*/
7136	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
7137	{
7138	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
7139	}
7140
7141	/**
7142	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
7143	*/
7144	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7145	{
7146	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
7147	}
7148
7149	/**
7150	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
7151	*/
7152	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
7153	{
7154	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
7155	}
7156
7157	#endif
7158
7159	/**
7160	* Read physical memory - unknown data usage.
7161	*
7162	* @returns VINF_SUCCESS (for now).
7163	* @param pDevIns The device instance.
7164	* @param GCPhys Physical address start reading from.
7165	* @param pvBuf Where to put the read bits.
7166	* @param cbRead How many bytes to read.
7167	* @thread Any thread, but the call may involve the emulation thread.
7168	*/
7169	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7170	{
7171	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7172	}
7173
7174	/**
7175	* Write to physical memory - unknown data usage.
7176	*
7177	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7178	* @param pDevIns The device instance.
7179	* @param GCPhys Physical address to write to.
7180	* @param pvBuf What to write.
7181	* @param cbWrite How many bytes to write.
7182	* @thread Any thread, but the call may involve the emulation thread.
7183	*/
7184	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7185	{
7186	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7187	}
7188
7189	/**
7190	* Read physical memory - reads meta data processed by the device.
7191	*
7192	* @returns VINF_SUCCESS (for now).
7193	* @param pDevIns The device instance.
7194	* @param GCPhys Physical address start reading from.
7195	* @param pvBuf Where to put the read bits.
7196	* @param cbRead How many bytes to read.
7197	* @thread Any thread, but the call may involve the emulation thread.
7198	*/
7199	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7200	{
7201	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7202	}
7203
7204	/**
7205	* Write to physical memory - written data was created/altered by the device.
7206	*
7207	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7208	* @param pDevIns The device instance.
7209	* @param GCPhys Physical address to write to.
7210	* @param pvBuf What to write.
7211	* @param cbWrite How many bytes to write.
7212	* @thread Any thread, but the call may involve the emulation thread.
7213	*/
7214	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7215	{
7216	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7217	}
7218
7219	/**
7220	* Read physical memory - read data will not be touched by the device.
7221	*
7222	* @returns VINF_SUCCESS (for now).
7223	* @param pDevIns The device instance.
7224	* @param GCPhys Physical address start reading from.
7225	* @param pvBuf Where to put the read bits.
7226	* @param cbRead How many bytes to read.
7227	* @thread Any thread, but the call may involve the emulation thread.
7228	*/
7229	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7230	{
7231	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7232	}
7233
7234	/**
7235	* Write to physical memory - written data was not touched/created by the device.
7236	*
7237	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7238	* @param pDevIns The device instance.
7239	* @param GCPhys Physical address to write to.
7240	* @param pvBuf What to write.
7241	* @param cbWrite How many bytes to write.
7242	* @thread Any thread, but the call may involve the emulation thread.
7243	*/
7244	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7245	{
7246	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7247	}
7248
7249	#ifdef IN_RING3
7250
7251	/**
7252	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
7253	*/
7254	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
7255	{
7256	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
7257	}
7258
7259	/**
7260	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
7261	*/
7262	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
7263	PPGMPAGEMAPLOCK pLock)
7264	{
7265	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
7266	}
7267
7268	/**
7269	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
7270	*/
7271	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
7272	{
7273	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
7274	}
7275
7276	/**
7277	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
7278	*/
7279	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7280	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
7281	{
7282	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7283	}
7284
7285	/**
7286	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
7287	*/
7288	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7289	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
7290	{
7291	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7292	}
7293
7294	/**
7295	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
7296	*/
7297	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
7298	{
7299	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
7300	}
7301
7302	/**
7303	* @copydoc PDMDEVHLPR3::pfnPhysIsGCPhysNormal
7304	*/
7305	DECLINLINE(bool) PDMDevHlpPhysIsGCPhysNormal(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
7306	{
7307	return pDevIns->CTX_SUFF(pHlp)->pfnPhysIsGCPhysNormal(pDevIns, GCPhys);
7308	}
7309
7310	/**
7311	* @copydoc PDMDEVHLPR3::pfnPhysChangeMemBalloon
7312	*/
7313	DECLINLINE(int) PDMDevHlpPhysChangeMemBalloon(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
7314	{
7315	return pDevIns->CTX_SUFF(pHlp)->pfnPhysChangeMemBalloon(pDevIns, fInflate, cPages, paPhysPage);
7316	}
7317
7318	/**
7319	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
7320	*/
7321	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
7322	{
7323	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
7324	}
7325
7326	/**
7327	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestScalableBusFrequency
7328	*/
7329	DECLINLINE(uint64_t) PDMDevHlpCpuGetGuestScalableBusFrequency(PPDMDEVINS pDevIns)
7330	{
7331	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestScalableBusFrequency(pDevIns);
7332	}
7333
7334	/**
7335	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
7336	*/
7337	DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth)
7338	{
7339	pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
7340	}
7341
7342	/**
7343	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
7344	*/
7345	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
7346	{
7347	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
7348	}
7349
7350	/**
7351	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
7352	*/
7353	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
7354	{
7355	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
7356	}
7357
7358	/**
7359	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
7360	*/
7361	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
7362	{
7363	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
7364	}
7365
7366	/**
7367	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
7368	*/
7369	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
7370	{
7371	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
7372	}
7373
7374	/**
7375	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
7376	*/
7377	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
7378	{
7379	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
7380	}
7381
7382	/**
7383	* Allocating string printf.
7384	*
7385	* @returns Pointer to the string.
7386	* @param pDevIns The device instance.
7387	* @param enmTag The statistics tag.
7388	* @param pszFormat The format string.
7389	* @param ... Format arguments.
7390	*/
7391	DECLINLINE(char ) RT_IPRT_FORMAT_ATTR(2, 3) PDMDevHlpMMHeapAPrintf(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, ...)
7392	{
7393	va_list va;
7394	va_start(va, pszFormat);
7395	char *psz = pDevIns->pHlpR3->pfnMMHeapAPrintfV(pDevIns, enmTag, pszFormat, va);
7396	va_end(va);
7397
7398	return psz;
7399	}
7400
7401	/**
7402	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
7403	*/
7404	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
7405	{
7406	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
7407	}
7408
7409	/**
7410	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSize
7411	*/
7412	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSize(PPDMDEVINS pDevIns)
7413	{
7414	return pDevIns->pHlpR3->pfnMMPhysGetRamSize(pDevIns);
7415	}
7416
7417	/**
7418	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeBelow4GB
7419	*/
7420	DECLINLINE(uint32_t) PDMDevHlpMMPhysGetRamSizeBelow4GB(PPDMDEVINS pDevIns)
7421	{
7422	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeBelow4GB(pDevIns);
7423	}
7424
7425	/**
7426	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeAbove4GB
7427	*/
7428	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSizeAbove4GB(PPDMDEVINS pDevIns)
7429	{
7430	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeAbove4GB(pDevIns);
7431	}
7432	#endif /* IN_RING3 */
7433
7434	/**
7435	* @copydoc PDMDEVHLPR3::pfnVMState
7436	*/
7437	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
7438	{
7439	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
7440	}
7441
7442	#ifdef IN_RING3
7443
7444	/**
7445	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
7446	*/
7447	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
7448	{
7449	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
7450	}
7451
7452	/**
7453	* Set the VM error message
7454	*
7455	* @returns rc.
7456	* @param pDevIns The device instance.
7457	* @param rc VBox status code.
7458	* @param SRC_POS Use RT_SRC_POS.
7459	* @param pszFormat Error message format string.
7460	* @param ... Error message arguments.
7461	* @sa VMSetError
7462	*/
7463	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
7464	const char *pszFormat, ...)
7465	{
7466	va_list va;
7467	va_start(va, pszFormat);
7468	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
7469	va_end(va);
7470	return rc;
7471	}
7472
7473	/**
7474	* Set the VM runtime error message
7475	*
7476	* @returns VBox status code.
7477	* @param pDevIns The device instance.
7478	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
7479	* @param pszErrorId Error ID string.
7480	* @param pszFormat Error message format string.
7481	* @param ... Error message arguments.
7482	* @sa VMSetRuntimeError
7483	*/
7484	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
7485	const char *pszFormat, ...)
7486	{
7487	va_list va;
7488	int rc;
7489	va_start(va, pszFormat);
7490	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
7491	va_end(va);
7492	return rc;
7493	}
7494
7495	/**
7496	* @copydoc PDMDEVHLPR3::pfnVMWaitForDeviceReady
7497	*/
7498	DECLINLINE(int) PDMDevHlpVMWaitForDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7499	{
7500	return pDevIns->CTX_SUFF(pHlp)->pfnVMWaitForDeviceReady(pDevIns, idCpu);
7501	}
7502
7503	/**
7504	* @copydoc PDMDEVHLPR3::pfnVMNotifyCpuDeviceReady
7505	*/
7506	DECLINLINE(int) PDMDevHlpVMNotifyCpuDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7507	{
7508	return pDevIns->CTX_SUFF(pHlp)->pfnVMNotifyCpuDeviceReady(pDevIns, idCpu);
7509	}
7510
7511	/**
7512	* Convenience wrapper for VMR3ReqCallU.
7513	*
7514	* This assumes (1) you're calling a function that returns an VBox status code
7515	* and that you do not wish to wait for it to complete.
7516	*
7517	* @returns VBox status code returned by VMR3ReqCallVU.
7518	*
7519	* @param pDevIns The device instance.
7520	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7521	* one of the following special values:
7522	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7523	* @param pfnFunction Pointer to the function to call.
7524	* @param cArgs Number of arguments following in the ellipsis.
7525	* @param ... Argument list.
7526	*
7527	* @remarks See remarks on VMR3ReqCallVU.
7528	*/
7529	DECLINLINE(int) PDMDevHlpVMReqCallNoWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7530	{
7531	va_list Args;
7532	va_start(Args, cArgs);
7533	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqCallNoWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7534	va_end(Args);
7535	return rc;
7536	}
7537
7538	/**
7539	* Convenience wrapper for VMR3ReqCallU.
7540	*
7541	* This assumes (1) you're calling a function that returns void, (2) that you
7542	* wish to wait for ever for it to return, and (3) that it's priority request
7543	* that can be safely be handled during async suspend and power off.
7544	*
7545	* @returns VBox status code of VMR3ReqCallVU.
7546	*
7547	* @param pDevIns The device instance.
7548	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7549	* one of the following special values:
7550	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7551	* @param pfnFunction Pointer to the function to call.
7552	* @param cArgs Number of arguments following in the ellipsis.
7553	* @param ... Argument list.
7554	*
7555	* @remarks See remarks on VMR3ReqCallVU.
7556	*/
7557	DECLINLINE(int) PDMDevHlpVMReqPriorityCallWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7558	{
7559	va_list Args;
7560	va_start(Args, cArgs);
7561	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqPriorityCallWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7562	va_end(Args);
7563	return rc;
7564	}
7565
7566	#endif /* IN_RING3 */
7567
7568	/**
7569	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
7570	*
7571	* @returns VBox status code which must be passed up to the VMM. This will be
7572	* VINF_SUCCESS in non-strict builds.
7573	* @param pDevIns The device instance.
7574	* @param SRC_POS Use RT_SRC_POS.
7575	* @param pszFormat Message. (optional)
7576	* @param ... Message parameters.
7577	*/
7578	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
7579	{
7580	#ifdef VBOX_STRICT
7581	# ifdef IN_RING3
7582	int rc;
7583	va_list args;
7584	va_start(args, pszFormat);
7585	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
7586	va_end(args);
7587	return rc;
7588	# else
7589	NOREF(pDevIns);
7590	NOREF(pszFile);
7591	NOREF(iLine);
7592	NOREF(pszFunction);
7593	NOREF(pszFormat);
7594	return VINF_EM_DBG_STOP;
7595	# endif
7596	#else
7597	NOREF(pDevIns);
7598	NOREF(pszFile);
7599	NOREF(iLine);
7600	NOREF(pszFunction);
7601	NOREF(pszFormat);
7602	return VINF_SUCCESS;
7603	#endif
7604	}
7605
7606	#ifdef IN_RING3
7607
7608	/**
7609	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
7610	*/
7611	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
7612	{
7613	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
7614	}
7615
7616	/**
7617	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
7618	*/
7619	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
7620	{
7621	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
7622	}
7623
7624	/**
7625	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
7626	*/
7627	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
7628	{
7629	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
7630	}
7631
7632	/**
7633	* @copydoc PDMDEVHLPR3::pfnDBGFReportBugCheck
7634	*/
7635	DECLINLINE(VBOXSTRICTRC) PDMDevHlpDBGFReportBugCheck(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
7636	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4)
7637	{
7638	return pDevIns->pHlpR3->pfnDBGFReportBugCheck(pDevIns, enmEvent, uBugCheck, uP1, uP2, uP3, uP4);
7639	}
7640
7641	/**
7642	* @copydoc PDMDEVHLPR3::pfnDBGFCoreWrite
7643	*/
7644	DECLINLINE(int) PDMDevHlpDBGFCoreWrite(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile)
7645	{
7646	return pDevIns->pHlpR3->pfnDBGFCoreWrite(pDevIns, pszFilename, fReplaceFile);
7647	}
7648
7649	/**
7650	* @copydoc PDMDEVHLPR3::pfnDBGFInfoLogHlp
7651	*/
7652	DECLINLINE(PCDBGFINFOHLP) PDMDevHlpDBGFInfoLogHlp(PPDMDEVINS pDevIns)
7653	{
7654	return pDevIns->pHlpR3->pfnDBGFInfoLogHlp(pDevIns);
7655	}
7656
7657	/**
7658	* @copydoc PDMDEVHLPR3::pfnDBGFRegNmQueryU64
7659	*/
7660	DECLINLINE(int) PDMDevHlpDBGFRegNmQueryU64(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64)
7661	{
7662	return pDevIns->pHlpR3->pfnDBGFRegNmQueryU64(pDevIns, idDefCpu, pszReg, pu64);
7663	}
7664
7665	/**
7666	* Format a set of registers.
7667	*
7668	* This is restricted to registers from one CPU, that specified by @a idCpu.
7669	*
7670	* @returns VBox status code.
7671	* @param pDevIns The device instance.
7672	* @param idCpu The CPU ID of any CPU registers that may be
7673	* printed, pass VMCPUID_ANY if not applicable.
7674	* @param pszBuf The output buffer.
7675	* @param cbBuf The size of the output buffer.
7676	* @param pszFormat The format string. Register names are given by
7677	* %VR{name}, they take no arguments.
7678	* @param ... Argument list.
7679	*/
7680	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpDBGFRegPrintf(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
7681	const char *pszFormat, ...)
7682	{
7683	va_list Args;
7684	va_start(Args, pszFormat);
7685	int rc = pDevIns->pHlpR3->pfnDBGFRegPrintfV(pDevIns, idCpu, pszBuf, cbBuf, pszFormat, Args);
7686	va_end(Args);
7687	return rc;
7688	}
7689
7690	/**
7691	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
7692	*/
7693	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
7694	{
7695	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
7696	}
7697
7698	/**
7699	* Same as pfnSTAMRegister except that the name is specified in a
7700	* RTStrPrintf like fashion.
7701	*
7702	* @returns VBox status.
7703	* @param pDevIns Device instance of the DMA.
7704	* @param pvSample Pointer to the sample.
7705	* @param enmType Sample type. This indicates what pvSample is
7706	* pointing at.
7707	* @param enmVisibility Visibility type specifying whether unused
7708	* statistics should be visible or not.
7709	* @param enmUnit Sample unit.
7710	* @param pszDesc Sample description.
7711	* @param pszName Sample name format string, unix path style. If
7712	* this does not start with a '/', the default
7713	* prefix will be prepended, otherwise it will be
7714	* used as-is.
7715	* @param ... Arguments to the format string.
7716	*/
7717	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
7718	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
7719	const char pszDesc, const char pszName, ...)
7720	{
7721	va_list va;
7722	va_start(va, pszName);
7723	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
7724	va_end(va);
7725	}
7726
7727	/**
7728	* @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
7729	*/
7730	DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
7731	{
7732	return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
7733	}
7734
7735	/**
7736	* Registers the device with the default PCI bus.
7737	*
7738	* @returns VBox status code.
7739	* @param pDevIns The device instance.
7740	* @param pPciDev The PCI device structure.
7741	* This must be kept in the instance data.
7742	* The PCI configuration must be initialized before registration.
7743	*/
7744	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
7745	{
7746	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
7747	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
7748	}
7749
7750	/**
7751	* @copydoc PDMDEVHLPR3::pfnPCIRegister
7752	*/
7753	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
7754	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
7755	{
7756	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
7757	}
7758
7759	/**
7760	* Initialize MSI emulation support for the first PCI device.
7761	*
7762	* @returns VBox status code.
7763	* @param pDevIns The device instance.
7764	* @param pMsiReg MSI emulation registration structure.
7765	*/
7766	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
7767	{
7768	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
7769	}
7770
7771	/**
7772	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
7773	*/
7774	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
7775	{
7776	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
7777	}
7778
7779	/**
7780	* Registers a I/O port region for the default PCI device.
7781	*
7782	* @returns VBox status code.
7783	* @param pDevIns The device instance.
7784	* @param iRegion The region number.
7785	* @param cbRegion Size of the region.
7786	* @param hIoPorts Handle to the I/O port region.
7787	*/
7788	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
7789	{
7790	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7791	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
7792	}
7793
7794	/**
7795	* Registers a I/O port region for the default PCI device, custom map/unmap.
7796	*
7797	* @returns VBox status code.
7798	* @param pDevIns The device instance.
7799	* @param iRegion The region number.
7800	* @param cbRegion Size of the region.
7801	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7802	* callback will be invoked holding only the PDM lock.
7803	* The device lock will _not_ be taken (due to lock
7804	* order).
7805	*/
7806	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7807	PFNPCIIOREGIONMAP pfnMapUnmap)
7808	{
7809	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7810	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7811	UINT64_MAX, pfnMapUnmap);
7812	}
7813
7814	/**
7815	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7816	* and registering an I/O port region for the default PCI device.
7817	*
7818	* @returns VBox status code.
7819	* @param pDevIns The device instance to register the ports with.
7820	* @param cPorts The count of I/O ports in the region (the size).
7821	* @param iPciRegion The PCI device region.
7822	* @param pfnOut Pointer to function which is gonna handle OUT
7823	* operations. Optional.
7824	* @param pfnIn Pointer to function which is gonna handle IN operations.
7825	* Optional.
7826	* @param pvUser User argument to pass to the callbacks.
7827	* @param pszDesc Pointer to description string. This must not be freed.
7828	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7829	* coverage is allowed. This must not be freed.
7830	* @param phIoPorts Where to return the I/O port range handle.
7831	*
7832	*/
7833	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7834	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7835	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7836
7837	{
7838	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7839	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7840	if (RT_SUCCESS(rc))
7841	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7842	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7843	phIoPorts, NULL /pfnMapUnmap*/);
7844	return rc;
7845	}
7846
7847	/**
7848	* Registers an MMIO region for the default PCI device.
7849	*
7850	* @returns VBox status code.
7851	* @param pDevIns The device instance.
7852	* @param iRegion The region number.
7853	* @param cbRegion Size of the region.
7854	* @param enmType PCI_ADDRESS_SPACE_MEM or
7855	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7856	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7857	* @param hMmioRegion Handle to the MMIO region.
7858	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7859	* callback will be invoked holding only the PDM lock.
7860	* The device lock will _not_ be taken (due to lock
7861	* order).
7862	*/
7863	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7864	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7865	{
7866	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7867	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7868	hMmioRegion, pfnMapUnmap);
7869	}
7870
7871	/**
7872	* Registers an MMIO region for the default PCI device, extended version.
7873	*
7874	* @returns VBox status code.
7875	* @param pDevIns The device instance.
7876	* @param pPciDev The PCI device structure.
7877	* @param iRegion The region number.
7878	* @param cbRegion Size of the region.
7879	* @param enmType PCI_ADDRESS_SPACE_MEM or
7880	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7881	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7882	* @param hMmioRegion Handle to the MMIO region.
7883	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7884	* callback will be invoked holding only the PDM lock.
7885	* The device lock will _not_ be taken (due to lock
7886	* order).
7887	*/
7888	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7889	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7890	PFNPCIIOREGIONMAP pfnMapUnmap)
7891	{
7892	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7893	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7894	hMmioRegion, pfnMapUnmap);
7895	}
7896
7897	/**
7898	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7899	* and registering an MMIO region for the default PCI device.
7900	*
7901	* @returns VBox status code.
7902	* @param pDevIns The device instance to register the ports with.
7903	* @param cbRegion The size of the region in bytes.
7904	* @param iPciRegion The PCI device region.
7905	* @param enmType PCI_ADDRESS_SPACE_MEM or
7906	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7907	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7908	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7909	* @param pfnWrite Pointer to function which is gonna handle Write
7910	* operations.
7911	* @param pfnRead Pointer to function which is gonna handle Read
7912	* operations.
7913	* @param pvUser User argument to pass to the callbacks.
7914	* @param pszDesc Pointer to description string. This must not be freed.
7915	* @param phRegion Where to return the MMIO region handle.
7916	*
7917	*/
7918	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7919	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7920	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7921
7922	{
7923	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7924	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7925	if (RT_SUCCESS(rc))
7926	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7927	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7928	phRegion, NULL /pfnMapUnmap*/);
7929	return rc;
7930	}
7931
7932
7933	/**
7934	* Registers an MMIO2 region for the default PCI device.
7935	*
7936	* @returns VBox status code.
7937	* @param pDevIns The device instance.
7938	* @param iRegion The region number.
7939	* @param cbRegion Size of the region.
7940	* @param enmType PCI_ADDRESS_SPACE_MEM or
7941	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7942	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7943	* @param hMmio2Region Handle to the MMIO2 region.
7944	*/
7945	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7946	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7947	{
7948	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7949	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7950	hMmio2Region, NULL);
7951	}
7952
7953	/**
7954	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7955	* and registering an MMIO2 region for the default PCI device, extended edition.
7956	*
7957	* @returns VBox status code.
7958	* @param pDevIns The device instance to register the ports with.
7959	* @param cbRegion The size of the region in bytes.
7960	* @param iPciRegion The PCI device region.
7961	* @param enmType PCI_ADDRESS_SPACE_MEM or
7962	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7963	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7964	* @param pszDesc Pointer to description string. This must not be freed.
7965	* @param ppvMapping Where to store the address of the ring-3 mapping of
7966	* the memory.
7967	* @param phRegion Where to return the MMIO2 region handle.
7968	*
7969	*/
7970	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7971	PCIADDRESSSPACE enmType, const char *pszDesc,
7972	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7973
7974	{
7975	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7976	pszDesc, ppvMapping, phRegion);
7977	if (RT_SUCCESS(rc))
7978	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7979	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7980	phRegion, NULL /pfnCallback*/);
7981	return rc;
7982	}
7983
7984	/**
7985	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7986	* and registering an MMIO2 region for the default PCI device.
7987	*
7988	* @returns VBox status code.
7989	* @param pDevIns The device instance to register the ports with.
7990	* @param cbRegion The size of the region in bytes.
7991	* @param iPciRegion The PCI device region.
7992	* @param enmType PCI_ADDRESS_SPACE_MEM or
7993	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7994	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7995	* @param fMmio2Flags PGMPHYS_MMIO2_FLAGS_XXX (see pgm.h).
7996	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7997	* callback will be invoked holding only the PDM lock.
7998	* The device lock will _not_ be taken (due to lock
7999	* order).
8000	* @param pszDesc Pointer to description string. This must not be freed.
8001	* @param ppvMapping Where to store the address of the ring-3 mapping of
8002	* the memory.
8003	* @param phRegion Where to return the MMIO2 region handle.
8004	*
8005	*/
8006	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
8007	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
8008	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
8009
8010	{
8011	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
8012	pszDesc, ppvMapping, phRegion);
8013	if (RT_SUCCESS(rc))
8014	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
8015	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
8016	*phRegion, pfnMapUnmap);
8017	return rc;
8018	}
8019
8020	/**
8021	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
8022	*/
8023	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
8024	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
8025	{
8026	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
8027	}
8028
8029	/**
8030	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
8031	*/
8032	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
8033	unsigned cb, uint32_t *pu32Value)
8034	{
8035	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
8036	}
8037
8038	/**
8039	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
8040	*/
8041	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
8042	unsigned cb, uint32_t u32Value)
8043	{
8044	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
8045	}
8046
8047	#endif /* IN_RING3 */
8048
8049	/**
8050	* Bus master physical memory read from the default PCI device.
8051	*
8052	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8053	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8054	* @param pDevIns The device instance.
8055	* @param GCPhys Physical address start reading from.
8056	* @param pvBuf Where to put the read bits.
8057	* @param cbRead How many bytes to read.
8058	* @thread Any thread, but the call may involve the emulation thread.
8059	*/
8060	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8061	{
8062	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8063	}
8064
8065	/**
8066	* Bus master physical memory read - unknown data usage.
8067	*
8068	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8069	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8070	* @param pDevIns The device instance.
8071	* @param pPciDev The PCI device structure. If NULL the default
8072	* PCI device for this device instance is used.
8073	* @param GCPhys Physical address start reading from.
8074	* @param pvBuf Where to put the read bits.
8075	* @param cbRead How many bytes to read.
8076	* @thread Any thread, but the call may involve the emulation thread.
8077	*/
8078	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8079	{
8080	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8081	}
8082
8083	/**
8084	* Bus master physical memory read from the default PCI device.
8085	*
8086	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8087	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8088	* @param pDevIns The device instance.
8089	* @param GCPhys Physical address start reading from.
8090	* @param pvBuf Where to put the read bits.
8091	* @param cbRead How many bytes to read.
8092	* @thread Any thread, but the call may involve the emulation thread.
8093	*/
8094	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8095	{
8096	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8097	}
8098
8099	/**
8100	* Bus master physical memory read - reads meta data processed by the device.
8101	*
8102	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8103	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8104	* @param pDevIns The device instance.
8105	* @param pPciDev The PCI device structure. If NULL the default
8106	* PCI device for this device instance is used.
8107	* @param GCPhys Physical address start reading from.
8108	* @param pvBuf Where to put the read bits.
8109	* @param cbRead How many bytes to read.
8110	* @thread Any thread, but the call may involve the emulation thread.
8111	*/
8112	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8113	{
8114	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8115	}
8116
8117	/**
8118	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
8119	*
8120	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8121	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8122	* @param pDevIns The device instance.
8123	* @param GCPhys Physical address start reading from.
8124	* @param pvBuf Where to put the read bits.
8125	* @param cbRead How many bytes to read.
8126	* @thread Any thread, but the call may involve the emulation thread.
8127	*/
8128	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8129	{
8130	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8131	}
8132
8133	/**
8134	* Bus master physical memory read - read data will not be touched by the device.
8135	*
8136	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8137	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8138	* @param pDevIns The device instance.
8139	* @param pPciDev The PCI device structure. If NULL the default
8140	* PCI device for this device instance is used.
8141	* @param GCPhys Physical address start reading from.
8142	* @param pvBuf Where to put the read bits.
8143	* @param cbRead How many bytes to read.
8144	* @thread Any thread, but the call may involve the emulation thread.
8145	*/
8146	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8147	{
8148	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8149	}
8150
8151	/**
8152	* Bus master physical memory write from the default PCI device - unknown data usage.
8153	*
8154	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8155	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8156	* @param pDevIns The device instance.
8157	* @param GCPhys Physical address to write to.
8158	* @param pvBuf What to write.
8159	* @param cbWrite How many bytes to write.
8160	* @thread Any thread, but the call may involve the emulation thread.
8161	*/
8162	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8163	{
8164	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8165	}
8166
8167	/**
8168	* Bus master physical memory write - unknown data usage.
8169	*
8170	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8171	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8172	* @param pDevIns The device instance.
8173	* @param pPciDev The PCI device structure. If NULL the default
8174	* PCI device for this device instance is used.
8175	* @param GCPhys Physical address to write to.
8176	* @param pvBuf What to write.
8177	* @param cbWrite How many bytes to write.
8178	* @thread Any thread, but the call may involve the emulation thread.
8179	*/
8180	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8181	{
8182	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8183	}
8184
8185	/**
8186	* Bus master physical memory write from the default PCI device.
8187	*
8188	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8189	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8190	* @param pDevIns The device instance.
8191	* @param GCPhys Physical address to write to.
8192	* @param pvBuf What to write.
8193	* @param cbWrite How many bytes to write.
8194	* @thread Any thread, but the call may involve the emulation thread.
8195	*/
8196	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8197	{
8198	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8199	}
8200
8201	/**
8202	* Bus master physical memory write - written data was created/altered by the device.
8203	*
8204	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8205	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8206	* @param pDevIns The device instance.
8207	* @param pPciDev The PCI device structure. If NULL the default
8208	* PCI device for this device instance is used.
8209	* @param GCPhys Physical address to write to.
8210	* @param pvBuf What to write.
8211	* @param cbWrite How many bytes to write.
8212	* @thread Any thread, but the call may involve the emulation thread.
8213	*/
8214	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8215	{
8216	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8217	}
8218
8219	/**
8220	* Bus master physical memory write from the default PCI device.
8221	*
8222	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8223	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8224	* @param pDevIns The device instance.
8225	* @param GCPhys Physical address to write to.
8226	* @param pvBuf What to write.
8227	* @param cbWrite How many bytes to write.
8228	* @thread Any thread, but the call may involve the emulation thread.
8229	*/
8230	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8231	{
8232	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8233	}
8234
8235	/**
8236	* Bus master physical memory write - written data was not touched/created by the device.
8237	*
8238	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8239	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8240	* @param pDevIns The device instance.
8241	* @param pPciDev The PCI device structure. If NULL the default
8242	* PCI device for this device instance is used.
8243	* @param GCPhys Physical address to write to.
8244	* @param pvBuf What to write.
8245	* @param cbWrite How many bytes to write.
8246	* @thread Any thread, but the call may involve the emulation thread.
8247	*/
8248	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8249	{
8250	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8251	}
8252
8253	#ifdef IN_RING3
8254	/**
8255	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
8256	*/
8257	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8258	void **ppv, PPGMPAGEMAPLOCK pLock)
8259	{
8260	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8261	}
8262
8263	/**
8264	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
8265	*/
8266	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8267	void const **ppv, PPGMPAGEMAPLOCK pLock)
8268	{
8269	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8270	}
8271
8272	/**
8273	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
8274	*/
8275	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8276	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
8277	PPGMPAGEMAPLOCK paLocks)
8278	{
8279	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
8280	paLocks);
8281	}
8282
8283	/**
8284	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
8285	*/
8286	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8287	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
8288	PPGMPAGEMAPLOCK paLocks)
8289	{
8290	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
8291	papvPages, paLocks);
8292	}
8293	#endif /* IN_RING3 */
8294
8295	/**
8296	* Sets the IRQ for the default PCI device.
8297	*
8298	* @param pDevIns The device instance.
8299	* @param iIrq IRQ number to set.
8300	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
8301	* @thread Any thread, but will involve the emulation thread.
8302	*/
8303	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8304	{
8305	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8306	}
8307
8308	/**
8309	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
8310	*/
8311	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8312	{
8313	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8314	}
8315
8316	/**
8317	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
8318	* the request when not called from EMT.
8319	*
8320	* @param pDevIns The device instance.
8321	* @param iIrq IRQ number to set.
8322	* @param iLevel IRQ level.
8323	* @thread Any thread, but will involve the emulation thread.
8324	*/
8325	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8326	{
8327	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8328	}
8329
8330	/**
8331	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
8332	*/
8333	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8334	{
8335	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8336	}
8337
8338	/**
8339	* @copydoc PDMDEVHLPR3::pfnISASetIrq
8340	*/
8341	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8342	{
8343	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8344	}
8345
8346	/**
8347	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
8348	*/
8349	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8350	{
8351	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8352	}
8353
8354	#ifdef IN_RING3
8355
8356	/**
8357	* @copydoc PDMDEVHLPR3::pfnDriverAttach
8358	*/
8359	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
8360	{
8361	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
8362	}
8363
8364	/**
8365	* @copydoc PDMDEVHLPR3::pfnDriverDetach
8366	*/
8367	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
8368	{
8369	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
8370	}
8371
8372	/**
8373	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
8374	*/
8375	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
8376	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
8377	{
8378	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
8379	}
8380
8381	/**
8382	* Reconfigures with a single driver reattachement, no config, noflags.
8383	* @sa PDMDevHlpDriverReconfigure
8384	*/
8385	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
8386	{
8387	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
8388	}
8389
8390	/**
8391	* Reconfigures with a two drivers reattachement, no config, noflags.
8392	* @sa PDMDevHlpDriverReconfigure
8393	*/
8394	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
8395	{
8396	char const * apszDrivers[2];
8397	apszDrivers[0] = pszDriver0;
8398	apszDrivers[1] = pszDriver1;
8399	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
8400	}
8401
8402	/**
8403	* @copydoc PDMDEVHLPR3::pfnQueueCreate
8404	*/
8405	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
8406	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
8407	{
8408	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
8409	}
8410
8411	#endif /* IN_RING3 */
8412
8413	/**
8414	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
8415	*/
8416	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8417	{
8418	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
8419	}
8420
8421	/**
8422	* @copydoc PDMDEVHLPR3::pfnQueueInsert
8423	*/
8424	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
8425	{
8426	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
8427	}
8428
8429	/**
8430	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
8431	*/
8432	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8433	{
8434	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
8435	}
8436
8437	#ifdef IN_RING3
8438	/**
8439	* @copydoc PDMDEVHLPR3::pfnTaskCreate
8440	*/
8441	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
8442	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
8443	{
8444	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
8445	}
8446	#endif
8447
8448	/**
8449	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
8450	*/
8451	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
8452	{
8453	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
8454	}
8455
8456	#ifdef IN_RING3
8457
8458	/**
8459	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
8460	*/
8461	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
8462	{
8463	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
8464	}
8465
8466	/**
8467	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
8468	*/
8469	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8470	{
8471	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
8472	}
8473
8474	#endif /* IN_RING3 */
8475
8476	/**
8477	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
8478	*/
8479	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8480	{
8481	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
8482	}
8483
8484	/**
8485	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
8486	*/
8487	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
8488	{
8489	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
8490	}
8491
8492	/**
8493	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
8494	*/
8495	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
8496	{
8497	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
8498	}
8499
8500	/**
8501	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
8502	*/
8503	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
8504	{
8505	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
8506	}
8507
8508	/**
8509	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
8510	*/
8511	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
8512	{
8513	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
8514	}
8515
8516	#ifdef IN_RING3
8517
8518	/**
8519	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
8520	*/
8521	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
8522	{
8523	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
8524	}
8525
8526	/**
8527	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
8528	*/
8529	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8530	{
8531	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
8532	}
8533
8534	#endif /* IN_RING3 */
8535
8536	/**
8537	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
8538	*/
8539	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8540	{
8541	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
8542	}
8543
8544	/**
8545	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
8546	*/
8547	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8548	{
8549	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
8550	}
8551
8552	/**
8553	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
8554	*/
8555	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
8556	{
8557	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
8558	}
8559
8560	/**
8561	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
8562	*/
8563	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
8564	{
8565	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
8566	}
8567
8568	/**
8569	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
8570	*/
8571	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
8572	{
8573	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
8574	}
8575
8576	/**
8577	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
8578	*/
8579	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
8580	{
8581	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
8582	}
8583
8584	#ifdef IN_RING3
8585
8586	/**
8587	* Initializes a PDM critical section.
8588	*
8589	* The PDM critical sections are derived from the IPRT critical sections, but
8590	* works in RC and R0 as well.
8591	*
8592	* @returns VBox status code.
8593	* @param pDevIns The device instance.
8594	* @param pCritSect Pointer to the critical section.
8595	* @param SRC_POS Use RT_SRC_POS.
8596	* @param pszNameFmt Format string for naming the critical section.
8597	* For statistics and lock validation.
8598	* @param ... Arguments for the format string.
8599	*/
8600	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
8601	const char *pszNameFmt, ...)
8602	{
8603	int rc;
8604	va_list va;
8605	va_start(va, pszNameFmt);
8606	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8607	va_end(va);
8608	return rc;
8609	}
8610
8611	#endif /* IN_RING3 */
8612
8613	/**
8614	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
8615	*/
8616	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
8617	{
8618	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
8619	}
8620
8621	/**
8622	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
8623	*/
8624	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8625	{
8626	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
8627	}
8628
8629	/**
8630	* Enters a PDM critical section.
8631	*
8632	* @returns VINF_SUCCESS if entered successfully.
8633	* @returns rcBusy when encountering a busy critical section in RC/R0.
8634	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8635	* during the operation.
8636	*
8637	* @param pDevIns The device instance.
8638	* @param pCritSect The PDM critical section to enter.
8639	* @param rcBusy The status code to return when we're in RC or R0
8640	* and the section is busy. Pass VINF_SUCCESS to
8641	* acquired the critical section thru a ring-3
8642	* call if necessary.
8643	*
8644	* @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
8645	* possible failures in ring-0 or at least apply
8646	* PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
8647	* function.
8648	*
8649	* @sa PDMCritSectEnter
8650	*/
8651	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
8652	{
8653	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
8654	}
8655
8656	/**
8657	* Enters a PDM critical section, with location information for debugging.
8658	*
8659	* @returns VINF_SUCCESS if entered successfully.
8660	* @returns rcBusy when encountering a busy critical section in RC/R0.
8661	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8662	* during the operation.
8663	*
8664	* @param pDevIns The device instance.
8665	* @param pCritSect The PDM critical section to enter.
8666	* @param rcBusy The status code to return when we're in RC or R0
8667	* and the section is busy. Pass VINF_SUCCESS to
8668	* acquired the critical section thru a ring-3
8669	* call if necessary.
8670	* @param uId Some kind of locking location ID. Typically a
8671	* return address up the stack. Optional (0).
8672	* @param SRC_POS The source position where to lock is being
8673	* acquired from. Optional.
8674	* @sa PDMCritSectEnterDebug
8675	*/
8676	DECLINLINE(DECL_CHECK_RETURN(int))
8677	PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8678	{
8679	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8680	}
8681
8682	/**
8683	* Try enter a critical section.
8684	*
8685	* @retval VINF_SUCCESS on success.
8686	* @retval VERR_SEM_BUSY if the critsect was owned.
8687	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8688	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8689	* during the operation.
8690	*
8691	* @param pDevIns The device instance.
8692	* @param pCritSect The critical section.
8693	* @sa PDMCritSectTryEnter
8694	*/
8695	DECLINLINE(DECL_CHECK_RETURN(int))
8696	PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8697	{
8698	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
8699	}
8700
8701	/**
8702	* Try enter a critical section, with location information for debugging.
8703	*
8704	* @retval VINF_SUCCESS on success.
8705	* @retval VERR_SEM_BUSY if the critsect was owned.
8706	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8707	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8708	* during the operation.
8709	*
8710	* @param pDevIns The device instance.
8711	* @param pCritSect The critical section.
8712	* @param uId Some kind of locking location ID. Typically a
8713	* return address up the stack. Optional (0).
8714	* @param SRC_POS The source position where to lock is being
8715	* acquired from. Optional.
8716	* @sa PDMCritSectTryEnterDebug
8717	*/
8718	DECLINLINE(DECL_CHECK_RETURN(int))
8719	PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8720	{
8721	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8722	}
8723
8724	/**
8725	* Leaves a critical section entered with PDMCritSectEnter().
8726	*
8727	* @returns Indication whether we really exited the critical section.
8728	* @retval VINF_SUCCESS if we really exited.
8729	* @retval VINF_SEM_NESTED if we only reduced the nesting count.
8730	* @retval VERR_NOT_OWNER if you somehow ignore release assertions.
8731	*
8732	* @param pDevIns The device instance.
8733	* @param pCritSect The PDM critical section to leave.
8734	* @sa PDMCritSectLeave
8735	*/
8736	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8737	{
8738	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
8739	}
8740
8741	/**
8742	* @see PDMCritSectIsOwner
8743	*/
8744	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8745	{
8746	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
8747	}
8748
8749	/**
8750	* @see PDMCritSectIsInitialized
8751	*/
8752	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8753	{
8754	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
8755	}
8756
8757	/**
8758	* @see PDMCritSectHasWaiters
8759	*/
8760	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8761	{
8762	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
8763	}
8764
8765	/**
8766	* @see PDMCritSectGetRecursion
8767	*/
8768	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8769	{
8770	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
8771	}
8772
8773	#if defined(IN_RING3) \|\| defined(IN_RING0)
8774	/**
8775	* @see PDMHCCritSectScheduleExitEvent
8776	*/
8777	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
8778	{
8779	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
8780	}
8781	#endif
8782
8783	/* Strict build: Remap the two enter calls to the debug versions. */
8784	#ifdef VBOX_STRICT
8785	# ifdef IPRT_INCLUDED_asm_h
8786	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8787	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8788	# else
8789	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8790	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8791	# endif
8792	#endif
8793
8794	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8795
8796	/**
8797	* Deletes the critical section.
8798	*
8799	* @returns VBox status code.
8800	* @param pDevIns The device instance.
8801	* @param pCritSect The PDM critical section to destroy.
8802	* @sa PDMR3CritSectDelete
8803	*/
8804	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8805	{
8806	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8807	}
8808
8809	/**
8810	* Initializes a PDM read/write critical section.
8811	*
8812	* The PDM read/write critical sections are derived from the IPRT critical
8813	* sections, but works in RC and R0 as well.
8814	*
8815	* @returns VBox status code.
8816	* @param pDevIns The device instance.
8817	* @param pCritSect Pointer to the read/write critical section.
8818	* @param SRC_POS Use RT_SRC_POS.
8819	* @param pszNameFmt Format string for naming the critical section.
8820	* For statistics and lock validation.
8821	* @param ... Arguments for the format string.
8822	*/
8823	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
8824	const char *pszNameFmt, ...)
8825	{
8826	int rc;
8827	va_list va;
8828	va_start(va, pszNameFmt);
8829	rc = pDevIns->pHlpR3->pfnCritSectRwInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8830	va_end(va);
8831	return rc;
8832	}
8833
8834	/**
8835	* Deletes the read/write critical section.
8836	*
8837	* @returns VBox status code.
8838	* @param pDevIns The device instance.
8839	* @param pCritSect The PDM read/write critical section to destroy.
8840	* @sa PDMR3CritSectRwDelete
8841	*/
8842	DECLINLINE(int) PDMDevHlpCritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8843	{
8844	return pDevIns->pHlpR3->pfnCritSectRwDelete(pDevIns, pCritSect);
8845	}
8846
8847	#endif /* IN_RING3 */
8848
8849	/**
8850	* @sa PDMCritSectRwEnterShared, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8851	*/
8852	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8853	{
8854	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterShared(pDevIns, pCritSect, rcBusy);
8855	}
8856
8857	/**
8858	* @sa PDMCritSectRwEnterSharedDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8859	*/
8860	DECLINLINE(DECL_CHECK_RETURN(int))
8861	PDMDevHlpCritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8862	{
8863	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterSharedDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8864	}
8865
8866	/**
8867	* @sa PDMCritSectRwTryEnterShared
8868	*/
8869	DECLINLINE(DECL_CHECK_RETURN(int))
8870	PDMDevHlpCritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8871	{
8872	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterShared(pDevIns, pCritSect);
8873	}
8874
8875	/**
8876	* @sa PDMCritSectRwTryEnterSharedDebug
8877	*/
8878	DECLINLINE(DECL_CHECK_RETURN(int))
8879	PDMDevHlpCritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8880	{
8881	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterSharedDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8882	}
8883
8884	/**
8885	* @sa PDMCritSectRwLeaveShared
8886	*/
8887	DECLINLINE(int) PDMDevHlpCritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8888	{
8889	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveShared(pDevIns, pCritSect);
8890	}
8891
8892	/**
8893	* @sa PDMCritSectRwEnterExcl, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8894	*/
8895	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8896	{
8897	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy);
8898	}
8899
8900	/**
8901	* @sa PDMCritSectRwEnterExclDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8902	*/
8903	DECLINLINE(DECL_CHECK_RETURN(int))
8904	PDMDevHlpCritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8905	{
8906	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExclDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8907	}
8908
8909	/**
8910	* @sa PDMCritSectRwTryEnterExcl
8911	*/
8912	DECLINLINE(DECL_CHECK_RETURN(int))
8913	PDMDevHlpCritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8914	{
8915	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExcl(pDevIns, pCritSect);
8916	}
8917
8918	/**
8919	* @sa PDMCritSectRwTryEnterExclDebug
8920	*/
8921	DECLINLINE(DECL_CHECK_RETURN(int))
8922	PDMDevHlpCritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8923	{
8924	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExclDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8925	}
8926
8927	/**
8928	* @sa PDMCritSectRwLeaveExcl
8929	*/
8930	DECLINLINE(int) PDMDevHlpCritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8931	{
8932	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveExcl(pDevIns, pCritSect);
8933	}
8934
8935	/**
8936	* @see PDMCritSectRwIsWriteOwner
8937	*/
8938	DECLINLINE(bool) PDMDevHlpCritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8939	{
8940	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsWriteOwner(pDevIns, pCritSect);
8941	}
8942
8943	/**
8944	* @see PDMCritSectRwIsReadOwner
8945	*/
8946	DECLINLINE(bool) PDMDevHlpCritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
8947	{
8948	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsReadOwner(pDevIns, pCritSect, fWannaHear);
8949	}
8950
8951	/**
8952	* @see PDMCritSectRwGetWriteRecursion
8953	*/
8954	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8955	{
8956	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriteRecursion(pDevIns, pCritSect);
8957	}
8958
8959	/**
8960	* @see PDMCritSectRwGetWriterReadRecursion
8961	*/
8962	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8963	{
8964	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriterReadRecursion(pDevIns, pCritSect);
8965	}
8966
8967	/**
8968	* @see PDMCritSectRwGetReadCount
8969	*/
8970	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8971	{
8972	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetReadCount(pDevIns, pCritSect);
8973	}
8974
8975	/**
8976	* @see PDMCritSectRwIsInitialized
8977	*/
8978	DECLINLINE(bool) PDMDevHlpCritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8979	{
8980	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsInitialized(pDevIns, pCritSect);
8981	}
8982
8983	/* Strict build: Remap the two enter calls to the debug versions. */
8984	#ifdef VBOX_STRICT
8985	# ifdef IPRT_INCLUDED_asm_h
8986	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8987	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8988	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8989	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8990	# else
8991	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8992	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8993	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8994	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8995	# endif
8996	#endif
8997
8998	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8999
9000	/**
9001	* @copydoc PDMDEVHLPR3::pfnThreadCreate
9002	*/
9003	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
9004	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
9005	{
9006	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
9007	}
9008
9009	/**
9010	* @copydoc PDMR3ThreadDestroy
9011	* @param pDevIns The device instance.
9012	*/
9013	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
9014	{
9015	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
9016	}
9017
9018	/**
9019	* @copydoc PDMR3ThreadIAmSuspending
9020	* @param pDevIns The device instance.
9021	*/
9022	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9023	{
9024	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
9025	}
9026
9027	/**
9028	* @copydoc PDMR3ThreadIAmRunning
9029	* @param pDevIns The device instance.
9030	*/
9031	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9032	{
9033	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
9034	}
9035
9036	/**
9037	* @copydoc PDMR3ThreadSleep
9038	* @param pDevIns The device instance.
9039	*/
9040	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
9041	{
9042	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
9043	}
9044
9045	/**
9046	* @copydoc PDMR3ThreadSuspend
9047	* @param pDevIns The device instance.
9048	*/
9049	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9050	{
9051	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
9052	}
9053
9054	/**
9055	* @copydoc PDMR3ThreadResume
9056	* @param pDevIns The device instance.
9057	*/
9058	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9059	{
9060	return pDevIns->pHlpR3->pfnThreadResume(pThread);
9061	}
9062
9063	/**
9064	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
9065	*/
9066	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
9067	{
9068	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
9069	}
9070
9071	/**
9072	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
9073	*/
9074	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
9075	{
9076	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
9077	}
9078
9079	/**
9080	* @copydoc PDMDEVHLPR3::pfnA20Set
9081	*/
9082	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
9083	{
9084	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
9085	}
9086
9087	/**
9088	* @copydoc PDMDEVHLPR3::pfnRTCRegister
9089	*/
9090	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
9091	{
9092	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
9093	}
9094
9095	/**
9096	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
9097	*/
9098	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
9099	{
9100	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
9101	}
9102
9103	/**
9104	* @copydoc PDMDEVHLPR3::pfnIommuRegister
9105	*/
9106	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
9107	{
9108	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
9109	}
9110
9111	/**
9112	* @copydoc PDMDEVHLPR3::pfnPICRegister
9113	*/
9114	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
9115	{
9116	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
9117	}
9118
9119	/**
9120	* @copydoc PDMDEVHLPR3::pfnApicRegister
9121	*/
9122	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
9123	{
9124	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
9125	}
9126
9127	/**
9128	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
9129	*/
9130	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9131	{
9132	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
9133	}
9134
9135	/**
9136	* @copydoc PDMDEVHLPR3::pfnHpetRegister
9137	*/
9138	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
9139	{
9140	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
9141	}
9142
9143	/**
9144	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
9145	*/
9146	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
9147	{
9148	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
9149	}
9150
9151	/**
9152	* @copydoc PDMDEVHLPR3::pfnDMACRegister
9153	*/
9154	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
9155	{
9156	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
9157	}
9158
9159	/**
9160	* @copydoc PDMDEVHLPR3::pfnDMARegister
9161	*/
9162	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
9163	{
9164	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
9165	}
9166
9167	/**
9168	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
9169	*/
9170	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
9171	{
9172	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
9173	}
9174
9175	/**
9176	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
9177	*/
9178	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
9179	{
9180	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
9181	}
9182
9183	/**
9184	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
9185	*/
9186	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
9187	{
9188	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
9189	}
9190
9191	/**
9192	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
9193	*/
9194	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
9195	{
9196	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
9197	}
9198
9199	/**
9200	* @copydoc PDMDEVHLPR3::pfnDMASchedule
9201	*/
9202	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
9203	{
9204	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
9205	}
9206
9207	/**
9208	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
9209	*/
9210	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
9211	{
9212	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
9213	}
9214
9215	/**
9216	* @copydoc PDMDEVHLPR3::pfnCMOSRead
9217	*/
9218	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
9219	{
9220	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
9221	}
9222
9223	/**
9224	* @copydoc PDMDEVHLPR3::pfnCallR0
9225	*/
9226	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
9227	{
9228	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
9229	}
9230
9231	/**
9232	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
9233	*/
9234	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
9235	{
9236	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
9237	}
9238
9239	/**
9240	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
9241	*/
9242	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
9243	{
9244	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
9245	}
9246
9247	/**
9248	* @copydoc PDMDEVHLPR3::pfnGetUVM
9249	*/
9250	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
9251	{
9252	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
9253	}
9254
9255	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
9256
9257	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
9258
9259	/**
9260	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
9261	*/
9262	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
9263	{
9264	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
9265	}
9266
9267	/**
9268	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
9269	*/
9270	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
9271	{
9272	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
9273	}
9274
9275	/**
9276	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
9277	*/
9278	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
9279	{
9280	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
9281	}
9282
9283	/**
9284	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
9285	*/
9286	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
9287	{
9288	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
9289	}
9290
9291	/**
9292	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
9293	*/
9294	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9295	{
9296	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
9297	}
9298
9299	/**
9300	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
9301	*/
9302	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
9303	{
9304	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
9305	}
9306
9307	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
9308
9309	/**
9310	* @copydoc PDMDEVHLPR3::pfnGetVM
9311	*/
9312	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
9313	{
9314	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
9315	}
9316
9317	/**
9318	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
9319	*/
9320	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
9321	{
9322	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
9323	}
9324
9325	/**
9326	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
9327	*/
9328	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
9329	{
9330	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
9331	}
9332
9333	/**
9334	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
9335	*/
9336	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
9337	{
9338	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
9339	}
9340
9341	/**
9342	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9343	*/
9344	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
9345	{
9346	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
9347	}
9348
9349	/**
9350	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9351	*/
9352	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
9353	{
9354	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
9355	}
9356
9357	#ifdef IN_RING3
9358	/**
9359	* @copydoc PDMDEVHLPR3::pfnTMCpuTicksPerSecond
9360	*/
9361	DECLINLINE(uint64_t) PDMDevHlpTMCpuTicksPerSecond(PPDMDEVINS pDevIns)
9362	{
9363	return pDevIns->CTX_SUFF(pHlp)->pfnTMCpuTicksPerSecond(pDevIns);
9364	}
9365
9366	/**
9367	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
9368	*/
9369	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
9370	{
9371	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
9372	}
9373
9374	/**
9375	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
9376	*/
9377	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
9378	{
9379	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
9380	}
9381
9382	/**
9383	* @copydoc PDMDEVHLPR3::pfnVMReset
9384	*/
9385	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
9386	{
9387	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
9388	}
9389
9390	/**
9391	* @copydoc PDMDEVHLPR3::pfnVMSuspend
9392	*/
9393	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
9394	{
9395	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
9396	}
9397
9398	/**
9399	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
9400	*/
9401	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
9402	{
9403	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
9404	}
9405
9406	/**
9407	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
9408	*/
9409	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
9410	{
9411	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
9412	}
9413
9414	#endif /* IN_RING3 */
9415
9416	/**
9417	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
9418	*/
9419	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
9420	{
9421	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
9422	}
9423
9424	#ifdef IN_RING3
9425	/**
9426	* @copydoc PDMDEVHLPR3::pfnGetCpuId
9427	*/
9428	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
9429	{
9430	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
9431	}
9432	#endif
9433
9434	/**
9435	* @copydoc PDMDEVHLPR3::pfnGetMainExecutionEngine
9436	*/
9437	DECLINLINE(uint8_t) PDMDevHlpGetMainExecutionEngine(PPDMDEVINS pDevIns)
9438	{
9439	return pDevIns->CTX_SUFF(pHlp)->pfnGetMainExecutionEngine(pDevIns);
9440	}
9441
9442	#ifdef IN_RING3
9443
9444	/**
9445	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
9446	*/
9447	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
9448	{
9449	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
9450	}
9451
9452	/**
9453	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
9454	*/
9455	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
9456	{
9457	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
9458	}
9459
9460	/**
9461	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
9462	*/
9463	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
9464	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
9465	const char pszHandlerR0, const char pszPfHandlerR0,
9466	const char pszHandlerRC, const char pszPfHandlerRC,
9467	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
9468	{
9469	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
9470	pszHandlerR0, pszPfHandlerR0,
9471	pszHandlerRC, pszPfHandlerRC,
9472	pszDesc, phType);
9473	}
9474
9475	/**
9476	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalRegister
9477	*/
9478	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
9479	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
9480	RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc)
9481	{
9482	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalRegister(pDevIns, GCPhys, GCPhysLast, hType,
9483	pvUserR3, pvUserR0, pvUserRC, pszDesc);
9484	}
9485
9486	/**
9487	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalDeregister
9488	*/
9489	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalDeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9490	{
9491	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalDeregister(pDevIns, GCPhys);
9492	}
9493	#endif
9494
9495	/**
9496	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalPageTempOff
9497	*/
9498	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
9499	{
9500	return pDevIns->CTX_SUFF(pHlp)->pfnPGMHandlerPhysicalPageTempOff(pDevIns, GCPhys, GCPhysPage);
9501	}
9502
9503	#ifdef IN_RING3
9504	/**
9505	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalReset
9506	*/
9507	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalReset(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9508	{
9509	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalReset(pDevIns, GCPhys);
9510	}
9511
9512	/**
9513	* @copydoc PDMDEVHLPR3::pfnVMMRegisterPatchMemory
9514	*/
9515	DECLINLINE(int) PDMDevHlpVMMRegisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9516	{
9517	return pDevIns->pHlpR3->pfnVMMRegisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9518	}
9519
9520	/**
9521	* @copydoc PDMDEVHLPR3::pfnVMMDeregisterPatchMemory
9522	*/
9523	DECLINLINE(int) PDMDevHlpVMMDeregisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9524	{
9525	return pDevIns->pHlpR3->pfnVMMDeregisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9526	}
9527
9528	/**
9529	* @copydoc PDMDEVHLPR3::pfnSharedModuleRegister
9530	*/
9531	DECLINLINE(int) PDMDevHlpSharedModuleRegister(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
9532	RTGCPTR GCBaseAddr, uint32_t cbModule,
9533	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions)
9534	{
9535	return pDevIns->pHlpR3->pfnSharedModuleRegister(pDevIns, enmGuestOS, pszModuleName, pszVersion,
9536	GCBaseAddr, cbModule, cRegions, paRegions);
9537	}
9538
9539	/**
9540	* @copydoc PDMDEVHLPR3::pfnSharedModuleUnregister
9541	*/
9542	DECLINLINE(int) PDMDevHlpSharedModuleUnregister(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
9543	RTGCPTR GCBaseAddr, uint32_t cbModule)
9544	{
9545	return pDevIns->pHlpR3->pfnSharedModuleUnregister(pDevIns, pszModuleName, pszVersion, GCBaseAddr, cbModule);
9546	}
9547
9548	/**
9549	* @copydoc PDMDEVHLPR3::pfnSharedModuleGetPageState
9550	*/
9551	DECLINLINE(int) PDMDevHlpSharedModuleGetPageState(PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool *pfShared,
9552	uint64_t *pfPageFlags)
9553	{
9554	return pDevIns->pHlpR3->pfnSharedModuleGetPageState(pDevIns, GCPtrPage, pfShared, pfPageFlags);
9555	}
9556
9557	/**
9558	* @copydoc PDMDEVHLPR3::pfnSharedModuleCheckAll
9559	*/
9560	DECLINLINE(int) PDMDevHlpSharedModuleCheckAll(PPDMDEVINS pDevIns)
9561	{
9562	return pDevIns->pHlpR3->pfnSharedModuleCheckAll(pDevIns);
9563	}
9564
9565	/**
9566	* @copydoc PDMDEVHLPR3::pfnQueryLun
9567	*/
9568	DECLINLINE(int) PDMDevHlpQueryLun(PPDMDEVINS pDevIns, const char pszDevice, unsigned iInstance, unsigned iLun, PPDMIBASE ppBase)
9569	{
9570	return pDevIns->pHlpR3->pfnQueryLun(pDevIns, pszDevice, iInstance, iLun, ppBase);
9571	}
9572
9573	/**
9574	* @copydoc PDMDEVHLPR3::pfnGIMDeviceRegister
9575	*/
9576	DECLINLINE(void) PDMDevHlpGIMDeviceRegister(PPDMDEVINS pDevIns, PGIMDEBUG pDbg)
9577	{
9578	pDevIns->pHlpR3->pfnGIMDeviceRegister(pDevIns, pDbg);
9579	}
9580
9581	/**
9582	* @copydoc PDMDEVHLPR3::pfnGIMGetDebugSetup
9583	*/
9584	DECLINLINE(int) PDMDevHlpGIMGetDebugSetup(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup)
9585	{
9586	return pDevIns->pHlpR3->pfnGIMGetDebugSetup(pDevIns, pDbgSetup);
9587	}
9588	#endif
9589
9590	/**
9591	* @copydoc PDMDEVHLPR3::pfnGIMGetMmio2Regions
9592	*/
9593	DECLINLINE(PGIMMMIO2REGION) PDMDevHlpGIMGetMmio2Regions(PPDMDEVINS pDevIns, uint32_t *pcRegions)
9594	{
9595	return pDevIns->CTX_SUFF(pHlp)->pfnGIMGetMmio2Regions(pDevIns, pcRegions);
9596	}
9597
9598	#ifdef IN_RING3
9599	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
9600	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9601	do { \
9602	uint32_t u32GetEnumTmp = 0; \
9603	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
9604	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9605	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
9606	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
9607	} while (0)
9608
9609	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
9610	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9611	do { \
9612	uint8_t bGetEnumTmp = 0; \
9613	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
9614	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9615	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
9616	} while (0)
9617
9618	#endif /* IN_RING3 */
9619
9620	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
9621	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
9622
9623	/**
9624	* Callbacks for VBoxDeviceRegister().
9625	*/
9626	typedef struct PDMDEVREGCB
9627	{
9628	/** Interface version.
9629	* This is set to PDM_DEVREG_CB_VERSION. */
9630	uint32_t u32Version;
9631
9632	/**
9633	* Registers a device with the current VM instance.
9634	*
9635	* @returns VBox status code.
9636	* @param pCallbacks Pointer to the callback table.
9637	* @param pReg Pointer to the device registration record.
9638	* This data must be permanent and readonly.
9639	*/
9640	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
9641	} PDMDEVREGCB;
9642
9643	/** Current version of the PDMDEVREGCB structure. */
9644	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
9645
9646
9647	/**
9648	* The VBoxDevicesRegister callback function.
9649	*
9650	* PDM will invoke this function after loading a device module and letting
9651	* the module decide which devices to register and how to handle conflicts.
9652	*
9653	* @returns VBox status code.
9654	* @param pCallbacks Pointer to the callback table.
9655	* @param u32Version VBox version number.
9656	*/
9657	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
9658
9659	/** @} */
9660
9661	RT_C_DECLS_END
9662
9663	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 92843

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