pdmdev.h@ 98103

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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
37	#define VBOX_INCLUDED_vmm_pdmdev_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmcritsectrw.h>
44	#include <VBox/vmm/pdmqueue.h>
45	#include <VBox/vmm/pdmtask.h>
46	#ifdef IN_RING3
47	# include <VBox/vmm/pdmthread.h>
48	#endif
49	#include <VBox/vmm/pdmifs.h>
50	#include <VBox/vmm/pdmins.h>
51	#include <VBox/vmm/pdmcommon.h>
52	#include <VBox/vmm/pdmpcidev.h>
53	#include <VBox/vmm/iom.h>
54	#include <VBox/vmm/mm.h>
55	#include <VBox/vmm/tm.h>
56	#include <VBox/vmm/ssm.h>
57	#include <VBox/vmm/cfgm.h>
58	#include <VBox/vmm/cpum.h>
59	#include <VBox/vmm/dbgf.h>
60	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
61	#include <VBox/vmm/gim.h>
62	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
63	#include <VBox/msi.h>
64	#include <iprt/stdarg.h>
65	#include <iprt/list.h>
66
67
68	RT_C_DECLS_BEGIN
69
70	/** @defgroup grp_pdm_device The PDM Devices API
71	* @ingroup grp_pdm
72	* @{
73	*/
74
75	/**
76	* Construct a device instance for a VM.
77	*
78	* @returns VBox status.
79	* @param pDevIns The device instance data. If the registration structure
80	* is needed, it can be accessed thru pDevIns->pReg.
81	* @param iInstance Instance number. Use this to figure out which registers
82	* and such to use. The instance number is also found in
83	* pDevIns->iInstance, but since it's likely to be
84	* frequently used PDM passes it as parameter.
85	* @param pCfg Configuration node handle for the driver. This is
86	* expected to be in high demand in the constructor and is
87	* therefore passed as an argument. When using it at other
88	* times, it can be found in pDevIns->pCfg.
89	*/
90	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
91	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
92	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
93
94	/**
95	* Destruct a device instance.
96	*
97	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
98	* resources can be freed correctly.
99	*
100	* @returns VBox status.
101	* @param pDevIns The device instance data.
102	*
103	* @remarks The device critical section is not entered. The routine may delete
104	* the critical section, so the caller cannot exit it.
105	*/
106	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
107	/** Pointer to a FNPDMDEVDESTRUCT() function. */
108	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
109
110	/**
111	* Device relocation callback.
112	*
113	* This is called when the instance data has been relocated in raw-mode context
114	* (RC). It is also called when the RC hypervisor selects changes. The device
115	* must fixup all necessary pointers and re-query all interfaces to other RC
116	* devices and drivers.
117	*
118	* Before the RC code is executed the first time, this function will be called
119	* with a 0 delta so RC pointer calculations can be one in one place.
120	*
121	* @param pDevIns Pointer to the device instance.
122	* @param offDelta The relocation delta relative to the old location.
123	*
124	* @remarks A relocation CANNOT fail.
125	*
126	* @remarks The device critical section is not entered. The relocations should
127	* not normally require any locking.
128	*/
129	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
130	/** Pointer to a FNPDMDEVRELOCATE() function. */
131	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
132
133	/**
134	* Power On notification.
135	*
136	* @returns VBox status.
137	* @param pDevIns The device instance data.
138	*
139	* @remarks Caller enters the device critical section.
140	*/
141	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
142	/** Pointer to a FNPDMDEVPOWERON() function. */
143	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
144
145	/**
146	* Reset notification.
147	*
148	* @returns VBox status.
149	* @param pDevIns The device instance data.
150	*
151	* @remarks Caller enters the device critical section.
152	*/
153	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
154	/** Pointer to a FNPDMDEVRESET() function. */
155	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
156
157	/**
158	* Soft reset notification.
159	*
160	* This is mainly for emulating the 286 style protected mode exits, in which
161	* most devices should remain in their current state.
162	*
163	* @returns VBox status.
164	* @param pDevIns The device instance data.
165	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
166	*
167	* @remarks Caller enters the device critical section.
168	*/
169	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
170	/** Pointer to a FNPDMDEVSOFTRESET() function. */
171	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
172
173	/** @name PDMVMRESET_F_XXX - VM reset flags.
174	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
175	* reset via PDMDevHlpVMReset.
176	* @{ */
177	/** Unknown reason. */
178	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
179	/** GIM triggered reset. */
180	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
181	/** The last source always causing hard resets. */
182	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
183	/** ACPI triggered reset. */
184	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
185	/** PS/2 system port A (92h) reset. */
186	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
187	/** Keyboard reset. */
188	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
189	/** Tripple fault. */
190	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
191	/** Reset source mask. */
192	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
193	/** @} */
194
195	/**
196	* Suspend notification.
197	*
198	* @returns VBox status.
199	* @param pDevIns The device instance data.
200	* @thread EMT(0)
201	*
202	* @remarks Caller enters the device critical section.
203	*/
204	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
205	/** Pointer to a FNPDMDEVSUSPEND() function. */
206	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
207
208	/**
209	* Resume notification.
210	*
211	* @returns VBox status.
212	* @param pDevIns The device instance data.
213	*
214	* @remarks Caller enters the device critical section.
215	*/
216	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
217	/** Pointer to a FNPDMDEVRESUME() function. */
218	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
219
220	/**
221	* Power Off notification.
222	*
223	* This is always called when VMR3PowerOff is called.
224	* There will be no callback when hot plugging devices.
225	*
226	* @param pDevIns The device instance data.
227	* @thread EMT(0)
228	*
229	* @remarks Caller enters the device critical section.
230	*/
231	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
232	/** Pointer to a FNPDMDEVPOWEROFF() function. */
233	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
234
235	/**
236	* Attach command.
237	*
238	* This is called to let the device attach to a driver for a specified LUN
239	* at runtime. This is not called during VM construction, the device
240	* constructor has to attach to all the available drivers.
241	*
242	* This is like plugging in the keyboard or mouse after turning on the PC.
243	*
244	* @returns VBox status code.
245	* @param pDevIns The device instance.
246	* @param iLUN The logical unit which is being attached.
247	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
248	*
249	* @remarks Caller enters the device critical section.
250	*/
251	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
252	/** Pointer to a FNPDMDEVATTACH() function. */
253	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
254
255	/**
256	* Detach notification.
257	*
258	* This is called when a driver is detaching itself from a LUN of the device.
259	* The device should adjust its state to reflect this.
260	*
261	* This is like unplugging the network cable to use it for the laptop or
262	* something while the PC is still running.
263	*
264	* @param pDevIns The device instance.
265	* @param iLUN The logical unit which is being detached.
266	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
267	*
268	* @remarks Caller enters the device critical section.
269	*/
270	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
271	/** Pointer to a FNPDMDEVDETACH() function. */
272	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
273
274	/**
275	* Query the base interface of a logical unit.
276	*
277	* @returns VBOX status code.
278	* @param pDevIns The device instance.
279	* @param iLUN The logicial unit to query.
280	* @param ppBase Where to store the pointer to the base interface of the LUN.
281	*
282	* @remarks The device critical section is not entered.
283	*/
284	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
285	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
286	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
287
288	/**
289	* Init complete notification (after ring-0 & RC init since 5.1).
290	*
291	* This can be done to do communication with other devices and other
292	* initialization which requires everything to be in place.
293	*
294	* @returns VBOX status code.
295	* @param pDevIns The device instance.
296	*
297	* @remarks Caller enters the device critical section.
298	*/
299	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
300	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
301	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
302
303
304	/**
305	* The context of a pfnMemSetup call.
306	*/
307	typedef enum PDMDEVMEMSETUPCTX
308	{
309	/** Invalid zero value. */
310	PDMDEVMEMSETUPCTX_INVALID = 0,
311	/** After construction. */
312	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
313	/** After reset. */
314	PDMDEVMEMSETUPCTX_AFTER_RESET,
315	/** Type size hack. */
316	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
317	} PDMDEVMEMSETUPCTX;
318
319
320	/**
321	* PDM Device Registration Structure.
322	*
323	* This structure is used when registering a device from VBoxInitDevices() in HC
324	* Ring-3. PDM will continue use till the VM is terminated.
325	*
326	* @note The first part is the same in every context.
327	*/
328	typedef struct PDMDEVREGR3
329	{
330	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
331	uint32_t u32Version;
332	/** Reserved, must be zero. */
333	uint32_t uReserved0;
334	/** Device name, must match the ring-3 one. */
335	char szName[32];
336	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
337	uint32_t fFlags;
338	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
339	uint32_t fClass;
340	/** Maximum number of instances (per VM). */
341	uint32_t cMaxInstances;
342	/** The shared data structure version number. */
343	uint32_t uSharedVersion;
344	/** Size of the instance data. */
345	uint32_t cbInstanceShared;
346	/** Size of the ring-0 instance data. */
347	uint32_t cbInstanceCC;
348	/** Size of the raw-mode instance data. */
349	uint32_t cbInstanceRC;
350	/** Max number of PCI devices. */
351	uint16_t cMaxPciDevices;
352	/** Max number of MSI-X vectors in any of the PCI devices. */
353	uint16_t cMaxMsixVectors;
354	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
355	* remain unchanged from registration till VM destruction. */
356	const char *pszDescription;
357
358	/** Name of the raw-mode context module (no path).
359	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
360	const char *pszRCMod;
361	/** Name of the ring-0 module (no path).
362	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
363	const char *pszR0Mod;
364
365	/** Construct instance - required. */
366	PFNPDMDEVCONSTRUCT pfnConstruct;
367	/** Destruct instance - optional.
368	* Critical section NOT entered (will be destroyed). */
369	PFNPDMDEVDESTRUCT pfnDestruct;
370	/** Relocation command - optional.
371	* Critical section NOT entered. */
372	PFNPDMDEVRELOCATE pfnRelocate;
373	/**
374	* Memory setup callback.
375	*
376	* @param pDevIns The device instance data.
377	* @param enmCtx Indicates the context of the call.
378	* @remarks The critical section is entered prior to calling this method.
379	*/
380	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
381	/** Power on notification - optional.
382	* Critical section is entered. */
383	PFNPDMDEVPOWERON pfnPowerOn;
384	/** Reset notification - optional.
385	* Critical section is entered. */
386	PFNPDMDEVRESET pfnReset;
387	/** Suspend notification - optional.
388	* Critical section is entered. */
389	PFNPDMDEVSUSPEND pfnSuspend;
390	/** Resume notification - optional.
391	* Critical section is entered. */
392	PFNPDMDEVRESUME pfnResume;
393	/** Attach command - optional.
394	* Critical section is entered. */
395	PFNPDMDEVATTACH pfnAttach;
396	/** Detach notification - optional.
397	* Critical section is entered. */
398	PFNPDMDEVDETACH pfnDetach;
399	/** Query a LUN base interface - optional.
400	* Critical section is NOT entered. */
401	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
402	/** Init complete notification - optional.
403	* Critical section is entered. */
404	PFNPDMDEVINITCOMPLETE pfnInitComplete;
405	/** Power off notification - optional.
406	* Critical section is entered. */
407	PFNPDMDEVPOWEROFF pfnPowerOff;
408	/** Software system reset notification - optional.
409	* Critical section is entered. */
410	PFNPDMDEVSOFTRESET pfnSoftReset;
411
412	/** @name Reserved for future extensions, must be zero.
413	* @{ */
414	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
415	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
416	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
417	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
418	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
419	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
420	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
421	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
422	/** @} */
423
424	/** Initialization safty marker. */
425	uint32_t u32VersionEnd;
426	} PDMDEVREGR3;
427	/** Pointer to a PDM Device Structure. */
428	typedef PDMDEVREGR3 *PPDMDEVREGR3;
429	/** Const pointer to a PDM Device Structure. */
430	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
431	/** Current DEVREGR3 version number. */
432	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
433
434
435	/** PDM Device Flags.
436	* @{ */
437	/** This flag is used to indicate that the device has a R0 component. */
438	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
439	/** Requires the ring-0 component, ignore configuration values. */
440	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
441	/** Requires the ring-0 component, ignore configuration values. */
442	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
443
444	/** This flag is used to indicate that the device has a RC component. */
445	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
446	/** Requires the raw-mode component, ignore configuration values. */
447	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
448	/** Requires the raw-mode component, ignore configuration values. */
449	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
450
451	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
452	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
453
454	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
455	* The bit count for the current host.
456	* @note Superfluous, but still around for hysterical raisins. */
457	#if HC_ARCH_BITS == 32
458	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
459	#elif HC_ARCH_BITS == 64
460	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
461	#else
462	# error Unsupported HC_ARCH_BITS value.
463	#endif
464	/** The host bit count mask. */
465	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
466
467	/** The device support only 32-bit guests. */
468	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
469	/** The device support only 64-bit guests. */
470	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
471	/** The device support both 32-bit & 64-bit guests. */
472	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
473	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
474	* The guest bit count for the current compilation. */
475	#if GC_ARCH_BITS == 32
476	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
477	#elif GC_ARCH_BITS == 64
478	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
479	#else
480	# error Unsupported GC_ARCH_BITS value.
481	#endif
482	/** The guest bit count mask. */
483	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
484
485	/** A convenience. */
486	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
487
488	/** Indicates that the device needs to be notified before the drivers when suspending. */
489	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
490	/** Indicates that the device needs to be notified before the drivers when powering off. */
491	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
492	/** Indicates that the device needs to be notified before the drivers when resetting. */
493	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
494
495	/** This flag is used to indicate that the device has been converted to the
496	* new device style. */
497	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
498
499	/** @} */
500
501
502	/** PDM Device Classes.
503	* The order is important, lower bit earlier instantiation.
504	* @{ */
505	/** Architecture device. */
506	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
507	/** Architecture BIOS device. */
508	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
509	/** PCI bus brigde. */
510	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
511	/** PCI built-in device (e.g. PCI root complex devices). */
512	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
513	/** Input device (mouse, keyboard, joystick, HID, ...). */
514	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
515	/** Interrupt controller (PIC). */
516	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
517	/** Interval controoler (PIT). */
518	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
519	/** RTC/CMOS. */
520	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
521	/** DMA controller. */
522	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
523	/** VMM Device. */
524	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
525	/** Graphics device, like VGA. */
526	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
527	/** Storage controller device. */
528	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
529	/** Network interface controller. */
530	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
531	/** Audio. */
532	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
533	/** USB HIC. */
534	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
535	/** ACPI. */
536	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
537	/** Serial controller device. */
538	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
539	/** Parallel controller device */
540	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
541	/** Host PCI pass-through device */
542	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
543	/** Misc devices (always last). */
544	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
545	/** @} */
546
547
548	/**
549	* PDM Device Registration Structure, ring-0.
550	*
551	* This structure is used when registering a device from VBoxInitDevices() in HC
552	* Ring-0. PDM will continue use till the VM is terminated.
553	*/
554	typedef struct PDMDEVREGR0
555	{
556	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
557	uint32_t u32Version;
558	/** Reserved, must be zero. */
559	uint32_t uReserved0;
560	/** Device name, must match the ring-3 one. */
561	char szName[32];
562	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
563	uint32_t fFlags;
564	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
565	uint32_t fClass;
566	/** Maximum number of instances (per VM). */
567	uint32_t cMaxInstances;
568	/** The shared data structure version number. */
569	uint32_t uSharedVersion;
570	/** Size of the instance data. */
571	uint32_t cbInstanceShared;
572	/** Size of the ring-0 instance data. */
573	uint32_t cbInstanceCC;
574	/** Size of the raw-mode instance data. */
575	uint32_t cbInstanceRC;
576	/** Max number of PCI devices. */
577	uint16_t cMaxPciDevices;
578	/** Max number of MSI-X vectors in any of the PCI devices. */
579	uint16_t cMaxMsixVectors;
580	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
581	* remain unchanged from registration till VM destruction. */
582	const char *pszDescription;
583
584	/**
585	* Early construction callback (optional).
586	*
587	* This is called right after the device instance structure has been allocated
588	* and before the ring-3 constructor gets called.
589	*
590	* @returns VBox status code.
591	* @param pDevIns The device instance data.
592	* @note The destructure is always called, regardless of the return status.
593	*/
594	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
595
596	/**
597	* Regular construction callback (optional).
598	*
599	* This is called after (or during) the ring-3 constructor.
600	*
601	* @returns VBox status code.
602	* @param pDevIns The device instance data.
603	* @note The destructure is always called, regardless of the return status.
604	*/
605	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
606
607	/**
608	* Destructor (optional).
609	*
610	* This is called after the ring-3 destruction. This is not called if ring-3
611	* fails to trigger it (e.g. process is killed or crashes).
612	*
613	* @param pDevIns The device instance data.
614	*/
615	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
616
617	/**
618	* Final destructor (optional).
619	*
620	* This is called right before the memory is freed, which happens when the
621	* VM/GVM object is destroyed. This is always called.
622	*
623	* @param pDevIns The device instance data.
624	*/
625	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
626
627	/**
628	* Generic request handler (optional).
629	*
630	* @param pDevIns The device instance data.
631	* @param uReq Device specific request.
632	* @param uArg Request argument.
633	*/
634	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
635
636	/** @name Reserved for future extensions, must be zero.
637	* @{ */
638	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
639	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
640	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
641	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
642	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
643	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
644	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
645	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
646	/** @} */
647
648	/** Initialization safty marker. */
649	uint32_t u32VersionEnd;
650	} PDMDEVREGR0;
651	/** Pointer to a ring-0 PDM device registration structure. */
652	typedef PDMDEVREGR0 *PPDMDEVREGR0;
653	/** Pointer to a const ring-0 PDM device registration structure. */
654	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
655	/** Current DEVREGR0 version number. */
656	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
657
658
659	/**
660	* PDM Device Registration Structure, raw-mode
661	*
662	* At the moment, this structure is mostly here to match the other two contexts.
663	*/
664	typedef struct PDMDEVREGRC
665	{
666	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
667	uint32_t u32Version;
668	/** Reserved, must be zero. */
669	uint32_t uReserved0;
670	/** Device name, must match the ring-3 one. */
671	char szName[32];
672	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
673	uint32_t fFlags;
674	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
675	uint32_t fClass;
676	/** Maximum number of instances (per VM). */
677	uint32_t cMaxInstances;
678	/** The shared data structure version number. */
679	uint32_t uSharedVersion;
680	/** Size of the instance data. */
681	uint32_t cbInstanceShared;
682	/** Size of the ring-0 instance data. */
683	uint32_t cbInstanceCC;
684	/** Size of the raw-mode instance data. */
685	uint32_t cbInstanceRC;
686	/** Max number of PCI devices. */
687	uint16_t cMaxPciDevices;
688	/** Max number of MSI-X vectors in any of the PCI devices. */
689	uint16_t cMaxMsixVectors;
690	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
691	* remain unchanged from registration till VM destruction. */
692	const char *pszDescription;
693
694	/**
695	* Constructor callback.
696	*
697	* This is called much later than both the ring-0 and ring-3 constructors, since
698	* raw-mode v2 require a working VMM to run actual code.
699	*
700	* @returns VBox status code.
701	* @param pDevIns The device instance data.
702	* @note The destructure is always called, regardless of the return status.
703	*/
704	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
705
706	/** @name Reserved for future extensions, must be zero.
707	* @{ */
708	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
709	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
710	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
711	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
712	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
713	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
714	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
715	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
716	/** @} */
717
718	/** Initialization safty marker. */
719	uint32_t u32VersionEnd;
720	} PDMDEVREGRC;
721	/** Pointer to a raw-mode PDM device registration structure. */
722	typedef PDMDEVREGRC *PPDMDEVREGRC;
723	/** Pointer to a const raw-mode PDM device registration structure. */
724	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
725	/** Current DEVREGRC version number. */
726	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
727
728
729
730	/** @def PDM_DEVREG_VERSION
731	* Current DEVREG version number. */
732	/** @typedef PDMDEVREGR3
733	* A current context PDM device registration structure. */
734	/** @typedef PPDMDEVREGR3
735	* Pointer to a current context PDM device registration structure. */
736	/** @typedef PCPDMDEVREGR3
737	* Pointer to a const current context PDM device registration structure. */
738	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
739	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
740	typedef PDMDEVREGR3 PDMDEVREG;
741	typedef PPDMDEVREGR3 PPDMDEVREG;
742	typedef PCPDMDEVREGR3 PCPDMDEVREG;
743	#elif defined(IN_RING0)
744	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
745	typedef PDMDEVREGR0 PDMDEVREG;
746	typedef PPDMDEVREGR0 PPDMDEVREG;
747	typedef PCPDMDEVREGR0 PCPDMDEVREG;
748	#elif defined(IN_RC)
749	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
750	typedef PDMDEVREGRC PDMDEVREG;
751	typedef PPDMDEVREGRC PPDMDEVREG;
752	typedef PCPDMDEVREGRC PCPDMDEVREG;
753	#else
754	# error "Not IN_RING3, IN_RING0 or IN_RC"
755	#endif
756
757
758	/**
759	* Device registrations for ring-0 modules.
760	*
761	* This structure is used directly and must therefore reside in persistent
762	* memory (i.e. the data section).
763	*/
764	typedef struct PDMDEVMODREGR0
765	{
766	/** The structure version (PDM_DEVMODREGR0_VERSION). */
767	uint32_t u32Version;
768	/** Number of devices in the array papDevRegs points to. */
769	uint32_t cDevRegs;
770	/** Pointer to device registration structures. */
771	PCPDMDEVREGR0 *papDevRegs;
772	/** The ring-0 module handle - PDM internal, fingers off. */
773	void *hMod;
774	/** List entry - PDM internal, fingers off. */
775	RTLISTNODE ListEntry;
776	} PDMDEVMODREGR0;
777	/** Pointer to device registriations for a ring-0 module. */
778	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
779	/** Current PDMDEVMODREGR0 version number. */
780	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
781
782
783	/** @name IRQ Level for use with the *SetIrq APIs.
784	* @{
785	*/
786	/** Assert the IRQ (can assume value 1). */
787	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
788	/** Deassert the IRQ (can assume value 0). */
789	#define PDM_IRQ_LEVEL_LOW 0
790	/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
791	* automatically deasserts it after delivery to the APIC (IOAPIC).
792	* @note Only suitable for edge trigger interrupts. */
793	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
794	/** @} */
795
796	/**
797	* Registration record for MSI/MSI-X emulation.
798	*/
799	typedef struct PDMMSIREG
800	{
801	/** Number of MSI interrupt vectors, 0 if MSI not supported */
802	uint16_t cMsiVectors;
803	/** Offset of MSI capability */
804	uint8_t iMsiCapOffset;
805	/** Offset of next capability to MSI */
806	uint8_t iMsiNextOffset;
807	/** If we support 64-bit MSI addressing */
808	bool fMsi64bit;
809	/** If we do not support per-vector masking */
810	bool fMsiNoMasking;
811
812	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
813	uint16_t cMsixVectors;
814	/** Offset of MSI-X capability */
815	uint8_t iMsixCapOffset;
816	/** Offset of next capability to MSI-X */
817	uint8_t iMsixNextOffset;
818	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
819	uint8_t iMsixBar;
820	} PDMMSIREG;
821	typedef PDMMSIREG *PPDMMSIREG;
822
823	/**
824	* PCI Bus registration structure.
825	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
826	*/
827	typedef struct PDMPCIBUSREGR3
828	{
829	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
830	uint32_t u32Version;
831
832	/**
833	* Registers the device with the default PCI bus.
834	*
835	* @returns VBox status code.
836	* @param pDevIns Device instance of the PCI Bus.
837	* @param pPciDev The PCI device structure.
838	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
839	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
840	* device number (0-31).
841	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
842	* function number (0-7).
843	* @param pszName Device name (static but not unique).
844	*
845	* @remarks Caller enters the PDM critical section.
846	*/
847	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
848	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
849
850	/**
851	* Initialize MSI or MSI-X emulation support in a PCI device.
852	*
853	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
854	* vast majority of device emulation it covers everything necessary. It's
855	* fully automatic, taking care of all BAR and config space requirements,
856	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
857	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
858	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
859	*
860	* A device not using this can still offer MSI/MSI-X. In this case it's
861	* completely up to the device (in the MSI-X case) to create/register the
862	* necessary MMIO BAR, handle all config space/BAR updating and take care
863	* of delivering the interrupts appropriately.
864	*
865	* @returns VBox status code.
866	* @param pDevIns Device instance of the PCI Bus.
867	* @param pPciDev The PCI device structure.
868	* @param pMsiReg MSI emulation registration structure
869	* @remarks Caller enters the PDM critical section.
870	*/
871	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
872
873	/**
874	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
875	*
876	* @returns VBox status code.
877	* @param pDevIns Device instance of the PCI Bus.
878	* @param pPciDev The PCI device structure.
879	* @param iRegion The region number.
880	* @param cbRegion Size of the region.
881	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
882	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
883	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
884	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
885	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
886	* @a fFlags, UINT64_MAX if no handle is passed
887	* (old style).
888	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
889	* is given.
890	* @remarks Caller enters the PDM critical section.
891	*/
892	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
893	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
894	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
895
896	/**
897	* Register PCI configuration space read/write intercept callbacks.
898	*
899	* @param pDevIns Device instance of the PCI Bus.
900	* @param pPciDev The PCI device structure.
901	* @param pfnRead Pointer to the user defined PCI config read function.
902	* @param pfnWrite Pointer to the user defined PCI config write function.
903	* to call default PCI config write function. Can be NULL.
904	* @remarks Caller enters the PDM critical section.
905	* @thread EMT
906	*/
907	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
908	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
909
910	/**
911	* Perform a PCI configuration space write, bypassing interception.
912	*
913	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
914	*
915	* @returns Strict VBox status code (mainly DBGFSTOP).
916	* @param pDevIns Device instance of the PCI Bus.
917	* @param pPciDev The PCI device which config space is being read.
918	* @param uAddress The config space address.
919	* @param cb The size of the read: 1, 2 or 4 bytes.
920	* @param u32Value The value to write.
921	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
922	* that the (root) bus will have done that already.
923	*/
924	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
925	uint32_t uAddress, unsigned cb, uint32_t u32Value));
926
927	/**
928	* Perform a PCI configuration space read, bypassing interception.
929	*
930	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
931	*
932	* @returns Strict VBox status code (mainly DBGFSTOP).
933	* @param pDevIns Device instance of the PCI Bus.
934	* @param pPciDev The PCI device which config space is being read.
935	* @param uAddress The config space address.
936	* @param cb The size of the read: 1, 2 or 4 bytes.
937	* @param pu32Value Where to return the value.
938	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
939	* that the (root) bus will have done that already.
940	*/
941	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
942	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
943
944	/**
945	* Set the IRQ for a PCI device.
946	*
947	* @param pDevIns Device instance of the PCI Bus.
948	* @param pPciDev The PCI device structure.
949	* @param iIrq IRQ number to set.
950	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
951	* @param uTagSrc The IRQ tag and source (for tracing).
952	* @remarks Caller enters the PDM critical section.
953	*/
954	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
955
956	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
957	uint32_t u32EndVersion;
958	} PDMPCIBUSREGR3;
959	/** Pointer to a PCI bus registration structure. */
960	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
961	/** Current PDMPCIBUSREGR3 version number. */
962	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
963
964	/**
965	* PCI Bus registration structure for ring-0.
966	*/
967	typedef struct PDMPCIBUSREGR0
968	{
969	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
970	uint32_t u32Version;
971	/** The PCI bus number (from ring-3 registration). */
972	uint32_t iBus;
973	/**
974	* Set the IRQ for a PCI device.
975	*
976	* @param pDevIns Device instance of the PCI Bus.
977	* @param pPciDev The PCI device structure.
978	* @param iIrq IRQ number to set.
979	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
980	* @param uTagSrc The IRQ tag and source (for tracing).
981	* @remarks Caller enters the PDM critical section.
982	*/
983	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
984	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
985	uint32_t u32EndVersion;
986	} PDMPCIBUSREGR0;
987	/** Pointer to a PCI bus ring-0 registration structure. */
988	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
989	/** Current PDMPCIBUSREGR0 version number. */
990	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
991
992	/**
993	* PCI Bus registration structure for raw-mode.
994	*/
995	typedef struct PDMPCIBUSREGRC
996	{
997	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
998	uint32_t u32Version;
999	/** The PCI bus number (from ring-3 registration). */
1000	uint32_t iBus;
1001	/**
1002	* Set the IRQ for a PCI device.
1003	*
1004	* @param pDevIns Device instance of the PCI Bus.
1005	* @param pPciDev The PCI device structure.
1006	* @param iIrq IRQ number to set.
1007	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1008	* @param uTagSrc The IRQ tag and source (for tracing).
1009	* @remarks Caller enters the PDM critical section.
1010	*/
1011	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
1012	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1013	uint32_t u32EndVersion;
1014	} PDMPCIBUSREGRC;
1015	/** Pointer to a PCI bus raw-mode registration structure. */
1016	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1017	/** Current PDMPCIBUSREGRC version number. */
1018	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1019
1020	/** PCI bus registration structure for the current context. */
1021	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1022	/** Pointer to a PCI bus registration structure for the current context. */
1023	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1024	/** PCI bus registration structure version for the current context. */
1025	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1026
1027
1028	/**
1029	* PCI Bus RC helpers.
1030	*/
1031	typedef struct PDMPCIHLPRC
1032	{
1033	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1034	uint32_t u32Version;
1035
1036	/**
1037	* Set an ISA IRQ.
1038	*
1039	* @param pDevIns PCI device instance.
1040	* @param iIrq IRQ number to set.
1041	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1042	* @param uTagSrc The IRQ tag and source (for tracing).
1043	* @thread EMT only.
1044	*/
1045	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1046
1047	/**
1048	* Set an I/O-APIC IRQ.
1049	*
1050	* @param pDevIns PCI device instance.
1051	* @param uBusDevFn The bus:device:function of the device initiating the
1052	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1053	* interrupt.
1054	* @param iIrq IRQ number to set.
1055	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1056	* @param uTagSrc The IRQ tag and source (for tracing).
1057	* @thread EMT only.
1058	*/
1059	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1060
1061	/**
1062	* Send an MSI.
1063	*
1064	* @param pDevIns PCI device instance.
1065	* @param uBusDevFn The bus:device:function of the device initiating the
1066	* MSI. Cannot be NIL_PCIBDF.
1067	* @param pMsi The MSI to send.
1068	* @param uTagSrc The IRQ tag and source (for tracing).
1069	* @thread EMT only.
1070	*/
1071	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1072
1073
1074	/**
1075	* Acquires the PDM lock.
1076	*
1077	* @returns VINF_SUCCESS on success.
1078	* @returns rc if we failed to acquire the lock.
1079	* @param pDevIns The PCI device instance.
1080	* @param rc What to return if we fail to acquire the lock.
1081	*
1082	* @sa PDMCritSectEnter
1083	*/
1084	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1085
1086	/**
1087	* Releases the PDM lock.
1088	*
1089	* @param pDevIns The PCI device instance.
1090	*/
1091	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1092
1093	/**
1094	* Gets a bus by it's PDM ordinal (typically the parent bus).
1095	*
1096	* @returns Pointer to the device instance of the bus.
1097	* @param pDevIns The PCI bus device instance.
1098	* @param idxPdmBus The PDM ordinal value of the bus to get.
1099	*/
1100	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1101
1102	/** Just a safety precaution. */
1103	uint32_t u32TheEnd;
1104	} PDMPCIHLPRC;
1105	/** Pointer to PCI helpers. */
1106	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1107	/** Pointer to const PCI helpers. */
1108	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1109
1110	/** Current PDMPCIHLPRC version number. */
1111	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1112
1113
1114	/**
1115	* PCI Bus R0 helpers.
1116	*/
1117	typedef struct PDMPCIHLPR0
1118	{
1119	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1120	uint32_t u32Version;
1121
1122	/**
1123	* Set an ISA IRQ.
1124	*
1125	* @param pDevIns PCI device instance.
1126	* @param iIrq IRQ number to set.
1127	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1128	* @param uTagSrc The IRQ tag and source (for tracing).
1129	* @thread EMT only.
1130	*/
1131	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1132
1133	/**
1134	* Set an I/O-APIC IRQ.
1135	*
1136	* @param pDevIns PCI device instance.
1137	* @param uBusDevFn The bus:device:function of the device initiating the
1138	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1139	* interrupt.
1140	* @param iIrq IRQ number to set.
1141	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1142	* @param uTagSrc The IRQ tag and source (for tracing).
1143	* @thread EMT only.
1144	*/
1145	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1146
1147	/**
1148	* Send an MSI.
1149	*
1150	* @param pDevIns PCI device instance.
1151	* @param uBusDevFn The bus:device:function of the device initiating the
1152	* MSI. Cannot be NIL_PCIBDF.
1153	* @param pMsi The MSI to send.
1154	* @param uTagSrc The IRQ tag and source (for tracing).
1155	* @thread EMT only.
1156	*/
1157	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1158
1159	/**
1160	* Acquires the PDM lock.
1161	*
1162	* @returns VINF_SUCCESS on success.
1163	* @returns rc if we failed to acquire the lock.
1164	* @param pDevIns The PCI device instance.
1165	* @param rc What to return if we fail to acquire the lock.
1166	*
1167	* @sa PDMCritSectEnter
1168	*/
1169	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1170
1171	/**
1172	* Releases the PDM lock.
1173	*
1174	* @param pDevIns The PCI device instance.
1175	*/
1176	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1177
1178	/**
1179	* Gets a bus by it's PDM ordinal (typically the parent bus).
1180	*
1181	* @returns Pointer to the device instance of the bus.
1182	* @param pDevIns The PCI bus device instance.
1183	* @param idxPdmBus The PDM ordinal value of the bus to get.
1184	*/
1185	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1186
1187	/** Just a safety precaution. */
1188	uint32_t u32TheEnd;
1189	} PDMPCIHLPR0;
1190	/** Pointer to PCI helpers. */
1191	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1192	/** Pointer to const PCI helpers. */
1193	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1194
1195	/** Current PDMPCIHLPR0 version number. */
1196	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1197
1198	/**
1199	* PCI device helpers.
1200	*/
1201	typedef struct PDMPCIHLPR3
1202	{
1203	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1204	uint32_t u32Version;
1205
1206	/**
1207	* Set an ISA IRQ.
1208	*
1209	* @param pDevIns The PCI device instance.
1210	* @param iIrq IRQ number to set.
1211	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1212	* @param uTagSrc The IRQ tag and source (for tracing).
1213	*/
1214	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1215
1216	/**
1217	* Set an I/O-APIC IRQ.
1218	*
1219	* @param pDevIns The PCI device instance.
1220	* @param uBusDevFn The bus:device:function of the device initiating the
1221	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1222	* interrupt.
1223	* @param iIrq IRQ number to set.
1224	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1225	* @param uTagSrc The IRQ tag and source (for tracing).
1226	*/
1227	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1228
1229	/**
1230	* Send an MSI.
1231	*
1232	* @param pDevIns PCI device instance.
1233	* @param uBusDevFn The bus:device:function of the device initiating the
1234	* MSI. Cannot be NIL_PCIBDF.
1235	* @param pMsi The MSI to send.
1236	* @param uTagSrc The IRQ tag and source (for tracing).
1237	*/
1238	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1239
1240	/**
1241	* Acquires the PDM lock.
1242	*
1243	* @returns VINF_SUCCESS on success.
1244	* @returns Fatal error on failure.
1245	* @param pDevIns The PCI device instance.
1246	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1247	*
1248	* @sa PDMCritSectEnter
1249	*/
1250	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1251
1252	/**
1253	* Releases the PDM lock.
1254	*
1255	* @param pDevIns The PCI device instance.
1256	*/
1257	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1258
1259	/**
1260	* Gets a bus by it's PDM ordinal (typically the parent bus).
1261	*
1262	* @returns Pointer to the device instance of the bus.
1263	* @param pDevIns The PCI bus device instance.
1264	* @param idxPdmBus The PDM ordinal value of the bus to get.
1265	*/
1266	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1267
1268	/** Just a safety precaution. */
1269	uint32_t u32TheEnd;
1270	} PDMPCIHLPR3;
1271	/** Pointer to PCI helpers. */
1272	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1273	/** Pointer to const PCI helpers. */
1274	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1275
1276	/** Current PDMPCIHLPR3 version number. */
1277	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1278
1279
1280	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1281	* These flags are used for memory access transactions via the IOMMU interface.
1282	* @{ */
1283	/** Memory read. */
1284	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1285	/** Memory write. */
1286	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1287	/** Valid flag mask. */
1288	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1289	/** @} */
1290
1291	/**
1292	* IOMMU registration structure for ring-0.
1293	*/
1294	typedef struct PDMIOMMUREGR0
1295	{
1296	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1297	* version. */
1298	uint32_t u32Version;
1299	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1300	uint32_t idxIommu;
1301
1302	/**
1303	* Translates the physical address for a memory transaction through the IOMMU.
1304	*
1305	* @returns VBox status code.
1306	* @param pDevIns The IOMMU device instance.
1307	* @param idDevice The device identifier (bus, device, function).
1308	* @param uIova The I/O virtual address being accessed.
1309	* @param cbIova The size of the access.
1310	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1311	* @param pGCPhysSpa Where to store the translated system physical address.
1312	* @param pcbContiguous Where to store the number of contiguous bytes translated
1313	* and permission-checked.
1314	*
1315	* @thread Any.
1316	*/
1317	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1318	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1319
1320	/**
1321	* Translates in bulk physical page addresses for memory transactions through the
1322	* IOMMU.
1323	*
1324	* @returns VBox status code.
1325	* @param pDevIns The IOMMU device instance.
1326	* @param idDevice The device identifier (bus, device, function).
1327	* @param cIovas The number of I/O virtual addresses being accessed.
1328	* @param pauIovas The I/O virtual addresses being accessed.
1329	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1330	* @param paGCPhysSpa Where to store the translated system physical page
1331	* addresses.
1332	*
1333	* @thread Any.
1334	*/
1335	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1336	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1337
1338	/**
1339	* Performs an interrupt remap request through the IOMMU.
1340	*
1341	* @returns VBox status code.
1342	* @param pDevIns The IOMMU device instance.
1343	* @param idDevice The device identifier (bus, device, function).
1344	* @param pMsiIn The source MSI.
1345	* @param pMsiOut Where to store the remapped MSI.
1346	*
1347	* @thread Any.
1348	*/
1349	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1350
1351	/** Just a safety precaution. */
1352	uint32_t u32TheEnd;
1353	} PDMIOMMUREGR0;
1354	/** Pointer to a IOMMU registration structure. */
1355	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1356
1357	/** Current PDMIOMMUREG version number. */
1358	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1359
1360
1361	/**
1362	* IOMMU registration structure for raw-mode.
1363	*/
1364	typedef struct PDMIOMMUREGRC
1365	{
1366	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1367	* version. */
1368	uint32_t u32Version;
1369	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1370	uint32_t idxIommu;
1371
1372	/**
1373	* Translates the physical address for a memory transaction through the IOMMU.
1374	*
1375	* @returns VBox status code.
1376	* @param pDevIns The IOMMU device instance.
1377	* @param idDevice The device identifier (bus, device, function).
1378	* @param uIova The I/O virtual address being accessed.
1379	* @param cbIova The size of the access.
1380	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1381	* @param pGCPhysSpa Where to store the translated system physical address.
1382	* @param pcbContiguous Where to store the number of contiguous bytes translated
1383	* and permission-checked.
1384	*
1385	* @thread Any.
1386	*/
1387	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1388	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1389
1390	/**
1391	* Translates in bulk physical page addresses for memory transactions through the
1392	* IOMMU.
1393	*
1394	* @returns VBox status code.
1395	* @param pDevIns The IOMMU device instance.
1396	* @param idDevice The device identifier (bus, device, function).
1397	* @param cIovas The number of I/O virtual addresses being accessed.
1398	* @param pauIovas The I/O virtual addresses being accessed.
1399	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1400	* @param paGCPhysSpa Where to store the translated system physical page
1401	* addresses.
1402	*
1403	* @thread Any.
1404	*/
1405	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1406	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1407
1408	/**
1409	* Performs an interrupt remap request through the IOMMU.
1410	*
1411	* @returns VBox status code.
1412	* @param pDevIns The IOMMU device instance.
1413	* @param idDevice The device identifier (bus, device, function).
1414	* @param pMsiIn The source MSI.
1415	* @param pMsiOut Where to store the remapped MSI.
1416	*
1417	* @thread Any.
1418	*/
1419	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1420
1421	/** Just a safety precaution. */
1422	uint32_t u32TheEnd;
1423	} PDMIOMMUREGRC;
1424	/** Pointer to a IOMMU registration structure. */
1425	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1426
1427	/** Current PDMIOMMUREG version number. */
1428	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1429
1430
1431	/**
1432	* IOMMU registration structure for ring-3.
1433	*/
1434	typedef struct PDMIOMMUREGR3
1435	{
1436	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1437	* version. */
1438	uint32_t u32Version;
1439	/** Padding. */
1440	uint32_t uPadding0;
1441
1442	/**
1443	* Translates the physical address for a memory transaction through the IOMMU.
1444	*
1445	* @returns VBox status code.
1446	* @param pDevIns The IOMMU device instance.
1447	* @param idDevice The device identifier (bus, device, function).
1448	* @param uIova The I/O virtual address being accessed.
1449	* @param cbIova The size of the access.
1450	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1451	* @param pGCPhysSpa Where to store the translated system physical address.
1452	* @param pcbContiguous Where to store the number of contiguous bytes translated
1453	* and permission-checked.
1454	*
1455	* @thread Any.
1456	*/
1457	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1458	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1459
1460	/**
1461	* Translates in bulk physical page addresses for memory transactions through the
1462	* IOMMU.
1463	*
1464	* @returns VBox status code.
1465	* @param pDevIns The IOMMU device instance.
1466	* @param idDevice The device identifier (bus, device, function).
1467	* @param cIovas The number of I/O virtual addresses being accessed.
1468	* @param pauIovas The I/O virtual addresses being accessed.
1469	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1470	* @param paGCPhysSpa Where to store the translated system physical page
1471	* addresses.
1472	*
1473	* @thread Any.
1474	*/
1475	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1476	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1477
1478	/**
1479	* Performs an interrupt remap request through the IOMMU.
1480	*
1481	* @returns VBox status code.
1482	* @param pDevIns The IOMMU device instance.
1483	* @param idDevice The device identifier (bus, device, function).
1484	* @param pMsiIn The source MSI.
1485	* @param pMsiOut Where to store the remapped MSI.
1486	*
1487	* @thread Any.
1488	*/
1489	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1490
1491	/** Just a safety precaution. */
1492	uint32_t u32TheEnd;
1493	} PDMIOMMUREGR3;
1494	/** Pointer to a IOMMU registration structure. */
1495	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1496
1497	/** Current PDMIOMMUREG version number. */
1498	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1499
1500	/** IOMMU registration structure for the current context. */
1501	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1502	/** Pointer to an IOMMU registration structure for the current context. */
1503	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1504	/** IOMMU registration structure version for the current context. */
1505	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1506
1507
1508	/**
1509	* IOMMU helpers for ring-0.
1510	*/
1511	typedef struct PDMIOMMUHLPR0
1512	{
1513	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1514	uint32_t u32Version;
1515
1516	/**
1517	* Acquires the PDM lock.
1518	*
1519	* @returns VINF_SUCCESS on success.
1520	* @returns rc if we failed to acquire the lock.
1521	* @param pDevIns The PCI device instance.
1522	* @param rc What to return if we fail to acquire the lock.
1523	*
1524	* @sa PDMCritSectEnter
1525	*/
1526	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1527
1528	/**
1529	* Releases the PDM lock.
1530	*
1531	* @param pDevIns The PCI device instance.
1532	*/
1533	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1534
1535	/**
1536	* Check whether the calling thread owns the PDM lock.
1537	*
1538	* @returns @c true if the PDM lock is owned, @c false otherwise.
1539	* @param pDevIns The PCI device instance.
1540	*/
1541	DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1542
1543	/**
1544	* Send an MSI (when generated by the IOMMU device itself).
1545	*
1546	* @param pDevIns PCI device instance.
1547	* @param pMsi The MSI to send.
1548	* @param uTagSrc The IRQ tag and source (for tracing).
1549	*/
1550	DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1551
1552	/** Just a safety precaution. */
1553	uint32_t u32TheEnd;
1554	} PDMIOMMUHLPR0;
1555	/** Pointer to IOMMU helpers for ring-0. */
1556	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1557	/** Pointer to const IOMMU helpers for ring-0. */
1558	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1559
1560	/** Current PDMIOMMUHLPR0 version number. */
1561	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1562
1563
1564	/**
1565	* IOMMU helpers for raw-mode.
1566	*/
1567	typedef struct PDMIOMMUHLPRC
1568	{
1569	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1570	uint32_t u32Version;
1571
1572	/**
1573	* Acquires the PDM lock.
1574	*
1575	* @returns VINF_SUCCESS on success.
1576	* @returns rc if we failed to acquire the lock.
1577	* @param pDevIns The PCI device instance.
1578	* @param rc What to return if we fail to acquire the lock.
1579	*
1580	* @sa PDMCritSectEnter
1581	*/
1582	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1583
1584	/**
1585	* Releases the PDM lock.
1586	*
1587	* @param pDevIns The PCI device instance.
1588	*/
1589	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1590
1591	/**
1592	* Check whether the threads owns the PDM lock.
1593	*
1594	* @returns @c true if the PDM lock is owned, @c false otherwise.
1595	* @param pDevIns The PCI device instance.
1596	*/
1597	DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1598
1599	/**
1600	* Send an MSI (when generated by the IOMMU device itself).
1601	*
1602	* @param pDevIns PCI device instance.
1603	* @param pMsi The MSI to send.
1604	* @param uTagSrc The IRQ tag and source (for tracing).
1605	*/
1606	DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1607
1608	/** Just a safety precaution. */
1609	uint32_t u32TheEnd;
1610	} PDMIOMMUHLPRC;
1611	/** Pointer to IOMMU helpers for raw-mode. */
1612	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1613	/** Pointer to const IOMMU helpers for raw-mode. */
1614	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1615
1616	/** Current PDMIOMMUHLPRC version number. */
1617	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1618
1619
1620	/**
1621	* IOMMU helpers for ring-3.
1622	*/
1623	typedef struct PDMIOMMUHLPR3
1624	{
1625	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1626	uint32_t u32Version;
1627
1628	/**
1629	* Acquires the PDM lock.
1630	*
1631	* @returns VINF_SUCCESS on success.
1632	* @returns rc if we failed to acquire the lock.
1633	* @param pDevIns The PCI device instance.
1634	* @param rc What to return if we fail to acquire the lock.
1635	*
1636	* @sa PDMCritSectEnter
1637	*/
1638	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1639
1640	/**
1641	* Releases the PDM lock.
1642	*
1643	* @param pDevIns The PCI device instance.
1644	*/
1645	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1646
1647	/**
1648	* Check whether the threads owns the PDM lock.
1649	*
1650	* @returns @c true if the PDM lock is owned, @c false otherwise.
1651	* @param pDevIns The PCI device instance.
1652	*/
1653	DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1654
1655	/**
1656	* Send an MSI (when generated by the IOMMU device itself).
1657	*
1658	* @param pDevIns PCI device instance.
1659	* @param pMsi The MSI to send.
1660	* @param uTagSrc The IRQ tag and source (for tracing).
1661	*/
1662	DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1663
1664	/** Just a safety precaution. */
1665	uint32_t u32TheEnd;
1666	} PDMIOMMUHLPR3;
1667	/** Pointer to IOMMU helpers for raw-mode. */
1668	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1669	/** Pointer to const IOMMU helpers for raw-mode. */
1670	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1671
1672	/** Current PDMIOMMUHLPR3 version number. */
1673	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1674
1675
1676	/**
1677	* Programmable Interrupt Controller registration structure (all contexts).
1678	*/
1679	typedef struct PDMPICREG
1680	{
1681	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1682	uint32_t u32Version;
1683
1684	/**
1685	* Set the an IRQ.
1686	*
1687	* @param pDevIns Device instance of the PIC.
1688	* @param iIrq IRQ number to set.
1689	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1690	* @param uTagSrc The IRQ tag and source (for tracing).
1691	* @remarks Caller enters the PDM critical section.
1692	*/
1693	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1694
1695	/**
1696	* Get a pending interrupt.
1697	*
1698	* @returns Pending interrupt number.
1699	* @param pDevIns Device instance of the PIC.
1700	* @param puTagSrc Where to return the IRQ tag and source.
1701	* @remarks Caller enters the PDM critical section.
1702	*/
1703	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1704
1705	/** Just a safety precaution. */
1706	uint32_t u32TheEnd;
1707	} PDMPICREG;
1708	/** Pointer to a PIC registration structure. */
1709	typedef PDMPICREG *PPDMPICREG;
1710
1711	/** Current PDMPICREG version number. */
1712	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1713
1714	/**
1715	* PIC helpers, same in all contexts.
1716	*/
1717	typedef struct PDMPICHLP
1718	{
1719	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1720	uint32_t u32Version;
1721
1722	/**
1723	* Set the interrupt force action flag.
1724	*
1725	* @param pDevIns Device instance of the PIC.
1726	*/
1727	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1728
1729	/**
1730	* Clear the interrupt force action flag.
1731	*
1732	* @param pDevIns Device instance of the PIC.
1733	*/
1734	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1735
1736	/**
1737	* Acquires the PDM lock.
1738	*
1739	* @returns VINF_SUCCESS on success.
1740	* @returns rc if we failed to acquire the lock.
1741	* @param pDevIns The PIC device instance.
1742	* @param rc What to return if we fail to acquire the lock.
1743	*
1744	* @sa PDMCritSectEnter
1745	*/
1746	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1747
1748	/**
1749	* Releases the PDM lock.
1750	*
1751	* @param pDevIns The PIC device instance.
1752	*/
1753	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1754
1755	/** Just a safety precaution. */
1756	uint32_t u32TheEnd;
1757	} PDMPICHLP;
1758	/** Pointer to PIC helpers. */
1759	typedef PDMPICHLP *PPDMPICHLP;
1760	/** Pointer to const PIC helpers. */
1761	typedef const PDMPICHLP *PCPDMPICHLP;
1762
1763	/** Current PDMPICHLP version number. */
1764	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1765
1766
1767	/**
1768	* Firmware registration structure.
1769	*/
1770	typedef struct PDMFWREG
1771	{
1772	/** Struct version+magic number (PDM_FWREG_VERSION). */
1773	uint32_t u32Version;
1774
1775	/**
1776	* Checks whether this is a hard or soft reset.
1777	*
1778	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1779	* is 5, 9 or 0xA.
1780	*
1781	* @returns true if hard reset, false if soft.
1782	* @param pDevIns Device instance of the firmware.
1783	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1784	*/
1785	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1786
1787	/** Just a safety precaution. */
1788	uint32_t u32TheEnd;
1789	} PDMFWREG;
1790	/** Pointer to a FW registration structure. */
1791	typedef PDMFWREG *PPDMFWREG;
1792	/** Pointer to a const FW registration structure. */
1793	typedef PDMFWREG const *PCPDMFWREG;
1794
1795	/** Current PDMFWREG version number. */
1796	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1797
1798	/**
1799	* Firmware R3 helpers.
1800	*/
1801	typedef struct PDMFWHLPR3
1802	{
1803	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1804	uint32_t u32Version;
1805
1806	/** Just a safety precaution. */
1807	uint32_t u32TheEnd;
1808	} PDMFWHLPR3;
1809
1810	/** Pointer to FW R3 helpers. */
1811	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1812	/** Pointer to const FW R3 helpers. */
1813	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1814
1815	/** Current PDMFWHLPR3 version number. */
1816	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1817
1818
1819	/**
1820	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1821	*
1822	* Also used in saved-states, CFGM don't change existing values.
1823	*/
1824	typedef enum PDMAPICMODE
1825	{
1826	/** Invalid 0 entry. */
1827	PDMAPICMODE_INVALID = 0,
1828	/** No APIC. */
1829	PDMAPICMODE_NONE,
1830	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1831	PDMAPICMODE_APIC,
1832	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1833	PDMAPICMODE_X2APIC,
1834	/** The usual 32-bit paranoia. */
1835	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1836	} PDMAPICMODE;
1837
1838	/**
1839	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1840	*/
1841	typedef enum PDMAPICIRQ
1842	{
1843	/** Invalid 0 entry. */
1844	PDMAPICIRQ_INVALID = 0,
1845	/** Normal hardware interrupt. */
1846	PDMAPICIRQ_HARDWARE,
1847	/** NMI. */
1848	PDMAPICIRQ_NMI,
1849	/** SMI. */
1850	PDMAPICIRQ_SMI,
1851	/** ExtINT (HW interrupt via PIC). */
1852	PDMAPICIRQ_EXTINT,
1853	/** Interrupt arrived, needs to be updated to the IRR. */
1854	PDMAPICIRQ_UPDATE_PENDING,
1855	/** The usual 32-bit paranoia. */
1856	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1857	} PDMAPICIRQ;
1858
1859
1860	/**
1861	* I/O APIC registration structure (all contexts).
1862	*/
1863	typedef struct PDMIOAPICREG
1864	{
1865	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1866	uint32_t u32Version;
1867
1868	/**
1869	* Set an IRQ.
1870	*
1871	* @param pDevIns Device instance of the I/O APIC.
1872	* @param uBusDevFn The bus:device:function of the device initiating the
1873	* IRQ. Can be NIL_PCIBDF.
1874	* @param iIrq IRQ number to set.
1875	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1876	* @param uTagSrc The IRQ tag and source (for tracing).
1877	*
1878	* @remarks Caller enters the PDM critical section
1879	* Actually, as per 2018-07-21 this isn't true (bird).
1880	*/
1881	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1882
1883	/**
1884	* Send a MSI.
1885	*
1886	* @param pDevIns Device instance of the I/O APIC.
1887	* @param uBusDevFn The bus:device:function of the device initiating the
1888	* MSI. Cannot be NIL_PCIBDF.
1889	* @param pMsi The MSI to send.
1890	* @param uTagSrc The IRQ tag and source (for tracing).
1891	*
1892	* @remarks Caller enters the PDM critical section
1893	* Actually, as per 2018-07-21 this isn't true (bird).
1894	*/
1895	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1896
1897	/**
1898	* Set the EOI for an interrupt vector.
1899	*
1900	* @param pDevIns Device instance of the I/O APIC.
1901	* @param u8Vector The vector.
1902	*
1903	* @remarks Caller enters the PDM critical section
1904	* Actually, as per 2018-07-21 this isn't true (bird).
1905	*/
1906	DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1907
1908	/** Just a safety precaution. */
1909	uint32_t u32TheEnd;
1910	} PDMIOAPICREG;
1911	/** Pointer to an APIC registration structure. */
1912	typedef PDMIOAPICREG *PPDMIOAPICREG;
1913
1914	/** Current PDMAPICREG version number. */
1915	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1916
1917
1918	/**
1919	* IOAPIC helpers, same in all contexts.
1920	*/
1921	typedef struct PDMIOAPICHLP
1922	{
1923	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1924	uint32_t u32Version;
1925
1926	/**
1927	* Private interface between the IOAPIC and APIC.
1928	*
1929	* @returns status code.
1930	* @param pDevIns Device instance of the IOAPIC.
1931	* @param u8Dest See APIC implementation.
1932	* @param u8DestMode See APIC implementation.
1933	* @param u8DeliveryMode See APIC implementation.
1934	* @param uVector See APIC implementation.
1935	* @param u8Polarity See APIC implementation.
1936	* @param u8TriggerMode See APIC implementation.
1937	* @param uTagSrc The IRQ tag and source (for tracing).
1938	*
1939	* @sa APICBusDeliver()
1940	*/
1941	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1942	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1943
1944	/**
1945	* Acquires the PDM lock.
1946	*
1947	* @returns VINF_SUCCESS on success.
1948	* @returns rc if we failed to acquire the lock.
1949	* @param pDevIns The IOAPIC device instance.
1950	* @param rc What to return if we fail to acquire the lock.
1951	*
1952	* @sa PDMCritSectEnter
1953	*/
1954	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1955
1956	/**
1957	* Releases the PDM lock.
1958	*
1959	* @param pDevIns The IOAPIC device instance.
1960	*/
1961	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1962
1963	/**
1964	* Checks if the calling thread owns the PDM lock.
1965	*
1966	* @param pDevIns The IOAPIC device instance.
1967	*/
1968	DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1969
1970	/**
1971	* Private interface between the IOAPIC and IOMMU.
1972	*
1973	* @returns status code.
1974	* @param pDevIns Device instance of the IOAPIC.
1975	* @param idDevice The device identifier (bus, device, function).
1976	* @param pMsiIn The source MSI.
1977	* @param pMsiOut Where to store the remapped MSI (only updated when
1978	* VINF_SUCCESS is returned).
1979	*/
1980	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1981
1982	/** Just a safety precaution. */
1983	uint32_t u32TheEnd;
1984	} PDMIOAPICHLP;
1985	/** Pointer to IOAPIC helpers. */
1986	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1987	/** Pointer to const IOAPIC helpers. */
1988	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1989
1990	/** Current PDMIOAPICHLP version number. */
1991	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1992
1993
1994	/**
1995	* HPET registration structure.
1996	*/
1997	typedef struct PDMHPETREG
1998	{
1999	/** Struct version+magic number (PDM_HPETREG_VERSION). */
2000	uint32_t u32Version;
2001	} PDMHPETREG;
2002	/** Pointer to an HPET registration structure. */
2003	typedef PDMHPETREG *PPDMHPETREG;
2004
2005	/** Current PDMHPETREG version number. */
2006	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
2007
2008	/**
2009	* HPET RC helpers.
2010	*
2011	* @remarks Keep this around in case HPET will need PDM interaction in again RC
2012	* at some later point.
2013	*/
2014	typedef struct PDMHPETHLPRC
2015	{
2016	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
2017	uint32_t u32Version;
2018
2019	/** Just a safety precaution. */
2020	uint32_t u32TheEnd;
2021	} PDMHPETHLPRC;
2022
2023	/** Pointer to HPET RC helpers. */
2024	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
2025	/** Pointer to const HPET RC helpers. */
2026	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
2027
2028	/** Current PDMHPETHLPRC version number. */
2029	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
2030
2031
2032	/**
2033	* HPET R0 helpers.
2034	*
2035	* @remarks Keep this around in case HPET will need PDM interaction in again R0
2036	* at some later point.
2037	*/
2038	typedef struct PDMHPETHLPR0
2039	{
2040	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2041	uint32_t u32Version;
2042
2043	/** Just a safety precaution. */
2044	uint32_t u32TheEnd;
2045	} PDMHPETHLPR0;
2046
2047	/** Pointer to HPET R0 helpers. */
2048	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2049	/** Pointer to const HPET R0 helpers. */
2050	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2051
2052	/** Current PDMHPETHLPR0 version number. */
2053	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2054
2055	/**
2056	* HPET R3 helpers.
2057	*/
2058	typedef struct PDMHPETHLPR3
2059	{
2060	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2061	uint32_t u32Version;
2062
2063	/**
2064	* Set legacy mode on PIT and RTC.
2065	*
2066	* @returns VINF_SUCCESS on success.
2067	* @returns rc if we failed to set legacy mode.
2068	* @param pDevIns Device instance of the HPET.
2069	* @param fActivated Whether legacy mode is activated or deactivated.
2070	*/
2071	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2072
2073
2074	/**
2075	* Set IRQ, bypassing ISA bus override rules.
2076	*
2077	* @returns VINF_SUCCESS on success.
2078	* @returns rc if we failed to set legacy mode.
2079	* @param pDevIns Device instance of the HPET.
2080	* @param iIrq IRQ number to set.
2081	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2082	*/
2083	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2084
2085	/** Just a safety precaution. */
2086	uint32_t u32TheEnd;
2087	} PDMHPETHLPR3;
2088
2089	/** Pointer to HPET R3 helpers. */
2090	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2091	/** Pointer to const HPET R3 helpers. */
2092	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2093
2094	/** Current PDMHPETHLPR3 version number. */
2095	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2096
2097
2098	/**
2099	* Raw PCI device registration structure.
2100	*/
2101	typedef struct PDMPCIRAWREG
2102	{
2103	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2104	uint32_t u32Version;
2105	/** Just a safety precaution. */
2106	uint32_t u32TheEnd;
2107	} PDMPCIRAWREG;
2108	/** Pointer to a raw PCI registration structure. */
2109	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2110
2111	/** Current PDMPCIRAWREG version number. */
2112	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2113
2114	/**
2115	* Raw PCI device raw-mode context helpers.
2116	*/
2117	typedef struct PDMPCIRAWHLPRC
2118	{
2119	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2120	uint32_t u32Version;
2121	/** Just a safety precaution. */
2122	uint32_t u32TheEnd;
2123	} PDMPCIRAWHLPRC;
2124	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2125	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2126	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2127	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2128
2129	/** Current PDMPCIRAWHLPRC version number. */
2130	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2131
2132	/**
2133	* Raw PCI device ring-0 context helpers.
2134	*/
2135	typedef struct PDMPCIRAWHLPR0
2136	{
2137	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2138	uint32_t u32Version;
2139	/** Just a safety precaution. */
2140	uint32_t u32TheEnd;
2141	} PDMPCIRAWHLPR0;
2142	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2143	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2144	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2145	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2146
2147	/** Current PDMPCIRAWHLPR0 version number. */
2148	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2149
2150
2151	/**
2152	* Raw PCI device ring-3 context helpers.
2153	*/
2154	typedef struct PDMPCIRAWHLPR3
2155	{
2156	/** Undefined structure version and magic number. */
2157	uint32_t u32Version;
2158
2159	/**
2160	* Gets the address of the RC raw PCI device helpers.
2161	*
2162	* This should be called at both construction and relocation time to obtain
2163	* the correct address of the RC helpers.
2164	*
2165	* @returns RC pointer to the raw PCI device helpers.
2166	* @param pDevIns Device instance of the raw PCI device.
2167	*/
2168	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2169
2170	/**
2171	* Gets the address of the R0 raw PCI device helpers.
2172	*
2173	* This should be called at both construction and relocation time to obtain
2174	* the correct address of the R0 helpers.
2175	*
2176	* @returns R0 pointer to the raw PCI device helpers.
2177	* @param pDevIns Device instance of the raw PCI device.
2178	*/
2179	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2180
2181	/** Just a safety precaution. */
2182	uint32_t u32TheEnd;
2183	} PDMPCIRAWHLPR3;
2184	/** Pointer to raw PCI R3 helpers. */
2185	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2186	/** Pointer to const raw PCI R3 helpers. */
2187	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2188
2189	/** Current PDMPCIRAWHLPR3 version number. */
2190	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2191
2192
2193	#ifdef IN_RING3
2194
2195	/**
2196	* DMA Transfer Handler.
2197	*
2198	* @returns Number of bytes transferred.
2199	* @param pDevIns The device instance that registered the handler.
2200	* @param pvUser User pointer.
2201	* @param uChannel Channel number.
2202	* @param off DMA position.
2203	* @param cb Block size.
2204	* @remarks The device lock is take before the callback (in fact, the locks of
2205	* DMA devices and the DMA controller itself are taken).
2206	*/
2207	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2208	uint32_t off, uint32_t cb));
2209	/** Pointer to a FNDMATRANSFERHANDLER(). */
2210	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2211
2212	/**
2213	* DMA Controller registration structure.
2214	*/
2215	typedef struct PDMDMAREG
2216	{
2217	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2218	uint32_t u32Version;
2219
2220	/**
2221	* Execute pending transfers.
2222	*
2223	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2224	* @param pDevIns Device instance of the DMAC.
2225	* @remarks No locks held, called on EMT(0) as a form of serialization.
2226	*/
2227	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2228
2229	/**
2230	* Register transfer function for DMA channel.
2231	*
2232	* @param pDevIns Device instance of the DMAC.
2233	* @param uChannel Channel number.
2234	* @param pDevInsHandler The device instance of the device making the
2235	* regstration (will be passed to the callback).
2236	* @param pfnTransferHandler Device specific transfer function.
2237	* @param pvUser User pointer to be passed to the callback.
2238	* @remarks No locks held, called on an EMT.
2239	*/
2240	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2241	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2242
2243	/**
2244	* Read memory
2245	*
2246	* @returns Number of bytes read.
2247	* @param pDevIns Device instance of the DMAC.
2248	* @param uChannel Channel number.
2249	* @param pvBuffer Pointer to target buffer.
2250	* @param off DMA position.
2251	* @param cbBlock Block size.
2252	* @remarks No locks held, called on an EMT.
2253	*/
2254	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2255
2256	/**
2257	* Write memory
2258	*
2259	* @returns Number of bytes written.
2260	* @param pDevIns Device instance of the DMAC.
2261	* @param uChannel Channel number.
2262	* @param pvBuffer Memory to write.
2263	* @param off DMA position.
2264	* @param cbBlock Block size.
2265	* @remarks No locks held, called on an EMT.
2266	*/
2267	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2268
2269	/**
2270	* Set the DREQ line.
2271	*
2272	* @param pDevIns Device instance of the DMAC.
2273	* @param uChannel Channel number.
2274	* @param uLevel Level of the line.
2275	* @remarks No locks held, called on an EMT.
2276	*/
2277	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2278
2279	/**
2280	* Get channel mode
2281	*
2282	* @returns Channel mode.
2283	* @param pDevIns Device instance of the DMAC.
2284	* @param uChannel Channel number.
2285	* @remarks No locks held, called on an EMT.
2286	*/
2287	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2288
2289	} PDMDMACREG;
2290	/** Pointer to a DMAC registration structure. */
2291	typedef PDMDMACREG *PPDMDMACREG;
2292
2293	/** Current PDMDMACREG version number. */
2294	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2295
2296
2297	/**
2298	* DMA Controller device helpers.
2299	*/
2300	typedef struct PDMDMACHLP
2301	{
2302	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2303	uint32_t u32Version;
2304
2305	/* to-be-defined */
2306
2307	} PDMDMACHLP;
2308	/** Pointer to DMAC helpers. */
2309	typedef PDMDMACHLP *PPDMDMACHLP;
2310	/** Pointer to const DMAC helpers. */
2311	typedef const PDMDMACHLP *PCPDMDMACHLP;
2312
2313	/** Current PDMDMACHLP version number. */
2314	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2315
2316	#endif /* IN_RING3 */
2317
2318
2319
2320	/**
2321	* RTC registration structure.
2322	*/
2323	typedef struct PDMRTCREG
2324	{
2325	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2326	uint32_t u32Version;
2327	uint32_t u32Alignment; /*< structure size alignment. /
2328
2329	/**
2330	* Write to a CMOS register and update the checksum if necessary.
2331	*
2332	* @returns VBox status code.
2333	* @param pDevIns Device instance of the RTC.
2334	* @param iReg The CMOS register index.
2335	* @param u8Value The CMOS register value.
2336	* @remarks Caller enters the device critical section.
2337	*/
2338	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2339
2340	/**
2341	* Read a CMOS register.
2342	*
2343	* @returns VBox status code.
2344	* @param pDevIns Device instance of the RTC.
2345	* @param iReg The CMOS register index.
2346	* @param pu8Value Where to store the CMOS register value.
2347	* @remarks Caller enters the device critical section.
2348	*/
2349	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2350
2351	} PDMRTCREG;
2352	/** Pointer to a RTC registration structure. */
2353	typedef PDMRTCREG *PPDMRTCREG;
2354	/** Pointer to a const RTC registration structure. */
2355	typedef const PDMRTCREG *PCPDMRTCREG;
2356
2357	/** Current PDMRTCREG version number. */
2358	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2359
2360
2361	/**
2362	* RTC device helpers.
2363	*/
2364	typedef struct PDMRTCHLP
2365	{
2366	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2367	uint32_t u32Version;
2368
2369	/* to-be-defined */
2370
2371	} PDMRTCHLP;
2372	/** Pointer to RTC helpers. */
2373	typedef PDMRTCHLP *PPDMRTCHLP;
2374	/** Pointer to const RTC helpers. */
2375	typedef const PDMRTCHLP *PCPDMRTCHLP;
2376
2377	/** Current PDMRTCHLP version number. */
2378	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2379
2380
2381
2382	/** @name Flags for PCI I/O region registration
2383	* @{ */
2384	/** No handle is passed. */
2385	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2386	/** An I/O port handle is passed. */
2387	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2388	/** An MMIO range handle is passed. */
2389	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2390	/** An MMIO2 handle is passed. */
2391	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2392	/** Handle type mask. */
2393	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2394	/** New-style (mostly wrt callbacks). */
2395	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2396	/** Mask of valid flags. */
2397	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2398	/** @} */
2399
2400
2401	/** @name Flags for the guest physical read/write helpers
2402	* @{ */
2403	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2404	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2405	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2406	* by the device in any way. */
2407	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2408	/** The data is metadata and being processed by the device in some way. */
2409	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2410	/** @} */
2411
2412
2413	#ifdef IN_RING3
2414
2415	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2416	* @{ */
2417	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2418	* This is handy when registering multiple PCI device functions and the device
2419	* number is left up to the PCI bus. In order to facilitate one PDM device
2420	* instance for each PCI function, this searches earlier PDM device
2421	* instances as well. */
2422	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2423	/** Use the first unused device number (all functions must be unused). */
2424	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2425	/** Use the first unused device function. */
2426	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2427
2428	/** The device and function numbers are not mandatory, just suggestions. */
2429	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2430	/** Registering a PCI bridge device. */
2431	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2432	/** Valid flag mask. */
2433	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2434	/** @} */
2435
2436	/** Current PDMDEVHLPR3 version number. */
2437	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 65, 0)
2438
2439	/**
2440	* PDM Device API.
2441	*/
2442	typedef struct PDMDEVHLPR3
2443	{
2444	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2445	uint32_t u32Version;
2446
2447	/** @name I/O ports
2448	* @{ */
2449	/**
2450	* Creates a range of I/O ports for a device.
2451	*
2452	* The I/O port range must be mapped in a separately call. Any ring-0 and
2453	* raw-mode context callback handlers needs to be set up in the respective
2454	* contexts.
2455	*
2456	* @returns VBox status.
2457	* @param pDevIns The device instance to register the ports with.
2458	* @param cPorts Number of ports to register.
2459	* @param fFlags IOM_IOPORT_F_XXX.
2460	* @param pPciDev The PCI device the range is associated with, if
2461	* applicable.
2462	* @param iPciRegion The PCI device region in the high 16-bit word and
2463	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2464	* @param pfnOut Pointer to function which is gonna handle OUT
2465	* operations. Optional.
2466	* @param pfnIn Pointer to function which is gonna handle IN operations.
2467	* Optional.
2468	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2469	* operations. Optional.
2470	* @param pfnInStr Pointer to function which is gonna handle string IN
2471	* operations. Optional.
2472	* @param pvUser User argument to pass to the callbacks.
2473	* @param pszDesc Pointer to description string. This must not be freed.
2474	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2475	* coverage is allowed. This must not be freed.
2476	* @param phIoPorts Where to return the I/O port range handle.
2477	*
2478	* @remarks Caller enters the device critical section prior to invoking the
2479	* registered callback methods.
2480	*
2481	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2482	* PDMDevHlpIoPortUnmap.
2483	*/
2484	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2485	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2486	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2487	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2488
2489	/**
2490	* Maps an I/O port range.
2491	*
2492	* @returns VBox status.
2493	* @param pDevIns The device instance to register the ports with.
2494	* @param hIoPorts The I/O port range handle.
2495	* @param Port Where to map the range.
2496	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2497	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2498	*/
2499	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2500
2501	/**
2502	* Unmaps an I/O port range.
2503	*
2504	* @returns VBox status.
2505	* @param pDevIns The device instance to register the ports with.
2506	* @param hIoPorts The I/O port range handle.
2507	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2508	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2509	*/
2510	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2511
2512	/**
2513	* Gets the mapping address of the I/O port range @a hIoPorts.
2514	*
2515	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2516	* parameters).
2517	* @param pDevIns The device instance to register the ports with.
2518	* @param hIoPorts The I/O port range handle.
2519	*/
2520	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2521
2522	/**
2523	* Writes to an I/O port register.
2524	*
2525	* @returns Strict VBox status code. Informational status codes other than the one documented
2526	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2527	* @retval VINF_SUCCESS Success.
2528	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2529	* status code must be passed on to EM.
2530	*
2531	* @param pDevIns The device instance to register the ports with.
2532	* @param Port The port to write to.
2533	* @param u32Value The value to write.
2534	* @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
2535	*
2536	* @thread EMT
2537	* @todo r=aeichner This is only used by DevPCI.cpp to write the ELCR of the PIC. This shouldn't be done that way
2538	* and removed again as soon as possible (no time right now)...
2539	*/
2540	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnIoPortWrite,(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t u32Value, size_t cbValue));
2541	/** @} */
2542
2543	/** @name MMIO
2544	* @{ */
2545	/**
2546	* Creates a memory mapped I/O (MMIO) region for a device.
2547	*
2548	* The MMIO region must be mapped in a separately call. Any ring-0 and
2549	* raw-mode context callback handlers needs to be set up in the respective
2550	* contexts.
2551	*
2552	* @returns VBox status.
2553	* @param pDevIns The device instance to register the ports with.
2554	* @param cbRegion The size of the region in bytes.
2555	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2556	* @param pPciDev The PCI device the range is associated with, if
2557	* applicable.
2558	* @param iPciRegion The PCI device region in the high 16-bit word and
2559	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2560	* @param pfnWrite Pointer to function which is gonna handle Write
2561	* operations.
2562	* @param pfnRead Pointer to function which is gonna handle Read
2563	* operations.
2564	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2565	* operations. (optional)
2566	* @param pvUser User argument to pass to the callbacks.
2567	* @param pszDesc Pointer to description string. This must not be freed.
2568	* @param phRegion Where to return the MMIO region handle.
2569	*
2570	* @remarks Caller enters the device critical section prior to invoking the
2571	* registered callback methods.
2572	*
2573	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2574	*/
2575	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2576	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2577	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2578	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2579
2580	/**
2581	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2582	*
2583	* @returns VBox status.
2584	* @param pDevIns The device instance the region is associated with.
2585	* @param hRegion The MMIO region handle.
2586	* @param GCPhys Where to map the region.
2587	* @note An MMIO range may overlap with base memory if a lot of RAM is
2588	* configured for the VM, in which case we'll drop the base memory
2589	* pages. Presently we will make no attempt to preserve anything that
2590	* happens to be present in the base memory that is replaced, this is
2591	* technically incorrect but it's just not worth the effort to do
2592	* right, at least not at this point.
2593	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2594	* PDMDevHlpMmioSetUpContext
2595	*/
2596	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2597
2598	/**
2599	* Unmaps a memory mapped I/O (MMIO) region.
2600	*
2601	* @returns VBox status.
2602	* @param pDevIns The device instance the region is associated with.
2603	* @param hRegion The MMIO region handle.
2604	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2605	* PDMDevHlpMmioSetUpContext
2606	*/
2607	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2608
2609	/**
2610	* Reduces the length of a MMIO range.
2611	*
2612	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2613	* only work during saved state restore. It will not call the PCI bus code, as
2614	* that is expected to restore the saved resource configuration.
2615	*
2616	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2617	* called it will only map @a cbRegion bytes and not the value set during
2618	* registration.
2619	*
2620	* @return VBox status code.
2621	* @param pDevIns The device owning the range.
2622	* @param hRegion The MMIO region handle.
2623	* @param cbRegion The new size, must be smaller.
2624	*/
2625	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2626
2627	/**
2628	* Gets the mapping address of the MMIO region @a hRegion.
2629	*
2630	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2631	* @param pDevIns The device instance to register the ports with.
2632	* @param hRegion The MMIO region handle.
2633	*/
2634	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2635	/** @} */
2636
2637	/** @name MMIO2
2638	* @{ */
2639	/**
2640	* Creates a MMIO2 region.
2641	*
2642	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2643	* associated with a device. It is also non-shared memory with a permanent
2644	* ring-3 mapping and page backing (presently).
2645	*
2646	* @returns VBox status.
2647	* @param pDevIns The device instance.
2648	* @param pPciDev The PCI device the region is associated with, or
2649	* NULL if no PCI device association.
2650	* @param iPciRegion The region number. Use the PCI region number as
2651	* this must be known to the PCI bus device too. If
2652	* it's not associated with the PCI device, then
2653	* any number up to UINT8_MAX is fine.
2654	* @param cbRegion The size (in bytes) of the region.
2655	* @param fFlags PGMPHYS_MMIO2_FLAGS_XXX (see pgm.h).
2656	* @param pszDesc Pointer to description string. This must not be
2657	* freed.
2658	* @param ppvMapping Where to store the address of the ring-3 mapping
2659	* of the memory.
2660	* @param phRegion Where to return the MMIO2 region handle.
2661	*
2662	* @thread EMT(0)
2663	*/
2664	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2665	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2666
2667	/**
2668	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2669	*
2670	* Any physical access handlers registered for the region must be deregistered
2671	* before calling this function.
2672	*
2673	* @returns VBox status code.
2674	* @param pDevIns The device instance.
2675	* @param hRegion The MMIO2 region handle.
2676	* @thread EMT.
2677	*/
2678	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2679
2680	/**
2681	* Maps a MMIO2 region (into the guest physical address space).
2682	*
2683	* @returns VBox status.
2684	* @param pDevIns The device instance the region is associated with.
2685	* @param hRegion The MMIO2 region handle.
2686	* @param GCPhys Where to map the region.
2687	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2688	* configured for the VM, in which case we'll drop the base memory
2689	* pages. Presently we will make no attempt to preserve anything that
2690	* happens to be present in the base memory that is replaced, this is
2691	* technically incorrect but it's just not worth the effort to do
2692	* right, at least not at this point.
2693	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2694	*/
2695	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2696
2697	/**
2698	* Unmaps a MMIO2 region.
2699	*
2700	* @returns VBox status.
2701	* @param pDevIns The device instance the region is associated with.
2702	* @param hRegion The MMIO2 region handle.
2703	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2704	*/
2705	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2706
2707	/**
2708	* Reduces the length of a MMIO range.
2709	*
2710	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2711	* only work during saved state restore. It will not call the PCI bus code, as
2712	* that is expected to restore the saved resource configuration.
2713	*
2714	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2715	* called it will only map @a cbRegion bytes and not the value set during
2716	* registration.
2717	*
2718	* @return VBox status code.
2719	* @param pDevIns The device owning the range.
2720	* @param hRegion The MMIO2 region handle.
2721	* @param cbRegion The new size, must be smaller.
2722	*/
2723	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2724
2725	/**
2726	* Gets the mapping address of the MMIO region @a hRegion.
2727	*
2728	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2729	* @param pDevIns The device instance to register the ports with.
2730	* @param hRegion The MMIO2 region handle.
2731	*/
2732	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2733
2734	/**
2735	* Queries and resets the dirty bitmap for an MMIO2 region.
2736	*
2737	* The MMIO2 region must have been created with the
2738	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
2739	*
2740	* @returns VBox status code.
2741	* @param pDevIns The device instance.
2742	* @param hRegion The MMIO2 region handle.
2743	* @param pvBitmap Where to return the bitmap. Must be 8-byte aligned.
2744	* Can be NULL if only resetting the tracking is desired.
2745	* @param cbBitmap The bitmap size. One bit per page in the region,
2746	* rounded up to 8-bytes. If pvBitmap is NULL this must
2747	* also be zero.
2748	*/
2749	DECLR3CALLBACKMEMBER(int, pfnMmio2QueryAndResetDirtyBitmap, (PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
2750	void *pvBitmap, size_t cbBitmap));
2751
2752	/**
2753	* Controls the dirty page tracking for an MMIO2 region.
2754	*
2755	* The MMIO2 region must have been created with the
2756	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
2757	*
2758	* @returns VBox status code.
2759	* @param pDevIns The device instance.
2760	* @param hRegion The MMIO2 region handle.
2761	* @param fEnabled When set to @c true the dirty page tracking will be
2762	* enabled if currently disabled (bitmap is reset). When
2763	* set to @c false the dirty page tracking will be
2764	* disabled.
2765	*/
2766	DECLR3CALLBACKMEMBER(int, pfnMmio2ControlDirtyPageTracking, (PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, bool fEnabled));
2767
2768	/**
2769	* Changes the number of an MMIO2 or pre-registered MMIO region.
2770	*
2771	* This should only be used to deal with saved state problems, so there is no
2772	* convenience inline wrapper for this method.
2773	*
2774	* @returns VBox status code.
2775	* @param pDevIns The device instance.
2776	* @param hRegion The MMIO2 region handle.
2777	* @param iNewRegion The new region index.
2778	*
2779	* @sa @bugref{9359}
2780	*/
2781	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2782
2783	/**
2784	* Mapping an MMIO2 page in place of an MMIO page for direct access.
2785	*
2786	* This is a special optimization used by the VGA device. Call
2787	* PDMDevHlpMmioResetRegion() to undo the mapping.
2788	*
2789	* @returns VBox status code. This API may return VINF_SUCCESS even if no
2790	* remapping is made.
2791	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
2792	*
2793	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
2794	* associated with.
2795	* @param hRegion The handle to the MMIO region.
2796	* @param offRegion The offset into @a hRegion of the page to be
2797	* remapped.
2798	* @param hMmio2 The MMIO2 handle.
2799	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
2800	* mapping.
2801	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
2802	* for the time being.
2803	*/
2804	DECLR3CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
2805	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
2806
2807	/**
2808	* Reset a previously modified MMIO region; restore the access flags.
2809	*
2810	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
2811	* intended for some ancient VGA hack. However, it would be great to extend it
2812	* beyond VT-x and/or nested-paging.
2813	*
2814	* @returns VBox status code.
2815	*
2816	* @param pDevIns The device instance @a hRegion is associated with.
2817	* @param hRegion The handle to the MMIO region.
2818	*/
2819	DECLR3CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2820	/** @} */
2821
2822	/**
2823	* Register a ROM (BIOS) region.
2824	*
2825	* It goes without saying that this is read-only memory. The memory region must be
2826	* in unassigned memory. I.e. from the top of the address space or on the PC in
2827	* the 0xa0000-0xfffff range.
2828	*
2829	* @returns VBox status.
2830	* @param pDevIns The device instance owning the ROM region.
2831	* @param GCPhysStart First physical address in the range.
2832	* Must be page aligned!
2833	* @param cbRange The size of the range (in bytes).
2834	* Must be page aligned!
2835	* @param pvBinary Pointer to the binary data backing the ROM image.
2836	* @param cbBinary The size of the binary pointer. This must
2837	* be equal or smaller than @a cbRange.
2838	* @param fFlags PGMPHYS_ROM_FLAGS_XXX (see pgm.h).
2839	* @param pszDesc Pointer to description string. This must not be freed.
2840	*
2841	* @remark There is no way to remove the rom, automatically on device cleanup or
2842	* manually from the device yet. At present I doubt we need such features...
2843	*/
2844	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2845	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2846
2847	/**
2848	* Changes the protection of shadowed ROM mapping.
2849	*
2850	* This is intented for use by the system BIOS, chipset or device in question to
2851	* change the protection of shadowed ROM code after init and on reset.
2852	*
2853	* @param pDevIns The device instance.
2854	* @param GCPhysStart Where the mapping starts.
2855	* @param cbRange The size of the mapping.
2856	* @param enmProt The new protection type.
2857	*/
2858	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2859
2860	/**
2861	* Register a save state data unit.
2862	*
2863	* @returns VBox status.
2864	* @param pDevIns The device instance.
2865	* @param uVersion Data layout version number.
2866	* @param cbGuess The approximate amount of data in the unit.
2867	* Only for progress indicators.
2868	* @param pszBefore Name of data unit which we should be put in
2869	* front of. Optional (NULL).
2870	*
2871	* @param pfnLivePrep Prepare live save callback, optional.
2872	* @param pfnLiveExec Execute live save callback, optional.
2873	* @param pfnLiveVote Vote live save callback, optional.
2874	*
2875	* @param pfnSavePrep Prepare save callback, optional.
2876	* @param pfnSaveExec Execute save callback, optional.
2877	* @param pfnSaveDone Done save callback, optional.
2878	*
2879	* @param pfnLoadPrep Prepare load callback, optional.
2880	* @param pfnLoadExec Execute load callback, optional.
2881	* @param pfnLoadDone Done load callback, optional.
2882	* @remarks Caller enters the device critical section prior to invoking the
2883	* registered callback methods.
2884	*/
2885	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2886	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2887	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2888	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2889
2890	/**
2891	* Register a save state data unit for backward compatibility.
2892	*
2893	* This is for migrating from an old device name to a new one or for merging
2894	* devices. It will only help loading old saved states.
2895	*
2896	* @returns VBox status.
2897	* @param pDevIns The device instance.
2898	* @param pszOldName The old unit name.
2899	* @param pfnLoadPrep Prepare load callback, optional.
2900	* @param pfnLoadExec Execute load callback, optional.
2901	* @param pfnLoadDone Done load callback, optional.
2902	* @remarks Caller enters the device critical section prior to invoking the
2903	* registered callback methods.
2904	*/
2905	DECLR3CALLBACKMEMBER(int, pfnSSMRegisterLegacy,(PPDMDEVINS pDevIns, const char *pszOldName, PFNSSMDEVLOADPREP pfnLoadPrep,
2906	PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2907
2908	/** @name Exported SSM Functions
2909	* @{ */
2910	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2911	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2912	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2913	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2914	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2915	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2916	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2917	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2918	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2919	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2920	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2921	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2922	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2923	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2924	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2925	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2926	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2927	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2928	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2929	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2930	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2931	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2932	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2933	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2934	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2935	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2936	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2937	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2938	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2939	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2940	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2941	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2942	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2943	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2944	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2945	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2946	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2947	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2948	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2949	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2950	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2951	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2952	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2953	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2954	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2955	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2956	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2957	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2958	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2959	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2960	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2961	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2962	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2963	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2964	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2965	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2966	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2967	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2968	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2969	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2970	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2971	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2972	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2973	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2974	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2975	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2976	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2977	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2978	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2979	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2980	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2981	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2982	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2983	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2984	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2985	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2986	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2987	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2988	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2989	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2990	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2991	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2992	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2993	/** @} */
2994
2995	/**
2996	* Creates a timer w/ a cross context handle.
2997	*
2998	* @returns VBox status.
2999	* @param pDevIns The device instance.
3000	* @param enmClock The clock to use on this timer.
3001	* @param pfnCallback Callback function.
3002	* @param pvUser User argument for the callback.
3003	* @param fFlags Flags, see TMTIMER_FLAGS_*.
3004	* @param pszDesc Pointer to description string which must stay around
3005	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
3006	* @param phTimer Where to store the timer handle on success.
3007	* @remarks Caller enters the device critical section prior to invoking the
3008	* callback.
3009	*/
3010	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
3011	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
3012
3013	/** @name Timer handle method wrappers
3014	* @{ */
3015	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
3016	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
3017	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
3018	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3019	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3020	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3021	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3022	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3023	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
3024	/** Takes the clock lock then enters the specified critical section. */
3025	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
3026	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
3027	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
3028	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
3029	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
3030	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
3031	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
3032	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3033	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3034	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
3035	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
3036	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3037	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3038	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3039	/** @sa TMR3TimerSkip */
3040	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
3041	/** @} */
3042
3043	/**
3044	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
3045	*
3046	* @returns pTime.
3047	* @param pDevIns The device instance.
3048	* @param pTime Where to store the time.
3049	*/
3050	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
3051
3052	/** @name Exported CFGM Functions.
3053	* @{ */
3054	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
3055	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
3056	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
3057	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3058	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3059	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
3060	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
3061	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPassword,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
3062	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPasswordDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
3063	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
3064	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3065	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3066	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
3067	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
3068	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
3069	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
3070	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
3071	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
3072	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
3073	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
3074	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
3075	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
3076	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
3077	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
3078	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
3079	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
3080	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
3081	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
3082	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
3083	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
3084	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
3085	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
3086	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
3087	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
3088	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
3089	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
3090	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
3091	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
3092	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
3093	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
3094	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
3095	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
3096	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
3097	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
3098	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
3099	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
3100	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
3101	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
3102	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
3103	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
3104	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
3105	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
3106	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
3107	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
3108	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
3109	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
3110	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
3111	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
3112	const char pszValidValues, const char pszValidNodes,
3113	const char *pszWho, uint32_t uInstance));
3114	/** @} */
3115
3116	/**
3117	* Read physical memory.
3118	*
3119	* @returns VINF_SUCCESS (for now).
3120	* @param pDevIns The device instance.
3121	* @param GCPhys Physical address start reading from.
3122	* @param pvBuf Where to put the read bits.
3123	* @param cbRead How many bytes to read.
3124	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3125	* @thread Any thread, but the call may involve the emulation thread.
3126	*/
3127	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3128
3129	/**
3130	* Write to physical memory.
3131	*
3132	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3133	* @param pDevIns The device instance.
3134	* @param GCPhys Physical address to write to.
3135	* @param pvBuf What to write.
3136	* @param cbWrite How many bytes to write.
3137	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3138	* @thread Any thread, but the call may involve the emulation thread.
3139	*/
3140	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3141
3142	/**
3143	* Requests the mapping of a guest page into ring-3.
3144	*
3145	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3146	* release it.
3147	*
3148	* This API will assume your intention is to write to the page, and will
3149	* therefore replace shared and zero pages. If you do not intend to modify the
3150	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3151	*
3152	* @returns VBox status code.
3153	* @retval VINF_SUCCESS on success.
3154	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3155	* backing or if the page has any active access handlers. The caller
3156	* must fall back on using PGMR3PhysWriteExternal.
3157	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3158	*
3159	* @param pDevIns The device instance.
3160	* @param GCPhys The guest physical address of the page that
3161	* should be mapped.
3162	* @param fFlags Flags reserved for future use, MBZ.
3163	* @param ppv Where to store the address corresponding to
3164	* GCPhys.
3165	* @param pLock Where to store the lock information that
3166	* pfnPhysReleasePageMappingLock needs.
3167	*
3168	* @remark Avoid calling this API from within critical sections (other than the
3169	* PGM one) because of the deadlock risk when we have to delegating the
3170	* task to an EMT.
3171	* @thread Any.
3172	*/
3173	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3174	PPGMPAGEMAPLOCK pLock));
3175
3176	/**
3177	* Requests the mapping of a guest page into ring-3, external threads.
3178	*
3179	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3180	* release it.
3181	*
3182	* @returns VBox status code.
3183	* @retval VINF_SUCCESS on success.
3184	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3185	* backing or if the page as an active ALL access handler. The caller
3186	* must fall back on using PGMPhysRead.
3187	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3188	*
3189	* @param pDevIns The device instance.
3190	* @param GCPhys The guest physical address of the page that
3191	* should be mapped.
3192	* @param fFlags Flags reserved for future use, MBZ.
3193	* @param ppv Where to store the address corresponding to
3194	* GCPhys.
3195	* @param pLock Where to store the lock information that
3196	* pfnPhysReleasePageMappingLock needs.
3197	*
3198	* @remark Avoid calling this API from within critical sections.
3199	* @thread Any.
3200	*/
3201	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3202	void const **ppv, PPGMPAGEMAPLOCK pLock));
3203
3204	/**
3205	* Release the mapping of a guest page.
3206	*
3207	* This is the counter part of pfnPhysGCPhys2CCPtr and
3208	* pfnPhysGCPhys2CCPtrReadOnly.
3209	*
3210	* @param pDevIns The device instance.
3211	* @param pLock The lock structure initialized by the mapping
3212	* function.
3213	*/
3214	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3215
3216	/**
3217	* Read guest physical memory by virtual address.
3218	*
3219	* @param pDevIns The device instance.
3220	* @param pvDst Where to put the read bits.
3221	* @param GCVirtSrc Guest virtual address to start reading from.
3222	* @param cb How many bytes to read.
3223	* @thread The emulation thread.
3224	*/
3225	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3226
3227	/**
3228	* Write to guest physical memory by virtual address.
3229	*
3230	* @param pDevIns The device instance.
3231	* @param GCVirtDst Guest virtual address to write to.
3232	* @param pvSrc What to write.
3233	* @param cb How many bytes to write.
3234	* @thread The emulation thread.
3235	*/
3236	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3237
3238	/**
3239	* Convert a guest virtual address to a guest physical address.
3240	*
3241	* @returns VBox status code.
3242	* @param pDevIns The device instance.
3243	* @param GCPtr Guest virtual address.
3244	* @param pGCPhys Where to store the GC physical address
3245	* corresponding to GCPtr.
3246	* @thread The emulation thread.
3247	* @remark Careful with page boundaries.
3248	*/
3249	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3250
3251	/**
3252	* Checks if a GC physical address is a normal page,
3253	* i.e. not ROM, MMIO or reserved.
3254	*
3255	* @returns true if normal.
3256	* @returns false if invalid, ROM, MMIO or reserved page.
3257	* @param pDevIns The device instance.
3258	* @param GCPhys The physical address to check.
3259	*/
3260	DECLR3CALLBACKMEMBER(bool, pfnPhysIsGCPhysNormal,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
3261
3262	/**
3263	* Inflate or deflate a memory balloon
3264	*
3265	* @returns VBox status code.
3266	* @param pDevIns The device instance.
3267	* @param fInflate Inflate or deflate memory balloon
3268	* @param cPages Number of pages to free
3269	* @param paPhysPage Array of guest physical addresses
3270	*/
3271	DECLR3CALLBACKMEMBER(int, pfnPhysChangeMemBalloon,(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage));
3272
3273	/**
3274	* Allocate memory which is associated with current VM instance
3275	* and automatically freed on it's destruction.
3276	*
3277	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3278	* @param pDevIns The device instance.
3279	* @param cb Number of bytes to allocate.
3280	*/
3281	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3282
3283	/**
3284	* Allocate memory which is associated with current VM instance
3285	* and automatically freed on it's destruction. The memory is ZEROed.
3286	*
3287	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3288	* @param pDevIns The device instance.
3289	* @param cb Number of bytes to allocate.
3290	*/
3291	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3292
3293	/**
3294	* Allocating string printf.
3295	*
3296	* @returns Pointer to the string.
3297	* @param pDevIns The device instance.
3298	* @param enmTag The statistics tag.
3299	* @param pszFormat The format string.
3300	* @param va Format arguments.
3301	*/
3302	DECLR3CALLBACKMEMBER(char , pfnMMHeapAPrintfV,(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, va_list va));
3303
3304	/**
3305	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3306	*
3307	* @param pDevIns The device instance.
3308	* @param pv Pointer to the memory to free.
3309	*/
3310	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3311
3312	/**
3313	* Returns the physical RAM size of the VM.
3314	*
3315	* @returns RAM size in bytes.
3316	* @param pDevIns The device instance.
3317	*/
3318	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSize,(PPDMDEVINS pDevIns));
3319
3320	/**
3321	* Returns the physical RAM size of the VM below the 4GB boundary.
3322	*
3323	* @returns RAM size in bytes.
3324	* @param pDevIns The device instance.
3325	*/
3326	DECLR3CALLBACKMEMBER(uint32_t, pfnMMPhysGetRamSizeBelow4GB,(PPDMDEVINS pDevIns));
3327
3328	/**
3329	* Returns the physical RAM size of the VM above the 4GB boundary.
3330	*
3331	* @returns RAM size in bytes.
3332	* @param pDevIns The device instance.
3333	*/
3334	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSizeAbove4GB,(PPDMDEVINS pDevIns));
3335
3336	/**
3337	* Gets the VM state.
3338	*
3339	* @returns VM state.
3340	* @param pDevIns The device instance.
3341	* @thread Any thread (just keep in mind that it's volatile info).
3342	*/
3343	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3344
3345	/**
3346	* Checks if the VM was teleported and hasn't been fully resumed yet.
3347	*
3348	* @returns true / false.
3349	* @param pDevIns The device instance.
3350	* @thread Any thread.
3351	*/
3352	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3353
3354	/**
3355	* Set the VM error message
3356	*
3357	* @returns rc.
3358	* @param pDevIns The device instance.
3359	* @param rc VBox status code.
3360	* @param SRC_POS Use RT_SRC_POS.
3361	* @param pszFormat Error message format string.
3362	* @param va Error message arguments.
3363	*/
3364	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3365	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3366
3367	/**
3368	* Set the VM runtime error message
3369	*
3370	* @returns VBox status code.
3371	* @param pDevIns The device instance.
3372	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3373	* @param pszErrorId Error ID string.
3374	* @param pszFormat Error message format string.
3375	* @param va Error message arguments.
3376	*/
3377	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3378	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3379
3380	/**
3381	* Special interface for implementing a HLT-like port on a device.
3382	*
3383	* This can be called directly from device code, provide the device is trusted
3384	* to access the VMM directly. Since we may not have an accurate register set
3385	* and the caller certainly shouldn't (device code does not access CPU
3386	* registers), this function will return when interrupts are pending regardless
3387	* of the actual EFLAGS.IF state.
3388	*
3389	* @returns VBox error status (never informational statuses).
3390	* @param pDevIns The device instance.
3391	* @param idCpu The id of the calling EMT.
3392	*/
3393	DECLR3CALLBACKMEMBER(int, pfnVMWaitForDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3394
3395	/**
3396	* Wakes up a CPU that has called PDMDEVHLPR3::pfnVMWaitForDeviceReady.
3397	*
3398	* @returns VBox error status (never informational statuses).
3399	* @param pDevIns The device instance.
3400	* @param idCpu The id of the calling EMT.
3401	*/
3402	DECLR3CALLBACKMEMBER(int, pfnVMNotifyCpuDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3403
3404	/**
3405	* Convenience wrapper for VMR3ReqCallU.
3406	*
3407	* This assumes (1) you're calling a function that returns an VBox status code
3408	* and that you do not wish to wait for it to complete.
3409	*
3410	* @returns VBox status code returned by VMR3ReqCallVU.
3411	*
3412	* @param pDevIns The device instance.
3413	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3414	* one of the following special values:
3415	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3416	* @param pfnFunction Pointer to the function to call.
3417	* @param cArgs Number of arguments following in the ellipsis.
3418	* @param Args Argument vector.
3419	*
3420	* @remarks See remarks on VMR3ReqCallVU.
3421	*/
3422	DECLR3CALLBACKMEMBER(int, pfnVMReqCallNoWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3423
3424	/**
3425	* Convenience wrapper for VMR3ReqCallU.
3426	*
3427	* This assumes (1) you're calling a function that returns void, (2) that you
3428	* wish to wait for ever for it to return, and (3) that it's priority request
3429	* that can be safely be handled during async suspend and power off.
3430	*
3431	* @returns VBox status code of VMR3ReqCallVU.
3432	*
3433	* @param pDevIns The device instance.
3434	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3435	* one of the following special values:
3436	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3437	* @param pfnFunction Pointer to the function to call.
3438	* @param cArgs Number of arguments following in the ellipsis.
3439	* @param Args Argument vector.
3440	*
3441	* @remarks See remarks on VMR3ReqCallVU.
3442	*/
3443	DECLR3CALLBACKMEMBER(int, pfnVMReqPriorityCallWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3444
3445	/**
3446	* Stops the VM and enters the debugger to look at the guest state.
3447	*
3448	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3449	* invoking this function directly.
3450	*
3451	* @returns VBox status code which must be passed up to the VMM.
3452	* @param pDevIns The device instance.
3453	* @param pszFile Filename of the assertion location.
3454	* @param iLine The linenumber of the assertion location.
3455	* @param pszFunction Function of the assertion location.
3456	* @param pszFormat Message. (optional)
3457	* @param args Message parameters.
3458	*/
3459	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3460	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3461
3462	/**
3463	* Register a info handler with DBGF.
3464	*
3465	* @returns VBox status code.
3466	* @param pDevIns The device instance.
3467	* @param pszName The identifier of the info.
3468	* @param pszDesc The description of the info and any arguments
3469	* the handler may take.
3470	* @param pfnHandler The handler function to be called to display the
3471	* info.
3472	*/
3473	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3474
3475	/**
3476	* Register a info handler with DBGF, argv style.
3477	*
3478	* @returns VBox status code.
3479	* @param pDevIns The device instance.
3480	* @param pszName The identifier of the info.
3481	* @param pszDesc The description of the info and any arguments
3482	* the handler may take.
3483	* @param pfnHandler The handler function to be called to display the
3484	* info.
3485	*/
3486	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3487
3488	/**
3489	* Registers a set of registers for a device.
3490	*
3491	* The @a pvUser argument of the getter and setter callbacks will be
3492	* @a pDevIns. The register names will be prefixed by the device name followed
3493	* immediately by the instance number.
3494	*
3495	* @returns VBox status code.
3496	* @param pDevIns The device instance.
3497	* @param paRegisters The register descriptors.
3498	*
3499	* @remarks The device critical section is NOT entered prior to working the
3500	* callbacks registered via this helper!
3501	*/
3502	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3503
3504	/**
3505	* Gets the trace buffer handle.
3506	*
3507	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3508	* really inteded for direct usage, thus no inline wrapper function.
3509	*
3510	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3511	* @param pDevIns The device instance.
3512	*/
3513	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3514
3515	/**
3516	* Report a bug check.
3517	*
3518	* @returns
3519	* @param pDevIns The device instance.
3520	* @param enmEvent The kind of BSOD event this is.
3521	* @param uBugCheck The bug check number.
3522	* @param uP1 The bug check parameter \#1.
3523	* @param uP2 The bug check parameter \#2.
3524	* @param uP3 The bug check parameter \#3.
3525	* @param uP4 The bug check parameter \#4.
3526	*
3527	* @thread EMT
3528	*/
3529	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnDBGFReportBugCheck,(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
3530	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4));
3531
3532	/**
3533	* Write core dump of the guest.
3534	*
3535	* @returns VBox status code.
3536	* @param pDevIns The device instance.
3537	* @param pszFilename The name of the file to which the guest core
3538	* dump should be written.
3539	* @param fReplaceFile Whether to replace the file or not.
3540	*
3541	* @remarks The VM may need to be suspended before calling this function in
3542	* order to truly stop all device threads and drivers. This function
3543	* only synchronizes EMTs.
3544	*/
3545	DECLR3CALLBACKMEMBER(int, pfnDBGFCoreWrite,(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile));
3546
3547	/**
3548	* Gets the logger info helper.
3549	* The returned info helper will unconditionally write all output to the log.
3550	*
3551	* @returns Pointer to the logger info helper.
3552	* @param pDevIns The device instance.
3553	*/
3554	DECLR3CALLBACKMEMBER(PCDBGFINFOHLP, pfnDBGFInfoLogHlp,(PPDMDEVINS pDevIns));
3555
3556	/**
3557	* Queries a 64-bit register value.
3558	*
3559	* @retval VINF_SUCCESS
3560	* @retval VERR_INVALID_VM_HANDLE
3561	* @retval VERR_INVALID_CPU_ID
3562	* @retval VERR_DBGF_REGISTER_NOT_FOUND
3563	* @retval VERR_DBGF_UNSUPPORTED_CAST
3564	* @retval VINF_DBGF_TRUNCATED_REGISTER
3565	* @retval VINF_DBGF_ZERO_EXTENDED_REGISTER
3566	*
3567	* @param pDevIns The device instance.
3568	* @param idDefCpu The default target CPU ID, VMCPUID_ANY if not
3569	* applicable. Can be OR'ed with
3570	* DBGFREG_HYPER_VMCPUID.
3571	* @param pszReg The register that's being queried. Except for
3572	* CPU registers, this must be on the form
3573	* "set.reg[.sub]".
3574	* @param pu64 Where to store the register value.
3575	*/
3576	DECLR3CALLBACKMEMBER(int, pfnDBGFRegNmQueryU64,(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64));
3577
3578	/**
3579	* Format a set of registers.
3580	*
3581	* This is restricted to registers from one CPU, that specified by @a idCpu.
3582	*
3583	* @returns VBox status code.
3584	* @param pDevIns The device instance.
3585	* @param idCpu The CPU ID of any CPU registers that may be
3586	* printed, pass VMCPUID_ANY if not applicable.
3587	* @param pszBuf The output buffer.
3588	* @param cbBuf The size of the output buffer.
3589	* @param pszFormat The format string. Register names are given by
3590	* %VR{name}, they take no arguments.
3591	* @param va Other format arguments.
3592	*/
3593	DECLR3CALLBACKMEMBER(int, pfnDBGFRegPrintfV,(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
3594	const char *pszFormat, va_list va));
3595
3596	/**
3597	* Registers a statistics sample.
3598	*
3599	* @param pDevIns Device instance of the DMA.
3600	* @param pvSample Pointer to the sample.
3601	* @param enmType Sample type. This indicates what pvSample is
3602	* pointing at.
3603	* @param pszName Sample name, unix path style. If this does not
3604	* start with a '/', the default prefix will be
3605	* prepended, otherwise it will be used as-is.
3606	* @param enmUnit Sample unit.
3607	* @param pszDesc Sample description.
3608	*/
3609	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3610
3611	/**
3612	* Same as pfnSTAMRegister except that the name is specified in a
3613	* RTStrPrintfV like fashion.
3614	*
3615	* @returns VBox status.
3616	* @param pDevIns Device instance of the DMA.
3617	* @param pvSample Pointer to the sample.
3618	* @param enmType Sample type. This indicates what pvSample is
3619	* pointing at.
3620	* @param enmVisibility Visibility type specifying whether unused
3621	* statistics should be visible or not.
3622	* @param enmUnit Sample unit.
3623	* @param pszDesc Sample description.
3624	* @param pszName Sample name format string, unix path style. If
3625	* this does not start with a '/', the default
3626	* prefix will be prepended, otherwise it will be
3627	* used as-is.
3628	* @param args Arguments to the format string.
3629	*/
3630	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3631	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3632	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3633
3634	/**
3635	* Registers a PCI device with the default PCI bus.
3636	*
3637	* If a PDM device has more than one PCI device, they must be registered in the
3638	* order of PDMDEVINSR3::apPciDevs.
3639	*
3640	* @returns VBox status code.
3641	* @param pDevIns The device instance.
3642	* @param pPciDev The PCI device structure.
3643	* This must be kept in the instance data.
3644	* The PCI configuration must be initialized before registration.
3645	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3646	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3647	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3648	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3649	* device number (0-31). This will be ignored if
3650	* the CFGM configuration contains a PCIDeviceNo
3651	* value.
3652	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3653	* function number (0-7). This will be ignored if
3654	* the CFGM configuration contains a PCIFunctionNo
3655	* value.
3656	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3657	* The pointer is saved, so don't free or changed.
3658	* @note The PCI device configuration is now implicit from the apPciDevs
3659	* index, meaning that the zero'th entry is the primary one and
3660	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3661	*/
3662	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3663	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3664
3665	/**
3666	* Initialize MSI or MSI-X emulation support for the given PCI device.
3667	*
3668	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3669	*
3670	* @returns VBox status code.
3671	* @param pDevIns The device instance.
3672	* @param pPciDev The PCI device. NULL is an alias for the first
3673	* one registered.
3674	* @param pMsiReg MSI emulation registration structure.
3675	*/
3676	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3677
3678	/**
3679	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3680	*
3681	* @returns VBox status code.
3682	* @param pDevIns The device instance.
3683	* @param pPciDev The PCI device structure. If NULL the default
3684	* PCI device for this device instance is used.
3685	* @param iRegion The region number.
3686	* @param cbRegion Size of the region.
3687	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3688	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3689	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3690	* @a fFlags, UINT64_MAX if no handle is passed
3691	* (old style).
3692	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3693	* handle is specified. The callback will be
3694	* invoked holding only the PDM lock. The device
3695	* lock will _not_ be taken (due to lock order).
3696	*/
3697	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3698	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3699	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3700
3701	/**
3702	* Register PCI configuration space read/write callbacks.
3703	*
3704	* @returns VBox status code.
3705	* @param pDevIns The device instance.
3706	* @param pPciDev The PCI device structure. If NULL the default
3707	* PCI device for this device instance is used.
3708	* @param pfnRead Pointer to the user defined PCI config read function.
3709	* to call default PCI config read function. Can be NULL.
3710	* @param pfnWrite Pointer to the user defined PCI config write function.
3711	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3712	* is NOT take because that is very likely be a lock order violation.
3713	* @thread EMT(0)
3714	* @note Only callable during VM creation.
3715	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3716	*/
3717	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3718	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3719
3720	/**
3721	* Perform a PCI configuration space write.
3722	*
3723	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3724	*
3725	* @returns Strict VBox status code (mainly DBGFSTOP).
3726	* @param pDevIns The device instance.
3727	* @param pPciDev The PCI device which config space is being read.
3728	* @param uAddress The config space address.
3729	* @param cb The size of the read: 1, 2 or 4 bytes.
3730	* @param u32Value The value to write.
3731	*/
3732	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3733	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3734
3735	/**
3736	* Perform a PCI configuration space read.
3737	*
3738	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3739	*
3740	* @returns Strict VBox status code (mainly DBGFSTOP).
3741	* @param pDevIns The device instance.
3742	* @param pPciDev The PCI device which config space is being read.
3743	* @param uAddress The config space address.
3744	* @param cb The size of the read: 1, 2 or 4 bytes.
3745	* @param pu32Value Where to return the value.
3746	*/
3747	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3748	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3749
3750	/**
3751	* Bus master physical memory read.
3752	*
3753	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3754	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3755	* @param pDevIns The device instance.
3756	* @param pPciDev The PCI device structure. If NULL the default
3757	* PCI device for this device instance is used.
3758	* @param GCPhys Physical address start reading from.
3759	* @param pvBuf Where to put the read bits.
3760	* @param cbRead How many bytes to read.
3761	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3762	* @thread Any thread, but the call may involve the emulation thread.
3763	*/
3764	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3765
3766	/**
3767	* Bus master physical memory write.
3768	*
3769	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3770	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3771	* @param pDevIns The device instance.
3772	* @param pPciDev The PCI device structure. If NULL the default
3773	* PCI device for this device instance is used.
3774	* @param GCPhys Physical address to write to.
3775	* @param pvBuf What to write.
3776	* @param cbWrite How many bytes to write.
3777	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3778	* @thread Any thread, but the call may involve the emulation thread.
3779	*/
3780	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3781
3782	/**
3783	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3784	* physical memory write operation.
3785	*
3786	* Refer pfnPhysGCPhys2CCPtr() for further details.
3787	*
3788	* @returns VBox status code.
3789	* @param pDevIns The device instance.
3790	* @param pPciDev The PCI device structure. If NULL the default
3791	* PCI device for this device instance is used.
3792	* @param GCPhys The guest physical address of the page that should be
3793	* mapped.
3794	* @param fFlags Flags reserved for future use, MBZ.
3795	* @param ppv Where to store the address corresponding to GCPhys.
3796	* @param pLock Where to store the lock information that
3797	* pfnPhysReleasePageMappingLock needs.
3798	*
3799	* @remarks Avoid calling this API from within critical sections (other than the PGM
3800	* one) because of the deadlock risk when we have to delegating the task to
3801	* an EMT.
3802	* @thread Any.
3803	*/
3804	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3805	void **ppv, PPGMPAGEMAPLOCK pLock));
3806
3807	/**
3808	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3809	* for a bus master physical memory read operation.
3810	*
3811	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3812	*
3813	* @returns VBox status code.
3814	* @param pDevIns The device instance.
3815	* @param pPciDev The PCI device structure. If NULL the default
3816	* PCI device for this device instance is used.
3817	* @param GCPhys The guest physical address of the page that
3818	* should be mapped.
3819	* @param fFlags Flags reserved for future use, MBZ.
3820	* @param ppv Where to store the address corresponding to
3821	* GCPhys.
3822	* @param pLock Where to store the lock information that
3823	* pfnPhysReleasePageMappingLock needs.
3824	*
3825	* @remarks Avoid calling this API from within critical sections.
3826	* @thread Any.
3827	*/
3828	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3829	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3830
3831	/**
3832	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3833	* master physical memory write operation.
3834	*
3835	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3836	* ASAP to release them.
3837	*
3838	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3839	*
3840	* @returns VBox status code.
3841	* @param pDevIns The device instance.
3842	* @param pPciDev The PCI device structure. If NULL the default
3843	* PCI device for this device instance is used.
3844	* @param cPages Number of pages to lock.
3845	* @param paGCPhysPages The guest physical address of the pages that
3846	* should be mapped (@a cPages entries).
3847	* @param fFlags Flags reserved for future use, MBZ.
3848	* @param papvPages Where to store the ring-3 mapping addresses
3849	* corresponding to @a paGCPhysPages.
3850	* @param paLocks Where to store the locking information that
3851	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3852	* in length).
3853	*/
3854	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3855	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3856	PPGMPAGEMAPLOCK paLocks));
3857
3858	/**
3859	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3860	* master physical memory read operation.
3861	*
3862	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3863	* ASAP to release them.
3864	*
3865	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3866	*
3867	* @returns VBox status code.
3868	* @param pDevIns The device instance.
3869	* @param pPciDev The PCI device structure. If NULL the default
3870	* PCI device for this device instance is used.
3871	* @param cPages Number of pages to lock.
3872	* @param paGCPhysPages The guest physical address of the pages that
3873	* should be mapped (@a cPages entries).
3874	* @param fFlags Flags reserved for future use, MBZ.
3875	* @param papvPages Where to store the ring-3 mapping addresses
3876	* corresponding to @a paGCPhysPages.
3877	* @param paLocks Where to store the lock information that
3878	* pfnPhysReleasePageMappingLock needs (@a cPages
3879	* in length).
3880	*/
3881	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3882	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3883	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3884
3885	/**
3886	* Sets the IRQ for the given PCI device.
3887	*
3888	* @param pDevIns The device instance.
3889	* @param pPciDev The PCI device structure. If NULL the default
3890	* PCI device for this device instance is used.
3891	* @param iIrq IRQ number to set.
3892	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3893	* @thread Any thread, but will involve the emulation thread.
3894	*/
3895	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3896
3897	/**
3898	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3899	* the request when not called from EMT.
3900	*
3901	* @param pDevIns The device instance.
3902	* @param pPciDev The PCI device structure. If NULL the default
3903	* PCI device for this device instance is used.
3904	* @param iIrq IRQ number to set.
3905	* @param iLevel IRQ level.
3906	* @thread Any thread, but will involve the emulation thread.
3907	*/
3908	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3909
3910	/**
3911	* Set ISA IRQ for a device.
3912	*
3913	* @param pDevIns The device instance.
3914	* @param iIrq IRQ number to set.
3915	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3916	* @thread Any thread, but will involve the emulation thread.
3917	*/
3918	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3919
3920	/**
3921	* Set the ISA IRQ for a device, but don't wait for EMT to process
3922	* the request when not called from EMT.
3923	*
3924	* @param pDevIns The device instance.
3925	* @param iIrq IRQ number to set.
3926	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3927	* @thread Any thread, but will involve the emulation thread.
3928	*/
3929	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3930
3931	/**
3932	* Attaches a driver (chain) to the device.
3933	*
3934	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3935	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3936	*
3937	* @returns VBox status code.
3938	* @param pDevIns The device instance.
3939	* @param iLun The logical unit to attach.
3940	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3941	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3942	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3943	* for the live of the device instance.
3944	*/
3945	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3946	PPDMIBASE ppBaseInterface, const char pszDesc));
3947
3948	/**
3949	* Detaches an attached driver (chain) from the device again.
3950	*
3951	* @returns VBox status code.
3952	* @param pDevIns The device instance.
3953	* @param pDrvIns The driver instance to detach.
3954	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3955	*/
3956	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3957
3958	/**
3959	* Reconfigures the driver chain for a LUN, detaching any driver currently
3960	* present there.
3961	*
3962	* Caller will have attach it, of course.
3963	*
3964	* @returns VBox status code.
3965	* @param pDevIns The device instance.
3966	* @param iLun The logical unit to reconfigure.
3967	* @param cDepth The depth of the driver chain. Determins the
3968	* size of @a papszDrivers and @a papConfigs.
3969	* @param papszDrivers The names of the drivers to configure in the
3970	* chain, first entry is the one immediately
3971	* below the device/LUN
3972	* @param papConfigs The configurations for each of the drivers
3973	* in @a papszDrivers array. NULL entries
3974	* corresponds to empty 'Config' nodes. This
3975	* function will take ownership of non-NULL
3976	* CFGM sub-trees and set the array member to
3977	* NULL, so the caller can do cleanups on
3978	* failure. This parameter is optional.
3979	* @param fFlags Reserved, MBZ.
3980	*/
3981	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3982	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3983
3984	/** @name Exported PDM Queue Functions
3985	* @{ */
3986	/**
3987	* Create a queue.
3988	*
3989	* @returns VBox status code.
3990	* @param pDevIns The device instance.
3991	* @param cbItem The size of a queue item.
3992	* @param cItems The number of items in the queue.
3993	* @param cMilliesInterval The number of milliseconds between polling the queue.
3994	* If 0 then the emulation thread will be notified whenever an item arrives.
3995	* @param pfnCallback The consumer function.
3996	* @param fRZEnabled Set if the queue should work in RC and R0.
3997	* @param pszName The queue base name. The instance number will be
3998	* appended automatically.
3999	* @param phQueue Where to store the queue handle on success.
4000	* @thread EMT(0)
4001	* @remarks The device critical section will NOT be entered before calling the
4002	* callback. No locks will be held, but for now it's safe to assume
4003	* that only one EMT will do queue callbacks at any one time.
4004	*/
4005	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
4006	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
4007	PDMQUEUEHANDLE *phQueue));
4008
4009	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
4010	DECLR3CALLBACKMEMBER(int, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
4011	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
4012	/** @} */
4013
4014	/** @name PDM Task
4015	* @{ */
4016	/**
4017	* Create an asynchronous ring-3 task.
4018	*
4019	* @returns VBox status code.
4020	* @param pDevIns The device instance.
4021	* @param fFlags PDMTASK_F_XXX
4022	* @param pszName The function name or similar. Used for statistics,
4023	* so no slashes.
4024	* @param pfnCallback The task function.
4025	* @param pvUser User argument for the task function.
4026	* @param phTask Where to return the task handle.
4027	* @thread EMT(0)
4028	*/
4029	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
4030	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
4031	/**
4032	* Triggers the running the given task.
4033	*
4034	* @returns VBox status code.
4035	* @retval VINF_ALREADY_POSTED is the task is already pending.
4036	* @param pDevIns The device instance.
4037	* @param hTask The task to trigger.
4038	* @thread Any thread.
4039	*/
4040	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
4041	/** @} */
4042
4043	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
4044	* These semaphores can be signalled from ring-0.
4045	* @{ */
4046	/** @sa SUPSemEventCreate */
4047	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
4048	/** @sa SUPSemEventClose */
4049	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
4050	/** @sa SUPSemEventSignal */
4051	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
4052	/** @sa SUPSemEventWaitNoResume */
4053	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
4054	/** @sa SUPSemEventWaitNsAbsIntr */
4055	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
4056	/** @sa SUPSemEventWaitNsRelIntr */
4057	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
4058	/** @sa SUPSemEventGetResolution */
4059	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
4060	/** @} */
4061
4062	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
4063	* These semaphores can be signalled from ring-0.
4064	* @{ */
4065	/** @sa SUPSemEventMultiCreate */
4066	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
4067	/** @sa SUPSemEventMultiClose */
4068	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4069	/** @sa SUPSemEventMultiSignal */
4070	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4071	/** @sa SUPSemEventMultiReset */
4072	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4073	/** @sa SUPSemEventMultiWaitNoResume */
4074	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
4075	/** @sa SUPSemEventMultiWaitNsAbsIntr */
4076	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
4077	/** @sa SUPSemEventMultiWaitNsRelIntr */
4078	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
4079	/** @sa SUPSemEventMultiGetResolution */
4080	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
4081	/** @} */
4082
4083	/**
4084	* Initializes a PDM critical section.
4085	*
4086	* The PDM critical sections are derived from the IPRT critical sections, but
4087	* works in RC and R0 as well.
4088	*
4089	* @returns VBox status code.
4090	* @param pDevIns The device instance.
4091	* @param pCritSect Pointer to the critical section.
4092	* @param SRC_POS Use RT_SRC_POS.
4093	* @param pszNameFmt Format string for naming the critical section.
4094	* For statistics and lock validation.
4095	* @param va Arguments for the format string.
4096	*/
4097	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
4098	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4099
4100	/**
4101	* Gets the NOP critical section.
4102	*
4103	* @returns The ring-3 address of the NOP critical section.
4104	* @param pDevIns The device instance.
4105	*/
4106	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4107
4108	/**
4109	* Changes the device level critical section from the automatically created
4110	* default to one desired by the device constructor.
4111	*
4112	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
4113	* the additional contexts.
4114	*
4115	* @returns VBox status code.
4116	* @param pDevIns The device instance.
4117	* @param pCritSect The critical section to use. NULL is not
4118	* valid, instead use the NOP critical
4119	* section.
4120	*/
4121	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4122
4123	/** @name Exported PDM Critical Section Functions
4124	* @{ */
4125	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4126	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4127	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4128	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4129	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4130	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4131	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4132	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4133	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4134	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4135	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
4136	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4137	/** @} */
4138
4139	/** @name Exported PDM Read/Write Critical Section Functions
4140	* @{ */
4141	DECLR3CALLBACKMEMBER(int, pfnCritSectRwInit,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
4142	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4143	DECLR3CALLBACKMEMBER(int, pfnCritSectRwDelete,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4144
4145	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4146	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4147	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4148	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4149	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4150
4151	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4152	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4153	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4154	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4155	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4156
4157	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4158	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
4159	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4160	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4161	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4162	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4163	/** @} */
4164
4165	/**
4166	* Creates a PDM thread.
4167	*
4168	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
4169	* resuming, and destroying the thread as the VM state changes.
4170	*
4171	* @returns VBox status code.
4172	* @param pDevIns The device instance.
4173	* @param ppThread Where to store the thread 'handle'.
4174	* @param pvUser The user argument to the thread function.
4175	* @param pfnThread The thread function.
4176	* @param pfnWakeup The wakup callback. This is called on the EMT
4177	* thread when a state change is pending.
4178	* @param cbStack See RTThreadCreate.
4179	* @param enmType See RTThreadCreate.
4180	* @param pszName See RTThreadCreate.
4181	* @remarks The device critical section will NOT be entered prior to invoking
4182	* the function pointers.
4183	*/
4184	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
4185	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
4186
4187	/** @name Exported PDM Thread Functions
4188	* @{ */
4189	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
4190	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
4191	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
4192	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
4193	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
4194	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
4195	/** @} */
4196
4197	/**
4198	* Set up asynchronous handling of a suspend, reset or power off notification.
4199	*
4200	* This shall only be called when getting the notification. It must be called
4201	* for each one.
4202	*
4203	* @returns VBox status code.
4204	* @param pDevIns The device instance.
4205	* @param pfnAsyncNotify The callback.
4206	* @thread EMT(0)
4207	* @remarks The caller will enter the device critical section prior to invoking
4208	* the callback.
4209	*/
4210	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
4211
4212	/**
4213	* Notify EMT(0) that the device has completed the asynchronous notification
4214	* handling.
4215	*
4216	* This can be called at any time, spurious calls will simply be ignored.
4217	*
4218	* @param pDevIns The device instance.
4219	* @thread Any
4220	*/
4221	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
4222
4223	/**
4224	* Register the RTC device.
4225	*
4226	* @returns VBox status code.
4227	* @param pDevIns The device instance.
4228	* @param pRtcReg Pointer to a RTC registration structure.
4229	* @param ppRtcHlp Where to store the pointer to the helper
4230	* functions.
4231	*/
4232	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
4233
4234	/**
4235	* Register a PCI Bus.
4236	*
4237	* @returns VBox status code, but the positive values 0..31 are used to indicate
4238	* bus number rather than informational status codes.
4239	* @param pDevIns The device instance.
4240	* @param pPciBusReg Pointer to PCI bus registration structure.
4241	* @param ppPciHlp Where to store the pointer to the PCI Bus
4242	* helpers.
4243	* @param piBus Where to return the PDM bus number. Optional.
4244	*/
4245	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
4246	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
4247
4248	/**
4249	* Register the IOMMU device.
4250	*
4251	* @returns VBox status code.
4252	* @param pDevIns The device instance.
4253	* @param pIommuReg Pointer to a IOMMU registration structure.
4254	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
4255	* helpers.
4256	* @param pidxIommu Where to return the IOMMU index. Optional.
4257	*/
4258	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
4259	uint32_t *pidxIommu));
4260
4261	/**
4262	* Register the PIC device.
4263	*
4264	* @returns VBox status code.
4265	* @param pDevIns The device instance.
4266	* @param pPicReg Pointer to a PIC registration structure.
4267	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
4268	* helpers.
4269	* @sa PDMDevHlpPICSetUpContext
4270	*/
4271	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4272
4273	/**
4274	* Register the APIC device.
4275	*
4276	* @returns VBox status code.
4277	* @param pDevIns The device instance.
4278	*/
4279	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
4280
4281	/**
4282	* Register the I/O APIC device.
4283	*
4284	* @returns VBox status code.
4285	* @param pDevIns The device instance.
4286	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4287	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
4288	* helpers.
4289	*/
4290	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4291
4292	/**
4293	* Register the HPET device.
4294	*
4295	* @returns VBox status code.
4296	* @param pDevIns The device instance.
4297	* @param pHpetReg Pointer to a HPET registration structure.
4298	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4299	* helpers.
4300	*/
4301	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4302
4303	/**
4304	* Register a raw PCI device.
4305	*
4306	* @returns VBox status code.
4307	* @param pDevIns The device instance.
4308	* @param pPciRawReg Pointer to a raw PCI registration structure.
4309	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4310	* device helpers.
4311	*/
4312	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4313
4314	/**
4315	* Register the DMA device.
4316	*
4317	* @returns VBox status code.
4318	* @param pDevIns The device instance.
4319	* @param pDmacReg Pointer to a DMAC registration structure.
4320	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4321	*/
4322	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4323
4324	/**
4325	* Register transfer function for DMA channel.
4326	*
4327	* @returns VBox status code.
4328	* @param pDevIns The device instance.
4329	* @param uChannel Channel number.
4330	* @param pfnTransferHandler Device specific transfer callback function.
4331	* @param pvUser User pointer to pass to the callback.
4332	* @thread EMT
4333	*/
4334	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4335
4336	/**
4337	* Read memory.
4338	*
4339	* @returns VBox status code.
4340	* @param pDevIns The device instance.
4341	* @param uChannel Channel number.
4342	* @param pvBuffer Pointer to target buffer.
4343	* @param off DMA position.
4344	* @param cbBlock Block size.
4345	* @param pcbRead Where to store the number of bytes which was
4346	* read. optional.
4347	* @thread EMT
4348	*/
4349	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4350
4351	/**
4352	* Write memory.
4353	*
4354	* @returns VBox status code.
4355	* @param pDevIns The device instance.
4356	* @param uChannel Channel number.
4357	* @param pvBuffer Memory to write.
4358	* @param off DMA position.
4359	* @param cbBlock Block size.
4360	* @param pcbWritten Where to store the number of bytes which was
4361	* written. optional.
4362	* @thread EMT
4363	*/
4364	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4365
4366	/**
4367	* Set the DREQ line.
4368	*
4369	* @returns VBox status code.
4370	* @param pDevIns Device instance.
4371	* @param uChannel Channel number.
4372	* @param uLevel Level of the line.
4373	* @thread EMT
4374	*/
4375	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4376
4377	/**
4378	* Get channel mode.
4379	*
4380	* @returns Channel mode. See specs.
4381	* @param pDevIns The device instance.
4382	* @param uChannel Channel number.
4383	* @thread EMT
4384	*/
4385	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4386
4387	/**
4388	* Schedule DMA execution.
4389	*
4390	* @param pDevIns The device instance.
4391	* @thread Any thread.
4392	*/
4393	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4394
4395	/**
4396	* Write CMOS value and update the checksum(s).
4397	*
4398	* @returns VBox status code.
4399	* @param pDevIns The device instance.
4400	* @param iReg The CMOS register index.
4401	* @param u8Value The CMOS register value.
4402	* @thread EMT
4403	*/
4404	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4405
4406	/**
4407	* Read CMOS value.
4408	*
4409	* @returns VBox status code.
4410	* @param pDevIns The device instance.
4411	* @param iReg The CMOS register index.
4412	* @param pu8Value Where to store the CMOS register value.
4413	* @thread EMT
4414	*/
4415	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4416
4417	/**
4418	* Assert that the current thread is the emulation thread.
4419	*
4420	* @returns True if correct.
4421	* @returns False if wrong.
4422	* @param pDevIns The device instance.
4423	* @param pszFile Filename of the assertion location.
4424	* @param iLine The linenumber of the assertion location.
4425	* @param pszFunction Function of the assertion location.
4426	*/
4427	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4428
4429	/**
4430	* Assert that the current thread is NOT the emulation thread.
4431	*
4432	* @returns True if correct.
4433	* @returns False if wrong.
4434	* @param pDevIns The device instance.
4435	* @param pszFile Filename of the assertion location.
4436	* @param iLine The linenumber of the assertion location.
4437	* @param pszFunction Function of the assertion location.
4438	*/
4439	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4440
4441	/**
4442	* Resolves the symbol for a raw-mode context interface.
4443	*
4444	* @returns VBox status code.
4445	* @param pDevIns The device instance.
4446	* @param pvInterface The interface structure.
4447	* @param cbInterface The size of the interface structure.
4448	* @param pszSymPrefix What to prefix the symbols in the list with
4449	* before resolving them. This must start with
4450	* 'dev' and contain the driver name.
4451	* @param pszSymList List of symbols corresponding to the interface.
4452	* There is generally a there is generally a define
4453	* holding this list associated with the interface
4454	* definition (INTERFACE_SYM_LIST). For more
4455	* details see PDMR3LdrGetInterfaceSymbols.
4456	* @thread EMT
4457	*/
4458	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4459	const char pszSymPrefix, const char pszSymList));
4460
4461	/**
4462	* Resolves the symbol for a ring-0 context interface.
4463	*
4464	* @returns VBox status code.
4465	* @param pDevIns The device instance.
4466	* @param pvInterface The interface structure.
4467	* @param cbInterface The size of the interface structure.
4468	* @param pszSymPrefix What to prefix the symbols in the list with
4469	* before resolving them. This must start with
4470	* 'dev' and contain the driver name.
4471	* @param pszSymList List of symbols corresponding to the interface.
4472	* There is generally a there is generally a define
4473	* holding this list associated with the interface
4474	* definition (INTERFACE_SYM_LIST). For more
4475	* details see PDMR3LdrGetInterfaceSymbols.
4476	* @thread EMT
4477	*/
4478	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4479	const char pszSymPrefix, const char pszSymList));
4480
4481	/**
4482	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4483	*
4484	* @returns VBox status code.
4485	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4486	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4487	*
4488	* @param pDevIns The device instance.
4489	* @param uOperation The operation to perform.
4490	* @param u64Arg 64-bit integer argument.
4491	* @thread EMT
4492	*/
4493	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4494
4495	/**
4496	* Gets the reason for the most recent VM suspend.
4497	*
4498	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4499	* suspend has been made or if the pDevIns is invalid.
4500	* @param pDevIns The device instance.
4501	*/
4502	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4503
4504	/**
4505	* Gets the reason for the most recent VM resume.
4506	*
4507	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4508	* resume has been made or if the pDevIns is invalid.
4509	* @param pDevIns The device instance.
4510	*/
4511	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4512
4513	/**
4514	* Requests the mapping of multiple guest page into ring-3.
4515	*
4516	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4517	* ASAP to release them.
4518	*
4519	* This API will assume your intention is to write to the pages, and will
4520	* therefore replace shared and zero pages. If you do not intend to modify the
4521	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4522	*
4523	* @returns VBox status code.
4524	* @retval VINF_SUCCESS on success.
4525	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4526	* backing or if any of the pages the page has any active access
4527	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4528	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4529	* an invalid physical address.
4530	*
4531	* @param pDevIns The device instance.
4532	* @param cPages Number of pages to lock.
4533	* @param paGCPhysPages The guest physical address of the pages that
4534	* should be mapped (@a cPages entries).
4535	* @param fFlags Flags reserved for future use, MBZ.
4536	* @param papvPages Where to store the ring-3 mapping addresses
4537	* corresponding to @a paGCPhysPages.
4538	* @param paLocks Where to store the locking information that
4539	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4540	* in length).
4541	*
4542	* @remark Avoid calling this API from within critical sections (other than the
4543	* PGM one) because of the deadlock risk when we have to delegating the
4544	* task to an EMT.
4545	* @thread Any.
4546	* @since 6.0.6
4547	*/
4548	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4549	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4550
4551	/**
4552	* Requests the mapping of multiple guest page into ring-3, for reading only.
4553	*
4554	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4555	* ASAP to release them.
4556	*
4557	* @returns VBox status code.
4558	* @retval VINF_SUCCESS on success.
4559	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4560	* backing or if any of the pages the page has an active ALL access
4561	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4562	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4563	* an invalid physical address.
4564	*
4565	* @param pDevIns The device instance.
4566	* @param cPages Number of pages to lock.
4567	* @param paGCPhysPages The guest physical address of the pages that
4568	* should be mapped (@a cPages entries).
4569	* @param fFlags Flags reserved for future use, MBZ.
4570	* @param papvPages Where to store the ring-3 mapping addresses
4571	* corresponding to @a paGCPhysPages.
4572	* @param paLocks Where to store the lock information that
4573	* pfnPhysReleasePageMappingLock needs (@a cPages
4574	* in length).
4575	*
4576	* @remark Avoid calling this API from within critical sections.
4577	* @thread Any.
4578	* @since 6.0.6
4579	*/
4580	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4581	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4582
4583	/**
4584	* Release the mappings of multiple guest pages.
4585	*
4586	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4587	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4588	*
4589	* @param pDevIns The device instance.
4590	* @param cPages Number of pages to unlock.
4591	* @param paLocks The lock structures initialized by the mapping
4592	* function (@a cPages in length).
4593	* @thread Any.
4594	* @since 6.0.6
4595	*/
4596	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4597
4598	/**
4599	* Returns the micro architecture used for the guest.
4600	*
4601	* @returns CPU micro architecture enum.
4602	* @param pDevIns The device instance.
4603	*/
4604	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4605
4606	/**
4607	* Get the number of physical and linear address bits supported by the guest.
4608	*
4609	* @param pDevIns The device instance.
4610	* @param pcPhysAddrWidth Where to store the number of physical address bits
4611	* supported by the guest.
4612	* @param pcLinearAddrWidth Where to store the number of linear address bits
4613	* supported by the guest.
4614	*/
4615	DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4616	uint8_t *pcLinearAddrWidth));
4617
4618	/**
4619	* Gets the scalable bus frequency.
4620	*
4621	* The bus frequency is used as a base in several MSRs that gives the CPU and
4622	* other frequency ratios.
4623	*
4624	* @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
4625	* @param pDevIns The device instance.
4626	*/
4627	DECLR3CALLBACKMEMBER(uint64_t, pfnCpuGetGuestScalableBusFrequency,(PPDMDEVINS pDevIns));
4628
4629	/** Space reserved for future members.
4630	* @{ */
4631	/**
4632	* Deregister zero or more samples given their name prefix.
4633	*
4634	* @returns VBox status code.
4635	* @param pDevIns The device instance.
4636	* @param pszPrefix The name prefix of the samples to remove. If this does
4637	* not start with a '/', the default prefix will be
4638	* prepended, otherwise it will be used as-is.
4639	*/
4640	DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4641	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4642	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4643	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4644	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4645	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4646	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4647	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4648	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4649	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4650	/** @} */
4651
4652
4653	/** API available to trusted devices only.
4654	*
4655	* These APIs are providing unrestricted access to the guest and the VM,
4656	* or they are interacting intimately with PDM.
4657	*
4658	* @{
4659	*/
4660
4661	/**
4662	* Gets the user mode VM handle. Restricted API.
4663	*
4664	* @returns User mode VM Handle.
4665	* @param pDevIns The device instance.
4666	*/
4667	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4668
4669	/**
4670	* Gets the global VM handle. Restricted API.
4671	*
4672	* @returns VM Handle.
4673	* @param pDevIns The device instance.
4674	*/
4675	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4676
4677	/**
4678	* Gets the VMCPU handle. Restricted API.
4679	*
4680	* @returns VMCPU Handle.
4681	* @param pDevIns The device instance.
4682	*/
4683	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4684
4685	/**
4686	* The the VM CPU ID of the current thread (restricted API).
4687	*
4688	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4689	* @param pDevIns The device instance.
4690	*/
4691	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4692
4693	/**
4694	* Registers the VMM device heap or notifies about mapping/unmapping.
4695	*
4696	* This interface serves three purposes:
4697	*
4698	* -# Register the VMM device heap during device construction
4699	* for the HM to use.
4700	* -# Notify PDM/HM that it's mapped into guest address
4701	* space (i.e. usable).
4702	* -# Notify PDM/HM that it is being unmapped from the guest
4703	* address space (i.e. not usable).
4704	*
4705	* @returns VBox status code.
4706	* @param pDevIns The device instance.
4707	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4708	* not mapped.
4709	* @param pvHeap Ring 3 heap pointer.
4710	* @param cbHeap Size of the heap.
4711	* @thread EMT.
4712	*/
4713	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4714
4715	/**
4716	* Registers the firmware (BIOS, EFI) device with PDM.
4717	*
4718	* The firmware provides a callback table and gets a special PDM helper table.
4719	* There can only be one firmware device for a VM.
4720	*
4721	* @returns VBox status code.
4722	* @param pDevIns The device instance.
4723	* @param pFwReg Firmware registration structure.
4724	* @param ppFwHlp Where to return the firmware helper structure.
4725	* @remarks Only valid during device construction.
4726	* @thread EMT(0)
4727	*/
4728	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4729
4730	/**
4731	* Resets the VM.
4732	*
4733	* @returns The appropriate VBox status code to pass around on reset.
4734	* @param pDevIns The device instance.
4735	* @param fFlags PDMVMRESET_F_XXX flags.
4736	* @thread The emulation thread.
4737	*/
4738	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4739
4740	/**
4741	* Suspends the VM.
4742	*
4743	* @returns The appropriate VBox status code to pass around on suspend.
4744	* @param pDevIns The device instance.
4745	* @thread The emulation thread.
4746	*/
4747	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4748
4749	/**
4750	* Suspends, saves and powers off the VM.
4751	*
4752	* @returns The appropriate VBox status code to pass around.
4753	* @param pDevIns The device instance.
4754	* @thread An emulation thread.
4755	*/
4756	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4757
4758	/**
4759	* Power off the VM.
4760	*
4761	* @returns The appropriate VBox status code to pass around on power off.
4762	* @param pDevIns The device instance.
4763	* @thread The emulation thread.
4764	*/
4765	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4766
4767	/**
4768	* Checks if the Gate A20 is enabled or not.
4769	*
4770	* @returns true if A20 is enabled.
4771	* @returns false if A20 is disabled.
4772	* @param pDevIns The device instance.
4773	* @thread The emulation thread.
4774	*/
4775	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4776
4777	/**
4778	* Enables or disables the Gate A20.
4779	*
4780	* @param pDevIns The device instance.
4781	* @param fEnable Set this flag to enable the Gate A20; clear it
4782	* to disable.
4783	* @thread The emulation thread.
4784	*/
4785	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4786
4787	/**
4788	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4789	* thread.
4790	*
4791	* @param pDevIns The device instance.
4792	* @param iLeaf The CPUID leaf to get.
4793	* @param pEax Where to store the EAX value.
4794	* @param pEbx Where to store the EBX value.
4795	* @param pEcx Where to store the ECX value.
4796	* @param pEdx Where to store the EDX value.
4797	* @thread EMT.
4798	*/
4799	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4800
4801	/**
4802	* Gets the main execution engine for the VM.
4803	*
4804	* @returns VM_EXEC_ENGINE_XXX
4805	* @param pDevIns The device instance.
4806	*/
4807	DECLR3CALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
4808
4809	/**
4810	* Get the current virtual clock time in a VM. The clock frequency must be
4811	* queried separately.
4812	*
4813	* @returns Current clock time.
4814	* @param pDevIns The device instance.
4815	*/
4816	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4817
4818	/**
4819	* Get the frequency of the virtual clock.
4820	*
4821	* @returns The clock frequency (not variable at run-time).
4822	* @param pDevIns The device instance.
4823	*/
4824	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4825
4826	/**
4827	* Get the current virtual clock time in a VM, in nanoseconds.
4828	*
4829	* @returns Current clock time (in ns).
4830	* @param pDevIns The device instance.
4831	*/
4832	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4833
4834	/**
4835	* Get the timestamp frequency.
4836	*
4837	* @returns Number of ticks per second.
4838	* @param pDevIns The device instance.
4839	*/
4840	DECLR3CALLBACKMEMBER(uint64_t, pfnTMCpuTicksPerSecond,(PPDMDEVINS pDevIns));
4841
4842	/**
4843	* Gets the support driver session.
4844	*
4845	* This is intended for working with the semaphore API.
4846	*
4847	* @returns Support driver session handle.
4848	* @param pDevIns The device instance.
4849	*/
4850	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4851
4852	/**
4853	* Queries a generic object from the VMM user.
4854	*
4855	* @returns Pointer to the object if found, NULL if not.
4856	* @param pDevIns The device instance.
4857	* @param pUuid The UUID of what's being queried. The UUIDs and
4858	* the usage conventions are defined by the user.
4859	*
4860	* @note It is strictly forbidden to call this internally in VBox! This
4861	* interface is exclusively for hacks in externally developed devices.
4862	*/
4863	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4864
4865	/**
4866	* Register a physical page access handler type.
4867	*
4868	* @returns VBox status code.
4869	* @param pDevIns The device instance.
4870	* @param enmKind The kind of access handler.
4871	* @param pfnHandler Pointer to the ring-3 handler callback.
4872	* @param pszDesc The type description.
4873	* @param phType Where to return the type handle (cross context safe).
4874	* @sa PDMDevHlpPGMHandlerPhysicalTypeSetUpContext
4875	*/
4876	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4877	PFNPGMPHYSHANDLER pfnHandler,
4878	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4879
4880	/**
4881	* Register a access handler for a physical range.
4882	*
4883	* @returns VBox status code.
4884	* @retval VINF_SUCCESS when successfully installed.
4885	* @retval VINF_PGM_GCPHYS_ALIASED when the shadow PTs could be updated because
4886	* the guest page aliased or/and mapped by multiple PTs. A CR3 sync has been
4887	* flagged together with a pool clearing.
4888	* @retval VERR_PGM_HANDLER_PHYSICAL_CONFLICT if the range conflicts with an existing
4889	* one. A debug assertion is raised.
4890	*
4891	* @param pDevIns The device instance.
4892	* @param GCPhys Start physical address.
4893	* @param GCPhysLast Last physical address. (inclusive)
4894	* @param hType The handler type registration handle.
4895	* @param pszDesc Description of this handler. If NULL, the type
4896	* description will be used instead.
4897	* @note There is no @a uUser argument, because it will be set to the pDevIns
4898	* in the context the handler is called.
4899	*/
4900	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalRegister, (PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
4901	PGMPHYSHANDLERTYPE hType, R3PTRTYPE(const char *) pszDesc));
4902
4903	/**
4904	* Deregister a physical page access handler.
4905	*
4906	* @returns VBox status code.
4907	* @param pDevIns The device instance.
4908	* @param GCPhys Start physical address.
4909	*/
4910	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalDeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4911
4912	/**
4913	* Temporarily turns off the access monitoring of a page within a monitored
4914	* physical write/all page access handler region.
4915	*
4916	* Use this when no further \#PFs are required for that page. Be aware that
4917	* a page directory sync might reset the flags, and turn on access monitoring
4918	* for the page.
4919	*
4920	* The caller must do required page table modifications.
4921	*
4922	* @returns VBox status code.
4923	* @param pDevIns The device instance.
4924	* @param GCPhys The start address of the access handler. This
4925	* must be a fully page aligned range or we risk
4926	* messing up other handlers installed for the
4927	* start and end pages.
4928	* @param GCPhysPage The physical address of the page to turn off
4929	* access monitoring for.
4930	*/
4931	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
4932
4933	/**
4934	* Resets any modifications to individual pages in a physical page access
4935	* handler region.
4936	*
4937	* This is used in pair with PGMHandlerPhysicalPageTempOff(),
4938	* PGMHandlerPhysicalPageAliasMmio2() or PGMHandlerPhysicalPageAliasHC().
4939	*
4940	* @returns VBox status code.
4941	* @param pDevIns The device instance.
4942	* @param GCPhys The start address of the handler regions, i.e. what you
4943	* passed to PGMR3HandlerPhysicalRegister(),
4944	* PGMHandlerPhysicalRegisterEx() or
4945	* PGMHandlerPhysicalModify().
4946	*/
4947	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalReset,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4948
4949	/**
4950	* Registers the guest memory range that can be used for patching.
4951	*
4952	* @returns VBox status code.
4953	* @param pDevIns The device instance.
4954	* @param GCPtrPatchMem Patch memory range.
4955	* @param cbPatchMem Size of the memory range.
4956	*/
4957	DECLR3CALLBACKMEMBER(int, pfnVMMRegisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4958
4959	/**
4960	* Deregisters the guest memory range that can be used for patching.
4961	*
4962	* @returns VBox status code.
4963	* @param pDevIns The device instance.
4964	* @param GCPtrPatchMem Patch memory range.
4965	* @param cbPatchMem Size of the memory range.
4966	*/
4967	DECLR3CALLBACKMEMBER(int, pfnVMMDeregisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4968
4969	/**
4970	* Registers a new shared module for the VM
4971	*
4972	* @returns VBox status code.
4973	* @param pDevIns The device instance.
4974	* @param enmGuestOS Guest OS type.
4975	* @param pszModuleName Module name.
4976	* @param pszVersion Module version.
4977	* @param GCBaseAddr Module base address.
4978	* @param cbModule Module size.
4979	* @param cRegions Number of shared region descriptors.
4980	* @param paRegions Shared region(s).
4981	*/
4982	DECLR3CALLBACKMEMBER(int, pfnSharedModuleRegister,(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
4983	RTGCPTR GCBaseAddr, uint32_t cbModule,
4984	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions));
4985
4986	/**
4987	* Unregisters a shared module for the VM
4988	*
4989	* @returns VBox status code.
4990	* @param pDevIns The device instance.
4991	* @param pszModuleName Module name.
4992	* @param pszVersion Module version.
4993	* @param GCBaseAddr Module base address.
4994	* @param cbModule Module size.
4995	*/
4996	DECLR3CALLBACKMEMBER(int, pfnSharedModuleUnregister,(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
4997	RTGCPTR GCBaseAddr, uint32_t cbModule));
4998
4999	/**
5000	* Query the state of a page in a shared module
5001	*
5002	* @returns VBox status code.
5003	* @param pDevIns The device instance.
5004	* @param GCPtrPage Page address.
5005	* @param pfShared Shared status (out).
5006	* @param pfPageFlags Page flags (out).
5007	*/
5008	DECLR3CALLBACKMEMBER(int, pfnSharedModuleGetPageState, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags));
5009
5010	/**
5011	* Check all registered modules for changes.
5012	*
5013	* @returns VBox status code.
5014	* @param pDevIns The device instance.
5015	*/
5016	DECLR3CALLBACKMEMBER(int, pfnSharedModuleCheckAll,(PPDMDEVINS pDevIns));
5017
5018	/**
5019	* Query the interface of the top level driver on a LUN.
5020	*
5021	* @returns VBox status code.
5022	* @param pDevIns The device instance.
5023	* @param pszDevice Device name.
5024	* @param iInstance Device instance.
5025	* @param iLun The Logical Unit to obtain the interface of.
5026	* @param ppBase Where to store the base interface pointer.
5027	*
5028	* @remark We're not doing any locking ATM, so don't try call this at times when the
5029	* device chain is known to be updated.
5030	*/
5031	DECLR3CALLBACKMEMBER(int, pfnQueryLun,(PPDMDEVINS pDevIns, const char *pszDevice, unsigned iInstance, unsigned iLun, PPPDMIBASE ppBase));
5032
5033	/**
5034	* Registers the GIM device with VMM.
5035	*
5036	* @param pDevIns Pointer to the GIM device instance.
5037	* @param pDbg Pointer to the GIM device debug structure, can be
5038	* NULL.
5039	*/
5040	DECLR3CALLBACKMEMBER(void, pfnGIMDeviceRegister,(PPDMDEVINS pDevIns, PGIMDEBUG pDbg));
5041
5042	/**
5043	* Gets debug setup specified by the provider.
5044	*
5045	* @returns VBox status code.
5046	* @param pDevIns Pointer to the GIM device instance.
5047	* @param pDbgSetup Where to store the debug setup details.
5048	*/
5049	DECLR3CALLBACKMEMBER(int, pfnGIMGetDebugSetup,(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup));
5050
5051	/**
5052	* Returns the array of MMIO2 regions that are expected to be registered and
5053	* later mapped into the guest-physical address space for the GIM provider
5054	* configured for the VM.
5055	*
5056	* @returns Pointer to an array of GIM MMIO2 regions, may return NULL.
5057	* @param pDevIns Pointer to the GIM device instance.
5058	* @param pcRegions Where to store the number of items in the array.
5059	*
5060	* @remarks The caller does not own and therefore must -NOT- try to free the
5061	* returned pointer.
5062	*/
5063	DECLR3CALLBACKMEMBER(PGIMMMIO2REGION, pfnGIMGetMmio2Regions,(PPDMDEVINS pDevIns, uint32_t *pcRegions));
5064
5065	/** @} */
5066
5067	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
5068	uint32_t u32TheEnd;
5069	} PDMDEVHLPR3;
5070	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
5071	/** Pointer to the R3 PDM Device API. */
5072	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
5073	/** Pointer to the R3 PDM Device API, const variant. */
5074	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
5075
5076
5077	/**
5078	* PDM Device API - RC Variant.
5079	*/
5080	typedef struct PDMDEVHLPRC
5081	{
5082	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
5083	uint32_t u32Version;
5084
5085	/**
5086	* Sets up raw-mode context callback handlers for an I/O port range.
5087	*
5088	* The range must have been registered in ring-3 first using
5089	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5090	*
5091	* @returns VBox status.
5092	* @param pDevIns The device instance to register the ports with.
5093	* @param hIoPorts The I/O port range handle.
5094	* @param pfnOut Pointer to function which is gonna handle OUT
5095	* operations. Optional.
5096	* @param pfnIn Pointer to function which is gonna handle IN operations.
5097	* Optional.
5098	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5099	* operations. Optional.
5100	* @param pfnInStr Pointer to function which is gonna handle string IN
5101	* operations. Optional.
5102	* @param pvUser User argument to pass to the callbacks.
5103	*
5104	* @remarks Caller enters the device critical section prior to invoking the
5105	* registered callback methods.
5106	*
5107	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
5108	* PDMDevHlpIoPortUnmap.
5109	*/
5110	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5111	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5112	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5113	void *pvUser));
5114
5115	/**
5116	* Sets up raw-mode context callback handlers for an MMIO region.
5117	*
5118	* The region must have been registered in ring-3 first using
5119	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
5120	*
5121	* @returns VBox status.
5122	* @param pDevIns The device instance to register the ports with.
5123	* @param hRegion The MMIO region handle.
5124	* @param pfnWrite Pointer to function which is gonna handle Write
5125	* operations.
5126	* @param pfnRead Pointer to function which is gonna handle Read
5127	* operations.
5128	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5129	* operations. (optional)
5130	* @param pvUser User argument to pass to the callbacks.
5131	*
5132	* @remarks Caller enters the device critical section prior to invoking the
5133	* registered callback methods.
5134	*
5135	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
5136	* PDMDevHlpMmioUnmap.
5137	*/
5138	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5139	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5140
5141	/**
5142	* Sets up a raw-mode mapping for an MMIO2 region.
5143	*
5144	* The region must have been created in ring-3 first using
5145	* PDMDevHlpMmio2Create().
5146	*
5147	* @returns VBox status.
5148	* @param pDevIns The device instance to register the ports with.
5149	* @param hRegion The MMIO2 region handle.
5150	* @param offSub Start of what to map into raw-mode. Must be page aligned.
5151	* @param cbSub Number of bytes to map into raw-mode. Must be page
5152	* aligned. Zero is an alias for everything.
5153	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5154	* @thread EMT(0)
5155	* @note Only available at VM creation time.
5156	*
5157	* @sa PDMDevHlpMmio2Create().
5158	*/
5159	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
5160	size_t offSub, size_t cbSub, void **ppvMapping));
5161
5162	/**
5163	* Bus master physical memory read from the given PCI device.
5164	*
5165	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
5166	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
5167	* @param pDevIns The device instance.
5168	* @param pPciDev The PCI device structure. If NULL the default
5169	* PCI device for this device instance is used.
5170	* @param GCPhys Physical address start reading from.
5171	* @param pvBuf Where to put the read bits.
5172	* @param cbRead How many bytes to read.
5173	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5174	* @thread Any thread, but the call may involve the emulation thread.
5175	*/
5176	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5177	void *pvBuf, size_t cbRead, uint32_t fFlags));
5178
5179	/**
5180	* Bus master physical memory write from the given PCI device.
5181	*
5182	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
5183	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
5184	* @param pDevIns The device instance.
5185	* @param pPciDev The PCI device structure. If NULL the default
5186	* PCI device for this device instance is used.
5187	* @param GCPhys Physical address to write to.
5188	* @param pvBuf What to write.
5189	* @param cbWrite How many bytes to write.
5190	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5191	* @thread Any thread, but the call may involve the emulation thread.
5192	*/
5193	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5194	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5195
5196	/**
5197	* Set the IRQ for the given PCI device.
5198	*
5199	* @param pDevIns Device instance.
5200	* @param pPciDev The PCI device structure. If NULL the default
5201	* PCI device for this device instance is used.
5202	* @param iIrq IRQ number to set.
5203	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5204	* @thread Any thread, but will involve the emulation thread.
5205	*/
5206	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5207
5208	/**
5209	* Set ISA IRQ for a device.
5210	*
5211	* @param pDevIns Device instance.
5212	* @param iIrq IRQ number to set.
5213	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5214	* @thread Any thread, but will involve the emulation thread.
5215	*/
5216	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5217
5218	/**
5219	* Read physical memory.
5220	*
5221	* @returns VINF_SUCCESS (for now).
5222	* @param pDevIns Device instance.
5223	* @param GCPhys Physical address start reading from.
5224	* @param pvBuf Where to put the read bits.
5225	* @param cbRead How many bytes to read.
5226	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5227	*/
5228	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5229
5230	/**
5231	* Write to physical memory.
5232	*
5233	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5234	* @param pDevIns Device instance.
5235	* @param GCPhys Physical address to write to.
5236	* @param pvBuf What to write.
5237	* @param cbWrite How many bytes to write.
5238	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5239	*/
5240	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5241
5242	/**
5243	* Checks if the Gate A20 is enabled or not.
5244	*
5245	* @returns true if A20 is enabled.
5246	* @returns false if A20 is disabled.
5247	* @param pDevIns Device instance.
5248	* @thread The emulation thread.
5249	*/
5250	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5251
5252	/**
5253	* Gets the VM state.
5254	*
5255	* @returns VM state.
5256	* @param pDevIns The device instance.
5257	* @thread Any thread (just keep in mind that it's volatile info).
5258	*/
5259	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5260
5261	/**
5262	* Gets the VM handle. Restricted API.
5263	*
5264	* @returns VM Handle.
5265	* @param pDevIns Device instance.
5266	*/
5267	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5268
5269	/**
5270	* Gets the VMCPU handle. Restricted API.
5271	*
5272	* @returns VMCPU Handle.
5273	* @param pDevIns The device instance.
5274	*/
5275	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5276
5277	/**
5278	* The the VM CPU ID of the current thread (restricted API).
5279	*
5280	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5281	* @param pDevIns The device instance.
5282	*/
5283	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5284
5285	/**
5286	* Gets the main execution engine for the VM.
5287	*
5288	* @returns VM_EXEC_ENGINE_XXX
5289	* @param pDevIns The device instance.
5290	*/
5291	DECLRCCALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
5292
5293	/**
5294	* Get the current virtual clock time in a VM. The clock frequency must be
5295	* queried separately.
5296	*
5297	* @returns Current clock time.
5298	* @param pDevIns The device instance.
5299	*/
5300	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5301
5302	/**
5303	* Get the frequency of the virtual clock.
5304	*
5305	* @returns The clock frequency (not variable at run-time).
5306	* @param pDevIns The device instance.
5307	*/
5308	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5309
5310	/**
5311	* Get the current virtual clock time in a VM, in nanoseconds.
5312	*
5313	* @returns Current clock time (in ns).
5314	* @param pDevIns The device instance.
5315	*/
5316	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5317
5318	/**
5319	* Gets the NOP critical section.
5320	*
5321	* @returns The ring-3 address of the NOP critical section.
5322	* @param pDevIns The device instance.
5323	*/
5324	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5325
5326	/**
5327	* Changes the device level critical section from the automatically created
5328	* default to one desired by the device constructor.
5329	*
5330	* Must first be done in ring-3.
5331	*
5332	* @returns VBox status code.
5333	* @param pDevIns The device instance.
5334	* @param pCritSect The critical section to use. NULL is not
5335	* valid, instead use the NOP critical
5336	* section.
5337	*/
5338	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5339
5340	/** @name Exported PDM Critical Section Functions
5341	* @{ */
5342	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5343	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5344	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5345	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5346	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5347	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5348	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5349	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5350	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5351	/** @} */
5352
5353	/** @name Exported PDM Read/Write Critical Section Functions
5354	* @{ */
5355	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5356	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5357	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5358	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5359	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5360
5361	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5362	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5363	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5364	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5365	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5366
5367	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5368	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5369	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5370	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5371	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5372	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5373	/** @} */
5374
5375	/**
5376	* Gets the trace buffer handle.
5377	*
5378	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5379	* really inteded for direct usage, thus no inline wrapper function.
5380	*
5381	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5382	* @param pDevIns The device instance.
5383	*/
5384	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5385
5386	/**
5387	* Sets up the PCI bus for the raw-mode context.
5388	*
5389	* This must be called after ring-3 has registered the PCI bus using
5390	* PDMDevHlpPCIBusRegister().
5391	*
5392	* @returns VBox status code.
5393	* @param pDevIns The device instance.
5394	* @param pPciBusReg The PCI bus registration information for raw-mode,
5395	* considered volatile.
5396	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
5397	*/
5398	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
5399
5400	/**
5401	* Sets up the IOMMU for the raw-mode context.
5402	*
5403	* This must be called after ring-3 has registered the IOMMU using
5404	* PDMDevHlpIommuRegister().
5405	*
5406	* @returns VBox status code.
5407	* @param pDevIns The device instance.
5408	* @param pIommuReg The IOMMU registration information for raw-mode,
5409	* considered volatile.
5410	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
5411	*/
5412	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
5413
5414	/**
5415	* Sets up the PIC for the ring-0 context.
5416	*
5417	* This must be called after ring-3 has registered the PIC using
5418	* PDMDevHlpPICRegister().
5419	*
5420	* @returns VBox status code.
5421	* @param pDevIns The device instance.
5422	* @param pPicReg The PIC registration information for ring-0,
5423	* considered volatile and copied.
5424	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5425	*/
5426	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5427
5428	/**
5429	* Sets up the APIC for the raw-mode context.
5430	*
5431	* This must be called after ring-3 has registered the APIC using
5432	* PDMDevHlpApicRegister().
5433	*
5434	* @returns VBox status code.
5435	* @param pDevIns The device instance.
5436	*/
5437	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5438
5439	/**
5440	* Sets up the IOAPIC for the ring-0 context.
5441	*
5442	* This must be called after ring-3 has registered the PIC using
5443	* PDMDevHlpIoApicRegister().
5444	*
5445	* @returns VBox status code.
5446	* @param pDevIns The device instance.
5447	* @param pIoApicReg The PIC registration information for ring-0,
5448	* considered volatile and copied.
5449	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5450	*/
5451	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5452
5453	/**
5454	* Sets up the HPET for the raw-mode context.
5455	*
5456	* This must be called after ring-3 has registered the PIC using
5457	* PDMDevHlpHpetRegister().
5458	*
5459	* @returns VBox status code.
5460	* @param pDevIns The device instance.
5461	* @param pHpetReg The PIC registration information for raw-mode,
5462	* considered volatile and copied.
5463	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
5464	*/
5465	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
5466
5467	/** Space reserved for future members.
5468	* @{ */
5469	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
5470	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
5471	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
5472	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
5473	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
5474	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
5475	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
5476	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
5477	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
5478	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
5479	/** @} */
5480
5481	/** Just a safety precaution. */
5482	uint32_t u32TheEnd;
5483	} PDMDEVHLPRC;
5484	/** Pointer PDM Device RC API. */
5485	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
5486	/** Pointer PDM Device RC API. */
5487	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
5488
5489	/** Current PDMDEVHLP version number. */
5490	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 19, 0)
5491
5492
5493	/**
5494	* PDM Device API - R0 Variant.
5495	*/
5496	typedef struct PDMDEVHLPR0
5497	{
5498	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5499	uint32_t u32Version;
5500
5501	/**
5502	* Sets up ring-0 callback handlers for an I/O port range.
5503	*
5504	* The range must have been created in ring-3 first using
5505	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5506	*
5507	* @returns VBox status.
5508	* @param pDevIns The device instance to register the ports with.
5509	* @param hIoPorts The I/O port range handle.
5510	* @param pfnOut Pointer to function which is gonna handle OUT
5511	* operations. Optional.
5512	* @param pfnIn Pointer to function which is gonna handle IN operations.
5513	* Optional.
5514	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5515	* operations. Optional.
5516	* @param pfnInStr Pointer to function which is gonna handle string IN
5517	* operations. Optional.
5518	* @param pvUser User argument to pass to the callbacks.
5519	*
5520	* @remarks Caller enters the device critical section prior to invoking the
5521	* registered callback methods.
5522	*
5523	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5524	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5525	*/
5526	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5527	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5528	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5529	void *pvUser));
5530
5531	/**
5532	* Sets up ring-0 callback handlers for an MMIO region.
5533	*
5534	* The region must have been created in ring-3 first using
5535	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5536	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5537	*
5538	* @returns VBox status.
5539	* @param pDevIns The device instance to register the ports with.
5540	* @param hRegion The MMIO region handle.
5541	* @param pfnWrite Pointer to function which is gonna handle Write
5542	* operations.
5543	* @param pfnRead Pointer to function which is gonna handle Read
5544	* operations.
5545	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5546	* operations. (optional)
5547	* @param pvUser User argument to pass to the callbacks.
5548	*
5549	* @remarks Caller enters the device critical section prior to invoking the
5550	* registered callback methods.
5551	*
5552	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5553	* PDMDevHlpMmioUnmap().
5554	*/
5555	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5556	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5557
5558	/**
5559	* Sets up a ring-0 mapping for an MMIO2 region.
5560	*
5561	* The region must have been created in ring-3 first using
5562	* PDMDevHlpMmio2Create().
5563	*
5564	* @returns VBox status.
5565	* @param pDevIns The device instance to register the ports with.
5566	* @param hRegion The MMIO2 region handle.
5567	* @param offSub Start of what to map into ring-0. Must be page aligned.
5568	* @param cbSub Number of bytes to map into ring-0. Must be page
5569	* aligned. Zero is an alias for everything.
5570	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5571	*
5572	* @thread EMT(0)
5573	* @note Only available at VM creation time.
5574	*
5575	* @sa PDMDevHlpMmio2Create().
5576	*/
5577	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5578	void **ppvMapping));
5579
5580	/**
5581	* Bus master physical memory read from the given PCI device.
5582	*
5583	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5584	* VERR_EM_MEMORY.
5585	* @param pDevIns The device instance.
5586	* @param pPciDev The PCI device structure. If NULL the default
5587	* PCI device for this device instance is used.
5588	* @param GCPhys Physical address start reading from.
5589	* @param pvBuf Where to put the read bits.
5590	* @param cbRead How many bytes to read.
5591	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5592	* @thread Any thread, but the call may involve the emulation thread.
5593	*/
5594	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5595	void *pvBuf, size_t cbRead, uint32_t fFlags));
5596
5597	/**
5598	* Bus master physical memory write from the given PCI device.
5599	*
5600	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5601	* VERR_EM_MEMORY.
5602	* @param pDevIns The device instance.
5603	* @param pPciDev The PCI device structure. If NULL the default
5604	* PCI device for this device instance is used.
5605	* @param GCPhys Physical address to write to.
5606	* @param pvBuf What to write.
5607	* @param cbWrite How many bytes to write.
5608	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5609	* @thread Any thread, but the call may involve the emulation thread.
5610	*/
5611	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5612	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5613
5614	/**
5615	* Set the IRQ for the given PCI device.
5616	*
5617	* @param pDevIns Device instance.
5618	* @param pPciDev The PCI device structure. If NULL the default
5619	* PCI device for this device instance is used.
5620	* @param iIrq IRQ number to set.
5621	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5622	* @thread Any thread, but will involve the emulation thread.
5623	*/
5624	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5625
5626	/**
5627	* Set ISA IRQ for a device.
5628	*
5629	* @param pDevIns Device instance.
5630	* @param iIrq IRQ number to set.
5631	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5632	* @thread Any thread, but will involve the emulation thread.
5633	*/
5634	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5635
5636	/**
5637	* Read physical memory.
5638	*
5639	* @returns VINF_SUCCESS (for now).
5640	* @param pDevIns Device instance.
5641	* @param GCPhys Physical address start reading from.
5642	* @param pvBuf Where to put the read bits.
5643	* @param cbRead How many bytes to read.
5644	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5645	*/
5646	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5647
5648	/**
5649	* Write to physical memory.
5650	*
5651	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5652	* @param pDevIns Device instance.
5653	* @param GCPhys Physical address to write to.
5654	* @param pvBuf What to write.
5655	* @param cbWrite How many bytes to write.
5656	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5657	*/
5658	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5659
5660	/**
5661	* Checks if the Gate A20 is enabled or not.
5662	*
5663	* @returns true if A20 is enabled.
5664	* @returns false if A20 is disabled.
5665	* @param pDevIns Device instance.
5666	* @thread The emulation thread.
5667	*/
5668	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5669
5670	/**
5671	* Gets the VM state.
5672	*
5673	* @returns VM state.
5674	* @param pDevIns The device instance.
5675	* @thread Any thread (just keep in mind that it's volatile info).
5676	*/
5677	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5678
5679	/**
5680	* Gets the VM handle. Restricted API.
5681	*
5682	* @returns VM Handle.
5683	* @param pDevIns Device instance.
5684	*/
5685	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5686
5687	/**
5688	* Gets the VMCPU handle. Restricted API.
5689	*
5690	* @returns VMCPU Handle.
5691	* @param pDevIns The device instance.
5692	*/
5693	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5694
5695	/**
5696	* The the VM CPU ID of the current thread (restricted API).
5697	*
5698	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5699	* @param pDevIns The device instance.
5700	*/
5701	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5702
5703	/**
5704	* Gets the main execution engine for the VM.
5705	*
5706	* @returns VM_EXEC_ENGINE_XXX
5707	* @param pDevIns The device instance.
5708	*/
5709	DECLR0CALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
5710
5711	/** @name Timer handle method wrappers
5712	* @{ */
5713	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5714	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5715	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5716	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5717	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5718	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5719	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5720	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5721	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5722	/** Takes the clock lock then enters the specified critical section. */
5723	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5724	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5725	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5726	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5727	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5728	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5729	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5730	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5731	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5732	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5733	/** @} */
5734
5735	/**
5736	* Get the current virtual clock time in a VM. The clock frequency must be
5737	* queried separately.
5738	*
5739	* @returns Current clock time.
5740	* @param pDevIns The device instance.
5741	*/
5742	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5743
5744	/**
5745	* Get the frequency of the virtual clock.
5746	*
5747	* @returns The clock frequency (not variable at run-time).
5748	* @param pDevIns The device instance.
5749	*/
5750	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5751
5752	/**
5753	* Get the current virtual clock time in a VM, in nanoseconds.
5754	*
5755	* @returns Current clock time (in ns).
5756	* @param pDevIns The device instance.
5757	*/
5758	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5759
5760	/** @name Exported PDM Queue Functions
5761	* @{ */
5762	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5763	DECLR0CALLBACKMEMBER(int, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5764	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5765	/** @} */
5766
5767	/** @name PDM Task
5768	* @{ */
5769	/**
5770	* Triggers the running the given task.
5771	*
5772	* @returns VBox status code.
5773	* @retval VINF_ALREADY_POSTED is the task is already pending.
5774	* @param pDevIns The device instance.
5775	* @param hTask The task to trigger.
5776	* @thread Any thread.
5777	*/
5778	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5779	/** @} */
5780
5781	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5782	* These semaphores can be signalled from ring-0.
5783	* @{ */
5784	/** @sa SUPSemEventSignal */
5785	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5786	/** @sa SUPSemEventWaitNoResume */
5787	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5788	/** @sa SUPSemEventWaitNsAbsIntr */
5789	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5790	/** @sa SUPSemEventWaitNsRelIntr */
5791	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5792	/** @sa SUPSemEventGetResolution */
5793	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5794	/** @} */
5795
5796	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5797	* These semaphores can be signalled from ring-0.
5798	* @{ */
5799	/** @sa SUPSemEventMultiSignal */
5800	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5801	/** @sa SUPSemEventMultiReset */
5802	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5803	/** @sa SUPSemEventMultiWaitNoResume */
5804	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5805	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5806	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5807	/** @sa SUPSemEventMultiWaitNsRelIntr */
5808	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5809	/** @sa SUPSemEventMultiGetResolution */
5810	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5811	/** @} */
5812
5813	/**
5814	* Gets the NOP critical section.
5815	*
5816	* @returns The ring-3 address of the NOP critical section.
5817	* @param pDevIns The device instance.
5818	*/
5819	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5820
5821	/**
5822	* Changes the device level critical section from the automatically created
5823	* default to one desired by the device constructor.
5824	*
5825	* Must first be done in ring-3.
5826	*
5827	* @returns VBox status code.
5828	* @param pDevIns The device instance.
5829	* @param pCritSect The critical section to use. NULL is not
5830	* valid, instead use the NOP critical
5831	* section.
5832	*/
5833	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5834
5835	/** @name Exported PDM Critical Section Functions
5836	* @{ */
5837	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5838	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5839	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5840	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5841	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5842	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5843	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5844	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5845	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5846	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5847	/** @} */
5848
5849	/** @name Exported PDM Read/Write Critical Section Functions
5850	* @{ */
5851	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5852	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5853	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5854	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5855	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5856
5857	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5858	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5859	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5860	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5861	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5862
5863	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5864	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5865	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5866	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5867	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5868	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5869	/** @} */
5870
5871	/**
5872	* Gets the trace buffer handle.
5873	*
5874	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5875	* really inteded for direct usage, thus no inline wrapper function.
5876	*
5877	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5878	* @param pDevIns The device instance.
5879	*/
5880	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5881
5882	/**
5883	* Sets up the PCI bus for the ring-0 context.
5884	*
5885	* This must be called after ring-3 has registered the PCI bus using
5886	* PDMDevHlpPCIBusRegister().
5887	*
5888	* @returns VBox status code.
5889	* @param pDevIns The device instance.
5890	* @param pPciBusReg The PCI bus registration information for ring-0,
5891	* considered volatile and copied.
5892	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5893	*/
5894	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5895
5896	/**
5897	* Sets up the IOMMU for the ring-0 context.
5898	*
5899	* This must be called after ring-3 has registered the IOMMU using
5900	* PDMDevHlpIommuRegister().
5901	*
5902	* @returns VBox status code.
5903	* @param pDevIns The device instance.
5904	* @param pIommuReg The IOMMU registration information for ring-0,
5905	* considered volatile and copied.
5906	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5907	*/
5908	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5909
5910	/**
5911	* Sets up the PIC for the ring-0 context.
5912	*
5913	* This must be called after ring-3 has registered the PIC using
5914	* PDMDevHlpPICRegister().
5915	*
5916	* @returns VBox status code.
5917	* @param pDevIns The device instance.
5918	* @param pPicReg The PIC registration information for ring-0,
5919	* considered volatile and copied.
5920	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5921	*/
5922	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5923
5924	/**
5925	* Sets up the APIC for the ring-0 context.
5926	*
5927	* This must be called after ring-3 has registered the APIC using
5928	* PDMDevHlpApicRegister().
5929	*
5930	* @returns VBox status code.
5931	* @param pDevIns The device instance.
5932	*/
5933	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5934
5935	/**
5936	* Sets up the IOAPIC for the ring-0 context.
5937	*
5938	* This must be called after ring-3 has registered the PIC using
5939	* PDMDevHlpIoApicRegister().
5940	*
5941	* @returns VBox status code.
5942	* @param pDevIns The device instance.
5943	* @param pIoApicReg The PIC registration information for ring-0,
5944	* considered volatile and copied.
5945	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5946	*/
5947	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5948
5949	/**
5950	* Sets up the HPET for the ring-0 context.
5951	*
5952	* This must be called after ring-3 has registered the PIC using
5953	* PDMDevHlpHpetRegister().
5954	*
5955	* @returns VBox status code.
5956	* @param pDevIns The device instance.
5957	* @param pHpetReg The PIC registration information for ring-0,
5958	* considered volatile and copied.
5959	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5960	*/
5961	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5962
5963	/**
5964	* Sets up a physical page access handler type for ring-0 callbacks.
5965	*
5966	* @returns VBox status code.
5967	* @param pDevIns The device instance.
5968	* @param enmKind The kind of access handler.
5969	* @param pfnHandler Pointer to the ring-0 handler callback. NULL if
5970	* the ring-3 handler should be called.
5971	* @param pfnPfHandler The name of the ring-0 \#PF handler, NULL if the
5972	* ring-3 handler should be called.
5973	* @param pszDesc The type description.
5974	* @param hType The type handle registered in ring-3 already.
5975	* @sa PDMDevHlpPGMHandlerPhysicalTypeRegister
5976	*/
5977	DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeSetUpContext, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
5978	PFNPGMPHYSHANDLER pfnHandler,
5979	PFNPGMRZPHYSPFHANDLER pfnPfHandler,
5980	const char *pszDesc, PGMPHYSHANDLERTYPE hType));
5981
5982	/**
5983	* Temporarily turns off the access monitoring of a page within a monitored
5984	* physical write/all page access handler region.
5985	*
5986	* Use this when no further \#PFs are required for that page. Be aware that
5987	* a page directory sync might reset the flags, and turn on access monitoring
5988	* for the page.
5989	*
5990	* The caller must do required page table modifications.
5991	*
5992	* @returns VBox status code.
5993	* @param pDevIns The device instance.
5994	* @param GCPhys The start address of the access handler. This
5995	* must be a fully page aligned range or we risk
5996	* messing up other handlers installed for the
5997	* start and end pages.
5998	* @param GCPhysPage The physical address of the page to turn off
5999	* access monitoring for.
6000	*/
6001	DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
6002
6003	/**
6004	* Mapping an MMIO2 page in place of an MMIO page for direct access.
6005	*
6006	* This is a special optimization used by the VGA device. Call
6007	* PDMDevHlpMmioResetRegion() to undo the mapping.
6008	*
6009	* @returns VBox status code. This API may return VINF_SUCCESS even if no
6010	* remapping is made.
6011	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
6012	*
6013	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
6014	* associated with.
6015	* @param hRegion The handle to the MMIO region.
6016	* @param offRegion The offset into @a hRegion of the page to be
6017	* remapped.
6018	* @param hMmio2 The MMIO2 handle.
6019	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
6020	* mapping.
6021	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
6022	* for the time being.
6023	*/
6024	DECLR0CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6025	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
6026
6027	/**
6028	* Reset a previously modified MMIO region; restore the access flags.
6029	*
6030	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
6031	* intended for some ancient VGA hack. However, it would be great to extend it
6032	* beyond VT-x and/or nested-paging.
6033	*
6034	* @returns VBox status code.
6035	*
6036	* @param pDevIns The device instance @a hRegion is associated with.
6037	* @param hRegion The handle to the MMIO region.
6038	*/
6039	DECLR0CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
6040
6041	/**
6042	* Returns the array of MMIO2 regions that are expected to be registered and
6043	* later mapped into the guest-physical address space for the GIM provider
6044	* configured for the VM.
6045	*
6046	* @returns Pointer to an array of GIM MMIO2 regions, may return NULL.
6047	* @param pDevIns Pointer to the GIM device instance.
6048	* @param pcRegions Where to store the number of items in the array.
6049	*
6050	* @remarks The caller does not own and therefore must -NOT- try to free the
6051	* returned pointer.
6052	*/
6053	DECLR0CALLBACKMEMBER(PGIMMMIO2REGION, pfnGIMGetMmio2Regions,(PPDMDEVINS pDevIns, uint32_t *pcRegions));
6054
6055	/** Space reserved for future members.
6056	* @{ */
6057	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
6058	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
6059	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
6060	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
6061	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
6062	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
6063	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
6064	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
6065	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
6066	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
6067	/** @} */
6068
6069	/** Just a safety precaution. */
6070	uint32_t u32TheEnd;
6071	} PDMDEVHLPR0;
6072	/** Pointer PDM Device R0 API. */
6073	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
6074	/** Pointer PDM Device GC API. */
6075	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
6076
6077	/** Current PDMDEVHLP version number. */
6078	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 27, 0)
6079
6080
6081	/**
6082	* PDM Device Instance.
6083	*/
6084	typedef struct PDMDEVINSR3
6085	{
6086	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
6087	uint32_t u32Version;
6088	/** Device instance number. */
6089	uint32_t iInstance;
6090	/** Size of the ring-3, raw-mode and shared bits. */
6091	uint32_t cbRing3;
6092	/** Set if ring-0 context is enabled. */
6093	bool fR0Enabled;
6094	/** Set if raw-mode context is enabled. */
6095	bool fRCEnabled;
6096	/** Alignment padding. */
6097	bool afReserved[2];
6098	/** Pointer the HC PDM Device API. */
6099	PCPDMDEVHLPR3 pHlpR3;
6100	/** Pointer to the shared device instance data. */
6101	RTR3PTR pvInstanceDataR3;
6102	/** Pointer to the device instance data for ring-3. */
6103	RTR3PTR pvInstanceDataForR3;
6104	/** The critical section for the device.
6105	*
6106	* TM and IOM will enter this critical section before calling into the device
6107	* code. PDM will when doing power on, power off, reset, suspend and resume
6108	* notifications. SSM will currently not, but this will be changed later on.
6109	*
6110	* The device gets a critical section automatically assigned to it before
6111	* the constructor is called. If the constructor wishes to use a different
6112	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6113	* very early on.
6114	*/
6115	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
6116	/** Pointer to device registration structure. */
6117	R3PTRTYPE(PCPDMDEVREG) pReg;
6118	/** Configuration handle. */
6119	R3PTRTYPE(PCFGMNODE) pCfg;
6120	/** The base interface of the device.
6121	*
6122	* The device constructor initializes this if it has any
6123	* device level interfaces to export. To obtain this interface
6124	* call PDMR3QueryDevice(). */
6125	PDMIBASE IBase;
6126
6127	/** Tracing indicator. */
6128	uint32_t fTracing;
6129	/** The tracing ID of this device. */
6130	uint32_t idTracing;
6131
6132	/** Ring-3 pointer to the raw-mode device instance. */
6133	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
6134	/** Raw-mode address of the raw-mode device instance. */
6135	RTRGPTR pDevInsForRC;
6136	/** Ring-3 pointer to the raw-mode instance data. */
6137	RTR3PTR pvInstanceDataForRCR3;
6138
6139	/** PCI device structure size. */
6140	uint32_t cbPciDev;
6141	/** Number of PCI devices in apPciDevs. */
6142	uint32_t cPciDevs;
6143	/** Pointer to the PCI devices for this device.
6144	* (Allocated after the shared instance data.)
6145	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6146	* two devices ever needing it can use cbPciDev and do the address
6147	* calculations that for entries 8+. */
6148	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6149
6150	/** Temporarily. */
6151	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
6152	/** Temporarily. */
6153	RTR0PTR pvInstanceDataR0;
6154	/** Temporarily. */
6155	RTRCPTR pvInstanceDataRC;
6156	/** Align the internal data more naturally. */
6157	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
6158
6159	/** Internal data. */
6160	union
6161	{
6162	#ifdef PDMDEVINSINT_DECLARED
6163	PDMDEVINSINTR3 s;
6164	#endif
6165	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
6166	} Internal;
6167
6168	/** Device instance data for ring-3. The size of this area is defined
6169	* in the PDMDEVREG::cbInstanceR3 field. */
6170	char achInstanceData[8];
6171	} PDMDEVINSR3;
6172
6173	/** Current PDMDEVINSR3 version number. */
6174	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
6175
6176	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
6177	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
6178
6179
6180	/**
6181	* PDM ring-0 device instance.
6182	*/
6183	typedef struct PDMDEVINSR0
6184	{
6185	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
6186	uint32_t u32Version;
6187	/** Device instance number. */
6188	uint32_t iInstance;
6189
6190	/** Pointer the HC PDM Device API. */
6191	PCPDMDEVHLPR0 pHlpR0;
6192	/** Pointer to the shared device instance data. */
6193	RTR0PTR pvInstanceDataR0;
6194	/** Pointer to the device instance data for ring-0. */
6195	RTR0PTR pvInstanceDataForR0;
6196	/** The critical section for the device.
6197	*
6198	* TM and IOM will enter this critical section before calling into the device
6199	* code. PDM will when doing power on, power off, reset, suspend and resume
6200	* notifications. SSM will currently not, but this will be changed later on.
6201	*
6202	* The device gets a critical section automatically assigned to it before
6203	* the constructor is called. If the constructor wishes to use a different
6204	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6205	* very early on.
6206	*/
6207	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
6208	/** Pointer to the ring-0 device registration structure. */
6209	R0PTRTYPE(PCPDMDEVREGR0) pReg;
6210	/** Ring-3 address of the ring-3 device instance. */
6211	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
6212	/** Ring-0 pointer to the ring-3 device instance. */
6213	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
6214	/** Ring-0 pointer to the ring-3 instance data. */
6215	RTR0PTR pvInstanceDataForR3R0;
6216	/** Raw-mode address of the raw-mode device instance. */
6217	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
6218	/** Ring-0 pointer to the raw-mode device instance. */
6219	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
6220	/** Ring-0 pointer to the raw-mode instance data. */
6221	RTR0PTR pvInstanceDataForRCR0;
6222
6223	/** PCI device structure size. */
6224	uint32_t cbPciDev;
6225	/** Number of PCI devices in apPciDevs. */
6226	uint32_t cPciDevs;
6227	/** Pointer to the PCI devices for this device.
6228	* (Allocated after the shared instance data.)
6229	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6230	* two devices ever needing it can use cbPciDev and do the address
6231	* calculations that for entries 8+. */
6232	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6233
6234	/** Align the internal data more naturally. */
6235	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
6236
6237	/** Internal data. */
6238	union
6239	{
6240	#ifdef PDMDEVINSINT_DECLARED
6241	PDMDEVINSINTR0 s;
6242	#endif
6243	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
6244	} Internal;
6245
6246	/** Device instance data for ring-0. The size of this area is defined
6247	* in the PDMDEVREG::cbInstanceR0 field. */
6248	char achInstanceData[8];
6249	} PDMDEVINSR0;
6250
6251	/** Current PDMDEVINSR0 version number. */
6252	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
6253
6254
6255	/**
6256	* PDM raw-mode device instance.
6257	*/
6258	typedef struct PDMDEVINSRC
6259	{
6260	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
6261	uint32_t u32Version;
6262	/** Device instance number. */
6263	uint32_t iInstance;
6264
6265	/** Pointer the HC PDM Device API. */
6266	PCPDMDEVHLPRC pHlpRC;
6267	/** Pointer to the shared device instance data. */
6268	RTRGPTR pvInstanceDataRC;
6269	/** Pointer to the device instance data for raw-mode. */
6270	RTRGPTR pvInstanceDataForRC;
6271	/** The critical section for the device.
6272	*
6273	* TM and IOM will enter this critical section before calling into the device
6274	* code. PDM will when doing power on, power off, reset, suspend and resume
6275	* notifications. SSM will currently not, but this will be changed later on.
6276	*
6277	* The device gets a critical section automatically assigned to it before
6278	* the constructor is called. If the constructor wishes to use a different
6279	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6280	* very early on.
6281	*/
6282	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
6283	/** Pointer to the raw-mode device registration structure. */
6284	RGPTRTYPE(PCPDMDEVREGRC) pReg;
6285
6286	/** PCI device structure size. */
6287	uint32_t cbPciDev;
6288	/** Number of PCI devices in apPciDevs. */
6289	uint32_t cPciDevs;
6290	/** Pointer to the PCI devices for this device.
6291	* (Allocated after the shared instance data.) */
6292	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6293
6294	/** Align the internal data more naturally. */
6295	uint32_t au32Padding[14];
6296
6297	/** Internal data. */
6298	union
6299	{
6300	#ifdef PDMDEVINSINT_DECLARED
6301	PDMDEVINSINTRC s;
6302	#endif
6303	uint8_t padding[0x10];
6304	} Internal;
6305
6306	/** Device instance data for ring-0. The size of this area is defined
6307	* in the PDMDEVREG::cbInstanceR0 field. */
6308	char achInstanceData[8];
6309	} PDMDEVINSRC;
6310
6311	/** Current PDMDEVINSR0 version number. */
6312	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
6313
6314
6315	/** @def PDM_DEVINS_VERSION
6316	* Current PDMDEVINS version number. */
6317	/** @typedef PDMDEVINS
6318	* The device instance structure for the current context. */
6319	#ifdef IN_RING3
6320	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
6321	typedef PDMDEVINSR3 PDMDEVINS;
6322	#elif defined(IN_RING0)
6323	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
6324	typedef PDMDEVINSR0 PDMDEVINS;
6325	#elif defined(IN_RC)
6326	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
6327	typedef PDMDEVINSRC PDMDEVINS;
6328	#else
6329	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
6330	#endif
6331
6332	/**
6333	* Get the pointer to an PCI device.
6334	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6335	*/
6336	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
6337	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
6338	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
6339
6340	/**
6341	* Calc the pointer to of a given PCI device.
6342	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6343	*/
6344	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
6345	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
6346	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
6347	: (PPDMPCIDEV)NULL )
6348
6349
6350	/**
6351	* Checks the structure versions of the device instance and device helpers,
6352	* returning if they are incompatible.
6353	*
6354	* This is for use in the constructor.
6355	*
6356	* @param pDevIns The device instance pointer.
6357	*/
6358	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
6359	do \
6360	{ \
6361	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6362	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6363	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6364	VERR_PDM_DEVINS_VERSION_MISMATCH); \
6365	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6366	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6367	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
6368	} while (0)
6369
6370	/**
6371	* Quietly checks the structure versions of the device instance and device
6372	* helpers, returning if they are incompatible.
6373	*
6374	* This is for use in the destructor.
6375	*
6376	* @param pDevIns The device instance pointer.
6377	*/
6378	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
6379	do \
6380	{ \
6381	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6382	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
6383	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
6384	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
6385	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
6386	} while (0)
6387
6388	/**
6389	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
6390	* constructor - returns on failure.
6391	*
6392	* This should be invoked after having initialized the instance data
6393	* sufficiently for the correct operation of the destructor. The destructor is
6394	* always called!
6395	*
6396	* @param pDevIns Pointer to the PDM device instance.
6397	* @param pszValidValues Patterns describing the valid value names. See
6398	* RTStrSimplePatternMultiMatch for details on the
6399	* pattern syntax.
6400	* @param pszValidNodes Patterns describing the valid node (key) names.
6401	* Pass empty string if no valid nodes.
6402	*/
6403	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
6404	do \
6405	{ \
6406	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
6407	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
6408	if (RT_SUCCESS(rcValCfg)) \
6409	{ /* likely */ } else return rcValCfg; \
6410	} while (0)
6411
6412	/** @def PDMDEV_ASSERT_EMT
6413	* Assert that the current thread is the emulation thread.
6414	*/
6415	#ifdef VBOX_STRICT
6416	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6417	#else
6418	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
6419	#endif
6420
6421	/** @def PDMDEV_ASSERT_OTHER
6422	* Assert that the current thread is NOT the emulation thread.
6423	*/
6424	#ifdef VBOX_STRICT
6425	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6426	#else
6427	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
6428	#endif
6429
6430	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
6431	* Assert that the current thread is owner of the VM lock.
6432	*/
6433	#ifdef VBOX_STRICT
6434	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6435	#else
6436	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
6437	#endif
6438
6439	/** @def PDMDEV_SET_ERROR
6440	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
6441	*/
6442	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
6443	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
6444
6445	/** @def PDMDEV_SET_RUNTIME_ERROR
6446	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
6447	*/
6448	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
6449	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
6450
6451	/** @def PDMDEVINS_2_RCPTR
6452	* Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
6453	*/
6454	#ifdef IN_RC
6455	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
6456	#else
6457	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
6458	#endif
6459
6460	/** @def PDMDEVINS_2_R3PTR
6461	* Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
6462	*/
6463	#ifdef IN_RING3
6464	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
6465	#else
6466	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
6467	#endif
6468
6469	/** @def PDMDEVINS_2_R0PTR
6470	* Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
6471	*/
6472	#ifdef IN_RING0
6473	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
6474	#else
6475	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
6476	#endif
6477
6478	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
6479	* Converts a PDM device instance data pointer to a ring-0 one.
6480	* @deprecated
6481	*/
6482	#ifdef IN_RING0
6483	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
6484	#else
6485	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
6486	#endif
6487
6488
6489	/** @def PDMDEVINS_2_DATA
6490	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
6491	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
6492	*
6493	* @note Do no use this macro in common code working on a core structure which
6494	* device specific code has expanded.
6495	*/
6496	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6497	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
6498	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6499	{ \
6500	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
6501	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
6502	return pLambdaRet; \
6503	}(a_pDevIns))
6504	#else
6505	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
6506	#endif
6507
6508	/** @def PDMDEVINS_2_DATA_CC
6509	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
6510	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
6511	*
6512	* @note Do no use this macro in common code working on a core structure which
6513	* device specific code has expanded.
6514	*/
6515	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6516	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
6517	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6518	{ \
6519	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
6520	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
6521	return pLambdaRet; \
6522	}(a_pDevIns))
6523	#else
6524	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
6525	#endif
6526
6527
6528	#ifdef IN_RING3
6529
6530	/**
6531	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
6532	*/
6533	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6534	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
6535	PIOMIOPORTHANDLE phIoPorts)
6536	{
6537	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6538	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6539	if (RT_SUCCESS(rc))
6540	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6541	return rc;
6542	}
6543
6544	/**
6545	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
6546	*/
6547	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6548	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6549	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6550	{
6551	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6552	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6553	if (RT_SUCCESS(rc))
6554	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6555	return rc;
6556	}
6557
6558	/**
6559	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
6560	*/
6561	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6562	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6563	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6564	{
6565	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6566	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6567	if (RT_SUCCESS(rc))
6568	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6569	return rc;
6570	}
6571
6572	/**
6573	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
6574	*/
6575	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6576	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6577	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6578	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6579	{
6580	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6581	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6582	if (RT_SUCCESS(rc))
6583	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6584	return rc;
6585	}
6586
6587	/**
6588	* @sa PDMDevHlpIoPortCreateEx
6589	*/
6590	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6591	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6592	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6593	{
6594	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
6595	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6596	}
6597
6598
6599	/**
6600	* @sa PDMDevHlpIoPortCreateEx
6601	*/
6602	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6603	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6604	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6605	{
6606	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6607	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6608	}
6609
6610	/**
6611	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6612	*/
6613	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6614	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6615	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6616	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6617	{
6618	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6619	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6620	}
6621
6622	/**
6623	* @copydoc PDMDEVHLPR3::pfnIoPortMap
6624	*/
6625	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6626	{
6627	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6628	}
6629
6630	/**
6631	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6632	*/
6633	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6634	{
6635	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6636	}
6637
6638	/**
6639	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6640	*/
6641	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6642	{
6643	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6644	}
6645
6646
6647	#endif /* IN_RING3 */
6648	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6649
6650	/**
6651	* @sa PDMDevHlpIoPortSetUpContextEx
6652	*/
6653	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6654	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6655	{
6656	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6657	}
6658
6659	/**
6660	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6661	*/
6662	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6663	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6664	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6665	{
6666	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6667	}
6668
6669	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6670	#ifdef IN_RING3
6671
6672	/**
6673	* @sa PDMDevHlpMmioCreateEx
6674	*/
6675	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6676	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6677	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6678	{
6679	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6680	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6681	}
6682
6683	/**
6684	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6685	*/
6686	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6687	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6688	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6689	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6690	{
6691	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6692	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6693	}
6694
6695	/**
6696	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6697	*/
6698	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6699	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6700	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6701	{
6702	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6703	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6704	if (RT_SUCCESS(rc))
6705	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6706	return rc;
6707	}
6708
6709	/**
6710	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6711	*/
6712	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6713	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6714	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6715	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6716	{
6717	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6718	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6719	if (RT_SUCCESS(rc))
6720	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6721	return rc;
6722	}
6723
6724	/**
6725	* @copydoc PDMDEVHLPR3::pfnMmioMap
6726	*/
6727	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6728	{
6729	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6730	}
6731
6732	/**
6733	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6734	*/
6735	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6736	{
6737	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6738	}
6739
6740	/**
6741	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6742	*/
6743	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6744	{
6745	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6746	}
6747
6748	/**
6749	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6750	*/
6751	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6752	{
6753	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6754	}
6755
6756	#endif /* IN_RING3 */
6757	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6758
6759	/**
6760	* @sa PDMDevHlpMmioSetUpContextEx
6761	*/
6762	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6763	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6764	{
6765	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6766	}
6767
6768	/**
6769	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6770	*/
6771	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6772	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6773	{
6774	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6775	}
6776
6777	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6778	#ifdef IN_RING3
6779
6780	/**
6781	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6782	*/
6783	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6784	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6785	{
6786	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6787	}
6788
6789	/**
6790	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6791	*/
6792	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6793	{
6794	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6795	}
6796
6797	/**
6798	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6799	*/
6800	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6801	{
6802	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6803	}
6804
6805	/**
6806	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6807	*/
6808	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6809	{
6810	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6811	}
6812
6813	/**
6814	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6815	*/
6816	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6817	{
6818	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6819	}
6820
6821	/**
6822	* @copydoc PDMDEVHLPR3::pfnMmio2QueryAndResetDirtyBitmap
6823	*/
6824	DECLINLINE(int) PDMDevHlpMmio2QueryAndResetDirtyBitmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6825	void *pvBitmap, size_t cbBitmap)
6826	{
6827	return pDevIns->pHlpR3->pfnMmio2QueryAndResetDirtyBitmap(pDevIns, hRegion, pvBitmap, cbBitmap);
6828	}
6829
6830	/**
6831	* Reset the dirty bitmap tracking for an MMIO2 region.
6832	*
6833	* The MMIO2 region must have been created with the
6834	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
6835	*
6836	* @returns VBox status code.
6837	* @param pDevIns The device instance.
6838	* @param hRegion The MMIO2 region handle.
6839	*/
6840	DECLINLINE(int) PDMDevHlpMmio2ResetDirtyBitmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6841	{
6842	return pDevIns->pHlpR3->pfnMmio2QueryAndResetDirtyBitmap(pDevIns, hRegion, NULL, 0);
6843	}
6844
6845	/**
6846	* @copydoc PDMDEVHLPR3::pfnMmio2ControlDirtyPageTracking
6847	*/
6848	DECLINLINE(int) PDMDevHlpMmio2ControlDirtyPageTracking(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, bool fEnabled)
6849	{
6850	return pDevIns->pHlpR3->pfnMmio2ControlDirtyPageTracking(pDevIns, hRegion, fEnabled);
6851	}
6852
6853	#endif /* IN_RING3 */
6854
6855	/**
6856	* @copydoc PDMDEVHLPR3::pfnMmioMapMmio2Page
6857	*/
6858	DECLINLINE(int) PDMDevHlpMmioMapMmio2Page(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6859	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags)
6860	{
6861	return pDevIns->CTX_SUFF(pHlp)->pfnMmioMapMmio2Page(pDevIns, hRegion, offRegion, hMmio2, offMmio2, fPageFlags);
6862	}
6863
6864	/**
6865	* @copydoc PDMDEVHLPR3::pfnMmioResetRegion
6866	*/
6867	DECLINLINE(int) PDMDevHlpMmioResetRegion(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6868	{
6869	return pDevIns->CTX_SUFF(pHlp)->pfnMmioResetRegion(pDevIns, hRegion);
6870	}
6871
6872	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6873
6874	/**
6875	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6876	*/
6877	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6878	size_t offSub, size_t cbSub, void **ppvMapping)
6879	{
6880	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6881	}
6882
6883	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6884	#ifdef IN_RING3
6885
6886	/**
6887	* @copydoc PDMDEVHLPR3::pfnROMRegister
6888	*/
6889	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6890	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6891	{
6892	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6893	}
6894
6895	/**
6896	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6897	*/
6898	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6899	{
6900	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6901	}
6902
6903	/**
6904	* Register a save state data unit.
6905	*
6906	* @returns VBox status.
6907	* @param pDevIns The device instance.
6908	* @param uVersion Data layout version number.
6909	* @param cbGuess The approximate amount of data in the unit.
6910	* Only for progress indicators.
6911	* @param pfnSaveExec Execute save callback, optional.
6912	* @param pfnLoadExec Execute load callback, optional.
6913	*/
6914	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6915	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6916	{
6917	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6918	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6919	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6920	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6921	}
6922
6923	/**
6924	* Register a save state data unit with a live save callback as well.
6925	*
6926	* @returns VBox status.
6927	* @param pDevIns The device instance.
6928	* @param uVersion Data layout version number.
6929	* @param cbGuess The approximate amount of data in the unit.
6930	* Only for progress indicators.
6931	* @param pfnLiveExec Execute live callback, optional.
6932	* @param pfnSaveExec Execute save callback, optional.
6933	* @param pfnLoadExec Execute load callback, optional.
6934	*/
6935	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6936	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6937	{
6938	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6939	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6940	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6941	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6942	}
6943
6944	/**
6945	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6946	*/
6947	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6948	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6949	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6950	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6951	{
6952	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6953	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6954	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6955	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6956	}
6957
6958	/**
6959	* @copydoc PDMDEVHLPR3::pfnSSMRegisterLegacy
6960	*/
6961	DECLINLINE(int) PDMDevHlpSSMRegisterLegacy(PPDMDEVINS pDevIns, const char *pszOldName, PFNSSMDEVLOADPREP pfnLoadPrep,
6962	PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6963	{
6964	return pDevIns->pHlpR3->pfnSSMRegisterLegacy(pDevIns, pszOldName, pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6965	}
6966
6967	/**
6968	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6969	*/
6970	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6971	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6972	{
6973	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6974	}
6975
6976	#endif /* IN_RING3 */
6977
6978	/**
6979	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6980	*/
6981	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6982	{
6983	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6984	}
6985
6986	/**
6987	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6988	*/
6989	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6990	{
6991	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6992	}
6993
6994	/**
6995	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6996	*/
6997	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6998	{
6999	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
7000	}
7001
7002	/**
7003	* @copydoc PDMDEVHLPR3::pfnTimerGet
7004	*/
7005	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7006	{
7007	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
7008	}
7009
7010	/**
7011	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
7012	*/
7013	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7014	{
7015	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
7016	}
7017
7018	/**
7019	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
7020	*/
7021	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7022	{
7023	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
7024	}
7025
7026	/**
7027	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
7028	*/
7029	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7030	{
7031	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
7032	}
7033
7034	/**
7035	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
7036	*/
7037	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7038	{
7039	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
7040	}
7041
7042	/**
7043	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
7044	*/
7045	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
7046	{
7047	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
7048	}
7049
7050	/**
7051	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
7052	*/
7053	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
7054	{
7055	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
7056	}
7057
7058	/**
7059	* @copydoc PDMDEVHLPR3::pfnTimerSet
7060	*/
7061	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
7062	{
7063	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
7064	}
7065
7066	/**
7067	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
7068	*/
7069	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
7070	{
7071	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
7072	}
7073
7074	/**
7075	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
7076	*/
7077	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
7078	{
7079	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
7080	}
7081
7082	/**
7083	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
7084	*/
7085	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
7086	{
7087	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
7088	}
7089
7090	/**
7091	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
7092	*/
7093	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
7094	{
7095	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
7096	}
7097
7098	/**
7099	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
7100	*/
7101	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
7102	{
7103	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
7104	}
7105
7106	/**
7107	* @copydoc PDMDEVHLPR3::pfnTimerStop
7108	*/
7109	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7110	{
7111	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
7112	}
7113
7114	/**
7115	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
7116	*/
7117	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7118	{
7119	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
7120	}
7121
7122	/**
7123	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
7124	*/
7125	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
7126	{
7127	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
7128	}
7129
7130	#ifdef IN_RING3
7131
7132	/**
7133	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
7134	*/
7135	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
7136	{
7137	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
7138	}
7139
7140	/**
7141	* @copydoc PDMDEVHLPR3::pfnTimerSave
7142	*/
7143	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
7144	{
7145	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
7146	}
7147
7148	/**
7149	* @copydoc PDMDEVHLPR3::pfnTimerLoad
7150	*/
7151	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
7152	{
7153	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
7154	}
7155
7156	/**
7157	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
7158	*/
7159	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7160	{
7161	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
7162	}
7163
7164	/**
7165	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
7166	*/
7167	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
7168	{
7169	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
7170	}
7171
7172	#endif
7173
7174	/**
7175	* Read physical memory - unknown data usage.
7176	*
7177	* @returns VINF_SUCCESS (for now).
7178	* @param pDevIns The device instance.
7179	* @param GCPhys Physical address start reading from.
7180	* @param pvBuf Where to put the read bits.
7181	* @param cbRead How many bytes to read.
7182	* @thread Any thread, but the call may involve the emulation thread.
7183	*/
7184	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7185	{
7186	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7187	}
7188
7189	/**
7190	* Write to physical memory - unknown data usage.
7191	*
7192	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7193	* @param pDevIns The device instance.
7194	* @param GCPhys Physical address to write to.
7195	* @param pvBuf What to write.
7196	* @param cbWrite How many bytes to write.
7197	* @thread Any thread, but the call may involve the emulation thread.
7198	*/
7199	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7200	{
7201	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7202	}
7203
7204	/**
7205	* Read physical memory - reads meta data processed by the device.
7206	*
7207	* @returns VINF_SUCCESS (for now).
7208	* @param pDevIns The device instance.
7209	* @param GCPhys Physical address start reading from.
7210	* @param pvBuf Where to put the read bits.
7211	* @param cbRead How many bytes to read.
7212	* @thread Any thread, but the call may involve the emulation thread.
7213	*/
7214	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7215	{
7216	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7217	}
7218
7219	/**
7220	* Write to physical memory - written data was created/altered by the device.
7221	*
7222	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7223	* @param pDevIns The device instance.
7224	* @param GCPhys Physical address to write to.
7225	* @param pvBuf What to write.
7226	* @param cbWrite How many bytes to write.
7227	* @thread Any thread, but the call may involve the emulation thread.
7228	*/
7229	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7230	{
7231	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7232	}
7233
7234	/**
7235	* Read physical memory - read data will not be touched by the device.
7236	*
7237	* @returns VINF_SUCCESS (for now).
7238	* @param pDevIns The device instance.
7239	* @param GCPhys Physical address start reading from.
7240	* @param pvBuf Where to put the read bits.
7241	* @param cbRead How many bytes to read.
7242	* @thread Any thread, but the call may involve the emulation thread.
7243	*/
7244	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7245	{
7246	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7247	}
7248
7249	/**
7250	* Write to physical memory - written data was not touched/created by the device.
7251	*
7252	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7253	* @param pDevIns The device instance.
7254	* @param GCPhys Physical address to write to.
7255	* @param pvBuf What to write.
7256	* @param cbWrite How many bytes to write.
7257	* @thread Any thread, but the call may involve the emulation thread.
7258	*/
7259	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7260	{
7261	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7262	}
7263
7264	#ifdef IN_RING3
7265
7266	/**
7267	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
7268	*/
7269	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
7270	{
7271	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
7272	}
7273
7274	/**
7275	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
7276	*/
7277	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
7278	PPGMPAGEMAPLOCK pLock)
7279	{
7280	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
7281	}
7282
7283	/**
7284	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
7285	*/
7286	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
7287	{
7288	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
7289	}
7290
7291	/**
7292	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
7293	*/
7294	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7295	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
7296	{
7297	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7298	}
7299
7300	/**
7301	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
7302	*/
7303	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7304	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
7305	{
7306	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7307	}
7308
7309	/**
7310	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
7311	*/
7312	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
7313	{
7314	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
7315	}
7316
7317	/**
7318	* @copydoc PDMDEVHLPR3::pfnPhysIsGCPhysNormal
7319	*/
7320	DECLINLINE(bool) PDMDevHlpPhysIsGCPhysNormal(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
7321	{
7322	return pDevIns->CTX_SUFF(pHlp)->pfnPhysIsGCPhysNormal(pDevIns, GCPhys);
7323	}
7324
7325	/**
7326	* @copydoc PDMDEVHLPR3::pfnPhysChangeMemBalloon
7327	*/
7328	DECLINLINE(int) PDMDevHlpPhysChangeMemBalloon(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
7329	{
7330	return pDevIns->CTX_SUFF(pHlp)->pfnPhysChangeMemBalloon(pDevIns, fInflate, cPages, paPhysPage);
7331	}
7332
7333	/**
7334	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
7335	*/
7336	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
7337	{
7338	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
7339	}
7340
7341	/**
7342	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestScalableBusFrequency
7343	*/
7344	DECLINLINE(uint64_t) PDMDevHlpCpuGetGuestScalableBusFrequency(PPDMDEVINS pDevIns)
7345	{
7346	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestScalableBusFrequency(pDevIns);
7347	}
7348
7349	/**
7350	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
7351	*/
7352	DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth)
7353	{
7354	pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
7355	}
7356
7357	/**
7358	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
7359	*/
7360	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
7361	{
7362	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
7363	}
7364
7365	/**
7366	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
7367	*/
7368	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
7369	{
7370	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
7371	}
7372
7373	/**
7374	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
7375	*/
7376	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
7377	{
7378	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
7379	}
7380
7381	/**
7382	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
7383	*/
7384	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
7385	{
7386	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
7387	}
7388
7389	/**
7390	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
7391	*/
7392	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
7393	{
7394	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
7395	}
7396
7397	/**
7398	* Allocating string printf.
7399	*
7400	* @returns Pointer to the string.
7401	* @param pDevIns The device instance.
7402	* @param enmTag The statistics tag.
7403	* @param pszFormat The format string.
7404	* @param ... Format arguments.
7405	*/
7406	DECLINLINE(char ) RT_IPRT_FORMAT_ATTR(2, 3) PDMDevHlpMMHeapAPrintf(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, ...)
7407	{
7408	va_list va;
7409	va_start(va, pszFormat);
7410	char *psz = pDevIns->pHlpR3->pfnMMHeapAPrintfV(pDevIns, enmTag, pszFormat, va);
7411	va_end(va);
7412
7413	return psz;
7414	}
7415
7416	/**
7417	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
7418	*/
7419	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
7420	{
7421	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
7422	}
7423
7424	/**
7425	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSize
7426	*/
7427	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSize(PPDMDEVINS pDevIns)
7428	{
7429	return pDevIns->pHlpR3->pfnMMPhysGetRamSize(pDevIns);
7430	}
7431
7432	/**
7433	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeBelow4GB
7434	*/
7435	DECLINLINE(uint32_t) PDMDevHlpMMPhysGetRamSizeBelow4GB(PPDMDEVINS pDevIns)
7436	{
7437	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeBelow4GB(pDevIns);
7438	}
7439
7440	/**
7441	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeAbove4GB
7442	*/
7443	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSizeAbove4GB(PPDMDEVINS pDevIns)
7444	{
7445	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeAbove4GB(pDevIns);
7446	}
7447	#endif /* IN_RING3 */
7448
7449	/**
7450	* @copydoc PDMDEVHLPR3::pfnVMState
7451	*/
7452	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
7453	{
7454	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
7455	}
7456
7457	#ifdef IN_RING3
7458
7459	/**
7460	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
7461	*/
7462	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
7463	{
7464	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
7465	}
7466
7467	/**
7468	* Set the VM error message
7469	*
7470	* @returns rc.
7471	* @param pDevIns The device instance.
7472	* @param rc VBox status code.
7473	* @param SRC_POS Use RT_SRC_POS.
7474	* @param pszFormat Error message format string.
7475	* @param ... Error message arguments.
7476	* @sa VMSetError
7477	*/
7478	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
7479	const char *pszFormat, ...)
7480	{
7481	va_list va;
7482	va_start(va, pszFormat);
7483	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
7484	va_end(va);
7485	return rc;
7486	}
7487
7488	/**
7489	* Set the VM runtime error message
7490	*
7491	* @returns VBox status code.
7492	* @param pDevIns The device instance.
7493	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
7494	* @param pszErrorId Error ID string.
7495	* @param pszFormat Error message format string.
7496	* @param ... Error message arguments.
7497	* @sa VMSetRuntimeError
7498	*/
7499	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
7500	const char *pszFormat, ...)
7501	{
7502	va_list va;
7503	int rc;
7504	va_start(va, pszFormat);
7505	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
7506	va_end(va);
7507	return rc;
7508	}
7509
7510	/**
7511	* @copydoc PDMDEVHLPR3::pfnVMWaitForDeviceReady
7512	*/
7513	DECLINLINE(int) PDMDevHlpVMWaitForDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7514	{
7515	return pDevIns->CTX_SUFF(pHlp)->pfnVMWaitForDeviceReady(pDevIns, idCpu);
7516	}
7517
7518	/**
7519	* @copydoc PDMDEVHLPR3::pfnVMNotifyCpuDeviceReady
7520	*/
7521	DECLINLINE(int) PDMDevHlpVMNotifyCpuDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7522	{
7523	return pDevIns->CTX_SUFF(pHlp)->pfnVMNotifyCpuDeviceReady(pDevIns, idCpu);
7524	}
7525
7526	/**
7527	* Convenience wrapper for VMR3ReqCallU.
7528	*
7529	* This assumes (1) you're calling a function that returns an VBox status code
7530	* and that you do not wish to wait for it to complete.
7531	*
7532	* @returns VBox status code returned by VMR3ReqCallVU.
7533	*
7534	* @param pDevIns The device instance.
7535	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7536	* one of the following special values:
7537	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7538	* @param pfnFunction Pointer to the function to call.
7539	* @param cArgs Number of arguments following in the ellipsis.
7540	* @param ... Argument list.
7541	*
7542	* @remarks See remarks on VMR3ReqCallVU.
7543	*/
7544	DECLINLINE(int) PDMDevHlpVMReqCallNoWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7545	{
7546	va_list Args;
7547	va_start(Args, cArgs);
7548	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqCallNoWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7549	va_end(Args);
7550	return rc;
7551	}
7552
7553	/**
7554	* Convenience wrapper for VMR3ReqCallU.
7555	*
7556	* This assumes (1) you're calling a function that returns void, (2) that you
7557	* wish to wait for ever for it to return, and (3) that it's priority request
7558	* that can be safely be handled during async suspend and power off.
7559	*
7560	* @returns VBox status code of VMR3ReqCallVU.
7561	*
7562	* @param pDevIns The device instance.
7563	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7564	* one of the following special values:
7565	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7566	* @param pfnFunction Pointer to the function to call.
7567	* @param cArgs Number of arguments following in the ellipsis.
7568	* @param ... Argument list.
7569	*
7570	* @remarks See remarks on VMR3ReqCallVU.
7571	*/
7572	DECLINLINE(int) PDMDevHlpVMReqPriorityCallWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7573	{
7574	va_list Args;
7575	va_start(Args, cArgs);
7576	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqPriorityCallWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7577	va_end(Args);
7578	return rc;
7579	}
7580
7581	#endif /* IN_RING3 */
7582
7583	/**
7584	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
7585	*
7586	* @returns VBox status code which must be passed up to the VMM. This will be
7587	* VINF_SUCCESS in non-strict builds.
7588	* @param pDevIns The device instance.
7589	* @param SRC_POS Use RT_SRC_POS.
7590	* @param pszFormat Message. (optional)
7591	* @param ... Message parameters.
7592	*/
7593	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
7594	{
7595	#ifdef VBOX_STRICT
7596	# ifdef IN_RING3
7597	int rc;
7598	va_list args;
7599	va_start(args, pszFormat);
7600	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
7601	va_end(args);
7602	return rc;
7603	# else
7604	NOREF(pDevIns);
7605	NOREF(pszFile);
7606	NOREF(iLine);
7607	NOREF(pszFunction);
7608	NOREF(pszFormat);
7609	return VINF_EM_DBG_STOP;
7610	# endif
7611	#else
7612	NOREF(pDevIns);
7613	NOREF(pszFile);
7614	NOREF(iLine);
7615	NOREF(pszFunction);
7616	NOREF(pszFormat);
7617	return VINF_SUCCESS;
7618	#endif
7619	}
7620
7621	#ifdef IN_RING3
7622
7623	/**
7624	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
7625	*/
7626	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
7627	{
7628	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
7629	}
7630
7631	/**
7632	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
7633	*/
7634	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
7635	{
7636	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
7637	}
7638
7639	/**
7640	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
7641	*/
7642	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
7643	{
7644	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
7645	}
7646
7647	/**
7648	* @copydoc PDMDEVHLPR3::pfnDBGFReportBugCheck
7649	*/
7650	DECLINLINE(VBOXSTRICTRC) PDMDevHlpDBGFReportBugCheck(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
7651	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4)
7652	{
7653	return pDevIns->pHlpR3->pfnDBGFReportBugCheck(pDevIns, enmEvent, uBugCheck, uP1, uP2, uP3, uP4);
7654	}
7655
7656	/**
7657	* @copydoc PDMDEVHLPR3::pfnDBGFCoreWrite
7658	*/
7659	DECLINLINE(int) PDMDevHlpDBGFCoreWrite(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile)
7660	{
7661	return pDevIns->pHlpR3->pfnDBGFCoreWrite(pDevIns, pszFilename, fReplaceFile);
7662	}
7663
7664	/**
7665	* @copydoc PDMDEVHLPR3::pfnDBGFInfoLogHlp
7666	*/
7667	DECLINLINE(PCDBGFINFOHLP) PDMDevHlpDBGFInfoLogHlp(PPDMDEVINS pDevIns)
7668	{
7669	return pDevIns->pHlpR3->pfnDBGFInfoLogHlp(pDevIns);
7670	}
7671
7672	/**
7673	* @copydoc PDMDEVHLPR3::pfnDBGFRegNmQueryU64
7674	*/
7675	DECLINLINE(int) PDMDevHlpDBGFRegNmQueryU64(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64)
7676	{
7677	return pDevIns->pHlpR3->pfnDBGFRegNmQueryU64(pDevIns, idDefCpu, pszReg, pu64);
7678	}
7679
7680	/**
7681	* Format a set of registers.
7682	*
7683	* This is restricted to registers from one CPU, that specified by @a idCpu.
7684	*
7685	* @returns VBox status code.
7686	* @param pDevIns The device instance.
7687	* @param idCpu The CPU ID of any CPU registers that may be
7688	* printed, pass VMCPUID_ANY if not applicable.
7689	* @param pszBuf The output buffer.
7690	* @param cbBuf The size of the output buffer.
7691	* @param pszFormat The format string. Register names are given by
7692	* %VR{name}, they take no arguments.
7693	* @param ... Argument list.
7694	*/
7695	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpDBGFRegPrintf(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
7696	const char *pszFormat, ...)
7697	{
7698	va_list Args;
7699	va_start(Args, pszFormat);
7700	int rc = pDevIns->pHlpR3->pfnDBGFRegPrintfV(pDevIns, idCpu, pszBuf, cbBuf, pszFormat, Args);
7701	va_end(Args);
7702	return rc;
7703	}
7704
7705	/**
7706	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
7707	*/
7708	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
7709	{
7710	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
7711	}
7712
7713	/**
7714	* Same as pfnSTAMRegister except that the name is specified in a
7715	* RTStrPrintf like fashion.
7716	*
7717	* @returns VBox status.
7718	* @param pDevIns Device instance of the DMA.
7719	* @param pvSample Pointer to the sample.
7720	* @param enmType Sample type. This indicates what pvSample is
7721	* pointing at.
7722	* @param enmVisibility Visibility type specifying whether unused
7723	* statistics should be visible or not.
7724	* @param enmUnit Sample unit.
7725	* @param pszDesc Sample description.
7726	* @param pszName Sample name format string, unix path style. If
7727	* this does not start with a '/', the default
7728	* prefix will be prepended, otherwise it will be
7729	* used as-is.
7730	* @param ... Arguments to the format string.
7731	*/
7732	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
7733	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
7734	const char pszDesc, const char pszName, ...)
7735	{
7736	va_list va;
7737	va_start(va, pszName);
7738	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
7739	va_end(va);
7740	}
7741
7742	/**
7743	* @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
7744	*/
7745	DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
7746	{
7747	return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
7748	}
7749
7750	/**
7751	* Registers the device with the default PCI bus.
7752	*
7753	* @returns VBox status code.
7754	* @param pDevIns The device instance.
7755	* @param pPciDev The PCI device structure.
7756	* This must be kept in the instance data.
7757	* The PCI configuration must be initialized before registration.
7758	*/
7759	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
7760	{
7761	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
7762	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
7763	}
7764
7765	/**
7766	* @copydoc PDMDEVHLPR3::pfnPCIRegister
7767	*/
7768	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
7769	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
7770	{
7771	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
7772	}
7773
7774	/**
7775	* Initialize MSI emulation support for the first PCI device.
7776	*
7777	* @returns VBox status code.
7778	* @param pDevIns The device instance.
7779	* @param pMsiReg MSI emulation registration structure.
7780	*/
7781	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
7782	{
7783	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
7784	}
7785
7786	/**
7787	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
7788	*/
7789	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
7790	{
7791	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
7792	}
7793
7794	/**
7795	* Registers a I/O port region for the default PCI device.
7796	*
7797	* @returns VBox status code.
7798	* @param pDevIns The device instance.
7799	* @param iRegion The region number.
7800	* @param cbRegion Size of the region.
7801	* @param hIoPorts Handle to the I/O port region.
7802	*/
7803	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
7804	{
7805	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7806	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
7807	}
7808
7809	/**
7810	* Registers a I/O port region for the default PCI device, custom map/unmap.
7811	*
7812	* @returns VBox status code.
7813	* @param pDevIns The device instance.
7814	* @param iRegion The region number.
7815	* @param cbRegion Size of the region.
7816	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7817	* callback will be invoked holding only the PDM lock.
7818	* The device lock will _not_ be taken (due to lock
7819	* order).
7820	*/
7821	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7822	PFNPCIIOREGIONMAP pfnMapUnmap)
7823	{
7824	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7825	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7826	UINT64_MAX, pfnMapUnmap);
7827	}
7828
7829	/**
7830	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7831	* and registering an I/O port region for the default PCI device.
7832	*
7833	* @returns VBox status code.
7834	* @param pDevIns The device instance to register the ports with.
7835	* @param cPorts The count of I/O ports in the region (the size).
7836	* @param iPciRegion The PCI device region.
7837	* @param pfnOut Pointer to function which is gonna handle OUT
7838	* operations. Optional.
7839	* @param pfnIn Pointer to function which is gonna handle IN operations.
7840	* Optional.
7841	* @param pvUser User argument to pass to the callbacks.
7842	* @param pszDesc Pointer to description string. This must not be freed.
7843	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7844	* coverage is allowed. This must not be freed.
7845	* @param phIoPorts Where to return the I/O port range handle.
7846	*
7847	*/
7848	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7849	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7850	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7851
7852	{
7853	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7854	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7855	if (RT_SUCCESS(rc))
7856	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7857	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7858	phIoPorts, NULL /pfnMapUnmap*/);
7859	return rc;
7860	}
7861
7862	/**
7863	* Registers an MMIO region for the default PCI device.
7864	*
7865	* @returns VBox status code.
7866	* @param pDevIns The device instance.
7867	* @param iRegion The region number.
7868	* @param cbRegion Size of the region.
7869	* @param enmType PCI_ADDRESS_SPACE_MEM or
7870	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7871	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7872	* @param hMmioRegion Handle to the MMIO region.
7873	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7874	* callback will be invoked holding only the PDM lock.
7875	* The device lock will _not_ be taken (due to lock
7876	* order).
7877	*/
7878	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7879	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7880	{
7881	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7882	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7883	hMmioRegion, pfnMapUnmap);
7884	}
7885
7886	/**
7887	* Registers an MMIO region for the default PCI device, extended version.
7888	*
7889	* @returns VBox status code.
7890	* @param pDevIns The device instance.
7891	* @param pPciDev The PCI device structure.
7892	* @param iRegion The region number.
7893	* @param cbRegion Size of the region.
7894	* @param enmType PCI_ADDRESS_SPACE_MEM or
7895	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7896	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7897	* @param hMmioRegion Handle to the MMIO region.
7898	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7899	* callback will be invoked holding only the PDM lock.
7900	* The device lock will _not_ be taken (due to lock
7901	* order).
7902	*/
7903	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7904	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7905	PFNPCIIOREGIONMAP pfnMapUnmap)
7906	{
7907	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7908	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7909	hMmioRegion, pfnMapUnmap);
7910	}
7911
7912	/**
7913	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7914	* and registering an MMIO region for the default PCI device.
7915	*
7916	* @returns VBox status code.
7917	* @param pDevIns The device instance to register the ports with.
7918	* @param cbRegion The size of the region in bytes.
7919	* @param iPciRegion The PCI device region.
7920	* @param enmType PCI_ADDRESS_SPACE_MEM or
7921	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7922	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7923	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7924	* @param pfnWrite Pointer to function which is gonna handle Write
7925	* operations.
7926	* @param pfnRead Pointer to function which is gonna handle Read
7927	* operations.
7928	* @param pvUser User argument to pass to the callbacks.
7929	* @param pszDesc Pointer to description string. This must not be freed.
7930	* @param phRegion Where to return the MMIO region handle.
7931	*
7932	*/
7933	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7934	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7935	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7936
7937	{
7938	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7939	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7940	if (RT_SUCCESS(rc))
7941	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7942	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7943	phRegion, NULL /pfnMapUnmap*/);
7944	return rc;
7945	}
7946
7947
7948	/**
7949	* Registers an MMIO2 region for the default PCI device.
7950	*
7951	* @returns VBox status code.
7952	* @param pDevIns The device instance.
7953	* @param iRegion The region number.
7954	* @param cbRegion Size of the region.
7955	* @param enmType PCI_ADDRESS_SPACE_MEM or
7956	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7957	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7958	* @param hMmio2Region Handle to the MMIO2 region.
7959	*/
7960	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7961	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7962	{
7963	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7964	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7965	hMmio2Region, NULL);
7966	}
7967
7968	/**
7969	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7970	* and registering an MMIO2 region for the default PCI device, extended edition.
7971	*
7972	* @returns VBox status code.
7973	* @param pDevIns The device instance to register the ports with.
7974	* @param cbRegion The size of the region in bytes.
7975	* @param iPciRegion The PCI device region.
7976	* @param enmType PCI_ADDRESS_SPACE_MEM or
7977	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7978	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7979	* @param pszDesc Pointer to description string. This must not be freed.
7980	* @param ppvMapping Where to store the address of the ring-3 mapping of
7981	* the memory.
7982	* @param phRegion Where to return the MMIO2 region handle.
7983	*
7984	*/
7985	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7986	PCIADDRESSSPACE enmType, const char *pszDesc,
7987	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7988
7989	{
7990	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7991	pszDesc, ppvMapping, phRegion);
7992	if (RT_SUCCESS(rc))
7993	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7994	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7995	phRegion, NULL /pfnCallback*/);
7996	return rc;
7997	}
7998
7999	/**
8000	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
8001	* and registering an MMIO2 region for the default PCI device.
8002	*
8003	* @returns VBox status code.
8004	* @param pDevIns The device instance to register the ports with.
8005	* @param cbRegion The size of the region in bytes.
8006	* @param iPciRegion The PCI device region.
8007	* @param enmType PCI_ADDRESS_SPACE_MEM or
8008	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
8009	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
8010	* @param fMmio2Flags PGMPHYS_MMIO2_FLAGS_XXX (see pgm.h).
8011	* @param pfnMapUnmap Callback for doing the mapping, optional. The
8012	* callback will be invoked holding only the PDM lock.
8013	* The device lock will _not_ be taken (due to lock
8014	* order).
8015	* @param pszDesc Pointer to description string. This must not be freed.
8016	* @param ppvMapping Where to store the address of the ring-3 mapping of
8017	* the memory.
8018	* @param phRegion Where to return the MMIO2 region handle.
8019	*
8020	*/
8021	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
8022	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
8023	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
8024
8025	{
8026	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
8027	pszDesc, ppvMapping, phRegion);
8028	if (RT_SUCCESS(rc))
8029	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
8030	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
8031	*phRegion, pfnMapUnmap);
8032	return rc;
8033	}
8034
8035	/**
8036	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
8037	*/
8038	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
8039	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
8040	{
8041	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
8042	}
8043
8044	/**
8045	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
8046	*/
8047	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
8048	unsigned cb, uint32_t *pu32Value)
8049	{
8050	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
8051	}
8052
8053	/**
8054	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
8055	*/
8056	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
8057	unsigned cb, uint32_t u32Value)
8058	{
8059	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
8060	}
8061
8062	#endif /* IN_RING3 */
8063
8064	/**
8065	* Bus master physical memory read from the default PCI device.
8066	*
8067	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8068	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8069	* @param pDevIns The device instance.
8070	* @param GCPhys Physical address start reading from.
8071	* @param pvBuf Where to put the read bits.
8072	* @param cbRead How many bytes to read.
8073	* @thread Any thread, but the call may involve the emulation thread.
8074	*/
8075	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8076	{
8077	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8078	}
8079
8080	/**
8081	* Bus master physical memory read - unknown data usage.
8082	*
8083	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8084	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8085	* @param pDevIns The device instance.
8086	* @param pPciDev The PCI device structure. If NULL the default
8087	* PCI device for this device instance is used.
8088	* @param GCPhys Physical address start reading from.
8089	* @param pvBuf Where to put the read bits.
8090	* @param cbRead How many bytes to read.
8091	* @thread Any thread, but the call may involve the emulation thread.
8092	*/
8093	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8094	{
8095	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8096	}
8097
8098	/**
8099	* Bus master physical memory read from the default PCI device.
8100	*
8101	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8102	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8103	* @param pDevIns The device instance.
8104	* @param GCPhys Physical address start reading from.
8105	* @param pvBuf Where to put the read bits.
8106	* @param cbRead How many bytes to read.
8107	* @thread Any thread, but the call may involve the emulation thread.
8108	*/
8109	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8110	{
8111	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8112	}
8113
8114	/**
8115	* Bus master physical memory read - reads meta data processed by the device.
8116	*
8117	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8118	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8119	* @param pDevIns The device instance.
8120	* @param pPciDev The PCI device structure. If NULL the default
8121	* PCI device for this device instance is used.
8122	* @param GCPhys Physical address start reading from.
8123	* @param pvBuf Where to put the read bits.
8124	* @param cbRead How many bytes to read.
8125	* @thread Any thread, but the call may involve the emulation thread.
8126	*/
8127	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8128	{
8129	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8130	}
8131
8132	/**
8133	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
8134	*
8135	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8136	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8137	* @param pDevIns The device instance.
8138	* @param GCPhys Physical address start reading from.
8139	* @param pvBuf Where to put the read bits.
8140	* @param cbRead How many bytes to read.
8141	* @thread Any thread, but the call may involve the emulation thread.
8142	*/
8143	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8144	{
8145	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8146	}
8147
8148	/**
8149	* Bus master physical memory read - read data will not be touched by the device.
8150	*
8151	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8152	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8153	* @param pDevIns The device instance.
8154	* @param pPciDev The PCI device structure. If NULL the default
8155	* PCI device for this device instance is used.
8156	* @param GCPhys Physical address start reading from.
8157	* @param pvBuf Where to put the read bits.
8158	* @param cbRead How many bytes to read.
8159	* @thread Any thread, but the call may involve the emulation thread.
8160	*/
8161	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8162	{
8163	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8164	}
8165
8166	/**
8167	* Bus master physical memory write from the default PCI device - unknown data usage.
8168	*
8169	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8170	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8171	* @param pDevIns The device instance.
8172	* @param GCPhys Physical address to write to.
8173	* @param pvBuf What to write.
8174	* @param cbWrite How many bytes to write.
8175	* @thread Any thread, but the call may involve the emulation thread.
8176	*/
8177	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8178	{
8179	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8180	}
8181
8182	/**
8183	* Bus master physical memory write - unknown data usage.
8184	*
8185	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8186	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8187	* @param pDevIns The device instance.
8188	* @param pPciDev The PCI device structure. If NULL the default
8189	* PCI device for this device instance is used.
8190	* @param GCPhys Physical address to write to.
8191	* @param pvBuf What to write.
8192	* @param cbWrite How many bytes to write.
8193	* @thread Any thread, but the call may involve the emulation thread.
8194	*/
8195	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8196	{
8197	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8198	}
8199
8200	/**
8201	* Bus master physical memory write from the default PCI device.
8202	*
8203	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8204	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8205	* @param pDevIns The device instance.
8206	* @param GCPhys Physical address to write to.
8207	* @param pvBuf What to write.
8208	* @param cbWrite How many bytes to write.
8209	* @thread Any thread, but the call may involve the emulation thread.
8210	*/
8211	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8212	{
8213	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8214	}
8215
8216	/**
8217	* Bus master physical memory write - written data was created/altered by the device.
8218	*
8219	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8220	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8221	* @param pDevIns The device instance.
8222	* @param pPciDev The PCI device structure. If NULL the default
8223	* PCI device for this device instance is used.
8224	* @param GCPhys Physical address to write to.
8225	* @param pvBuf What to write.
8226	* @param cbWrite How many bytes to write.
8227	* @thread Any thread, but the call may involve the emulation thread.
8228	*/
8229	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8230	{
8231	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8232	}
8233
8234	/**
8235	* Bus master physical memory write from the default PCI device.
8236	*
8237	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8238	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8239	* @param pDevIns The device instance.
8240	* @param GCPhys Physical address to write to.
8241	* @param pvBuf What to write.
8242	* @param cbWrite How many bytes to write.
8243	* @thread Any thread, but the call may involve the emulation thread.
8244	*/
8245	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8246	{
8247	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8248	}
8249
8250	/**
8251	* Bus master physical memory write - written data was not touched/created by the device.
8252	*
8253	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8254	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8255	* @param pDevIns The device instance.
8256	* @param pPciDev The PCI device structure. If NULL the default
8257	* PCI device for this device instance is used.
8258	* @param GCPhys Physical address to write to.
8259	* @param pvBuf What to write.
8260	* @param cbWrite How many bytes to write.
8261	* @thread Any thread, but the call may involve the emulation thread.
8262	*/
8263	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8264	{
8265	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8266	}
8267
8268	#ifdef IN_RING3
8269	/**
8270	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
8271	*/
8272	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8273	void **ppv, PPGMPAGEMAPLOCK pLock)
8274	{
8275	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8276	}
8277
8278	/**
8279	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
8280	*/
8281	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8282	void const **ppv, PPGMPAGEMAPLOCK pLock)
8283	{
8284	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8285	}
8286
8287	/**
8288	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
8289	*/
8290	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8291	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
8292	PPGMPAGEMAPLOCK paLocks)
8293	{
8294	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
8295	paLocks);
8296	}
8297
8298	/**
8299	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
8300	*/
8301	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8302	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
8303	PPGMPAGEMAPLOCK paLocks)
8304	{
8305	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
8306	papvPages, paLocks);
8307	}
8308	#endif /* IN_RING3 */
8309
8310	/**
8311	* Sets the IRQ for the default PCI device.
8312	*
8313	* @param pDevIns The device instance.
8314	* @param iIrq IRQ number to set.
8315	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
8316	* @thread Any thread, but will involve the emulation thread.
8317	*/
8318	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8319	{
8320	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8321	}
8322
8323	/**
8324	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
8325	*/
8326	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8327	{
8328	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8329	}
8330
8331	/**
8332	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
8333	* the request when not called from EMT.
8334	*
8335	* @param pDevIns The device instance.
8336	* @param iIrq IRQ number to set.
8337	* @param iLevel IRQ level.
8338	* @thread Any thread, but will involve the emulation thread.
8339	*/
8340	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8341	{
8342	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8343	}
8344
8345	/**
8346	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
8347	*/
8348	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8349	{
8350	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8351	}
8352
8353	/**
8354	* @copydoc PDMDEVHLPR3::pfnISASetIrq
8355	*/
8356	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8357	{
8358	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8359	}
8360
8361	/**
8362	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
8363	*/
8364	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8365	{
8366	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8367	}
8368
8369	#ifdef IN_RING3
8370
8371	/**
8372	* @copydoc PDMDEVHLPR3::pfnDriverAttach
8373	*/
8374	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
8375	{
8376	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
8377	}
8378
8379	/**
8380	* @copydoc PDMDEVHLPR3::pfnDriverDetach
8381	*/
8382	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
8383	{
8384	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
8385	}
8386
8387	/**
8388	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
8389	*/
8390	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
8391	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
8392	{
8393	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
8394	}
8395
8396	/**
8397	* Reconfigures with a single driver reattachement, no config, noflags.
8398	* @sa PDMDevHlpDriverReconfigure
8399	*/
8400	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
8401	{
8402	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
8403	}
8404
8405	/**
8406	* Reconfigures with a two drivers reattachement, no config, noflags.
8407	* @sa PDMDevHlpDriverReconfigure
8408	*/
8409	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
8410	{
8411	char const * apszDrivers[2];
8412	apszDrivers[0] = pszDriver0;
8413	apszDrivers[1] = pszDriver1;
8414	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
8415	}
8416
8417	/**
8418	* @copydoc PDMDEVHLPR3::pfnQueueCreate
8419	*/
8420	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
8421	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
8422	{
8423	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
8424	}
8425
8426	#endif /* IN_RING3 */
8427
8428	/**
8429	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
8430	*/
8431	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8432	{
8433	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
8434	}
8435
8436	/**
8437	* @copydoc PDMDEVHLPR3::pfnQueueInsert
8438	*/
8439	DECLINLINE(int) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
8440	{
8441	return pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
8442	}
8443
8444	/**
8445	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
8446	*/
8447	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8448	{
8449	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
8450	}
8451
8452	#ifdef IN_RING3
8453	/**
8454	* @copydoc PDMDEVHLPR3::pfnTaskCreate
8455	*/
8456	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
8457	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
8458	{
8459	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
8460	}
8461	#endif
8462
8463	/**
8464	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
8465	*/
8466	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
8467	{
8468	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
8469	}
8470
8471	#ifdef IN_RING3
8472
8473	/**
8474	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
8475	*/
8476	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
8477	{
8478	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
8479	}
8480
8481	/**
8482	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
8483	*/
8484	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8485	{
8486	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
8487	}
8488
8489	#endif /* IN_RING3 */
8490
8491	/**
8492	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
8493	*/
8494	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8495	{
8496	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
8497	}
8498
8499	/**
8500	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
8501	*/
8502	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
8503	{
8504	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
8505	}
8506
8507	/**
8508	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
8509	*/
8510	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
8511	{
8512	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
8513	}
8514
8515	/**
8516	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
8517	*/
8518	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
8519	{
8520	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
8521	}
8522
8523	/**
8524	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
8525	*/
8526	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
8527	{
8528	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
8529	}
8530
8531	#ifdef IN_RING3
8532
8533	/**
8534	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
8535	*/
8536	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
8537	{
8538	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
8539	}
8540
8541	/**
8542	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
8543	*/
8544	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8545	{
8546	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
8547	}
8548
8549	#endif /* IN_RING3 */
8550
8551	/**
8552	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
8553	*/
8554	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8555	{
8556	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
8557	}
8558
8559	/**
8560	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
8561	*/
8562	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8563	{
8564	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
8565	}
8566
8567	/**
8568	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
8569	*/
8570	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
8571	{
8572	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
8573	}
8574
8575	/**
8576	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
8577	*/
8578	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
8579	{
8580	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
8581	}
8582
8583	/**
8584	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
8585	*/
8586	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
8587	{
8588	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
8589	}
8590
8591	/**
8592	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
8593	*/
8594	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
8595	{
8596	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
8597	}
8598
8599	#ifdef IN_RING3
8600
8601	/**
8602	* Initializes a PDM critical section.
8603	*
8604	* The PDM critical sections are derived from the IPRT critical sections, but
8605	* works in RC and R0 as well.
8606	*
8607	* @returns VBox status code.
8608	* @param pDevIns The device instance.
8609	* @param pCritSect Pointer to the critical section.
8610	* @param SRC_POS Use RT_SRC_POS.
8611	* @param pszNameFmt Format string for naming the critical section.
8612	* For statistics and lock validation.
8613	* @param ... Arguments for the format string.
8614	*/
8615	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
8616	const char *pszNameFmt, ...)
8617	{
8618	int rc;
8619	va_list va;
8620	va_start(va, pszNameFmt);
8621	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8622	va_end(va);
8623	return rc;
8624	}
8625
8626	#endif /* IN_RING3 */
8627
8628	/**
8629	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
8630	*/
8631	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
8632	{
8633	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
8634	}
8635
8636	/**
8637	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
8638	*/
8639	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8640	{
8641	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
8642	}
8643
8644	/**
8645	* Enters a PDM critical section.
8646	*
8647	* @returns VINF_SUCCESS if entered successfully.
8648	* @returns rcBusy when encountering a busy critical section in RC/R0.
8649	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8650	* during the operation.
8651	*
8652	* @param pDevIns The device instance.
8653	* @param pCritSect The PDM critical section to enter.
8654	* @param rcBusy The status code to return when we're in RC or R0
8655	* and the section is busy. Pass VINF_SUCCESS to
8656	* acquired the critical section thru a ring-3
8657	* call if necessary.
8658	*
8659	* @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
8660	* possible failures in ring-0 or at least apply
8661	* PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
8662	* function.
8663	*
8664	* @sa PDMCritSectEnter
8665	*/
8666	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
8667	{
8668	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
8669	}
8670
8671	/**
8672	* Enters a PDM critical section, with location information for debugging.
8673	*
8674	* @returns VINF_SUCCESS if entered successfully.
8675	* @returns rcBusy when encountering a busy critical section in RC/R0.
8676	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8677	* during the operation.
8678	*
8679	* @param pDevIns The device instance.
8680	* @param pCritSect The PDM critical section to enter.
8681	* @param rcBusy The status code to return when we're in RC or R0
8682	* and the section is busy. Pass VINF_SUCCESS to
8683	* acquired the critical section thru a ring-3
8684	* call if necessary.
8685	* @param uId Some kind of locking location ID. Typically a
8686	* return address up the stack. Optional (0).
8687	* @param SRC_POS The source position where to lock is being
8688	* acquired from. Optional.
8689	* @sa PDMCritSectEnterDebug
8690	*/
8691	DECLINLINE(DECL_CHECK_RETURN(int))
8692	PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8693	{
8694	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8695	}
8696
8697	/**
8698	* Try enter a critical section.
8699	*
8700	* @retval VINF_SUCCESS on success.
8701	* @retval VERR_SEM_BUSY if the critsect was owned.
8702	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8703	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8704	* during the operation.
8705	*
8706	* @param pDevIns The device instance.
8707	* @param pCritSect The critical section.
8708	* @sa PDMCritSectTryEnter
8709	*/
8710	DECLINLINE(DECL_CHECK_RETURN(int))
8711	PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8712	{
8713	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
8714	}
8715
8716	/**
8717	* Try enter a critical section, with location information for debugging.
8718	*
8719	* @retval VINF_SUCCESS on success.
8720	* @retval VERR_SEM_BUSY if the critsect was owned.
8721	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8722	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8723	* during the operation.
8724	*
8725	* @param pDevIns The device instance.
8726	* @param pCritSect The critical section.
8727	* @param uId Some kind of locking location ID. Typically a
8728	* return address up the stack. Optional (0).
8729	* @param SRC_POS The source position where to lock is being
8730	* acquired from. Optional.
8731	* @sa PDMCritSectTryEnterDebug
8732	*/
8733	DECLINLINE(DECL_CHECK_RETURN(int))
8734	PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8735	{
8736	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8737	}
8738
8739	/**
8740	* Leaves a critical section entered with PDMCritSectEnter().
8741	*
8742	* @returns Indication whether we really exited the critical section.
8743	* @retval VINF_SUCCESS if we really exited.
8744	* @retval VINF_SEM_NESTED if we only reduced the nesting count.
8745	* @retval VERR_NOT_OWNER if you somehow ignore release assertions.
8746	*
8747	* @param pDevIns The device instance.
8748	* @param pCritSect The PDM critical section to leave.
8749	* @sa PDMCritSectLeave
8750	*/
8751	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8752	{
8753	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
8754	}
8755
8756	/**
8757	* @see PDMCritSectIsOwner
8758	*/
8759	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8760	{
8761	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
8762	}
8763
8764	/**
8765	* @see PDMCritSectIsInitialized
8766	*/
8767	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8768	{
8769	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
8770	}
8771
8772	/**
8773	* @see PDMCritSectHasWaiters
8774	*/
8775	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8776	{
8777	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
8778	}
8779
8780	/**
8781	* @see PDMCritSectGetRecursion
8782	*/
8783	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8784	{
8785	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
8786	}
8787
8788	#if defined(IN_RING3) \|\| defined(IN_RING0)
8789	/**
8790	* @see PDMHCCritSectScheduleExitEvent
8791	*/
8792	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
8793	{
8794	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
8795	}
8796	#endif
8797
8798	/* Strict build: Remap the two enter calls to the debug versions. */
8799	#ifdef VBOX_STRICT
8800	# ifdef IPRT_INCLUDED_asm_h
8801	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8802	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8803	# else
8804	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8805	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8806	# endif
8807	#endif
8808
8809	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8810
8811	/**
8812	* Deletes the critical section.
8813	*
8814	* @returns VBox status code.
8815	* @param pDevIns The device instance.
8816	* @param pCritSect The PDM critical section to destroy.
8817	* @sa PDMR3CritSectDelete
8818	*/
8819	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8820	{
8821	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8822	}
8823
8824	/**
8825	* Initializes a PDM read/write critical section.
8826	*
8827	* The PDM read/write critical sections are derived from the IPRT critical
8828	* sections, but works in RC and R0 as well.
8829	*
8830	* @returns VBox status code.
8831	* @param pDevIns The device instance.
8832	* @param pCritSect Pointer to the read/write critical section.
8833	* @param SRC_POS Use RT_SRC_POS.
8834	* @param pszNameFmt Format string for naming the critical section.
8835	* For statistics and lock validation.
8836	* @param ... Arguments for the format string.
8837	*/
8838	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
8839	const char *pszNameFmt, ...)
8840	{
8841	int rc;
8842	va_list va;
8843	va_start(va, pszNameFmt);
8844	rc = pDevIns->pHlpR3->pfnCritSectRwInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8845	va_end(va);
8846	return rc;
8847	}
8848
8849	/**
8850	* Deletes the read/write critical section.
8851	*
8852	* @returns VBox status code.
8853	* @param pDevIns The device instance.
8854	* @param pCritSect The PDM read/write critical section to destroy.
8855	* @sa PDMR3CritSectRwDelete
8856	*/
8857	DECLINLINE(int) PDMDevHlpCritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8858	{
8859	return pDevIns->pHlpR3->pfnCritSectRwDelete(pDevIns, pCritSect);
8860	}
8861
8862	#endif /* IN_RING3 */
8863
8864	/**
8865	* @sa PDMCritSectRwEnterShared, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8866	*/
8867	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8868	{
8869	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterShared(pDevIns, pCritSect, rcBusy);
8870	}
8871
8872	/**
8873	* @sa PDMCritSectRwEnterSharedDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8874	*/
8875	DECLINLINE(DECL_CHECK_RETURN(int))
8876	PDMDevHlpCritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8877	{
8878	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterSharedDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8879	}
8880
8881	/**
8882	* @sa PDMCritSectRwTryEnterShared
8883	*/
8884	DECLINLINE(DECL_CHECK_RETURN(int))
8885	PDMDevHlpCritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8886	{
8887	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterShared(pDevIns, pCritSect);
8888	}
8889
8890	/**
8891	* @sa PDMCritSectRwTryEnterSharedDebug
8892	*/
8893	DECLINLINE(DECL_CHECK_RETURN(int))
8894	PDMDevHlpCritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8895	{
8896	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterSharedDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8897	}
8898
8899	/**
8900	* @sa PDMCritSectRwLeaveShared
8901	*/
8902	DECLINLINE(int) PDMDevHlpCritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8903	{
8904	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveShared(pDevIns, pCritSect);
8905	}
8906
8907	/**
8908	* @sa PDMCritSectRwEnterExcl, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8909	*/
8910	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8911	{
8912	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy);
8913	}
8914
8915	/**
8916	* @sa PDMCritSectRwEnterExclDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8917	*/
8918	DECLINLINE(DECL_CHECK_RETURN(int))
8919	PDMDevHlpCritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8920	{
8921	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExclDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8922	}
8923
8924	/**
8925	* @sa PDMCritSectRwTryEnterExcl
8926	*/
8927	DECLINLINE(DECL_CHECK_RETURN(int))
8928	PDMDevHlpCritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8929	{
8930	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExcl(pDevIns, pCritSect);
8931	}
8932
8933	/**
8934	* @sa PDMCritSectRwTryEnterExclDebug
8935	*/
8936	DECLINLINE(DECL_CHECK_RETURN(int))
8937	PDMDevHlpCritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8938	{
8939	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExclDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8940	}
8941
8942	/**
8943	* @sa PDMCritSectRwLeaveExcl
8944	*/
8945	DECLINLINE(int) PDMDevHlpCritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8946	{
8947	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveExcl(pDevIns, pCritSect);
8948	}
8949
8950	/**
8951	* @see PDMCritSectRwIsWriteOwner
8952	*/
8953	DECLINLINE(bool) PDMDevHlpCritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8954	{
8955	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsWriteOwner(pDevIns, pCritSect);
8956	}
8957
8958	/**
8959	* @see PDMCritSectRwIsReadOwner
8960	*/
8961	DECLINLINE(bool) PDMDevHlpCritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
8962	{
8963	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsReadOwner(pDevIns, pCritSect, fWannaHear);
8964	}
8965
8966	/**
8967	* @see PDMCritSectRwGetWriteRecursion
8968	*/
8969	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8970	{
8971	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriteRecursion(pDevIns, pCritSect);
8972	}
8973
8974	/**
8975	* @see PDMCritSectRwGetWriterReadRecursion
8976	*/
8977	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8978	{
8979	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriterReadRecursion(pDevIns, pCritSect);
8980	}
8981
8982	/**
8983	* @see PDMCritSectRwGetReadCount
8984	*/
8985	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8986	{
8987	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetReadCount(pDevIns, pCritSect);
8988	}
8989
8990	/**
8991	* @see PDMCritSectRwIsInitialized
8992	*/
8993	DECLINLINE(bool) PDMDevHlpCritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8994	{
8995	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsInitialized(pDevIns, pCritSect);
8996	}
8997
8998	/* Strict build: Remap the two enter calls to the debug versions. */
8999	#ifdef VBOX_STRICT
9000	# ifdef IPRT_INCLUDED_asm_h
9001	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9002	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9003	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9004	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9005	# else
9006	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
9007	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
9008	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
9009	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
9010	# endif
9011	#endif
9012
9013	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
9014
9015	/**
9016	* @copydoc PDMDEVHLPR3::pfnThreadCreate
9017	*/
9018	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
9019	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
9020	{
9021	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
9022	}
9023
9024	/**
9025	* @copydoc PDMR3ThreadDestroy
9026	* @param pDevIns The device instance.
9027	*/
9028	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
9029	{
9030	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
9031	}
9032
9033	/**
9034	* @copydoc PDMR3ThreadIAmSuspending
9035	* @param pDevIns The device instance.
9036	*/
9037	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9038	{
9039	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
9040	}
9041
9042	/**
9043	* @copydoc PDMR3ThreadIAmRunning
9044	* @param pDevIns The device instance.
9045	*/
9046	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9047	{
9048	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
9049	}
9050
9051	/**
9052	* @copydoc PDMR3ThreadSleep
9053	* @param pDevIns The device instance.
9054	*/
9055	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
9056	{
9057	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
9058	}
9059
9060	/**
9061	* @copydoc PDMR3ThreadSuspend
9062	* @param pDevIns The device instance.
9063	*/
9064	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9065	{
9066	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
9067	}
9068
9069	/**
9070	* @copydoc PDMR3ThreadResume
9071	* @param pDevIns The device instance.
9072	*/
9073	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9074	{
9075	return pDevIns->pHlpR3->pfnThreadResume(pThread);
9076	}
9077
9078	/**
9079	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
9080	*/
9081	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
9082	{
9083	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
9084	}
9085
9086	/**
9087	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
9088	*/
9089	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
9090	{
9091	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
9092	}
9093
9094	/**
9095	* @copydoc PDMDEVHLPR3::pfnA20Set
9096	*/
9097	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
9098	{
9099	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
9100	}
9101
9102	/**
9103	* @copydoc PDMDEVHLPR3::pfnRTCRegister
9104	*/
9105	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
9106	{
9107	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
9108	}
9109
9110	/**
9111	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
9112	*/
9113	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
9114	{
9115	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
9116	}
9117
9118	/**
9119	* @copydoc PDMDEVHLPR3::pfnIommuRegister
9120	*/
9121	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
9122	{
9123	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
9124	}
9125
9126	/**
9127	* @copydoc PDMDEVHLPR3::pfnPICRegister
9128	*/
9129	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
9130	{
9131	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
9132	}
9133
9134	/**
9135	* @copydoc PDMDEVHLPR3::pfnApicRegister
9136	*/
9137	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
9138	{
9139	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
9140	}
9141
9142	/**
9143	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
9144	*/
9145	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9146	{
9147	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
9148	}
9149
9150	/**
9151	* @copydoc PDMDEVHLPR3::pfnHpetRegister
9152	*/
9153	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
9154	{
9155	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
9156	}
9157
9158	/**
9159	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
9160	*/
9161	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
9162	{
9163	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
9164	}
9165
9166	/**
9167	* @copydoc PDMDEVHLPR3::pfnDMACRegister
9168	*/
9169	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
9170	{
9171	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
9172	}
9173
9174	/**
9175	* @copydoc PDMDEVHLPR3::pfnDMARegister
9176	*/
9177	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
9178	{
9179	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
9180	}
9181
9182	/**
9183	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
9184	*/
9185	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
9186	{
9187	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
9188	}
9189
9190	/**
9191	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
9192	*/
9193	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
9194	{
9195	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
9196	}
9197
9198	/**
9199	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
9200	*/
9201	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
9202	{
9203	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
9204	}
9205
9206	/**
9207	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
9208	*/
9209	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
9210	{
9211	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
9212	}
9213
9214	/**
9215	* @copydoc PDMDEVHLPR3::pfnDMASchedule
9216	*/
9217	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
9218	{
9219	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
9220	}
9221
9222	/**
9223	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
9224	*/
9225	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
9226	{
9227	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
9228	}
9229
9230	/**
9231	* @copydoc PDMDEVHLPR3::pfnCMOSRead
9232	*/
9233	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
9234	{
9235	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
9236	}
9237
9238	/**
9239	* @copydoc PDMDEVHLPR3::pfnCallR0
9240	*/
9241	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
9242	{
9243	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
9244	}
9245
9246	/**
9247	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
9248	*/
9249	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
9250	{
9251	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
9252	}
9253
9254	/**
9255	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
9256	*/
9257	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
9258	{
9259	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
9260	}
9261
9262	/**
9263	* @copydoc PDMDEVHLPR3::pfnGetUVM
9264	*/
9265	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
9266	{
9267	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
9268	}
9269
9270	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
9271
9272	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
9273
9274	/**
9275	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
9276	*/
9277	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
9278	{
9279	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
9280	}
9281
9282	/**
9283	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
9284	*/
9285	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
9286	{
9287	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
9288	}
9289
9290	/**
9291	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
9292	*/
9293	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
9294	{
9295	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
9296	}
9297
9298	/**
9299	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
9300	*/
9301	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
9302	{
9303	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
9304	}
9305
9306	/**
9307	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
9308	*/
9309	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9310	{
9311	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
9312	}
9313
9314	/**
9315	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
9316	*/
9317	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
9318	{
9319	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
9320	}
9321
9322	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
9323
9324	/**
9325	* @copydoc PDMDEVHLPR3::pfnGetVM
9326	*/
9327	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
9328	{
9329	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
9330	}
9331
9332	/**
9333	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
9334	*/
9335	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
9336	{
9337	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
9338	}
9339
9340	/**
9341	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
9342	*/
9343	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
9344	{
9345	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
9346	}
9347
9348	/**
9349	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
9350	*/
9351	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
9352	{
9353	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
9354	}
9355
9356	/**
9357	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9358	*/
9359	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
9360	{
9361	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
9362	}
9363
9364	/**
9365	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9366	*/
9367	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
9368	{
9369	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
9370	}
9371
9372	#ifdef IN_RING3
9373	/**
9374	* @copydoc PDMDEVHLPR3::pfnTMCpuTicksPerSecond
9375	*/
9376	DECLINLINE(uint64_t) PDMDevHlpTMCpuTicksPerSecond(PPDMDEVINS pDevIns)
9377	{
9378	return pDevIns->CTX_SUFF(pHlp)->pfnTMCpuTicksPerSecond(pDevIns);
9379	}
9380
9381	/**
9382	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
9383	*/
9384	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
9385	{
9386	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
9387	}
9388
9389	/**
9390	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
9391	*/
9392	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
9393	{
9394	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
9395	}
9396
9397	/**
9398	* @copydoc PDMDEVHLPR3::pfnVMReset
9399	*/
9400	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
9401	{
9402	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
9403	}
9404
9405	/**
9406	* @copydoc PDMDEVHLPR3::pfnVMSuspend
9407	*/
9408	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
9409	{
9410	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
9411	}
9412
9413	/**
9414	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
9415	*/
9416	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
9417	{
9418	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
9419	}
9420
9421	/**
9422	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
9423	*/
9424	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
9425	{
9426	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
9427	}
9428
9429	#endif /* IN_RING3 */
9430
9431	/**
9432	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
9433	*/
9434	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
9435	{
9436	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
9437	}
9438
9439	#ifdef IN_RING3
9440	/**
9441	* @copydoc PDMDEVHLPR3::pfnGetCpuId
9442	*/
9443	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
9444	{
9445	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
9446	}
9447	#endif
9448
9449	/**
9450	* @copydoc PDMDEVHLPR3::pfnGetMainExecutionEngine
9451	*/
9452	DECLINLINE(uint8_t) PDMDevHlpGetMainExecutionEngine(PPDMDEVINS pDevIns)
9453	{
9454	return pDevIns->CTX_SUFF(pHlp)->pfnGetMainExecutionEngine(pDevIns);
9455	}
9456
9457	#ifdef IN_RING3
9458
9459	/**
9460	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
9461	*/
9462	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
9463	{
9464	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
9465	}
9466
9467	/**
9468	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
9469	*/
9470	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
9471	{
9472	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
9473	}
9474
9475	/**
9476	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
9477	*/
9478	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
9479	PFNPGMPHYSHANDLER pfnHandler, const char *pszDesc,
9480	PPGMPHYSHANDLERTYPE phType)
9481	{
9482	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandler, pszDesc, phType);
9483	}
9484
9485	#elif defined(IN_RING0)
9486
9487	/**
9488	* @copydoc PDMDEVHLPR0::pfnPGMHandlerPhysicalTypeSetUpContext
9489	*/
9490	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeSetUpContext(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
9491	PFNPGMPHYSHANDLER pfnHandler, PFNPGMRZPHYSPFHANDLER pfnPfHandler,
9492	const char *pszDesc, PGMPHYSHANDLERTYPE hType)
9493	{
9494	return pDevIns->pHlpR0->pfnPGMHandlerPhysicalTypeSetUpContext(pDevIns, enmKind, pfnHandler, pfnPfHandler, pszDesc, hType);
9495	}
9496
9497	#endif
9498	#ifdef IN_RING3
9499
9500	/**
9501	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalRegister
9502	*/
9503	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
9504	PGMPHYSHANDLERTYPE hType, R3PTRTYPE(const char *) pszDesc)
9505	{
9506	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalRegister(pDevIns, GCPhys, GCPhysLast, hType, pszDesc);
9507	}
9508
9509	/**
9510	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalDeregister
9511	*/
9512	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalDeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9513	{
9514	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalDeregister(pDevIns, GCPhys);
9515	}
9516
9517	#endif /* IN_RING3 */
9518
9519	/**
9520	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalPageTempOff
9521	*/
9522	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
9523	{
9524	return pDevIns->CTX_SUFF(pHlp)->pfnPGMHandlerPhysicalPageTempOff(pDevIns, GCPhys, GCPhysPage);
9525	}
9526
9527	#ifdef IN_RING3
9528
9529	/**
9530	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalReset
9531	*/
9532	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalReset(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9533	{
9534	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalReset(pDevIns, GCPhys);
9535	}
9536
9537	/**
9538	* @copydoc PDMDEVHLPR3::pfnVMMRegisterPatchMemory
9539	*/
9540	DECLINLINE(int) PDMDevHlpVMMRegisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9541	{
9542	return pDevIns->pHlpR3->pfnVMMRegisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9543	}
9544
9545	/**
9546	* @copydoc PDMDEVHLPR3::pfnVMMDeregisterPatchMemory
9547	*/
9548	DECLINLINE(int) PDMDevHlpVMMDeregisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9549	{
9550	return pDevIns->pHlpR3->pfnVMMDeregisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9551	}
9552
9553	/**
9554	* @copydoc PDMDEVHLPR3::pfnSharedModuleRegister
9555	*/
9556	DECLINLINE(int) PDMDevHlpSharedModuleRegister(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
9557	RTGCPTR GCBaseAddr, uint32_t cbModule,
9558	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions)
9559	{
9560	return pDevIns->pHlpR3->pfnSharedModuleRegister(pDevIns, enmGuestOS, pszModuleName, pszVersion,
9561	GCBaseAddr, cbModule, cRegions, paRegions);
9562	}
9563
9564	/**
9565	* @copydoc PDMDEVHLPR3::pfnSharedModuleUnregister
9566	*/
9567	DECLINLINE(int) PDMDevHlpSharedModuleUnregister(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
9568	RTGCPTR GCBaseAddr, uint32_t cbModule)
9569	{
9570	return pDevIns->pHlpR3->pfnSharedModuleUnregister(pDevIns, pszModuleName, pszVersion, GCBaseAddr, cbModule);
9571	}
9572
9573	/**
9574	* @copydoc PDMDEVHLPR3::pfnSharedModuleGetPageState
9575	*/
9576	DECLINLINE(int) PDMDevHlpSharedModuleGetPageState(PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool *pfShared,
9577	uint64_t *pfPageFlags)
9578	{
9579	return pDevIns->pHlpR3->pfnSharedModuleGetPageState(pDevIns, GCPtrPage, pfShared, pfPageFlags);
9580	}
9581
9582	/**
9583	* @copydoc PDMDEVHLPR3::pfnSharedModuleCheckAll
9584	*/
9585	DECLINLINE(int) PDMDevHlpSharedModuleCheckAll(PPDMDEVINS pDevIns)
9586	{
9587	return pDevIns->pHlpR3->pfnSharedModuleCheckAll(pDevIns);
9588	}
9589
9590	/**
9591	* @copydoc PDMDEVHLPR3::pfnQueryLun
9592	*/
9593	DECLINLINE(int) PDMDevHlpQueryLun(PPDMDEVINS pDevIns, const char pszDevice, unsigned iInstance, unsigned iLun, PPDMIBASE ppBase)
9594	{
9595	return pDevIns->pHlpR3->pfnQueryLun(pDevIns, pszDevice, iInstance, iLun, ppBase);
9596	}
9597
9598	/**
9599	* @copydoc PDMDEVHLPR3::pfnGIMDeviceRegister
9600	*/
9601	DECLINLINE(void) PDMDevHlpGIMDeviceRegister(PPDMDEVINS pDevIns, PGIMDEBUG pDbg)
9602	{
9603	pDevIns->pHlpR3->pfnGIMDeviceRegister(pDevIns, pDbg);
9604	}
9605
9606	/**
9607	* @copydoc PDMDEVHLPR3::pfnGIMGetDebugSetup
9608	*/
9609	DECLINLINE(int) PDMDevHlpGIMGetDebugSetup(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup)
9610	{
9611	return pDevIns->pHlpR3->pfnGIMGetDebugSetup(pDevIns, pDbgSetup);
9612	}
9613
9614	#endif /* IN_RING3 */
9615
9616	/**
9617	* @copydoc PDMDEVHLPR3::pfnGIMGetMmio2Regions
9618	*/
9619	DECLINLINE(PGIMMMIO2REGION) PDMDevHlpGIMGetMmio2Regions(PPDMDEVINS pDevIns, uint32_t *pcRegions)
9620	{
9621	return pDevIns->CTX_SUFF(pHlp)->pfnGIMGetMmio2Regions(pDevIns, pcRegions);
9622	}
9623
9624	#ifdef IN_RING3
9625
9626	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
9627	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9628	do { \
9629	uint32_t u32GetEnumTmp = 0; \
9630	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
9631	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9632	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
9633	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
9634	} while (0)
9635
9636	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
9637	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9638	do { \
9639	uint8_t bGetEnumTmp = 0; \
9640	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
9641	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9642	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
9643	} while (0)
9644
9645	#endif /* IN_RING3 */
9646
9647	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
9648	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
9649
9650	/**
9651	* Callbacks for VBoxDeviceRegister().
9652	*/
9653	typedef struct PDMDEVREGCB
9654	{
9655	/** Interface version.
9656	* This is set to PDM_DEVREG_CB_VERSION. */
9657	uint32_t u32Version;
9658
9659	/**
9660	* Registers a device with the current VM instance.
9661	*
9662	* @returns VBox status code.
9663	* @param pCallbacks Pointer to the callback table.
9664	* @param pReg Pointer to the device registration record.
9665	* This data must be permanent and readonly.
9666	*/
9667	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
9668	} PDMDEVREGCB;
9669
9670	/** Current version of the PDMDEVREGCB structure. */
9671	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
9672
9673
9674	/**
9675	* The VBoxDevicesRegister callback function.
9676	*
9677	* PDM will invoke this function after loading a device module and letting
9678	* the module decide which devices to register and how to handle conflicts.
9679	*
9680	* @returns VBox status code.
9681	* @param pCallbacks Pointer to the callback table.
9682	* @param u32Version VBox version number.
9683	*/
9684	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
9685
9686	/** @} */
9687
9688	RT_C_DECLS_END
9689
9690	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 98103

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