pdmdev.h@ 99745

Last change on this file since 99745 was 99745, checked in by vboxsync, 19 months ago
VMM: Add full support for reading/writing I/O ports on ARMv8 in order to emulate PIO accesses to PCI devices through a dedicated MMIO region by the host to PCI bridge, bugref:10445 [doxygen]
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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
37	#define VBOX_INCLUDED_vmm_pdmdev_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmcritsectrw.h>
44	#include <VBox/vmm/pdmqueue.h>
45	#include <VBox/vmm/pdmtask.h>
46	#ifdef IN_RING3
47	# include <VBox/vmm/pdmthread.h>
48	#endif
49	#include <VBox/vmm/pdmifs.h>
50	#include <VBox/vmm/pdmins.h>
51	#include <VBox/vmm/pdmcommon.h>
52	#include <VBox/vmm/pdmpcidev.h>
53	#include <VBox/vmm/iom.h>
54	#include <VBox/vmm/mm.h>
55	#include <VBox/vmm/tm.h>
56	#include <VBox/vmm/ssm.h>
57	#include <VBox/vmm/cfgm.h>
58	#include <VBox/vmm/cpum.h>
59	#include <VBox/vmm/dbgf.h>
60	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
61	#include <VBox/vmm/gim.h>
62	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
63	#include <VBox/msi.h>
64	#include <iprt/stdarg.h>
65	#include <iprt/list.h>
66
67
68	RT_C_DECLS_BEGIN
69
70	/** @defgroup grp_pdm_device The PDM Devices API
71	* @ingroup grp_pdm
72	* @{
73	*/
74
75	/**
76	* Construct a device instance for a VM.
77	*
78	* @returns VBox status.
79	* @param pDevIns The device instance data. If the registration structure
80	* is needed, it can be accessed thru pDevIns->pReg.
81	* @param iInstance Instance number. Use this to figure out which registers
82	* and such to use. The instance number is also found in
83	* pDevIns->iInstance, but since it's likely to be
84	* frequently used PDM passes it as parameter.
85	* @param pCfg Configuration node handle for the driver. This is
86	* expected to be in high demand in the constructor and is
87	* therefore passed as an argument. When using it at other
88	* times, it can be found in pDevIns->pCfg.
89	*/
90	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
91	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
92	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
93
94	/**
95	* Destruct a device instance.
96	*
97	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
98	* resources can be freed correctly.
99	*
100	* @returns VBox status.
101	* @param pDevIns The device instance data.
102	*
103	* @remarks The device critical section is not entered. The routine may delete
104	* the critical section, so the caller cannot exit it.
105	*/
106	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
107	/** Pointer to a FNPDMDEVDESTRUCT() function. */
108	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
109
110	/**
111	* Device relocation callback.
112	*
113	* This is called when the instance data has been relocated in raw-mode context
114	* (RC). It is also called when the RC hypervisor selects changes. The device
115	* must fixup all necessary pointers and re-query all interfaces to other RC
116	* devices and drivers.
117	*
118	* Before the RC code is executed the first time, this function will be called
119	* with a 0 delta so RC pointer calculations can be one in one place.
120	*
121	* @param pDevIns Pointer to the device instance.
122	* @param offDelta The relocation delta relative to the old location.
123	*
124	* @remarks A relocation CANNOT fail.
125	*
126	* @remarks The device critical section is not entered. The relocations should
127	* not normally require any locking.
128	*/
129	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
130	/** Pointer to a FNPDMDEVRELOCATE() function. */
131	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
132
133	/**
134	* Power On notification.
135	*
136	* @param pDevIns The device instance data.
137	*
138	* @remarks Caller enters the device critical section.
139	*/
140	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
141	/** Pointer to a FNPDMDEVPOWERON() function. */
142	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
143
144	/**
145	* Reset notification.
146	*
147	* @param pDevIns The device instance data.
148	*
149	* @remarks Caller enters the device critical section.
150	*/
151	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
152	/** Pointer to a FNPDMDEVRESET() function. */
153	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
154
155	/**
156	* Soft reset notification.
157	*
158	* This is mainly for emulating the 286 style protected mode exits, in which
159	* most devices should remain in their current state.
160	*
161	* @param pDevIns The device instance data.
162	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
163	*
164	* @remarks Caller enters the device critical section.
165	*/
166	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
167	/** Pointer to a FNPDMDEVSOFTRESET() function. */
168	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
169
170	/** @name PDMVMRESET_F_XXX - VM reset flags.
171	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
172	* reset via PDMDevHlpVMReset.
173	* @{ */
174	/** Unknown reason. */
175	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
176	/** GIM triggered reset. */
177	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
178	/** The last source always causing hard resets. */
179	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
180	/** ACPI triggered reset. */
181	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
182	/** PS/2 system port A (92h) reset. */
183	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
184	/** Keyboard reset. */
185	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
186	/** Tripple fault. */
187	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
188	/** Reset source mask. */
189	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
190	/** @} */
191
192	/**
193	* Suspend notification.
194	*
195	* @param pDevIns The device instance data.
196	* @thread EMT(0)
197	*
198	* @remarks Caller enters the device critical section.
199	*/
200	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
201	/** Pointer to a FNPDMDEVSUSPEND() function. */
202	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
203
204	/**
205	* Resume notification.
206	*
207	* @param pDevIns The device instance data.
208	*
209	* @remarks Caller enters the device critical section.
210	*/
211	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
212	/** Pointer to a FNPDMDEVRESUME() function. */
213	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
214
215	/**
216	* Power Off notification.
217	*
218	* This is always called when VMR3PowerOff is called.
219	* There will be no callback when hot plugging devices.
220	*
221	* @param pDevIns The device instance data.
222	* @thread EMT(0)
223	*
224	* @remarks Caller enters the device critical section.
225	*/
226	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
227	/** Pointer to a FNPDMDEVPOWEROFF() function. */
228	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
229
230	/**
231	* Attach command.
232	*
233	* This is called to let the device attach to a driver for a specified LUN
234	* at runtime. This is not called during VM construction, the device
235	* constructor has to attach to all the available drivers.
236	*
237	* This is like plugging in the keyboard or mouse after turning on the PC.
238	*
239	* @returns VBox status code.
240	* @param pDevIns The device instance.
241	* @param iLUN The logical unit which is being attached.
242	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
243	*
244	* @remarks Caller enters the device critical section.
245	*/
246	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
247	/** Pointer to a FNPDMDEVATTACH() function. */
248	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
249
250	/**
251	* Detach notification.
252	*
253	* This is called when a driver is detaching itself from a LUN of the device.
254	* The device should adjust its state to reflect this.
255	*
256	* This is like unplugging the network cable to use it for the laptop or
257	* something while the PC is still running.
258	*
259	* @param pDevIns The device instance.
260	* @param iLUN The logical unit which is being detached.
261	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
262	*
263	* @remarks Caller enters the device critical section.
264	*/
265	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
266	/** Pointer to a FNPDMDEVDETACH() function. */
267	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
268
269	/**
270	* Query the base interface of a logical unit.
271	*
272	* @returns VBOX status code.
273	* @param pDevIns The device instance.
274	* @param iLUN The logicial unit to query.
275	* @param ppBase Where to store the pointer to the base interface of the LUN.
276	*
277	* @remarks The device critical section is not entered.
278	*/
279	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
280	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
281	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
282
283	/**
284	* Init complete notification (after ring-0 & RC init since 5.1).
285	*
286	* This can be done to do communication with other devices and other
287	* initialization which requires everything to be in place.
288	*
289	* @returns VBOX status code.
290	* @param pDevIns The device instance.
291	*
292	* @remarks Caller enters the device critical section.
293	*/
294	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
295	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
296	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
297
298
299	/**
300	* The context of a pfnMemSetup call.
301	*/
302	typedef enum PDMDEVMEMSETUPCTX
303	{
304	/** Invalid zero value. */
305	PDMDEVMEMSETUPCTX_INVALID = 0,
306	/** After construction. */
307	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
308	/** After reset. */
309	PDMDEVMEMSETUPCTX_AFTER_RESET,
310	/** Type size hack. */
311	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
312	} PDMDEVMEMSETUPCTX;
313
314
315	/**
316	* PDM Device Registration Structure.
317	*
318	* This structure is used when registering a device from VBoxInitDevices() in HC
319	* Ring-3. PDM will continue use till the VM is terminated.
320	*
321	* @note The first part is the same in every context.
322	*/
323	typedef struct PDMDEVREGR3
324	{
325	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
326	uint32_t u32Version;
327	/** Reserved, must be zero. */
328	uint32_t uReserved0;
329	/** Device name, must match the ring-3 one. */
330	char szName[32];
331	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
332	uint32_t fFlags;
333	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
334	uint32_t fClass;
335	/** Maximum number of instances (per VM). */
336	uint32_t cMaxInstances;
337	/** The shared data structure version number. */
338	uint32_t uSharedVersion;
339	/** Size of the instance data. */
340	uint32_t cbInstanceShared;
341	/** Size of the ring-0 instance data. */
342	uint32_t cbInstanceCC;
343	/** Size of the raw-mode instance data. */
344	uint32_t cbInstanceRC;
345	/** Max number of PCI devices. */
346	uint16_t cMaxPciDevices;
347	/** Max number of MSI-X vectors in any of the PCI devices. */
348	uint16_t cMaxMsixVectors;
349	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
350	* remain unchanged from registration till VM destruction. */
351	const char *pszDescription;
352
353	/** Name of the raw-mode context module (no path).
354	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
355	const char *pszRCMod;
356	/** Name of the ring-0 module (no path).
357	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
358	const char *pszR0Mod;
359
360	/** Construct instance - required. */
361	PFNPDMDEVCONSTRUCT pfnConstruct;
362	/** Destruct instance - optional.
363	* Critical section NOT entered (will be destroyed). */
364	PFNPDMDEVDESTRUCT pfnDestruct;
365	/** Relocation command - optional.
366	* Critical section NOT entered. */
367	PFNPDMDEVRELOCATE pfnRelocate;
368	/**
369	* Memory setup callback.
370	*
371	* @param pDevIns The device instance data.
372	* @param enmCtx Indicates the context of the call.
373	* @remarks The critical section is entered prior to calling this method.
374	*/
375	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
376	/** Power on notification - optional.
377	* Critical section is entered. */
378	PFNPDMDEVPOWERON pfnPowerOn;
379	/** Reset notification - optional.
380	* Critical section is entered. */
381	PFNPDMDEVRESET pfnReset;
382	/** Suspend notification - optional.
383	* Critical section is entered. */
384	PFNPDMDEVSUSPEND pfnSuspend;
385	/** Resume notification - optional.
386	* Critical section is entered. */
387	PFNPDMDEVRESUME pfnResume;
388	/** Attach command - optional.
389	* Critical section is entered. */
390	PFNPDMDEVATTACH pfnAttach;
391	/** Detach notification - optional.
392	* Critical section is entered. */
393	PFNPDMDEVDETACH pfnDetach;
394	/** Query a LUN base interface - optional.
395	* Critical section is NOT entered. */
396	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
397	/** Init complete notification - optional.
398	* Critical section is entered. */
399	PFNPDMDEVINITCOMPLETE pfnInitComplete;
400	/** Power off notification - optional.
401	* Critical section is entered. */
402	PFNPDMDEVPOWEROFF pfnPowerOff;
403	/** Software system reset notification - optional.
404	* Critical section is entered. */
405	PFNPDMDEVSOFTRESET pfnSoftReset;
406
407	/** @name Reserved for future extensions, must be zero.
408	* @{ */
409	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
410	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
411	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
412	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
413	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
414	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
415	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
416	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
417	/** @} */
418
419	/** Initialization safty marker. */
420	uint32_t u32VersionEnd;
421	} PDMDEVREGR3;
422	/** Pointer to a PDM Device Structure. */
423	typedef PDMDEVREGR3 *PPDMDEVREGR3;
424	/** Const pointer to a PDM Device Structure. */
425	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
426	/** Current DEVREGR3 version number. */
427	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
428
429
430	/** PDM Device Flags.
431	* @{ */
432	/** This flag is used to indicate that the device has a R0 component. */
433	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
434	/** Requires the ring-0 component, ignore configuration values. */
435	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
436	/** Requires the ring-0 component, ignore configuration values. */
437	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
438
439	/** This flag is used to indicate that the device has a RC component. */
440	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
441	/** Requires the raw-mode component, ignore configuration values. */
442	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
443	/** Requires the raw-mode component, ignore configuration values. */
444	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
445
446	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
447	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
448
449	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
450	* The bit count for the current host.
451	* @note Superfluous, but still around for hysterical raisins. */
452	#if HC_ARCH_BITS == 32
453	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
454	#elif HC_ARCH_BITS == 64
455	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
456	#else
457	# error Unsupported HC_ARCH_BITS value.
458	#endif
459	/** The host bit count mask. */
460	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
461
462	/** The device support only 32-bit guests. */
463	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
464	/** The device support only 64-bit guests. */
465	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
466	/** The device support both 32-bit & 64-bit guests. */
467	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
468	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
469	* The guest bit count for the current compilation. */
470	#if GC_ARCH_BITS == 32
471	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
472	#elif GC_ARCH_BITS == 64
473	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
474	#else
475	# error Unsupported GC_ARCH_BITS value.
476	#endif
477	/** The guest bit count mask. */
478	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
479
480	/** A convenience. */
481	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
482
483	/** Indicates that the device needs to be notified before the drivers when suspending. */
484	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
485	/** Indicates that the device needs to be notified before the drivers when powering off. */
486	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
487	/** Indicates that the device needs to be notified before the drivers when resetting. */
488	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
489
490	/** This flag is used to indicate that the device has been converted to the
491	* new device style. */
492	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
493
494	/** @} */
495
496
497	/** PDM Device Classes.
498	* The order is important, lower bit earlier instantiation.
499	* @{ */
500	/** Architecture device. */
501	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
502	/** Architecture BIOS device. */
503	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
504	/** PCI bus brigde. */
505	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
506	/** PCI built-in device (e.g. PCI root complex devices). */
507	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
508	/** Input device (mouse, keyboard, joystick, HID, ...). */
509	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
510	/** Interrupt controller (PIC). */
511	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
512	/** Interval controoler (PIT). */
513	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
514	/** RTC/CMOS. */
515	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
516	/** DMA controller. */
517	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
518	/** VMM Device. */
519	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
520	/** Graphics device, like VGA. */
521	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
522	/** Storage controller device. */
523	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
524	/** Network interface controller. */
525	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
526	/** Audio. */
527	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
528	/** USB HIC. */
529	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
530	/** ACPI. */
531	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
532	/** Serial controller device. */
533	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
534	/** Parallel controller device */
535	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
536	/** Host PCI pass-through device */
537	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
538	/** Misc devices (always last). */
539	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
540	/** @} */
541
542
543	/**
544	* PDM Device Registration Structure, ring-0.
545	*
546	* This structure is used when registering a device from VBoxInitDevices() in HC
547	* Ring-0. PDM will continue use till the VM is terminated.
548	*/
549	typedef struct PDMDEVREGR0
550	{
551	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
552	uint32_t u32Version;
553	/** Reserved, must be zero. */
554	uint32_t uReserved0;
555	/** Device name, must match the ring-3 one. */
556	char szName[32];
557	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
558	uint32_t fFlags;
559	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
560	uint32_t fClass;
561	/** Maximum number of instances (per VM). */
562	uint32_t cMaxInstances;
563	/** The shared data structure version number. */
564	uint32_t uSharedVersion;
565	/** Size of the instance data. */
566	uint32_t cbInstanceShared;
567	/** Size of the ring-0 instance data. */
568	uint32_t cbInstanceCC;
569	/** Size of the raw-mode instance data. */
570	uint32_t cbInstanceRC;
571	/** Max number of PCI devices. */
572	uint16_t cMaxPciDevices;
573	/** Max number of MSI-X vectors in any of the PCI devices. */
574	uint16_t cMaxMsixVectors;
575	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
576	* remain unchanged from registration till VM destruction. */
577	const char *pszDescription;
578
579	/**
580	* Early construction callback (optional).
581	*
582	* This is called right after the device instance structure has been allocated
583	* and before the ring-3 constructor gets called.
584	*
585	* @returns VBox status code.
586	* @param pDevIns The device instance data.
587	* @note The destructure is always called, regardless of the return status.
588	*/
589	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
590
591	/**
592	* Regular construction callback (optional).
593	*
594	* This is called after (or during) the ring-3 constructor.
595	*
596	* @returns VBox status code.
597	* @param pDevIns The device instance data.
598	* @note The destructure is always called, regardless of the return status.
599	*/
600	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
601
602	/**
603	* Destructor (optional).
604	*
605	* This is called after the ring-3 destruction. This is not called if ring-3
606	* fails to trigger it (e.g. process is killed or crashes).
607	*
608	* @param pDevIns The device instance data.
609	*/
610	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
611
612	/**
613	* Final destructor (optional).
614	*
615	* This is called right before the memory is freed, which happens when the
616	* VM/GVM object is destroyed. This is always called.
617	*
618	* @param pDevIns The device instance data.
619	*/
620	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
621
622	/**
623	* Generic request handler (optional).
624	*
625	* @param pDevIns The device instance data.
626	* @param uReq Device specific request.
627	* @param uArg Request argument.
628	*/
629	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
630
631	/** @name Reserved for future extensions, must be zero.
632	* @{ */
633	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
634	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
635	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
636	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
637	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
638	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
639	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
640	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
641	/** @} */
642
643	/** Initialization safty marker. */
644	uint32_t u32VersionEnd;
645	} PDMDEVREGR0;
646	/** Pointer to a ring-0 PDM device registration structure. */
647	typedef PDMDEVREGR0 *PPDMDEVREGR0;
648	/** Pointer to a const ring-0 PDM device registration structure. */
649	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
650	/** Current DEVREGR0 version number. */
651	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
652
653
654	/**
655	* PDM Device Registration Structure, raw-mode
656	*
657	* At the moment, this structure is mostly here to match the other two contexts.
658	*/
659	typedef struct PDMDEVREGRC
660	{
661	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
662	uint32_t u32Version;
663	/** Reserved, must be zero. */
664	uint32_t uReserved0;
665	/** Device name, must match the ring-3 one. */
666	char szName[32];
667	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
668	uint32_t fFlags;
669	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
670	uint32_t fClass;
671	/** Maximum number of instances (per VM). */
672	uint32_t cMaxInstances;
673	/** The shared data structure version number. */
674	uint32_t uSharedVersion;
675	/** Size of the instance data. */
676	uint32_t cbInstanceShared;
677	/** Size of the ring-0 instance data. */
678	uint32_t cbInstanceCC;
679	/** Size of the raw-mode instance data. */
680	uint32_t cbInstanceRC;
681	/** Max number of PCI devices. */
682	uint16_t cMaxPciDevices;
683	/** Max number of MSI-X vectors in any of the PCI devices. */
684	uint16_t cMaxMsixVectors;
685	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
686	* remain unchanged from registration till VM destruction. */
687	const char *pszDescription;
688
689	/**
690	* Constructor callback.
691	*
692	* This is called much later than both the ring-0 and ring-3 constructors, since
693	* raw-mode v2 require a working VMM to run actual code.
694	*
695	* @returns VBox status code.
696	* @param pDevIns The device instance data.
697	* @note The destructure is always called, regardless of the return status.
698	*/
699	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
700
701	/** @name Reserved for future extensions, must be zero.
702	* @{ */
703	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
704	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
705	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
706	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
707	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
708	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
709	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
710	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
711	/** @} */
712
713	/** Initialization safty marker. */
714	uint32_t u32VersionEnd;
715	} PDMDEVREGRC;
716	/** Pointer to a raw-mode PDM device registration structure. */
717	typedef PDMDEVREGRC *PPDMDEVREGRC;
718	/** Pointer to a const raw-mode PDM device registration structure. */
719	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
720	/** Current DEVREGRC version number. */
721	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
722
723
724
725	/** @def PDM_DEVREG_VERSION
726	* Current DEVREG version number. */
727	/** @typedef PDMDEVREGR3
728	* A current context PDM device registration structure. */
729	/** @typedef PPDMDEVREGR3
730	* Pointer to a current context PDM device registration structure. */
731	/** @typedef PCPDMDEVREGR3
732	* Pointer to a const current context PDM device registration structure. */
733	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
734	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
735	typedef PDMDEVREGR3 PDMDEVREG;
736	typedef PPDMDEVREGR3 PPDMDEVREG;
737	typedef PCPDMDEVREGR3 PCPDMDEVREG;
738	#elif defined(IN_RING0)
739	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
740	typedef PDMDEVREGR0 PDMDEVREG;
741	typedef PPDMDEVREGR0 PPDMDEVREG;
742	typedef PCPDMDEVREGR0 PCPDMDEVREG;
743	#elif defined(IN_RC)
744	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
745	typedef PDMDEVREGRC PDMDEVREG;
746	typedef PPDMDEVREGRC PPDMDEVREG;
747	typedef PCPDMDEVREGRC PCPDMDEVREG;
748	#else
749	# error "Not IN_RING3, IN_RING0 or IN_RC"
750	#endif
751
752
753	/**
754	* Device registrations for ring-0 modules.
755	*
756	* This structure is used directly and must therefore reside in persistent
757	* memory (i.e. the data section).
758	*/
759	typedef struct PDMDEVMODREGR0
760	{
761	/** The structure version (PDM_DEVMODREGR0_VERSION). */
762	uint32_t u32Version;
763	/** Number of devices in the array papDevRegs points to. */
764	uint32_t cDevRegs;
765	/** Pointer to device registration structures. */
766	PCPDMDEVREGR0 *papDevRegs;
767	/** The ring-0 module handle - PDM internal, fingers off. */
768	void *hMod;
769	/** List entry - PDM internal, fingers off. */
770	RTLISTNODE ListEntry;
771	} PDMDEVMODREGR0;
772	/** Pointer to device registriations for a ring-0 module. */
773	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
774	/** Current PDMDEVMODREGR0 version number. */
775	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
776
777
778	/** @name IRQ Level for use with the *SetIrq APIs.
779	* @{
780	*/
781	/** Assert the IRQ (can assume value 1). */
782	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
783	/** Deassert the IRQ (can assume value 0). */
784	#define PDM_IRQ_LEVEL_LOW 0
785	/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
786	* automatically deasserts it after delivery to the APIC (IOAPIC).
787	* @note Only suitable for edge trigger interrupts. */
788	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
789	/** @} */
790
791	/**
792	* Registration record for MSI/MSI-X emulation.
793	*/
794	typedef struct PDMMSIREG
795	{
796	/** Number of MSI interrupt vectors, 0 if MSI not supported */
797	uint16_t cMsiVectors;
798	/** Offset of MSI capability */
799	uint8_t iMsiCapOffset;
800	/** Offset of next capability to MSI */
801	uint8_t iMsiNextOffset;
802	/** If we support 64-bit MSI addressing */
803	bool fMsi64bit;
804	/** If we do not support per-vector masking */
805	bool fMsiNoMasking;
806
807	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
808	uint16_t cMsixVectors;
809	/** Offset of MSI-X capability */
810	uint8_t iMsixCapOffset;
811	/** Offset of next capability to MSI-X */
812	uint8_t iMsixNextOffset;
813	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
814	uint8_t iMsixBar;
815	} PDMMSIREG;
816	typedef PDMMSIREG *PPDMMSIREG;
817
818	/**
819	* PCI Bus registration structure.
820	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
821	*/
822	typedef struct PDMPCIBUSREGR3
823	{
824	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
825	uint32_t u32Version;
826
827	/**
828	* Registers the device with the default PCI bus.
829	*
830	* @returns VBox status code.
831	* @param pDevIns Device instance of the PCI Bus.
832	* @param pPciDev The PCI device structure.
833	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
834	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
835	* device number (0-31).
836	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
837	* function number (0-7).
838	* @param pszName Device name (static but not unique).
839	*
840	* @remarks Caller enters the PDM critical section.
841	*/
842	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
843	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
844
845	/**
846	* Initialize MSI or MSI-X emulation support in a PCI device.
847	*
848	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
849	* vast majority of device emulation it covers everything necessary. It's
850	* fully automatic, taking care of all BAR and config space requirements,
851	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
852	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
853	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
854	*
855	* A device not using this can still offer MSI/MSI-X. In this case it's
856	* completely up to the device (in the MSI-X case) to create/register the
857	* necessary MMIO BAR, handle all config space/BAR updating and take care
858	* of delivering the interrupts appropriately.
859	*
860	* @returns VBox status code.
861	* @param pDevIns Device instance of the PCI Bus.
862	* @param pPciDev The PCI device structure.
863	* @param pMsiReg MSI emulation registration structure
864	* @remarks Caller enters the PDM critical section.
865	*/
866	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
867
868	/**
869	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
870	*
871	* @returns VBox status code.
872	* @param pDevIns Device instance of the PCI Bus.
873	* @param pPciDev The PCI device structure.
874	* @param iRegion The region number.
875	* @param cbRegion Size of the region.
876	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
877	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
878	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
879	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
880	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
881	* @a fFlags, UINT64_MAX if no handle is passed
882	* (old style).
883	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
884	* is given.
885	* @remarks Caller enters the PDM critical section.
886	*/
887	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
888	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
889	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
890
891	/**
892	* Register PCI configuration space read/write intercept callbacks.
893	*
894	* @param pDevIns Device instance of the PCI Bus.
895	* @param pPciDev The PCI device structure.
896	* @param pfnRead Pointer to the user defined PCI config read function.
897	* @param pfnWrite Pointer to the user defined PCI config write function.
898	* to call default PCI config write function. Can be NULL.
899	* @remarks Caller enters the PDM critical section.
900	* @thread EMT
901	*/
902	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
903	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
904
905	/**
906	* Perform a PCI configuration space write, bypassing interception.
907	*
908	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
909	*
910	* @returns Strict VBox status code (mainly DBGFSTOP).
911	* @param pDevIns Device instance of the PCI Bus.
912	* @param pPciDev The PCI device which config space is being read.
913	* @param uAddress The config space address.
914	* @param cb The size of the read: 1, 2 or 4 bytes.
915	* @param u32Value The value to write.
916	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
917	* that the (root) bus will have done that already.
918	*/
919	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
920	uint32_t uAddress, unsigned cb, uint32_t u32Value));
921
922	/**
923	* Perform a PCI configuration space read, bypassing interception.
924	*
925	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
926	*
927	* @returns Strict VBox status code (mainly DBGFSTOP).
928	* @param pDevIns Device instance of the PCI Bus.
929	* @param pPciDev The PCI device which config space is being read.
930	* @param uAddress The config space address.
931	* @param cb The size of the read: 1, 2 or 4 bytes.
932	* @param pu32Value Where to return the value.
933	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
934	* that the (root) bus will have done that already.
935	*/
936	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
937	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
938
939	/**
940	* Set the IRQ for a PCI device.
941	*
942	* @param pDevIns Device instance of the PCI Bus.
943	* @param pPciDev The PCI device structure.
944	* @param iIrq IRQ number to set.
945	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
946	* @param uTagSrc The IRQ tag and source (for tracing).
947	* @remarks Caller enters the PDM critical section.
948	*/
949	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
950
951	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
952	uint32_t u32EndVersion;
953	} PDMPCIBUSREGR3;
954	/** Pointer to a PCI bus registration structure. */
955	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
956	/** Current PDMPCIBUSREGR3 version number. */
957	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
958
959	/**
960	* PCI Bus registration structure for ring-0.
961	*/
962	typedef struct PDMPCIBUSREGR0
963	{
964	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
965	uint32_t u32Version;
966	/** The PCI bus number (from ring-3 registration). */
967	uint32_t iBus;
968	/**
969	* Set the IRQ for a PCI device.
970	*
971	* @param pDevIns Device instance of the PCI Bus.
972	* @param pPciDev The PCI device structure.
973	* @param iIrq IRQ number to set.
974	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
975	* @param uTagSrc The IRQ tag and source (for tracing).
976	* @remarks Caller enters the PDM critical section.
977	*/
978	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
979	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
980	uint32_t u32EndVersion;
981	} PDMPCIBUSREGR0;
982	/** Pointer to a PCI bus ring-0 registration structure. */
983	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
984	/** Current PDMPCIBUSREGR0 version number. */
985	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
986
987	/**
988	* PCI Bus registration structure for raw-mode.
989	*/
990	typedef struct PDMPCIBUSREGRC
991	{
992	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
993	uint32_t u32Version;
994	/** The PCI bus number (from ring-3 registration). */
995	uint32_t iBus;
996	/**
997	* Set the IRQ for a PCI device.
998	*
999	* @param pDevIns Device instance of the PCI Bus.
1000	* @param pPciDev The PCI device structure.
1001	* @param iIrq IRQ number to set.
1002	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1003	* @param uTagSrc The IRQ tag and source (for tracing).
1004	* @remarks Caller enters the PDM critical section.
1005	*/
1006	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
1007	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1008	uint32_t u32EndVersion;
1009	} PDMPCIBUSREGRC;
1010	/** Pointer to a PCI bus raw-mode registration structure. */
1011	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1012	/** Current PDMPCIBUSREGRC version number. */
1013	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1014
1015	/** PCI bus registration structure for the current context. */
1016	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1017	/** Pointer to a PCI bus registration structure for the current context. */
1018	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1019	/** PCI bus registration structure version for the current context. */
1020	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1021
1022
1023	/**
1024	* PCI Bus RC helpers.
1025	*/
1026	typedef struct PDMPCIHLPRC
1027	{
1028	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1029	uint32_t u32Version;
1030
1031	/**
1032	* Set an ISA IRQ.
1033	*
1034	* @param pDevIns PCI device instance.
1035	* @param iIrq IRQ number to set.
1036	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1037	* @param uTagSrc The IRQ tag and source (for tracing).
1038	* @thread EMT only.
1039	*/
1040	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1041
1042	/**
1043	* Set an I/O-APIC IRQ.
1044	*
1045	* @param pDevIns PCI device instance.
1046	* @param uBusDevFn The bus:device:function of the device initiating the
1047	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1048	* interrupt.
1049	* @param iIrq IRQ number to set.
1050	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1051	* @param uTagSrc The IRQ tag and source (for tracing).
1052	* @thread EMT only.
1053	*/
1054	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1055
1056	/**
1057	* Send an MSI.
1058	*
1059	* @param pDevIns PCI device instance.
1060	* @param uBusDevFn The bus:device:function of the device initiating the
1061	* MSI. Cannot be NIL_PCIBDF.
1062	* @param pMsi The MSI to send.
1063	* @param uTagSrc The IRQ tag and source (for tracing).
1064	* @thread EMT only.
1065	*/
1066	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1067
1068
1069	/**
1070	* Acquires the PDM lock.
1071	*
1072	* @returns VINF_SUCCESS on success.
1073	* @returns rc if we failed to acquire the lock.
1074	* @param pDevIns The PCI device instance.
1075	* @param rc What to return if we fail to acquire the lock.
1076	*
1077	* @sa PDMCritSectEnter
1078	*/
1079	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1080
1081	/**
1082	* Releases the PDM lock.
1083	*
1084	* @param pDevIns The PCI device instance.
1085	*/
1086	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1087
1088	/**
1089	* Gets a bus by it's PDM ordinal (typically the parent bus).
1090	*
1091	* @returns Pointer to the device instance of the bus.
1092	* @param pDevIns The PCI bus device instance.
1093	* @param idxPdmBus The PDM ordinal value of the bus to get.
1094	*/
1095	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1096
1097	/** Just a safety precaution. */
1098	uint32_t u32TheEnd;
1099	} PDMPCIHLPRC;
1100	/** Pointer to PCI helpers. */
1101	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1102	/** Pointer to const PCI helpers. */
1103	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1104
1105	/** Current PDMPCIHLPRC version number. */
1106	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1107
1108
1109	/**
1110	* PCI Bus R0 helpers.
1111	*/
1112	typedef struct PDMPCIHLPR0
1113	{
1114	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1115	uint32_t u32Version;
1116
1117	/**
1118	* Set an ISA IRQ.
1119	*
1120	* @param pDevIns PCI device instance.
1121	* @param iIrq IRQ number to set.
1122	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1123	* @param uTagSrc The IRQ tag and source (for tracing).
1124	* @thread EMT only.
1125	*/
1126	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1127
1128	/**
1129	* Set an I/O-APIC IRQ.
1130	*
1131	* @param pDevIns PCI device instance.
1132	* @param uBusDevFn The bus:device:function of the device initiating the
1133	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1134	* interrupt.
1135	* @param iIrq IRQ number to set.
1136	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1137	* @param uTagSrc The IRQ tag and source (for tracing).
1138	* @thread EMT only.
1139	*/
1140	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1141
1142	/**
1143	* Send an MSI.
1144	*
1145	* @param pDevIns PCI device instance.
1146	* @param uBusDevFn The bus:device:function of the device initiating the
1147	* MSI. Cannot be NIL_PCIBDF.
1148	* @param pMsi The MSI to send.
1149	* @param uTagSrc The IRQ tag and source (for tracing).
1150	* @thread EMT only.
1151	*/
1152	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1153
1154	/**
1155	* Acquires the PDM lock.
1156	*
1157	* @returns VINF_SUCCESS on success.
1158	* @returns rc if we failed to acquire the lock.
1159	* @param pDevIns The PCI device instance.
1160	* @param rc What to return if we fail to acquire the lock.
1161	*
1162	* @sa PDMCritSectEnter
1163	*/
1164	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1165
1166	/**
1167	* Releases the PDM lock.
1168	*
1169	* @param pDevIns The PCI device instance.
1170	*/
1171	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1172
1173	/**
1174	* Gets a bus by it's PDM ordinal (typically the parent bus).
1175	*
1176	* @returns Pointer to the device instance of the bus.
1177	* @param pDevIns The PCI bus device instance.
1178	* @param idxPdmBus The PDM ordinal value of the bus to get.
1179	*/
1180	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1181
1182	/** Just a safety precaution. */
1183	uint32_t u32TheEnd;
1184	} PDMPCIHLPR0;
1185	/** Pointer to PCI helpers. */
1186	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1187	/** Pointer to const PCI helpers. */
1188	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1189
1190	/** Current PDMPCIHLPR0 version number. */
1191	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1192
1193	/**
1194	* PCI device helpers.
1195	*/
1196	typedef struct PDMPCIHLPR3
1197	{
1198	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1199	uint32_t u32Version;
1200
1201	/**
1202	* Set an ISA IRQ.
1203	*
1204	* @param pDevIns The PCI device instance.
1205	* @param iIrq IRQ number to set.
1206	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1207	* @param uTagSrc The IRQ tag and source (for tracing).
1208	*/
1209	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1210
1211	/**
1212	* Set an I/O-APIC IRQ.
1213	*
1214	* @param pDevIns The PCI device instance.
1215	* @param uBusDevFn The bus:device:function of the device initiating the
1216	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1217	* interrupt.
1218	* @param iIrq IRQ number to set.
1219	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1220	* @param uTagSrc The IRQ tag and source (for tracing).
1221	*/
1222	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1223
1224	/**
1225	* Send an MSI.
1226	*
1227	* @param pDevIns PCI device instance.
1228	* @param uBusDevFn The bus:device:function of the device initiating the
1229	* MSI. Cannot be NIL_PCIBDF.
1230	* @param pMsi The MSI to send.
1231	* @param uTagSrc The IRQ tag and source (for tracing).
1232	*/
1233	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1234
1235	/**
1236	* Acquires the PDM lock.
1237	*
1238	* @returns VINF_SUCCESS on success.
1239	* @returns Fatal error on failure.
1240	* @param pDevIns The PCI device instance.
1241	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1242	*
1243	* @sa PDMCritSectEnter
1244	*/
1245	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1246
1247	/**
1248	* Releases the PDM lock.
1249	*
1250	* @param pDevIns The PCI device instance.
1251	*/
1252	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1253
1254	/**
1255	* Gets a bus by it's PDM ordinal (typically the parent bus).
1256	*
1257	* @returns Pointer to the device instance of the bus.
1258	* @param pDevIns The PCI bus device instance.
1259	* @param idxPdmBus The PDM ordinal value of the bus to get.
1260	*/
1261	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1262
1263	/** Just a safety precaution. */
1264	uint32_t u32TheEnd;
1265	} PDMPCIHLPR3;
1266	/** Pointer to PCI helpers. */
1267	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1268	/** Pointer to const PCI helpers. */
1269	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1270
1271	/** Current PDMPCIHLPR3 version number. */
1272	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1273
1274
1275	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1276	* These flags are used for memory access transactions via the IOMMU interface.
1277	* @{ */
1278	/** Memory read. */
1279	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1280	/** Memory write. */
1281	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1282	/** Valid flag mask. */
1283	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1284	/** @} */
1285
1286	/**
1287	* IOMMU registration structure for ring-0.
1288	*/
1289	typedef struct PDMIOMMUREGR0
1290	{
1291	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1292	* version. */
1293	uint32_t u32Version;
1294	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1295	uint32_t idxIommu;
1296
1297	/**
1298	* Translates the physical address for a memory transaction through the IOMMU.
1299	*
1300	* @returns VBox status code.
1301	* @param pDevIns The IOMMU device instance.
1302	* @param idDevice The device identifier (bus, device, function).
1303	* @param uIova The I/O virtual address being accessed.
1304	* @param cbIova The size of the access.
1305	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1306	* @param pGCPhysSpa Where to store the translated system physical address.
1307	* @param pcbContiguous Where to store the number of contiguous bytes translated
1308	* and permission-checked.
1309	*
1310	* @thread Any.
1311	*/
1312	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1313	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1314
1315	/**
1316	* Translates in bulk physical page addresses for memory transactions through the
1317	* IOMMU.
1318	*
1319	* @returns VBox status code.
1320	* @param pDevIns The IOMMU device instance.
1321	* @param idDevice The device identifier (bus, device, function).
1322	* @param cIovas The number of I/O virtual addresses being accessed.
1323	* @param pauIovas The I/O virtual addresses being accessed.
1324	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1325	* @param paGCPhysSpa Where to store the translated system physical page
1326	* addresses.
1327	*
1328	* @thread Any.
1329	*/
1330	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1331	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1332
1333	/**
1334	* Performs an interrupt remap request through the IOMMU.
1335	*
1336	* @returns VBox status code.
1337	* @param pDevIns The IOMMU device instance.
1338	* @param idDevice The device identifier (bus, device, function).
1339	* @param pMsiIn The source MSI.
1340	* @param pMsiOut Where to store the remapped MSI.
1341	*
1342	* @thread Any.
1343	*/
1344	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1345
1346	/** Just a safety precaution. */
1347	uint32_t u32TheEnd;
1348	} PDMIOMMUREGR0;
1349	/** Pointer to a IOMMU registration structure. */
1350	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1351
1352	/** Current PDMIOMMUREG version number. */
1353	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1354
1355
1356	/**
1357	* IOMMU registration structure for raw-mode.
1358	*/
1359	typedef struct PDMIOMMUREGRC
1360	{
1361	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1362	* version. */
1363	uint32_t u32Version;
1364	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1365	uint32_t idxIommu;
1366
1367	/**
1368	* Translates the physical address for a memory transaction through the IOMMU.
1369	*
1370	* @returns VBox status code.
1371	* @param pDevIns The IOMMU device instance.
1372	* @param idDevice The device identifier (bus, device, function).
1373	* @param uIova The I/O virtual address being accessed.
1374	* @param cbIova The size of the access.
1375	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1376	* @param pGCPhysSpa Where to store the translated system physical address.
1377	* @param pcbContiguous Where to store the number of contiguous bytes translated
1378	* and permission-checked.
1379	*
1380	* @thread Any.
1381	*/
1382	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1383	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1384
1385	/**
1386	* Translates in bulk physical page addresses for memory transactions through the
1387	* IOMMU.
1388	*
1389	* @returns VBox status code.
1390	* @param pDevIns The IOMMU device instance.
1391	* @param idDevice The device identifier (bus, device, function).
1392	* @param cIovas The number of I/O virtual addresses being accessed.
1393	* @param pauIovas The I/O virtual addresses being accessed.
1394	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1395	* @param paGCPhysSpa Where to store the translated system physical page
1396	* addresses.
1397	*
1398	* @thread Any.
1399	*/
1400	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1401	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1402
1403	/**
1404	* Performs an interrupt remap request through the IOMMU.
1405	*
1406	* @returns VBox status code.
1407	* @param pDevIns The IOMMU device instance.
1408	* @param idDevice The device identifier (bus, device, function).
1409	* @param pMsiIn The source MSI.
1410	* @param pMsiOut Where to store the remapped MSI.
1411	*
1412	* @thread Any.
1413	*/
1414	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1415
1416	/** Just a safety precaution. */
1417	uint32_t u32TheEnd;
1418	} PDMIOMMUREGRC;
1419	/** Pointer to a IOMMU registration structure. */
1420	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1421
1422	/** Current PDMIOMMUREG version number. */
1423	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1424
1425
1426	/**
1427	* IOMMU registration structure for ring-3.
1428	*/
1429	typedef struct PDMIOMMUREGR3
1430	{
1431	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1432	* version. */
1433	uint32_t u32Version;
1434	/** Padding. */
1435	uint32_t uPadding0;
1436
1437	/**
1438	* Translates the physical address for a memory transaction through the IOMMU.
1439	*
1440	* @returns VBox status code.
1441	* @param pDevIns The IOMMU device instance.
1442	* @param idDevice The device identifier (bus, device, function).
1443	* @param uIova The I/O virtual address being accessed.
1444	* @param cbIova The size of the access.
1445	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1446	* @param pGCPhysSpa Where to store the translated system physical address.
1447	* @param pcbContiguous Where to store the number of contiguous bytes translated
1448	* and permission-checked.
1449	*
1450	* @thread Any.
1451	*/
1452	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1453	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1454
1455	/**
1456	* Translates in bulk physical page addresses for memory transactions through the
1457	* IOMMU.
1458	*
1459	* @returns VBox status code.
1460	* @param pDevIns The IOMMU device instance.
1461	* @param idDevice The device identifier (bus, device, function).
1462	* @param cIovas The number of I/O virtual addresses being accessed.
1463	* @param pauIovas The I/O virtual addresses being accessed.
1464	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1465	* @param paGCPhysSpa Where to store the translated system physical page
1466	* addresses.
1467	*
1468	* @thread Any.
1469	*/
1470	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1471	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1472
1473	/**
1474	* Performs an interrupt remap request through the IOMMU.
1475	*
1476	* @returns VBox status code.
1477	* @param pDevIns The IOMMU device instance.
1478	* @param idDevice The device identifier (bus, device, function).
1479	* @param pMsiIn The source MSI.
1480	* @param pMsiOut Where to store the remapped MSI.
1481	*
1482	* @thread Any.
1483	*/
1484	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1485
1486	/** Just a safety precaution. */
1487	uint32_t u32TheEnd;
1488	} PDMIOMMUREGR3;
1489	/** Pointer to a IOMMU registration structure. */
1490	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1491
1492	/** Current PDMIOMMUREG version number. */
1493	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1494
1495	/** IOMMU registration structure for the current context. */
1496	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1497	/** Pointer to an IOMMU registration structure for the current context. */
1498	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1499	/** IOMMU registration structure version for the current context. */
1500	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1501
1502
1503	/**
1504	* IOMMU helpers for ring-0.
1505	*/
1506	typedef struct PDMIOMMUHLPR0
1507	{
1508	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1509	uint32_t u32Version;
1510
1511	/**
1512	* Acquires the PDM lock.
1513	*
1514	* @returns VINF_SUCCESS on success.
1515	* @returns rc if we failed to acquire the lock.
1516	* @param pDevIns The PCI device instance.
1517	* @param rc What to return if we fail to acquire the lock.
1518	*
1519	* @sa PDMCritSectEnter
1520	*/
1521	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1522
1523	/**
1524	* Releases the PDM lock.
1525	*
1526	* @param pDevIns The PCI device instance.
1527	*/
1528	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1529
1530	/**
1531	* Check whether the calling thread owns the PDM lock.
1532	*
1533	* @returns @c true if the PDM lock is owned, @c false otherwise.
1534	* @param pDevIns The PCI device instance.
1535	*/
1536	DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1537
1538	/**
1539	* Send an MSI (when generated by the IOMMU device itself).
1540	*
1541	* @param pDevIns PCI device instance.
1542	* @param pMsi The MSI to send.
1543	* @param uTagSrc The IRQ tag and source (for tracing).
1544	*/
1545	DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1546
1547	/** Just a safety precaution. */
1548	uint32_t u32TheEnd;
1549	} PDMIOMMUHLPR0;
1550	/** Pointer to IOMMU helpers for ring-0. */
1551	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1552	/** Pointer to const IOMMU helpers for ring-0. */
1553	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1554
1555	/** Current PDMIOMMUHLPR0 version number. */
1556	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1557
1558
1559	/**
1560	* IOMMU helpers for raw-mode.
1561	*/
1562	typedef struct PDMIOMMUHLPRC
1563	{
1564	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1565	uint32_t u32Version;
1566
1567	/**
1568	* Acquires the PDM lock.
1569	*
1570	* @returns VINF_SUCCESS on success.
1571	* @returns rc if we failed to acquire the lock.
1572	* @param pDevIns The PCI device instance.
1573	* @param rc What to return if we fail to acquire the lock.
1574	*
1575	* @sa PDMCritSectEnter
1576	*/
1577	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1578
1579	/**
1580	* Releases the PDM lock.
1581	*
1582	* @param pDevIns The PCI device instance.
1583	*/
1584	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1585
1586	/**
1587	* Check whether the threads owns the PDM lock.
1588	*
1589	* @returns @c true if the PDM lock is owned, @c false otherwise.
1590	* @param pDevIns The PCI device instance.
1591	*/
1592	DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1593
1594	/**
1595	* Send an MSI (when generated by the IOMMU device itself).
1596	*
1597	* @param pDevIns PCI device instance.
1598	* @param pMsi The MSI to send.
1599	* @param uTagSrc The IRQ tag and source (for tracing).
1600	*/
1601	DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1602
1603	/** Just a safety precaution. */
1604	uint32_t u32TheEnd;
1605	} PDMIOMMUHLPRC;
1606	/** Pointer to IOMMU helpers for raw-mode. */
1607	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1608	/** Pointer to const IOMMU helpers for raw-mode. */
1609	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1610
1611	/** Current PDMIOMMUHLPRC version number. */
1612	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1613
1614
1615	/**
1616	* IOMMU helpers for ring-3.
1617	*/
1618	typedef struct PDMIOMMUHLPR3
1619	{
1620	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1621	uint32_t u32Version;
1622
1623	/**
1624	* Acquires the PDM lock.
1625	*
1626	* @returns VINF_SUCCESS on success.
1627	* @returns rc if we failed to acquire the lock.
1628	* @param pDevIns The PCI device instance.
1629	* @param rc What to return if we fail to acquire the lock.
1630	*
1631	* @sa PDMCritSectEnter
1632	*/
1633	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1634
1635	/**
1636	* Releases the PDM lock.
1637	*
1638	* @param pDevIns The PCI device instance.
1639	*/
1640	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1641
1642	/**
1643	* Check whether the threads owns the PDM lock.
1644	*
1645	* @returns @c true if the PDM lock is owned, @c false otherwise.
1646	* @param pDevIns The PCI device instance.
1647	*/
1648	DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1649
1650	/**
1651	* Send an MSI (when generated by the IOMMU device itself).
1652	*
1653	* @param pDevIns PCI device instance.
1654	* @param pMsi The MSI to send.
1655	* @param uTagSrc The IRQ tag and source (for tracing).
1656	*/
1657	DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1658
1659	/** Just a safety precaution. */
1660	uint32_t u32TheEnd;
1661	} PDMIOMMUHLPR3;
1662	/** Pointer to IOMMU helpers for raw-mode. */
1663	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1664	/** Pointer to const IOMMU helpers for raw-mode. */
1665	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1666
1667	/** Current PDMIOMMUHLPR3 version number. */
1668	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1669
1670
1671	/**
1672	* Programmable Interrupt Controller registration structure (all contexts).
1673	*/
1674	typedef struct PDMPICREG
1675	{
1676	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1677	uint32_t u32Version;
1678
1679	/**
1680	* Set the an IRQ.
1681	*
1682	* @param pDevIns Device instance of the PIC.
1683	* @param iIrq IRQ number to set.
1684	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1685	* @param uTagSrc The IRQ tag and source (for tracing).
1686	* @remarks Caller enters the PDM critical section.
1687	*/
1688	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1689
1690	/**
1691	* Get a pending interrupt.
1692	*
1693	* @returns Pending interrupt number.
1694	* @param pDevIns Device instance of the PIC.
1695	* @param puTagSrc Where to return the IRQ tag and source.
1696	* @remarks Caller enters the PDM critical section.
1697	*/
1698	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1699
1700	/** Just a safety precaution. */
1701	uint32_t u32TheEnd;
1702	} PDMPICREG;
1703	/** Pointer to a PIC registration structure. */
1704	typedef PDMPICREG *PPDMPICREG;
1705
1706	/** Current PDMPICREG version number. */
1707	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1708
1709	/**
1710	* PIC helpers, same in all contexts.
1711	*/
1712	typedef struct PDMPICHLP
1713	{
1714	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1715	uint32_t u32Version;
1716
1717	/**
1718	* Set the interrupt force action flag.
1719	*
1720	* @param pDevIns Device instance of the PIC.
1721	*/
1722	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1723
1724	/**
1725	* Clear the interrupt force action flag.
1726	*
1727	* @param pDevIns Device instance of the PIC.
1728	*/
1729	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1730
1731	/**
1732	* Acquires the PDM lock.
1733	*
1734	* @returns VINF_SUCCESS on success.
1735	* @returns rc if we failed to acquire the lock.
1736	* @param pDevIns The PIC device instance.
1737	* @param rc What to return if we fail to acquire the lock.
1738	*
1739	* @sa PDMCritSectEnter
1740	*/
1741	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1742
1743	/**
1744	* Releases the PDM lock.
1745	*
1746	* @param pDevIns The PIC device instance.
1747	*/
1748	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1749
1750	/** Just a safety precaution. */
1751	uint32_t u32TheEnd;
1752	} PDMPICHLP;
1753	/** Pointer to PIC helpers. */
1754	typedef PDMPICHLP *PPDMPICHLP;
1755	/** Pointer to const PIC helpers. */
1756	typedef const PDMPICHLP *PCPDMPICHLP;
1757
1758	/** Current PDMPICHLP version number. */
1759	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1760
1761
1762	/**
1763	* Firmware registration structure.
1764	*/
1765	typedef struct PDMFWREG
1766	{
1767	/** Struct version+magic number (PDM_FWREG_VERSION). */
1768	uint32_t u32Version;
1769
1770	/**
1771	* Checks whether this is a hard or soft reset.
1772	*
1773	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1774	* is 5, 9 or 0xA.
1775	*
1776	* @returns true if hard reset, false if soft.
1777	* @param pDevIns Device instance of the firmware.
1778	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1779	*/
1780	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1781
1782	/** Just a safety precaution. */
1783	uint32_t u32TheEnd;
1784	} PDMFWREG;
1785	/** Pointer to a FW registration structure. */
1786	typedef PDMFWREG *PPDMFWREG;
1787	/** Pointer to a const FW registration structure. */
1788	typedef PDMFWREG const *PCPDMFWREG;
1789
1790	/** Current PDMFWREG version number. */
1791	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1792
1793	/**
1794	* Firmware R3 helpers.
1795	*/
1796	typedef struct PDMFWHLPR3
1797	{
1798	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1799	uint32_t u32Version;
1800
1801	/** Just a safety precaution. */
1802	uint32_t u32TheEnd;
1803	} PDMFWHLPR3;
1804
1805	/** Pointer to FW R3 helpers. */
1806	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1807	/** Pointer to const FW R3 helpers. */
1808	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1809
1810	/** Current PDMFWHLPR3 version number. */
1811	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1812
1813
1814	/**
1815	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1816	*
1817	* Also used in saved-states, CFGM don't change existing values.
1818	*/
1819	typedef enum PDMAPICMODE
1820	{
1821	/** Invalid 0 entry. */
1822	PDMAPICMODE_INVALID = 0,
1823	/** No APIC. */
1824	PDMAPICMODE_NONE,
1825	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1826	PDMAPICMODE_APIC,
1827	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1828	PDMAPICMODE_X2APIC,
1829	/** The usual 32-bit paranoia. */
1830	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1831	} PDMAPICMODE;
1832
1833	/**
1834	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1835	*/
1836	typedef enum PDMAPICIRQ
1837	{
1838	/** Invalid 0 entry. */
1839	PDMAPICIRQ_INVALID = 0,
1840	/** Normal hardware interrupt. */
1841	PDMAPICIRQ_HARDWARE,
1842	/** NMI. */
1843	PDMAPICIRQ_NMI,
1844	/** SMI. */
1845	PDMAPICIRQ_SMI,
1846	/** ExtINT (HW interrupt via PIC). */
1847	PDMAPICIRQ_EXTINT,
1848	/** Interrupt arrived, needs to be updated to the IRR. */
1849	PDMAPICIRQ_UPDATE_PENDING,
1850	/** The usual 32-bit paranoia. */
1851	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1852	} PDMAPICIRQ;
1853
1854
1855	/**
1856	* I/O APIC registration structure (all contexts).
1857	*/
1858	typedef struct PDMIOAPICREG
1859	{
1860	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1861	uint32_t u32Version;
1862
1863	/**
1864	* Set an IRQ.
1865	*
1866	* @param pDevIns Device instance of the I/O APIC.
1867	* @param uBusDevFn The bus:device:function of the device initiating the
1868	* IRQ. Can be NIL_PCIBDF.
1869	* @param iIrq IRQ number to set.
1870	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1871	* @param uTagSrc The IRQ tag and source (for tracing).
1872	*
1873	* @remarks Caller enters the PDM critical section
1874	* Actually, as per 2018-07-21 this isn't true (bird).
1875	*/
1876	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1877
1878	/**
1879	* Send a MSI.
1880	*
1881	* @param pDevIns Device instance of the I/O APIC.
1882	* @param uBusDevFn The bus:device:function of the device initiating the
1883	* MSI. Cannot be NIL_PCIBDF.
1884	* @param pMsi The MSI to send.
1885	* @param uTagSrc The IRQ tag and source (for tracing).
1886	*
1887	* @remarks Caller enters the PDM critical section
1888	* Actually, as per 2018-07-21 this isn't true (bird).
1889	*/
1890	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1891
1892	/**
1893	* Set the EOI for an interrupt vector.
1894	*
1895	* @param pDevIns Device instance of the I/O APIC.
1896	* @param u8Vector The vector.
1897	*
1898	* @remarks Caller enters the PDM critical section
1899	* Actually, as per 2018-07-21 this isn't true (bird).
1900	*/
1901	DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1902
1903	/** Just a safety precaution. */
1904	uint32_t u32TheEnd;
1905	} PDMIOAPICREG;
1906	/** Pointer to an APIC registration structure. */
1907	typedef PDMIOAPICREG *PPDMIOAPICREG;
1908
1909	/** Current PDMAPICREG version number. */
1910	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1911
1912
1913	/**
1914	* IOAPIC helpers, same in all contexts.
1915	*/
1916	typedef struct PDMIOAPICHLP
1917	{
1918	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1919	uint32_t u32Version;
1920
1921	/**
1922	* Private interface between the IOAPIC and APIC.
1923	*
1924	* @returns status code.
1925	* @param pDevIns Device instance of the IOAPIC.
1926	* @param u8Dest See APIC implementation.
1927	* @param u8DestMode See APIC implementation.
1928	* @param u8DeliveryMode See APIC implementation.
1929	* @param uVector See APIC implementation.
1930	* @param u8Polarity See APIC implementation.
1931	* @param u8TriggerMode See APIC implementation.
1932	* @param uTagSrc The IRQ tag and source (for tracing).
1933	*
1934	* @sa APICBusDeliver()
1935	*/
1936	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1937	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1938
1939	/**
1940	* Acquires the PDM lock.
1941	*
1942	* @returns VINF_SUCCESS on success.
1943	* @returns rc if we failed to acquire the lock.
1944	* @param pDevIns The IOAPIC device instance.
1945	* @param rc What to return if we fail to acquire the lock.
1946	*
1947	* @sa PDMCritSectEnter
1948	*/
1949	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1950
1951	/**
1952	* Releases the PDM lock.
1953	*
1954	* @param pDevIns The IOAPIC device instance.
1955	*/
1956	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1957
1958	/**
1959	* Checks if the calling thread owns the PDM lock.
1960	*
1961	* @param pDevIns The IOAPIC device instance.
1962	*/
1963	DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1964
1965	/**
1966	* Private interface between the IOAPIC and IOMMU.
1967	*
1968	* @returns status code.
1969	* @param pDevIns Device instance of the IOAPIC.
1970	* @param idDevice The device identifier (bus, device, function).
1971	* @param pMsiIn The source MSI.
1972	* @param pMsiOut Where to store the remapped MSI (only updated when
1973	* VINF_SUCCESS is returned).
1974	*/
1975	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1976
1977	/** Just a safety precaution. */
1978	uint32_t u32TheEnd;
1979	} PDMIOAPICHLP;
1980	/** Pointer to IOAPIC helpers. */
1981	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1982	/** Pointer to const IOAPIC helpers. */
1983	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1984
1985	/** Current PDMIOAPICHLP version number. */
1986	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1987
1988
1989	/**
1990	* HPET registration structure.
1991	*/
1992	typedef struct PDMHPETREG
1993	{
1994	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1995	uint32_t u32Version;
1996	} PDMHPETREG;
1997	/** Pointer to an HPET registration structure. */
1998	typedef PDMHPETREG *PPDMHPETREG;
1999
2000	/** Current PDMHPETREG version number. */
2001	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
2002
2003	/**
2004	* HPET RC helpers.
2005	*
2006	* @remarks Keep this around in case HPET will need PDM interaction in again RC
2007	* at some later point.
2008	*/
2009	typedef struct PDMHPETHLPRC
2010	{
2011	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
2012	uint32_t u32Version;
2013
2014	/** Just a safety precaution. */
2015	uint32_t u32TheEnd;
2016	} PDMHPETHLPRC;
2017
2018	/** Pointer to HPET RC helpers. */
2019	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
2020	/** Pointer to const HPET RC helpers. */
2021	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
2022
2023	/** Current PDMHPETHLPRC version number. */
2024	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
2025
2026
2027	/**
2028	* HPET R0 helpers.
2029	*
2030	* @remarks Keep this around in case HPET will need PDM interaction in again R0
2031	* at some later point.
2032	*/
2033	typedef struct PDMHPETHLPR0
2034	{
2035	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2036	uint32_t u32Version;
2037
2038	/** Just a safety precaution. */
2039	uint32_t u32TheEnd;
2040	} PDMHPETHLPR0;
2041
2042	/** Pointer to HPET R0 helpers. */
2043	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2044	/** Pointer to const HPET R0 helpers. */
2045	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2046
2047	/** Current PDMHPETHLPR0 version number. */
2048	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2049
2050	/**
2051	* HPET R3 helpers.
2052	*/
2053	typedef struct PDMHPETHLPR3
2054	{
2055	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2056	uint32_t u32Version;
2057
2058	/**
2059	* Set legacy mode on PIT and RTC.
2060	*
2061	* @returns VINF_SUCCESS on success.
2062	* @returns rc if we failed to set legacy mode.
2063	* @param pDevIns Device instance of the HPET.
2064	* @param fActivated Whether legacy mode is activated or deactivated.
2065	*/
2066	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2067
2068
2069	/**
2070	* Set IRQ, bypassing ISA bus override rules.
2071	*
2072	* @returns VINF_SUCCESS on success.
2073	* @returns rc if we failed to set legacy mode.
2074	* @param pDevIns Device instance of the HPET.
2075	* @param iIrq IRQ number to set.
2076	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2077	*/
2078	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2079
2080	/** Just a safety precaution. */
2081	uint32_t u32TheEnd;
2082	} PDMHPETHLPR3;
2083
2084	/** Pointer to HPET R3 helpers. */
2085	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2086	/** Pointer to const HPET R3 helpers. */
2087	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2088
2089	/** Current PDMHPETHLPR3 version number. */
2090	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2091
2092
2093	/**
2094	* Raw PCI device registration structure.
2095	*/
2096	typedef struct PDMPCIRAWREG
2097	{
2098	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2099	uint32_t u32Version;
2100	/** Just a safety precaution. */
2101	uint32_t u32TheEnd;
2102	} PDMPCIRAWREG;
2103	/** Pointer to a raw PCI registration structure. */
2104	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2105
2106	/** Current PDMPCIRAWREG version number. */
2107	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2108
2109	/**
2110	* Raw PCI device raw-mode context helpers.
2111	*/
2112	typedef struct PDMPCIRAWHLPRC
2113	{
2114	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2115	uint32_t u32Version;
2116	/** Just a safety precaution. */
2117	uint32_t u32TheEnd;
2118	} PDMPCIRAWHLPRC;
2119	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2120	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2121	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2122	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2123
2124	/** Current PDMPCIRAWHLPRC version number. */
2125	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2126
2127	/**
2128	* Raw PCI device ring-0 context helpers.
2129	*/
2130	typedef struct PDMPCIRAWHLPR0
2131	{
2132	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2133	uint32_t u32Version;
2134	/** Just a safety precaution. */
2135	uint32_t u32TheEnd;
2136	} PDMPCIRAWHLPR0;
2137	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2138	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2139	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2140	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2141
2142	/** Current PDMPCIRAWHLPR0 version number. */
2143	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2144
2145
2146	/**
2147	* Raw PCI device ring-3 context helpers.
2148	*/
2149	typedef struct PDMPCIRAWHLPR3
2150	{
2151	/** Undefined structure version and magic number. */
2152	uint32_t u32Version;
2153
2154	/**
2155	* Gets the address of the RC raw PCI device helpers.
2156	*
2157	* This should be called at both construction and relocation time to obtain
2158	* the correct address of the RC helpers.
2159	*
2160	* @returns RC pointer to the raw PCI device helpers.
2161	* @param pDevIns Device instance of the raw PCI device.
2162	*/
2163	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2164
2165	/**
2166	* Gets the address of the R0 raw PCI device helpers.
2167	*
2168	* This should be called at both construction and relocation time to obtain
2169	* the correct address of the R0 helpers.
2170	*
2171	* @returns R0 pointer to the raw PCI device helpers.
2172	* @param pDevIns Device instance of the raw PCI device.
2173	*/
2174	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2175
2176	/** Just a safety precaution. */
2177	uint32_t u32TheEnd;
2178	} PDMPCIRAWHLPR3;
2179	/** Pointer to raw PCI R3 helpers. */
2180	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2181	/** Pointer to const raw PCI R3 helpers. */
2182	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2183
2184	/** Current PDMPCIRAWHLPR3 version number. */
2185	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2186
2187
2188	#ifdef IN_RING3
2189
2190	/**
2191	* DMA Transfer Handler.
2192	*
2193	* @returns Number of bytes transferred.
2194	* @param pDevIns The device instance that registered the handler.
2195	* @param pvUser User pointer.
2196	* @param uChannel Channel number.
2197	* @param off DMA position.
2198	* @param cb Block size.
2199	* @remarks The device lock is take before the callback (in fact, the locks of
2200	* DMA devices and the DMA controller itself are taken).
2201	*/
2202	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2203	uint32_t off, uint32_t cb));
2204	/** Pointer to a FNDMATRANSFERHANDLER(). */
2205	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2206
2207	/**
2208	* DMA Controller registration structure.
2209	*/
2210	typedef struct PDMDMAREG
2211	{
2212	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2213	uint32_t u32Version;
2214
2215	/**
2216	* Execute pending transfers.
2217	*
2218	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2219	* @param pDevIns Device instance of the DMAC.
2220	* @remarks No locks held, called on EMT(0) as a form of serialization.
2221	*/
2222	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2223
2224	/**
2225	* Register transfer function for DMA channel.
2226	*
2227	* @param pDevIns Device instance of the DMAC.
2228	* @param uChannel Channel number.
2229	* @param pDevInsHandler The device instance of the device making the
2230	* regstration (will be passed to the callback).
2231	* @param pfnTransferHandler Device specific transfer function.
2232	* @param pvUser User pointer to be passed to the callback.
2233	* @remarks No locks held, called on an EMT.
2234	*/
2235	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2236	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2237
2238	/**
2239	* Read memory
2240	*
2241	* @returns Number of bytes read.
2242	* @param pDevIns Device instance of the DMAC.
2243	* @param uChannel Channel number.
2244	* @param pvBuffer Pointer to target buffer.
2245	* @param off DMA position.
2246	* @param cbBlock Block size.
2247	* @remarks No locks held, called on an EMT.
2248	*/
2249	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2250
2251	/**
2252	* Write memory
2253	*
2254	* @returns Number of bytes written.
2255	* @param pDevIns Device instance of the DMAC.
2256	* @param uChannel Channel number.
2257	* @param pvBuffer Memory to write.
2258	* @param off DMA position.
2259	* @param cbBlock Block size.
2260	* @remarks No locks held, called on an EMT.
2261	*/
2262	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2263
2264	/**
2265	* Set the DREQ line.
2266	*
2267	* @param pDevIns Device instance of the DMAC.
2268	* @param uChannel Channel number.
2269	* @param uLevel Level of the line.
2270	* @remarks No locks held, called on an EMT.
2271	*/
2272	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2273
2274	/**
2275	* Get channel mode
2276	*
2277	* @returns Channel mode.
2278	* @param pDevIns Device instance of the DMAC.
2279	* @param uChannel Channel number.
2280	* @remarks No locks held, called on an EMT.
2281	*/
2282	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2283
2284	} PDMDMACREG;
2285	/** Pointer to a DMAC registration structure. */
2286	typedef PDMDMACREG *PPDMDMACREG;
2287
2288	/** Current PDMDMACREG version number. */
2289	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2290
2291
2292	/**
2293	* DMA Controller device helpers.
2294	*/
2295	typedef struct PDMDMACHLP
2296	{
2297	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2298	uint32_t u32Version;
2299
2300	/* to-be-defined */
2301
2302	} PDMDMACHLP;
2303	/** Pointer to DMAC helpers. */
2304	typedef PDMDMACHLP *PPDMDMACHLP;
2305	/** Pointer to const DMAC helpers. */
2306	typedef const PDMDMACHLP *PCPDMDMACHLP;
2307
2308	/** Current PDMDMACHLP version number. */
2309	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2310
2311	#endif /* IN_RING3 */
2312
2313
2314
2315	/**
2316	* RTC registration structure.
2317	*/
2318	typedef struct PDMRTCREG
2319	{
2320	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2321	uint32_t u32Version;
2322	uint32_t u32Alignment; /*< structure size alignment. /
2323
2324	/**
2325	* Write to a CMOS register and update the checksum if necessary.
2326	*
2327	* @returns VBox status code.
2328	* @param pDevIns Device instance of the RTC.
2329	* @param iReg The CMOS register index.
2330	* @param u8Value The CMOS register value.
2331	* @remarks Caller enters the device critical section.
2332	*/
2333	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2334
2335	/**
2336	* Read a CMOS register.
2337	*
2338	* @returns VBox status code.
2339	* @param pDevIns Device instance of the RTC.
2340	* @param iReg The CMOS register index.
2341	* @param pu8Value Where to store the CMOS register value.
2342	* @remarks Caller enters the device critical section.
2343	*/
2344	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2345
2346	} PDMRTCREG;
2347	/** Pointer to a RTC registration structure. */
2348	typedef PDMRTCREG *PPDMRTCREG;
2349	/** Pointer to a const RTC registration structure. */
2350	typedef const PDMRTCREG *PCPDMRTCREG;
2351
2352	/** Current PDMRTCREG version number. */
2353	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2354
2355
2356	/**
2357	* RTC device helpers.
2358	*/
2359	typedef struct PDMRTCHLP
2360	{
2361	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2362	uint32_t u32Version;
2363
2364	/* to-be-defined */
2365
2366	} PDMRTCHLP;
2367	/** Pointer to RTC helpers. */
2368	typedef PDMRTCHLP *PPDMRTCHLP;
2369	/** Pointer to const RTC helpers. */
2370	typedef const PDMRTCHLP *PCPDMRTCHLP;
2371
2372	/** Current PDMRTCHLP version number. */
2373	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2374
2375
2376
2377	/** @name Flags for PCI I/O region registration
2378	* @{ */
2379	/** No handle is passed. */
2380	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2381	/** An I/O port handle is passed. */
2382	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2383	/** An MMIO range handle is passed. */
2384	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2385	/** An MMIO2 handle is passed. */
2386	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2387	/** Handle type mask. */
2388	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2389	/** New-style (mostly wrt callbacks). */
2390	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2391	/** Mask of valid flags. */
2392	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2393	/** @} */
2394
2395
2396	/** @name Flags for the guest physical read/write helpers
2397	* @{ */
2398	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2399	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2400	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2401	* by the device in any way. */
2402	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2403	/** The data is metadata and being processed by the device in some way. */
2404	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2405	/** @} */
2406
2407
2408	#ifdef IN_RING3
2409
2410	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2411	* @{ */
2412	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2413	* This is handy when registering multiple PCI device functions and the device
2414	* number is left up to the PCI bus. In order to facilitate one PDM device
2415	* instance for each PCI function, this searches earlier PDM device
2416	* instances as well. */
2417	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2418	/** Use the first unused device number (all functions must be unused). */
2419	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2420	/** Use the first unused device function. */
2421	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2422
2423	/** The device and function numbers are not mandatory, just suggestions. */
2424	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2425	/** Registering a PCI bridge device. */
2426	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2427	/** Valid flag mask. */
2428	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2429	/** @} */
2430
2431	/** Current PDMDEVHLPR3 version number. */
2432	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 66, 0)
2433
2434	/**
2435	* PDM Device API.
2436	*/
2437	typedef struct PDMDEVHLPR3
2438	{
2439	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2440	uint32_t u32Version;
2441
2442	/** @name I/O ports
2443	* @{ */
2444	/**
2445	* Creates a range of I/O ports for a device.
2446	*
2447	* The I/O port range must be mapped in a separately call. Any ring-0 and
2448	* raw-mode context callback handlers needs to be set up in the respective
2449	* contexts.
2450	*
2451	* @returns VBox status.
2452	* @param pDevIns The device instance to register the ports with.
2453	* @param cPorts Number of ports to register.
2454	* @param fFlags IOM_IOPORT_F_XXX.
2455	* @param pPciDev The PCI device the range is associated with, if
2456	* applicable.
2457	* @param iPciRegion The PCI device region in the high 16-bit word and
2458	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2459	* @param pfnOut Pointer to function which is gonna handle OUT
2460	* operations. Optional.
2461	* @param pfnIn Pointer to function which is gonna handle IN operations.
2462	* Optional.
2463	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2464	* operations. Optional.
2465	* @param pfnInStr Pointer to function which is gonna handle string IN
2466	* operations. Optional.
2467	* @param pvUser User argument to pass to the callbacks.
2468	* @param pszDesc Pointer to description string. This must not be freed.
2469	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2470	* coverage is allowed. This must not be freed.
2471	* @param phIoPorts Where to return the I/O port range handle.
2472	*
2473	* @remarks Caller enters the device critical section prior to invoking the
2474	* registered callback methods.
2475	*
2476	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2477	* PDMDevHlpIoPortUnmap.
2478	*/
2479	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2480	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2481	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2482	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2483
2484	/**
2485	* Maps an I/O port range.
2486	*
2487	* @returns VBox status.
2488	* @param pDevIns The device instance to register the ports with.
2489	* @param hIoPorts The I/O port range handle.
2490	* @param Port Where to map the range.
2491	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2492	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2493	*/
2494	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2495
2496	/**
2497	* Unmaps an I/O port range.
2498	*
2499	* @returns VBox status.
2500	* @param pDevIns The device instance to register the ports with.
2501	* @param hIoPorts The I/O port range handle.
2502	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2503	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2504	*/
2505	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2506
2507	/**
2508	* Gets the mapping address of the I/O port range @a hIoPorts.
2509	*
2510	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2511	* parameters).
2512	* @param pDevIns The device instance to register the ports with.
2513	* @param hIoPorts The I/O port range handle.
2514	*/
2515	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2516
2517	/**
2518	* Reads from an I/O port register.
2519	*
2520	* @returns Strict VBox status code. Informational status codes other than the one documented
2521	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2522	* @retval VINF_SUCCESS Success.
2523	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2524	* status code must be passed on to EM.
2525	*
2526	* @param pDevIns The device instance to register the ports with.
2527	* @param Port The port to read from.
2528	* @param pu32Value Where to store the read value.
2529	* @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
2530	*
2531	* @thread EMT
2532	*
2533	* @note This is required for the ARM platform in order to emulate PIO accesses through a dedicated MMIO region.
2534	*/
2535	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnIoPortRead,(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue));
2536
2537	/**
2538	* Writes to an I/O port register.
2539	*
2540	* @returns Strict VBox status code. Informational status codes other than the one documented
2541	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2542	* @retval VINF_SUCCESS Success.
2543	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2544	* status code must be passed on to EM.
2545	*
2546	* @param pDevIns The device instance to register the ports with.
2547	* @param Port The port to write to.
2548	* @param u32Value The value to write.
2549	* @param cbValue The size of the register to write in bytes. 1, 2 or 4 bytes.
2550	*
2551	* @thread EMT
2552	*
2553	* @note This is required for the ARM platform in order to emulate PIO accesses through a dedicated MMIO region.
2554	*/
2555	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnIoPortWrite,(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t u32Value, size_t cbValue));
2556	/** @} */
2557
2558	/** @name MMIO
2559	* @{ */
2560	/**
2561	* Creates a memory mapped I/O (MMIO) region for a device.
2562	*
2563	* The MMIO region must be mapped in a separately call. Any ring-0 and
2564	* raw-mode context callback handlers needs to be set up in the respective
2565	* contexts.
2566	*
2567	* @returns VBox status.
2568	* @param pDevIns The device instance to register the ports with.
2569	* @param cbRegion The size of the region in bytes.
2570	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2571	* @param pPciDev The PCI device the range is associated with, if
2572	* applicable.
2573	* @param iPciRegion The PCI device region in the high 16-bit word and
2574	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2575	* @param pfnWrite Pointer to function which is gonna handle Write
2576	* operations.
2577	* @param pfnRead Pointer to function which is gonna handle Read
2578	* operations.
2579	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2580	* operations. (optional)
2581	* @param pvUser User argument to pass to the callbacks.
2582	* @param pszDesc Pointer to description string. This must not be freed.
2583	* @param phRegion Where to return the MMIO region handle.
2584	*
2585	* @remarks Caller enters the device critical section prior to invoking the
2586	* registered callback methods.
2587	*
2588	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2589	*/
2590	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2591	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2592	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2593	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2594
2595	/**
2596	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2597	*
2598	* @returns VBox status.
2599	* @param pDevIns The device instance the region is associated with.
2600	* @param hRegion The MMIO region handle.
2601	* @param GCPhys Where to map the region.
2602	* @note An MMIO range may overlap with base memory if a lot of RAM is
2603	* configured for the VM, in which case we'll drop the base memory
2604	* pages. Presently we will make no attempt to preserve anything that
2605	* happens to be present in the base memory that is replaced, this is
2606	* technically incorrect but it's just not worth the effort to do
2607	* right, at least not at this point.
2608	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2609	* PDMDevHlpMmioSetUpContext
2610	*/
2611	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2612
2613	/**
2614	* Unmaps a memory mapped I/O (MMIO) region.
2615	*
2616	* @returns VBox status.
2617	* @param pDevIns The device instance the region is associated with.
2618	* @param hRegion The MMIO region handle.
2619	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2620	* PDMDevHlpMmioSetUpContext
2621	*/
2622	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2623
2624	/**
2625	* Reduces the length of a MMIO range.
2626	*
2627	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2628	* only work during saved state restore. It will not call the PCI bus code, as
2629	* that is expected to restore the saved resource configuration.
2630	*
2631	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2632	* called it will only map @a cbRegion bytes and not the value set during
2633	* registration.
2634	*
2635	* @return VBox status code.
2636	* @param pDevIns The device owning the range.
2637	* @param hRegion The MMIO region handle.
2638	* @param cbRegion The new size, must be smaller.
2639	*/
2640	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2641
2642	/**
2643	* Gets the mapping address of the MMIO region @a hRegion.
2644	*
2645	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2646	* @param pDevIns The device instance to register the ports with.
2647	* @param hRegion The MMIO region handle.
2648	*/
2649	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2650	/** @} */
2651
2652	/** @name MMIO2
2653	* @{ */
2654	/**
2655	* Creates a MMIO2 region.
2656	*
2657	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2658	* associated with a device. It is also non-shared memory with a permanent
2659	* ring-3 mapping and page backing (presently).
2660	*
2661	* @returns VBox status.
2662	* @param pDevIns The device instance.
2663	* @param pPciDev The PCI device the region is associated with, or
2664	* NULL if no PCI device association.
2665	* @param iPciRegion The region number. Use the PCI region number as
2666	* this must be known to the PCI bus device too. If
2667	* it's not associated with the PCI device, then
2668	* any number up to UINT8_MAX is fine.
2669	* @param cbRegion The size (in bytes) of the region.
2670	* @param fFlags PGMPHYS_MMIO2_FLAGS_XXX (see pgm.h).
2671	* @param pszDesc Pointer to description string. This must not be
2672	* freed.
2673	* @param ppvMapping Where to store the address of the ring-3 mapping
2674	* of the memory.
2675	* @param phRegion Where to return the MMIO2 region handle.
2676	*
2677	* @thread EMT(0)
2678	*/
2679	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2680	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2681
2682	/**
2683	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2684	*
2685	* Any physical access handlers registered for the region must be deregistered
2686	* before calling this function.
2687	*
2688	* @returns VBox status code.
2689	* @param pDevIns The device instance.
2690	* @param hRegion The MMIO2 region handle.
2691	* @thread EMT.
2692	*/
2693	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2694
2695	/**
2696	* Maps a MMIO2 region (into the guest physical address space).
2697	*
2698	* @returns VBox status.
2699	* @param pDevIns The device instance the region is associated with.
2700	* @param hRegion The MMIO2 region handle.
2701	* @param GCPhys Where to map the region.
2702	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2703	* configured for the VM, in which case we'll drop the base memory
2704	* pages. Presently we will make no attempt to preserve anything that
2705	* happens to be present in the base memory that is replaced, this is
2706	* technically incorrect but it's just not worth the effort to do
2707	* right, at least not at this point.
2708	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2709	*/
2710	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2711
2712	/**
2713	* Unmaps a MMIO2 region.
2714	*
2715	* @returns VBox status.
2716	* @param pDevIns The device instance the region is associated with.
2717	* @param hRegion The MMIO2 region handle.
2718	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2719	*/
2720	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2721
2722	/**
2723	* Reduces the length of a MMIO range.
2724	*
2725	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2726	* only work during saved state restore. It will not call the PCI bus code, as
2727	* that is expected to restore the saved resource configuration.
2728	*
2729	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2730	* called it will only map @a cbRegion bytes and not the value set during
2731	* registration.
2732	*
2733	* @return VBox status code.
2734	* @param pDevIns The device owning the range.
2735	* @param hRegion The MMIO2 region handle.
2736	* @param cbRegion The new size, must be smaller.
2737	*/
2738	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2739
2740	/**
2741	* Gets the mapping address of the MMIO region @a hRegion.
2742	*
2743	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2744	* @param pDevIns The device instance to register the ports with.
2745	* @param hRegion The MMIO2 region handle.
2746	*/
2747	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2748
2749	/**
2750	* Queries and resets the dirty bitmap for an MMIO2 region.
2751	*
2752	* The MMIO2 region must have been created with the
2753	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
2754	*
2755	* @returns VBox status code.
2756	* @param pDevIns The device instance.
2757	* @param hRegion The MMIO2 region handle.
2758	* @param pvBitmap Where to return the bitmap. Must be 8-byte aligned.
2759	* Can be NULL if only resetting the tracking is desired.
2760	* @param cbBitmap The bitmap size. One bit per page in the region,
2761	* rounded up to 8-bytes. If pvBitmap is NULL this must
2762	* also be zero.
2763	*/
2764	DECLR3CALLBACKMEMBER(int, pfnMmio2QueryAndResetDirtyBitmap, (PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
2765	void *pvBitmap, size_t cbBitmap));
2766
2767	/**
2768	* Controls the dirty page tracking for an MMIO2 region.
2769	*
2770	* The MMIO2 region must have been created with the
2771	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
2772	*
2773	* @returns VBox status code.
2774	* @param pDevIns The device instance.
2775	* @param hRegion The MMIO2 region handle.
2776	* @param fEnabled When set to @c true the dirty page tracking will be
2777	* enabled if currently disabled (bitmap is reset). When
2778	* set to @c false the dirty page tracking will be
2779	* disabled.
2780	*/
2781	DECLR3CALLBACKMEMBER(int, pfnMmio2ControlDirtyPageTracking, (PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, bool fEnabled));
2782
2783	/**
2784	* Changes the number of an MMIO2 or pre-registered MMIO region.
2785	*
2786	* This should only be used to deal with saved state problems, so there is no
2787	* convenience inline wrapper for this method.
2788	*
2789	* @returns VBox status code.
2790	* @param pDevIns The device instance.
2791	* @param hRegion The MMIO2 region handle.
2792	* @param iNewRegion The new region index.
2793	*
2794	* @sa @bugref{9359}
2795	*/
2796	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2797
2798	/**
2799	* Mapping an MMIO2 page in place of an MMIO page for direct access.
2800	*
2801	* This is a special optimization used by the VGA device. Call
2802	* PDMDevHlpMmioResetRegion() to undo the mapping.
2803	*
2804	* @returns VBox status code. This API may return VINF_SUCCESS even if no
2805	* remapping is made.
2806	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
2807	*
2808	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
2809	* associated with.
2810	* @param hRegion The handle to the MMIO region.
2811	* @param offRegion The offset into @a hRegion of the page to be
2812	* remapped.
2813	* @param hMmio2 The MMIO2 handle.
2814	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
2815	* mapping.
2816	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
2817	* for the time being.
2818	*/
2819	DECLR3CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
2820	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
2821
2822	/**
2823	* Reset a previously modified MMIO region; restore the access flags.
2824	*
2825	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
2826	* intended for some ancient VGA hack. However, it would be great to extend it
2827	* beyond VT-x and/or nested-paging.
2828	*
2829	* @returns VBox status code.
2830	*
2831	* @param pDevIns The device instance @a hRegion is associated with.
2832	* @param hRegion The handle to the MMIO region.
2833	*/
2834	DECLR3CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2835	/** @} */
2836
2837	/**
2838	* Register a ROM (BIOS) region.
2839	*
2840	* It goes without saying that this is read-only memory. The memory region must be
2841	* in unassigned memory. I.e. from the top of the address space or on the PC in
2842	* the 0xa0000-0xfffff range.
2843	*
2844	* @returns VBox status.
2845	* @param pDevIns The device instance owning the ROM region.
2846	* @param GCPhysStart First physical address in the range.
2847	* Must be page aligned!
2848	* @param cbRange The size of the range (in bytes).
2849	* Must be page aligned!
2850	* @param pvBinary Pointer to the binary data backing the ROM image.
2851	* @param cbBinary The size of the binary pointer. This must
2852	* be equal or smaller than @a cbRange.
2853	* @param fFlags PGMPHYS_ROM_FLAGS_XXX (see pgm.h).
2854	* @param pszDesc Pointer to description string. This must not be freed.
2855	*
2856	* @remark There is no way to remove the rom, automatically on device cleanup or
2857	* manually from the device yet. At present I doubt we need such features...
2858	*/
2859	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2860	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2861
2862	/**
2863	* Changes the protection of shadowed ROM mapping.
2864	*
2865	* This is intented for use by the system BIOS, chipset or device in question to
2866	* change the protection of shadowed ROM code after init and on reset.
2867	*
2868	* @param pDevIns The device instance.
2869	* @param GCPhysStart Where the mapping starts.
2870	* @param cbRange The size of the mapping.
2871	* @param enmProt The new protection type.
2872	*/
2873	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2874
2875	/**
2876	* Register a save state data unit.
2877	*
2878	* @returns VBox status.
2879	* @param pDevIns The device instance.
2880	* @param uVersion Data layout version number.
2881	* @param cbGuess The approximate amount of data in the unit.
2882	* Only for progress indicators.
2883	* @param pszBefore Name of data unit which we should be put in
2884	* front of. Optional (NULL).
2885	*
2886	* @param pfnLivePrep Prepare live save callback, optional.
2887	* @param pfnLiveExec Execute live save callback, optional.
2888	* @param pfnLiveVote Vote live save callback, optional.
2889	*
2890	* @param pfnSavePrep Prepare save callback, optional.
2891	* @param pfnSaveExec Execute save callback, optional.
2892	* @param pfnSaveDone Done save callback, optional.
2893	*
2894	* @param pfnLoadPrep Prepare load callback, optional.
2895	* @param pfnLoadExec Execute load callback, optional.
2896	* @param pfnLoadDone Done load callback, optional.
2897	* @remarks Caller enters the device critical section prior to invoking the
2898	* registered callback methods.
2899	*/
2900	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2901	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2902	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2903	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2904
2905	/**
2906	* Register a save state data unit for backward compatibility.
2907	*
2908	* This is for migrating from an old device name to a new one or for merging
2909	* devices. It will only help loading old saved states.
2910	*
2911	* @returns VBox status.
2912	* @param pDevIns The device instance.
2913	* @param pszOldName The old unit name.
2914	* @param pfnLoadPrep Prepare load callback, optional.
2915	* @param pfnLoadExec Execute load callback, optional.
2916	* @param pfnLoadDone Done load callback, optional.
2917	* @remarks Caller enters the device critical section prior to invoking the
2918	* registered callback methods.
2919	*/
2920	DECLR3CALLBACKMEMBER(int, pfnSSMRegisterLegacy,(PPDMDEVINS pDevIns, const char *pszOldName, PFNSSMDEVLOADPREP pfnLoadPrep,
2921	PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2922
2923	/** @name Exported SSM Functions
2924	* @{ */
2925	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2926	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2927	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2928	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2929	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2930	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2931	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2932	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2933	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2934	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2935	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2936	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2937	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2938	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2939	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2940	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2941	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2942	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2943	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2944	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2945	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2946	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2947	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2948	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2949	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2950	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2951	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2952	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2953	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2954	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2955	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2956	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2957	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2958	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2959	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2960	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2961	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2962	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2963	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2964	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2965	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2966	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2967	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2968	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2969	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2970	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2971	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2972	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2973	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2974	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2975	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2976	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2977	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2978	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2979	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2980	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2981	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2982	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2983	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2984	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2985	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2986	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2987	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2988	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2989	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2990	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2991	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2992	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2993	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2994	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2995	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2996	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2997	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2998	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2999	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
3000	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
3001	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
3002	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
3003	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
3004	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
3005	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
3006	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
3007	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
3008	/** @} */
3009
3010	/**
3011	* Creates a timer w/ a cross context handle.
3012	*
3013	* @returns VBox status.
3014	* @param pDevIns The device instance.
3015	* @param enmClock The clock to use on this timer.
3016	* @param pfnCallback Callback function.
3017	* @param pvUser User argument for the callback.
3018	* @param fFlags Flags, see TMTIMER_FLAGS_*.
3019	* @param pszDesc Pointer to description string which must stay around
3020	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
3021	* @param phTimer Where to store the timer handle on success.
3022	* @remarks Caller enters the device critical section prior to invoking the
3023	* callback.
3024	*/
3025	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
3026	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
3027
3028	/** @name Timer handle method wrappers
3029	* @{ */
3030	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
3031	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
3032	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
3033	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3034	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3035	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3036	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3037	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3038	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
3039	/** Takes the clock lock then enters the specified critical section. */
3040	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
3041	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
3042	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
3043	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
3044	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
3045	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
3046	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
3047	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3048	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3049	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
3050	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
3051	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3052	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3053	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3054	/** @sa TMR3TimerSkip */
3055	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
3056	/** @} */
3057
3058	/**
3059	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
3060	*
3061	* @returns pTime.
3062	* @param pDevIns The device instance.
3063	* @param pTime Where to store the time.
3064	*/
3065	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
3066
3067	/** @name Exported CFGM Functions.
3068	* @{ */
3069	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
3070	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
3071	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
3072	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3073	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3074	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
3075	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
3076	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPassword,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
3077	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPasswordDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
3078	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
3079	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3080	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3081	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
3082	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
3083	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
3084	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
3085	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
3086	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
3087	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
3088	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
3089	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
3090	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
3091	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
3092	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
3093	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
3094	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
3095	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
3096	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
3097	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
3098	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
3099	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
3100	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
3101	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
3102	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
3103	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
3104	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
3105	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
3106	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
3107	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
3108	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
3109	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
3110	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
3111	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
3112	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
3113	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
3114	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
3115	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
3116	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
3117	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
3118	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
3119	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
3120	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
3121	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
3122	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
3123	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
3124	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
3125	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
3126	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
3127	const char pszValidValues, const char pszValidNodes,
3128	const char *pszWho, uint32_t uInstance));
3129	/** @} */
3130
3131	/**
3132	* Read physical memory.
3133	*
3134	* @returns VINF_SUCCESS (for now).
3135	* @param pDevIns The device instance.
3136	* @param GCPhys Physical address start reading from.
3137	* @param pvBuf Where to put the read bits.
3138	* @param cbRead How many bytes to read.
3139	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3140	* @thread Any thread, but the call may involve the emulation thread.
3141	*/
3142	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3143
3144	/**
3145	* Write to physical memory.
3146	*
3147	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3148	* @param pDevIns The device instance.
3149	* @param GCPhys Physical address to write to.
3150	* @param pvBuf What to write.
3151	* @param cbWrite How many bytes to write.
3152	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3153	* @thread Any thread, but the call may involve the emulation thread.
3154	*/
3155	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3156
3157	/**
3158	* Requests the mapping of a guest page into ring-3.
3159	*
3160	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3161	* release it.
3162	*
3163	* This API will assume your intention is to write to the page, and will
3164	* therefore replace shared and zero pages. If you do not intend to modify the
3165	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3166	*
3167	* @returns VBox status code.
3168	* @retval VINF_SUCCESS on success.
3169	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3170	* backing or if the page has any active access handlers. The caller
3171	* must fall back on using PGMR3PhysWriteExternal.
3172	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3173	*
3174	* @param pDevIns The device instance.
3175	* @param GCPhys The guest physical address of the page that
3176	* should be mapped.
3177	* @param fFlags Flags reserved for future use, MBZ.
3178	* @param ppv Where to store the address corresponding to
3179	* GCPhys.
3180	* @param pLock Where to store the lock information that
3181	* pfnPhysReleasePageMappingLock needs.
3182	*
3183	* @remark Avoid calling this API from within critical sections (other than the
3184	* PGM one) because of the deadlock risk when we have to delegating the
3185	* task to an EMT.
3186	* @thread Any.
3187	*/
3188	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3189	PPGMPAGEMAPLOCK pLock));
3190
3191	/**
3192	* Requests the mapping of a guest page into ring-3, external threads.
3193	*
3194	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3195	* release it.
3196	*
3197	* @returns VBox status code.
3198	* @retval VINF_SUCCESS on success.
3199	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3200	* backing or if the page as an active ALL access handler. The caller
3201	* must fall back on using PGMPhysRead.
3202	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3203	*
3204	* @param pDevIns The device instance.
3205	* @param GCPhys The guest physical address of the page that
3206	* should be mapped.
3207	* @param fFlags Flags reserved for future use, MBZ.
3208	* @param ppv Where to store the address corresponding to
3209	* GCPhys.
3210	* @param pLock Where to store the lock information that
3211	* pfnPhysReleasePageMappingLock needs.
3212	*
3213	* @remark Avoid calling this API from within critical sections.
3214	* @thread Any.
3215	*/
3216	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3217	void const **ppv, PPGMPAGEMAPLOCK pLock));
3218
3219	/**
3220	* Release the mapping of a guest page.
3221	*
3222	* This is the counter part of pfnPhysGCPhys2CCPtr and
3223	* pfnPhysGCPhys2CCPtrReadOnly.
3224	*
3225	* @param pDevIns The device instance.
3226	* @param pLock The lock structure initialized by the mapping
3227	* function.
3228	*/
3229	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3230
3231	/**
3232	* Read guest physical memory by virtual address.
3233	*
3234	* @param pDevIns The device instance.
3235	* @param pvDst Where to put the read bits.
3236	* @param GCVirtSrc Guest virtual address to start reading from.
3237	* @param cb How many bytes to read.
3238	* @thread The emulation thread.
3239	*/
3240	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3241
3242	/**
3243	* Write to guest physical memory by virtual address.
3244	*
3245	* @param pDevIns The device instance.
3246	* @param GCVirtDst Guest virtual address to write to.
3247	* @param pvSrc What to write.
3248	* @param cb How many bytes to write.
3249	* @thread The emulation thread.
3250	*/
3251	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3252
3253	/**
3254	* Convert a guest virtual address to a guest physical address.
3255	*
3256	* @returns VBox status code.
3257	* @param pDevIns The device instance.
3258	* @param GCPtr Guest virtual address.
3259	* @param pGCPhys Where to store the GC physical address
3260	* corresponding to GCPtr.
3261	* @thread The emulation thread.
3262	* @remark Careful with page boundaries.
3263	*/
3264	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3265
3266	/**
3267	* Checks if a GC physical address is a normal page,
3268	* i.e. not ROM, MMIO or reserved.
3269	*
3270	* @returns true if normal.
3271	* @returns false if invalid, ROM, MMIO or reserved page.
3272	* @param pDevIns The device instance.
3273	* @param GCPhys The physical address to check.
3274	*/
3275	DECLR3CALLBACKMEMBER(bool, pfnPhysIsGCPhysNormal,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
3276
3277	/**
3278	* Inflate or deflate a memory balloon
3279	*
3280	* @returns VBox status code.
3281	* @param pDevIns The device instance.
3282	* @param fInflate Inflate or deflate memory balloon
3283	* @param cPages Number of pages to free
3284	* @param paPhysPage Array of guest physical addresses
3285	*/
3286	DECLR3CALLBACKMEMBER(int, pfnPhysChangeMemBalloon,(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage));
3287
3288	/**
3289	* Allocate memory which is associated with current VM instance
3290	* and automatically freed on it's destruction.
3291	*
3292	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3293	* @param pDevIns The device instance.
3294	* @param cb Number of bytes to allocate.
3295	*/
3296	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3297
3298	/**
3299	* Allocate memory which is associated with current VM instance
3300	* and automatically freed on it's destruction. The memory is ZEROed.
3301	*
3302	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3303	* @param pDevIns The device instance.
3304	* @param cb Number of bytes to allocate.
3305	*/
3306	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3307
3308	/**
3309	* Allocating string printf.
3310	*
3311	* @returns Pointer to the string.
3312	* @param pDevIns The device instance.
3313	* @param enmTag The statistics tag.
3314	* @param pszFormat The format string.
3315	* @param va Format arguments.
3316	*/
3317	DECLR3CALLBACKMEMBER(char , pfnMMHeapAPrintfV,(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, va_list va));
3318
3319	/**
3320	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3321	*
3322	* @param pDevIns The device instance.
3323	* @param pv Pointer to the memory to free.
3324	*/
3325	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3326
3327	/**
3328	* Returns the physical RAM size of the VM.
3329	*
3330	* @returns RAM size in bytes.
3331	* @param pDevIns The device instance.
3332	*/
3333	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSize,(PPDMDEVINS pDevIns));
3334
3335	/**
3336	* Returns the physical RAM size of the VM below the 4GB boundary.
3337	*
3338	* @returns RAM size in bytes.
3339	* @param pDevIns The device instance.
3340	*/
3341	DECLR3CALLBACKMEMBER(uint32_t, pfnMMPhysGetRamSizeBelow4GB,(PPDMDEVINS pDevIns));
3342
3343	/**
3344	* Returns the physical RAM size of the VM above the 4GB boundary.
3345	*
3346	* @returns RAM size in bytes.
3347	* @param pDevIns The device instance.
3348	*/
3349	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSizeAbove4GB,(PPDMDEVINS pDevIns));
3350
3351	/**
3352	* Gets the VM state.
3353	*
3354	* @returns VM state.
3355	* @param pDevIns The device instance.
3356	* @thread Any thread (just keep in mind that it's volatile info).
3357	*/
3358	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3359
3360	/**
3361	* Checks if the VM was teleported and hasn't been fully resumed yet.
3362	*
3363	* @returns true / false.
3364	* @param pDevIns The device instance.
3365	* @thread Any thread.
3366	*/
3367	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3368
3369	/**
3370	* Set the VM error message
3371	*
3372	* @returns rc.
3373	* @param pDevIns The device instance.
3374	* @param rc VBox status code.
3375	* @param SRC_POS Use RT_SRC_POS.
3376	* @param pszFormat Error message format string.
3377	* @param va Error message arguments.
3378	*/
3379	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3380	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3381
3382	/**
3383	* Set the VM runtime error message
3384	*
3385	* @returns VBox status code.
3386	* @param pDevIns The device instance.
3387	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3388	* @param pszErrorId Error ID string.
3389	* @param pszFormat Error message format string.
3390	* @param va Error message arguments.
3391	*/
3392	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3393	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3394
3395	/**
3396	* Special interface for implementing a HLT-like port on a device.
3397	*
3398	* This can be called directly from device code, provide the device is trusted
3399	* to access the VMM directly. Since we may not have an accurate register set
3400	* and the caller certainly shouldn't (device code does not access CPU
3401	* registers), this function will return when interrupts are pending regardless
3402	* of the actual EFLAGS.IF state.
3403	*
3404	* @returns VBox error status (never informational statuses).
3405	* @param pDevIns The device instance.
3406	* @param idCpu The id of the calling EMT.
3407	*/
3408	DECLR3CALLBACKMEMBER(int, pfnVMWaitForDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3409
3410	/**
3411	* Wakes up a CPU that has called PDMDEVHLPR3::pfnVMWaitForDeviceReady.
3412	*
3413	* @returns VBox error status (never informational statuses).
3414	* @param pDevIns The device instance.
3415	* @param idCpu The id of the calling EMT.
3416	*/
3417	DECLR3CALLBACKMEMBER(int, pfnVMNotifyCpuDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3418
3419	/**
3420	* Convenience wrapper for VMR3ReqCallU.
3421	*
3422	* This assumes (1) you're calling a function that returns an VBox status code
3423	* and that you do not wish to wait for it to complete.
3424	*
3425	* @returns VBox status code returned by VMR3ReqCallVU.
3426	*
3427	* @param pDevIns The device instance.
3428	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3429	* one of the following special values:
3430	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3431	* @param pfnFunction Pointer to the function to call.
3432	* @param cArgs Number of arguments following in the ellipsis.
3433	* @param Args Argument vector.
3434	*
3435	* @remarks See remarks on VMR3ReqCallVU.
3436	*/
3437	DECLR3CALLBACKMEMBER(int, pfnVMReqCallNoWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3438
3439	/**
3440	* Convenience wrapper for VMR3ReqCallU.
3441	*
3442	* This assumes (1) you're calling a function that returns void, (2) that you
3443	* wish to wait for ever for it to return, and (3) that it's priority request
3444	* that can be safely be handled during async suspend and power off.
3445	*
3446	* @returns VBox status code of VMR3ReqCallVU.
3447	*
3448	* @param pDevIns The device instance.
3449	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3450	* one of the following special values:
3451	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3452	* @param pfnFunction Pointer to the function to call.
3453	* @param cArgs Number of arguments following in the ellipsis.
3454	* @param Args Argument vector.
3455	*
3456	* @remarks See remarks on VMR3ReqCallVU.
3457	*/
3458	DECLR3CALLBACKMEMBER(int, pfnVMReqPriorityCallWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3459
3460	/**
3461	* Stops the VM and enters the debugger to look at the guest state.
3462	*
3463	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3464	* invoking this function directly.
3465	*
3466	* @returns VBox status code which must be passed up to the VMM.
3467	* @param pDevIns The device instance.
3468	* @param pszFile Filename of the assertion location.
3469	* @param iLine The linenumber of the assertion location.
3470	* @param pszFunction Function of the assertion location.
3471	* @param pszFormat Message. (optional)
3472	* @param args Message parameters.
3473	*/
3474	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3475	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3476
3477	/**
3478	* Register a info handler with DBGF.
3479	*
3480	* @returns VBox status code.
3481	* @param pDevIns The device instance.
3482	* @param pszName The identifier of the info.
3483	* @param pszDesc The description of the info and any arguments
3484	* the handler may take.
3485	* @param pfnHandler The handler function to be called to display the
3486	* info.
3487	*/
3488	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3489
3490	/**
3491	* Register a info handler with DBGF, argv style.
3492	*
3493	* @returns VBox status code.
3494	* @param pDevIns The device instance.
3495	* @param pszName The identifier of the info.
3496	* @param pszDesc The description of the info and any arguments
3497	* the handler may take.
3498	* @param pfnHandler The handler function to be called to display the
3499	* info.
3500	*/
3501	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3502
3503	/**
3504	* Registers a set of registers for a device.
3505	*
3506	* The @a pvUser argument of the getter and setter callbacks will be
3507	* @a pDevIns. The register names will be prefixed by the device name followed
3508	* immediately by the instance number.
3509	*
3510	* @returns VBox status code.
3511	* @param pDevIns The device instance.
3512	* @param paRegisters The register descriptors.
3513	*
3514	* @remarks The device critical section is NOT entered prior to working the
3515	* callbacks registered via this helper!
3516	*/
3517	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3518
3519	/**
3520	* Gets the trace buffer handle.
3521	*
3522	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3523	* really inteded for direct usage, thus no inline wrapper function.
3524	*
3525	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3526	* @param pDevIns The device instance.
3527	*/
3528	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3529
3530	/**
3531	* Report a bug check.
3532	*
3533	* @returns
3534	* @param pDevIns The device instance.
3535	* @param enmEvent The kind of BSOD event this is.
3536	* @param uBugCheck The bug check number.
3537	* @param uP1 The bug check parameter \#1.
3538	* @param uP2 The bug check parameter \#2.
3539	* @param uP3 The bug check parameter \#3.
3540	* @param uP4 The bug check parameter \#4.
3541	*
3542	* @thread EMT
3543	*/
3544	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnDBGFReportBugCheck,(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
3545	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4));
3546
3547	/**
3548	* Write core dump of the guest.
3549	*
3550	* @returns VBox status code.
3551	* @param pDevIns The device instance.
3552	* @param pszFilename The name of the file to which the guest core
3553	* dump should be written.
3554	* @param fReplaceFile Whether to replace the file or not.
3555	*
3556	* @remarks The VM may need to be suspended before calling this function in
3557	* order to truly stop all device threads and drivers. This function
3558	* only synchronizes EMTs.
3559	*/
3560	DECLR3CALLBACKMEMBER(int, pfnDBGFCoreWrite,(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile));
3561
3562	/**
3563	* Gets the logger info helper.
3564	* The returned info helper will unconditionally write all output to the log.
3565	*
3566	* @returns Pointer to the logger info helper.
3567	* @param pDevIns The device instance.
3568	*/
3569	DECLR3CALLBACKMEMBER(PCDBGFINFOHLP, pfnDBGFInfoLogHlp,(PPDMDEVINS pDevIns));
3570
3571	/**
3572	* Queries a 64-bit register value.
3573	*
3574	* @retval VINF_SUCCESS
3575	* @retval VERR_INVALID_VM_HANDLE
3576	* @retval VERR_INVALID_CPU_ID
3577	* @retval VERR_DBGF_REGISTER_NOT_FOUND
3578	* @retval VERR_DBGF_UNSUPPORTED_CAST
3579	* @retval VINF_DBGF_TRUNCATED_REGISTER
3580	* @retval VINF_DBGF_ZERO_EXTENDED_REGISTER
3581	*
3582	* @param pDevIns The device instance.
3583	* @param idDefCpu The default target CPU ID, VMCPUID_ANY if not
3584	* applicable. Can be OR'ed with
3585	* DBGFREG_HYPER_VMCPUID.
3586	* @param pszReg The register that's being queried. Except for
3587	* CPU registers, this must be on the form
3588	* "set.reg[.sub]".
3589	* @param pu64 Where to store the register value.
3590	*/
3591	DECLR3CALLBACKMEMBER(int, pfnDBGFRegNmQueryU64,(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64));
3592
3593	/**
3594	* Format a set of registers.
3595	*
3596	* This is restricted to registers from one CPU, that specified by @a idCpu.
3597	*
3598	* @returns VBox status code.
3599	* @param pDevIns The device instance.
3600	* @param idCpu The CPU ID of any CPU registers that may be
3601	* printed, pass VMCPUID_ANY if not applicable.
3602	* @param pszBuf The output buffer.
3603	* @param cbBuf The size of the output buffer.
3604	* @param pszFormat The format string. Register names are given by
3605	* %VR{name}, they take no arguments.
3606	* @param va Other format arguments.
3607	*/
3608	DECLR3CALLBACKMEMBER(int, pfnDBGFRegPrintfV,(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
3609	const char *pszFormat, va_list va));
3610
3611	/**
3612	* Registers a statistics sample.
3613	*
3614	* @param pDevIns Device instance of the DMA.
3615	* @param pvSample Pointer to the sample.
3616	* @param enmType Sample type. This indicates what pvSample is
3617	* pointing at.
3618	* @param pszName Sample name, unix path style. If this does not
3619	* start with a '/', the default prefix will be
3620	* prepended, otherwise it will be used as-is.
3621	* @param enmUnit Sample unit.
3622	* @param pszDesc Sample description.
3623	*/
3624	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3625
3626	/**
3627	* Same as pfnSTAMRegister except that the name is specified in a
3628	* RTStrPrintfV like fashion.
3629	*
3630	* @param pDevIns Device instance of the DMA.
3631	* @param pvSample Pointer to the sample.
3632	* @param enmType Sample type. This indicates what pvSample is
3633	* pointing at.
3634	* @param enmVisibility Visibility type specifying whether unused
3635	* statistics should be visible or not.
3636	* @param enmUnit Sample unit.
3637	* @param pszDesc Sample description.
3638	* @param pszName Sample name format string, unix path style. If
3639	* this does not start with a '/', the default
3640	* prefix will be prepended, otherwise it will be
3641	* used as-is.
3642	* @param args Arguments to the format string.
3643	*/
3644	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3645	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3646	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3647
3648	/**
3649	* Registers a PCI device with the default PCI bus.
3650	*
3651	* If a PDM device has more than one PCI device, they must be registered in the
3652	* order of PDMDEVINSR3::apPciDevs.
3653	*
3654	* @returns VBox status code.
3655	* @param pDevIns The device instance.
3656	* @param pPciDev The PCI device structure.
3657	* This must be kept in the instance data.
3658	* The PCI configuration must be initialized before registration.
3659	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3660	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3661	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3662	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3663	* device number (0-31). This will be ignored if
3664	* the CFGM configuration contains a PCIDeviceNo
3665	* value.
3666	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3667	* function number (0-7). This will be ignored if
3668	* the CFGM configuration contains a PCIFunctionNo
3669	* value.
3670	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3671	* The pointer is saved, so don't free or changed.
3672	* @note The PCI device configuration is now implicit from the apPciDevs
3673	* index, meaning that the zero'th entry is the primary one and
3674	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3675	*/
3676	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3677	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3678
3679	/**
3680	* Initialize MSI or MSI-X emulation support for the given PCI device.
3681	*
3682	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3683	*
3684	* @returns VBox status code.
3685	* @param pDevIns The device instance.
3686	* @param pPciDev The PCI device. NULL is an alias for the first
3687	* one registered.
3688	* @param pMsiReg MSI emulation registration structure.
3689	*/
3690	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3691
3692	/**
3693	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3694	*
3695	* @returns VBox status code.
3696	* @param pDevIns The device instance.
3697	* @param pPciDev The PCI device structure. If NULL the default
3698	* PCI device for this device instance is used.
3699	* @param iRegion The region number.
3700	* @param cbRegion Size of the region.
3701	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3702	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3703	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3704	* @a fFlags, UINT64_MAX if no handle is passed
3705	* (old style).
3706	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3707	* handle is specified. The callback will be
3708	* invoked holding only the PDM lock. The device
3709	* lock will _not_ be taken (due to lock order).
3710	*/
3711	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3712	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3713	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3714
3715	/**
3716	* Register PCI configuration space read/write callbacks.
3717	*
3718	* @returns VBox status code.
3719	* @param pDevIns The device instance.
3720	* @param pPciDev The PCI device structure. If NULL the default
3721	* PCI device for this device instance is used.
3722	* @param pfnRead Pointer to the user defined PCI config read function.
3723	* to call default PCI config read function. Can be NULL.
3724	* @param pfnWrite Pointer to the user defined PCI config write function.
3725	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3726	* is NOT take because that is very likely be a lock order violation.
3727	* @thread EMT(0)
3728	* @note Only callable during VM creation.
3729	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3730	*/
3731	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3732	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3733
3734	/**
3735	* Perform a PCI configuration space write.
3736	*
3737	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3738	*
3739	* @returns Strict VBox status code (mainly DBGFSTOP).
3740	* @param pDevIns The device instance.
3741	* @param pPciDev The PCI device which config space is being read.
3742	* @param uAddress The config space address.
3743	* @param cb The size of the read: 1, 2 or 4 bytes.
3744	* @param u32Value The value to write.
3745	*/
3746	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3747	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3748
3749	/**
3750	* Perform a PCI configuration space read.
3751	*
3752	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3753	*
3754	* @returns Strict VBox status code (mainly DBGFSTOP).
3755	* @param pDevIns The device instance.
3756	* @param pPciDev The PCI device which config space is being read.
3757	* @param uAddress The config space address.
3758	* @param cb The size of the read: 1, 2 or 4 bytes.
3759	* @param pu32Value Where to return the value.
3760	*/
3761	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3762	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3763
3764	/**
3765	* Bus master physical memory read.
3766	*
3767	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3768	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3769	* @param pDevIns The device instance.
3770	* @param pPciDev The PCI device structure. If NULL the default
3771	* PCI device for this device instance is used.
3772	* @param GCPhys Physical address start reading from.
3773	* @param pvBuf Where to put the read bits.
3774	* @param cbRead How many bytes to read.
3775	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3776	* @thread Any thread, but the call may involve the emulation thread.
3777	*/
3778	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3779
3780	/**
3781	* Bus master physical memory write.
3782	*
3783	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3784	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3785	* @param pDevIns The device instance.
3786	* @param pPciDev The PCI device structure. If NULL the default
3787	* PCI device for this device instance is used.
3788	* @param GCPhys Physical address to write to.
3789	* @param pvBuf What to write.
3790	* @param cbWrite How many bytes to write.
3791	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3792	* @thread Any thread, but the call may involve the emulation thread.
3793	*/
3794	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3795
3796	/**
3797	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3798	* physical memory write operation.
3799	*
3800	* Refer pfnPhysGCPhys2CCPtr() for further details.
3801	*
3802	* @returns VBox status code.
3803	* @param pDevIns The device instance.
3804	* @param pPciDev The PCI device structure. If NULL the default
3805	* PCI device for this device instance is used.
3806	* @param GCPhys The guest physical address of the page that should be
3807	* mapped.
3808	* @param fFlags Flags reserved for future use, MBZ.
3809	* @param ppv Where to store the address corresponding to GCPhys.
3810	* @param pLock Where to store the lock information that
3811	* pfnPhysReleasePageMappingLock needs.
3812	*
3813	* @remarks Avoid calling this API from within critical sections (other than the PGM
3814	* one) because of the deadlock risk when we have to delegating the task to
3815	* an EMT.
3816	* @thread Any.
3817	*/
3818	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3819	void **ppv, PPGMPAGEMAPLOCK pLock));
3820
3821	/**
3822	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3823	* for a bus master physical memory read operation.
3824	*
3825	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3826	*
3827	* @returns VBox status code.
3828	* @param pDevIns The device instance.
3829	* @param pPciDev The PCI device structure. If NULL the default
3830	* PCI device for this device instance is used.
3831	* @param GCPhys The guest physical address of the page that
3832	* should be mapped.
3833	* @param fFlags Flags reserved for future use, MBZ.
3834	* @param ppv Where to store the address corresponding to
3835	* GCPhys.
3836	* @param pLock Where to store the lock information that
3837	* pfnPhysReleasePageMappingLock needs.
3838	*
3839	* @remarks Avoid calling this API from within critical sections.
3840	* @thread Any.
3841	*/
3842	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3843	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3844
3845	/**
3846	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3847	* master physical memory write operation.
3848	*
3849	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3850	* ASAP to release them.
3851	*
3852	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3853	*
3854	* @returns VBox status code.
3855	* @param pDevIns The device instance.
3856	* @param pPciDev The PCI device structure. If NULL the default
3857	* PCI device for this device instance is used.
3858	* @param cPages Number of pages to lock.
3859	* @param paGCPhysPages The guest physical address of the pages that
3860	* should be mapped (@a cPages entries).
3861	* @param fFlags Flags reserved for future use, MBZ.
3862	* @param papvPages Where to store the ring-3 mapping addresses
3863	* corresponding to @a paGCPhysPages.
3864	* @param paLocks Where to store the locking information that
3865	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3866	* in length).
3867	*/
3868	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3869	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3870	PPGMPAGEMAPLOCK paLocks));
3871
3872	/**
3873	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3874	* master physical memory read operation.
3875	*
3876	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3877	* ASAP to release them.
3878	*
3879	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3880	*
3881	* @returns VBox status code.
3882	* @param pDevIns The device instance.
3883	* @param pPciDev The PCI device structure. If NULL the default
3884	* PCI device for this device instance is used.
3885	* @param cPages Number of pages to lock.
3886	* @param paGCPhysPages The guest physical address of the pages that
3887	* should be mapped (@a cPages entries).
3888	* @param fFlags Flags reserved for future use, MBZ.
3889	* @param papvPages Where to store the ring-3 mapping addresses
3890	* corresponding to @a paGCPhysPages.
3891	* @param paLocks Where to store the lock information that
3892	* pfnPhysReleasePageMappingLock needs (@a cPages
3893	* in length).
3894	*/
3895	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3896	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3897	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3898
3899	/**
3900	* Sets the IRQ for the given PCI device.
3901	*
3902	* @param pDevIns The device instance.
3903	* @param pPciDev The PCI device structure. If NULL the default
3904	* PCI device for this device instance is used.
3905	* @param iIrq IRQ number to set.
3906	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3907	* @thread Any thread, but will involve the emulation thread.
3908	*/
3909	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3910
3911	/**
3912	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3913	* the request when not called from EMT.
3914	*
3915	* @param pDevIns The device instance.
3916	* @param pPciDev The PCI device structure. If NULL the default
3917	* PCI device for this device instance is used.
3918	* @param iIrq IRQ number to set.
3919	* @param iLevel IRQ level.
3920	* @thread Any thread, but will involve the emulation thread.
3921	*/
3922	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3923
3924	/**
3925	* Set ISA IRQ for a device.
3926	*
3927	* @param pDevIns The device instance.
3928	* @param iIrq IRQ number to set.
3929	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3930	* @thread Any thread, but will involve the emulation thread.
3931	*/
3932	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3933
3934	/**
3935	* Set the ISA IRQ for a device, but don't wait for EMT to process
3936	* the request when not called from EMT.
3937	*
3938	* @param pDevIns The device instance.
3939	* @param iIrq IRQ number to set.
3940	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3941	* @thread Any thread, but will involve the emulation thread.
3942	*/
3943	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3944
3945	/**
3946	* Attaches a driver (chain) to the device.
3947	*
3948	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3949	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3950	*
3951	* @returns VBox status code.
3952	* @param pDevIns The device instance.
3953	* @param iLun The logical unit to attach.
3954	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3955	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3956	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3957	* for the live of the device instance.
3958	*/
3959	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3960	PPDMIBASE ppBaseInterface, const char pszDesc));
3961
3962	/**
3963	* Detaches an attached driver (chain) from the device again.
3964	*
3965	* @returns VBox status code.
3966	* @param pDevIns The device instance.
3967	* @param pDrvIns The driver instance to detach.
3968	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3969	*/
3970	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3971
3972	/**
3973	* Reconfigures the driver chain for a LUN, detaching any driver currently
3974	* present there.
3975	*
3976	* Caller will have attach it, of course.
3977	*
3978	* @returns VBox status code.
3979	* @param pDevIns The device instance.
3980	* @param iLun The logical unit to reconfigure.
3981	* @param cDepth The depth of the driver chain. Determins the
3982	* size of @a papszDrivers and @a papConfigs.
3983	* @param papszDrivers The names of the drivers to configure in the
3984	* chain, first entry is the one immediately
3985	* below the device/LUN
3986	* @param papConfigs The configurations for each of the drivers
3987	* in @a papszDrivers array. NULL entries
3988	* corresponds to empty 'Config' nodes. This
3989	* function will take ownership of non-NULL
3990	* CFGM sub-trees and set the array member to
3991	* NULL, so the caller can do cleanups on
3992	* failure. This parameter is optional.
3993	* @param fFlags Reserved, MBZ.
3994	*/
3995	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3996	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3997
3998	/** @name Exported PDM Queue Functions
3999	* @{ */
4000	/**
4001	* Create a queue.
4002	*
4003	* @returns VBox status code.
4004	* @param pDevIns The device instance.
4005	* @param cbItem The size of a queue item.
4006	* @param cItems The number of items in the queue.
4007	* @param cMilliesInterval The number of milliseconds between polling the queue.
4008	* If 0 then the emulation thread will be notified whenever an item arrives.
4009	* @param pfnCallback The consumer function.
4010	* @param fRZEnabled Set if the queue should work in RC and R0.
4011	* @param pszName The queue base name. The instance number will be
4012	* appended automatically.
4013	* @param phQueue Where to store the queue handle on success.
4014	* @thread EMT(0)
4015	* @remarks The device critical section will NOT be entered before calling the
4016	* callback. No locks will be held, but for now it's safe to assume
4017	* that only one EMT will do queue callbacks at any one time.
4018	*/
4019	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
4020	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
4021	PDMQUEUEHANDLE *phQueue));
4022
4023	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
4024	DECLR3CALLBACKMEMBER(int, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
4025	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
4026	/** @} */
4027
4028	/** @name PDM Task
4029	* @{ */
4030	/**
4031	* Create an asynchronous ring-3 task.
4032	*
4033	* @returns VBox status code.
4034	* @param pDevIns The device instance.
4035	* @param fFlags PDMTASK_F_XXX
4036	* @param pszName The function name or similar. Used for statistics,
4037	* so no slashes.
4038	* @param pfnCallback The task function.
4039	* @param pvUser User argument for the task function.
4040	* @param phTask Where to return the task handle.
4041	* @thread EMT(0)
4042	*/
4043	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
4044	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
4045	/**
4046	* Triggers the running the given task.
4047	*
4048	* @returns VBox status code.
4049	* @retval VINF_ALREADY_POSTED is the task is already pending.
4050	* @param pDevIns The device instance.
4051	* @param hTask The task to trigger.
4052	* @thread Any thread.
4053	*/
4054	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
4055	/** @} */
4056
4057	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
4058	* These semaphores can be signalled from ring-0.
4059	* @{ */
4060	/** @sa SUPSemEventCreate */
4061	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
4062	/** @sa SUPSemEventClose */
4063	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
4064	/** @sa SUPSemEventSignal */
4065	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
4066	/** @sa SUPSemEventWaitNoResume */
4067	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
4068	/** @sa SUPSemEventWaitNsAbsIntr */
4069	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
4070	/** @sa SUPSemEventWaitNsRelIntr */
4071	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
4072	/** @sa SUPSemEventGetResolution */
4073	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
4074	/** @} */
4075
4076	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
4077	* These semaphores can be signalled from ring-0.
4078	* @{ */
4079	/** @sa SUPSemEventMultiCreate */
4080	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
4081	/** @sa SUPSemEventMultiClose */
4082	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4083	/** @sa SUPSemEventMultiSignal */
4084	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4085	/** @sa SUPSemEventMultiReset */
4086	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4087	/** @sa SUPSemEventMultiWaitNoResume */
4088	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
4089	/** @sa SUPSemEventMultiWaitNsAbsIntr */
4090	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
4091	/** @sa SUPSemEventMultiWaitNsRelIntr */
4092	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
4093	/** @sa SUPSemEventMultiGetResolution */
4094	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
4095	/** @} */
4096
4097	/**
4098	* Initializes a PDM critical section.
4099	*
4100	* The PDM critical sections are derived from the IPRT critical sections, but
4101	* works in RC and R0 as well.
4102	*
4103	* @returns VBox status code.
4104	* @param pDevIns The device instance.
4105	* @param pCritSect Pointer to the critical section.
4106	* @param SRC_POS Use RT_SRC_POS.
4107	* @param pszNameFmt Format string for naming the critical section.
4108	* For statistics and lock validation.
4109	* @param va Arguments for the format string.
4110	*/
4111	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
4112	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4113
4114	/**
4115	* Gets the NOP critical section.
4116	*
4117	* @returns The ring-3 address of the NOP critical section.
4118	* @param pDevIns The device instance.
4119	*/
4120	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4121
4122	/**
4123	* Changes the device level critical section from the automatically created
4124	* default to one desired by the device constructor.
4125	*
4126	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
4127	* the additional contexts.
4128	*
4129	* @returns VBox status code.
4130	* @param pDevIns The device instance.
4131	* @param pCritSect The critical section to use. NULL is not
4132	* valid, instead use the NOP critical
4133	* section.
4134	*/
4135	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4136
4137	/** @name Exported PDM Critical Section Functions
4138	* @{ */
4139	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4140	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4141	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4142	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4143	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4144	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4145	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4146	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4147	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4148	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4149	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
4150	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4151	/** @} */
4152
4153	/** @name Exported PDM Read/Write Critical Section Functions
4154	* @{ */
4155	DECLR3CALLBACKMEMBER(int, pfnCritSectRwInit,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
4156	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4157	DECLR3CALLBACKMEMBER(int, pfnCritSectRwDelete,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4158
4159	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4160	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4161	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4162	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4163	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4164
4165	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4166	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4167	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4168	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4169	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4170
4171	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4172	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
4173	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4174	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4175	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4176	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4177	/** @} */
4178
4179	/**
4180	* Creates a PDM thread.
4181	*
4182	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
4183	* resuming, and destroying the thread as the VM state changes.
4184	*
4185	* @returns VBox status code.
4186	* @param pDevIns The device instance.
4187	* @param ppThread Where to store the thread 'handle'.
4188	* @param pvUser The user argument to the thread function.
4189	* @param pfnThread The thread function.
4190	* @param pfnWakeup The wakup callback. This is called on the EMT
4191	* thread when a state change is pending.
4192	* @param cbStack See RTThreadCreate.
4193	* @param enmType See RTThreadCreate.
4194	* @param pszName See RTThreadCreate.
4195	* @remarks The device critical section will NOT be entered prior to invoking
4196	* the function pointers.
4197	*/
4198	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
4199	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
4200
4201	/** @name Exported PDM Thread Functions
4202	* @{ */
4203	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
4204	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
4205	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
4206	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
4207	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
4208	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
4209	/** @} */
4210
4211	/**
4212	* Set up asynchronous handling of a suspend, reset or power off notification.
4213	*
4214	* This shall only be called when getting the notification. It must be called
4215	* for each one.
4216	*
4217	* @returns VBox status code.
4218	* @param pDevIns The device instance.
4219	* @param pfnAsyncNotify The callback.
4220	* @thread EMT(0)
4221	* @remarks The caller will enter the device critical section prior to invoking
4222	* the callback.
4223	*/
4224	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
4225
4226	/**
4227	* Notify EMT(0) that the device has completed the asynchronous notification
4228	* handling.
4229	*
4230	* This can be called at any time, spurious calls will simply be ignored.
4231	*
4232	* @param pDevIns The device instance.
4233	* @thread Any
4234	*/
4235	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
4236
4237	/**
4238	* Register the RTC device.
4239	*
4240	* @returns VBox status code.
4241	* @param pDevIns The device instance.
4242	* @param pRtcReg Pointer to a RTC registration structure.
4243	* @param ppRtcHlp Where to store the pointer to the helper
4244	* functions.
4245	*/
4246	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
4247
4248	/**
4249	* Register a PCI Bus.
4250	*
4251	* @returns VBox status code, but the positive values 0..31 are used to indicate
4252	* bus number rather than informational status codes.
4253	* @param pDevIns The device instance.
4254	* @param pPciBusReg Pointer to PCI bus registration structure.
4255	* @param ppPciHlp Where to store the pointer to the PCI Bus
4256	* helpers.
4257	* @param piBus Where to return the PDM bus number. Optional.
4258	*/
4259	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
4260	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
4261
4262	/**
4263	* Register the IOMMU device.
4264	*
4265	* @returns VBox status code.
4266	* @param pDevIns The device instance.
4267	* @param pIommuReg Pointer to a IOMMU registration structure.
4268	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
4269	* helpers.
4270	* @param pidxIommu Where to return the IOMMU index. Optional.
4271	*/
4272	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
4273	uint32_t *pidxIommu));
4274
4275	/**
4276	* Register the PIC device.
4277	*
4278	* @returns VBox status code.
4279	* @param pDevIns The device instance.
4280	* @param pPicReg Pointer to a PIC registration structure.
4281	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
4282	* helpers.
4283	* @sa PDMDevHlpPICSetUpContext
4284	*/
4285	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4286
4287	/**
4288	* Register the APIC device.
4289	*
4290	* @returns VBox status code.
4291	* @param pDevIns The device instance.
4292	*/
4293	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
4294
4295	/**
4296	* Register the I/O APIC device.
4297	*
4298	* @returns VBox status code.
4299	* @param pDevIns The device instance.
4300	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4301	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
4302	* helpers.
4303	*/
4304	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4305
4306	/**
4307	* Register the HPET device.
4308	*
4309	* @returns VBox status code.
4310	* @param pDevIns The device instance.
4311	* @param pHpetReg Pointer to a HPET registration structure.
4312	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4313	* helpers.
4314	*/
4315	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4316
4317	/**
4318	* Register a raw PCI device.
4319	*
4320	* @returns VBox status code.
4321	* @param pDevIns The device instance.
4322	* @param pPciRawReg Pointer to a raw PCI registration structure.
4323	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4324	* device helpers.
4325	*/
4326	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4327
4328	/**
4329	* Register the DMA device.
4330	*
4331	* @returns VBox status code.
4332	* @param pDevIns The device instance.
4333	* @param pDmacReg Pointer to a DMAC registration structure.
4334	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4335	*/
4336	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4337
4338	/**
4339	* Register transfer function for DMA channel.
4340	*
4341	* @returns VBox status code.
4342	* @param pDevIns The device instance.
4343	* @param uChannel Channel number.
4344	* @param pfnTransferHandler Device specific transfer callback function.
4345	* @param pvUser User pointer to pass to the callback.
4346	* @thread EMT
4347	*/
4348	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4349
4350	/**
4351	* Read memory.
4352	*
4353	* @returns VBox status code.
4354	* @param pDevIns The device instance.
4355	* @param uChannel Channel number.
4356	* @param pvBuffer Pointer to target buffer.
4357	* @param off DMA position.
4358	* @param cbBlock Block size.
4359	* @param pcbRead Where to store the number of bytes which was
4360	* read. optional.
4361	* @thread EMT
4362	*/
4363	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4364
4365	/**
4366	* Write memory.
4367	*
4368	* @returns VBox status code.
4369	* @param pDevIns The device instance.
4370	* @param uChannel Channel number.
4371	* @param pvBuffer Memory to write.
4372	* @param off DMA position.
4373	* @param cbBlock Block size.
4374	* @param pcbWritten Where to store the number of bytes which was
4375	* written. optional.
4376	* @thread EMT
4377	*/
4378	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4379
4380	/**
4381	* Set the DREQ line.
4382	*
4383	* @returns VBox status code.
4384	* @param pDevIns Device instance.
4385	* @param uChannel Channel number.
4386	* @param uLevel Level of the line.
4387	* @thread EMT
4388	*/
4389	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4390
4391	/**
4392	* Get channel mode.
4393	*
4394	* @returns Channel mode. See specs.
4395	* @param pDevIns The device instance.
4396	* @param uChannel Channel number.
4397	* @thread EMT
4398	*/
4399	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4400
4401	/**
4402	* Schedule DMA execution.
4403	*
4404	* @param pDevIns The device instance.
4405	* @thread Any thread.
4406	*/
4407	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4408
4409	/**
4410	* Write CMOS value and update the checksum(s).
4411	*
4412	* @returns VBox status code.
4413	* @param pDevIns The device instance.
4414	* @param iReg The CMOS register index.
4415	* @param u8Value The CMOS register value.
4416	* @thread EMT
4417	*/
4418	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4419
4420	/**
4421	* Read CMOS value.
4422	*
4423	* @returns VBox status code.
4424	* @param pDevIns The device instance.
4425	* @param iReg The CMOS register index.
4426	* @param pu8Value Where to store the CMOS register value.
4427	* @thread EMT
4428	*/
4429	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4430
4431	/**
4432	* Assert that the current thread is the emulation thread.
4433	*
4434	* @returns True if correct.
4435	* @returns False if wrong.
4436	* @param pDevIns The device instance.
4437	* @param pszFile Filename of the assertion location.
4438	* @param iLine The linenumber of the assertion location.
4439	* @param pszFunction Function of the assertion location.
4440	*/
4441	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4442
4443	/**
4444	* Assert that the current thread is NOT the emulation thread.
4445	*
4446	* @returns True if correct.
4447	* @returns False if wrong.
4448	* @param pDevIns The device instance.
4449	* @param pszFile Filename of the assertion location.
4450	* @param iLine The linenumber of the assertion location.
4451	* @param pszFunction Function of the assertion location.
4452	*/
4453	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4454
4455	/**
4456	* Resolves the symbol for a raw-mode context interface.
4457	*
4458	* @returns VBox status code.
4459	* @param pDevIns The device instance.
4460	* @param pvInterface The interface structure.
4461	* @param cbInterface The size of the interface structure.
4462	* @param pszSymPrefix What to prefix the symbols in the list with
4463	* before resolving them. This must start with
4464	* 'dev' and contain the driver name.
4465	* @param pszSymList List of symbols corresponding to the interface.
4466	* There is generally a there is generally a define
4467	* holding this list associated with the interface
4468	* definition (INTERFACE_SYM_LIST). For more
4469	* details see PDMR3LdrGetInterfaceSymbols.
4470	* @thread EMT
4471	*/
4472	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4473	const char pszSymPrefix, const char pszSymList));
4474
4475	/**
4476	* Resolves the symbol for a ring-0 context interface.
4477	*
4478	* @returns VBox status code.
4479	* @param pDevIns The device instance.
4480	* @param pvInterface The interface structure.
4481	* @param cbInterface The size of the interface structure.
4482	* @param pszSymPrefix What to prefix the symbols in the list with
4483	* before resolving them. This must start with
4484	* 'dev' and contain the driver name.
4485	* @param pszSymList List of symbols corresponding to the interface.
4486	* There is generally a there is generally a define
4487	* holding this list associated with the interface
4488	* definition (INTERFACE_SYM_LIST). For more
4489	* details see PDMR3LdrGetInterfaceSymbols.
4490	* @thread EMT
4491	*/
4492	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4493	const char pszSymPrefix, const char pszSymList));
4494
4495	/**
4496	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4497	*
4498	* @returns VBox status code.
4499	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4500	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4501	*
4502	* @param pDevIns The device instance.
4503	* @param uOperation The operation to perform.
4504	* @param u64Arg 64-bit integer argument.
4505	* @thread EMT
4506	*/
4507	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4508
4509	/**
4510	* Gets the reason for the most recent VM suspend.
4511	*
4512	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4513	* suspend has been made or if the pDevIns is invalid.
4514	* @param pDevIns The device instance.
4515	*/
4516	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4517
4518	/**
4519	* Gets the reason for the most recent VM resume.
4520	*
4521	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4522	* resume has been made or if the pDevIns is invalid.
4523	* @param pDevIns The device instance.
4524	*/
4525	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4526
4527	/**
4528	* Requests the mapping of multiple guest page into ring-3.
4529	*
4530	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4531	* ASAP to release them.
4532	*
4533	* This API will assume your intention is to write to the pages, and will
4534	* therefore replace shared and zero pages. If you do not intend to modify the
4535	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4536	*
4537	* @returns VBox status code.
4538	* @retval VINF_SUCCESS on success.
4539	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4540	* backing or if any of the pages the page has any active access
4541	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4542	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4543	* an invalid physical address.
4544	*
4545	* @param pDevIns The device instance.
4546	* @param cPages Number of pages to lock.
4547	* @param paGCPhysPages The guest physical address of the pages that
4548	* should be mapped (@a cPages entries).
4549	* @param fFlags Flags reserved for future use, MBZ.
4550	* @param papvPages Where to store the ring-3 mapping addresses
4551	* corresponding to @a paGCPhysPages.
4552	* @param paLocks Where to store the locking information that
4553	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4554	* in length).
4555	*
4556	* @remark Avoid calling this API from within critical sections (other than the
4557	* PGM one) because of the deadlock risk when we have to delegating the
4558	* task to an EMT.
4559	* @thread Any.
4560	* @since 6.0.6
4561	*/
4562	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4563	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4564
4565	/**
4566	* Requests the mapping of multiple guest page into ring-3, for reading only.
4567	*
4568	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4569	* ASAP to release them.
4570	*
4571	* @returns VBox status code.
4572	* @retval VINF_SUCCESS on success.
4573	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4574	* backing or if any of the pages the page has an active ALL access
4575	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4576	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4577	* an invalid physical address.
4578	*
4579	* @param pDevIns The device instance.
4580	* @param cPages Number of pages to lock.
4581	* @param paGCPhysPages The guest physical address of the pages that
4582	* should be mapped (@a cPages entries).
4583	* @param fFlags Flags reserved for future use, MBZ.
4584	* @param papvPages Where to store the ring-3 mapping addresses
4585	* corresponding to @a paGCPhysPages.
4586	* @param paLocks Where to store the lock information that
4587	* pfnPhysReleasePageMappingLock needs (@a cPages
4588	* in length).
4589	*
4590	* @remark Avoid calling this API from within critical sections.
4591	* @thread Any.
4592	* @since 6.0.6
4593	*/
4594	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4595	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4596
4597	/**
4598	* Release the mappings of multiple guest pages.
4599	*
4600	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4601	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4602	*
4603	* @param pDevIns The device instance.
4604	* @param cPages Number of pages to unlock.
4605	* @param paLocks The lock structures initialized by the mapping
4606	* function (@a cPages in length).
4607	* @thread Any.
4608	* @since 6.0.6
4609	*/
4610	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4611
4612	/**
4613	* Returns the micro architecture used for the guest.
4614	*
4615	* @returns CPU micro architecture enum.
4616	* @param pDevIns The device instance.
4617	*/
4618	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4619
4620	/**
4621	* Get the number of physical and linear address bits supported by the guest.
4622	*
4623	* @param pDevIns The device instance.
4624	* @param pcPhysAddrWidth Where to store the number of physical address bits
4625	* supported by the guest.
4626	* @param pcLinearAddrWidth Where to store the number of linear address bits
4627	* supported by the guest.
4628	*/
4629	DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4630	uint8_t *pcLinearAddrWidth));
4631
4632	/**
4633	* Gets the scalable bus frequency.
4634	*
4635	* The bus frequency is used as a base in several MSRs that gives the CPU and
4636	* other frequency ratios.
4637	*
4638	* @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
4639	* @param pDevIns The device instance.
4640	*/
4641	DECLR3CALLBACKMEMBER(uint64_t, pfnCpuGetGuestScalableBusFrequency,(PPDMDEVINS pDevIns));
4642
4643	/** Space reserved for future members.
4644	* @{ */
4645	/**
4646	* Deregister zero or more samples given their name prefix.
4647	*
4648	* @returns VBox status code.
4649	* @param pDevIns The device instance.
4650	* @param pszPrefix The name prefix of the samples to remove. If this does
4651	* not start with a '/', the default prefix will be
4652	* prepended, otherwise it will be used as-is.
4653	*/
4654	DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4655	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4656	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4657	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4658	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4659	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4660	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4661	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4662	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4663	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4664	/** @} */
4665
4666
4667	/** API available to trusted devices only.
4668	*
4669	* These APIs are providing unrestricted access to the guest and the VM,
4670	* or they are interacting intimately with PDM.
4671	*
4672	* @{
4673	*/
4674
4675	/**
4676	* Gets the user mode VM handle. Restricted API.
4677	*
4678	* @returns User mode VM Handle.
4679	* @param pDevIns The device instance.
4680	*/
4681	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4682
4683	/**
4684	* Gets the global VM handle. Restricted API.
4685	*
4686	* @returns VM Handle.
4687	* @param pDevIns The device instance.
4688	*/
4689	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4690
4691	/**
4692	* Gets the VMCPU handle. Restricted API.
4693	*
4694	* @returns VMCPU Handle.
4695	* @param pDevIns The device instance.
4696	*/
4697	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4698
4699	/**
4700	* The the VM CPU ID of the current thread (restricted API).
4701	*
4702	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4703	* @param pDevIns The device instance.
4704	*/
4705	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4706
4707	/**
4708	* Registers the VMM device heap or notifies about mapping/unmapping.
4709	*
4710	* This interface serves three purposes:
4711	*
4712	* -# Register the VMM device heap during device construction
4713	* for the HM to use.
4714	* -# Notify PDM/HM that it's mapped into guest address
4715	* space (i.e. usable).
4716	* -# Notify PDM/HM that it is being unmapped from the guest
4717	* address space (i.e. not usable).
4718	*
4719	* @returns VBox status code.
4720	* @param pDevIns The device instance.
4721	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4722	* not mapped.
4723	* @param pvHeap Ring 3 heap pointer.
4724	* @param cbHeap Size of the heap.
4725	* @thread EMT.
4726	*/
4727	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4728
4729	/**
4730	* Registers the firmware (BIOS, EFI) device with PDM.
4731	*
4732	* The firmware provides a callback table and gets a special PDM helper table.
4733	* There can only be one firmware device for a VM.
4734	*
4735	* @returns VBox status code.
4736	* @param pDevIns The device instance.
4737	* @param pFwReg Firmware registration structure.
4738	* @param ppFwHlp Where to return the firmware helper structure.
4739	* @remarks Only valid during device construction.
4740	* @thread EMT(0)
4741	*/
4742	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4743
4744	/**
4745	* Resets the VM.
4746	*
4747	* @returns The appropriate VBox status code to pass around on reset.
4748	* @param pDevIns The device instance.
4749	* @param fFlags PDMVMRESET_F_XXX flags.
4750	* @thread The emulation thread.
4751	*/
4752	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4753
4754	/**
4755	* Suspends the VM.
4756	*
4757	* @returns The appropriate VBox status code to pass around on suspend.
4758	* @param pDevIns The device instance.
4759	* @thread The emulation thread.
4760	*/
4761	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4762
4763	/**
4764	* Suspends, saves and powers off the VM.
4765	*
4766	* @returns The appropriate VBox status code to pass around.
4767	* @param pDevIns The device instance.
4768	* @thread An emulation thread.
4769	*/
4770	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4771
4772	/**
4773	* Power off the VM.
4774	*
4775	* @returns The appropriate VBox status code to pass around on power off.
4776	* @param pDevIns The device instance.
4777	* @thread The emulation thread.
4778	*/
4779	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4780
4781	/**
4782	* Checks if the Gate A20 is enabled or not.
4783	*
4784	* @returns true if A20 is enabled.
4785	* @returns false if A20 is disabled.
4786	* @param pDevIns The device instance.
4787	* @thread The emulation thread.
4788	*/
4789	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4790
4791	/**
4792	* Enables or disables the Gate A20.
4793	*
4794	* @param pDevIns The device instance.
4795	* @param fEnable Set this flag to enable the Gate A20; clear it
4796	* to disable.
4797	* @thread The emulation thread.
4798	*/
4799	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4800
4801	/**
4802	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4803	* thread.
4804	*
4805	* @param pDevIns The device instance.
4806	* @param iLeaf The CPUID leaf to get.
4807	* @param pEax Where to store the EAX value.
4808	* @param pEbx Where to store the EBX value.
4809	* @param pEcx Where to store the ECX value.
4810	* @param pEdx Where to store the EDX value.
4811	* @thread EMT.
4812	*/
4813	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4814
4815	/**
4816	* Gets the main execution engine for the VM.
4817	*
4818	* @returns VM_EXEC_ENGINE_XXX
4819	* @param pDevIns The device instance.
4820	*/
4821	DECLR3CALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
4822
4823	/**
4824	* Get the current virtual clock time in a VM. The clock frequency must be
4825	* queried separately.
4826	*
4827	* @returns Current clock time.
4828	* @param pDevIns The device instance.
4829	*/
4830	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4831
4832	/**
4833	* Get the frequency of the virtual clock.
4834	*
4835	* @returns The clock frequency (not variable at run-time).
4836	* @param pDevIns The device instance.
4837	*/
4838	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4839
4840	/**
4841	* Get the current virtual clock time in a VM, in nanoseconds.
4842	*
4843	* @returns Current clock time (in ns).
4844	* @param pDevIns The device instance.
4845	*/
4846	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4847
4848	/**
4849	* Get the timestamp frequency.
4850	*
4851	* @returns Number of ticks per second.
4852	* @param pDevIns The device instance.
4853	*/
4854	DECLR3CALLBACKMEMBER(uint64_t, pfnTMCpuTicksPerSecond,(PPDMDEVINS pDevIns));
4855
4856	/**
4857	* Gets the support driver session.
4858	*
4859	* This is intended for working with the semaphore API.
4860	*
4861	* @returns Support driver session handle.
4862	* @param pDevIns The device instance.
4863	*/
4864	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4865
4866	/**
4867	* Queries a generic object from the VMM user.
4868	*
4869	* @returns Pointer to the object if found, NULL if not.
4870	* @param pDevIns The device instance.
4871	* @param pUuid The UUID of what's being queried. The UUIDs and
4872	* the usage conventions are defined by the user.
4873	*
4874	* @note It is strictly forbidden to call this internally in VBox! This
4875	* interface is exclusively for hacks in externally developed devices.
4876	*/
4877	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4878
4879	/**
4880	* Register a physical page access handler type.
4881	*
4882	* @returns VBox status code.
4883	* @param pDevIns The device instance.
4884	* @param enmKind The kind of access handler.
4885	* @param pfnHandler Pointer to the ring-3 handler callback.
4886	* @param pszDesc The type description.
4887	* @param phType Where to return the type handle (cross context safe).
4888	* @sa PDMDevHlpPGMHandlerPhysicalTypeSetUpContext
4889	*/
4890	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4891	PFNPGMPHYSHANDLER pfnHandler,
4892	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4893
4894	/**
4895	* Register a access handler for a physical range.
4896	*
4897	* @returns VBox status code.
4898	* @retval VINF_SUCCESS when successfully installed.
4899	* @retval VINF_PGM_GCPHYS_ALIASED when the shadow PTs could be updated because
4900	* the guest page aliased or/and mapped by multiple PTs. A CR3 sync has been
4901	* flagged together with a pool clearing.
4902	* @retval VERR_PGM_HANDLER_PHYSICAL_CONFLICT if the range conflicts with an existing
4903	* one. A debug assertion is raised.
4904	*
4905	* @param pDevIns The device instance.
4906	* @param GCPhys Start physical address.
4907	* @param GCPhysLast Last physical address. (inclusive)
4908	* @param hType The handler type registration handle.
4909	* @param pszDesc Description of this handler. If NULL, the type
4910	* description will be used instead.
4911	* @note There is no @a uUser argument, because it will be set to the pDevIns
4912	* in the context the handler is called.
4913	*/
4914	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalRegister, (PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
4915	PGMPHYSHANDLERTYPE hType, R3PTRTYPE(const char *) pszDesc));
4916
4917	/**
4918	* Deregister a physical page access handler.
4919	*
4920	* @returns VBox status code.
4921	* @param pDevIns The device instance.
4922	* @param GCPhys Start physical address.
4923	*/
4924	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalDeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4925
4926	/**
4927	* Temporarily turns off the access monitoring of a page within a monitored
4928	* physical write/all page access handler region.
4929	*
4930	* Use this when no further \#PFs are required for that page. Be aware that
4931	* a page directory sync might reset the flags, and turn on access monitoring
4932	* for the page.
4933	*
4934	* The caller must do required page table modifications.
4935	*
4936	* @returns VBox status code.
4937	* @param pDevIns The device instance.
4938	* @param GCPhys The start address of the access handler. This
4939	* must be a fully page aligned range or we risk
4940	* messing up other handlers installed for the
4941	* start and end pages.
4942	* @param GCPhysPage The physical address of the page to turn off
4943	* access monitoring for.
4944	*/
4945	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
4946
4947	/**
4948	* Resets any modifications to individual pages in a physical page access
4949	* handler region.
4950	*
4951	* This is used in pair with PGMHandlerPhysicalPageTempOff(),
4952	* PGMHandlerPhysicalPageAliasMmio2() or PGMHandlerPhysicalPageAliasHC().
4953	*
4954	* @returns VBox status code.
4955	* @param pDevIns The device instance.
4956	* @param GCPhys The start address of the handler regions, i.e. what you
4957	* passed to PGMR3HandlerPhysicalRegister(),
4958	* PGMHandlerPhysicalRegisterEx() or
4959	* PGMHandlerPhysicalModify().
4960	*/
4961	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalReset,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4962
4963	/**
4964	* Registers the guest memory range that can be used for patching.
4965	*
4966	* @returns VBox status code.
4967	* @param pDevIns The device instance.
4968	* @param GCPtrPatchMem Patch memory range.
4969	* @param cbPatchMem Size of the memory range.
4970	*/
4971	DECLR3CALLBACKMEMBER(int, pfnVMMRegisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4972
4973	/**
4974	* Deregisters the guest memory range that can be used for patching.
4975	*
4976	* @returns VBox status code.
4977	* @param pDevIns The device instance.
4978	* @param GCPtrPatchMem Patch memory range.
4979	* @param cbPatchMem Size of the memory range.
4980	*/
4981	DECLR3CALLBACKMEMBER(int, pfnVMMDeregisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4982
4983	/**
4984	* Registers a new shared module for the VM
4985	*
4986	* @returns VBox status code.
4987	* @param pDevIns The device instance.
4988	* @param enmGuestOS Guest OS type.
4989	* @param pszModuleName Module name.
4990	* @param pszVersion Module version.
4991	* @param GCBaseAddr Module base address.
4992	* @param cbModule Module size.
4993	* @param cRegions Number of shared region descriptors.
4994	* @param paRegions Shared region(s).
4995	*/
4996	DECLR3CALLBACKMEMBER(int, pfnSharedModuleRegister,(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
4997	RTGCPTR GCBaseAddr, uint32_t cbModule,
4998	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions));
4999
5000	/**
5001	* Unregisters a shared module for the VM
5002	*
5003	* @returns VBox status code.
5004	* @param pDevIns The device instance.
5005	* @param pszModuleName Module name.
5006	* @param pszVersion Module version.
5007	* @param GCBaseAddr Module base address.
5008	* @param cbModule Module size.
5009	*/
5010	DECLR3CALLBACKMEMBER(int, pfnSharedModuleUnregister,(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
5011	RTGCPTR GCBaseAddr, uint32_t cbModule));
5012
5013	/**
5014	* Query the state of a page in a shared module
5015	*
5016	* @returns VBox status code.
5017	* @param pDevIns The device instance.
5018	* @param GCPtrPage Page address.
5019	* @param pfShared Shared status (out).
5020	* @param pfPageFlags Page flags (out).
5021	*/
5022	DECLR3CALLBACKMEMBER(int, pfnSharedModuleGetPageState, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags));
5023
5024	/**
5025	* Check all registered modules for changes.
5026	*
5027	* @returns VBox status code.
5028	* @param pDevIns The device instance.
5029	*/
5030	DECLR3CALLBACKMEMBER(int, pfnSharedModuleCheckAll,(PPDMDEVINS pDevIns));
5031
5032	/**
5033	* Query the interface of the top level driver on a LUN.
5034	*
5035	* @returns VBox status code.
5036	* @param pDevIns The device instance.
5037	* @param pszDevice Device name.
5038	* @param iInstance Device instance.
5039	* @param iLun The Logical Unit to obtain the interface of.
5040	* @param ppBase Where to store the base interface pointer.
5041	*
5042	* @remark We're not doing any locking ATM, so don't try call this at times when the
5043	* device chain is known to be updated.
5044	*/
5045	DECLR3CALLBACKMEMBER(int, pfnQueryLun,(PPDMDEVINS pDevIns, const char *pszDevice, unsigned iInstance, unsigned iLun, PPPDMIBASE ppBase));
5046
5047	/**
5048	* Registers the GIM device with VMM.
5049	*
5050	* @param pDevIns Pointer to the GIM device instance.
5051	* @param pDbg Pointer to the GIM device debug structure, can be
5052	* NULL.
5053	*/
5054	DECLR3CALLBACKMEMBER(void, pfnGIMDeviceRegister,(PPDMDEVINS pDevIns, PGIMDEBUG pDbg));
5055
5056	/**
5057	* Gets debug setup specified by the provider.
5058	*
5059	* @returns VBox status code.
5060	* @param pDevIns Pointer to the GIM device instance.
5061	* @param pDbgSetup Where to store the debug setup details.
5062	*/
5063	DECLR3CALLBACKMEMBER(int, pfnGIMGetDebugSetup,(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup));
5064
5065	/**
5066	* Returns the array of MMIO2 regions that are expected to be registered and
5067	* later mapped into the guest-physical address space for the GIM provider
5068	* configured for the VM.
5069	*
5070	* @returns Pointer to an array of GIM MMIO2 regions, may return NULL.
5071	* @param pDevIns Pointer to the GIM device instance.
5072	* @param pcRegions Where to store the number of items in the array.
5073	*
5074	* @remarks The caller does not own and therefore must -NOT- try to free the
5075	* returned pointer.
5076	*/
5077	DECLR3CALLBACKMEMBER(PGIMMMIO2REGION, pfnGIMGetMmio2Regions,(PPDMDEVINS pDevIns, uint32_t *pcRegions));
5078
5079	/** @} */
5080
5081	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
5082	uint32_t u32TheEnd;
5083	} PDMDEVHLPR3;
5084	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
5085	/** Pointer to the R3 PDM Device API. */
5086	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
5087	/** Pointer to the R3 PDM Device API, const variant. */
5088	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
5089
5090
5091	/**
5092	* PDM Device API - RC Variant.
5093	*/
5094	typedef struct PDMDEVHLPRC
5095	{
5096	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
5097	uint32_t u32Version;
5098
5099	/**
5100	* Sets up raw-mode context callback handlers for an I/O port range.
5101	*
5102	* The range must have been registered in ring-3 first using
5103	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5104	*
5105	* @returns VBox status.
5106	* @param pDevIns The device instance to register the ports with.
5107	* @param hIoPorts The I/O port range handle.
5108	* @param pfnOut Pointer to function which is gonna handle OUT
5109	* operations. Optional.
5110	* @param pfnIn Pointer to function which is gonna handle IN operations.
5111	* Optional.
5112	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5113	* operations. Optional.
5114	* @param pfnInStr Pointer to function which is gonna handle string IN
5115	* operations. Optional.
5116	* @param pvUser User argument to pass to the callbacks.
5117	*
5118	* @remarks Caller enters the device critical section prior to invoking the
5119	* registered callback methods.
5120	*
5121	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
5122	* PDMDevHlpIoPortUnmap.
5123	*/
5124	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5125	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5126	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5127	void *pvUser));
5128
5129	/**
5130	* Sets up raw-mode context callback handlers for an MMIO region.
5131	*
5132	* The region must have been registered in ring-3 first using
5133	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
5134	*
5135	* @returns VBox status.
5136	* @param pDevIns The device instance to register the ports with.
5137	* @param hRegion The MMIO region handle.
5138	* @param pfnWrite Pointer to function which is gonna handle Write
5139	* operations.
5140	* @param pfnRead Pointer to function which is gonna handle Read
5141	* operations.
5142	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5143	* operations. (optional)
5144	* @param pvUser User argument to pass to the callbacks.
5145	*
5146	* @remarks Caller enters the device critical section prior to invoking the
5147	* registered callback methods.
5148	*
5149	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
5150	* PDMDevHlpMmioUnmap.
5151	*/
5152	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5153	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5154
5155	/**
5156	* Sets up a raw-mode mapping for an MMIO2 region.
5157	*
5158	* The region must have been created in ring-3 first using
5159	* PDMDevHlpMmio2Create().
5160	*
5161	* @returns VBox status.
5162	* @param pDevIns The device instance to register the ports with.
5163	* @param hRegion The MMIO2 region handle.
5164	* @param offSub Start of what to map into raw-mode. Must be page aligned.
5165	* @param cbSub Number of bytes to map into raw-mode. Must be page
5166	* aligned. Zero is an alias for everything.
5167	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5168	* @thread EMT(0)
5169	* @note Only available at VM creation time.
5170	*
5171	* @sa PDMDevHlpMmio2Create().
5172	*/
5173	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
5174	size_t offSub, size_t cbSub, void **ppvMapping));
5175
5176	/**
5177	* Bus master physical memory read from the given PCI device.
5178	*
5179	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
5180	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
5181	* @param pDevIns The device instance.
5182	* @param pPciDev The PCI device structure. If NULL the default
5183	* PCI device for this device instance is used.
5184	* @param GCPhys Physical address start reading from.
5185	* @param pvBuf Where to put the read bits.
5186	* @param cbRead How many bytes to read.
5187	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5188	* @thread Any thread, but the call may involve the emulation thread.
5189	*/
5190	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5191	void *pvBuf, size_t cbRead, uint32_t fFlags));
5192
5193	/**
5194	* Bus master physical memory write from the given PCI device.
5195	*
5196	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
5197	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
5198	* @param pDevIns The device instance.
5199	* @param pPciDev The PCI device structure. If NULL the default
5200	* PCI device for this device instance is used.
5201	* @param GCPhys Physical address to write to.
5202	* @param pvBuf What to write.
5203	* @param cbWrite How many bytes to write.
5204	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5205	* @thread Any thread, but the call may involve the emulation thread.
5206	*/
5207	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5208	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5209
5210	/**
5211	* Set the IRQ for the given PCI device.
5212	*
5213	* @param pDevIns Device instance.
5214	* @param pPciDev The PCI device structure. If NULL the default
5215	* PCI device for this device instance is used.
5216	* @param iIrq IRQ number to set.
5217	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5218	* @thread Any thread, but will involve the emulation thread.
5219	*/
5220	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5221
5222	/**
5223	* Set ISA IRQ for a device.
5224	*
5225	* @param pDevIns Device instance.
5226	* @param iIrq IRQ number to set.
5227	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5228	* @thread Any thread, but will involve the emulation thread.
5229	*/
5230	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5231
5232	/**
5233	* Read physical memory.
5234	*
5235	* @returns VINF_SUCCESS (for now).
5236	* @param pDevIns Device instance.
5237	* @param GCPhys Physical address start reading from.
5238	* @param pvBuf Where to put the read bits.
5239	* @param cbRead How many bytes to read.
5240	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5241	*/
5242	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5243
5244	/**
5245	* Write to physical memory.
5246	*
5247	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5248	* @param pDevIns Device instance.
5249	* @param GCPhys Physical address to write to.
5250	* @param pvBuf What to write.
5251	* @param cbWrite How many bytes to write.
5252	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5253	*/
5254	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5255
5256	/**
5257	* Checks if the Gate A20 is enabled or not.
5258	*
5259	* @returns true if A20 is enabled.
5260	* @returns false if A20 is disabled.
5261	* @param pDevIns Device instance.
5262	* @thread The emulation thread.
5263	*/
5264	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5265
5266	/**
5267	* Gets the VM state.
5268	*
5269	* @returns VM state.
5270	* @param pDevIns The device instance.
5271	* @thread Any thread (just keep in mind that it's volatile info).
5272	*/
5273	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5274
5275	/**
5276	* Gets the VM handle. Restricted API.
5277	*
5278	* @returns VM Handle.
5279	* @param pDevIns Device instance.
5280	*/
5281	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5282
5283	/**
5284	* Gets the VMCPU handle. Restricted API.
5285	*
5286	* @returns VMCPU Handle.
5287	* @param pDevIns The device instance.
5288	*/
5289	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5290
5291	/**
5292	* The the VM CPU ID of the current thread (restricted API).
5293	*
5294	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5295	* @param pDevIns The device instance.
5296	*/
5297	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5298
5299	/**
5300	* Gets the main execution engine for the VM.
5301	*
5302	* @returns VM_EXEC_ENGINE_XXX
5303	* @param pDevIns The device instance.
5304	*/
5305	DECLRCCALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
5306
5307	/**
5308	* Get the current virtual clock time in a VM. The clock frequency must be
5309	* queried separately.
5310	*
5311	* @returns Current clock time.
5312	* @param pDevIns The device instance.
5313	*/
5314	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5315
5316	/**
5317	* Get the frequency of the virtual clock.
5318	*
5319	* @returns The clock frequency (not variable at run-time).
5320	* @param pDevIns The device instance.
5321	*/
5322	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5323
5324	/**
5325	* Get the current virtual clock time in a VM, in nanoseconds.
5326	*
5327	* @returns Current clock time (in ns).
5328	* @param pDevIns The device instance.
5329	*/
5330	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5331
5332	/**
5333	* Gets the NOP critical section.
5334	*
5335	* @returns The ring-3 address of the NOP critical section.
5336	* @param pDevIns The device instance.
5337	*/
5338	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5339
5340	/**
5341	* Changes the device level critical section from the automatically created
5342	* default to one desired by the device constructor.
5343	*
5344	* Must first be done in ring-3.
5345	*
5346	* @returns VBox status code.
5347	* @param pDevIns The device instance.
5348	* @param pCritSect The critical section to use. NULL is not
5349	* valid, instead use the NOP critical
5350	* section.
5351	*/
5352	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5353
5354	/** @name Exported PDM Critical Section Functions
5355	* @{ */
5356	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5357	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5358	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5359	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5360	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5361	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5362	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5363	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5364	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5365	/** @} */
5366
5367	/** @name Exported PDM Read/Write Critical Section Functions
5368	* @{ */
5369	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5370	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5371	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5372	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5373	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5374
5375	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5376	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5377	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5378	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5379	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5380
5381	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5382	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5383	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5384	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5385	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5386	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5387	/** @} */
5388
5389	/**
5390	* Gets the trace buffer handle.
5391	*
5392	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5393	* really inteded for direct usage, thus no inline wrapper function.
5394	*
5395	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5396	* @param pDevIns The device instance.
5397	*/
5398	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5399
5400	/**
5401	* Sets up the PCI bus for the raw-mode context.
5402	*
5403	* This must be called after ring-3 has registered the PCI bus using
5404	* PDMDevHlpPCIBusRegister().
5405	*
5406	* @returns VBox status code.
5407	* @param pDevIns The device instance.
5408	* @param pPciBusReg The PCI bus registration information for raw-mode,
5409	* considered volatile.
5410	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
5411	*/
5412	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
5413
5414	/**
5415	* Sets up the IOMMU for the raw-mode context.
5416	*
5417	* This must be called after ring-3 has registered the IOMMU using
5418	* PDMDevHlpIommuRegister().
5419	*
5420	* @returns VBox status code.
5421	* @param pDevIns The device instance.
5422	* @param pIommuReg The IOMMU registration information for raw-mode,
5423	* considered volatile.
5424	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
5425	*/
5426	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
5427
5428	/**
5429	* Sets up the PIC for the ring-0 context.
5430	*
5431	* This must be called after ring-3 has registered the PIC using
5432	* PDMDevHlpPICRegister().
5433	*
5434	* @returns VBox status code.
5435	* @param pDevIns The device instance.
5436	* @param pPicReg The PIC registration information for ring-0,
5437	* considered volatile and copied.
5438	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5439	*/
5440	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5441
5442	/**
5443	* Sets up the APIC for the raw-mode context.
5444	*
5445	* This must be called after ring-3 has registered the APIC using
5446	* PDMDevHlpApicRegister().
5447	*
5448	* @returns VBox status code.
5449	* @param pDevIns The device instance.
5450	*/
5451	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5452
5453	/**
5454	* Sets up the IOAPIC for the ring-0 context.
5455	*
5456	* This must be called after ring-3 has registered the PIC using
5457	* PDMDevHlpIoApicRegister().
5458	*
5459	* @returns VBox status code.
5460	* @param pDevIns The device instance.
5461	* @param pIoApicReg The PIC registration information for ring-0,
5462	* considered volatile and copied.
5463	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5464	*/
5465	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5466
5467	/**
5468	* Sets up the HPET for the raw-mode context.
5469	*
5470	* This must be called after ring-3 has registered the PIC using
5471	* PDMDevHlpHpetRegister().
5472	*
5473	* @returns VBox status code.
5474	* @param pDevIns The device instance.
5475	* @param pHpetReg The PIC registration information for raw-mode,
5476	* considered volatile and copied.
5477	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
5478	*/
5479	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
5480
5481	/** Space reserved for future members.
5482	* @{ */
5483	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
5484	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
5485	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
5486	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
5487	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
5488	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
5489	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
5490	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
5491	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
5492	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
5493	/** @} */
5494
5495	/** Just a safety precaution. */
5496	uint32_t u32TheEnd;
5497	} PDMDEVHLPRC;
5498	/** Pointer PDM Device RC API. */
5499	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
5500	/** Pointer PDM Device RC API. */
5501	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
5502
5503	/** Current PDMDEVHLP version number. */
5504	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 19, 0)
5505
5506
5507	/**
5508	* PDM Device API - R0 Variant.
5509	*/
5510	typedef struct PDMDEVHLPR0
5511	{
5512	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5513	uint32_t u32Version;
5514
5515	/**
5516	* Sets up ring-0 callback handlers for an I/O port range.
5517	*
5518	* The range must have been created in ring-3 first using
5519	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5520	*
5521	* @returns VBox status.
5522	* @param pDevIns The device instance to register the ports with.
5523	* @param hIoPorts The I/O port range handle.
5524	* @param pfnOut Pointer to function which is gonna handle OUT
5525	* operations. Optional.
5526	* @param pfnIn Pointer to function which is gonna handle IN operations.
5527	* Optional.
5528	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5529	* operations. Optional.
5530	* @param pfnInStr Pointer to function which is gonna handle string IN
5531	* operations. Optional.
5532	* @param pvUser User argument to pass to the callbacks.
5533	*
5534	* @remarks Caller enters the device critical section prior to invoking the
5535	* registered callback methods.
5536	*
5537	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5538	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5539	*/
5540	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5541	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5542	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5543	void *pvUser));
5544
5545	/**
5546	* Sets up ring-0 callback handlers for an MMIO region.
5547	*
5548	* The region must have been created in ring-3 first using
5549	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5550	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5551	*
5552	* @returns VBox status.
5553	* @param pDevIns The device instance to register the ports with.
5554	* @param hRegion The MMIO region handle.
5555	* @param pfnWrite Pointer to function which is gonna handle Write
5556	* operations.
5557	* @param pfnRead Pointer to function which is gonna handle Read
5558	* operations.
5559	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5560	* operations. (optional)
5561	* @param pvUser User argument to pass to the callbacks.
5562	*
5563	* @remarks Caller enters the device critical section prior to invoking the
5564	* registered callback methods.
5565	*
5566	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5567	* PDMDevHlpMmioUnmap().
5568	*/
5569	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5570	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5571
5572	/**
5573	* Sets up a ring-0 mapping for an MMIO2 region.
5574	*
5575	* The region must have been created in ring-3 first using
5576	* PDMDevHlpMmio2Create().
5577	*
5578	* @returns VBox status.
5579	* @param pDevIns The device instance to register the ports with.
5580	* @param hRegion The MMIO2 region handle.
5581	* @param offSub Start of what to map into ring-0. Must be page aligned.
5582	* @param cbSub Number of bytes to map into ring-0. Must be page
5583	* aligned. Zero is an alias for everything.
5584	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5585	*
5586	* @thread EMT(0)
5587	* @note Only available at VM creation time.
5588	*
5589	* @sa PDMDevHlpMmio2Create().
5590	*/
5591	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5592	void **ppvMapping));
5593
5594	/**
5595	* Bus master physical memory read from the given PCI device.
5596	*
5597	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5598	* VERR_EM_MEMORY.
5599	* @param pDevIns The device instance.
5600	* @param pPciDev The PCI device structure. If NULL the default
5601	* PCI device for this device instance is used.
5602	* @param GCPhys Physical address start reading from.
5603	* @param pvBuf Where to put the read bits.
5604	* @param cbRead How many bytes to read.
5605	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5606	* @thread Any thread, but the call may involve the emulation thread.
5607	*/
5608	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5609	void *pvBuf, size_t cbRead, uint32_t fFlags));
5610
5611	/**
5612	* Bus master physical memory write from the given PCI device.
5613	*
5614	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5615	* VERR_EM_MEMORY.
5616	* @param pDevIns The device instance.
5617	* @param pPciDev The PCI device structure. If NULL the default
5618	* PCI device for this device instance is used.
5619	* @param GCPhys Physical address to write to.
5620	* @param pvBuf What to write.
5621	* @param cbWrite How many bytes to write.
5622	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5623	* @thread Any thread, but the call may involve the emulation thread.
5624	*/
5625	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5626	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5627
5628	/**
5629	* Set the IRQ for the given PCI device.
5630	*
5631	* @param pDevIns Device instance.
5632	* @param pPciDev The PCI device structure. If NULL the default
5633	* PCI device for this device instance is used.
5634	* @param iIrq IRQ number to set.
5635	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5636	* @thread Any thread, but will involve the emulation thread.
5637	*/
5638	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5639
5640	/**
5641	* Set ISA IRQ for a device.
5642	*
5643	* @param pDevIns Device instance.
5644	* @param iIrq IRQ number to set.
5645	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5646	* @thread Any thread, but will involve the emulation thread.
5647	*/
5648	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5649
5650	/**
5651	* Read physical memory.
5652	*
5653	* @returns VINF_SUCCESS (for now).
5654	* @param pDevIns Device instance.
5655	* @param GCPhys Physical address start reading from.
5656	* @param pvBuf Where to put the read bits.
5657	* @param cbRead How many bytes to read.
5658	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5659	*/
5660	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5661
5662	/**
5663	* Write to physical memory.
5664	*
5665	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5666	* @param pDevIns Device instance.
5667	* @param GCPhys Physical address to write to.
5668	* @param pvBuf What to write.
5669	* @param cbWrite How many bytes to write.
5670	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5671	*/
5672	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5673
5674	/**
5675	* Checks if the Gate A20 is enabled or not.
5676	*
5677	* @returns true if A20 is enabled.
5678	* @returns false if A20 is disabled.
5679	* @param pDevIns Device instance.
5680	* @thread The emulation thread.
5681	*/
5682	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5683
5684	/**
5685	* Gets the VM state.
5686	*
5687	* @returns VM state.
5688	* @param pDevIns The device instance.
5689	* @thread Any thread (just keep in mind that it's volatile info).
5690	*/
5691	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5692
5693	/**
5694	* Gets the VM handle. Restricted API.
5695	*
5696	* @returns VM Handle.
5697	* @param pDevIns Device instance.
5698	*/
5699	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5700
5701	/**
5702	* Gets the VMCPU handle. Restricted API.
5703	*
5704	* @returns VMCPU Handle.
5705	* @param pDevIns The device instance.
5706	*/
5707	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5708
5709	/**
5710	* The the VM CPU ID of the current thread (restricted API).
5711	*
5712	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5713	* @param pDevIns The device instance.
5714	*/
5715	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5716
5717	/**
5718	* Gets the main execution engine for the VM.
5719	*
5720	* @returns VM_EXEC_ENGINE_XXX
5721	* @param pDevIns The device instance.
5722	*/
5723	DECLR0CALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
5724
5725	/** @name Timer handle method wrappers
5726	* @{ */
5727	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5728	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5729	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5730	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5731	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5732	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5733	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5734	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5735	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5736	/** Takes the clock lock then enters the specified critical section. */
5737	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5738	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5739	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5740	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5741	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5742	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5743	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5744	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5745	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5746	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5747	/** @} */
5748
5749	/**
5750	* Get the current virtual clock time in a VM. The clock frequency must be
5751	* queried separately.
5752	*
5753	* @returns Current clock time.
5754	* @param pDevIns The device instance.
5755	*/
5756	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5757
5758	/**
5759	* Get the frequency of the virtual clock.
5760	*
5761	* @returns The clock frequency (not variable at run-time).
5762	* @param pDevIns The device instance.
5763	*/
5764	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5765
5766	/**
5767	* Get the current virtual clock time in a VM, in nanoseconds.
5768	*
5769	* @returns Current clock time (in ns).
5770	* @param pDevIns The device instance.
5771	*/
5772	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5773
5774	/** @name Exported PDM Queue Functions
5775	* @{ */
5776	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5777	DECLR0CALLBACKMEMBER(int, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5778	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5779	/** @} */
5780
5781	/** @name PDM Task
5782	* @{ */
5783	/**
5784	* Triggers the running the given task.
5785	*
5786	* @returns VBox status code.
5787	* @retval VINF_ALREADY_POSTED is the task is already pending.
5788	* @param pDevIns The device instance.
5789	* @param hTask The task to trigger.
5790	* @thread Any thread.
5791	*/
5792	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5793	/** @} */
5794
5795	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5796	* These semaphores can be signalled from ring-0.
5797	* @{ */
5798	/** @sa SUPSemEventSignal */
5799	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5800	/** @sa SUPSemEventWaitNoResume */
5801	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5802	/** @sa SUPSemEventWaitNsAbsIntr */
5803	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5804	/** @sa SUPSemEventWaitNsRelIntr */
5805	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5806	/** @sa SUPSemEventGetResolution */
5807	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5808	/** @} */
5809
5810	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5811	* These semaphores can be signalled from ring-0.
5812	* @{ */
5813	/** @sa SUPSemEventMultiSignal */
5814	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5815	/** @sa SUPSemEventMultiReset */
5816	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5817	/** @sa SUPSemEventMultiWaitNoResume */
5818	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5819	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5820	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5821	/** @sa SUPSemEventMultiWaitNsRelIntr */
5822	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5823	/** @sa SUPSemEventMultiGetResolution */
5824	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5825	/** @} */
5826
5827	/**
5828	* Gets the NOP critical section.
5829	*
5830	* @returns The ring-3 address of the NOP critical section.
5831	* @param pDevIns The device instance.
5832	*/
5833	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5834
5835	/**
5836	* Changes the device level critical section from the automatically created
5837	* default to one desired by the device constructor.
5838	*
5839	* Must first be done in ring-3.
5840	*
5841	* @returns VBox status code.
5842	* @param pDevIns The device instance.
5843	* @param pCritSect The critical section to use. NULL is not
5844	* valid, instead use the NOP critical
5845	* section.
5846	*/
5847	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5848
5849	/** @name Exported PDM Critical Section Functions
5850	* @{ */
5851	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5852	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5853	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5854	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5855	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5856	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5857	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5858	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5859	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5860	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5861	/** @} */
5862
5863	/** @name Exported PDM Read/Write Critical Section Functions
5864	* @{ */
5865	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5866	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5867	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5868	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5869	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5870
5871	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5872	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5873	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5874	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5875	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5876
5877	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5878	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5879	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5880	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5881	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5882	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5883	/** @} */
5884
5885	/**
5886	* Gets the trace buffer handle.
5887	*
5888	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5889	* really inteded for direct usage, thus no inline wrapper function.
5890	*
5891	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5892	* @param pDevIns The device instance.
5893	*/
5894	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5895
5896	/**
5897	* Sets up the PCI bus for the ring-0 context.
5898	*
5899	* This must be called after ring-3 has registered the PCI bus using
5900	* PDMDevHlpPCIBusRegister().
5901	*
5902	* @returns VBox status code.
5903	* @param pDevIns The device instance.
5904	* @param pPciBusReg The PCI bus registration information for ring-0,
5905	* considered volatile and copied.
5906	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5907	*/
5908	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5909
5910	/**
5911	* Sets up the IOMMU for the ring-0 context.
5912	*
5913	* This must be called after ring-3 has registered the IOMMU using
5914	* PDMDevHlpIommuRegister().
5915	*
5916	* @returns VBox status code.
5917	* @param pDevIns The device instance.
5918	* @param pIommuReg The IOMMU registration information for ring-0,
5919	* considered volatile and copied.
5920	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5921	*/
5922	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5923
5924	/**
5925	* Sets up the PIC for the ring-0 context.
5926	*
5927	* This must be called after ring-3 has registered the PIC using
5928	* PDMDevHlpPICRegister().
5929	*
5930	* @returns VBox status code.
5931	* @param pDevIns The device instance.
5932	* @param pPicReg The PIC registration information for ring-0,
5933	* considered volatile and copied.
5934	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5935	*/
5936	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5937
5938	/**
5939	* Sets up the APIC for the ring-0 context.
5940	*
5941	* This must be called after ring-3 has registered the APIC using
5942	* PDMDevHlpApicRegister().
5943	*
5944	* @returns VBox status code.
5945	* @param pDevIns The device instance.
5946	*/
5947	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5948
5949	/**
5950	* Sets up the IOAPIC for the ring-0 context.
5951	*
5952	* This must be called after ring-3 has registered the PIC using
5953	* PDMDevHlpIoApicRegister().
5954	*
5955	* @returns VBox status code.
5956	* @param pDevIns The device instance.
5957	* @param pIoApicReg The PIC registration information for ring-0,
5958	* considered volatile and copied.
5959	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5960	*/
5961	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5962
5963	/**
5964	* Sets up the HPET for the ring-0 context.
5965	*
5966	* This must be called after ring-3 has registered the PIC using
5967	* PDMDevHlpHpetRegister().
5968	*
5969	* @returns VBox status code.
5970	* @param pDevIns The device instance.
5971	* @param pHpetReg The PIC registration information for ring-0,
5972	* considered volatile and copied.
5973	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5974	*/
5975	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5976
5977	/**
5978	* Sets up a physical page access handler type for ring-0 callbacks.
5979	*
5980	* @returns VBox status code.
5981	* @param pDevIns The device instance.
5982	* @param enmKind The kind of access handler.
5983	* @param pfnHandler Pointer to the ring-0 handler callback. NULL if
5984	* the ring-3 handler should be called.
5985	* @param pfnPfHandler The name of the ring-0 \#PF handler, NULL if the
5986	* ring-3 handler should be called.
5987	* @param pszDesc The type description.
5988	* @param hType The type handle registered in ring-3 already.
5989	* @sa PDMDevHlpPGMHandlerPhysicalTypeRegister
5990	*/
5991	DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeSetUpContext, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
5992	PFNPGMPHYSHANDLER pfnHandler,
5993	PFNPGMRZPHYSPFHANDLER pfnPfHandler,
5994	const char *pszDesc, PGMPHYSHANDLERTYPE hType));
5995
5996	/**
5997	* Temporarily turns off the access monitoring of a page within a monitored
5998	* physical write/all page access handler region.
5999	*
6000	* Use this when no further \#PFs are required for that page. Be aware that
6001	* a page directory sync might reset the flags, and turn on access monitoring
6002	* for the page.
6003	*
6004	* The caller must do required page table modifications.
6005	*
6006	* @returns VBox status code.
6007	* @param pDevIns The device instance.
6008	* @param GCPhys The start address of the access handler. This
6009	* must be a fully page aligned range or we risk
6010	* messing up other handlers installed for the
6011	* start and end pages.
6012	* @param GCPhysPage The physical address of the page to turn off
6013	* access monitoring for.
6014	*/
6015	DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
6016
6017	/**
6018	* Mapping an MMIO2 page in place of an MMIO page for direct access.
6019	*
6020	* This is a special optimization used by the VGA device. Call
6021	* PDMDevHlpMmioResetRegion() to undo the mapping.
6022	*
6023	* @returns VBox status code. This API may return VINF_SUCCESS even if no
6024	* remapping is made.
6025	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
6026	*
6027	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
6028	* associated with.
6029	* @param hRegion The handle to the MMIO region.
6030	* @param offRegion The offset into @a hRegion of the page to be
6031	* remapped.
6032	* @param hMmio2 The MMIO2 handle.
6033	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
6034	* mapping.
6035	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
6036	* for the time being.
6037	*/
6038	DECLR0CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6039	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
6040
6041	/**
6042	* Reset a previously modified MMIO region; restore the access flags.
6043	*
6044	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
6045	* intended for some ancient VGA hack. However, it would be great to extend it
6046	* beyond VT-x and/or nested-paging.
6047	*
6048	* @returns VBox status code.
6049	*
6050	* @param pDevIns The device instance @a hRegion is associated with.
6051	* @param hRegion The handle to the MMIO region.
6052	*/
6053	DECLR0CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
6054
6055	/**
6056	* Returns the array of MMIO2 regions that are expected to be registered and
6057	* later mapped into the guest-physical address space for the GIM provider
6058	* configured for the VM.
6059	*
6060	* @returns Pointer to an array of GIM MMIO2 regions, may return NULL.
6061	* @param pDevIns Pointer to the GIM device instance.
6062	* @param pcRegions Where to store the number of items in the array.
6063	*
6064	* @remarks The caller does not own and therefore must -NOT- try to free the
6065	* returned pointer.
6066	*/
6067	DECLR0CALLBACKMEMBER(PGIMMMIO2REGION, pfnGIMGetMmio2Regions,(PPDMDEVINS pDevIns, uint32_t *pcRegions));
6068
6069	/** Space reserved for future members.
6070	* @{ */
6071	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
6072	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
6073	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
6074	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
6075	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
6076	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
6077	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
6078	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
6079	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
6080	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
6081	/** @} */
6082
6083	/** Just a safety precaution. */
6084	uint32_t u32TheEnd;
6085	} PDMDEVHLPR0;
6086	/** Pointer PDM Device R0 API. */
6087	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
6088	/** Pointer PDM Device GC API. */
6089	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
6090
6091	/** Current PDMDEVHLP version number. */
6092	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 27, 0)
6093
6094
6095	/**
6096	* PDM Device Instance.
6097	*/
6098	typedef struct PDMDEVINSR3
6099	{
6100	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
6101	uint32_t u32Version;
6102	/** Device instance number. */
6103	uint32_t iInstance;
6104	/** Size of the ring-3, raw-mode and shared bits. */
6105	uint32_t cbRing3;
6106	/** Set if ring-0 context is enabled. */
6107	bool fR0Enabled;
6108	/** Set if raw-mode context is enabled. */
6109	bool fRCEnabled;
6110	/** Alignment padding. */
6111	bool afReserved[2];
6112	/** Pointer the HC PDM Device API. */
6113	PCPDMDEVHLPR3 pHlpR3;
6114	/** Pointer to the shared device instance data. */
6115	RTR3PTR pvInstanceDataR3;
6116	/** Pointer to the device instance data for ring-3. */
6117	RTR3PTR pvInstanceDataForR3;
6118	/** The critical section for the device.
6119	*
6120	* TM and IOM will enter this critical section before calling into the device
6121	* code. PDM will when doing power on, power off, reset, suspend and resume
6122	* notifications. SSM will currently not, but this will be changed later on.
6123	*
6124	* The device gets a critical section automatically assigned to it before
6125	* the constructor is called. If the constructor wishes to use a different
6126	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6127	* very early on.
6128	*/
6129	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
6130	/** Pointer to device registration structure. */
6131	R3PTRTYPE(PCPDMDEVREG) pReg;
6132	/** Configuration handle. */
6133	R3PTRTYPE(PCFGMNODE) pCfg;
6134	/** The base interface of the device.
6135	*
6136	* The device constructor initializes this if it has any
6137	* device level interfaces to export. To obtain this interface
6138	* call PDMR3QueryDevice(). */
6139	PDMIBASE IBase;
6140
6141	/** Tracing indicator. */
6142	uint32_t fTracing;
6143	/** The tracing ID of this device. */
6144	uint32_t idTracing;
6145
6146	/** Ring-3 pointer to the raw-mode device instance. */
6147	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
6148	/** Raw-mode address of the raw-mode device instance. */
6149	RTRGPTR pDevInsForRC;
6150	/** Ring-3 pointer to the raw-mode instance data. */
6151	RTR3PTR pvInstanceDataForRCR3;
6152
6153	/** PCI device structure size. */
6154	uint32_t cbPciDev;
6155	/** Number of PCI devices in apPciDevs. */
6156	uint32_t cPciDevs;
6157	/** Pointer to the PCI devices for this device.
6158	* (Allocated after the shared instance data.)
6159	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6160	* two devices ever needing it can use cbPciDev and do the address
6161	* calculations that for entries 8+. */
6162	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6163
6164	/** Temporarily. */
6165	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
6166	/** Temporarily. */
6167	RTR0PTR pvInstanceDataR0;
6168	/** Temporarily. */
6169	RTRCPTR pvInstanceDataRC;
6170	/** Align the internal data more naturally. */
6171	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
6172
6173	/** Internal data. */
6174	union
6175	{
6176	#ifdef PDMDEVINSINT_DECLARED
6177	PDMDEVINSINTR3 s;
6178	#endif
6179	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
6180	} Internal;
6181
6182	/** Device instance data for ring-3. The size of this area is defined
6183	* in the PDMDEVREG::cbInstanceR3 field. */
6184	char achInstanceData[8];
6185	} PDMDEVINSR3;
6186
6187	/** Current PDMDEVINSR3 version number. */
6188	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
6189
6190	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
6191	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
6192
6193
6194	/**
6195	* PDM ring-0 device instance.
6196	*/
6197	typedef struct PDMDEVINSR0
6198	{
6199	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
6200	uint32_t u32Version;
6201	/** Device instance number. */
6202	uint32_t iInstance;
6203
6204	/** Pointer the HC PDM Device API. */
6205	PCPDMDEVHLPR0 pHlpR0;
6206	/** Pointer to the shared device instance data. */
6207	RTR0PTR pvInstanceDataR0;
6208	/** Pointer to the device instance data for ring-0. */
6209	RTR0PTR pvInstanceDataForR0;
6210	/** The critical section for the device.
6211	*
6212	* TM and IOM will enter this critical section before calling into the device
6213	* code. PDM will when doing power on, power off, reset, suspend and resume
6214	* notifications. SSM will currently not, but this will be changed later on.
6215	*
6216	* The device gets a critical section automatically assigned to it before
6217	* the constructor is called. If the constructor wishes to use a different
6218	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6219	* very early on.
6220	*/
6221	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
6222	/** Pointer to the ring-0 device registration structure. */
6223	R0PTRTYPE(PCPDMDEVREGR0) pReg;
6224	/** Ring-3 address of the ring-3 device instance. */
6225	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
6226	/** Ring-0 pointer to the ring-3 device instance. */
6227	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
6228	/** Ring-0 pointer to the ring-3 instance data. */
6229	RTR0PTR pvInstanceDataForR3R0;
6230	/** Raw-mode address of the raw-mode device instance. */
6231	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
6232	/** Ring-0 pointer to the raw-mode device instance. */
6233	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
6234	/** Ring-0 pointer to the raw-mode instance data. */
6235	RTR0PTR pvInstanceDataForRCR0;
6236
6237	/** PCI device structure size. */
6238	uint32_t cbPciDev;
6239	/** Number of PCI devices in apPciDevs. */
6240	uint32_t cPciDevs;
6241	/** Pointer to the PCI devices for this device.
6242	* (Allocated after the shared instance data.)
6243	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6244	* two devices ever needing it can use cbPciDev and do the address
6245	* calculations that for entries 8+. */
6246	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6247
6248	/** Align the internal data more naturally. */
6249	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
6250
6251	/** Internal data. */
6252	union
6253	{
6254	#ifdef PDMDEVINSINT_DECLARED
6255	PDMDEVINSINTR0 s;
6256	#endif
6257	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
6258	} Internal;
6259
6260	/** Device instance data for ring-0. The size of this area is defined
6261	* in the PDMDEVREG::cbInstanceR0 field. */
6262	char achInstanceData[8];
6263	} PDMDEVINSR0;
6264
6265	/** Current PDMDEVINSR0 version number. */
6266	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
6267
6268
6269	/**
6270	* PDM raw-mode device instance.
6271	*/
6272	typedef struct PDMDEVINSRC
6273	{
6274	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
6275	uint32_t u32Version;
6276	/** Device instance number. */
6277	uint32_t iInstance;
6278
6279	/** Pointer the HC PDM Device API. */
6280	PCPDMDEVHLPRC pHlpRC;
6281	/** Pointer to the shared device instance data. */
6282	RTRGPTR pvInstanceDataRC;
6283	/** Pointer to the device instance data for raw-mode. */
6284	RTRGPTR pvInstanceDataForRC;
6285	/** The critical section for the device.
6286	*
6287	* TM and IOM will enter this critical section before calling into the device
6288	* code. PDM will when doing power on, power off, reset, suspend and resume
6289	* notifications. SSM will currently not, but this will be changed later on.
6290	*
6291	* The device gets a critical section automatically assigned to it before
6292	* the constructor is called. If the constructor wishes to use a different
6293	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6294	* very early on.
6295	*/
6296	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
6297	/** Pointer to the raw-mode device registration structure. */
6298	RGPTRTYPE(PCPDMDEVREGRC) pReg;
6299
6300	/** PCI device structure size. */
6301	uint32_t cbPciDev;
6302	/** Number of PCI devices in apPciDevs. */
6303	uint32_t cPciDevs;
6304	/** Pointer to the PCI devices for this device.
6305	* (Allocated after the shared instance data.) */
6306	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6307
6308	/** Align the internal data more naturally. */
6309	uint32_t au32Padding[14];
6310
6311	/** Internal data. */
6312	union
6313	{
6314	#ifdef PDMDEVINSINT_DECLARED
6315	PDMDEVINSINTRC s;
6316	#endif
6317	uint8_t padding[0x10];
6318	} Internal;
6319
6320	/** Device instance data for ring-0. The size of this area is defined
6321	* in the PDMDEVREG::cbInstanceR0 field. */
6322	char achInstanceData[8];
6323	} PDMDEVINSRC;
6324
6325	/** Current PDMDEVINSR0 version number. */
6326	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
6327
6328
6329	/** @def PDM_DEVINS_VERSION
6330	* Current PDMDEVINS version number. */
6331	/** @typedef PDMDEVINS
6332	* The device instance structure for the current context. */
6333	#ifdef IN_RING3
6334	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
6335	typedef PDMDEVINSR3 PDMDEVINS;
6336	#elif defined(IN_RING0)
6337	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
6338	typedef PDMDEVINSR0 PDMDEVINS;
6339	#elif defined(IN_RC)
6340	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
6341	typedef PDMDEVINSRC PDMDEVINS;
6342	#else
6343	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
6344	#endif
6345
6346	/**
6347	* Get the pointer to an PCI device.
6348	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6349	*/
6350	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
6351	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
6352	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
6353
6354	/**
6355	* Calc the pointer to of a given PCI device.
6356	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6357	*/
6358	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
6359	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
6360	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
6361	: (PPDMPCIDEV)NULL )
6362
6363
6364	/**
6365	* Checks the structure versions of the device instance and device helpers,
6366	* returning if they are incompatible.
6367	*
6368	* This is for use in the constructor.
6369	*
6370	* @param pDevIns The device instance pointer.
6371	*/
6372	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
6373	do \
6374	{ \
6375	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6376	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6377	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6378	VERR_PDM_DEVINS_VERSION_MISMATCH); \
6379	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6380	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6381	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
6382	} while (0)
6383
6384	/**
6385	* Quietly checks the structure versions of the device instance and device
6386	* helpers, returning if they are incompatible.
6387	*
6388	* This is for use in the destructor.
6389	*
6390	* @param pDevIns The device instance pointer.
6391	*/
6392	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
6393	do \
6394	{ \
6395	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6396	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
6397	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
6398	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
6399	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
6400	} while (0)
6401
6402	/**
6403	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
6404	* constructor - returns on failure.
6405	*
6406	* This should be invoked after having initialized the instance data
6407	* sufficiently for the correct operation of the destructor. The destructor is
6408	* always called!
6409	*
6410	* @param pDevIns Pointer to the PDM device instance.
6411	* @param pszValidValues Patterns describing the valid value names. See
6412	* RTStrSimplePatternMultiMatch for details on the
6413	* pattern syntax.
6414	* @param pszValidNodes Patterns describing the valid node (key) names.
6415	* Pass empty string if no valid nodes.
6416	*/
6417	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
6418	do \
6419	{ \
6420	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
6421	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
6422	if (RT_SUCCESS(rcValCfg)) \
6423	{ /* likely */ } else return rcValCfg; \
6424	} while (0)
6425
6426	/** @def PDMDEV_ASSERT_EMT
6427	* Assert that the current thread is the emulation thread.
6428	*/
6429	#ifdef VBOX_STRICT
6430	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6431	#else
6432	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
6433	#endif
6434
6435	/** @def PDMDEV_ASSERT_OTHER
6436	* Assert that the current thread is NOT the emulation thread.
6437	*/
6438	#ifdef VBOX_STRICT
6439	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6440	#else
6441	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
6442	#endif
6443
6444	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
6445	* Assert that the current thread is owner of the VM lock.
6446	*/
6447	#ifdef VBOX_STRICT
6448	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6449	#else
6450	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
6451	#endif
6452
6453	/** @def PDMDEV_SET_ERROR
6454	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
6455	*/
6456	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
6457	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
6458
6459	/** @def PDMDEV_SET_RUNTIME_ERROR
6460	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
6461	*/
6462	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
6463	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
6464
6465	/** @def PDMDEVINS_2_RCPTR
6466	* Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
6467	*/
6468	#ifdef IN_RC
6469	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
6470	#else
6471	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
6472	#endif
6473
6474	/** @def PDMDEVINS_2_R3PTR
6475	* Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
6476	*/
6477	#ifdef IN_RING3
6478	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
6479	#else
6480	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
6481	#endif
6482
6483	/** @def PDMDEVINS_2_R0PTR
6484	* Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
6485	*/
6486	#ifdef IN_RING0
6487	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
6488	#else
6489	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
6490	#endif
6491
6492	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
6493	* Converts a PDM device instance data pointer to a ring-0 one.
6494	* @deprecated
6495	*/
6496	#ifdef IN_RING0
6497	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
6498	#else
6499	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
6500	#endif
6501
6502
6503	/** @def PDMDEVINS_2_DATA
6504	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
6505	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
6506	*
6507	* @note Do no use this macro in common code working on a core structure which
6508	* device specific code has expanded.
6509	*/
6510	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6511	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
6512	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6513	{ \
6514	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
6515	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
6516	return pLambdaRet; \
6517	}(a_pDevIns))
6518	#else
6519	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
6520	#endif
6521
6522	/** @def PDMDEVINS_2_DATA_CC
6523	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
6524	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
6525	*
6526	* @note Do no use this macro in common code working on a core structure which
6527	* device specific code has expanded.
6528	*/
6529	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6530	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
6531	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6532	{ \
6533	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
6534	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
6535	return pLambdaRet; \
6536	}(a_pDevIns))
6537	#else
6538	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
6539	#endif
6540
6541
6542	#ifdef IN_RING3
6543
6544	/**
6545	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
6546	*/
6547	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6548	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
6549	PIOMIOPORTHANDLE phIoPorts)
6550	{
6551	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6552	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6553	if (RT_SUCCESS(rc))
6554	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6555	return rc;
6556	}
6557
6558	/**
6559	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
6560	*/
6561	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6562	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6563	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6564	{
6565	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6566	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6567	if (RT_SUCCESS(rc))
6568	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6569	return rc;
6570	}
6571
6572	/**
6573	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
6574	*/
6575	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6576	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6577	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6578	{
6579	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6580	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6581	if (RT_SUCCESS(rc))
6582	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6583	return rc;
6584	}
6585
6586	/**
6587	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
6588	*/
6589	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6590	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6591	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6592	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6593	{
6594	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6595	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6596	if (RT_SUCCESS(rc))
6597	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6598	return rc;
6599	}
6600
6601	/**
6602	* @sa PDMDevHlpIoPortCreateEx
6603	*/
6604	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6605	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6606	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6607	{
6608	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
6609	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6610	}
6611
6612
6613	/**
6614	* @sa PDMDevHlpIoPortCreateEx
6615	*/
6616	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6617	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6618	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6619	{
6620	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6621	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6622	}
6623
6624	/**
6625	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6626	*/
6627	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6628	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6629	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6630	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6631	{
6632	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6633	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6634	}
6635
6636	/**
6637	* @copydoc PDMDEVHLPR3::pfnIoPortMap
6638	*/
6639	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6640	{
6641	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6642	}
6643
6644	/**
6645	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6646	*/
6647	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6648	{
6649	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6650	}
6651
6652	/**
6653	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6654	*/
6655	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6656	{
6657	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6658	}
6659
6660	/**
6661	* @copydoc PDMDEVHLPR3::pfnIoPortRead
6662	*/
6663	DECLINLINE(VBOXSTRICTRC) PDMDevHlpIoPortRead(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue)
6664	{
6665	return pDevIns->pHlpR3->pfnIoPortRead(pDevIns, Port, pu32Value, cbValue);
6666	}
6667
6668	/**
6669	* @copydoc PDMDEVHLPR3::pfnIoPortWrite
6670	*/
6671	DECLINLINE(VBOXSTRICTRC) PDMDevHlpIoPortWrite(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t u32Value, size_t cbValue)
6672	{
6673	return pDevIns->pHlpR3->pfnIoPortWrite(pDevIns, Port, u32Value, cbValue);
6674	}
6675
6676
6677	#endif /* IN_RING3 */
6678	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6679
6680	/**
6681	* @sa PDMDevHlpIoPortSetUpContextEx
6682	*/
6683	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6684	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6685	{
6686	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6687	}
6688
6689	/**
6690	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6691	*/
6692	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6693	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6694	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6695	{
6696	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6697	}
6698
6699	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6700	#ifdef IN_RING3
6701
6702	/**
6703	* @sa PDMDevHlpMmioCreateEx
6704	*/
6705	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6706	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6707	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6708	{
6709	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6710	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6711	}
6712
6713	/**
6714	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6715	*/
6716	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6717	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6718	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6719	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6720	{
6721	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6722	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6723	}
6724
6725	/**
6726	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6727	*/
6728	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6729	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6730	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6731	{
6732	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6733	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6734	if (RT_SUCCESS(rc))
6735	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6736	return rc;
6737	}
6738
6739	/**
6740	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6741	*/
6742	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6743	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6744	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6745	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6746	{
6747	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6748	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6749	if (RT_SUCCESS(rc))
6750	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6751	return rc;
6752	}
6753
6754	/**
6755	* @copydoc PDMDEVHLPR3::pfnMmioMap
6756	*/
6757	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6758	{
6759	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6760	}
6761
6762	/**
6763	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6764	*/
6765	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6766	{
6767	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6768	}
6769
6770	/**
6771	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6772	*/
6773	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6774	{
6775	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6776	}
6777
6778	/**
6779	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6780	*/
6781	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6782	{
6783	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6784	}
6785
6786	#endif /* IN_RING3 */
6787	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6788
6789	/**
6790	* @sa PDMDevHlpMmioSetUpContextEx
6791	*/
6792	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6793	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6794	{
6795	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6796	}
6797
6798	/**
6799	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6800	*/
6801	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6802	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6803	{
6804	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6805	}
6806
6807	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6808	#ifdef IN_RING3
6809
6810	/**
6811	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6812	*/
6813	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6814	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6815	{
6816	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6817	}
6818
6819	/**
6820	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6821	*/
6822	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6823	{
6824	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6825	}
6826
6827	/**
6828	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6829	*/
6830	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6831	{
6832	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6833	}
6834
6835	/**
6836	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6837	*/
6838	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6839	{
6840	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6841	}
6842
6843	/**
6844	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6845	*/
6846	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6847	{
6848	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6849	}
6850
6851	/**
6852	* @copydoc PDMDEVHLPR3::pfnMmio2QueryAndResetDirtyBitmap
6853	*/
6854	DECLINLINE(int) PDMDevHlpMmio2QueryAndResetDirtyBitmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6855	void *pvBitmap, size_t cbBitmap)
6856	{
6857	return pDevIns->pHlpR3->pfnMmio2QueryAndResetDirtyBitmap(pDevIns, hRegion, pvBitmap, cbBitmap);
6858	}
6859
6860	/**
6861	* Reset the dirty bitmap tracking for an MMIO2 region.
6862	*
6863	* The MMIO2 region must have been created with the
6864	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
6865	*
6866	* @returns VBox status code.
6867	* @param pDevIns The device instance.
6868	* @param hRegion The MMIO2 region handle.
6869	*/
6870	DECLINLINE(int) PDMDevHlpMmio2ResetDirtyBitmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6871	{
6872	return pDevIns->pHlpR3->pfnMmio2QueryAndResetDirtyBitmap(pDevIns, hRegion, NULL, 0);
6873	}
6874
6875	/**
6876	* @copydoc PDMDEVHLPR3::pfnMmio2ControlDirtyPageTracking
6877	*/
6878	DECLINLINE(int) PDMDevHlpMmio2ControlDirtyPageTracking(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, bool fEnabled)
6879	{
6880	return pDevIns->pHlpR3->pfnMmio2ControlDirtyPageTracking(pDevIns, hRegion, fEnabled);
6881	}
6882
6883	#endif /* IN_RING3 */
6884
6885	/**
6886	* @copydoc PDMDEVHLPR3::pfnMmioMapMmio2Page
6887	*/
6888	DECLINLINE(int) PDMDevHlpMmioMapMmio2Page(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6889	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags)
6890	{
6891	return pDevIns->CTX_SUFF(pHlp)->pfnMmioMapMmio2Page(pDevIns, hRegion, offRegion, hMmio2, offMmio2, fPageFlags);
6892	}
6893
6894	/**
6895	* @copydoc PDMDEVHLPR3::pfnMmioResetRegion
6896	*/
6897	DECLINLINE(int) PDMDevHlpMmioResetRegion(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6898	{
6899	return pDevIns->CTX_SUFF(pHlp)->pfnMmioResetRegion(pDevIns, hRegion);
6900	}
6901
6902	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6903
6904	/**
6905	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6906	*/
6907	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6908	size_t offSub, size_t cbSub, void **ppvMapping)
6909	{
6910	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6911	}
6912
6913	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6914	#ifdef IN_RING3
6915
6916	/**
6917	* @copydoc PDMDEVHLPR3::pfnROMRegister
6918	*/
6919	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6920	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6921	{
6922	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6923	}
6924
6925	/**
6926	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6927	*/
6928	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6929	{
6930	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6931	}
6932
6933	/**
6934	* Register a save state data unit.
6935	*
6936	* @returns VBox status.
6937	* @param pDevIns The device instance.
6938	* @param uVersion Data layout version number.
6939	* @param cbGuess The approximate amount of data in the unit.
6940	* Only for progress indicators.
6941	* @param pfnSaveExec Execute save callback, optional.
6942	* @param pfnLoadExec Execute load callback, optional.
6943	*/
6944	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6945	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6946	{
6947	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6948	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6949	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6950	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6951	}
6952
6953	/**
6954	* Register a save state data unit with a live save callback as well.
6955	*
6956	* @returns VBox status.
6957	* @param pDevIns The device instance.
6958	* @param uVersion Data layout version number.
6959	* @param cbGuess The approximate amount of data in the unit.
6960	* Only for progress indicators.
6961	* @param pfnLiveExec Execute live callback, optional.
6962	* @param pfnSaveExec Execute save callback, optional.
6963	* @param pfnLoadExec Execute load callback, optional.
6964	*/
6965	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6966	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6967	{
6968	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6969	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6970	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6971	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6972	}
6973
6974	/**
6975	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6976	*/
6977	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6978	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6979	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6980	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6981	{
6982	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6983	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6984	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6985	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6986	}
6987
6988	/**
6989	* @copydoc PDMDEVHLPR3::pfnSSMRegisterLegacy
6990	*/
6991	DECLINLINE(int) PDMDevHlpSSMRegisterLegacy(PPDMDEVINS pDevIns, const char *pszOldName, PFNSSMDEVLOADPREP pfnLoadPrep,
6992	PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6993	{
6994	return pDevIns->pHlpR3->pfnSSMRegisterLegacy(pDevIns, pszOldName, pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6995	}
6996
6997	/**
6998	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6999	*/
7000	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
7001	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
7002	{
7003	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
7004	}
7005
7006	#endif /* IN_RING3 */
7007
7008	/**
7009	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
7010	*/
7011	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
7012	{
7013	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
7014	}
7015
7016	/**
7017	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
7018	*/
7019	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
7020	{
7021	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
7022	}
7023
7024	/**
7025	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
7026	*/
7027	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
7028	{
7029	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
7030	}
7031
7032	/**
7033	* @copydoc PDMDEVHLPR3::pfnTimerGet
7034	*/
7035	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7036	{
7037	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
7038	}
7039
7040	/**
7041	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
7042	*/
7043	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7044	{
7045	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
7046	}
7047
7048	/**
7049	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
7050	*/
7051	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7052	{
7053	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
7054	}
7055
7056	/**
7057	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
7058	*/
7059	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7060	{
7061	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
7062	}
7063
7064	/**
7065	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
7066	*/
7067	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7068	{
7069	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
7070	}
7071
7072	/**
7073	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
7074	*/
7075	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
7076	{
7077	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
7078	}
7079
7080	/**
7081	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
7082	*/
7083	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
7084	{
7085	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
7086	}
7087
7088	/**
7089	* @copydoc PDMDEVHLPR3::pfnTimerSet
7090	*/
7091	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
7092	{
7093	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
7094	}
7095
7096	/**
7097	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
7098	*/
7099	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
7100	{
7101	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
7102	}
7103
7104	/**
7105	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
7106	*/
7107	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
7108	{
7109	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
7110	}
7111
7112	/**
7113	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
7114	*/
7115	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
7116	{
7117	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
7118	}
7119
7120	/**
7121	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
7122	*/
7123	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
7124	{
7125	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
7126	}
7127
7128	/**
7129	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
7130	*/
7131	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
7132	{
7133	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
7134	}
7135
7136	/**
7137	* @copydoc PDMDEVHLPR3::pfnTimerStop
7138	*/
7139	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7140	{
7141	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
7142	}
7143
7144	/**
7145	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
7146	*/
7147	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7148	{
7149	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
7150	}
7151
7152	/**
7153	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
7154	*/
7155	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
7156	{
7157	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
7158	}
7159
7160	#ifdef IN_RING3
7161
7162	/**
7163	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
7164	*/
7165	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
7166	{
7167	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
7168	}
7169
7170	/**
7171	* @copydoc PDMDEVHLPR3::pfnTimerSave
7172	*/
7173	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
7174	{
7175	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
7176	}
7177
7178	/**
7179	* @copydoc PDMDEVHLPR3::pfnTimerLoad
7180	*/
7181	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
7182	{
7183	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
7184	}
7185
7186	/**
7187	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
7188	*/
7189	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7190	{
7191	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
7192	}
7193
7194	/**
7195	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
7196	*/
7197	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
7198	{
7199	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
7200	}
7201
7202	#endif
7203
7204	/**
7205	* Read physical memory - unknown data usage.
7206	*
7207	* @returns VINF_SUCCESS (for now).
7208	* @param pDevIns The device instance.
7209	* @param GCPhys Physical address start reading from.
7210	* @param pvBuf Where to put the read bits.
7211	* @param cbRead How many bytes to read.
7212	* @thread Any thread, but the call may involve the emulation thread.
7213	*/
7214	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7215	{
7216	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7217	}
7218
7219	/**
7220	* Write to physical memory - unknown data usage.
7221	*
7222	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7223	* @param pDevIns The device instance.
7224	* @param GCPhys Physical address to write to.
7225	* @param pvBuf What to write.
7226	* @param cbWrite How many bytes to write.
7227	* @thread Any thread, but the call may involve the emulation thread.
7228	*/
7229	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7230	{
7231	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7232	}
7233
7234	/**
7235	* Read physical memory - reads meta data processed by the device.
7236	*
7237	* @returns VINF_SUCCESS (for now).
7238	* @param pDevIns The device instance.
7239	* @param GCPhys Physical address start reading from.
7240	* @param pvBuf Where to put the read bits.
7241	* @param cbRead How many bytes to read.
7242	* @thread Any thread, but the call may involve the emulation thread.
7243	*/
7244	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7245	{
7246	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7247	}
7248
7249	/**
7250	* Write to physical memory - written data was created/altered by the device.
7251	*
7252	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7253	* @param pDevIns The device instance.
7254	* @param GCPhys Physical address to write to.
7255	* @param pvBuf What to write.
7256	* @param cbWrite How many bytes to write.
7257	* @thread Any thread, but the call may involve the emulation thread.
7258	*/
7259	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7260	{
7261	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7262	}
7263
7264	/**
7265	* Read physical memory - read data will not be touched by the device.
7266	*
7267	* @returns VINF_SUCCESS (for now).
7268	* @param pDevIns The device instance.
7269	* @param GCPhys Physical address start reading from.
7270	* @param pvBuf Where to put the read bits.
7271	* @param cbRead How many bytes to read.
7272	* @thread Any thread, but the call may involve the emulation thread.
7273	*/
7274	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7275	{
7276	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7277	}
7278
7279	/**
7280	* Write to physical memory - written data was not touched/created by the device.
7281	*
7282	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7283	* @param pDevIns The device instance.
7284	* @param GCPhys Physical address to write to.
7285	* @param pvBuf What to write.
7286	* @param cbWrite How many bytes to write.
7287	* @thread Any thread, but the call may involve the emulation thread.
7288	*/
7289	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7290	{
7291	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7292	}
7293
7294	#ifdef IN_RING3
7295
7296	/**
7297	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
7298	*/
7299	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
7300	{
7301	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
7302	}
7303
7304	/**
7305	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
7306	*/
7307	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
7308	PPGMPAGEMAPLOCK pLock)
7309	{
7310	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
7311	}
7312
7313	/**
7314	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
7315	*/
7316	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
7317	{
7318	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
7319	}
7320
7321	/**
7322	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
7323	*/
7324	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7325	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
7326	{
7327	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7328	}
7329
7330	/**
7331	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
7332	*/
7333	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7334	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
7335	{
7336	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7337	}
7338
7339	/**
7340	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
7341	*/
7342	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
7343	{
7344	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
7345	}
7346
7347	/**
7348	* @copydoc PDMDEVHLPR3::pfnPhysIsGCPhysNormal
7349	*/
7350	DECLINLINE(bool) PDMDevHlpPhysIsGCPhysNormal(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
7351	{
7352	return pDevIns->CTX_SUFF(pHlp)->pfnPhysIsGCPhysNormal(pDevIns, GCPhys);
7353	}
7354
7355	/**
7356	* @copydoc PDMDEVHLPR3::pfnPhysChangeMemBalloon
7357	*/
7358	DECLINLINE(int) PDMDevHlpPhysChangeMemBalloon(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
7359	{
7360	return pDevIns->CTX_SUFF(pHlp)->pfnPhysChangeMemBalloon(pDevIns, fInflate, cPages, paPhysPage);
7361	}
7362
7363	/**
7364	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
7365	*/
7366	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
7367	{
7368	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
7369	}
7370
7371	/**
7372	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestScalableBusFrequency
7373	*/
7374	DECLINLINE(uint64_t) PDMDevHlpCpuGetGuestScalableBusFrequency(PPDMDEVINS pDevIns)
7375	{
7376	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestScalableBusFrequency(pDevIns);
7377	}
7378
7379	/**
7380	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
7381	*/
7382	DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth)
7383	{
7384	pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
7385	}
7386
7387	/**
7388	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
7389	*/
7390	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
7391	{
7392	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
7393	}
7394
7395	/**
7396	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
7397	*/
7398	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
7399	{
7400	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
7401	}
7402
7403	/**
7404	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
7405	*/
7406	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
7407	{
7408	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
7409	}
7410
7411	/**
7412	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
7413	*/
7414	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
7415	{
7416	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
7417	}
7418
7419	/**
7420	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
7421	*/
7422	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
7423	{
7424	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
7425	}
7426
7427	/**
7428	* Allocating string printf.
7429	*
7430	* @returns Pointer to the string.
7431	* @param pDevIns The device instance.
7432	* @param enmTag The statistics tag.
7433	* @param pszFormat The format string.
7434	* @param ... Format arguments.
7435	*/
7436	DECLINLINE(char ) RT_IPRT_FORMAT_ATTR(2, 3) PDMDevHlpMMHeapAPrintf(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, ...)
7437	{
7438	va_list va;
7439	va_start(va, pszFormat);
7440	char *psz = pDevIns->pHlpR3->pfnMMHeapAPrintfV(pDevIns, enmTag, pszFormat, va);
7441	va_end(va);
7442
7443	return psz;
7444	}
7445
7446	/**
7447	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
7448	*/
7449	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
7450	{
7451	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
7452	}
7453
7454	/**
7455	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSize
7456	*/
7457	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSize(PPDMDEVINS pDevIns)
7458	{
7459	return pDevIns->pHlpR3->pfnMMPhysGetRamSize(pDevIns);
7460	}
7461
7462	/**
7463	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeBelow4GB
7464	*/
7465	DECLINLINE(uint32_t) PDMDevHlpMMPhysGetRamSizeBelow4GB(PPDMDEVINS pDevIns)
7466	{
7467	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeBelow4GB(pDevIns);
7468	}
7469
7470	/**
7471	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeAbove4GB
7472	*/
7473	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSizeAbove4GB(PPDMDEVINS pDevIns)
7474	{
7475	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeAbove4GB(pDevIns);
7476	}
7477	#endif /* IN_RING3 */
7478
7479	/**
7480	* @copydoc PDMDEVHLPR3::pfnVMState
7481	*/
7482	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
7483	{
7484	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
7485	}
7486
7487	#ifdef IN_RING3
7488
7489	/**
7490	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
7491	*/
7492	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
7493	{
7494	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
7495	}
7496
7497	/**
7498	* Set the VM error message
7499	*
7500	* @returns rc.
7501	* @param pDevIns The device instance.
7502	* @param rc VBox status code.
7503	* @param SRC_POS Use RT_SRC_POS.
7504	* @param pszFormat Error message format string.
7505	* @param ... Error message arguments.
7506	* @sa VMSetError
7507	*/
7508	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
7509	const char *pszFormat, ...)
7510	{
7511	va_list va;
7512	va_start(va, pszFormat);
7513	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
7514	va_end(va);
7515	return rc;
7516	}
7517
7518	/**
7519	* Set the VM runtime error message
7520	*
7521	* @returns VBox status code.
7522	* @param pDevIns The device instance.
7523	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
7524	* @param pszErrorId Error ID string.
7525	* @param pszFormat Error message format string.
7526	* @param ... Error message arguments.
7527	* @sa VMSetRuntimeError
7528	*/
7529	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
7530	const char *pszFormat, ...)
7531	{
7532	va_list va;
7533	int rc;
7534	va_start(va, pszFormat);
7535	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
7536	va_end(va);
7537	return rc;
7538	}
7539
7540	/**
7541	* @copydoc PDMDEVHLPR3::pfnVMWaitForDeviceReady
7542	*/
7543	DECLINLINE(int) PDMDevHlpVMWaitForDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7544	{
7545	return pDevIns->CTX_SUFF(pHlp)->pfnVMWaitForDeviceReady(pDevIns, idCpu);
7546	}
7547
7548	/**
7549	* @copydoc PDMDEVHLPR3::pfnVMNotifyCpuDeviceReady
7550	*/
7551	DECLINLINE(int) PDMDevHlpVMNotifyCpuDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7552	{
7553	return pDevIns->CTX_SUFF(pHlp)->pfnVMNotifyCpuDeviceReady(pDevIns, idCpu);
7554	}
7555
7556	/**
7557	* Convenience wrapper for VMR3ReqCallU.
7558	*
7559	* This assumes (1) you're calling a function that returns an VBox status code
7560	* and that you do not wish to wait for it to complete.
7561	*
7562	* @returns VBox status code returned by VMR3ReqCallVU.
7563	*
7564	* @param pDevIns The device instance.
7565	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7566	* one of the following special values:
7567	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7568	* @param pfnFunction Pointer to the function to call.
7569	* @param cArgs Number of arguments following in the ellipsis.
7570	* @param ... Argument list.
7571	*
7572	* @remarks See remarks on VMR3ReqCallVU.
7573	*/
7574	DECLINLINE(int) PDMDevHlpVMReqCallNoWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7575	{
7576	va_list Args;
7577	va_start(Args, cArgs);
7578	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqCallNoWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7579	va_end(Args);
7580	return rc;
7581	}
7582
7583	/**
7584	* Convenience wrapper for VMR3ReqCallU.
7585	*
7586	* This assumes (1) you're calling a function that returns void, (2) that you
7587	* wish to wait for ever for it to return, and (3) that it's priority request
7588	* that can be safely be handled during async suspend and power off.
7589	*
7590	* @returns VBox status code of VMR3ReqCallVU.
7591	*
7592	* @param pDevIns The device instance.
7593	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7594	* one of the following special values:
7595	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7596	* @param pfnFunction Pointer to the function to call.
7597	* @param cArgs Number of arguments following in the ellipsis.
7598	* @param ... Argument list.
7599	*
7600	* @remarks See remarks on VMR3ReqCallVU.
7601	*/
7602	DECLINLINE(int) PDMDevHlpVMReqPriorityCallWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7603	{
7604	va_list Args;
7605	va_start(Args, cArgs);
7606	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqPriorityCallWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7607	va_end(Args);
7608	return rc;
7609	}
7610
7611	#endif /* IN_RING3 */
7612
7613	/**
7614	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
7615	*
7616	* @returns VBox status code which must be passed up to the VMM. This will be
7617	* VINF_SUCCESS in non-strict builds.
7618	* @param pDevIns The device instance.
7619	* @param SRC_POS Use RT_SRC_POS.
7620	* @param pszFormat Message. (optional)
7621	* @param ... Message parameters.
7622	*/
7623	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
7624	{
7625	#ifdef VBOX_STRICT
7626	# ifdef IN_RING3
7627	int rc;
7628	va_list args;
7629	va_start(args, pszFormat);
7630	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
7631	va_end(args);
7632	return rc;
7633	# else
7634	NOREF(pDevIns);
7635	NOREF(pszFile);
7636	NOREF(iLine);
7637	NOREF(pszFunction);
7638	NOREF(pszFormat);
7639	return VINF_EM_DBG_STOP;
7640	# endif
7641	#else
7642	NOREF(pDevIns);
7643	NOREF(pszFile);
7644	NOREF(iLine);
7645	NOREF(pszFunction);
7646	NOREF(pszFormat);
7647	return VINF_SUCCESS;
7648	#endif
7649	}
7650
7651	#ifdef IN_RING3
7652
7653	/**
7654	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
7655	*/
7656	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
7657	{
7658	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
7659	}
7660
7661	/**
7662	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
7663	*/
7664	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
7665	{
7666	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
7667	}
7668
7669	/**
7670	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
7671	*/
7672	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
7673	{
7674	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
7675	}
7676
7677	/**
7678	* @copydoc PDMDEVHLPR3::pfnDBGFReportBugCheck
7679	*/
7680	DECLINLINE(VBOXSTRICTRC) PDMDevHlpDBGFReportBugCheck(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
7681	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4)
7682	{
7683	return pDevIns->pHlpR3->pfnDBGFReportBugCheck(pDevIns, enmEvent, uBugCheck, uP1, uP2, uP3, uP4);
7684	}
7685
7686	/**
7687	* @copydoc PDMDEVHLPR3::pfnDBGFCoreWrite
7688	*/
7689	DECLINLINE(int) PDMDevHlpDBGFCoreWrite(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile)
7690	{
7691	return pDevIns->pHlpR3->pfnDBGFCoreWrite(pDevIns, pszFilename, fReplaceFile);
7692	}
7693
7694	/**
7695	* @copydoc PDMDEVHLPR3::pfnDBGFInfoLogHlp
7696	*/
7697	DECLINLINE(PCDBGFINFOHLP) PDMDevHlpDBGFInfoLogHlp(PPDMDEVINS pDevIns)
7698	{
7699	return pDevIns->pHlpR3->pfnDBGFInfoLogHlp(pDevIns);
7700	}
7701
7702	/**
7703	* @copydoc PDMDEVHLPR3::pfnDBGFRegNmQueryU64
7704	*/
7705	DECLINLINE(int) PDMDevHlpDBGFRegNmQueryU64(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64)
7706	{
7707	return pDevIns->pHlpR3->pfnDBGFRegNmQueryU64(pDevIns, idDefCpu, pszReg, pu64);
7708	}
7709
7710	/**
7711	* Format a set of registers.
7712	*
7713	* This is restricted to registers from one CPU, that specified by @a idCpu.
7714	*
7715	* @returns VBox status code.
7716	* @param pDevIns The device instance.
7717	* @param idCpu The CPU ID of any CPU registers that may be
7718	* printed, pass VMCPUID_ANY if not applicable.
7719	* @param pszBuf The output buffer.
7720	* @param cbBuf The size of the output buffer.
7721	* @param pszFormat The format string. Register names are given by
7722	* %VR{name}, they take no arguments.
7723	* @param ... Argument list.
7724	*/
7725	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpDBGFRegPrintf(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
7726	const char *pszFormat, ...)
7727	{
7728	va_list Args;
7729	va_start(Args, pszFormat);
7730	int rc = pDevIns->pHlpR3->pfnDBGFRegPrintfV(pDevIns, idCpu, pszBuf, cbBuf, pszFormat, Args);
7731	va_end(Args);
7732	return rc;
7733	}
7734
7735	/**
7736	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
7737	*/
7738	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
7739	{
7740	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
7741	}
7742
7743	/**
7744	* Same as pfnSTAMRegister except that the name is specified in a
7745	* RTStrPrintf like fashion.
7746	*
7747	* @param pDevIns Device instance of the DMA.
7748	* @param pvSample Pointer to the sample.
7749	* @param enmType Sample type. This indicates what pvSample is
7750	* pointing at.
7751	* @param enmVisibility Visibility type specifying whether unused
7752	* statistics should be visible or not.
7753	* @param enmUnit Sample unit.
7754	* @param pszDesc Sample description.
7755	* @param pszName Sample name format string, unix path style. If
7756	* this does not start with a '/', the default
7757	* prefix will be prepended, otherwise it will be
7758	* used as-is.
7759	* @param ... Arguments to the format string.
7760	*/
7761	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
7762	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
7763	const char pszDesc, const char pszName, ...)
7764	{
7765	va_list va;
7766	va_start(va, pszName);
7767	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
7768	va_end(va);
7769	}
7770
7771	/**
7772	* @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
7773	*/
7774	DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
7775	{
7776	return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
7777	}
7778
7779	/**
7780	* Registers the device with the default PCI bus.
7781	*
7782	* @returns VBox status code.
7783	* @param pDevIns The device instance.
7784	* @param pPciDev The PCI device structure.
7785	* This must be kept in the instance data.
7786	* The PCI configuration must be initialized before registration.
7787	*/
7788	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
7789	{
7790	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
7791	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
7792	}
7793
7794	/**
7795	* @copydoc PDMDEVHLPR3::pfnPCIRegister
7796	*/
7797	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
7798	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
7799	{
7800	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
7801	}
7802
7803	/**
7804	* Initialize MSI emulation support for the first PCI device.
7805	*
7806	* @returns VBox status code.
7807	* @param pDevIns The device instance.
7808	* @param pMsiReg MSI emulation registration structure.
7809	*/
7810	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
7811	{
7812	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
7813	}
7814
7815	/**
7816	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
7817	*/
7818	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
7819	{
7820	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
7821	}
7822
7823	/**
7824	* Registers a I/O port region for the default PCI device.
7825	*
7826	* @returns VBox status code.
7827	* @param pDevIns The device instance.
7828	* @param iRegion The region number.
7829	* @param cbRegion Size of the region.
7830	* @param hIoPorts Handle to the I/O port region.
7831	*/
7832	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
7833	{
7834	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7835	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
7836	}
7837
7838	/**
7839	* Registers a I/O port region for the default PCI device, custom map/unmap.
7840	*
7841	* @returns VBox status code.
7842	* @param pDevIns The device instance.
7843	* @param iRegion The region number.
7844	* @param cbRegion Size of the region.
7845	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7846	* callback will be invoked holding only the PDM lock.
7847	* The device lock will _not_ be taken (due to lock
7848	* order).
7849	*/
7850	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7851	PFNPCIIOREGIONMAP pfnMapUnmap)
7852	{
7853	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7854	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7855	UINT64_MAX, pfnMapUnmap);
7856	}
7857
7858	/**
7859	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7860	* and registering an I/O port region for the default PCI device.
7861	*
7862	* @returns VBox status code.
7863	* @param pDevIns The device instance to register the ports with.
7864	* @param cPorts The count of I/O ports in the region (the size).
7865	* @param iPciRegion The PCI device region.
7866	* @param pfnOut Pointer to function which is gonna handle OUT
7867	* operations. Optional.
7868	* @param pfnIn Pointer to function which is gonna handle IN operations.
7869	* Optional.
7870	* @param pvUser User argument to pass to the callbacks.
7871	* @param pszDesc Pointer to description string. This must not be freed.
7872	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7873	* coverage is allowed. This must not be freed.
7874	* @param phIoPorts Where to return the I/O port range handle.
7875	*
7876	*/
7877	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7878	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7879	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7880
7881	{
7882	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7883	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7884	if (RT_SUCCESS(rc))
7885	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7886	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7887	phIoPorts, NULL /pfnMapUnmap*/);
7888	return rc;
7889	}
7890
7891	/**
7892	* Registers an MMIO region for the default PCI device.
7893	*
7894	* @returns VBox status code.
7895	* @param pDevIns The device instance.
7896	* @param iRegion The region number.
7897	* @param cbRegion Size of the region.
7898	* @param enmType PCI_ADDRESS_SPACE_MEM or
7899	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7900	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7901	* @param hMmioRegion Handle to the MMIO region.
7902	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7903	* callback will be invoked holding only the PDM lock.
7904	* The device lock will _not_ be taken (due to lock
7905	* order).
7906	*/
7907	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7908	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7909	{
7910	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7911	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7912	hMmioRegion, pfnMapUnmap);
7913	}
7914
7915	/**
7916	* Registers an MMIO region for the default PCI device, extended version.
7917	*
7918	* @returns VBox status code.
7919	* @param pDevIns The device instance.
7920	* @param pPciDev The PCI device structure.
7921	* @param iRegion The region number.
7922	* @param cbRegion Size of the region.
7923	* @param enmType PCI_ADDRESS_SPACE_MEM or
7924	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7925	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7926	* @param hMmioRegion Handle to the MMIO region.
7927	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7928	* callback will be invoked holding only the PDM lock.
7929	* The device lock will _not_ be taken (due to lock
7930	* order).
7931	*/
7932	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7933	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7934	PFNPCIIOREGIONMAP pfnMapUnmap)
7935	{
7936	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7937	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7938	hMmioRegion, pfnMapUnmap);
7939	}
7940
7941	/**
7942	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7943	* and registering an MMIO region for the default PCI device.
7944	*
7945	* @returns VBox status code.
7946	* @param pDevIns The device instance to register the ports with.
7947	* @param cbRegion The size of the region in bytes.
7948	* @param iPciRegion The PCI device region.
7949	* @param enmType PCI_ADDRESS_SPACE_MEM or
7950	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7951	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7952	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7953	* @param pfnWrite Pointer to function which is gonna handle Write
7954	* operations.
7955	* @param pfnRead Pointer to function which is gonna handle Read
7956	* operations.
7957	* @param pvUser User argument to pass to the callbacks.
7958	* @param pszDesc Pointer to description string. This must not be freed.
7959	* @param phRegion Where to return the MMIO region handle.
7960	*
7961	*/
7962	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7963	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7964	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7965
7966	{
7967	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7968	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7969	if (RT_SUCCESS(rc))
7970	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7971	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7972	phRegion, NULL /pfnMapUnmap*/);
7973	return rc;
7974	}
7975
7976
7977	/**
7978	* Registers an MMIO2 region for the default PCI device.
7979	*
7980	* @returns VBox status code.
7981	* @param pDevIns The device instance.
7982	* @param iRegion The region number.
7983	* @param cbRegion Size of the region.
7984	* @param enmType PCI_ADDRESS_SPACE_MEM or
7985	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7986	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7987	* @param hMmio2Region Handle to the MMIO2 region.
7988	*/
7989	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7990	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7991	{
7992	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7993	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7994	hMmio2Region, NULL);
7995	}
7996
7997	/**
7998	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7999	* and registering an MMIO2 region for the default PCI device, extended edition.
8000	*
8001	* @returns VBox status code.
8002	* @param pDevIns The device instance to register the ports with.
8003	* @param cbRegion The size of the region in bytes.
8004	* @param iPciRegion The PCI device region.
8005	* @param enmType PCI_ADDRESS_SPACE_MEM or
8006	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
8007	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
8008	* @param pszDesc Pointer to description string. This must not be freed.
8009	* @param ppvMapping Where to store the address of the ring-3 mapping of
8010	* the memory.
8011	* @param phRegion Where to return the MMIO2 region handle.
8012	*
8013	*/
8014	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
8015	PCIADDRESSSPACE enmType, const char *pszDesc,
8016	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
8017
8018	{
8019	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
8020	pszDesc, ppvMapping, phRegion);
8021	if (RT_SUCCESS(rc))
8022	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
8023	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
8024	phRegion, NULL /pfnCallback*/);
8025	return rc;
8026	}
8027
8028	/**
8029	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
8030	* and registering an MMIO2 region for the default PCI device.
8031	*
8032	* @returns VBox status code.
8033	* @param pDevIns The device instance to register the ports with.
8034	* @param cbRegion The size of the region in bytes.
8035	* @param iPciRegion The PCI device region.
8036	* @param enmType PCI_ADDRESS_SPACE_MEM or
8037	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
8038	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
8039	* @param fMmio2Flags PGMPHYS_MMIO2_FLAGS_XXX (see pgm.h).
8040	* @param pfnMapUnmap Callback for doing the mapping, optional. The
8041	* callback will be invoked holding only the PDM lock.
8042	* The device lock will _not_ be taken (due to lock
8043	* order).
8044	* @param pszDesc Pointer to description string. This must not be freed.
8045	* @param ppvMapping Where to store the address of the ring-3 mapping of
8046	* the memory.
8047	* @param phRegion Where to return the MMIO2 region handle.
8048	*
8049	*/
8050	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
8051	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
8052	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
8053
8054	{
8055	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
8056	pszDesc, ppvMapping, phRegion);
8057	if (RT_SUCCESS(rc))
8058	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
8059	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
8060	*phRegion, pfnMapUnmap);
8061	return rc;
8062	}
8063
8064	/**
8065	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
8066	*/
8067	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
8068	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
8069	{
8070	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
8071	}
8072
8073	/**
8074	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
8075	*/
8076	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
8077	unsigned cb, uint32_t *pu32Value)
8078	{
8079	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
8080	}
8081
8082	/**
8083	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
8084	*/
8085	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
8086	unsigned cb, uint32_t u32Value)
8087	{
8088	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
8089	}
8090
8091	#endif /* IN_RING3 */
8092
8093	/**
8094	* Bus master physical memory read from the default PCI device.
8095	*
8096	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8097	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8098	* @param pDevIns The device instance.
8099	* @param GCPhys Physical address start reading from.
8100	* @param pvBuf Where to put the read bits.
8101	* @param cbRead How many bytes to read.
8102	* @thread Any thread, but the call may involve the emulation thread.
8103	*/
8104	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8105	{
8106	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8107	}
8108
8109	/**
8110	* Bus master physical memory read - unknown data usage.
8111	*
8112	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8113	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8114	* @param pDevIns The device instance.
8115	* @param pPciDev The PCI device structure. If NULL the default
8116	* PCI device for this device instance is used.
8117	* @param GCPhys Physical address start reading from.
8118	* @param pvBuf Where to put the read bits.
8119	* @param cbRead How many bytes to read.
8120	* @thread Any thread, but the call may involve the emulation thread.
8121	*/
8122	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8123	{
8124	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8125	}
8126
8127	/**
8128	* Bus master physical memory read from the default PCI device.
8129	*
8130	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8131	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8132	* @param pDevIns The device instance.
8133	* @param GCPhys Physical address start reading from.
8134	* @param pvBuf Where to put the read bits.
8135	* @param cbRead How many bytes to read.
8136	* @thread Any thread, but the call may involve the emulation thread.
8137	*/
8138	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8139	{
8140	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8141	}
8142
8143	/**
8144	* Bus master physical memory read - reads meta data processed by the device.
8145	*
8146	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8147	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8148	* @param pDevIns The device instance.
8149	* @param pPciDev The PCI device structure. If NULL the default
8150	* PCI device for this device instance is used.
8151	* @param GCPhys Physical address start reading from.
8152	* @param pvBuf Where to put the read bits.
8153	* @param cbRead How many bytes to read.
8154	* @thread Any thread, but the call may involve the emulation thread.
8155	*/
8156	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8157	{
8158	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8159	}
8160
8161	/**
8162	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
8163	*
8164	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8165	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8166	* @param pDevIns The device instance.
8167	* @param GCPhys Physical address start reading from.
8168	* @param pvBuf Where to put the read bits.
8169	* @param cbRead How many bytes to read.
8170	* @thread Any thread, but the call may involve the emulation thread.
8171	*/
8172	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8173	{
8174	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8175	}
8176
8177	/**
8178	* Bus master physical memory read - read data will not be touched by the device.
8179	*
8180	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8181	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8182	* @param pDevIns The device instance.
8183	* @param pPciDev The PCI device structure. If NULL the default
8184	* PCI device for this device instance is used.
8185	* @param GCPhys Physical address start reading from.
8186	* @param pvBuf Where to put the read bits.
8187	* @param cbRead How many bytes to read.
8188	* @thread Any thread, but the call may involve the emulation thread.
8189	*/
8190	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8191	{
8192	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8193	}
8194
8195	/**
8196	* Bus master physical memory write from the default PCI device - unknown data usage.
8197	*
8198	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8199	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8200	* @param pDevIns The device instance.
8201	* @param GCPhys Physical address to write to.
8202	* @param pvBuf What to write.
8203	* @param cbWrite How many bytes to write.
8204	* @thread Any thread, but the call may involve the emulation thread.
8205	*/
8206	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8207	{
8208	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8209	}
8210
8211	/**
8212	* Bus master physical memory write - unknown data usage.
8213	*
8214	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8215	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8216	* @param pDevIns The device instance.
8217	* @param pPciDev The PCI device structure. If NULL the default
8218	* PCI device for this device instance is used.
8219	* @param GCPhys Physical address to write to.
8220	* @param pvBuf What to write.
8221	* @param cbWrite How many bytes to write.
8222	* @thread Any thread, but the call may involve the emulation thread.
8223	*/
8224	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8225	{
8226	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8227	}
8228
8229	/**
8230	* Bus master physical memory write from the default PCI device.
8231	*
8232	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8233	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8234	* @param pDevIns The device instance.
8235	* @param GCPhys Physical address to write to.
8236	* @param pvBuf What to write.
8237	* @param cbWrite How many bytes to write.
8238	* @thread Any thread, but the call may involve the emulation thread.
8239	*/
8240	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8241	{
8242	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8243	}
8244
8245	/**
8246	* Bus master physical memory write - written data was created/altered by the device.
8247	*
8248	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8249	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8250	* @param pDevIns The device instance.
8251	* @param pPciDev The PCI device structure. If NULL the default
8252	* PCI device for this device instance is used.
8253	* @param GCPhys Physical address to write to.
8254	* @param pvBuf What to write.
8255	* @param cbWrite How many bytes to write.
8256	* @thread Any thread, but the call may involve the emulation thread.
8257	*/
8258	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8259	{
8260	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8261	}
8262
8263	/**
8264	* Bus master physical memory write from the default PCI device.
8265	*
8266	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8267	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8268	* @param pDevIns The device instance.
8269	* @param GCPhys Physical address to write to.
8270	* @param pvBuf What to write.
8271	* @param cbWrite How many bytes to write.
8272	* @thread Any thread, but the call may involve the emulation thread.
8273	*/
8274	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8275	{
8276	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8277	}
8278
8279	/**
8280	* Bus master physical memory write - written data was not touched/created by the device.
8281	*
8282	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8283	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8284	* @param pDevIns The device instance.
8285	* @param pPciDev The PCI device structure. If NULL the default
8286	* PCI device for this device instance is used.
8287	* @param GCPhys Physical address to write to.
8288	* @param pvBuf What to write.
8289	* @param cbWrite How many bytes to write.
8290	* @thread Any thread, but the call may involve the emulation thread.
8291	*/
8292	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8293	{
8294	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8295	}
8296
8297	#ifdef IN_RING3
8298	/**
8299	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
8300	*/
8301	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8302	void **ppv, PPGMPAGEMAPLOCK pLock)
8303	{
8304	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8305	}
8306
8307	/**
8308	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
8309	*/
8310	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8311	void const **ppv, PPGMPAGEMAPLOCK pLock)
8312	{
8313	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8314	}
8315
8316	/**
8317	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
8318	*/
8319	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8320	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
8321	PPGMPAGEMAPLOCK paLocks)
8322	{
8323	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
8324	paLocks);
8325	}
8326
8327	/**
8328	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
8329	*/
8330	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8331	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
8332	PPGMPAGEMAPLOCK paLocks)
8333	{
8334	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
8335	papvPages, paLocks);
8336	}
8337	#endif /* IN_RING3 */
8338
8339	/**
8340	* Sets the IRQ for the default PCI device.
8341	*
8342	* @param pDevIns The device instance.
8343	* @param iIrq IRQ number to set.
8344	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
8345	* @thread Any thread, but will involve the emulation thread.
8346	*/
8347	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8348	{
8349	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8350	}
8351
8352	/**
8353	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
8354	*/
8355	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8356	{
8357	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8358	}
8359
8360	/**
8361	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
8362	* the request when not called from EMT.
8363	*
8364	* @param pDevIns The device instance.
8365	* @param iIrq IRQ number to set.
8366	* @param iLevel IRQ level.
8367	* @thread Any thread, but will involve the emulation thread.
8368	*/
8369	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8370	{
8371	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8372	}
8373
8374	/**
8375	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
8376	*/
8377	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8378	{
8379	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8380	}
8381
8382	/**
8383	* @copydoc PDMDEVHLPR3::pfnISASetIrq
8384	*/
8385	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8386	{
8387	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8388	}
8389
8390	/**
8391	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
8392	*/
8393	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8394	{
8395	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8396	}
8397
8398	#ifdef IN_RING3
8399
8400	/**
8401	* @copydoc PDMDEVHLPR3::pfnDriverAttach
8402	*/
8403	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
8404	{
8405	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
8406	}
8407
8408	/**
8409	* @copydoc PDMDEVHLPR3::pfnDriverDetach
8410	*/
8411	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
8412	{
8413	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
8414	}
8415
8416	/**
8417	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
8418	*/
8419	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
8420	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
8421	{
8422	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
8423	}
8424
8425	/**
8426	* Reconfigures with a single driver reattachement, no config, noflags.
8427	* @sa PDMDevHlpDriverReconfigure
8428	*/
8429	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
8430	{
8431	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
8432	}
8433
8434	/**
8435	* Reconfigures with a two drivers reattachement, no config, noflags.
8436	* @sa PDMDevHlpDriverReconfigure
8437	*/
8438	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
8439	{
8440	char const * apszDrivers[2];
8441	apszDrivers[0] = pszDriver0;
8442	apszDrivers[1] = pszDriver1;
8443	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
8444	}
8445
8446	/**
8447	* @copydoc PDMDEVHLPR3::pfnQueueCreate
8448	*/
8449	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
8450	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
8451	{
8452	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
8453	}
8454
8455	#endif /* IN_RING3 */
8456
8457	/**
8458	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
8459	*/
8460	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8461	{
8462	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
8463	}
8464
8465	/**
8466	* @copydoc PDMDEVHLPR3::pfnQueueInsert
8467	*/
8468	DECLINLINE(int) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
8469	{
8470	return pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
8471	}
8472
8473	/**
8474	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
8475	*/
8476	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8477	{
8478	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
8479	}
8480
8481	#ifdef IN_RING3
8482	/**
8483	* @copydoc PDMDEVHLPR3::pfnTaskCreate
8484	*/
8485	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
8486	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
8487	{
8488	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
8489	}
8490	#endif
8491
8492	/**
8493	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
8494	*/
8495	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
8496	{
8497	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
8498	}
8499
8500	#ifdef IN_RING3
8501
8502	/**
8503	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
8504	*/
8505	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
8506	{
8507	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
8508	}
8509
8510	/**
8511	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
8512	*/
8513	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8514	{
8515	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
8516	}
8517
8518	#endif /* IN_RING3 */
8519
8520	/**
8521	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
8522	*/
8523	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8524	{
8525	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
8526	}
8527
8528	/**
8529	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
8530	*/
8531	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
8532	{
8533	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
8534	}
8535
8536	/**
8537	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
8538	*/
8539	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
8540	{
8541	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
8542	}
8543
8544	/**
8545	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
8546	*/
8547	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
8548	{
8549	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
8550	}
8551
8552	/**
8553	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
8554	*/
8555	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
8556	{
8557	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
8558	}
8559
8560	#ifdef IN_RING3
8561
8562	/**
8563	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
8564	*/
8565	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
8566	{
8567	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
8568	}
8569
8570	/**
8571	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
8572	*/
8573	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8574	{
8575	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
8576	}
8577
8578	#endif /* IN_RING3 */
8579
8580	/**
8581	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
8582	*/
8583	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8584	{
8585	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
8586	}
8587
8588	/**
8589	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
8590	*/
8591	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8592	{
8593	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
8594	}
8595
8596	/**
8597	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
8598	*/
8599	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
8600	{
8601	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
8602	}
8603
8604	/**
8605	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
8606	*/
8607	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
8608	{
8609	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
8610	}
8611
8612	/**
8613	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
8614	*/
8615	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
8616	{
8617	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
8618	}
8619
8620	/**
8621	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
8622	*/
8623	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
8624	{
8625	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
8626	}
8627
8628	#ifdef IN_RING3
8629
8630	/**
8631	* Initializes a PDM critical section.
8632	*
8633	* The PDM critical sections are derived from the IPRT critical sections, but
8634	* works in RC and R0 as well.
8635	*
8636	* @returns VBox status code.
8637	* @param pDevIns The device instance.
8638	* @param pCritSect Pointer to the critical section.
8639	* @param SRC_POS Use RT_SRC_POS.
8640	* @param pszNameFmt Format string for naming the critical section.
8641	* For statistics and lock validation.
8642	* @param ... Arguments for the format string.
8643	*/
8644	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
8645	const char *pszNameFmt, ...)
8646	{
8647	int rc;
8648	va_list va;
8649	va_start(va, pszNameFmt);
8650	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8651	va_end(va);
8652	return rc;
8653	}
8654
8655	#endif /* IN_RING3 */
8656
8657	/**
8658	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
8659	*/
8660	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
8661	{
8662	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
8663	}
8664
8665	/**
8666	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
8667	*/
8668	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8669	{
8670	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
8671	}
8672
8673	/**
8674	* Enters a PDM critical section.
8675	*
8676	* @returns VINF_SUCCESS if entered successfully.
8677	* @returns rcBusy when encountering a busy critical section in RC/R0.
8678	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8679	* during the operation.
8680	*
8681	* @param pDevIns The device instance.
8682	* @param pCritSect The PDM critical section to enter.
8683	* @param rcBusy The status code to return when we're in RC or R0
8684	* and the section is busy. Pass VINF_SUCCESS to
8685	* acquired the critical section thru a ring-3
8686	* call if necessary.
8687	*
8688	* @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
8689	* possible failures in ring-0 or at least apply
8690	* PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
8691	* function.
8692	*
8693	* @sa PDMCritSectEnter
8694	*/
8695	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
8696	{
8697	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
8698	}
8699
8700	/**
8701	* Enters a PDM critical section, with location information for debugging.
8702	*
8703	* @returns VINF_SUCCESS if entered successfully.
8704	* @returns rcBusy when encountering a busy critical section in RC/R0.
8705	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8706	* during the operation.
8707	*
8708	* @param pDevIns The device instance.
8709	* @param pCritSect The PDM critical section to enter.
8710	* @param rcBusy The status code to return when we're in RC or R0
8711	* and the section is busy. Pass VINF_SUCCESS to
8712	* acquired the critical section thru a ring-3
8713	* call if necessary.
8714	* @param uId Some kind of locking location ID. Typically a
8715	* return address up the stack. Optional (0).
8716	* @param SRC_POS The source position where to lock is being
8717	* acquired from. Optional.
8718	* @sa PDMCritSectEnterDebug
8719	*/
8720	DECLINLINE(DECL_CHECK_RETURN(int))
8721	PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8722	{
8723	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8724	}
8725
8726	/**
8727	* Try enter a critical section.
8728	*
8729	* @retval VINF_SUCCESS on success.
8730	* @retval VERR_SEM_BUSY if the critsect was owned.
8731	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8732	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8733	* during the operation.
8734	*
8735	* @param pDevIns The device instance.
8736	* @param pCritSect The critical section.
8737	* @sa PDMCritSectTryEnter
8738	*/
8739	DECLINLINE(DECL_CHECK_RETURN(int))
8740	PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8741	{
8742	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
8743	}
8744
8745	/**
8746	* Try enter a critical section, with location information for debugging.
8747	*
8748	* @retval VINF_SUCCESS on success.
8749	* @retval VERR_SEM_BUSY if the critsect was owned.
8750	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8751	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8752	* during the operation.
8753	*
8754	* @param pDevIns The device instance.
8755	* @param pCritSect The critical section.
8756	* @param uId Some kind of locking location ID. Typically a
8757	* return address up the stack. Optional (0).
8758	* @param SRC_POS The source position where to lock is being
8759	* acquired from. Optional.
8760	* @sa PDMCritSectTryEnterDebug
8761	*/
8762	DECLINLINE(DECL_CHECK_RETURN(int))
8763	PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8764	{
8765	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8766	}
8767
8768	/**
8769	* Leaves a critical section entered with PDMCritSectEnter().
8770	*
8771	* @returns Indication whether we really exited the critical section.
8772	* @retval VINF_SUCCESS if we really exited.
8773	* @retval VINF_SEM_NESTED if we only reduced the nesting count.
8774	* @retval VERR_NOT_OWNER if you somehow ignore release assertions.
8775	*
8776	* @param pDevIns The device instance.
8777	* @param pCritSect The PDM critical section to leave.
8778	* @sa PDMCritSectLeave
8779	*/
8780	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8781	{
8782	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
8783	}
8784
8785	/**
8786	* @see PDMCritSectIsOwner
8787	*/
8788	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8789	{
8790	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
8791	}
8792
8793	/**
8794	* @see PDMCritSectIsInitialized
8795	*/
8796	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8797	{
8798	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
8799	}
8800
8801	/**
8802	* @see PDMCritSectHasWaiters
8803	*/
8804	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8805	{
8806	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
8807	}
8808
8809	/**
8810	* @see PDMCritSectGetRecursion
8811	*/
8812	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8813	{
8814	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
8815	}
8816
8817	#if defined(IN_RING3) \|\| defined(IN_RING0)
8818	/**
8819	* @see PDMHCCritSectScheduleExitEvent
8820	*/
8821	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
8822	{
8823	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
8824	}
8825	#endif
8826
8827	/* Strict build: Remap the two enter calls to the debug versions. */
8828	#ifdef VBOX_STRICT
8829	# ifdef IPRT_INCLUDED_asm_h
8830	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8831	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8832	# else
8833	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8834	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8835	# endif
8836	#endif
8837
8838	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8839
8840	/**
8841	* Deletes the critical section.
8842	*
8843	* @returns VBox status code.
8844	* @param pDevIns The device instance.
8845	* @param pCritSect The PDM critical section to destroy.
8846	* @sa PDMR3CritSectDelete
8847	*/
8848	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8849	{
8850	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8851	}
8852
8853	/**
8854	* Initializes a PDM read/write critical section.
8855	*
8856	* The PDM read/write critical sections are derived from the IPRT critical
8857	* sections, but works in RC and R0 as well.
8858	*
8859	* @returns VBox status code.
8860	* @param pDevIns The device instance.
8861	* @param pCritSect Pointer to the read/write critical section.
8862	* @param SRC_POS Use RT_SRC_POS.
8863	* @param pszNameFmt Format string for naming the critical section.
8864	* For statistics and lock validation.
8865	* @param ... Arguments for the format string.
8866	*/
8867	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
8868	const char *pszNameFmt, ...)
8869	{
8870	int rc;
8871	va_list va;
8872	va_start(va, pszNameFmt);
8873	rc = pDevIns->pHlpR3->pfnCritSectRwInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8874	va_end(va);
8875	return rc;
8876	}
8877
8878	/**
8879	* Deletes the read/write critical section.
8880	*
8881	* @returns VBox status code.
8882	* @param pDevIns The device instance.
8883	* @param pCritSect The PDM read/write critical section to destroy.
8884	* @sa PDMR3CritSectRwDelete
8885	*/
8886	DECLINLINE(int) PDMDevHlpCritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8887	{
8888	return pDevIns->pHlpR3->pfnCritSectRwDelete(pDevIns, pCritSect);
8889	}
8890
8891	#endif /* IN_RING3 */
8892
8893	/**
8894	* @sa PDMCritSectRwEnterShared, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8895	*/
8896	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8897	{
8898	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterShared(pDevIns, pCritSect, rcBusy);
8899	}
8900
8901	/**
8902	* @sa PDMCritSectRwEnterSharedDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8903	*/
8904	DECLINLINE(DECL_CHECK_RETURN(int))
8905	PDMDevHlpCritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8906	{
8907	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterSharedDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8908	}
8909
8910	/**
8911	* @sa PDMCritSectRwTryEnterShared
8912	*/
8913	DECLINLINE(DECL_CHECK_RETURN(int))
8914	PDMDevHlpCritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8915	{
8916	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterShared(pDevIns, pCritSect);
8917	}
8918
8919	/**
8920	* @sa PDMCritSectRwTryEnterSharedDebug
8921	*/
8922	DECLINLINE(DECL_CHECK_RETURN(int))
8923	PDMDevHlpCritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8924	{
8925	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterSharedDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8926	}
8927
8928	/**
8929	* @sa PDMCritSectRwLeaveShared
8930	*/
8931	DECLINLINE(int) PDMDevHlpCritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8932	{
8933	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveShared(pDevIns, pCritSect);
8934	}
8935
8936	/**
8937	* @sa PDMCritSectRwEnterExcl, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8938	*/
8939	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8940	{
8941	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy);
8942	}
8943
8944	/**
8945	* @sa PDMCritSectRwEnterExclDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8946	*/
8947	DECLINLINE(DECL_CHECK_RETURN(int))
8948	PDMDevHlpCritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8949	{
8950	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExclDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8951	}
8952
8953	/**
8954	* @sa PDMCritSectRwTryEnterExcl
8955	*/
8956	DECLINLINE(DECL_CHECK_RETURN(int))
8957	PDMDevHlpCritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8958	{
8959	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExcl(pDevIns, pCritSect);
8960	}
8961
8962	/**
8963	* @sa PDMCritSectRwTryEnterExclDebug
8964	*/
8965	DECLINLINE(DECL_CHECK_RETURN(int))
8966	PDMDevHlpCritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8967	{
8968	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExclDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8969	}
8970
8971	/**
8972	* @sa PDMCritSectRwLeaveExcl
8973	*/
8974	DECLINLINE(int) PDMDevHlpCritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8975	{
8976	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveExcl(pDevIns, pCritSect);
8977	}
8978
8979	/**
8980	* @see PDMCritSectRwIsWriteOwner
8981	*/
8982	DECLINLINE(bool) PDMDevHlpCritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8983	{
8984	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsWriteOwner(pDevIns, pCritSect);
8985	}
8986
8987	/**
8988	* @see PDMCritSectRwIsReadOwner
8989	*/
8990	DECLINLINE(bool) PDMDevHlpCritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
8991	{
8992	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsReadOwner(pDevIns, pCritSect, fWannaHear);
8993	}
8994
8995	/**
8996	* @see PDMCritSectRwGetWriteRecursion
8997	*/
8998	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8999	{
9000	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriteRecursion(pDevIns, pCritSect);
9001	}
9002
9003	/**
9004	* @see PDMCritSectRwGetWriterReadRecursion
9005	*/
9006	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
9007	{
9008	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriterReadRecursion(pDevIns, pCritSect);
9009	}
9010
9011	/**
9012	* @see PDMCritSectRwGetReadCount
9013	*/
9014	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
9015	{
9016	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetReadCount(pDevIns, pCritSect);
9017	}
9018
9019	/**
9020	* @see PDMCritSectRwIsInitialized
9021	*/
9022	DECLINLINE(bool) PDMDevHlpCritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
9023	{
9024	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsInitialized(pDevIns, pCritSect);
9025	}
9026
9027	/* Strict build: Remap the two enter calls to the debug versions. */
9028	#ifdef VBOX_STRICT
9029	# ifdef IPRT_INCLUDED_asm_h
9030	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9031	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9032	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9033	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9034	# else
9035	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
9036	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
9037	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
9038	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
9039	# endif
9040	#endif
9041
9042	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
9043
9044	/**
9045	* @copydoc PDMDEVHLPR3::pfnThreadCreate
9046	*/
9047	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
9048	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
9049	{
9050	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
9051	}
9052
9053	/**
9054	* @copydoc PDMR3ThreadDestroy
9055	* @param pDevIns The device instance.
9056	*/
9057	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
9058	{
9059	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
9060	}
9061
9062	/**
9063	* @copydoc PDMR3ThreadIAmSuspending
9064	* @param pDevIns The device instance.
9065	*/
9066	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9067	{
9068	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
9069	}
9070
9071	/**
9072	* @copydoc PDMR3ThreadIAmRunning
9073	* @param pDevIns The device instance.
9074	*/
9075	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9076	{
9077	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
9078	}
9079
9080	/**
9081	* @copydoc PDMR3ThreadSleep
9082	* @param pDevIns The device instance.
9083	*/
9084	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
9085	{
9086	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
9087	}
9088
9089	/**
9090	* @copydoc PDMR3ThreadSuspend
9091	* @param pDevIns The device instance.
9092	*/
9093	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9094	{
9095	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
9096	}
9097
9098	/**
9099	* @copydoc PDMR3ThreadResume
9100	* @param pDevIns The device instance.
9101	*/
9102	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9103	{
9104	return pDevIns->pHlpR3->pfnThreadResume(pThread);
9105	}
9106
9107	/**
9108	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
9109	*/
9110	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
9111	{
9112	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
9113	}
9114
9115	/**
9116	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
9117	*/
9118	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
9119	{
9120	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
9121	}
9122
9123	/**
9124	* @copydoc PDMDEVHLPR3::pfnA20Set
9125	*/
9126	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
9127	{
9128	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
9129	}
9130
9131	/**
9132	* @copydoc PDMDEVHLPR3::pfnRTCRegister
9133	*/
9134	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
9135	{
9136	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
9137	}
9138
9139	/**
9140	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
9141	*/
9142	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
9143	{
9144	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
9145	}
9146
9147	/**
9148	* @copydoc PDMDEVHLPR3::pfnIommuRegister
9149	*/
9150	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
9151	{
9152	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
9153	}
9154
9155	/**
9156	* @copydoc PDMDEVHLPR3::pfnPICRegister
9157	*/
9158	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
9159	{
9160	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
9161	}
9162
9163	/**
9164	* @copydoc PDMDEVHLPR3::pfnApicRegister
9165	*/
9166	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
9167	{
9168	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
9169	}
9170
9171	/**
9172	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
9173	*/
9174	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9175	{
9176	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
9177	}
9178
9179	/**
9180	* @copydoc PDMDEVHLPR3::pfnHpetRegister
9181	*/
9182	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
9183	{
9184	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
9185	}
9186
9187	/**
9188	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
9189	*/
9190	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
9191	{
9192	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
9193	}
9194
9195	/**
9196	* @copydoc PDMDEVHLPR3::pfnDMACRegister
9197	*/
9198	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
9199	{
9200	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
9201	}
9202
9203	/**
9204	* @copydoc PDMDEVHLPR3::pfnDMARegister
9205	*/
9206	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
9207	{
9208	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
9209	}
9210
9211	/**
9212	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
9213	*/
9214	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
9215	{
9216	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
9217	}
9218
9219	/**
9220	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
9221	*/
9222	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
9223	{
9224	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
9225	}
9226
9227	/**
9228	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
9229	*/
9230	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
9231	{
9232	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
9233	}
9234
9235	/**
9236	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
9237	*/
9238	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
9239	{
9240	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
9241	}
9242
9243	/**
9244	* @copydoc PDMDEVHLPR3::pfnDMASchedule
9245	*/
9246	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
9247	{
9248	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
9249	}
9250
9251	/**
9252	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
9253	*/
9254	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
9255	{
9256	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
9257	}
9258
9259	/**
9260	* @copydoc PDMDEVHLPR3::pfnCMOSRead
9261	*/
9262	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
9263	{
9264	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
9265	}
9266
9267	/**
9268	* @copydoc PDMDEVHLPR3::pfnCallR0
9269	*/
9270	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
9271	{
9272	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
9273	}
9274
9275	/**
9276	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
9277	*/
9278	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
9279	{
9280	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
9281	}
9282
9283	/**
9284	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
9285	*/
9286	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
9287	{
9288	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
9289	}
9290
9291	/**
9292	* @copydoc PDMDEVHLPR3::pfnGetUVM
9293	*/
9294	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
9295	{
9296	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
9297	}
9298
9299	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
9300
9301	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
9302
9303	/**
9304	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
9305	*/
9306	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
9307	{
9308	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
9309	}
9310
9311	/**
9312	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
9313	*/
9314	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
9315	{
9316	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
9317	}
9318
9319	/**
9320	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
9321	*/
9322	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
9323	{
9324	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
9325	}
9326
9327	/**
9328	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
9329	*/
9330	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
9331	{
9332	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
9333	}
9334
9335	/**
9336	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
9337	*/
9338	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9339	{
9340	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
9341	}
9342
9343	/**
9344	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
9345	*/
9346	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
9347	{
9348	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
9349	}
9350
9351	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
9352
9353	/**
9354	* @copydoc PDMDEVHLPR3::pfnGetVM
9355	*/
9356	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
9357	{
9358	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
9359	}
9360
9361	/**
9362	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
9363	*/
9364	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
9365	{
9366	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
9367	}
9368
9369	/**
9370	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
9371	*/
9372	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
9373	{
9374	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
9375	}
9376
9377	/**
9378	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
9379	*/
9380	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
9381	{
9382	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
9383	}
9384
9385	/**
9386	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9387	*/
9388	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
9389	{
9390	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
9391	}
9392
9393	/**
9394	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9395	*/
9396	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
9397	{
9398	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
9399	}
9400
9401	#ifdef IN_RING3
9402	/**
9403	* @copydoc PDMDEVHLPR3::pfnTMCpuTicksPerSecond
9404	*/
9405	DECLINLINE(uint64_t) PDMDevHlpTMCpuTicksPerSecond(PPDMDEVINS pDevIns)
9406	{
9407	return pDevIns->CTX_SUFF(pHlp)->pfnTMCpuTicksPerSecond(pDevIns);
9408	}
9409
9410	/**
9411	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
9412	*/
9413	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
9414	{
9415	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
9416	}
9417
9418	/**
9419	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
9420	*/
9421	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
9422	{
9423	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
9424	}
9425
9426	/**
9427	* @copydoc PDMDEVHLPR3::pfnVMReset
9428	*/
9429	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
9430	{
9431	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
9432	}
9433
9434	/**
9435	* @copydoc PDMDEVHLPR3::pfnVMSuspend
9436	*/
9437	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
9438	{
9439	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
9440	}
9441
9442	/**
9443	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
9444	*/
9445	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
9446	{
9447	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
9448	}
9449
9450	/**
9451	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
9452	*/
9453	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
9454	{
9455	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
9456	}
9457
9458	#endif /* IN_RING3 */
9459
9460	/**
9461	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
9462	*/
9463	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
9464	{
9465	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
9466	}
9467
9468	#ifdef IN_RING3
9469	/**
9470	* @copydoc PDMDEVHLPR3::pfnGetCpuId
9471	*/
9472	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
9473	{
9474	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
9475	}
9476	#endif
9477
9478	/**
9479	* @copydoc PDMDEVHLPR3::pfnGetMainExecutionEngine
9480	*/
9481	DECLINLINE(uint8_t) PDMDevHlpGetMainExecutionEngine(PPDMDEVINS pDevIns)
9482	{
9483	return pDevIns->CTX_SUFF(pHlp)->pfnGetMainExecutionEngine(pDevIns);
9484	}
9485
9486	#ifdef IN_RING3
9487
9488	/**
9489	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
9490	*/
9491	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
9492	{
9493	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
9494	}
9495
9496	/**
9497	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
9498	*/
9499	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
9500	{
9501	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
9502	}
9503
9504	/**
9505	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
9506	*/
9507	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
9508	PFNPGMPHYSHANDLER pfnHandler, const char *pszDesc,
9509	PPGMPHYSHANDLERTYPE phType)
9510	{
9511	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandler, pszDesc, phType);
9512	}
9513
9514	#elif defined(IN_RING0)
9515
9516	/**
9517	* @copydoc PDMDEVHLPR0::pfnPGMHandlerPhysicalTypeSetUpContext
9518	*/
9519	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeSetUpContext(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
9520	PFNPGMPHYSHANDLER pfnHandler, PFNPGMRZPHYSPFHANDLER pfnPfHandler,
9521	const char *pszDesc, PGMPHYSHANDLERTYPE hType)
9522	{
9523	return pDevIns->pHlpR0->pfnPGMHandlerPhysicalTypeSetUpContext(pDevIns, enmKind, pfnHandler, pfnPfHandler, pszDesc, hType);
9524	}
9525
9526	#endif
9527	#ifdef IN_RING3
9528
9529	/**
9530	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalRegister
9531	*/
9532	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
9533	PGMPHYSHANDLERTYPE hType, R3PTRTYPE(const char *) pszDesc)
9534	{
9535	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalRegister(pDevIns, GCPhys, GCPhysLast, hType, pszDesc);
9536	}
9537
9538	/**
9539	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalDeregister
9540	*/
9541	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalDeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9542	{
9543	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalDeregister(pDevIns, GCPhys);
9544	}
9545
9546	#endif /* IN_RING3 */
9547
9548	/**
9549	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalPageTempOff
9550	*/
9551	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
9552	{
9553	return pDevIns->CTX_SUFF(pHlp)->pfnPGMHandlerPhysicalPageTempOff(pDevIns, GCPhys, GCPhysPage);
9554	}
9555
9556	#ifdef IN_RING3
9557
9558	/**
9559	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalReset
9560	*/
9561	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalReset(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9562	{
9563	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalReset(pDevIns, GCPhys);
9564	}
9565
9566	/**
9567	* @copydoc PDMDEVHLPR3::pfnVMMRegisterPatchMemory
9568	*/
9569	DECLINLINE(int) PDMDevHlpVMMRegisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9570	{
9571	return pDevIns->pHlpR3->pfnVMMRegisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9572	}
9573
9574	/**
9575	* @copydoc PDMDEVHLPR3::pfnVMMDeregisterPatchMemory
9576	*/
9577	DECLINLINE(int) PDMDevHlpVMMDeregisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9578	{
9579	return pDevIns->pHlpR3->pfnVMMDeregisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9580	}
9581
9582	/**
9583	* @copydoc PDMDEVHLPR3::pfnSharedModuleRegister
9584	*/
9585	DECLINLINE(int) PDMDevHlpSharedModuleRegister(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
9586	RTGCPTR GCBaseAddr, uint32_t cbModule,
9587	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions)
9588	{
9589	return pDevIns->pHlpR3->pfnSharedModuleRegister(pDevIns, enmGuestOS, pszModuleName, pszVersion,
9590	GCBaseAddr, cbModule, cRegions, paRegions);
9591	}
9592
9593	/**
9594	* @copydoc PDMDEVHLPR3::pfnSharedModuleUnregister
9595	*/
9596	DECLINLINE(int) PDMDevHlpSharedModuleUnregister(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
9597	RTGCPTR GCBaseAddr, uint32_t cbModule)
9598	{
9599	return pDevIns->pHlpR3->pfnSharedModuleUnregister(pDevIns, pszModuleName, pszVersion, GCBaseAddr, cbModule);
9600	}
9601
9602	/**
9603	* @copydoc PDMDEVHLPR3::pfnSharedModuleGetPageState
9604	*/
9605	DECLINLINE(int) PDMDevHlpSharedModuleGetPageState(PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool *pfShared,
9606	uint64_t *pfPageFlags)
9607	{
9608	return pDevIns->pHlpR3->pfnSharedModuleGetPageState(pDevIns, GCPtrPage, pfShared, pfPageFlags);
9609	}
9610
9611	/**
9612	* @copydoc PDMDEVHLPR3::pfnSharedModuleCheckAll
9613	*/
9614	DECLINLINE(int) PDMDevHlpSharedModuleCheckAll(PPDMDEVINS pDevIns)
9615	{
9616	return pDevIns->pHlpR3->pfnSharedModuleCheckAll(pDevIns);
9617	}
9618
9619	/**
9620	* @copydoc PDMDEVHLPR3::pfnQueryLun
9621	*/
9622	DECLINLINE(int) PDMDevHlpQueryLun(PPDMDEVINS pDevIns, const char pszDevice, unsigned iInstance, unsigned iLun, PPDMIBASE ppBase)
9623	{
9624	return pDevIns->pHlpR3->pfnQueryLun(pDevIns, pszDevice, iInstance, iLun, ppBase);
9625	}
9626
9627	/**
9628	* @copydoc PDMDEVHLPR3::pfnGIMDeviceRegister
9629	*/
9630	DECLINLINE(void) PDMDevHlpGIMDeviceRegister(PPDMDEVINS pDevIns, PGIMDEBUG pDbg)
9631	{
9632	pDevIns->pHlpR3->pfnGIMDeviceRegister(pDevIns, pDbg);
9633	}
9634
9635	/**
9636	* @copydoc PDMDEVHLPR3::pfnGIMGetDebugSetup
9637	*/
9638	DECLINLINE(int) PDMDevHlpGIMGetDebugSetup(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup)
9639	{
9640	return pDevIns->pHlpR3->pfnGIMGetDebugSetup(pDevIns, pDbgSetup);
9641	}
9642
9643	#endif /* IN_RING3 */
9644
9645	/**
9646	* @copydoc PDMDEVHLPR3::pfnGIMGetMmio2Regions
9647	*/
9648	DECLINLINE(PGIMMMIO2REGION) PDMDevHlpGIMGetMmio2Regions(PPDMDEVINS pDevIns, uint32_t *pcRegions)
9649	{
9650	return pDevIns->CTX_SUFF(pHlp)->pfnGIMGetMmio2Regions(pDevIns, pcRegions);
9651	}
9652
9653	#ifdef IN_RING3
9654
9655	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
9656	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9657	do { \
9658	uint32_t u32GetEnumTmp = 0; \
9659	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
9660	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9661	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
9662	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
9663	} while (0)
9664
9665	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
9666	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9667	do { \
9668	uint8_t bGetEnumTmp = 0; \
9669	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
9670	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9671	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
9672	} while (0)
9673
9674	#endif /* IN_RING3 */
9675
9676	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
9677	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
9678
9679	/**
9680	* Callbacks for VBoxDeviceRegister().
9681	*/
9682	typedef struct PDMDEVREGCB
9683	{
9684	/** Interface version.
9685	* This is set to PDM_DEVREG_CB_VERSION. */
9686	uint32_t u32Version;
9687
9688	/**
9689	* Registers a device with the current VM instance.
9690	*
9691	* @returns VBox status code.
9692	* @param pCallbacks Pointer to the callback table.
9693	* @param pReg Pointer to the device registration record.
9694	* This data must be permanent and readonly.
9695	*/
9696	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
9697	} PDMDEVREGCB;
9698
9699	/** Current version of the PDMDEVREGCB structure. */
9700	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
9701
9702
9703	/**
9704	* The VBoxDevicesRegister callback function.
9705	*
9706	* PDM will invoke this function after loading a device module and letting
9707	* the module decide which devices to register and how to handle conflicts.
9708	*
9709	* @returns VBox status code.
9710	* @param pCallbacks Pointer to the callback table.
9711	* @param u32Version VBox version number.
9712	*/
9713	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
9714
9715	/** @} */
9716
9717	RT_C_DECLS_END
9718
9719	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 99745

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