| 1 | /* $Id: pdmpcidevint.h 65101 2017-01-04 12:07:43Z vboxsync $ */
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| 2 | /** @file
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| 3 | * DevPCI - PDM PCI Internal header - Only for hiding bits of PDMPCIDEV.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2016 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 | #ifndef ___VBox_vmm_pdmpcidevint_h
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| 19 | #define ___VBox_vmm_pdmpcidevint_h
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| 20 |
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| 21 | #include <VBox/vmm/pdmdev.h>
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| 22 |
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| 23 | /** @defgroup grp_pdm_pcidev_int The PDM PCI Device Internals
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| 24 | * @ingroup grp_pdm_pcidev
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| 25 | *
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| 26 | * @remarks The PDM PCI device internals are visible to both PDM and the PCI Bus
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| 27 | * implementation, thus it lives among the the public headers despite
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| 28 | * being rather private and internal.
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| 29 | *
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| 30 | * @{
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| 31 | */
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| 32 |
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| 33 |
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| 34 | /**
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| 35 | * PCI I/O region.
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| 36 | */
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| 37 | typedef struct PCIIOREGION
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| 38 | {
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| 39 | /** Current PCI mapping address, 0xffffffff means not mapped. */
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| 40 | uint64_t addr;
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| 41 | uint64_t size;
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| 42 | uint8_t type; /* PCIADDRESSSPACE */
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| 43 | uint8_t padding[HC_ARCH_BITS == 32 ? 3 : 7];
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| 44 | /** Callback called when the region is mapped. */
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| 45 | R3PTRTYPE(PFNPCIIOREGIONMAP) map_func;
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| 46 | } PCIIOREGION, PCIIORegion;
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| 47 | /** Pointer to PCI I/O region. */
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| 48 | typedef PCIIOREGION *PPCIIOREGION;
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| 49 |
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| 50 | /**
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| 51 | * Callback function for reading from the PCI configuration space.
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| 52 | *
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| 53 | * @returns The register value.
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| 54 | * @param pDevIns Pointer to the device instance of the PCI bus.
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| 55 | * @param iBus The bus number this device is on.
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| 56 | * @param iDevice The number of the device on the bus.
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| 57 | * @param u32Address The configuration space register address. [0..255]
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| 58 | * @param cb The register size. [1,2,4]
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| 59 | */
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| 60 | typedef DECLCALLBACK(uint32_t) FNPCIBRIDGECONFIGREAD(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb);
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| 61 | /** Pointer to a FNPCICONFIGREAD() function. */
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| 62 | typedef FNPCIBRIDGECONFIGREAD *PFNPCIBRIDGECONFIGREAD;
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| 63 | /** Pointer to a PFNPCICONFIGREAD. */
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| 64 | typedef PFNPCIBRIDGECONFIGREAD *PPFNPCIBRIDGECONFIGREAD;
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| 65 |
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| 66 | /**
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| 67 | * Callback function for writing to the PCI configuration space.
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| 68 | *
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| 69 | * @param pDevIns Pointer to the device instance of the PCI bus.
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| 70 | * @param iBus The bus number this device is on.
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| 71 | * @param iDevice The number of the device on the bus.
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| 72 | * @param u32Address The configuration space register address. [0..255]
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| 73 | * @param u32Value The value that's being written. The number of bits actually used from
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| 74 | * this value is determined by the cb parameter.
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| 75 | * @param cb The register size. [1,2,4]
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| 76 | */
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| 77 | typedef DECLCALLBACK(void) FNPCIBRIDGECONFIGWRITE(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb);
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| 78 | /** Pointer to a FNPCICONFIGWRITE() function. */
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| 79 | typedef FNPCIBRIDGECONFIGWRITE *PFNPCIBRIDGECONFIGWRITE;
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| 80 | /** Pointer to a PFNPCICONFIGWRITE. */
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| 81 | typedef PFNPCIBRIDGECONFIGWRITE *PPFNPCIBRIDGECONFIGWRITE;
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| 82 |
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| 83 | /* Forward declaration */
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| 84 | struct DEVPCIBUS;
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| 85 |
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| 86 | enum {
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| 87 | /** Flag whether the device is a pci-to-pci bridge.
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| 88 | * This is set prior to device registration. */
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| 89 | PCIDEV_FLAG_PCI_TO_PCI_BRIDGE = RT_BIT_32(1),
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| 90 | /** Flag whether the device is a PCI Express device.
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| 91 | * This is set prior to device registration. */
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| 92 | PCIDEV_FLAG_PCI_EXPRESS_DEVICE = RT_BIT_32(2),
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| 93 | /** Flag whether the device is capable of MSI.
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| 94 | * This one is set by MsiInit(). */
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| 95 | PCIDEV_FLAG_MSI_CAPABLE = RT_BIT_32(3),
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| 96 | /** Flag whether the device is capable of MSI-X.
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| 97 | * This one is set by MsixInit(). */
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| 98 | PCIDEV_FLAG_MSIX_CAPABLE = RT_BIT_32(4),
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| 99 | /** Flag if device represents real physical device in passthrough mode. */
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| 100 | PCIDEV_FLAG_PASSTHROUGH = RT_BIT_32(5),
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| 101 | /** Flag whether the device is capable of MSI using 64-bit address. */
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| 102 | PCIDEV_FLAG_MSI64_CAPABLE = RT_BIT_32(6)
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| 103 |
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| 104 | };
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| 105 |
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| 106 |
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| 107 | /**
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| 108 | * PDM PCI Device - Internal data.
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| 109 | *
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| 110 | * @sa PDMPCIDEV
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| 111 | */
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| 112 | typedef struct PDMPCIDEVINT
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| 113 | {
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| 114 | /** @name Owned by PDM.
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| 115 | * @remarks The bus may use the device instance pointers.
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| 116 | * @{
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| 117 | */
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| 118 | /** Pointer to the PDM device the PCI device belongs to. (R3 ptr) */
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| 119 | PPDMDEVINSR3 pDevInsR3;
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| 120 | /** Pointer to the next PDM device associate with the PDM device. (R3 ptr) */
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| 121 | R3PTRTYPE(PPDMPCIDEV) pNextR3;
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| 122 | /** Pointer to the internal PDM PCI bus for the device. (R3 ptr) */
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| 123 | R3PTRTYPE(struct PDMPCIBUS *) pPdmBusR3;
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| 124 |
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| 125 | /** Pointer to the PDM device the PCI device belongs to. (R0 ptr) */
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| 126 | PPDMDEVINSR0 pDevInsR0;
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| 127 | /** Pointer to the next PDM device associate with the PDM device. (R0 ptr) */
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| 128 | R0PTRTYPE(PPDMPCIDEV) pNextR0;
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| 129 | /** Pointer to the internal PDM PCI bus for the device. (R0 ptr) */
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| 130 | R0PTRTYPE(struct PDMPCIBUS *) pPdmBusR0;
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| 131 |
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| 132 | /** Pointer to the PDM device the PCI device belongs to. (RC ptr) */
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| 133 | PPDMDEVINSRC pDevInsRC;
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| 134 | /** Pointer to the next PDM device associate with the PDM device. (RC ptr) */
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| 135 | RCPTRTYPE(PPDMPCIDEV) pNextRC;
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| 136 | /** Pointer to the internal PDM PCI bus for the device. (RC ptr) */
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| 137 | RCPTRTYPE(struct PDMPCIBUS *) pPdmBusRC;
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| 138 |
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| 139 | /** The CFGM device configuration index (default, PciDev1..255).
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| 140 | * This also works as the internal sub-device ordinal with MMIOEx. */
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| 141 | uint8_t idxDevCfg;
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| 142 | /** Set if the it can be reassigned to a different PCI device number. */
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| 143 | bool fReassignableDevNo;
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| 144 | /** Set if the it can be reassigned to a different PCI function number. */
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| 145 | bool fReassignableFunNo;
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| 146 | /** Alignment padding. */
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| 147 | uint8_t bPadding0;
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| 148 | /** @} */
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| 149 |
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| 150 | /** @name Owned by the PCI Bus
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| 151 | * @remarks PDM will not touch anything here (includes not relocating anything).
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| 152 | * @{
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| 153 | */
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| 154 | /** Pointer to the PCI bus of the device. (R3 ptr) */
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| 155 | R3PTRTYPE(struct DEVPCIBUS *) pBusR3;
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| 156 | /** Page used for MSI-X state. (R3 ptr) */
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| 157 | R3PTRTYPE(void *) pMsixPageR3;
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| 158 | /** Read config callback. */
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| 159 | R3PTRTYPE(PFNPCICONFIGREAD) pfnConfigRead;
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| 160 | /** Write config callback. */
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| 161 | R3PTRTYPE(PFNPCICONFIGWRITE) pfnConfigWrite;
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| 162 | /** Read config callback for PCI bridges to pass requests
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| 163 | * to devices on another bus. */
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| 164 | R3PTRTYPE(PFNPCIBRIDGECONFIGREAD) pfnBridgeConfigRead;
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| 165 | /** Write config callback for PCI bridges to pass requests
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| 166 | * to devices on another bus. */
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| 167 | R3PTRTYPE(PFNPCIBRIDGECONFIGWRITE) pfnBridgeConfigWrite;
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| 168 |
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| 169 | /** Pointer to the PCI bus of the device. (R0 ptr) */
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| 170 | R0PTRTYPE(struct DEVPCIBUS *) pBusR0;
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| 171 | /** Page used for MSI-X state. (R0 ptr) */
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| 172 | R0PTRTYPE(void *) pMsixPageR0;
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| 173 |
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| 174 | /** Pointer to the PCI bus of the device. (RC ptr) */
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| 175 | RCPTRTYPE(struct DEVPCIBUS *) pBusRC;
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| 176 | /** Page used for MSI-X state. (RC ptr) */
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| 177 | RCPTRTYPE(void *) pMsixPageRC;
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| 178 |
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| 179 | /** Flags of this PCI device, see PCIDEV_FLAG_XXX constants. */
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| 180 | uint32_t fFlags;
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| 181 | /** Current state of the IRQ pin of the device. */
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| 182 | int32_t uIrqPinState;
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| 183 |
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| 184 | /** Offset of MSI PCI capability in config space, or 0.
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| 185 | * @todo fix non-standard naming. */
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| 186 | uint8_t u8MsiCapOffset;
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| 187 | /** Size of MSI PCI capability in config space, or 0.
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| 188 | * @todo fix non-standard naming. */
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| 189 | uint8_t u8MsiCapSize;
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| 190 | /** Offset of MSI-X PCI capability in config space, or 0.
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| 191 | * @todo fix non-standard naming. */
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| 192 | uint8_t u8MsixCapOffset;
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| 193 | /** Size of MSI-X PCI capability in config space, or 0.
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| 194 | * @todo fix non-standard naming. */
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| 195 | uint8_t u8MsixCapSize;
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| 196 | #if HC_ARCH_BITS == 64
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| 197 | /** Explicit alignment padding. */
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| 198 | uint8_t abPadding1[HC_ARCH_BITS == 32 ? 0 : 4];
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| 199 | #endif
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| 200 |
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| 201 | /** Pointer to bus specific data. (R3 ptr) */
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| 202 | R3PTRTYPE(const void *) pPciBusPtrR3;
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| 203 |
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| 204 | /** I/O regions. */
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| 205 | PCIIOREGION aIORegions[VBOX_PCI_NUM_REGIONS];
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| 206 | /** @} */
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| 207 | } PDMPCIDEVINT;
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| 208 | AssertCompileMemberAlignment(PDMPCIDEVINT, aIORegions, 8);
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| 209 | AssertCompileSize(PDMPCIDEVINT, HC_ARCH_BITS == 32 ? 264 : 384);
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| 210 |
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| 211 | /** Indicate that PDMPCIDEV::Int.s can be declared. */
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| 212 | #define PDMPCIDEVINT_DECLARED
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| 213 |
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| 214 | /** @} */
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| 215 |
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| 216 | #endif
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| 217 |
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