VirtualBox

source: vbox/trunk/include/VBox/vmm/pdmpcidevint.h@ 79342

Last change on this file since 79342 was 76585, checked in by vboxsync, 6 years ago

*: scm --fix-header-guard-endif

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 9.3 KB
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1/* $Id: pdmpcidevint.h 76585 2019-01-01 06:31:29Z vboxsync $ */
2/** @file
3 * DevPCI - PDM PCI Internal header - Only for hiding bits of PDMPCIDEV.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27#ifndef VBOX_INCLUDED_vmm_pdmpcidevint_h
28#define VBOX_INCLUDED_vmm_pdmpcidevint_h
29#ifndef RT_WITHOUT_PRAGMA_ONCE
30# pragma once
31#endif
32
33#include <VBox/vmm/pdmdev.h>
34
35/** @defgroup grp_pdm_pcidev_int The PDM PCI Device Internals
36 * @ingroup grp_pdm_pcidev
37 *
38 * @remarks The PDM PCI device internals are visible to both PDM and the PCI Bus
39 * implementation, thus it lives among the the public headers despite
40 * being rather private and internal.
41 *
42 * @{
43 */
44
45
46/**
47 * PCI I/O region.
48 */
49typedef struct PCIIOREGION
50{
51 /** Current PCI mapping address, 0xffffffff means not mapped. */
52 uint64_t addr;
53 uint64_t size;
54 uint8_t type; /* PCIADDRESSSPACE */
55 uint8_t padding[HC_ARCH_BITS == 32 ? 3 : 7];
56 /** Callback called when the region is mapped. */
57 R3PTRTYPE(PFNPCIIOREGIONMAP) map_func;
58} PCIIOREGION, PCIIORegion;
59/** Pointer to PCI I/O region. */
60typedef PCIIOREGION *PPCIIOREGION;
61
62/**
63 * Callback function for reading from the PCI configuration space.
64 *
65 * @returns The register value.
66 * @param pDevIns Pointer to the device instance of the PCI bus.
67 * @param iBus The bus number this device is on.
68 * @param iDevice The number of the device on the bus.
69 * @param u32Address The configuration space register address. [0..255]
70 * @param cb The register size. [1,2,4]
71 */
72typedef DECLCALLBACK(uint32_t) FNPCIBRIDGECONFIGREAD(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb);
73/** Pointer to a FNPCICONFIGREAD() function. */
74typedef FNPCIBRIDGECONFIGREAD *PFNPCIBRIDGECONFIGREAD;
75/** Pointer to a PFNPCICONFIGREAD. */
76typedef PFNPCIBRIDGECONFIGREAD *PPFNPCIBRIDGECONFIGREAD;
77
78/**
79 * Callback function for writing to the PCI configuration space.
80 *
81 * @param pDevIns Pointer to the device instance of the PCI bus.
82 * @param iBus The bus number this device is on.
83 * @param iDevice The number of the device on the bus.
84 * @param u32Address The configuration space register address. [0..255]
85 * @param u32Value The value that's being written. The number of bits actually used from
86 * this value is determined by the cb parameter.
87 * @param cb The register size. [1,2,4]
88 */
89typedef DECLCALLBACK(void) FNPCIBRIDGECONFIGWRITE(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb);
90/** Pointer to a FNPCICONFIGWRITE() function. */
91typedef FNPCIBRIDGECONFIGWRITE *PFNPCIBRIDGECONFIGWRITE;
92/** Pointer to a PFNPCICONFIGWRITE. */
93typedef PFNPCIBRIDGECONFIGWRITE *PPFNPCIBRIDGECONFIGWRITE;
94
95/* Forward declaration */
96struct DEVPCIBUS;
97
98enum {
99 /** Flag whether the device is a pci-to-pci bridge.
100 * This is set prior to device registration. */
101 PCIDEV_FLAG_PCI_TO_PCI_BRIDGE = RT_BIT_32(1),
102 /** Flag whether the device is a PCI Express device.
103 * This is set prior to device registration. */
104 PCIDEV_FLAG_PCI_EXPRESS_DEVICE = RT_BIT_32(2),
105 /** Flag whether the device is capable of MSI.
106 * This one is set by MsiInit(). */
107 PCIDEV_FLAG_MSI_CAPABLE = RT_BIT_32(3),
108 /** Flag whether the device is capable of MSI-X.
109 * This one is set by MsixInit(). */
110 PCIDEV_FLAG_MSIX_CAPABLE = RT_BIT_32(4),
111 /** Flag if device represents real physical device in passthrough mode. */
112 PCIDEV_FLAG_PASSTHROUGH = RT_BIT_32(5),
113 /** Flag whether the device is capable of MSI using 64-bit address. */
114 PCIDEV_FLAG_MSI64_CAPABLE = RT_BIT_32(6)
115
116};
117
118
119/**
120 * PDM PCI Device - Internal data.
121 *
122 * @sa PDMPCIDEV
123 */
124typedef struct PDMPCIDEVINT
125{
126 /** @name Owned by PDM.
127 * @remarks The bus may use the device instance pointers.
128 * @{
129 */
130 /** Pointer to the PDM device the PCI device belongs to. (R3 ptr) */
131 PPDMDEVINSR3 pDevInsR3;
132 /** Pointer to the next PDM device associate with the PDM device. (R3 ptr) */
133 R3PTRTYPE(PPDMPCIDEV) pNextR3;
134 /** Pointer to the internal PDM PCI bus for the device. (R3 ptr) */
135 R3PTRTYPE(struct PDMPCIBUS *) pPdmBusR3;
136
137 /** Pointer to the PDM device the PCI device belongs to. (R0 ptr) */
138 PPDMDEVINSR0 pDevInsR0;
139 /** Pointer to the next PDM device associate with the PDM device. (R0 ptr) */
140 R0PTRTYPE(PPDMPCIDEV) pNextR0;
141 /** Pointer to the internal PDM PCI bus for the device. (R0 ptr) */
142 R0PTRTYPE(struct PDMPCIBUS *) pPdmBusR0;
143
144 /** Pointer to the PDM device the PCI device belongs to. (RC ptr) */
145 PPDMDEVINSRC pDevInsRC;
146 /** Pointer to the next PDM device associate with the PDM device. (RC ptr) */
147 RCPTRTYPE(PPDMPCIDEV) pNextRC;
148 /** Pointer to the internal PDM PCI bus for the device. (RC ptr) */
149 RCPTRTYPE(struct PDMPCIBUS *) pPdmBusRC;
150
151 /** The CFGM device configuration index (default, PciDev1..255).
152 * This also works as the internal sub-device ordinal with MMIOEx. */
153 uint8_t idxDevCfg;
154 /** Set if the it can be reassigned to a different PCI device number. */
155 bool fReassignableDevNo;
156 /** Set if the it can be reassigned to a different PCI function number. */
157 bool fReassignableFunNo;
158 /** Alignment padding. */
159 uint8_t bPadding0;
160 /** @} */
161
162 /** @name Owned by the PCI Bus
163 * @remarks PDM will not touch anything here (includes not relocating anything).
164 * @{
165 */
166 /** Pointer to the PCI bus of the device. (R3 ptr) */
167 R3PTRTYPE(struct DEVPCIBUS *) pBusR3;
168 /** Page used for MSI-X state. (R3 ptr) */
169 R3PTRTYPE(void *) pMsixPageR3;
170 /** Read config callback. */
171 R3PTRTYPE(PFNPCICONFIGREAD) pfnConfigRead;
172 /** Write config callback. */
173 R3PTRTYPE(PFNPCICONFIGWRITE) pfnConfigWrite;
174 /** Read config callback for PCI bridges to pass requests
175 * to devices on another bus. */
176 R3PTRTYPE(PFNPCIBRIDGECONFIGREAD) pfnBridgeConfigRead;
177 /** Write config callback for PCI bridges to pass requests
178 * to devices on another bus. */
179 R3PTRTYPE(PFNPCIBRIDGECONFIGWRITE) pfnBridgeConfigWrite;
180
181 /** Pointer to the PCI bus of the device. (R0 ptr) */
182 R0PTRTYPE(struct DEVPCIBUS *) pBusR0;
183 /** Page used for MSI-X state. (R0 ptr) */
184 R0PTRTYPE(void *) pMsixPageR0;
185
186 /** Pointer to the PCI bus of the device. (RC ptr) */
187 RCPTRTYPE(struct DEVPCIBUS *) pBusRC;
188 /** Page used for MSI-X state. (RC ptr) */
189 RCPTRTYPE(void *) pMsixPageRC;
190
191 /** Flags of this PCI device, see PCIDEV_FLAG_XXX constants. */
192 uint32_t fFlags;
193 /** Current state of the IRQ pin of the device. */
194 int32_t uIrqPinState;
195
196 /** Offset of MSI PCI capability in config space, or 0.
197 * @todo fix non-standard naming. */
198 uint8_t u8MsiCapOffset;
199 /** Size of MSI PCI capability in config space, or 0.
200 * @todo fix non-standard naming. */
201 uint8_t u8MsiCapSize;
202 /** Offset of MSI-X PCI capability in config space, or 0.
203 * @todo fix non-standard naming. */
204 uint8_t u8MsixCapOffset;
205 /** Size of MSI-X PCI capability in config space, or 0.
206 * @todo fix non-standard naming. */
207 uint8_t u8MsixCapSize;
208 /** Size of the MSI-X region. */
209 uint16_t cbMsixRegion;
210 /** Offset to the PBA for MSI-X. */
211 uint16_t offMsixPba;
212#if HC_ARCH_BITS == 32
213 /** Add padding to align aIORegions to an 8 byte boundary. */
214 uint8_t abPadding1[12];
215#endif
216
217 /** Pointer to bus specific data. (R3 ptr) */
218 R3PTRTYPE(const void *) pPciBusPtrR3;
219
220 /** I/O regions. */
221 PCIIOREGION aIORegions[VBOX_PCI_NUM_REGIONS];
222 /** @} */
223} PDMPCIDEVINT;
224AssertCompileMemberAlignment(PDMPCIDEVINT, aIORegions, 8);
225AssertCompileSize(PDMPCIDEVINT, HC_ARCH_BITS == 32 ? 280 : 384);
226
227/** Indicate that PDMPCIDEV::Int.s can be declared. */
228#define PDMPCIDEVINT_DECLARED
229
230/** @} */
231
232#endif /* !VBOX_INCLUDED_vmm_pdmpcidevint_h */
233
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