pgm.h@ 76399

Last change on this file since 76399 was 76393, checked in by vboxsync, 6 years ago
VBox/vmm/gmm.h,pgm.h: Avoid dragging in VMMDev.h just for VMMDEVSHAREDREGIONDESC, so moved VMMDEVSHAREDREGIONDESC to types.h. bugref:9344
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_pgm_h
27	#define ___VBox_vmm_pgm_h
28
29	#include <VBox/types.h>
30	#include <VBox/sup.h>
31	#include <VBox/vmm/vmapi.h>
32	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
33	#include <iprt/x86.h>
34	#include <VBox/param.h>
35
36	RT_C_DECLS_BEGIN
37
38	/** @defgroup grp_pgm The Page Monitor / Manager API
39	* @ingroup grp_vmm
40	* @{
41	*/
42
43	/**
44	* FNPGMRELOCATE callback mode.
45	*/
46	typedef enum PGMRELOCATECALL
47	{
48	/** The callback is for checking if the suggested address is suitable. */
49	PGMRELOCATECALL_SUGGEST = 1,
50	/** The callback is for executing the relocation. */
51	PGMRELOCATECALL_RELOCATE
52	} PGMRELOCATECALL;
53
54
55	/**
56	* Callback function which will be called when PGM is trying to find
57	* a new location for the mapping.
58	*
59	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
60	* In 1) the callback should say if it objects to a suggested new location. If it
61	* accepts the new location, it is called again for doing it's relocation.
62	*
63	*
64	* @returns true if the location is ok.
65	* @returns false if another location should be found.
66	* @param pVM The cross context VM structure.
67	* @param GCPtrOld The old virtual address.
68	* @param GCPtrNew The new virtual address.
69	* @param enmMode Used to indicate the callback mode.
70	* @param pvUser User argument.
71	* @remark The return value is no a failure indicator, it's an acceptance
72	* indicator. Relocation can not fail!
73	*/
74	typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
75	/** Pointer to a relocation callback function. */
76	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
77
78
79	/**
80	* Memory access origin.
81	*/
82	typedef enum PGMACCESSORIGIN
83	{
84	/** Invalid zero value. */
85	PGMACCESSORIGIN_INVALID = 0,
86	/** IEM is access memory. */
87	PGMACCESSORIGIN_IEM,
88	/** HM is access memory. */
89	PGMACCESSORIGIN_HM,
90	/** Some device is access memory. */
91	PGMACCESSORIGIN_DEVICE,
92	/** Someone debugging is access memory. */
93	PGMACCESSORIGIN_DEBUGGER,
94	/** SELM is access memory. */
95	PGMACCESSORIGIN_SELM,
96	/** FTM is access memory. */
97	PGMACCESSORIGIN_FTM,
98	/** REM is access memory. */
99	PGMACCESSORIGIN_REM,
100	/** IOM is access memory. */
101	PGMACCESSORIGIN_IOM,
102	/** End of valid values. */
103	PGMACCESSORIGIN_END,
104	/** Type size hack. */
105	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
106	} PGMACCESSORIGIN;
107
108
109	/**
110	* Physical page access handler kind.
111	*/
112	typedef enum PGMPHYSHANDLERKIND
113	{
114	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
115	PGMPHYSHANDLERKIND_MMIO = 1,
116	/** Handler all write access to a physical page range. */
117	PGMPHYSHANDLERKIND_WRITE,
118	/** Handler all access to a physical page range. */
119	PGMPHYSHANDLERKIND_ALL
120
121	} PGMPHYSHANDLERKIND;
122
123	/**
124	* Guest Access type
125	*/
126	typedef enum PGMACCESSTYPE
127	{
128	/** Read access. */
129	PGMACCESSTYPE_READ = 1,
130	/** Write access. */
131	PGMACCESSTYPE_WRITE
132	} PGMACCESSTYPE;
133
134
135	/** @def PGM_ALL_CB_DECL
136	* Macro for declaring a handler callback for all contexts. The handler
137	* callback is static in ring-3, and exported in RC and R0.
138	* @sa PGM_ALL_CB2_DECL.
139	*/
140	#if defined(IN_RC) \|\| defined(IN_RING0)
141	# ifdef __cplusplus
142	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
143	# else
144	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
145	# endif
146	#else
147	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
148	#endif
149
150	/** @def PGM_ALL_CB2_DECL
151	* Macro for declaring a handler callback for all contexts. The handler
152	* callback is hidden in ring-3, and exported in RC and R0.
153	* @sa PGM_ALL_CB2_DECL.
154	*/
155	#if defined(IN_RC) \|\| defined(IN_RING0)
156	# ifdef __cplusplus
157	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
158	# else
159	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
160	# endif
161	#else
162	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLHIDDEN(type))
163	#endif
164
165	/** @def PGM_ALL_CB2_PROTO
166	* Macro for declaring a handler callback for all contexts. The handler
167	* callback is hidden in ring-3, and exported in RC and R0.
168	* @param fnType The callback function type.
169	* @sa PGM_ALL_CB2_DECL.
170	*/
171	#if defined(IN_RC) \|\| defined(IN_RING0)
172	# ifdef __cplusplus
173	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
174	# else
175	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
176	# endif
177	#else
178	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
179	#endif
180
181
182	/**
183	* \#PF Handler callback for physical access handler ranges in RC and R0.
184	*
185	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
186	* @param pVM The cross context VM structure.
187	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
188	* @param uErrorCode CPU Error code.
189	* @param pRegFrame Trap register frame.
190	* NULL on DMA and other non CPU access.
191	* @param pvFault The fault address (cr2).
192	* @param GCPhysFault The GC physical address corresponding to pvFault.
193	* @param pvUser User argument.
194	* @thread EMT(pVCpu)
195	*/
196	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRZPHYSPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
197	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
198	/** Pointer to PGM access callback. */
199	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
200
201
202	/**
203	* Access handler callback for physical access handler ranges.
204	*
205	* The handler can not raise any faults, it's mainly for monitoring write access
206	* to certain pages (like MMIO).
207	*
208	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
209	* the only supported informational status code is
210	* VINF_PGM_HANDLER_DO_DEFAULT.
211	* @retval VINF_SUCCESS if the handler have carried out the operation.
212	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
213	* access operation.
214	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
215	*
216	* @param pVM The cross context VM structure.
217	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
218	* @param GCPhys The physical address the guest is writing to.
219	* @param pvPhys The HC mapping of that address.
220	* @param pvBuf What the guest is reading/writing.
221	* @param cbBuf How much it's reading/writing.
222	* @param enmAccessType The access type.
223	* @param enmOrigin The origin of this call.
224	* @param pvUser User argument.
225	* @thread EMT(pVCpu)
226	*/
227	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMPHYSHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
228	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
229	/** Pointer to PGM access callback. */
230	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
231
232
233	/**
234	* Virtual access handler type.
235	*/
236	typedef enum PGMVIRTHANDLERKIND
237	{
238	/** Write access handled. */
239	PGMVIRTHANDLERKIND_WRITE = 1,
240	/** All access handled. */
241	PGMVIRTHANDLERKIND_ALL,
242	/** Hypervisor write access handled.
243	* This is used to catch the guest trying to write to LDT, TSS and any other
244	* system structure which the brain dead intel guys let unprivilegde code find. */
245	PGMVIRTHANDLERKIND_HYPERVISOR
246	} PGMVIRTHANDLERKIND;
247
248	/**
249	* \#PF handler callback for virtual access handler ranges, RC.
250	*
251	* Important to realize that a physical page in a range can have aliases, and
252	* for ALL and WRITE handlers these will also trigger.
253	*
254	* @returns Strict VBox status code (appropriate for raw-mode).
255	* @param pVM The cross context VM structure.
256	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
257	* @param uErrorCode CPU Error code (X86_TRAP_PF_XXX).
258	* @param pRegFrame Trap register frame.
259	* @param pvFault The fault address (cr2).
260	* @param pvRange The base address of the handled virtual range.
261	* @param offRange The offset of the access into this range.
262	* (If it's a EIP range this is the EIP, if not it's pvFault.)
263	* @param pvUser User argument.
264	* @thread EMT(pVCpu)
265	*/
266	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRCVIRTPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
267	RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange, void *pvUser);
268	/** Pointer to PGM access callback. */
269	typedef FNPGMRCVIRTPFHANDLER *PFNPGMRCVIRTPFHANDLER;
270
271	/**
272	* Access handler callback for virtual access handler ranges.
273	*
274	* Important to realize that a physical page in a range can have aliases, and
275	* for ALL and WRITE handlers these will also trigger.
276	*
277	* @returns VINF_SUCCESS if the handler have carried out the operation.
278	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
279	* @param pVM The cross context VM structure.
280	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
281	* @param GCPtr The virtual address the guest is writing to. This
282	* is the registered address corresponding to the
283	* access, so no aliasing trouble here.
284	* @param pvPtr The HC mapping of that address.
285	* @param pvBuf What the guest is reading/writing.
286	* @param cbBuf How much it's reading/writing.
287	* @param enmAccessType The access type.
288	* @param enmOrigin Who is calling.
289	* @param pvUser User argument.
290	* @thread EMT(pVCpu)
291	*/
292	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMVIRTHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
293	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
294	/** Pointer to PGM access callback. */
295	typedef FNPGMVIRTHANDLER *PFNPGMVIRTHANDLER;
296
297	/**
298	* \#PF Handler callback for invalidation of virtual access handler ranges.
299	*
300	* @param pVM The cross context VM structure.
301	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
302	* @param GCPtr The virtual address the guest has changed.
303	* @param pvUser User argument.
304	* @thread EMT(pVCpu)
305	*
306	* @todo FNPGMR3VIRTINVALIDATE will not actually be called! It was introduced
307	* in r13179 (1.1) and stopped working with r13806 (PGMPool merge,
308	* v1.2), exactly a month later.
309	*/
310	typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void *pvUser);
311	/** Pointer to PGM invalidation callback. */
312	typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
313
314
315	/**
316	* PGMR3PhysEnumDirtyFTPages callback for syncing dirty physical pages
317	*
318	* @param pVM The cross context VM structure.
319	* @param GCPhys GC physical address
320	* @param pRange HC virtual address of the page(s)
321	* @param cbRange Size of the dirty range in bytes.
322	* @param pvUser User argument.
323	*/
324	typedef DECLCALLBACK(int) FNPGMENUMDIRTYFTPAGES(PVM pVM, RTGCPHYS GCPhys, uint8_t pRange, unsigned cbRange, void pvUser);
325	/** Pointer to PGMR3PhysEnumDirtyFTPages callback. */
326	typedef FNPGMENUMDIRTYFTPAGES *PFNPGMENUMDIRTYFTPAGES;
327
328
329	/**
330	* Paging mode.
331	*
332	* @note Part of saved state. Change with extreme care.
333	*/
334	typedef enum PGMMODE
335	{
336	/** The usual invalid value. */
337	PGMMODE_INVALID = 0,
338	/** Real mode. */
339	PGMMODE_REAL,
340	/** Protected mode, no paging. */
341	PGMMODE_PROTECTED,
342	/** 32-bit paging. */
343	PGMMODE_32_BIT,
344	/** PAE paging. */
345	PGMMODE_PAE,
346	/** PAE paging with NX enabled. */
347	PGMMODE_PAE_NX,
348	/** 64-bit AMD paging (long mode). */
349	PGMMODE_AMD64,
350	/** 64-bit AMD paging (long mode) with NX enabled. */
351	PGMMODE_AMD64_NX,
352	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
353	PGMMODE_NESTED_32BIT,
354	/** PAE nested paging mode (shadow only; guest physical to host physical). */
355	PGMMODE_NESTED_PAE,
356	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
357	PGMMODE_NESTED_AMD64,
358	/** Extended paging (Intel) mode. */
359	PGMMODE_EPT,
360	/** Special mode used by NEM to indicate no shadow paging necessary. */
361	PGMMODE_NONE,
362	/** The max number of modes */
363	PGMMODE_MAX,
364	/** 32bit hackishness. */
365	PGMMODE_32BIT_HACK = 0x7fffffff
366	} PGMMODE;
367
368	/** Macro for checking if the guest is using paging.
369	* @param enmMode PGMMODE_*.
370	* @remark ASSUMES certain order of the PGMMODE_* values.
371	*/
372	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
373
374	/** Macro for checking if it's one of the long mode modes.
375	* @param enmMode PGMMODE_*.
376	*/
377	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
378
379	/** Macro for checking if it's one of the AMD64 nested modes.
380	* @param enmMode PGMMODE_*.
381	*/
382	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
383	\|\| (enmMode) == PGMMODE_NESTED_PAE \
384	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
385
386	/**
387	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
388	*
389	* @returns boolean.
390	* @param enmProt The PGMROMPROT value, must be valid.
391	*/
392	#define PGMROMPROT_IS_ROM(enmProt) \
393	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
394	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
395
396
397	VMMDECL(bool) PGMIsLockOwner(PVM pVM);
398
399	VMMDECL(int) PGMRegisterStringFormatTypes(void);
400	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
401	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
402	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
403	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
404	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
405	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
406	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
407	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
408	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
409	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
410	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
411	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
412	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
413	VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
414	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
415	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
416	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
417	#ifndef IN_RING0
418	VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
419	#endif
420	#ifdef VBOX_STRICT
421	VMMDECL(void) PGMMapCheck(PVM pVM);
422	#endif
423	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
424	VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
425	VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
426	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
427	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
428	* PGMShwMakePageNotPresent
429	* @{ */
430	/** The call is from an access handler for dealing with the a faulting write
431	* operation. The virtual address is within the same page. */
432	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
433	/** The page is an MMIO2. */
434	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
435	/** @}*/
436	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
437	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
438	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
439	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
440	VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes);
441	VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes);
442
443	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
444	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
445	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
446	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
447	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
448	VMM_INT_DECL(int) PGMHCChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
449	VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu);
450	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
451	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
452	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
453	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
454	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
455	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
456	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
457
458	/** PGM physical access handler type registration handle (heap offset, valid
459	* cross contexts without needing fixing up). Callbacks and handler type is
460	* associated with this and it is shared by all handler registrations. */
461	typedef uint32_t PGMPHYSHANDLERTYPE;
462	/** Pointer to a PGM physical handler type registration handle. */
463	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
464	/** NIL value for PGM physical access handler type handle. */
465	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
466	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVM pVM, PGMPHYSHANDLERTYPE hType);
467	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
468
469	VMMDECL(int) PGMHandlerPhysicalRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
470	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
471	R3PTRTYPE(const char *) pszDesc);
472	VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
473	VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
474	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVM pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC);
475	VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
476	VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
477	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
478	VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
479	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
480	VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
481	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
482
483	/** PGM virtual access handler type registration handle (heap offset, valid
484	* cross contexts without needing fixing up). Callbacks and handler type is
485	* associated with this and it is shared by all handler registrations. */
486	typedef uint32_t PGMVIRTHANDLERTYPE;
487	/** Pointer to a PGM virtual handler type registration handle. */
488	typedef PGMVIRTHANDLERTYPE *PPGMVIRTHANDLERTYPE;
489	/** NIL value for PGM virtual access handler type handle. */
490	#define NIL_PGMVIRTHANDLERTYPE UINT32_MAX
491	#ifdef VBOX_WITH_RAW_MODE
492	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRelease(PVM pVM, PGMVIRTHANDLERTYPE hType);
493	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRetain(PVM pVM, PGMVIRTHANDLERTYPE hType);
494	VMM_INT_DECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
495	#endif
496
497
498	/**
499	* Page type.
500	*
501	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
502	* @remarks This is used in the saved state, so changes to it requires bumping
503	* the saved state version.
504	* @todo So, convert to \#defines!
505	*/
506	typedef enum PGMPAGETYPE
507	{
508	/** The usual invalid zero entry. */
509	PGMPAGETYPE_INVALID = 0,
510	/** RAM page. (RWX) */
511	PGMPAGETYPE_RAM,
512	/** MMIO2 page. (RWX) */
513	PGMPAGETYPE_MMIO2,
514	/** MMIO2 page aliased over an MMIO page. (RWX)
515	* See PGMHandlerPhysicalPageAlias(). */
516	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
517	/** Special page aliased over an MMIO page. (RWX)
518	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
519	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
520	* the shadow paging code. */
521	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
522	/** Shadowed ROM. (RWX) */
523	PGMPAGETYPE_ROM_SHADOW,
524	/** ROM page. (R-X) */
525	PGMPAGETYPE_ROM,
526	/** MMIO page. (---) */
527	PGMPAGETYPE_MMIO,
528	/** End of valid entries. */
529	PGMPAGETYPE_END
530	} PGMPAGETYPE;
531	AssertCompile(PGMPAGETYPE_END == 8);
532
533	/** @name PGM page type predicates.
534	* @{ */
535	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
536	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
537	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
538	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
539	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
540	/** @} */
541
542
543	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVM pVM, RTGCPHYS GCPhys);
544
545	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
546	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
547	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
548	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
549	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
550	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
551
552	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
553	VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
554	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
555	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
556	VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
557
558	/** @def PGM_PHYS_RW_IS_SUCCESS
559	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
560	* PGMPhysWriteGCPtr call completed the given task.
561	*
562	* @returns true if completed, false if not.
563	* @param a_rcStrict The status code.
564	* @sa IOM_SUCCESS
565	*/
566	#ifdef IN_RING3
567	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
568	( (a_rcStrict) == VINF_SUCCESS \
569	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
570	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
571	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
572	)
573	#elif defined(IN_RING0)
574	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
575	( (a_rcStrict) == VINF_SUCCESS \
576	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
577	\|\| (a_rcStrict) == VINF_EM_OFF \
578	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
579	\|\| (a_rcStrict) == VINF_EM_RESET \
580	\|\| (a_rcStrict) == VINF_EM_HALT \
581	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
582	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
583	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
584	)
585	#elif defined(IN_RC)
586	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
587	( (a_rcStrict) == VINF_SUCCESS \
588	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
589	\|\| (a_rcStrict) == VINF_EM_OFF \
590	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
591	\|\| (a_rcStrict) == VINF_EM_RESET \
592	\|\| (a_rcStrict) == VINF_EM_HALT \
593	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
594	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
595	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
596	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
597	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
598	)
599	#endif
600	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
601	* Updates the return code with a new result.
602	*
603	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
604	*
605	* @param a_rcStrict The current return code, to be updated.
606	* @param a_rcStrict2 The new return code to merge in.
607	*/
608	#ifdef IN_RING3
609	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
610	do { \
611	Assert(rcStrict == VINF_SUCCESS); \
612	Assert(rcStrict2 == VINF_SUCCESS); \
613	} while (0)
614	#elif defined(IN_RING0)
615	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
616	do { \
617	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
618	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
619	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
620	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
621	{ /* likely */ } \
622	else if ( (a_rcStrict) == VINF_SUCCESS \
623	\|\| (a_rcStrict) > (a_rcStrict2)) \
624	(a_rcStrict) = (a_rcStrict2); \
625	} while (0)
626	#elif defined(IN_RC)
627	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
628	do { \
629	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
630	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
631	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
632	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
633	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
634	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
635	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
636	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
637	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
638	{ /* likely */ } \
639	else if ((a_rcStrict) == VINF_SUCCESS) \
640	(a_rcStrict) = (a_rcStrict2); \
641	else if ( ( (a_rcStrict) > (a_rcStrict2) \
642	&& ( (a_rcStrict2) <= VINF_EM_RESET \
643	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
644	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
645	&& (a_rcStrict) > VINF_EM_RESET) ) \
646	(a_rcStrict) = (a_rcStrict2); \
647	} while (0)
648	#endif
649
650	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
651	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
652	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
653	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
654
655	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
656	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
657	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
658	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
659	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
660	VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
661	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
662	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
663
664	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
665	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVM pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
666	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
667	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
668	R3PTRTYPE(uint8_t ) ppb,
669	#else
670	R3R0PTRTYPE(uint8_t ) ppb,
671	#endif
672	uint64_t *pfTlb);
673	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
674	* @{ */
675	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
676	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
677	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
678	/** @} */
679
680	/** Information returned by PGMPhysNemQueryPageInfo. */
681	typedef struct PGMPHYSNEMPAGEINFO
682	{
683	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
684	RTHCPHYS HCPhys;
685	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
686	uint32_t fNemProt : 8;
687	/** The NEM state associated with the PAGE. */
688	uint32_t u2NemState : 2;
689	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
690	uint32_t u2OldNemState : 2;
691	/** Set if the page has handler. */
692	uint32_t fHasHandlers : 1;
693	/** Set if is the zero page backing it. */
694	uint32_t fZeroPage : 1;
695	/** Set if the page has handler. */
696	PGMPAGETYPE enmType;
697	} PGMPHYSNEMPAGEINFO;
698	/** Pointer to page information for NEM. */
699	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
700	/**
701	* Callback for checking that the page is in sync while under the PGM lock.
702	*
703	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
704	* in-sync between PGM and the native hypervisor API in an atomic fashion.
705	*
706	* @returns VBox status code.
707	* @param pVM The cross context VM structure.
708	* @param pVCpu The cross context per virtual CPU structure. Optional,
709	* see PGMPhysNemQueryPageInfo.
710	* @param GCPhys The guest physical address (not A20 masked).
711	* @param pInfo The page info structure. This function updates the
712	* u2NemState memory and the caller will update the PGMPAGE
713	* copy accordingly.
714	* @param pvUser Callback user argument.
715	*/
716	typedef DECLCALLBACK(int) FNPGMPHYSNEMCHECKPAGE(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser);
717	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
718	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
719
720	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
721	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
722
723	/**
724	* Callback for use with PGMPhysNemEnumPagesByState.
725	* @returns VBox status code.
726	* Failure status will stop enumeration immediately and return.
727	* @param pVM The cross context VM structure.
728	* @param pVCpu The cross context per virtual CPU structure. Optional,
729	* see PGMPhysNemEnumPagesByState.
730	* @param GCPhys The guest physical address (not A20 masked).
731	* @param pu2NemState Pointer to variable with the NEM state. This can be
732	* update.
733	* @param pvUser The user argument.
734	*/
735	typedef DECLCALLBACK(int) FNPGMPHYSNEMENUMCALLBACK(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint8_t pu2NemState, void pvUser);
736	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
737	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
738	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVM pVM, PVMCPU VCpu, uint8_t uMinState,
739	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
740
741
742	#ifdef VBOX_STRICT
743	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
744	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
745	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
746	#endif /* VBOX_STRICT */
747
748	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
749	VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu);
750	VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu);
751	VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu);
752	VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu);
753	VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
754	#endif
755
756	VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages);
757
758	/**
759	* Query large page usage state
760	*
761	* @returns 0 - disabled, 1 - enabled
762	* @param pVM The cross context VM structure.
763	*/
764	#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
765
766
767	#ifdef IN_RC
768	/** @defgroup grp_pgm_gc The PGM Guest Context API
769	* @{
770	*/
771	VMMRCDECL(int) PGMRCDynMapInit(PVM pVM);
772	/** @} */
773	#endif /* IN_RC */
774
775
776	#ifdef IN_RING0
777	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
778	* @{
779	*/
780	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, PVM pVM, VMCPUID idCpu);
781	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, PVM pVM, VMCPUID idCpu);
782	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PGVM pGVM, PVM pVM, VMCPUID idCpu);
783	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM, PVM pVM);
784	VMMR0DECL(int) PGMR0SharedModuleCheck(PVM pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule, PCRTGCPTR64 paRegionsGCPtrs);
785	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
786	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
787	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
788	VMMR0DECL(int) PGMR0DynMapInit(void);
789	VMMR0DECL(void) PGMR0DynMapTerm(void);
790	VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
791	VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
792	VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
793	VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu);
794	VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu);
795	# endif
796	/** @} */
797	#endif /* IN_RING0 */
798
799
800
801	#ifdef IN_RING3
802	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
803	* @{
804	*/
805	VMMR3DECL(int) PGMR3Init(PVM pVM);
806	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
807	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
808	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
809	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
810	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
811	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
812	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
813	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
814	VMMR3DECL(int) PGMR3Term(PVM pVM);
815	VMMR3DECL(int) PGMR3LockCall(PVM pVM);
816
817	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
818	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
819	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
820	VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser);
821	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
822	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
823	const char *ppszDesc, bool pfIsMmio);
824	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
825	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
826
827	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
828	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
829	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
830	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc);
831	VMMR3DECL(int) PGMR3PhysMMIOExPreRegister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion, PGMPHYSHANDLERTYPE hType,
832	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
833	VMMR3DECL(int) PGMR3PhysMMIOExDeregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion);
834	VMMR3DECL(int) PGMR3PhysMMIOExMap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys);
835	VMMR3DECL(int) PGMR3PhysMMIOExUnmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys);
836	VMMR3_INT_DECL(int) PGMR3PhysMMIOExReduce(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion);
837	VMMR3DECL(bool) PGMR3PhysMMIOExIsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
838	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
839	VMMR3_INT_DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
840
841	/** @name PGMR3PhysRegisterRom flags.
842	* @{ */
843	/** Inidicates that ROM shadowing should be enabled. */
844	#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
845	/** Indicates that what pvBinary points to won't go away
846	* and can be used for strictness checks. */
847	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
848	/** @} */
849
850	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
851	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc);
852	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
853	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc);
854	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
855	/** @name PGMR3MapPT flags.
856	* @{ */
857	/** The mapping may be unmapped later. The default is permanent mappings. */
858	#define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
859	/** @} */
860	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc);
861	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
862	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
863	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
864	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
865	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
866	VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
867	#if defined(VBOX_WITH_RAW_MODE) \|\| HC_ARCH_BITS == 32 /* (latter for 64-bit guests on 32-bit hosts) */
868	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
869	#endif
870	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
871
872	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind,
873	PFNPGMPHYSHANDLER pfnHandlerR3,
874	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
875	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
876	RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC,
877	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC,
878	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
879	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind,
880	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
881	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
882	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
883	const char *pszDesc,
884	PPGMPHYSHANDLERTYPE phType);
885	#ifdef VBOX_WITH_RAW_MODE
886	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegisterEx(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
887	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
888	PFNPGMVIRTHANDLER pfnHandlerR3,
889	RCPTRTYPE(FNPGMVIRTHANDLER) pfnHandlerRC,
890	RCPTRTYPE(FNPGMRCVIRTPFHANDLER) pfnPfHandlerRC,
891	const char *pszDesc, PPGMVIRTHANDLERTYPE phType);
892	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegister(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
893	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
894	PFNPGMVIRTHANDLER pfnHandlerR3,
895	const char pszHandlerRC, const char pszPfHandlerRC, const char *pszDesc,
896	PPGMVIRTHANDLERTYPE phType);
897	VMMR3_INT_DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PVMCPU pVCpu, PGMVIRTHANDLERTYPE hType, RTGCPTR GCPtr,
898	RTGCPTR GCPtrLast, void pvUserR3, RTRCPTR pvUserRC, const char pszDesc);
899	VMMR3_INT_DECL(int) PGMHandlerVirtualChangeType(PVM pVM, RTGCPTR GCPtr, PGMVIRTHANDLERTYPE hNewType);
900	VMMR3_INT_DECL(int) PGMHandlerVirtualDeregister(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, bool fHypervisor);
901	#endif
902	VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
903
904	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
905	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
906	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
907	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
908	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
909	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
910	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
911	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
912	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
913	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
914	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
915	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
916	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
917	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
918	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
919	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
920	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
921
922	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
923
924	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
925	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
926	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
927	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
928	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
929	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
930	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
931	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
932	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
933	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
934	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
935
936
937	/** @name Page sharing
938	* @{ */
939	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
940	RTGCPTR GCBaseAddr, uint32_t cbModule,
941	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
942	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
943	RTGCPTR GCBaseAddr, uint32_t cbModule);
944	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
945	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
946	/** @} */
947
948	/** @} */
949	#endif /* IN_RING3 */
950
951	RT_C_DECLS_END
952
953	/** @} */
954	#endif
955

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 76399

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