pgm.h@ 104767

Last change on this file since 104767 was 104767, checked in by vboxsync, 6 months ago
VMM/PGM,IOM,PDM: MMIO cleanups. bugref:10687
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_pgm_h
37	#define VBOX_INCLUDED_vmm_pgm_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/types.h>
43	#include <VBox/sup.h>
44	#include <VBox/vmm/vmapi.h>
45	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
46	#include <VBox/vmm/hm_vmx.h>
47	#include <iprt/x86.h>
48	#include <VBox/param.h>
49
50	RT_C_DECLS_BEGIN
51
52	/** @defgroup grp_pgm The Page Monitor / Manager API
53	* @ingroup grp_vmm
54	* @{
55	*/
56
57	/**
58	* FNPGMRELOCATE callback mode.
59	*/
60	typedef enum PGMRELOCATECALL
61	{
62	/** The callback is for checking if the suggested address is suitable. */
63	PGMRELOCATECALL_SUGGEST = 1,
64	/** The callback is for executing the relocation. */
65	PGMRELOCATECALL_RELOCATE
66	} PGMRELOCATECALL;
67
68
69	/**
70	* Callback function which will be called when PGM is trying to find
71	* a new location for the mapping.
72	*
73	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
74	* In 1) the callback should say if it objects to a suggested new location. If it
75	* accepts the new location, it is called again for doing it's relocation.
76	*
77	*
78	* @returns true if the location is ok.
79	* @returns false if another location should be found.
80	* @param pVM The cross context VM structure.
81	* @param GCPtrOld The old virtual address.
82	* @param GCPtrNew The new virtual address.
83	* @param enmMode Used to indicate the callback mode.
84	* @param pvUser User argument.
85	* @remark The return value is no a failure indicator, it's an acceptance
86	* indicator. Relocation can not fail!
87	*/
88	typedef DECLCALLBACKTYPE(bool, FNPGMRELOCATE,(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser));
89	/** Pointer to a relocation callback function. */
90	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
91
92
93	/**
94	* Memory access origin.
95	*/
96	typedef enum PGMACCESSORIGIN
97	{
98	/** Invalid zero value. */
99	PGMACCESSORIGIN_INVALID = 0,
100	/** IEM is access memory. */
101	PGMACCESSORIGIN_IEM,
102	/** HM is access memory. */
103	PGMACCESSORIGIN_HM,
104	/** Some device is access memory. */
105	PGMACCESSORIGIN_DEVICE,
106	/** Someone debugging is access memory. */
107	PGMACCESSORIGIN_DEBUGGER,
108	/** SELM is access memory. */
109	PGMACCESSORIGIN_SELM,
110	/** FTM is access memory. */
111	PGMACCESSORIGIN_FTM,
112	/** REM is access memory. */
113	PGMACCESSORIGIN_REM,
114	/** IOM is access memory. */
115	PGMACCESSORIGIN_IOM,
116	/** End of valid values. */
117	PGMACCESSORIGIN_END,
118	/** Type size hack. */
119	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
120	} PGMACCESSORIGIN;
121
122
123	/**
124	* Physical page access handler kind.
125	*/
126	typedef enum PGMPHYSHANDLERKIND
127	{
128	/** Invalid zero value. */
129	PGMPHYSHANDLERKIND_INVALID = 0,
130	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
131	PGMPHYSHANDLERKIND_MMIO,
132	/** Handler all write access to a physical page range. */
133	PGMPHYSHANDLERKIND_WRITE,
134	/** Handler all access to a physical page range. */
135	PGMPHYSHANDLERKIND_ALL,
136	/** End of the valid values. */
137	PGMPHYSHANDLERKIND_END,
138	/** Type size hack. */
139	PGMPHYSHANDLERKIND_32BIT_HACK = 0x7fffffff
140	} PGMPHYSHANDLERKIND;
141
142	/**
143	* Guest Access type
144	*/
145	typedef enum PGMACCESSTYPE
146	{
147	/** Read access. */
148	PGMACCESSTYPE_READ = 1,
149	/** Write access. */
150	PGMACCESSTYPE_WRITE
151	} PGMACCESSTYPE;
152
153
154	/** @def PGM_ALL_CB_DECL
155	* Macro for declaring a handler callback for all contexts. The handler
156	* callback is static in ring-3, and exported in RC and R0.
157	* @sa PGM_ALL_CB2_DECL.
158	*/
159	#if defined(IN_RC) \|\| defined(IN_RING0)
160	# ifdef __cplusplus
161	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
162	# else
163	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
164	# endif
165	#else
166	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
167	#endif
168
169	/** @def PGM_ALL_CB2_DECL
170	* Macro for declaring a handler callback for all contexts. The handler
171	* callback is hidden in ring-3, and exported in RC and R0.
172	* @sa PGM_ALL_CB2_DECL.
173	*/
174	#if defined(IN_RC) \|\| defined(IN_RING0)
175	# ifdef __cplusplus
176	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
177	# else
178	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
179	# endif
180	#else
181	# define PGM_ALL_CB2_DECL(type) DECL_HIDDEN_CALLBACK(type)
182	#endif
183
184	/** @def PGM_ALL_CB2_PROTO
185	* Macro for declaring a handler callback for all contexts. The handler
186	* callback is hidden in ring-3, and exported in RC and R0.
187	* @param fnType The callback function type.
188	* @sa PGM_ALL_CB2_DECL.
189	*/
190	#if defined(IN_RC) \|\| defined(IN_RING0)
191	# ifdef __cplusplus
192	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
193	# else
194	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
195	# endif
196	#else
197	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
198	#endif
199
200
201	/**
202	* \#PF Handler callback for physical access handler ranges in RC and R0.
203	*
204	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
205	* @param pVM The cross context VM structure.
206	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
207	* @param uErrorCode CPU Error code.
208	* @param pCtx Pointer to the register context for the CPU.
209	* @param pvFault The fault address (cr2).
210	* @param GCPhysFault The GC physical address corresponding to pvFault.
211	* @param uUser User argument (not a pointer).
212	* @thread EMT(pVCpu)
213	*/
214	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx,
215	RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser));
216	/** Pointer to PGM access callback. */
217	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
218
219
220	/**
221	* Access handler callback for physical access handler ranges.
222	*
223	* The handler can not raise any faults, it's mainly for monitoring write access
224	* to certain pages (like MMIO).
225	*
226	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
227	* the only supported informational status code is
228	* VINF_PGM_HANDLER_DO_DEFAULT.
229	* @retval VINF_SUCCESS if the handler have carried out the operation.
230	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
231	* access operation.
232	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
233	*
234	* @param pVM The cross context VM structure.
235	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
236	* @param GCPhys The physical address the guest is writing to.
237	* @param pvPhys The HC mapping of that address.
238	* @param pvBuf What the guest is reading/writing.
239	* @param cbBuf How much it's reading/writing.
240	* @param enmAccessType The access type.
241	* @param enmOrigin The origin of this call.
242	* @param uUser User argument (not a pointer).
243	* @thread EMT(pVCpu)
244	*/
245	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMPHYSHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
246	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
247	PGMACCESSORIGIN enmOrigin, uint64_t uUser));
248	/** Pointer to PGM access callback. */
249	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
250
251
252	/**
253	* Paging mode.
254	*
255	* @note Part of saved state. Change with extreme care.
256	*/
257	typedef enum PGMMODE
258	{
259	/** The usual invalid value. */
260	PGMMODE_INVALID = 0,
261	/** Real mode. */
262	PGMMODE_REAL,
263	/** Protected mode, no paging. */
264	PGMMODE_PROTECTED,
265	/** 32-bit paging. */
266	PGMMODE_32_BIT,
267	/** PAE paging. */
268	PGMMODE_PAE,
269	/** PAE paging with NX enabled. */
270	PGMMODE_PAE_NX,
271	/** 64-bit AMD paging (long mode). */
272	PGMMODE_AMD64,
273	/** 64-bit AMD paging (long mode) with NX enabled. */
274	PGMMODE_AMD64_NX,
275	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
276	PGMMODE_NESTED_32BIT,
277	/** PAE nested paging mode (shadow only; guest physical to host physical). */
278	PGMMODE_NESTED_PAE,
279	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
280	PGMMODE_NESTED_AMD64,
281	/** Extended paging (Intel) mode. */
282	PGMMODE_EPT,
283	/** Special mode used by NEM to indicate no shadow paging necessary. */
284	PGMMODE_NONE,
285	/** The max number of modes */
286	PGMMODE_MAX,
287	/** 32bit hackishness. */
288	PGMMODE_32BIT_HACK = 0x7fffffff
289	} PGMMODE;
290
291	/**
292	* Second level address translation (SLAT) mode.
293	*/
294	typedef enum PGMSLAT
295	{
296	/** The usual invalid value. */
297	PGMSLAT_INVALID = 0,
298	/** No second level translation. */
299	PGMSLAT_DIRECT,
300	/** Intel Extended Page Tables (EPT). */
301	PGMSLAT_EPT,
302	/** AMD-V Nested Paging 32-bit. */
303	PGMSLAT_32BIT,
304	/** AMD-V Nested Paging PAE. */
305	PGMSLAT_PAE,
306	/** AMD-V Nested Paging 64-bit. */
307	PGMSLAT_AMD64,
308	/** 32bit hackishness. */
309	PGMSLAT_32BIT_HACK = 0x7fffffff
310	} PGMSLAT;
311
312
313	/** @name PGMPTWALK::fFailed flags.
314	* These flags indicate the type of a page-walk failure.
315	* @{
316	*/
317	typedef uint32_t PGMWALKFAIL;
318	/** Regular page fault (MBZ since guest Walk code don't set these explicitly). */
319	#define PGM_WALKFAIL_PAGE_FAULT UINT32_C(0)
320	/** EPT violation - Intel. */
321	#define PGM_WALKFAIL_EPT_VIOLATION RT_BIT_32(0)
322	/** EPT violation, convertible to \#VE exception - Intel. */
323	#define PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE RT_BIT_32(1)
324	/** EPT misconfiguration - Intel. */
325	#define PGM_WALKFAIL_EPT_MISCONFIG RT_BIT_32(2)
326
327	/** Mask of all EPT induced page-walk failures - Intel. */
328	#define PGM_WALKFAIL_EPT ( PGM_WALKFAIL_EPT_VIOLATION \
329	\| PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE \
330	\| PGM_WALKFAIL_EPT_MISCONFIG)
331	/** @} */
332
333
334	/** @name PGMPTATTRS - PGM page-table attributes.
335	*
336	* This is VirtualBox's combined page table attributes. It combines regular page
337	* table and Intel EPT attributes. It's 64-bit in size so there's ample room for
338	* bits added in the future to EPT or regular page tables (for e.g. Protection Key).
339	*
340	* The following bits map 1:1 (shifted by PGM_PTATTRS_EPT_SHIFT) to the Intel EPT
341	* attributes as these are unique to EPT and fit within 64-bits despite the shift:
342	* - EPT_R : Read access.
343	* - EPT_W : Write access.
344	* - EPT_X_SUPER : Execute or execute for supervisor-mode linear addr access.
345	* - EPT_MEMTYPE : EPT memory type.
346	* - EPT_IGNORE_PAT: Ignore PAT memory type.
347	* - EPT_X_USER : Execute access for user-mode linear addresses.
348	*
349	* For regular page tables, the R bit is always 1 (same as P bit).
350	* For Intel EPT, the EPT_R and EPT_W bits are copied to R and W bits respectively.
351	*
352	* The following EPT attributes are mapped to the following positions because they
353	* exist in the regular page tables at these positions OR are exclusive to EPT and
354	* have been mapped to arbitrarily chosen positions:
355	* - EPT_A : Accessed (EPT bit 8 maps to bit 5).
356	* - EPT_D : Dirty (EPT bit 9 maps to bit 6).
357	* - EPT_SUPER_SHW_STACK : Supervisor Shadow Stack (EPT bit 60 maps to bit 24).
358	* - EPT_SUPPRESS_VE_XCPT: Suppress \#VE exception (EPT bit 63 maps to bit 25).
359	*
360	* Bits 12, 11:9 and 43 are deliberately kept unused (correspond to bit PS and bits
361	* 11:9 in the regular page-table structures and to bit 11 in the EPT structures
362	* respectively) as bit 12 is the page-size bit and bits 11:9 are reserved for
363	* use by software and we may want to use/preserve them in the future.
364	*
365	* @{ */
366	typedef uint64_t PGMPTATTRS;
367	/** Pointer to a PGMPTATTRS type. */
368	typedef PGMPTATTRS *PPGMPTATTRS;
369
370	/** Read bit (always 1 for regular PT, copy of EPT_R for EPT). */
371	#define PGM_PTATTRS_R_SHIFT 0
372	#define PGM_PTATTRS_R_MASK RT_BIT_64(PGM_PTATTRS_R_SHIFT)
373	/** Write access bit (aka read/write bit for regular PT). */
374	#define PGM_PTATTRS_W_SHIFT 1
375	#define PGM_PTATTRS_W_MASK RT_BIT_64(PGM_PTATTRS_W_SHIFT)
376	/** User-mode access bit. */
377	#define PGM_PTATTRS_US_SHIFT 2
378	#define PGM_PTATTRS_US_MASK RT_BIT_64(PGM_PTATTRS_US_SHIFT)
379	/** Write through cache bit. */
380	#define PGM_PTATTRS_PWT_SHIFT 3
381	#define PGM_PTATTRS_PWT_MASK RT_BIT_64(PGM_PTATTRS_PWT_SHIFT)
382	/** Cache disabled bit. */
383	#define PGM_PTATTRS_PCD_SHIFT 4
384	#define PGM_PTATTRS_PCD_MASK RT_BIT_64(PGM_PTATTRS_PCD_SHIFT)
385	/** Accessed bit. */
386	#define PGM_PTATTRS_A_SHIFT 5
387	#define PGM_PTATTRS_A_MASK RT_BIT_64(PGM_PTATTRS_A_SHIFT)
388	/** Dirty bit. */
389	#define PGM_PTATTRS_D_SHIFT 6
390	#define PGM_PTATTRS_D_MASK RT_BIT_64(PGM_PTATTRS_D_SHIFT)
391	/** The PAT bit. */
392	#define PGM_PTATTRS_PAT_SHIFT 7
393	#define PGM_PTATTRS_PAT_MASK RT_BIT_64(PGM_PTATTRS_PAT_SHIFT)
394	/** The global bit. */
395	#define PGM_PTATTRS_G_SHIFT 8
396	#define PGM_PTATTRS_G_MASK RT_BIT_64(PGM_PTATTRS_G_SHIFT)
397	/** Reserved (bits 12:9) unused. */
398	#define PGM_PTATTRS_RSVD_12_9_SHIFT 9
399	#define PGM_PTATTRS_RSVD_12_9_MASK UINT64_C(0x0000000000001e00)
400	/** Read access bit - EPT only. */
401	#define PGM_PTATTRS_EPT_R_SHIFT 13
402	#define PGM_PTATTRS_EPT_R_MASK RT_BIT_64(PGM_PTATTRS_EPT_R_SHIFT)
403	/** Write access bit - EPT only. */
404	#define PGM_PTATTRS_EPT_W_SHIFT 14
405	#define PGM_PTATTRS_EPT_W_MASK RT_BIT_64(PGM_PTATTRS_EPT_W_SHIFT)
406	/** Execute or execute access for supervisor-mode linear addresses - EPT only. */
407	#define PGM_PTATTRS_EPT_X_SUPER_SHIFT 15
408	#define PGM_PTATTRS_EPT_X_SUPER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_SUPER_SHIFT)
409	/** EPT memory type - EPT only. */
410	#define PGM_PTATTRS_EPT_MEMTYPE_SHIFT 16
411	#define PGM_PTATTRS_EPT_MEMTYPE_MASK UINT64_C(0x0000000000070000)
412	/** Ignore PAT memory type - EPT only. */
413	#define PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT 19
414	#define PGM_PTATTRS_EPT_IGNORE_PAT_MASK RT_BIT_64(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT)
415	/** Leaf paging entry (big or regular) - EPT only. */
416	#define PGM_PTATTRS_EPT_LEAF_SHIFT 20
417	#define PGM_PTATTRS_EPT_LEAF_MASK RT_BIT_64(PGM_PTATTRS_EPT_LEAF_SHIFT)
418	/** Accessed bit - EPT only. */
419	#define PGM_PTATTRS_EPT_A_SHIFT 21
420	#define PGM_PTATTRS_EPT_A_MASK RT_BIT_64(PGM_PTATTRS_EPT_A_SHIFT)
421	/** Dirty bit - EPT only. */
422	#define PGM_PTATTRS_EPT_D_SHIFT 22
423	#define PGM_PTATTRS_EPT_D_MASK RT_BIT_64(PGM_PTATTRS_EPT_D_SHIFT)
424	/** Execute access for user-mode linear addresses - EPT only. */
425	#define PGM_PTATTRS_EPT_X_USER_SHIFT 23
426	#define PGM_PTATTRS_EPT_X_USER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_USER_SHIFT)
427	/** Reserved (bits 29:24) - unused. */
428	#define PGM_PTATTRS_RSVD_29_24_SHIFT 24
429	#define PGM_PTATTRS_RSVD_29_24_MASK UINT64_C(0x000000003f000000)
430	/** Verify Guest Paging - EPT only. */
431	#define PGM_PTATTRS_EPT_VGP_SHIFT 30
432	#define PGM_PTATTRS_EPT_VGP_MASK RT_BIT_64(PGM_PTATTRS_EPT_VGP_SHIFT)
433	/** Paging-write - EPT only. */
434	#define PGM_PTATTRS_EPT_PW_SHIFT 31
435	#define PGM_PTATTRS_EPT_PW_MASK RT_BIT_64(PGM_PTATTRS_EPT_PW_SHIFT)
436	/** Reserved (bit 32) - unused. */
437	#define PGM_PTATTRS_RSVD_32_SHIFT 32
438	#define PGM_PTATTRS_RSVD_32_MASK UINT64_C(0x0000000100000000)
439	/** Supervisor shadow stack - EPT only. */
440	#define PGM_PTATTRS_EPT_SSS_SHIFT 33
441	#define PGM_PTATTRS_EPT_SSS_MASK RT_BIT_64(PGM_PTATTRS_EPT_SSS_SHIFT)
442	/** Sub-page write permission - EPT only. */
443	#define PGM_PTATTRS_EPT_SPP_SHIFT 34
444	#define PGM_PTATTRS_EPT_SPP_MASK RT_BIT_64(PGM_PTATTRS_EPT_SPP_SHIFT)
445	/** Reserved (bit 35) - unused. */
446	#define PGM_PTATTRS_RSVD_35_SHIFT 35
447	#define PGM_PTATTRS_RSVD_35_MASK UINT64_C(0x0000000800000000)
448	/** Suppress \#VE exception - EPT only. */
449	#define PGM_PTATTRS_EPT_SVE_SHIFT 36
450	#define PGM_PTATTRS_EPT_SVE_MASK RT_BIT_64(PGM_PTATTRS_EPT_SVE_SHIFT)
451	/** Reserved (bits 62:37) - unused. */
452	#define PGM_PTATTRS_RSVD_62_37_SHIFT 37
453	#define PGM_PTATTRS_RSVD_62_37_MASK UINT64_C(0x7fffffe000000000)
454	/** No-execute bit. */
455	#define PGM_PTATTRS_NX_SHIFT 63
456	#define PGM_PTATTRS_NX_MASK RT_BIT_64(PGM_PTATTRS_NX_SHIFT)
457
458	RT_BF_ASSERT_COMPILE_CHECKS(PGM_PTATTRS_, UINT64_C(0), UINT64_MAX,
459	(R, W, US, PWT, PCD, A, D, PAT, G, RSVD_12_9, EPT_R, EPT_W, EPT_X_SUPER, EPT_MEMTYPE, EPT_IGNORE_PAT,
460	EPT_LEAF, EPT_A, EPT_D, EPT_X_USER, RSVD_29_24, EPT_VGP, EPT_PW, RSVD_32, EPT_SSS, EPT_SPP,
461	RSVD_35, EPT_SVE, RSVD_62_37, NX));
462
463	/** The bit position where the EPT specific attributes begin. */
464	#define PGM_PTATTRS_EPT_SHIFT PGM_PTATTRS_EPT_R_SHIFT
465	/** The mask of EPT bits (bits 36:ATTR_SHIFT). In the future we might choose to
466	* use higher unused bits for something else, in that case adjust this mask. */
467	#define PGM_PTATTRS_EPT_MASK UINT64_C(0x0000001fffffe000)
468
469	/** The mask of all PGM page attribute bits for regular page-tables. */
470	#define PGM_PTATTRS_PT_VALID_MASK ( PGM_PTATTRS_R_MASK \
471	\| PGM_PTATTRS_W_MASK \
472	\| PGM_PTATTRS_US_MASK \
473	\| PGM_PTATTRS_PWT_MASK \
474	\| PGM_PTATTRS_PCD_MASK \
475	\| PGM_PTATTRS_A_MASK \
476	\| PGM_PTATTRS_D_MASK \
477	\| PGM_PTATTRS_PAT_MASK \
478	\| PGM_PTATTRS_G_MASK \
479	\| PGM_PTATTRS_NX_MASK)
480
481	/** The mask of all PGM page attribute bits for EPT. */
482	#define PGM_PTATTRS_EPT_VALID_MASK ( PGM_PTATTRS_EPT_R_MASK \
483	\| PGM_PTATTRS_EPT_W_MASK \
484	\| PGM_PTATTRS_EPT_X_SUPER_MASK \
485	\| PGM_PTATTRS_EPT_MEMTYPE_MASK \
486	\| PGM_PTATTRS_EPT_IGNORE_PAT_MASK \
487	\| PGM_PTATTRS_EPT_LEAF_MASK \
488	\| PGM_PTATTRS_EPT_A_MASK \
489	\| PGM_PTATTRS_EPT_D_MASK \
490	\| PGM_PTATTRS_EPT_X_USER_MASK \
491	\| PGM_PTATTRS_EPT_VGP_MASK \
492	\| PGM_PTATTRS_EPT_PW_MASK \
493	\| PGM_PTATTRS_EPT_SSS_MASK \
494	\| PGM_PTATTRS_EPT_SPP_MASK \
495	\| PGM_PTATTRS_EPT_SVE_MASK)
496
497	/* The mask of all PGM page attribute bits (combined). */
498	#define PGM_PTATTRS_VALID_MASK (PGM_PTATTRS_PT_VALID_MASK \| PGM_PTATTRS_EPT_VALID_MASK)
499
500	/* Verify bits match the regular PT bits. */
501	AssertCompile(PGM_PTATTRS_W_SHIFT == X86_PTE_BIT_RW);
502	AssertCompile(PGM_PTATTRS_US_SHIFT == X86_PTE_BIT_US);
503	AssertCompile(PGM_PTATTRS_PWT_SHIFT == X86_PTE_BIT_PWT);
504	AssertCompile(PGM_PTATTRS_PCD_SHIFT == X86_PTE_BIT_PCD);
505	AssertCompile(PGM_PTATTRS_A_SHIFT == X86_PTE_BIT_A);
506	AssertCompile(PGM_PTATTRS_D_SHIFT == X86_PTE_BIT_D);
507	AssertCompile(PGM_PTATTRS_PAT_SHIFT == X86_PTE_BIT_PAT);
508	AssertCompile(PGM_PTATTRS_G_SHIFT == X86_PTE_BIT_G);
509	AssertCompile(PGM_PTATTRS_W_MASK == X86_PTE_RW);
510	AssertCompile(PGM_PTATTRS_US_MASK == X86_PTE_US);
511	AssertCompile(PGM_PTATTRS_PWT_MASK == X86_PTE_PWT);
512	AssertCompile(PGM_PTATTRS_PCD_MASK == X86_PTE_PCD);
513	AssertCompile(PGM_PTATTRS_A_MASK == X86_PTE_A);
514	AssertCompile(PGM_PTATTRS_D_MASK == X86_PTE_D);
515	AssertCompile(PGM_PTATTRS_PAT_MASK == X86_PTE_PAT);
516	AssertCompile(PGM_PTATTRS_G_MASK == X86_PTE_G);
517	AssertCompile(PGM_PTATTRS_NX_MASK == X86_PTE_PAE_NX);
518
519	/* Verify those EPT bits that must map 1:1 (after shifting). */
520	AssertCompile(PGM_PTATTRS_EPT_R_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_READ);
521	AssertCompile(PGM_PTATTRS_EPT_W_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_WRITE);
522	AssertCompile(PGM_PTATTRS_EPT_X_SUPER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_EXECUTE);
523	AssertCompile(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_IGNORE_PAT);
524	AssertCompile(PGM_PTATTRS_EPT_X_USER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_USER_EXECUTE);
525	/** @} */
526
527
528	/**
529	* Page table walk information.
530	*
531	* This provides extensive information regarding page faults (or EPT
532	* violations/misconfigurations) while traversing page tables.
533	*/
534	typedef struct PGMPTWALK
535	{
536	/** The linear address that is being resolved (input). */
537	RTGCPTR GCPtr;
538
539	/** The second-level physical address (input/output).
540	* @remarks only valid if fIsSlat is set. */
541	RTGCPHYS GCPhysNested;
542
543	/** The physical address that is the result of the walk (output). */
544	RTGCPHYS GCPhys;
545
546	/** Set if the walk succeeded. */
547	bool fSucceeded;
548	/** Whether this is a second-level address translation. */
549	bool fIsSlat;
550	/** Whether the linear address (GCPtr) caused the second-level
551	* address translation. */
552	bool fIsLinearAddrValid;
553	/** The level problem arrised at.
554	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
555	* level 8. This is 0 on success. */
556	uint8_t uLevel;
557	/** Set if the page isn't present. */
558	bool fNotPresent;
559	/** Encountered a bad physical address. */
560	bool fBadPhysAddr;
561	/** Set if there was reserved bit violations. */
562	bool fRsvdError;
563	/** Set if it involves a big page (2/4 MB). */
564	bool fBigPage;
565	/** Set if it involves a gigantic page (1 GB). */
566	bool fGigantPage;
567	bool afPadding[3];
568	/** Page-walk failure type, PGM_WALKFAIL_XXX. */
569	PGMWALKFAIL fFailed;
570
571	/** The effective page-table attributes, PGM_PTATTRS_XXX. */
572	PGMPTATTRS fEffective;
573	} PGMPTWALK;
574	/** Pointer to page walk information. */
575	typedef PGMPTWALK *PPGMPTWALK;
576	/** Pointer to const page walk information. */
577	typedef PGMPTWALK const *PCPGMPTWALK;
578
579
580	/** Macro for checking if the guest is using paging.
581	* @param enmMode PGMMODE_*.
582	* @remark ASSUMES certain order of the PGMMODE_* values.
583	*/
584	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
585
586	/** Macro for checking if it's one of the long mode modes.
587	* @param enmMode PGMMODE_*.
588	*/
589	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
590
591	/** Macro for checking if it's one of the AMD64 nested modes.
592	* @param enmMode PGMMODE_*.
593	*/
594	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
595	\|\| (enmMode) == PGMMODE_NESTED_PAE \
596	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
597
598	/** Macro for checking if it's one of the PAE modes.
599	* @param enmMode PGMMODE_*.
600	*/
601	#define PGMMODE_IS_PAE(enmMode) ( (enmMode) == PGMMODE_PAE \
602	\|\| (enmMode) == PGMMODE_PAE_NX)
603
604	/**
605	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
606	*
607	* @returns boolean.
608	* @param enmProt The PGMROMPROT value, must be valid.
609	*/
610	#define PGMROMPROT_IS_ROM(enmProt) \
611	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
612	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
613
614
615	VMMDECL(bool) PGMIsLockOwner(PVMCC pVM);
616
617	VMMDECL(int) PGMRegisterStringFormatTypes(void);
618	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
619	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
620	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault);
621	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
622	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCPUCC pVCpu, RTGCPTR pvFault);
623	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
624	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
625	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
626	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
627	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
628	* PGMShwMakePageNotPresent
629	* @{ */
630	/** The call is from an access handler for dealing with the a faulting write
631	* operation. The virtual address is within the same page. */
632	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
633	/** The page is an MMIO2. */
634	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
635	/** @}*/
636	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk);
637	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
638	VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
639	VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
640	VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3);
641
642	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
643	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal);
644	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
645	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3);
646	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer, bool fForce);
647	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode, bool fForce);
648	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
649	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
650	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
651	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
652	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
653	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
654	VMM_INT_DECL(const char *) PGMGetSlatModeName(PGMSLAT enmSlatMode);
655	#endif
656	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
657	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
658	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
659	VMM_INT_DECL(void) PGMSetGuestEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr);
660
661	/** PGM physical access handler type registration handle (heap offset, valid
662	* cross contexts without needing fixing up). Callbacks and handler type is
663	* associated with this and it is shared by all handler registrations. */
664	typedef uint64_t PGMPHYSHANDLERTYPE;
665	/** Pointer to a PGM physical handler type registration handle. */
666	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
667	/** NIL value for PGM physical access handler type handle. */
668	#define NIL_PGMPHYSHANDLERTYPE UINT64_MAX
669	VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
670	uint64_t uUser, R3PTRTYPE(const char *) pszDesc);
671	VMMDECL(int) PGMHandlerPhysicalRegisterVmxApicAccessPage(PVMCC pVM, RTGCPHYS GCPhys, PGMPHYSHANDLERTYPE hType);
672	VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
673	VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
674	VMMDECL(int) PGMHandlerPhysicalChangeUserArg(PVMCC pVM, RTGCPHYS GCPhys, uint64_t uUser);
675	VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
676	VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
677	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
678	VMMDECL(int) PGMHandlerPhysicalPageAliasMmio2(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage,
679	PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS offMMio2PageRemap);
680	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
681	VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
682	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
683
684	/** @name PGMPHYSHANDLER_F_XXX - flags for PGMR3HandlerPhysicalTypeRegister and PGMR0HandlerPhysicalTypeRegister
685	* @{ */
686	/** Whether to hold the PGM lock while calling the handler or not.
687	* Mainly an optimization for PGM callers. */
688	#define PGMPHYSHANDLER_F_KEEP_PGM_LOCK RT_BIT_32(0)
689	/** The uUser value is a ring-0 device instance index that needs translating
690	* into a PDMDEVINS pointer before calling the handler. This is a hack to make
691	* it possible to use access handlers in devices. */
692	#define PGMPHYSHANDLER_F_R0_DEVINS_IDX RT_BIT_32(1)
693	/** Don't apply the access handler to VT-x and AMD-V. Only works with full pages.
694	* This is a trick for the VT-x APIC access page in nested VT-x setups. */
695	#define PGMPHYSHANDLER_F_NOT_IN_HM RT_BIT_32(2)
696	/** Mask of valid bits. */
697	#define PGMPHYSHANDLER_F_VALID_MASK UINT32_C(7)
698	/** @} */
699
700
701	/**
702	* Page type.
703	*
704	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
705	* @remarks This is used in the saved state, so changes to it requires bumping
706	* the saved state version.
707	* @todo So, convert to \#defines!
708	*/
709	typedef enum PGMPAGETYPE
710	{
711	/** The usual invalid zero entry. */
712	PGMPAGETYPE_INVALID = 0,
713	/** RAM page. (RWX) */
714	PGMPAGETYPE_RAM,
715	/** MMIO2 page. (RWX) */
716	PGMPAGETYPE_MMIO2,
717	/** MMIO2 page aliased over an MMIO page. (RWX)
718	* See PGMHandlerPhysicalPageAlias(). */
719	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
720	/** Special page aliased over an MMIO page. (RWX)
721	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
722	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
723	* the shadow paging code. */
724	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
725	/** Shadowed ROM. (RWX) */
726	PGMPAGETYPE_ROM_SHADOW,
727	/** ROM page. (R-X) */
728	PGMPAGETYPE_ROM,
729	/** MMIO page. (---) */
730	PGMPAGETYPE_MMIO,
731	/** End of valid entries. */
732	PGMPAGETYPE_END
733	} PGMPAGETYPE;
734	AssertCompile(PGMPAGETYPE_END == 8);
735
736	/** @name PGM page type predicates.
737	* @{ */
738	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
739	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
740	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
741	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
742	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
743	/** @} */
744
745
746	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
747
748	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
749	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
750	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
751	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
752	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
753	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
754
755	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
756	VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
757	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
758	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
759	VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
760	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
761
762	/** @def PGM_PHYS_RW_IS_SUCCESS
763	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
764	* PGMPhysWriteGCPtr call completed the given task.
765	*
766	* @returns true if completed, false if not.
767	* @param a_rcStrict The status code.
768	* @sa IOM_SUCCESS
769	*/
770	#ifdef IN_RING3
771	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
772	( (a_rcStrict) == VINF_SUCCESS \
773	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
774	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
775	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
776	)
777	#elif defined(IN_RING0)
778	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
779	( (a_rcStrict) == VINF_SUCCESS \
780	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
781	\|\| (a_rcStrict) == VINF_EM_OFF \
782	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
783	\|\| (a_rcStrict) == VINF_EM_RESET \
784	\|\| (a_rcStrict) == VINF_EM_HALT \
785	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
786	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
787	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
788	)
789	#elif defined(IN_RC)
790	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
791	( (a_rcStrict) == VINF_SUCCESS \
792	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
793	\|\| (a_rcStrict) == VINF_EM_OFF \
794	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
795	\|\| (a_rcStrict) == VINF_EM_RESET \
796	\|\| (a_rcStrict) == VINF_EM_HALT \
797	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
798	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
799	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
800	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
801	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
802	)
803	#endif
804	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
805	* Updates the return code with a new result.
806	*
807	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
808	*
809	* @param a_rcStrict The current return code, to be updated.
810	* @param a_rcStrict2 The new return code to merge in.
811	*/
812	#ifdef IN_RING3
813	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
814	do { \
815	Assert(rcStrict == VINF_SUCCESS); \
816	Assert(rcStrict2 == VINF_SUCCESS); \
817	} while (0)
818	#elif defined(IN_RING0)
819	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
820	do { \
821	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
822	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
823	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
824	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
825	{ /* likely */ } \
826	else if ( (a_rcStrict) == VINF_SUCCESS \
827	\|\| (a_rcStrict) > (a_rcStrict2)) \
828	(a_rcStrict) = (a_rcStrict2); \
829	} while (0)
830	#elif defined(IN_RC)
831	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
832	do { \
833	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
834	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
835	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
836	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
837	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
838	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
839	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
840	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
841	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
842	{ /* likely */ } \
843	else if ((a_rcStrict) == VINF_SUCCESS) \
844	(a_rcStrict) = (a_rcStrict2); \
845	else if ( ( (a_rcStrict) > (a_rcStrict2) \
846	&& ( (a_rcStrict2) <= VINF_EM_RESET \
847	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
848	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
849	&& (a_rcStrict) > VINF_EM_RESET) ) \
850	(a_rcStrict) = (a_rcStrict2); \
851	} while (0)
852	#endif
853
854	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
855	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
856	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
857	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
858
859	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
860	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
861	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
862	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
863	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
864
865	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
866	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
867	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
868	#if defined(IN_RC)
869	R3PTRTYPE(uint8_t ) ppb,
870	#else
871	R3R0PTRTYPE(uint8_t ) ppb,
872	#endif
873	uint64_t *pfTlb);
874	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
875	* @{ */
876	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
877	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
878	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
879	#define PGMIEMGCPHYS2PTR_F_UNASSIGNED RT_BIT_32(8) /*< Unassgined memory (IEMTLBE_F_PG_UNASSIGNED). /
880	#define PGMIEMGCPHYS2PTR_F_CODE_PAGE RT_BIT_32(9) /*< Write monitored IEM code page (IEMTLBE_F_PG_CODE_PAGE). /
881	/** @} */
882
883	/** Information returned by PGMPhysNemQueryPageInfo. */
884	typedef struct PGMPHYSNEMPAGEINFO
885	{
886	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
887	RTHCPHYS HCPhys;
888	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
889	uint32_t fNemProt : 8;
890	/** The NEM state associated with the PAGE. */
891	uint32_t u2NemState : 2;
892	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
893	uint32_t u2OldNemState : 2;
894	/** Set if the page has handler. */
895	uint32_t fHasHandlers : 1;
896	/** Set if is the zero page backing it. */
897	uint32_t fZeroPage : 1;
898	/** Set if the page has handler. */
899	PGMPAGETYPE enmType;
900	} PGMPHYSNEMPAGEINFO;
901	/** Pointer to page information for NEM. */
902	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
903	/**
904	* Callback for checking that the page is in sync while under the PGM lock.
905	*
906	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
907	* in-sync between PGM and the native hypervisor API in an atomic fashion.
908	*
909	* @returns VBox status code.
910	* @param pVM The cross context VM structure.
911	* @param pVCpu The cross context per virtual CPU structure. Optional,
912	* see PGMPhysNemQueryPageInfo.
913	* @param GCPhys The guest physical address (not A20 masked).
914	* @param pInfo The page info structure. This function updates the
915	* u2NemState memory and the caller will update the PGMPAGE
916	* copy accordingly.
917	* @param pvUser Callback user argument.
918	*/
919	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMCHECKPAGE,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser));
920	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
921	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
922
923	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
924	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
925
926	/**
927	* Callback for use with PGMPhysNemEnumPagesByState.
928	* @returns VBox status code.
929	* Failure status will stop enumeration immediately and return.
930	* @param pVM The cross context VM structure.
931	* @param pVCpu The cross context per virtual CPU structure. Optional,
932	* see PGMPhysNemEnumPagesByState.
933	* @param GCPhys The guest physical address (not A20 masked).
934	* @param pu2NemState Pointer to variable with the NEM state. This can be
935	* update.
936	* @param pvUser The user argument.
937	*/
938	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMENUMCALLBACK,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
939	uint8_t pu2NemState, void pvUser));
940	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
941	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
942	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
943	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
944
945
946	#ifdef VBOX_STRICT
947	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVMCC pVM);
948	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
949	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
950	#endif /* VBOX_STRICT */
951
952	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
953
954	/**
955	* Query large page usage state
956	*
957	* @returns 0 - disabled, 1 - enabled
958	* @param pVM The cross context VM structure.
959	*/
960	#define PGMIsUsingLargePages(pVM) ((pVM)->pgm.s.fUseLargePages)
961
962
963	#ifdef IN_RING0
964	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
965	* @{
966	*/
967	VMMR0_INT_DECL(int) PGMR0InitPerVMData(PGVM pGVM, RTR0MEMOBJ hMemObj);
968	VMMR0_INT_DECL(int) PGMR0InitVM(PGVM pGVM);
969	VMMR0_INT_DECL(void) PGMR0DoneInitVM(PGVM pGVM);
970	VMMR0_INT_DECL(void) PGMR0CleanupVM(PGVM pGVM);
971	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
972	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
973	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
974	VMMR0_INT_DECL(int) PGMR0PhysMMIO2MapKernel(PGVM pGVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
975	size_t offSub, size_t cbSub, void **ppvMapping);
976	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
977	VMMR0_INT_DECL(int) PGMR0PhysHandlerInitReqHandler(PGVM pGVM, uint32_t cEntries);
978	VMMR0_INT_DECL(int) PGMR0HandlerPhysicalTypeSetUpContext(PGVM pGVM, PGMPHYSHANDLERKIND enmKind, uint32_t fFlags,
979	PFNPGMPHYSHANDLER pfnHandler, PFNPGMRZPHYSPFHANDLER pfnPfHandler,
980	const char *pszDesc, PGMPHYSHANDLERTYPE hType);
981
982	VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule,
983	PCRTGCPTR64 paRegionsGCPtrs);
984	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
985	PCPUMCTX pCtx, RTGCPHYS pvFault);
986	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
987	PCPUMCTX pCtx, RTGCPHYS GCPhysFault, uint32_t uErr);
988	VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu);
989
990	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
991	VMMR0DECL(VBOXSTRICTRC) PGMR0NestedTrap0eHandlerNestedPaging(PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
992	PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
993	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk);
994	# endif
995	/** @} */
996	#endif /* IN_RING0 */
997
998
999
1000	#ifdef IN_RING3
1001	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
1002	* @{
1003	*/
1004	VMMR3_INT_DECL(void) PGMR3EnableNemMode(PVM pVM);
1005	VMMR3_INT_DECL(bool) PGMR3IsNemModeEnabled(PVM pVM);
1006	VMMR3DECL(int) PGMR3Init(PVM pVM);
1007	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
1008	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
1009	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
1010	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1011	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
1012	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
1013	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
1014	VMMR3DECL(int) PGMR3Term(PVM pVM);
1015
1016	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
1017	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
1018	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
1019	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
1020	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1021	const char *ppszDesc, bool pfIsMmio);
1022	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
1023	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
1024
1025	VMMR3_INT_DECL(int) PGMR3PhysMmioRegister(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
1026	uint64_t uUser, const char *pszDesc);
1027	VMMR3_INT_DECL(int) PGMR3PhysMmioDeregister(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb);
1028
1029	/** @name PGMPHYS_MMIO2_FLAGS_XXX - MMIO2 registration flags.
1030	* @see PGMR3PhysMmio2Register, PDMDevHlpMmio2Create
1031	* @{ */
1032	/** Track dirty pages.
1033	* @see PGMR3PhysMmio2QueryAndResetDirtyBitmap(), PGMR3PhysMmio2ControlDirtyPageTracking(). */
1034	#define PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES RT_BIT_32(0)
1035	/** Valid flags. */
1036	#define PGMPHYS_MMIO2_FLAGS_VALID_MASK UINT32_C(0x00000001)
1037	/** @} */
1038
1039	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
1040	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion);
1041	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1042	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
1043	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
1044	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion);
1045	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1046	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1047	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion);
1048	VMMR3_INT_DECL(int) PGMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
1049	void *pvBitmap, size_t cbBitmap);
1050	VMMR3_INT_DECL(int) PGMR3PhysMmio2ControlDirtyPageTracking(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled);
1051
1052	/** @name PGMPHYS_ROM_FLAGS_XXX - ROM registration flags.
1053	* @see PGMR3PhysRegisterRom, PDMDevHlpROMRegister
1054	* @{ */
1055	/** Inidicates that ROM shadowing should be enabled. */
1056	#define PGMPHYS_ROM_FLAGS_SHADOWED UINT8_C(0x01)
1057	/** Indicates that what pvBinary points to won't go away
1058	* and can be used for strictness checks. */
1059	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY UINT8_C(0x02)
1060	/** Indicates that the ROM is allowed to be missing from saved state.
1061	* @note This is a hack for EFI, see @bugref{6940} */
1062	#define PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE UINT8_C(0x04)
1063	/** Valid flags. */
1064	#define PGMPHYS_ROM_FLAGS_VALID_MASK UINT8_C(0x07)
1065	/** @} */
1066
1067	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
1068	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc);
1069	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
1070	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
1071
1072	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, uint32_t fFlags,
1073	PFNPGMPHYSHANDLER pfnHandlerR3, const char *pszDesc,
1074	PPGMPHYSHANDLERTYPE phType);
1075
1076	VMMR3_INT_DECL(int) PGMR3PoolGrow(PVM pVM, PVMCPU pVCpu);
1077
1078	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
1079	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1080	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1081	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1082	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1083	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
1084	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
1085	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
1086	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
1087	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
1088	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
1089	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
1090	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
1091	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1092	void **papvPages, PPGMPAGEMAPLOCK paLocks);
1093	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1094	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
1095	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
1096	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
1097
1098	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
1099
1100	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
1101	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
1102	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
1103	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1104	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1105	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1106	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1107	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
1108	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
1109	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1110	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1111
1112
1113	/** @name Page sharing
1114	* @{ */
1115	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
1116	RTGCPTR GCBaseAddr, uint32_t cbModule,
1117	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
1118	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
1119	RTGCPTR GCBaseAddr, uint32_t cbModule);
1120	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
1121	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
1122	/** @} */
1123
1124	/** @} */
1125	#endif /* IN_RING3 */
1126
1127	RT_C_DECLS_END
1128
1129	/** @} */
1130	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
1131

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 104767

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